1 //
2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2013 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // 64 bit registers used excluding r19.
638 // Used to hold the TOC to avoid collisions with expanded DynamicCall
639 // which uses r19 as inline cache internally and expanded LeafCall which uses
640 // r2, r11 and r12 internally.
641 reg_class bits64_constant_table_base(
642 /*R0_H, R0*/ // R0
643 /*R1_H, R1*/ // SP
644 /*R2_H, R2*/ // TOC
645 R3_H, R3,
646 R4_H, R4,
647 R5_H, R5,
648 R6_H, R6,
649 R7_H, R7,
650 R8_H, R8,
651 R9_H, R9,
652 R10_H, R10,
653 /*R11_H, R11*/
654 /*R12_H, R12*/
655 /*R13_H, R13*/ // system thread id
656 R14_H, R14,
657 R15_H, R15,
658 /*R16_H, R16*/ // R16_thread
659 R17_H, R17,
660 R18_H, R18,
661 /*R19_H, R19*/
662 R20_H, R20,
663 R21_H, R21,
664 R22_H, R22,
665 R23_H, R23,
666 R24_H, R24,
667 R25_H, R25,
668 R26_H, R26,
669 R27_H, R27,
670 R28_H, R28,
671 /*R29_H, R29*/
672 /*R30_H, R30*/
673 R31_H, R31
674 );
675
676 // 64 bit registers that can only be read i.e. these registers can
677 // only be src of all instructions.
678 reg_class bits64_reg_ro(
679 /*R0_H, R0*/ // R0
680 R1_H, R1,
681 R2_H, R2, // TOC
682 R3_H, R3,
683 R4_H, R4,
684 R5_H, R5,
685 R6_H, R6,
686 R7_H, R7,
687 R8_H, R8,
688 R9_H, R9,
689 R10_H, R10,
690 R11_H, R11,
691 R12_H, R12,
692 /*R13_H, R13*/ // system thread id
693 R14_H, R14,
694 R15_H, R15,
695 R16_H, R16, // R16_thread
696 R17_H, R17,
697 R18_H, R18,
698 R19_H, R19,
699 R20_H, R20,
700 R21_H, R21,
701 R22_H, R22,
702 R23_H, R23,
703 R24_H, R24,
704 R25_H, R25,
705 R26_H, R26,
706 R27_H, R27,
707 R28_H, R28,
708 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
709 /*R30_H, R30,*/
710 R31_H, R31
711 );
712
713 // Complement-required-in-pipeline operands.
714 reg_class bits64_reg_ro_not_complement (
715 /*R0_H, R0*/ // R0
716 R1_H, R1, // SP
717 R2_H, R2, // TOC
718 R3_H, R3,
719 R4_H, R4,
720 R5_H, R5,
721 R6_H, R6,
722 R7_H, R7,
723 R8_H, R8,
724 R9_H, R9,
725 R10_H, R10,
726 R11_H, R11,
727 R12_H, R12,
728 /*R13_H, R13*/ // system thread id
729 R14_H, R14,
730 R15_H, R15,
731 R16_H, R16, // R16_thread
732 R17_H, R17,
733 R18_H, R18,
734 R19_H, R19,
735 R20_H, R20,
736 R21_H, R21,
737 R22_H, R22,
738 /*R23_H, R23,
739 R24_H, R24,
740 R25_H, R25,
741 R26_H, R26,
742 R27_H, R27,
743 R28_H, R28,*/
744 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
745 /*R30_H, R30,*/
746 R31_H, R31
747 );
748
749 // Complement-required-in-pipeline operands.
750 // This register mask is used for the trap instructions that implement
751 // the null checks on AIX. The trap instruction first computes the
752 // complement of the value it shall trap on. Because of this, the
753 // instruction can not be scheduled in the same cycle as an other
754 // instruction reading the normal value of the same register. So we
755 // force the value to check into 'bits64_reg_ro_not_complement'
756 // and then copy it to 'bits64_reg_ro_complement' for the trap.
757 reg_class bits64_reg_ro_complement (
758 R23_H, R23,
759 R24_H, R24,
760 R25_H, R25,
761 R26_H, R26,
762 R27_H, R27,
763 R28_H, R28
764 );
765
766
767 // ----------------------------
768 // Special Class for Condition Code Flags Register
769
770 reg_class int_flags(
771 /*CCR0*/ // scratch
772 /*CCR1*/ // scratch
773 /*CCR2*/ // nv!
774 /*CCR3*/ // nv!
775 /*CCR4*/ // nv!
776 CCR5,
777 CCR6,
778 CCR7
779 );
780
781 reg_class int_flags_CR0(CCR0);
782 reg_class int_flags_CR1(CCR1);
783 reg_class int_flags_CR6(CCR6);
784 reg_class ctr_reg(SR_CTR);
785
786 // ----------------------------
787 // Float Register Classes
788 // ----------------------------
789
790 reg_class flt_reg(
791 /*F0*/ // scratch
792 F1,
793 F2,
794 F3,
795 F4,
796 F5,
797 F6,
798 F7,
799 F8,
800 F9,
801 F10,
802 F11,
803 F12,
804 F13,
805 F14, // nv!
806 F15, // nv!
807 F16, // nv!
808 F17, // nv!
809 F18, // nv!
810 F19, // nv!
811 F20, // nv!
812 F21, // nv!
813 F22, // nv!
814 F23, // nv!
815 F24, // nv!
816 F25, // nv!
817 F26, // nv!
818 F27, // nv!
819 F28, // nv!
820 F29, // nv!
821 F30, // nv!
822 F31 // nv!
823 );
824
825 // Double precision float registers have virtual `high halves' that
826 // are needed by the allocator.
827 reg_class dbl_reg(
828 /*F0, F0_H*/ // scratch
829 F1, F1_H,
830 F2, F2_H,
831 F3, F3_H,
832 F4, F4_H,
833 F5, F5_H,
834 F6, F6_H,
835 F7, F7_H,
836 F8, F8_H,
837 F9, F9_H,
838 F10, F10_H,
839 F11, F11_H,
840 F12, F12_H,
841 F13, F13_H,
842 F14, F14_H, // nv!
843 F15, F15_H, // nv!
844 F16, F16_H, // nv!
845 F17, F17_H, // nv!
846 F18, F18_H, // nv!
847 F19, F19_H, // nv!
848 F20, F20_H, // nv!
849 F21, F21_H, // nv!
850 F22, F22_H, // nv!
851 F23, F23_H, // nv!
852 F24, F24_H, // nv!
853 F25, F25_H, // nv!
854 F26, F26_H, // nv!
855 F27, F27_H, // nv!
856 F28, F28_H, // nv!
857 F29, F29_H, // nv!
858 F30, F30_H, // nv!
859 F31, F31_H // nv!
860 );
861
862 %}
863
864 //----------DEFINITION BLOCK---------------------------------------------------
865 // Define name --> value mappings to inform the ADLC of an integer valued name
866 // Current support includes integer values in the range [0, 0x7FFFFFFF]
867 // Format:
868 // int_def <name> ( <int_value>, <expression>);
869 // Generated Code in ad_<arch>.hpp
870 // #define <name> (<expression>)
871 // // value == <int_value>
872 // Generated code in ad_<arch>.cpp adlc_verification()
873 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
874 //
875 definitions %{
876 // The default cost (of an ALU instruction).
877 int_def DEFAULT_COST_LOW ( 30, 30);
878 int_def DEFAULT_COST ( 100, 100);
879 int_def HUGE_COST (1000000, 1000000);
880
881 // Memory refs
882 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
883 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
884
885 // Branches are even more expensive.
886 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
887 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
888 %}
889
890
891 //----------SOURCE BLOCK-------------------------------------------------------
892 // This is a block of C++ code which provides values, functions, and
893 // definitions necessary in the rest of the architecture description.
894 source_hpp %{
895 // Returns true if Node n is followed by a MemBar node that
896 // will do an acquire. If so, this node must not do the acquire
897 // operation.
898 bool followed_by_acquire(const Node *n);
899 %}
900
901 source %{
902
903 // Optimize load-acquire.
904 //
905 // Check if acquire is unnecessary due to following operation that does
906 // acquire anyways.
907 // Walk the pattern:
908 //
909 // n: Load.acq
910 // |
911 // MemBarAcquire
912 // | |
913 // Proj(ctrl) Proj(mem)
914 // | |
915 // MemBarRelease/Volatile
916 //
917 bool followed_by_acquire(const Node *load) {
918 assert(load->is_Load(), "So far implemented only for loads.");
919
920 // Find MemBarAcquire.
921 const Node *mba = NULL;
922 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
923 const Node *out = load->fast_out(i);
924 if (out->Opcode() == Op_MemBarAcquire) {
925 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
926 mba = out;
927 break;
928 }
929 }
930 if (!mba) return false;
931
932 // Find following MemBar node.
933 //
934 // The following node must be reachable by control AND memory
935 // edge to assure no other operations are in between the two nodes.
936 //
937 // So first get the Proj node, mem_proj, to use it to iterate forward.
938 Node *mem_proj = NULL;
939 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
940 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
941 assert(mem_proj->is_Proj(), "only projections here");
942 ProjNode *proj = mem_proj->as_Proj();
943 if (proj->_con == TypeFunc::Memory &&
944 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
945 break;
946 }
947 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
948
949 // Search MemBar behind Proj. If there are other memory operations
950 // behind the Proj we lost.
951 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
952 Node *x = mem_proj->fast_out(j);
953 // Proj might have an edge to a store or load node which precedes the membar.
954 if (x->is_Mem()) return false;
955
956 // On PPC64 release and volatile are implemented by an instruction
957 // that also has acquire semantics. I.e. there is no need for an
958 // acquire before these.
959 int xop = x->Opcode();
960 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
961 // Make sure we're not missing Call/Phi/MergeMem by checking
962 // control edges. The control edge must directly lead back
963 // to the MemBarAcquire
964 Node *ctrl_proj = x->in(0);
965 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
966 return true;
967 }
968 }
969 }
970
971 return false;
972 }
973
974 #define __ _masm.
975
976 // Tertiary op of a LoadP or StoreP encoding.
977 #define REGP_OP true
978
979 // ****************************************************************************
980
981 // REQUIRED FUNCTIONALITY
982
983 // !!!!! Special hack to get all type of calls to specify the byte offset
984 // from the start of the call to the point where the return address
985 // will point.
986
987 // PPC port: Removed use of lazy constant construct.
988
989 int MachCallStaticJavaNode::ret_addr_offset() {
990 // It's only a single branch-and-link instruction.
991 return 4;
992 }
993
994 int MachCallDynamicJavaNode::ret_addr_offset() {
995 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
996 // postalloc expanded calls if we use inline caches and do not update method data.
997 if (UseInlineCaches)
998 return 4;
999
1000 int vtable_index = this->_vtable_index;
1001 if (vtable_index < 0) {
1002 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1003 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1004 return 12;
1005 } else {
1006 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1007 return 24;
1008 }
1009 }
1010
1011 int MachCallRuntimeNode::ret_addr_offset() {
1012 return 40;
1013 }
1014
1015 //=============================================================================
1016
1017 // condition code conversions
1018
1019 static int cc_to_boint(int cc) {
1020 return Assembler::bcondCRbiIs0 | (cc & 8);
1021 }
1022
1023 static int cc_to_inverse_boint(int cc) {
1024 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1025 }
1026
1027 static int cc_to_biint(int cc, int flags_reg) {
1028 return (flags_reg << 2) | (cc & 3);
1029 }
1030
1031 //=============================================================================
1032
1033 // Compute padding required for nodes which need alignment. The padding
1034 // is the number of bytes (not instructions) which will be inserted before
1035 // the instruction. The padding must match the size of a NOP instruction.
1036
1037 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1038 return (3*4-current_offset)&31;
1039 }
1040
1041 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1042 return (2*4-current_offset)&31;
1043 }
1044
1045 int string_indexOf_immNode::compute_padding(int current_offset) const {
1046 return (3*4-current_offset)&31;
1047 }
1048
1049 int string_indexOfNode::compute_padding(int current_offset) const {
1050 return (1*4-current_offset)&31;
1051 }
1052
1053 int string_compareNode::compute_padding(int current_offset) const {
1054 return (4*4-current_offset)&31;
1055 }
1056
1057 int string_equals_immNode::compute_padding(int current_offset) const {
1058 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1059 return (2*4-current_offset)&31;
1060 }
1061
1062 int string_equalsNode::compute_padding(int current_offset) const {
1063 return (7*4-current_offset)&31;
1064 }
1065
1066 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1067 return (2*4-current_offset)&31;
1068 }
1069
1070 //=============================================================================
1071
1072 // Indicate if the safepoint node needs the polling page as an input.
1073 bool SafePointNode::needs_polling_address_input() {
1074 // The address is loaded from thread by a seperate node.
1075 return true;
1076 }
1077
1078 //=============================================================================
1079
1080 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1081 void emit_break(CodeBuffer &cbuf) {
1082 MacroAssembler _masm(&cbuf);
1083 __ illtrap();
1084 }
1085
1086 #ifndef PRODUCT
1087 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1088 st->print("BREAKPOINT");
1089 }
1090 #endif
1091
1092 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1093 emit_break(cbuf);
1094 }
1095
1096 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1097 return MachNode::size(ra_);
1098 }
1099
1100 //=============================================================================
1101
1102 void emit_nop(CodeBuffer &cbuf) {
1103 MacroAssembler _masm(&cbuf);
1104 __ nop();
1105 }
1106
1107 static inline void emit_long(CodeBuffer &cbuf, int value) {
1108 *((int*)(cbuf.insts_end())) = value;
1109 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1110 }
1111
1112 //=============================================================================
1113
1114 // Emit a trampoline stub for a call to a target which is too far away.
1115 //
1116 // code sequences:
1117 //
1118 // call-site:
1119 // branch-and-link to <destination> or <trampoline stub>
1120 //
1121 // Related trampoline stub for this call-site in the stub section:
1122 // load the call target from the constant pool
1123 // branch via CTR (LR/link still points to the call-site above)
1124
1125 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1126
1127 void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1128 // Start the stub.
1129 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1130 if (stub == NULL) {
1131 Compile::current()->env()->record_out_of_memory_failure();
1132 return;
1133 }
1134
1135 // For java_to_interp stubs we use R11_scratch1 as scratch register
1136 // and in call trampoline stubs we use R12_scratch2. This way we
1137 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1138 Register reg_scratch = R12_scratch2;
1139
1140 // Create a trampoline stub relocation which relates this trampoline stub
1141 // with the call instruction at insts_call_instruction_offset in the
1142 // instructions code-section.
1143 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1144 const int stub_start_offset = __ offset();
1145
1146 // Now, create the trampoline stub's code:
1147 // - load the TOC
1148 // - load the call target from the constant pool
1149 // - call
1150 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1151 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1152 __ mtctr(reg_scratch);
1153 __ bctr();
1154
1155 const address stub_start_addr = __ addr_at(stub_start_offset);
1156
1157 // FIXME: Assert that the trampoline stub can be identified and patched.
1158
1159 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1160 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1161 "encoded offset into the constant pool must match");
1162 // Trampoline_stub_size should be good.
1163 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1164 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1165
1166 // End the stub.
1167 __ end_a_stub();
1168 }
1169
1170 // Size of trampoline stub, this doesn't need to be accurate but it must
1171 // be larger or equal to the real size of the stub.
1172 // Used for optimization in Compile::Shorten_branches.
1173 uint size_call_trampoline() {
1174 return trampoline_stub_size;
1175 }
1176
1177 // Number of relocation entries needed by trampoline stub.
1178 // Used for optimization in Compile::Shorten_branches.
1179 uint reloc_call_trampoline() {
1180 return 5;
1181 }
1182
1183 //=============================================================================
1184
1185 // Emit an inline branch-and-link call and a related trampoline stub.
1186 //
1187 // code sequences:
1188 //
1189 // call-site:
1190 // branch-and-link to <destination> or <trampoline stub>
1191 //
1192 // Related trampoline stub for this call-site in the stub section:
1193 // load the call target from the constant pool
1194 // branch via CTR (LR/link still points to the call-site above)
1195 //
1196
1197 typedef struct {
1198 int insts_call_instruction_offset;
1199 int ret_addr_offset;
1200 } EmitCallOffsets;
1201
1202 // Emit a branch-and-link instruction that branches to a trampoline.
1203 // - Remember the offset of the branch-and-link instruction.
1204 // - Add a relocation at the branch-and-link instruction.
1205 // - Emit a branch-and-link.
1206 // - Remember the return pc offset.
1207 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1208 EmitCallOffsets offsets = { -1, -1 };
1209 const int start_offset = __ offset();
1210 offsets.insts_call_instruction_offset = __ offset();
1211
1212 // No entry point given, use the current pc.
1213 if (entry_point == NULL) entry_point = __ pc();
1214
1215 if (!Compile::current()->in_scratch_emit_size()) {
1216 // Put the entry point as a constant into the constant pool.
1217 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1218 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1219
1220 // Emit the trampoline stub which will be related to the branch-and-link below.
1221 emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1222 __ relocate(rtype);
1223 }
1224
1225 // Note: At this point we do not have the address of the trampoline
1226 // stub, and the entry point might be too far away for bl, so __ pc()
1227 // serves as dummy and the bl will be patched later.
1228 __ bl((address) __ pc());
1229
1230 offsets.ret_addr_offset = __ offset() - start_offset;
1231
1232 return offsets;
1233 }
1234
1235 //=============================================================================
1236
1237 // Factory for creating loadConL* nodes for large/small constant pool.
1238
1239 static inline jlong replicate_immF(float con) {
1240 // Replicate float con 2 times and pack into vector.
1241 int val = *((int*)&con);
1242 jlong lval = val;
1243 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1244 return lval;
1245 }
1246
1247 //=============================================================================
1248
1249 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1250 int Compile::ConstantTable::calculate_table_base_offset() const {
1251 return 0; // absolute addressing, no offset
1252 }
1253
1254 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1255 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1256 Compile *C = ra_->C;
1257
1258 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1259 MachNode *m1 = new (C) loadToc_hiNode();
1260 MachNode *m2 = new (C) loadToc_loNode();
1261
1262 m1->add_req(NULL);
1263 m2->add_req(NULL, m1);
1264 m1->_opnds[0] = op_dst;
1265 m2->_opnds[0] = op_dst;
1266 m2->_opnds[1] = op_dst;
1267 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1268 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1269 nodes->push(m1);
1270 nodes->push(m2);
1271 }
1272
1273 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1274 // Is postalloc expanded.
1275 ShouldNotReachHere();
1276 }
1277
1278 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1279 return 0;
1280 }
1281
1282 #ifndef PRODUCT
1283 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1284 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1285 }
1286 #endif
1287
1288 //=============================================================================
1289
1290 #ifndef PRODUCT
1291 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1292 Compile* C = ra_->C;
1293 const long framesize = C->frame_slots() << LogBytesPerInt;
1294
1295 st->print("PROLOG\n\t");
1296 if (C->need_stack_bang(framesize)) {
1297 st->print("stack_overflow_check\n\t");
1298 }
1299
1300 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1301 st->print("save return pc\n\t");
1302 st->print("push frame %d\n\t", -framesize);
1303 }
1304 }
1305 #endif
1306
1307 // Macro used instead of the common __ to emulate the pipes of PPC.
1308 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1309 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1310 // still no scheduling of this code is possible, the micro scheduler is aware of the
1311 // code and can update its internal data. The following mechanism is used to achieve this:
1312 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1313 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1314 #if 0 // TODO: PPC port
1315 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1316 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1317 _masm.
1318 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1319 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1320 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1321 C->hb_scheduling()->_pdScheduling->advance_offset
1322 #else
1323 #define ___(op) if (UsePower6SchedulerPPC64) \
1324 Unimplemented(); \
1325 _masm.
1326 #define ___stop if (UsePower6SchedulerPPC64) \
1327 Unimplemented()
1328 #define ___advance if (UsePower6SchedulerPPC64) \
1329 Unimplemented()
1330 #endif
1331
1332 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1333 Compile* C = ra_->C;
1334 MacroAssembler _masm(&cbuf);
1335
1336 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1337 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1338
1339 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1340
1341 const Register return_pc = R20; // Must match return_addr() in frame section.
1342 const Register callers_sp = R21;
1343 const Register push_frame_temp = R22;
1344 const Register toc_temp = R23;
1345 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1346
1347 if (method_is_frameless) {
1348 // Add nop at beginning of all frameless methods to prevent any
1349 // oop instructions from getting overwritten by make_not_entrant
1350 // (patching attempt would fail).
1351 ___(nop) nop();
1352 } else {
1353 // Get return pc.
1354 ___(mflr) mflr(return_pc);
1355 }
1356
1357 // Calls to C2R adapters often do not accept exceptional returns.
1358 // We require that their callers must bang for them. But be
1359 // careful, because some VM calls (such as call site linkage) can
1360 // use several kilobytes of stack. But the stack safety zone should
1361 // account for that. See bugs 4446381, 4468289, 4497237.
1362 if (C->need_stack_bang(framesize) && UseStackBanging) {
1363 // Unfortunately we cannot use the function provided in
1364 // assembler.cpp as we have to emulate the pipes. So I had to
1365 // insert the code of generate_stack_overflow_check(), see
1366 // assembler.cpp for some illuminative comments.
1367 const int page_size = os::vm_page_size();
1368 int bang_end = StackShadowPages*page_size;
1369
1370 // This is how far the previous frame's stack banging extended.
1371 const int bang_end_safe = bang_end;
1372
1373 if (framesize > page_size) {
1374 bang_end += framesize;
1375 }
1376
1377 int bang_offset = bang_end_safe;
1378
1379 while (bang_offset <= bang_end) {
1380 // Need at least one stack bang at end of shadow zone.
1381
1382 // Again I had to copy code, this time from assembler_ppc64.cpp,
1383 // bang_stack_with_offset - see there for comments.
1384
1385 // Stack grows down, caller passes positive offset.
1386 assert(bang_offset > 0, "must bang with positive offset");
1387
1388 long stdoffset = -bang_offset;
1389
1390 if (Assembler::is_simm(stdoffset, 16)) {
1391 // Signed 16 bit offset, a simple std is ok.
1392 if (UseLoadInstructionsForStackBangingPPC64) {
1393 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1394 } else {
1395 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1396 }
1397 } else if (Assembler::is_simm(stdoffset, 31)) {
1398 // Use largeoffset calculations for addis & ld/std.
1399 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1400 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1401
1402 Register tmp = R11;
1403 ___(addis) addis(tmp, R1_SP, hi);
1404 if (UseLoadInstructionsForStackBangingPPC64) {
1405 ___(ld) ld(R0, lo, tmp);
1406 } else {
1407 ___(std) std(R0, lo, tmp);
1408 }
1409 } else {
1410 ShouldNotReachHere();
1411 }
1412
1413 bang_offset += page_size;
1414 }
1415 // R11 trashed
1416 } // C->need_stack_bang(framesize) && UseStackBanging
1417
1418 unsigned int bytes = (unsigned int)framesize;
1419 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1420 ciMethod *currMethod = C -> method();
1421
1422 // Optimized version for most common case.
1423 if (UsePower6SchedulerPPC64 &&
1424 !method_is_frameless && Assembler::is_simm((int)(-(_abi(lr) + offset)), 16) &&
1425 !(false /* ConstantsALot TODO: PPC port*/)) {
1426 ___(or) mr(callers_sp, R1_SP);
1427 ___(addi) addi(R1_SP, R1_SP, -offset);
1428 ___stop; // Emulator won't recognize dependency.
1429 ___(std) std(return_pc, _abi(lr) + offset, R1_SP);
1430 ___(std) std(callers_sp, 0, R1_SP);
1431 return;
1432 }
1433
1434 if (!method_is_frameless) {
1435 // Get callers sp.
1436 ___(or) mr(callers_sp, R1_SP);
1437
1438 // Push method's frame, modifies SP.
1439 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1440 // The ABI is already accounted for in 'framesize' via the
1441 // 'out_preserve' area.
1442 Register tmp = push_frame_temp;
1443 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1444 if (Assembler::is_simm(-offset, 16)) {
1445 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1446 } else {
1447 long x = -offset;
1448 // Had to insert load_const(tmp, -offset).
1449 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1450 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1451 ___(rldicr) sldi(tmp, tmp, 32);
1452 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1453 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1454
1455 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1456 }
1457 }
1458 #if 0 // TODO: PPC port
1459 // For testing large constant pools, emit a lot of constants to constant pool.
1460 // "Randomize" const_size.
1461 if (ConstantsALot) {
1462 const int num_consts = const_size();
1463 for (int i = 0; i < num_consts; i++) {
1464 __ long_constant(0xB0B5B00BBABE);
1465 }
1466 }
1467 #endif
1468 if (!method_is_frameless) {
1469 // Save return pc.
1470 ___(std) std(return_pc, _abi(lr), callers_sp);
1471 }
1472 }
1473 #undef ___
1474 #undef ___stop
1475
1476 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1477 // Variable size. determine dynamically.
1478 return MachNode::size(ra_);
1479 }
1480
1481 int MachPrologNode::reloc() const {
1482 // Return number of relocatable values contained in this instruction.
1483 return 1; // 1 reloc entry for load_const(toc).
1484 }
1485
1486 //=============================================================================
1487
1488 #ifndef PRODUCT
1489 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1490 Compile* C = ra_->C;
1491
1492 st->print("EPILOG\n\t");
1493 st->print("restore return pc\n\t");
1494 st->print("pop frame\n\t");
1495
1496 if (do_polling() && C->is_method_compilation()) {
1497 st->print("touch polling page\n\t");
1498 }
1499 }
1500 #endif
1501
1502 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1503 Compile* C = ra_->C;
1504 MacroAssembler _masm(&cbuf);
1505
1506 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1507 assert(framesize >= 0, "negative frame-size?");
1508
1509 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1510 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1511 const Register return_pc = R11;
1512 const Register polling_page = R12;
1513
1514 if (!method_is_frameless) {
1515 // Restore return pc relative to callers' sp.
1516 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1517 }
1518
1519 if (method_needs_polling) {
1520 if (LoadPollAddressFromThread) {
1521 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1522 Unimplemented();
1523 } else {
1524 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1525 }
1526 }
1527
1528 if (!method_is_frameless) {
1529 // Move return pc to LR.
1530 __ mtlr(return_pc);
1531 // Pop frame (fixed frame-size).
1532 __ addi(R1_SP, R1_SP, (int)framesize);
1533 }
1534
1535 if (method_needs_polling) {
1536 // We need to mark the code position where the load from the safepoint
1537 // polling page was emitted as relocInfo::poll_return_type here.
1538 __ relocate(relocInfo::poll_return_type);
1539 __ load_from_polling_page(polling_page);
1540 }
1541 }
1542
1543 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1544 // Variable size. Determine dynamically.
1545 return MachNode::size(ra_);
1546 }
1547
1548 int MachEpilogNode::reloc() const {
1549 // Return number of relocatable values contained in this instruction.
1550 return 1; // 1 for load_from_polling_page.
1551 }
1552
1553 const Pipeline * MachEpilogNode::pipeline() const {
1554 return MachNode::pipeline_class();
1555 }
1556
1557 // This method seems to be obsolete. It is declared in machnode.hpp
1558 // and defined in all *.ad files, but it is never called. Should we
1559 // get rid of it?
1560 int MachEpilogNode::safepoint_offset() const {
1561 assert(do_polling(), "no return for this epilog node");
1562 return 0;
1563 }
1564
1565 #if 0 // TODO: PPC port
1566 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1567 MacroAssembler _masm(&cbuf);
1568 if (LoadPollAddressFromThread) {
1569 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1570 } else {
1571 _masm.nop();
1572 }
1573 }
1574
1575 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1576 if (LoadPollAddressFromThread) {
1577 return 4;
1578 } else {
1579 return 4;
1580 }
1581 }
1582
1583 #ifndef PRODUCT
1584 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1585 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1586 }
1587 #endif
1588
1589 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1590 return RSCRATCH1_BITS64_REG_mask();
1591 }
1592 #endif // PPC port
1593
1594 // =============================================================================
1595
1596 // Figure out which register class each belongs in: rc_int, rc_float or
1597 // rc_stack.
1598 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1599
1600 static enum RC rc_class(OptoReg::Name reg) {
1601 // Return the register class for the given register. The given register
1602 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1603 // enumeration in adGlobals_ppc64.hpp.
1604
1605 if (reg == OptoReg::Bad) return rc_bad;
1606
1607 // We have 64 integer register halves, starting at index 0.
1608 if (reg < 64) return rc_int;
1609
1610 // We have 64 floating-point register halves, starting at index 64.
1611 if (reg < 64+64) return rc_float;
1612
1613 // Between float regs & stack are the flags regs.
1614 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1615
1616 return rc_stack;
1617 }
1618
1619 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1620 bool do_print, Compile* C, outputStream *st) {
1621
1622 assert(opcode == Assembler::LD_OPCODE ||
1623 opcode == Assembler::STD_OPCODE ||
1624 opcode == Assembler::LWZ_OPCODE ||
1625 opcode == Assembler::STW_OPCODE ||
1626 opcode == Assembler::LFD_OPCODE ||
1627 opcode == Assembler::STFD_OPCODE ||
1628 opcode == Assembler::LFS_OPCODE ||
1629 opcode == Assembler::STFS_OPCODE,
1630 "opcode not supported");
1631
1632 if (cbuf) {
1633 int d =
1634 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1635 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1636 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1637 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1638 }
1639 #ifndef PRODUCT
1640 else if (do_print) {
1641 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1642 op_str,
1643 Matcher::regName[reg],
1644 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1645 }
1646 #endif
1647 return 4; // size
1648 }
1649
1650 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1651 Compile* C = ra_->C;
1652
1653 // Get registers to move.
1654 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1655 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1656 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1657 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1658
1659 enum RC src_hi_rc = rc_class(src_hi);
1660 enum RC src_lo_rc = rc_class(src_lo);
1661 enum RC dst_hi_rc = rc_class(dst_hi);
1662 enum RC dst_lo_rc = rc_class(dst_lo);
1663
1664 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1665 if (src_hi != OptoReg::Bad)
1666 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1667 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1668 "expected aligned-adjacent pairs");
1669 // Generate spill code!
1670 int size = 0;
1671
1672 if (src_lo == dst_lo && src_hi == dst_hi)
1673 return size; // Self copy, no move.
1674
1675 // --------------------------------------
1676 // Memory->Memory Spill. Use R0 to hold the value.
1677 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1678 int src_offset = ra_->reg2offset(src_lo);
1679 int dst_offset = ra_->reg2offset(dst_lo);
1680 if (src_hi != OptoReg::Bad) {
1681 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1682 "expected same type of move for high parts");
1683 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1684 if (!cbuf && !do_size) st->print("\n\t");
1685 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1686 } else {
1687 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1688 if (!cbuf && !do_size) st->print("\n\t");
1689 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1690 }
1691 return size;
1692 }
1693
1694 // --------------------------------------
1695 // Check for float->int copy; requires a trip through memory.
1696 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1697 Unimplemented();
1698 }
1699
1700 // --------------------------------------
1701 // Check for integer reg-reg copy.
1702 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1703 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1704 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1705 size = (Rsrc != Rdst) ? 4 : 0;
1706
1707 if (cbuf) {
1708 MacroAssembler _masm(cbuf);
1709 if (size) {
1710 __ mr(Rdst, Rsrc);
1711 }
1712 }
1713 #ifndef PRODUCT
1714 else if (!do_size) {
1715 if (size) {
1716 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1717 } else {
1718 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1719 }
1720 }
1721 #endif
1722 return size;
1723 }
1724
1725 // Check for integer store.
1726 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1727 int dst_offset = ra_->reg2offset(dst_lo);
1728 if (src_hi != OptoReg::Bad) {
1729 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1730 "expected same type of move for high parts");
1731 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1732 } else {
1733 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1734 }
1735 return size;
1736 }
1737
1738 // Check for integer load.
1739 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1740 int src_offset = ra_->reg2offset(src_lo);
1741 if (src_hi != OptoReg::Bad) {
1742 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1743 "expected same type of move for high parts");
1744 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1745 } else {
1746 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1747 }
1748 return size;
1749 }
1750
1751 // Check for float reg-reg copy.
1752 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1753 if (cbuf) {
1754 MacroAssembler _masm(cbuf);
1755 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1756 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1757 __ fmr(Rdst, Rsrc);
1758 }
1759 #ifndef PRODUCT
1760 else if (!do_size) {
1761 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1762 }
1763 #endif
1764 return 4;
1765 }
1766
1767 // Check for float store.
1768 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1769 int dst_offset = ra_->reg2offset(dst_lo);
1770 if (src_hi != OptoReg::Bad) {
1771 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1772 "expected same type of move for high parts");
1773 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1774 } else {
1775 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1776 }
1777 return size;
1778 }
1779
1780 // Check for float load.
1781 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1782 int src_offset = ra_->reg2offset(src_lo);
1783 if (src_hi != OptoReg::Bad) {
1784 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1785 "expected same type of move for high parts");
1786 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1787 } else {
1788 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1789 }
1790 return size;
1791 }
1792
1793 // --------------------------------------------------------------------
1794 // Check for hi bits still needing moving. Only happens for misaligned
1795 // arguments to native calls.
1796 if (src_hi == dst_hi)
1797 return size; // Self copy; no move.
1798
1799 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1800 ShouldNotReachHere(); // Unimplemented
1801 return 0;
1802 }
1803
1804 #ifndef PRODUCT
1805 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1806 if (!ra_)
1807 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1808 else
1809 implementation(NULL, ra_, false, st);
1810 }
1811 #endif
1812
1813 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1814 implementation(&cbuf, ra_, false, NULL);
1815 }
1816
1817 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1818 return implementation(NULL, ra_, true, NULL);
1819 }
1820
1821 #if 0 // TODO: PPC port
1822 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1823 #ifndef PRODUCT
1824 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1825 #endif
1826 assert(ra_->node_regs_max_index() != 0, "");
1827
1828 // Get registers to move.
1829 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1830 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1831 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1832 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1833
1834 enum RC src_lo_rc = rc_class(src_lo);
1835 enum RC dst_lo_rc = rc_class(dst_lo);
1836
1837 if (src_lo == dst_lo && src_hi == dst_hi)
1838 return ppc64Opcode_none; // Self copy, no move.
1839
1840 // --------------------------------------
1841 // Memory->Memory Spill. Use R0 to hold the value.
1842 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1843 return ppc64Opcode_compound;
1844 }
1845
1846 // --------------------------------------
1847 // Check for float->int copy; requires a trip through memory.
1848 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1849 Unimplemented();
1850 }
1851
1852 // --------------------------------------
1853 // Check for integer reg-reg copy.
1854 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1855 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1856 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1857 if (Rsrc == Rdst) {
1858 return ppc64Opcode_none;
1859 } else {
1860 return ppc64Opcode_or;
1861 }
1862 }
1863
1864 // Check for integer store.
1865 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1866 if (src_hi != OptoReg::Bad) {
1867 return ppc64Opcode_std;
1868 } else {
1869 return ppc64Opcode_stw;
1870 }
1871 }
1872
1873 // Check for integer load.
1874 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1875 if (src_hi != OptoReg::Bad) {
1876 return ppc64Opcode_ld;
1877 } else {
1878 return ppc64Opcode_lwz;
1879 }
1880 }
1881
1882 // Check for float reg-reg copy.
1883 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1884 return ppc64Opcode_fmr;
1885 }
1886
1887 // Check for float store.
1888 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1889 if (src_hi != OptoReg::Bad) {
1890 return ppc64Opcode_stfd;
1891 } else {
1892 return ppc64Opcode_stfs;
1893 }
1894 }
1895
1896 // Check for float load.
1897 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1898 if (src_hi != OptoReg::Bad) {
1899 return ppc64Opcode_lfd;
1900 } else {
1901 return ppc64Opcode_lfs;
1902 }
1903 }
1904
1905 // --------------------------------------------------------------------
1906 // Check for hi bits still needing moving. Only happens for misaligned
1907 // arguments to native calls.
1908 if (src_hi == dst_hi)
1909 return ppc64Opcode_none; // Self copy; no move.
1910
1911 ShouldNotReachHere();
1912 return ppc64Opcode_undefined;
1913 }
1914 #endif // PPC port
1915
1916 #ifndef PRODUCT
1917 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1918 st->print("NOP \t// %d nops to pad for loops.", _count);
1919 }
1920 #endif
1921
1922 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1923 MacroAssembler _masm(&cbuf);
1924 // _count contains the number of nops needed for padding.
1925 for (int i = 0; i < _count; i++) {
1926 __ nop();
1927 }
1928 }
1929
1930 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1931 return _count * 4;
1932 }
1933
1934 #ifndef PRODUCT
1935 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1936 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1937 int reg = ra_->get_reg_first(this);
1938 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1939 }
1940 #endif
1941
1942 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1943 MacroAssembler _masm(&cbuf);
1944
1945 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1946 int reg = ra_->get_encode(this);
1947
1948 if (Assembler::is_simm(offset, 16)) {
1949 __ addi(as_Register(reg), R1, offset);
1950 } else {
1951 ShouldNotReachHere();
1952 }
1953 }
1954
1955 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1956 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1957 return 4;
1958 }
1959
1960 #ifndef PRODUCT
1961 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1962 st->print_cr("---- MachUEPNode ----");
1963 st->print_cr("...");
1964 }
1965 #endif
1966
1967 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1968 // This is the unverified entry point.
1969 MacroAssembler _masm(&cbuf);
1970
1971 // Inline_cache contains a klass.
1972 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1973 Register receiver_klass = R0; // tmp
1974
1975 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1976 assert(R11_scratch1 == R11, "need prologue scratch register");
1977
1978 // Check for NULL argument if we don't have implicit null checks.
1979 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1980 if (TrapBasedNullChecks) {
1981 __ trap_null_check(R3_ARG1);
1982 } else {
1983 Label valid;
1984 __ cmpdi(CCR0, R3_ARG1, 0);
1985 __ bne_predict_taken(CCR0, valid);
1986 // We have a null argument, branch to ic_miss_stub.
1987 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1988 relocInfo::runtime_call_type);
1989 __ bind(valid);
1990 }
1991 }
1992 // Assume argument is not NULL, load klass from receiver.
1993 __ load_klass(receiver_klass, R3_ARG1);
1994
1995 if (TrapBasedICMissChecks) {
1996 __ trap_ic_miss_check(receiver_klass, ic_klass);
1997 } else {
1998 Label valid;
1999 __ cmpd(CCR0, receiver_klass, ic_klass);
2000 __ beq_predict_taken(CCR0, valid);
2001 // We have an unexpected klass, branch to ic_miss_stub.
2002 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2003 relocInfo::runtime_call_type);
2004 __ bind(valid);
2005 }
2006
2007 // Argument is valid and klass is as expected, continue.
2008 }
2009
2010 #if 0 // TODO: PPC port
2011 // Optimize UEP code on z (save a load_const() call in main path).
2012 int MachUEPNode::ep_offset() {
2013 return 0;
2014 }
2015 #endif
2016
2017 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2018 // Variable size. Determine dynamically.
2019 return MachNode::size(ra_);
2020 }
2021
2022 //=============================================================================
2023
2024 uint size_exception_handler() {
2025 // The exception_handler is a b64_patchable.
2026 return MacroAssembler::b64_patchable_size;
2027 }
2028
2029 uint size_deopt_handler() {
2030 // The deopt_handler is a bl64_patchable.
2031 return MacroAssembler::bl64_patchable_size;
2032 }
2033
2034 int emit_exception_handler(CodeBuffer &cbuf) {
2035 MacroAssembler _masm(&cbuf);
2036
2037 address base = __ start_a_stub(size_exception_handler());
2038 if (base == NULL) return 0; // CodeBuffer::expand failed
2039
2040 int offset = __ offset();
2041 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2042 relocInfo::runtime_call_type);
2043 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2044 __ end_a_stub();
2045
2046 return offset;
2047 }
2048
2049 // The deopt_handler is like the exception handler, but it calls to
2050 // the deoptimization blob instead of jumping to the exception blob.
2051 int emit_deopt_handler(CodeBuffer& cbuf) {
2052 MacroAssembler _masm(&cbuf);
2053
2054 address base = __ start_a_stub(size_deopt_handler());
2055 if (base == NULL) return 0; // CodeBuffer::expand failed
2056
2057 int offset = __ offset();
2058 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2059 relocInfo::runtime_call_type);
2060 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2061 __ end_a_stub();
2062
2063 return offset;
2064 }
2065
2066 //=============================================================================
2067
2068 // Use a frame slots bias for frameless methods if accessing the stack.
2069 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2070 if (as_Register(reg_enc) == R1_SP) {
2071 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2072 }
2073 return 0;
2074 }
2075
2076 const bool Matcher::match_rule_supported(int opcode) {
2077 if (!has_match_rule(opcode))
2078 return false;
2079
2080 switch (opcode) {
2081 case Op_CountLeadingZerosI:
2082 case Op_CountLeadingZerosL:
2083 case Op_CountTrailingZerosI:
2084 case Op_CountTrailingZerosL:
2085 if (!UseCountLeadingZerosInstructionsPPC64)
2086 return false;
2087 break;
2088
2089 case Op_PopCountI:
2090 case Op_PopCountL:
2091 return (UsePopCountInstruction && VM_Version::has_popcntw());
2092
2093 case Op_StrComp:
2094 return SpecialStringCompareTo;
2095 case Op_StrEquals:
2096 return SpecialStringEquals;
2097 case Op_StrIndexOf:
2098 return SpecialStringIndexOf;
2099 }
2100
2101 return true; // Per default match rules are supported.
2102 }
2103
2104 int Matcher::regnum_to_fpu_offset(int regnum) {
2105 // No user for this method?
2106 Unimplemented();
2107 return 999;
2108 }
2109
2110 const bool Matcher::convL2FSupported(void) {
2111 // fcfids can do the conversion (>= Power7).
2112 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2113 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2114 }
2115
2116 // Vector width in bytes.
2117 const int Matcher::vector_width_in_bytes(BasicType bt) {
2118 assert(MaxVectorSize == 8, "");
2119 return 8;
2120 }
2121
2122 // Vector ideal reg.
2123 const int Matcher::vector_ideal_reg(int size) {
2124 assert(MaxVectorSize == 8 && size == 8, "");
2125 return Op_RegL;
2126 }
2127
2128 const int Matcher::vector_shift_count_ideal_reg(int size) {
2129 fatal("vector shift is not supported");
2130 return Node::NotAMachineReg;
2131 }
2132
2133 // Limits on vector size (number of elements) loaded into vector.
2134 const int Matcher::max_vector_size(const BasicType bt) {
2135 assert(is_java_primitive(bt), "only primitive type vectors");
2136 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2137 }
2138
2139 const int Matcher::min_vector_size(const BasicType bt) {
2140 return max_vector_size(bt); // Same as max.
2141 }
2142
2143 // PPC doesn't support misaligned vectors store/load.
2144 const bool Matcher::misaligned_vectors_ok() {
2145 return false;
2146 }
2147
2148 // RETURNS: whether this branch offset is short enough that a short
2149 // branch can be used.
2150 //
2151 // If the platform does not provide any short branch variants, then
2152 // this method should return `false' for offset 0.
2153 //
2154 // `Compile::Fill_buffer' will decide on basis of this information
2155 // whether to do the pass `Compile::Shorten_branches' at all.
2156 //
2157 // And `Compile::Shorten_branches' will decide on basis of this
2158 // information whether to replace particular branch sites by short
2159 // ones.
2160 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2161 // Is the offset within the range of a ppc64 pc relative branch?
2162 bool b;
2163
2164 const int safety_zone = 3 * BytesPerInstWord;
2165 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2166 29 - 16 + 1 + 2);
2167 return b;
2168 }
2169
2170 const bool Matcher::isSimpleConstant64(jlong value) {
2171 // Probably always true, even if a temp register is required.
2172 return true;
2173 }
2174 /* TODO: PPC port
2175 // Make a new machine dependent decode node (with its operands).
2176 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2177 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2178 "This method is only implemented for unscaled cOops mode so far");
2179 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2180 decode->set_opnd_array(0, new (C) iRegPdstOper());
2181 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2182 return decode;
2183 }
2184 */
2185 // Threshold size for cleararray.
2186 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2187
2188 // false => size gets scaled to BytesPerLong, ok.
2189 const bool Matcher::init_array_count_is_in_bytes = false;
2190
2191 // Use conditional move (CMOVL) on Power7.
2192 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2193
2194 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2195 // fsel doesn't accept a condition register as input, so this would be slightly different.
2196 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2197
2198 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2199 const bool Matcher::require_postalloc_expand = true;
2200
2201 // Should the Matcher clone shifts on addressing modes, expecting them to
2202 // be subsumed into complex addressing expressions or compute them into
2203 // registers? True for Intel but false for most RISCs.
2204 const bool Matcher::clone_shift_expressions = false;
2205
2206 // Do we need to mask the count passed to shift instructions or does
2207 // the cpu only look at the lower 5/6 bits anyway?
2208 // Off, as masks are generated in expand rules where required.
2209 // Constant shift counts are handled in Ideal phase.
2210 const bool Matcher::need_masked_shift_count = false;
2211
2212 // This affects two different things:
2213 // - how Decode nodes are matched
2214 // - how ImplicitNullCheck opportunities are recognized
2215 // If true, the matcher will try to remove all Decodes and match them
2216 // (as operands) into nodes. NullChecks are not prepared to deal with
2217 // Decodes by final_graph_reshaping().
2218 // If false, final_graph_reshaping() forces the decode behind the Cmp
2219 // for a NullCheck. The matcher matches the Decode node into a register.
2220 // Implicit_null_check optimization moves the Decode along with the
2221 // memory operation back up before the NullCheck.
2222 bool Matcher::narrow_oop_use_complex_address() {
2223 // TODO: PPC port if (MatchDecodeNodes) return true;
2224 return false;
2225 }
2226
2227 bool Matcher::narrow_klass_use_complex_address() {
2228 NOT_LP64(ShouldNotCallThis());
2229 assert(UseCompressedClassPointers, "only for compressed klass code");
2230 // TODO: PPC port if (MatchDecodeNodes) return true;
2231 return false;
2232 }
2233
2234 // Is it better to copy float constants, or load them directly from memory?
2235 // Intel can load a float constant from a direct address, requiring no
2236 // extra registers. Most RISCs will have to materialize an address into a
2237 // register first, so they would do better to copy the constant from stack.
2238 const bool Matcher::rematerialize_float_constants = false;
2239
2240 // If CPU can load and store mis-aligned doubles directly then no fixup is
2241 // needed. Else we split the double into 2 integer pieces and move it
2242 // piece-by-piece. Only happens when passing doubles into C code as the
2243 // Java calling convention forces doubles to be aligned.
2244 const bool Matcher::misaligned_doubles_ok = true;
2245
2246 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2247 Unimplemented();
2248 }
2249
2250 // Advertise here if the CPU requires explicit rounding operations
2251 // to implement the UseStrictFP mode.
2252 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2253
2254 // Do floats take an entire double register or just half?
2255 //
2256 // A float occupies a ppc64 double register. For the allocator, a
2257 // ppc64 double register appears as a pair of float registers.
2258 bool Matcher::float_in_double() { return true; }
2259
2260 // Do ints take an entire long register or just half?
2261 // The relevant question is how the int is callee-saved:
2262 // the whole long is written but de-opt'ing will have to extract
2263 // the relevant 32 bits.
2264 const bool Matcher::int_in_long = true;
2265
2266 // Constants for c2c and c calling conventions.
2267
2268 const MachRegisterNumbers iarg_reg[8] = {
2269 R3_num, R4_num, R5_num, R6_num,
2270 R7_num, R8_num, R9_num, R10_num
2271 };
2272
2273 const MachRegisterNumbers farg_reg[13] = {
2274 F1_num, F2_num, F3_num, F4_num,
2275 F5_num, F6_num, F7_num, F8_num,
2276 F9_num, F10_num, F11_num, F12_num,
2277 F13_num
2278 };
2279
2280 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2281
2282 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2283
2284 // Return whether or not this register is ever used as an argument. This
2285 // function is used on startup to build the trampoline stubs in generateOptoStub.
2286 // Registers not mentioned will be killed by the VM call in the trampoline, and
2287 // arguments in those registers not be available to the callee.
2288 bool Matcher::can_be_java_arg(int reg) {
2289 // We return true for all registers contained in iarg_reg[] and
2290 // farg_reg[] and their virtual halves.
2291 // We must include the virtual halves in order to get STDs and LDs
2292 // instead of STWs and LWs in the trampoline stubs.
2293
2294 if ( reg == R3_num || reg == R3_H_num
2295 || reg == R4_num || reg == R4_H_num
2296 || reg == R5_num || reg == R5_H_num
2297 || reg == R6_num || reg == R6_H_num
2298 || reg == R7_num || reg == R7_H_num
2299 || reg == R8_num || reg == R8_H_num
2300 || reg == R9_num || reg == R9_H_num
2301 || reg == R10_num || reg == R10_H_num)
2302 return true;
2303
2304 if ( reg == F1_num || reg == F1_H_num
2305 || reg == F2_num || reg == F2_H_num
2306 || reg == F3_num || reg == F3_H_num
2307 || reg == F4_num || reg == F4_H_num
2308 || reg == F5_num || reg == F5_H_num
2309 || reg == F6_num || reg == F6_H_num
2310 || reg == F7_num || reg == F7_H_num
2311 || reg == F8_num || reg == F8_H_num
2312 || reg == F9_num || reg == F9_H_num
2313 || reg == F10_num || reg == F10_H_num
2314 || reg == F11_num || reg == F11_H_num
2315 || reg == F12_num || reg == F12_H_num
2316 || reg == F13_num || reg == F13_H_num)
2317 return true;
2318
2319 return false;
2320 }
2321
2322 bool Matcher::is_spillable_arg(int reg) {
2323 return can_be_java_arg(reg);
2324 }
2325
2326 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2327 return false;
2328 }
2329
2330 // Register for DIVI projection of divmodI.
2331 RegMask Matcher::divI_proj_mask() {
2332 ShouldNotReachHere();
2333 return RegMask();
2334 }
2335
2336 // Register for MODI projection of divmodI.
2337 RegMask Matcher::modI_proj_mask() {
2338 ShouldNotReachHere();
2339 return RegMask();
2340 }
2341
2342 // Register for DIVL projection of divmodL.
2343 RegMask Matcher::divL_proj_mask() {
2344 ShouldNotReachHere();
2345 return RegMask();
2346 }
2347
2348 // Register for MODL projection of divmodL.
2349 RegMask Matcher::modL_proj_mask() {
2350 ShouldNotReachHere();
2351 return RegMask();
2352 }
2353
2354 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2355 return RegMask();
2356 }
2357
2358 const RegMask Matcher::mathExactI_result_proj_mask() {
2359 return RARG4_BITS64_REG_mask();
2360 }
2361
2362 const RegMask Matcher::mathExactL_result_proj_mask() {
2363 return RARG4_BITS64_REG_mask();
2364 }
2365
2366 const RegMask Matcher::mathExactI_flags_proj_mask() {
2367 return INT_FLAGS_mask();
2368 }
2369
2370 %}
2371
2372 //----------ENCODING BLOCK-----------------------------------------------------
2373 // This block specifies the encoding classes used by the compiler to output
2374 // byte streams. Encoding classes are parameterized macros used by
2375 // Machine Instruction Nodes in order to generate the bit encoding of the
2376 // instruction. Operands specify their base encoding interface with the
2377 // interface keyword. There are currently supported four interfaces,
2378 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2379 // operand to generate a function which returns its register number when
2380 // queried. CONST_INTER causes an operand to generate a function which
2381 // returns the value of the constant when queried. MEMORY_INTER causes an
2382 // operand to generate four functions which return the Base Register, the
2383 // Index Register, the Scale Value, and the Offset Value of the operand when
2384 // queried. COND_INTER causes an operand to generate six functions which
2385 // return the encoding code (ie - encoding bits for the instruction)
2386 // associated with each basic boolean condition for a conditional instruction.
2387 //
2388 // Instructions specify two basic values for encoding. Again, a function
2389 // is available to check if the constant displacement is an oop. They use the
2390 // ins_encode keyword to specify their encoding classes (which must be
2391 // a sequence of enc_class names, and their parameters, specified in
2392 // the encoding block), and they use the
2393 // opcode keyword to specify, in order, their primary, secondary, and
2394 // tertiary opcode. Only the opcode sections which a particular instruction
2395 // needs for encoding need to be specified.
2396 encode %{
2397 enc_class enc_unimplemented %{
2398 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2399 MacroAssembler _masm(&cbuf);
2400 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2401 %}
2402
2403 enc_class enc_untested %{
2404 #ifdef ASSERT
2405 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2406 MacroAssembler _masm(&cbuf);
2407 __ untested("Untested mach node encoding in AD file.");
2408 #else
2409 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2410 #endif
2411 %}
2412
2413 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2414 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2415 MacroAssembler _masm(&cbuf);
2416 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2417 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2418 %}
2419
2420 // Load acquire.
2421 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2422 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2423 MacroAssembler _masm(&cbuf);
2424 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2425 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2426 __ twi_0($dst$$Register);
2427 __ isync();
2428 %}
2429
2430 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2431 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2432
2433 MacroAssembler _masm(&cbuf);
2434 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2435 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2436 %}
2437
2438 // Load acquire.
2439 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2440 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2441
2442 MacroAssembler _masm(&cbuf);
2443 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2444 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2445 __ twi_0($dst$$Register);
2446 __ isync();
2447 %}
2448
2449 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2450 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2451
2452 MacroAssembler _masm(&cbuf);
2453 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2454 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2455 %}
2456
2457 // Load acquire.
2458 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2459 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2460
2461 MacroAssembler _masm(&cbuf);
2462 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2463 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2464 __ twi_0($dst$$Register);
2465 __ isync();
2466 %}
2467
2468 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2469 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2470 MacroAssembler _masm(&cbuf);
2471 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2472 // Operand 'ds' requires 4-alignment.
2473 assert((Idisp & 0x3) == 0, "unaligned offset");
2474 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2475 %}
2476
2477 // Load acquire.
2478 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2479 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2480 MacroAssembler _masm(&cbuf);
2481 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2482 // Operand 'ds' requires 4-alignment.
2483 assert((Idisp & 0x3) == 0, "unaligned offset");
2484 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2485 __ twi_0($dst$$Register);
2486 __ isync();
2487 %}
2488
2489 enc_class enc_lfd(RegF dst, memory mem) %{
2490 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2491 MacroAssembler _masm(&cbuf);
2492 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2493 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2494 %}
2495
2496 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2497 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2498
2499 MacroAssembler _masm(&cbuf);
2500 int toc_offset = 0;
2501
2502 if (!ra_->C->in_scratch_emit_size()) {
2503 address const_toc_addr;
2504 // Create a non-oop constant, no relocation needed.
2505 // If it is an IC, it has a virtual_call_Relocation.
2506 const_toc_addr = __ long_constant((jlong)$src$$constant);
2507
2508 // Get the constant's TOC offset.
2509 toc_offset = __ offset_to_method_toc(const_toc_addr);
2510
2511 // Keep the current instruction offset in mind.
2512 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2513 }
2514
2515 __ ld($dst$$Register, toc_offset, $toc$$Register);
2516 %}
2517
2518 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2519 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2520
2521 MacroAssembler _masm(&cbuf);
2522
2523 if (!ra_->C->in_scratch_emit_size()) {
2524 address const_toc_addr;
2525 // Create a non-oop constant, no relocation needed.
2526 // If it is an IC, it has a virtual_call_Relocation.
2527 const_toc_addr = __ long_constant((jlong)$src$$constant);
2528
2529 // Get the constant's TOC offset.
2530 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2531 // Store the toc offset of the constant.
2532 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2533
2534 // Also keep the current instruction offset in mind.
2535 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2536 }
2537
2538 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2539 %}
2540
2541 %} // encode
2542
2543 source %{
2544
2545 typedef struct {
2546 loadConL_hiNode *_large_hi;
2547 loadConL_loNode *_large_lo;
2548 loadConLNode *_small;
2549 MachNode *_last;
2550 } loadConLNodesTuple;
2551
2552 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2553 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2554 loadConLNodesTuple nodes;
2555
2556 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2557 if (large_constant_pool) {
2558 // Create new nodes.
2559 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2560 loadConL_loNode *m2 = new (C) loadConL_loNode();
2561
2562 // inputs for new nodes
2563 m1->add_req(NULL, toc);
2564 m2->add_req(NULL, m1);
2565
2566 // operands for new nodes
2567 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2568 m1->_opnds[1] = immSrc; // src
2569 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2570 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2571 m2->_opnds[1] = immSrc; // src
2572 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2573
2574 // Initialize ins_attrib TOC fields.
2575 m1->_const_toc_offset = -1;
2576 m2->_const_toc_offset_hi_node = m1;
2577
2578 // Initialize ins_attrib instruction offset.
2579 m1->_cbuf_insts_offset = -1;
2580
2581 // register allocation for new nodes
2582 ra_->set_pair(m1->_idx, reg_second, reg_first);
2583 ra_->set_pair(m2->_idx, reg_second, reg_first);
2584
2585 // Create result.
2586 nodes._large_hi = m1;
2587 nodes._large_lo = m2;
2588 nodes._small = NULL;
2589 nodes._last = nodes._large_lo;
2590 assert(m2->bottom_type()->isa_long(), "must be long");
2591 } else {
2592 loadConLNode *m2 = new (C) loadConLNode();
2593
2594 // inputs for new nodes
2595 m2->add_req(NULL, toc);
2596
2597 // operands for new nodes
2598 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2599 m2->_opnds[1] = immSrc; // src
2600 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2601
2602 // Initialize ins_attrib instruction offset.
2603 m2->_cbuf_insts_offset = -1;
2604
2605 // register allocation for new nodes
2606 ra_->set_pair(m2->_idx, reg_second, reg_first);
2607
2608 // Create result.
2609 nodes._large_hi = NULL;
2610 nodes._large_lo = NULL;
2611 nodes._small = m2;
2612 nodes._last = nodes._small;
2613 assert(m2->bottom_type()->isa_long(), "must be long");
2614 }
2615
2616 return nodes;
2617 }
2618
2619 %} // source
2620
2621 encode %{
2622 // Postalloc expand emitter for loading a long constant from the method's TOC.
2623 // Enc_class needed as consttanttablebase is not supported by postalloc
2624 // expand.
2625 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2626 // Create new nodes.
2627 loadConLNodesTuple loadConLNodes =
2628 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2629 ra_->get_reg_second(this), ra_->get_reg_first(this));
2630
2631 // Push new nodes.
2632 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2633 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2634
2635 // some asserts
2636 assert(nodes->length() >= 1, "must have created at least 1 node");
2637 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2638 %}
2639
2640 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2641 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2642
2643 MacroAssembler _masm(&cbuf);
2644 int toc_offset = 0;
2645
2646 if (!ra_->C->in_scratch_emit_size()) {
2647 intptr_t val = $src$$constant;
2648 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2649 address const_toc_addr;
2650 if (constant_reloc == relocInfo::oop_type) {
2651 // Create an oop constant and a corresponding relocation.
2652 AddressLiteral a = __ allocate_oop_address((jobject)val);
2653 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2654 __ relocate(a.rspec());
2655 } else if (constant_reloc == relocInfo::metadata_type) {
2656 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2657 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2658 __ relocate(a.rspec());
2659 } else {
2660 // Create a non-oop constant, no relocation needed.
2661 const_toc_addr = __ long_constant((jlong)$src$$constant);
2662 }
2663
2664 // Get the constant's TOC offset.
2665 toc_offset = __ offset_to_method_toc(const_toc_addr);
2666 }
2667
2668 __ ld($dst$$Register, toc_offset, $toc$$Register);
2669 %}
2670
2671 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2672 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2673
2674 MacroAssembler _masm(&cbuf);
2675 if (!ra_->C->in_scratch_emit_size()) {
2676 intptr_t val = $src$$constant;
2677 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2678 address const_toc_addr;
2679 if (constant_reloc == relocInfo::oop_type) {
2680 // Create an oop constant and a corresponding relocation.
2681 AddressLiteral a = __ allocate_oop_address((jobject)val);
2682 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2683 __ relocate(a.rspec());
2684 } else if (constant_reloc == relocInfo::metadata_type) {
2685 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2686 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2687 __ relocate(a.rspec());
2688 } else { // non-oop pointers, e.g. card mark base, heap top
2689 // Create a non-oop constant, no relocation needed.
2690 const_toc_addr = __ long_constant((jlong)$src$$constant);
2691 }
2692
2693 // Get the constant's TOC offset.
2694 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2695 // Store the toc offset of the constant.
2696 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2697 }
2698
2699 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2700 %}
2701
2702 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2703 // Enc_class needed as consttanttablebase is not supported by postalloc
2704 // expand.
2705 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2706 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2707 if (large_constant_pool) {
2708 // Create new nodes.
2709 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2710 loadConP_loNode *m2 = new (C) loadConP_loNode();
2711
2712 // inputs for new nodes
2713 m1->add_req(NULL, n_toc);
2714 m2->add_req(NULL, m1);
2715
2716 // operands for new nodes
2717 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2718 m1->_opnds[1] = op_src; // src
2719 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2720 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2721 m2->_opnds[1] = op_src; // src
2722 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2723
2724 // Initialize ins_attrib TOC fields.
2725 m1->_const_toc_offset = -1;
2726 m2->_const_toc_offset_hi_node = m1;
2727
2728 // Register allocation for new nodes.
2729 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2730 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2731
2732 nodes->push(m1);
2733 nodes->push(m2);
2734 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2735 } else {
2736 loadConPNode *m2 = new (C) loadConPNode();
2737
2738 // inputs for new nodes
2739 m2->add_req(NULL, n_toc);
2740
2741 // operands for new nodes
2742 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2743 m2->_opnds[1] = op_src; // src
2744 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2745
2746 // Register allocation for new nodes.
2747 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2748
2749 nodes->push(m2);
2750 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2751 }
2752 %}
2753
2754 // Enc_class needed as consttanttablebase is not supported by postalloc
2755 // expand.
2756 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2757 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2758
2759 MachNode *m2;
2760 if (large_constant_pool) {
2761 m2 = new (C) loadConFCompNode();
2762 } else {
2763 m2 = new (C) loadConFNode();
2764 }
2765 // inputs for new nodes
2766 m2->add_req(NULL, n_toc);
2767
2768 // operands for new nodes
2769 m2->_opnds[0] = op_dst;
2770 m2->_opnds[1] = op_src;
2771 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2772
2773 // register allocation for new nodes
2774 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2775 nodes->push(m2);
2776 %}
2777
2778 // Enc_class needed as consttanttablebase is not supported by postalloc
2779 // expand.
2780 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2781 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2782
2783 MachNode *m2;
2784 if (large_constant_pool) {
2785 m2 = new (C) loadConDCompNode();
2786 } else {
2787 m2 = new (C) loadConDNode();
2788 }
2789 // inputs for new nodes
2790 m2->add_req(NULL, n_toc);
2791
2792 // operands for new nodes
2793 m2->_opnds[0] = op_dst;
2794 m2->_opnds[1] = op_src;
2795 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2796
2797 // register allocation for new nodes
2798 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2799 nodes->push(m2);
2800 %}
2801
2802 enc_class enc_stw(iRegIsrc src, memory mem) %{
2803 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2804 MacroAssembler _masm(&cbuf);
2805 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2806 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2807 %}
2808
2809 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2810 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2811 MacroAssembler _masm(&cbuf);
2812 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2813 // Operand 'ds' requires 4-alignment.
2814 assert((Idisp & 0x3) == 0, "unaligned offset");
2815 __ std($src$$Register, Idisp, $mem$$base$$Register);
2816 %}
2817
2818 enc_class enc_stfs(RegF src, memory mem) %{
2819 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2820 MacroAssembler _masm(&cbuf);
2821 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2822 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2823 %}
2824
2825 enc_class enc_stfd(RegF src, memory mem) %{
2826 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2827 MacroAssembler _masm(&cbuf);
2828 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2829 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2830 %}
2831
2832 // Use release_store for card-marking to ensure that previous
2833 // oop-stores are visible before the card-mark change.
2834 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2835 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2836 // FIXME: Implement this as a cmove and use a fixed condition code
2837 // register which is written on every transition to compiled code,
2838 // e.g. in call-stub and when returning from runtime stubs.
2839 //
2840 // Proposed code sequence for the cmove implementation:
2841 //
2842 // Label skip_release;
2843 // __ beq(CCRfixed, skip_release);
2844 // __ release();
2845 // __ bind(skip_release);
2846 // __ stb(card mark);
2847
2848 MacroAssembler _masm(&cbuf);
2849 Label skip_storestore;
2850
2851 #if 0 // TODO: PPC port
2852 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2853 // StoreStore barrier conditionally.
2854 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2855 __ cmpwi(CCR0, R0, 0);
2856 __ beq_predict_taken(CCR0, skip_release);
2857 #endif
2858 __ li(R0, 0);
2859 __ membar(Assembler::StoreStore);
2860 #if 0 // TODO: PPC port
2861 __ bind(skip_storestore);
2862 #endif
2863
2864 // Do the store.
2865 if ($mem$$index == 0) {
2866 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2867 } else {
2868 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2869 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2870 }
2871 %}
2872
2873 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2874
2875 if (VM_Version::has_isel()) {
2876 // use isel instruction with Power 7
2877 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2878 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2879 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2880 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2881
2882 n_compare->add_req(n_region, n_src);
2883 n_compare->_opnds[0] = op_crx;
2884 n_compare->_opnds[1] = op_src;
2885 n_compare->_opnds[2] = new (C) immL16Oper(0);
2886
2887 n_sub_base->add_req(n_region, n_src);
2888 n_sub_base->_opnds[0] = op_dst;
2889 n_sub_base->_opnds[1] = op_src;
2890 n_sub_base->_bottom_type = _bottom_type;
2891
2892 n_shift->add_req(n_region, n_sub_base);
2893 n_shift->_opnds[0] = op_dst;
2894 n_shift->_opnds[1] = op_dst;
2895 n_shift->_bottom_type = _bottom_type;
2896
2897 n_cond_set->add_req(n_region, n_compare, n_shift);
2898 n_cond_set->_opnds[0] = op_dst;
2899 n_cond_set->_opnds[1] = op_crx;
2900 n_cond_set->_opnds[2] = op_dst;
2901 n_cond_set->_bottom_type = _bottom_type;
2902
2903 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2904 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2905 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2906 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2907
2908 nodes->push(n_compare);
2909 nodes->push(n_sub_base);
2910 nodes->push(n_shift);
2911 nodes->push(n_cond_set);
2912
2913 } else {
2914 // before Power 7
2915 moveRegNode *n_move = new (C) moveRegNode();
2916 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2917 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2918 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2919
2920 n_move->add_req(n_region, n_src);
2921 n_move->_opnds[0] = op_dst;
2922 n_move->_opnds[1] = op_src;
2923 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2924
2925 n_compare->add_req(n_region, n_src);
2926 n_compare->add_prec(n_move);
2927
2928 n_compare->_opnds[0] = op_crx;
2929 n_compare->_opnds[1] = op_src;
2930 n_compare->_opnds[2] = new (C) immL16Oper(0);
2931
2932 n_sub_base->add_req(n_region, n_compare, n_src);
2933 n_sub_base->_opnds[0] = op_dst;
2934 n_sub_base->_opnds[1] = op_crx;
2935 n_sub_base->_opnds[2] = op_src;
2936 n_sub_base->_bottom_type = _bottom_type;
2937
2938 n_shift->add_req(n_region, n_sub_base);
2939 n_shift->_opnds[0] = op_dst;
2940 n_shift->_opnds[1] = op_dst;
2941 n_shift->_bottom_type = _bottom_type;
2942
2943 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2944 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2945 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2946 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2947
2948 nodes->push(n_move);
2949 nodes->push(n_compare);
2950 nodes->push(n_sub_base);
2951 nodes->push(n_shift);
2952 }
2953
2954 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2955 %}
2956
2957 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2958
2959 encodeP_subNode *n1 = new (C) encodeP_subNode();
2960 n1->add_req(n_region, n_src);
2961 n1->_opnds[0] = op_dst;
2962 n1->_opnds[1] = op_src;
2963 n1->_bottom_type = _bottom_type;
2964
2965 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
2966 n2->add_req(n_region, n1);
2967 n2->_opnds[0] = op_dst;
2968 n2->_opnds[1] = op_dst;
2969 n2->_bottom_type = _bottom_type;
2970 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2971 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2972
2973 nodes->push(n1);
2974 nodes->push(n2);
2975 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2976 %}
2977
2978 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2979 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
2980 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
2981
2982 n_compare->add_req(n_region, n_src);
2983 n_compare->_opnds[0] = op_crx;
2984 n_compare->_opnds[1] = op_src;
2985 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
2986
2987 n_shift->add_req(n_region, n_src);
2988 n_shift->_opnds[0] = op_dst;
2989 n_shift->_opnds[1] = op_src;
2990 n_shift->_bottom_type = _bottom_type;
2991
2992 if (VM_Version::has_isel()) {
2993 // use isel instruction with Power 7
2994
2995 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
2996 n_add_base->add_req(n_region, n_shift);
2997 n_add_base->_opnds[0] = op_dst;
2998 n_add_base->_opnds[1] = op_dst;
2999 n_add_base->_bottom_type = _bottom_type;
3000
3001 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3002 n_cond_set->add_req(n_region, n_compare, n_add_base);
3003 n_cond_set->_opnds[0] = op_dst;
3004 n_cond_set->_opnds[1] = op_crx;
3005 n_cond_set->_opnds[2] = op_dst;
3006 n_cond_set->_bottom_type = _bottom_type;
3007
3008 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3009 ra_->set_oop(n_cond_set, true);
3010
3011 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3012 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3013 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3014 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3015
3016 nodes->push(n_compare);
3017 nodes->push(n_shift);
3018 nodes->push(n_add_base);
3019 nodes->push(n_cond_set);
3020
3021 } else {
3022 // before Power 7
3023 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3024
3025 n_add_base->add_req(n_region, n_compare, n_shift);
3026 n_add_base->_opnds[0] = op_dst;
3027 n_add_base->_opnds[1] = op_crx;
3028 n_add_base->_opnds[2] = op_dst;
3029 n_add_base->_bottom_type = _bottom_type;
3030
3031 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3032 ra_->set_oop(n_add_base, true);
3033
3034 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3035 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3036 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3037
3038 nodes->push(n_compare);
3039 nodes->push(n_shift);
3040 nodes->push(n_add_base);
3041 }
3042 %}
3043
3044 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3045 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3046 n1->add_req(n_region, n_src);
3047 n1->_opnds[0] = op_dst;
3048 n1->_opnds[1] = op_src;
3049 n1->_bottom_type = _bottom_type;
3050
3051 decodeN_addNode *n2 = new (C) decodeN_addNode();
3052 n2->add_req(n_region, n1);
3053 n2->_opnds[0] = op_dst;
3054 n2->_opnds[1] = op_dst;
3055 n2->_bottom_type = _bottom_type;
3056 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3057 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3058
3059 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3060 ra_->set_oop(n2, true);
3061
3062 nodes->push(n1);
3063 nodes->push(n2);
3064 %}
3065
3066 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3067 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3068
3069 MacroAssembler _masm(&cbuf);
3070 int cc = $cmp$$cmpcode;
3071 int flags_reg = $crx$$reg;
3072 Label done;
3073 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3074 // Branch if not (cmp crx).
3075 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3076 __ mr($dst$$Register, $src$$Register);
3077 // TODO PPC port __ endgroup_if_needed(_size == 12);
3078 __ bind(done);
3079 %}
3080
3081 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3082 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3083
3084 MacroAssembler _masm(&cbuf);
3085 Label done;
3086 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3087 // Branch if not (cmp crx).
3088 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3089 __ li($dst$$Register, $src$$constant);
3090 // TODO PPC port __ endgroup_if_needed(_size == 12);
3091 __ bind(done);
3092 %}
3093
3094 // New atomics.
3095 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3096 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3097
3098 MacroAssembler _masm(&cbuf);
3099 Register Rtmp = R0;
3100 Register Rres = $res$$Register;
3101 Register Rsrc = $src$$Register;
3102 Register Rptr = $mem_ptr$$Register;
3103 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3104 Register Rold = RegCollision ? Rtmp : Rres;
3105
3106 Label Lretry;
3107 __ bind(Lretry);
3108 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3109 __ add(Rtmp, Rsrc, Rold);
3110 __ stwcx_(Rtmp, Rptr);
3111 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3112 __ bne_predict_not_taken(CCR0, Lretry);
3113 } else {
3114 __ bne( CCR0, Lretry);
3115 }
3116 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3117 __ fence();
3118 %}
3119
3120 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3121 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3122
3123 MacroAssembler _masm(&cbuf);
3124 Register Rtmp = R0;
3125 Register Rres = $res$$Register;
3126 Register Rsrc = $src$$Register;
3127 Register Rptr = $mem_ptr$$Register;
3128 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3129 Register Rold = RegCollision ? Rtmp : Rres;
3130
3131 Label Lretry;
3132 __ bind(Lretry);
3133 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3134 __ add(Rtmp, Rsrc, Rold);
3135 __ stdcx_(Rtmp, Rptr);
3136 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3137 __ bne_predict_not_taken(CCR0, Lretry);
3138 } else {
3139 __ bne( CCR0, Lretry);
3140 }
3141 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3142 __ fence();
3143 %}
3144
3145 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3146 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3147
3148 MacroAssembler _masm(&cbuf);
3149 Register Rtmp = R0;
3150 Register Rres = $res$$Register;
3151 Register Rsrc = $src$$Register;
3152 Register Rptr = $mem_ptr$$Register;
3153 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3154 Register Rold = RegCollision ? Rtmp : Rres;
3155
3156 Label Lretry;
3157 __ bind(Lretry);
3158 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3159 __ stwcx_(Rsrc, Rptr);
3160 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3161 __ bne_predict_not_taken(CCR0, Lretry);
3162 } else {
3163 __ bne( CCR0, Lretry);
3164 }
3165 if (RegCollision) __ mr(Rres, Rtmp);
3166 __ fence();
3167 %}
3168
3169 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3170 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3171
3172 MacroAssembler _masm(&cbuf);
3173 Register Rtmp = R0;
3174 Register Rres = $res$$Register;
3175 Register Rsrc = $src$$Register;
3176 Register Rptr = $mem_ptr$$Register;
3177 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3178 Register Rold = RegCollision ? Rtmp : Rres;
3179
3180 Label Lretry;
3181 __ bind(Lretry);
3182 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3183 __ stdcx_(Rsrc, Rptr);
3184 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3185 __ bne_predict_not_taken(CCR0, Lretry);
3186 } else {
3187 __ bne( CCR0, Lretry);
3188 }
3189 if (RegCollision) __ mr(Rres, Rtmp);
3190 __ fence();
3191 %}
3192
3193 // This enc_class is needed so that scheduler gets proper
3194 // input mapping for latency computation.
3195 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3196 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3197 MacroAssembler _masm(&cbuf);
3198 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3199 %}
3200
3201 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3202 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3203
3204 MacroAssembler _masm(&cbuf);
3205
3206 Label done;
3207 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3208 __ li($dst$$Register, $zero$$constant);
3209 __ beq($crx$$CondRegister, done);
3210 __ li($dst$$Register, $notzero$$constant);
3211 __ bind(done);
3212 %}
3213
3214 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3215 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3216
3217 MacroAssembler _masm(&cbuf);
3218
3219 Label done;
3220 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3221 __ li($dst$$Register, $zero$$constant);
3222 __ beq($crx$$CondRegister, done);
3223 __ li($dst$$Register, $notzero$$constant);
3224 __ bind(done);
3225 %}
3226
3227 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3228 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3229
3230 MacroAssembler _masm(&cbuf);
3231 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3232 Label done;
3233 __ bso($crx$$CondRegister, done);
3234 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3235 // TODO PPC port __ endgroup_if_needed(_size == 12);
3236 __ bind(done);
3237 %}
3238
3239 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3240 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3241
3242 MacroAssembler _masm(&cbuf);
3243 Label d; // dummy
3244 __ bind(d);
3245 Label* p = ($lbl$$label);
3246 // `p' is `NULL' when this encoding class is used only to
3247 // determine the size of the encoded instruction.
3248 Label& l = (NULL == p)? d : *(p);
3249 int cc = $cmp$$cmpcode;
3250 int flags_reg = $crx$$reg;
3251 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3252 int bhint = Assembler::bhintNoHint;
3253
3254 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3255 if (_prob <= PROB_NEVER) {
3256 bhint = Assembler::bhintIsNotTaken;
3257 } else if (_prob >= PROB_ALWAYS) {
3258 bhint = Assembler::bhintIsTaken;
3259 }
3260 }
3261
3262 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3263 cc_to_biint(cc, flags_reg),
3264 l);
3265 %}
3266
3267 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3268 // The scheduler doesn't know about branch shortening, so we set the opcode
3269 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3270 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3271
3272 MacroAssembler _masm(&cbuf);
3273 Label d; // dummy
3274 __ bind(d);
3275 Label* p = ($lbl$$label);
3276 // `p' is `NULL' when this encoding class is used only to
3277 // determine the size of the encoded instruction.
3278 Label& l = (NULL == p)? d : *(p);
3279 int cc = $cmp$$cmpcode;
3280 int flags_reg = $crx$$reg;
3281 int bhint = Assembler::bhintNoHint;
3282
3283 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3284 if (_prob <= PROB_NEVER) {
3285 bhint = Assembler::bhintIsNotTaken;
3286 } else if (_prob >= PROB_ALWAYS) {
3287 bhint = Assembler::bhintIsTaken;
3288 }
3289 }
3290
3291 // Tell the conditional far branch to optimize itself when being relocated.
3292 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3293 cc_to_biint(cc, flags_reg),
3294 l,
3295 MacroAssembler::bc_far_optimize_on_relocate);
3296 %}
3297
3298 // Branch used with Power6 scheduling (can be shortened without changing the node).
3299 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3300 // The scheduler doesn't know about branch shortening, so we set the opcode
3301 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3302 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3303
3304 MacroAssembler _masm(&cbuf);
3305 Label d; // dummy
3306 __ bind(d);
3307 Label* p = ($lbl$$label);
3308 // `p' is `NULL' when this encoding class is used only to
3309 // determine the size of the encoded instruction.
3310 Label& l = (NULL == p)? d : *(p);
3311 int cc = $cmp$$cmpcode;
3312 int flags_reg = $crx$$reg;
3313 int bhint = Assembler::bhintNoHint;
3314
3315 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3316 if (_prob <= PROB_NEVER) {
3317 bhint = Assembler::bhintIsNotTaken;
3318 } else if (_prob >= PROB_ALWAYS) {
3319 bhint = Assembler::bhintIsTaken;
3320 }
3321 }
3322
3323 #if 0 // TODO: PPC port
3324 if (_size == 8) {
3325 // Tell the conditional far branch to optimize itself when being relocated.
3326 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3327 cc_to_biint(cc, flags_reg),
3328 l,
3329 MacroAssembler::bc_far_optimize_on_relocate);
3330 } else {
3331 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3332 cc_to_biint(cc, flags_reg),
3333 l);
3334 }
3335 #endif
3336 Unimplemented();
3337 %}
3338
3339 // Postalloc expand emitter for loading a replicatef float constant from
3340 // the method's TOC.
3341 // Enc_class needed as consttanttablebase is not supported by postalloc
3342 // expand.
3343 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3344 // Create new nodes.
3345
3346 // Make an operand with the bit pattern to load as float.
3347 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3348
3349 loadConLNodesTuple loadConLNodes =
3350 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3351 ra_->get_reg_second(this), ra_->get_reg_first(this));
3352
3353 // Push new nodes.
3354 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3355 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3356
3357 assert(nodes->length() >= 1, "must have created at least 1 node");
3358 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3359 %}
3360
3361 // This enc_class is needed so that scheduler gets proper
3362 // input mapping for latency computation.
3363 enc_class enc_poll(immI dst, iRegLdst poll) %{
3364 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3365 // Fake operand dst needed for PPC scheduler.
3366 assert($dst$$constant == 0x0, "dst must be 0x0");
3367
3368 MacroAssembler _masm(&cbuf);
3369 // Mark the code position where the load from the safepoint
3370 // polling page was emitted as relocInfo::poll_type.
3371 __ relocate(relocInfo::poll_type);
3372 __ load_from_polling_page($poll$$Register);
3373 %}
3374
3375 // A Java static call or a runtime call.
3376 //
3377 // Branch-and-link relative to a trampoline.
3378 // The trampoline loads the target address and does a long branch to there.
3379 // In case we call java, the trampoline branches to a interpreter_stub
3380 // which loads the inline cache and the real call target from the constant pool.
3381 //
3382 // This basically looks like this:
3383 //
3384 // >>>> consts -+ -+
3385 // | |- offset1
3386 // [call target1] | <-+
3387 // [IC cache] |- offset2
3388 // [call target2] <--+
3389 //
3390 // <<<< consts
3391 // >>>> insts
3392 //
3393 // bl offset16 -+ -+ ??? // How many bits available?
3394 // | |
3395 // <<<< insts | |
3396 // >>>> stubs | |
3397 // | |- trampoline_stub_Reloc
3398 // trampoline stub: | <-+
3399 // r2 = toc |
3400 // r2 = [r2 + offset1] | // Load call target1 from const section
3401 // mtctr r2 |
3402 // bctr |- static_stub_Reloc
3403 // comp_to_interp_stub: <---+
3404 // r1 = toc
3405 // ICreg = [r1 + IC_offset] // Load IC from const section
3406 // r1 = [r1 + offset2] // Load call target2 from const section
3407 // mtctr r1
3408 // bctr
3409 //
3410 // <<<< stubs
3411 //
3412 // The call instruction in the code either
3413 // - Branches directly to a compiled method if the offset is encodable in instruction.
3414 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3415 // - Branches to the compiled_to_interp stub if the target is interpreted.
3416 //
3417 // Further there are three relocations from the loads to the constants in
3418 // the constant section.
3419 //
3420 // Usage of r1 and r2 in the stubs allows to distinguish them.
3421 enc_class enc_java_static_call(method meth) %{
3422 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3423
3424 MacroAssembler _masm(&cbuf);
3425 address entry_point = (address)$meth$$method;
3426
3427 if (!_method) {
3428 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3429 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3430 } else {
3431 // Remember the offset not the address.
3432 const int start_offset = __ offset();
3433 // The trampoline stub.
3434 if (!Compile::current()->in_scratch_emit_size()) {
3435 // No entry point given, use the current pc.
3436 // Make sure branch fits into
3437 if (entry_point == 0) entry_point = __ pc();
3438
3439 // Put the entry point as a constant into the constant pool.
3440 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3441 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3442
3443 // Emit the trampoline stub which will be related to the branch-and-link below.
3444 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3445 __ relocate(_optimized_virtual ?
3446 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3447 }
3448
3449 // The real call.
3450 // Note: At this point we do not have the address of the trampoline
3451 // stub, and the entry point might be too far away for bl, so __ pc()
3452 // serves as dummy and the bl will be patched later.
3453 cbuf.set_insts_mark();
3454 __ bl(__ pc()); // Emits a relocation.
3455
3456 // The stub for call to interpreter.
3457 CompiledStaticCall::emit_to_interp_stub(cbuf);
3458 }
3459 %}
3460
3461 // Emit a method handle call.
3462 //
3463 // Method handle calls from compiled to compiled are going thru a
3464 // c2i -> i2c adapter, extending the frame for their arguments. The
3465 // caller however, returns directly to the compiled callee, that has
3466 // to cope with the extended frame. We restore the original frame by
3467 // loading the callers sp and adding the calculated framesize.
3468 enc_class enc_java_handle_call(method meth) %{
3469 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3470
3471 MacroAssembler _masm(&cbuf);
3472 address entry_point = (address)$meth$$method;
3473
3474 // Remember the offset not the address.
3475 const int start_offset = __ offset();
3476 // The trampoline stub.
3477 if (!ra_->C->in_scratch_emit_size()) {
3478 // No entry point given, use the current pc.
3479 // Make sure branch fits into
3480 if (entry_point == 0) entry_point = __ pc();
3481
3482 // Put the entry point as a constant into the constant pool.
3483 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3484 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3485
3486 // Emit the trampoline stub which will be related to the branch-and-link below.
3487 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3488 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3489 __ relocate(relocInfo::opt_virtual_call_type);
3490 }
3491
3492 // The real call.
3493 // Note: At this point we do not have the address of the trampoline
3494 // stub, and the entry point might be too far away for bl, so __ pc()
3495 // serves as dummy and the bl will be patched later.
3496 cbuf.set_insts_mark();
3497 __ bl(__ pc()); // Emits a relocation.
3498
3499 assert(_method, "execute next statement conditionally");
3500 // The stub for call to interpreter.
3501 CompiledStaticCall::emit_to_interp_stub(cbuf);
3502
3503 // Restore original sp.
3504 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3505 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3506 unsigned int bytes = (unsigned int)framesize;
3507 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3508 if (Assembler::is_simm(-offset, 16)) {
3509 __ addi(R1_SP, R11_scratch1, -offset);
3510 } else {
3511 __ load_const_optimized(R12_scratch2, -offset);
3512 __ add(R1_SP, R11_scratch1, R12_scratch2);
3513 }
3514 #ifdef ASSERT
3515 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3516 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3517 __ asm_assert_eq("backlink changed", 0x8000);
3518 #endif
3519 // If fails should store backlink before unextending.
3520
3521 if (ra_->C->env()->failing())
3522 return;
3523 %}
3524
3525 // Second node of expanded dynamic call - the call.
3526 enc_class enc_java_dynamic_call_sched(method meth) %{
3527 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3528
3529 MacroAssembler _masm(&cbuf);
3530
3531 if (!ra_->C->in_scratch_emit_size()) {
3532 // Create a call trampoline stub for the given method.
3533 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3534 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3535 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3536 emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3537
3538 if (ra_->C->env()->failing())
3539 return;
3540
3541 // Build relocation at call site with ic position as data.
3542 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3543 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3544 "must have one, but can't have both");
3545 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3546 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3547 "must contain instruction offset");
3548 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3549 ? _load_ic_hi_node->_cbuf_insts_offset
3550 : _load_ic_node->_cbuf_insts_offset;
3551 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3552 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3553 "should be load from TOC");
3554
3555 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3556 }
3557
3558 // At this point I do not have the address of the trampoline stub,
3559 // and the entry point might be too far away for bl. Pc() serves
3560 // as dummy and bl will be patched later.
3561 __ bl((address) __ pc());
3562 %}
3563
3564 // postalloc expand emitter for virtual calls.
3565 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3566
3567 // Create the nodes for loading the IC from the TOC.
3568 loadConLNodesTuple loadConLNodes_IC =
3569 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3570 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3571
3572 // Create the call node.
3573 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3574 call->_method_handle_invoke = _method_handle_invoke;
3575 call->_vtable_index = _vtable_index;
3576 call->_method = _method;
3577 call->_bci = _bci;
3578 call->_optimized_virtual = _optimized_virtual;
3579 call->_tf = _tf;
3580 call->_entry_point = _entry_point;
3581 call->_cnt = _cnt;
3582 call->_argsize = _argsize;
3583 call->_oop_map = _oop_map;
3584 call->_jvms = _jvms;
3585 call->_jvmadj = _jvmadj;
3586 call->_in_rms = _in_rms;
3587 call->_nesting = _nesting;
3588
3589 // New call needs all inputs of old call.
3590 // Req...
3591 for (uint i = 0; i < req(); ++i) {
3592 // The expanded node does not need toc any more.
3593 // Add the inline cache constant here instead. This expresses the
3594 // register of the inline cache must be live at the call.
3595 // Else we would have to adapt JVMState by -1.
3596 if (i == mach_constant_base_node_input()) {
3597 call->add_req(loadConLNodes_IC._last);
3598 } else {
3599 call->add_req(in(i));
3600 }
3601 }
3602 // ...as well as prec
3603 for (uint i = req(); i < len(); ++i) {
3604 call->add_prec(in(i));
3605 }
3606
3607 // Remember nodes loading the inline cache into r19.
3608 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3609 call->_load_ic_node = loadConLNodes_IC._small;
3610
3611 // Operands for new nodes.
3612 call->_opnds[0] = _opnds[0];
3613 call->_opnds[1] = _opnds[1];
3614
3615 // Only the inline cache is associated with a register.
3616 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3617
3618 // Push new nodes.
3619 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3620 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3621 nodes->push(call);
3622 %}
3623
3624 // Compound version of call dynamic
3625 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3626 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3627 MacroAssembler _masm(&cbuf);
3628 int start_offset = __ offset();
3629
3630 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3631 #if 0
3632 if (_vtable_index < 0) {
3633 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3634 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3635 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3636 AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word());
3637
3638 address virtual_call_meta_addr = __ pc();
3639 __ load_const_from_method_toc(ic_reg, meta, Rtoc);
3640 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3641 // to determine who we intended to call.
3642 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3643 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3644 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3645 "Fix constant in ret_addr_offset()");
3646 } else {
3647 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3648 // Go thru the vtable. Get receiver klass. Receiver already
3649 // checked for non-null. If we'll go thru a C2I adapter, the
3650 // interpreter expects method in R19_method.
3651
3652 __ load_klass(R11_scratch1, R3);
3653
3654 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3655 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3656 __ li(R19_method, v_off);
3657 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3658 // NOTE: for vtable dispatches, the vtable entry will never be
3659 // null. However it may very well end up in handle_wrong_method
3660 // if the method is abstract for the particular class.
3661 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3662 // Call target. Either compiled code or C2I adapter.
3663 __ mtctr(R11_scratch1);
3664 __ bctrl();
3665 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3666 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3667 }
3668 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3669 "Fix constant in ret_addr_offset()");
3670 }
3671 #endif
3672 guarantee(0, "Fix handling of toc edge: messes up derived/base pairs.");
3673 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3674 %}
3675
3676 // a runtime call
3677 enc_class enc_java_to_runtime_call (method meth) %{
3678 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3679
3680 MacroAssembler _masm(&cbuf);
3681 const address start_pc = __ pc();
3682
3683 // The function we're going to call.
3684 FunctionDescriptor fdtemp;
3685 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3686
3687 Register Rtoc = R12_scratch2;
3688 // Calculate the method's TOC.
3689 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3690 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3691 // pool entries; call_c_using_toc will optimize the call.
3692 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3693
3694 // Check the ret_addr_offset.
3695 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3696 "Fix constant in ret_addr_offset()");
3697 %}
3698
3699 // Move to ctr for leaf call.
3700 // This enc_class is needed so that scheduler gets proper
3701 // input mapping for latency computation.
3702 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3703 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3704 MacroAssembler _masm(&cbuf);
3705 __ mtctr($src$$Register);
3706 %}
3707
3708 // postalloc expand emitter for runtime leaf calls.
3709 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3710 // Get the struct that describes the function we are about to call.
3711 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3712 assert(fd, "need fd here");
3713 // new nodes
3714 loadConLNodesTuple loadConLNodes_Entry;
3715 loadConLNodesTuple loadConLNodes_Env;
3716 loadConLNodesTuple loadConLNodes_Toc;
3717 MachNode *mtctr = NULL;
3718 MachCallLeafNode *call = NULL;
3719
3720 // Create nodes and operands for loading the entry point.
3721 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->entry()),
3722 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3723
3724
3725 // Create nodes and operands for loading the env pointer.
3726 if (fd->env() != NULL) {
3727 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3728 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3729 } else {
3730 loadConLNodes_Env._large_hi = NULL;
3731 loadConLNodes_Env._large_lo = NULL;
3732 loadConLNodes_Env._small = NULL;
3733 loadConLNodes_Env._last = new (C) loadConL16Node();
3734 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3735 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3736 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3737 }
3738
3739 // Create nodes and operands for loading the Toc point.
3740 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3741 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3742 // mtctr node
3743 mtctr = new (C) CallLeafDirect_mtctrNode();
3744
3745 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3746 mtctr->add_req(0, loadConLNodes_Entry._last);
3747
3748 mtctr->_opnds[0] = new (C) iRegLdstOper();
3749 mtctr->_opnds[1] = new (C) iRegLdstOper();
3750
3751 // call node
3752 call = new (C) CallLeafDirectNode();
3753
3754 call->_opnds[0] = _opnds[0];
3755 call->_opnds[1] = new (C) methodOper((intptr_t) fd->entry()); // may get set later
3756
3757 // Make the new call node look like the old one.
3758 call->_name = _name;
3759 call->_tf = _tf;
3760 call->_entry_point = _entry_point;
3761 call->_cnt = _cnt;
3762 call->_argsize = _argsize;
3763 call->_oop_map = _oop_map;
3764 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3765 call->_jvms = NULL;
3766 call->_jvmadj = _jvmadj;
3767 call->_in_rms = _in_rms;
3768 call->_nesting = _nesting;
3769
3770
3771 // New call needs all inputs of old call.
3772 // Req...
3773 for (uint i = 0; i < req(); ++i) {
3774 if (i != mach_constant_base_node_input()) {
3775 call->add_req(in(i));
3776 }
3777 }
3778
3779 // These must be reqired edges, as the registers are live up to
3780 // the call. Else the constants are handled as kills.
3781 call->add_req(mtctr);
3782 call->add_req(loadConLNodes_Env._last);
3783 call->add_req(loadConLNodes_Toc._last);
3784
3785 // ...as well as prec
3786 for (uint i = req(); i < len(); ++i) {
3787 call->add_prec(in(i));
3788 }
3789
3790 // registers
3791 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3792
3793 // Insert the new nodes.
3794 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3795 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3796 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3797 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3798 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3799 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3800 nodes->push(mtctr);
3801 nodes->push(call);
3802 %}
3803 %}
3804
3805 //----------FRAME--------------------------------------------------------------
3806 // Definition of frame structure and management information.
3807
3808 frame %{
3809 // What direction does stack grow in (assumed to be same for native & Java).
3810 stack_direction(TOWARDS_LOW);
3811
3812 // These two registers define part of the calling convention between
3813 // compiled code and the interpreter.
3814
3815 // Inline Cache Register or method for I2C.
3816 inline_cache_reg(R19); // R19_method
3817
3818 // Method Oop Register when calling interpreter.
3819 interpreter_method_oop_reg(R19); // R19_method
3820
3821 // Optional: name the operand used by cisc-spilling to access
3822 // [stack_pointer + offset].
3823 cisc_spilling_operand_name(indOffset);
3824
3825 // Number of stack slots consumed by a Monitor enter.
3826 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3827
3828 // Compiled code's Frame Pointer.
3829 frame_pointer(R1); // R1_SP
3830
3831 // Interpreter stores its frame pointer in a register which is
3832 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3833 // interpreted java to compiled java.
3834 //
3835 // R14_state holds pointer to caller's cInterpreter.
3836 interpreter_frame_pointer(R14); // R14_state
3837
3838 stack_alignment(frame::alignment_in_bytes);
3839
3840 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3841
3842 // Number of outgoing stack slots killed above the
3843 // out_preserve_stack_slots for calls to C. Supports the var-args
3844 // backing area for register parms.
3845 //
3846 varargs_C_out_slots_killed(((frame::abi_112_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3847
3848 // The after-PROLOG location of the return address. Location of
3849 // return address specifies a type (REG or STACK) and a number
3850 // representing the register number (i.e. - use a register name) or
3851 // stack slot.
3852 //
3853 // A: Link register is stored in stack slot ...
3854 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3855 // J: Therefore, we make sure that the link register is also in R11_scratch1
3856 // at the end of the prolog.
3857 // B: We use R20, now.
3858 //return_addr(REG R20);
3859
3860 // G: After reading the comments made by all the luminaries on their
3861 // failure to tell the compiler where the return address really is,
3862 // I hardly dare to try myself. However, I'm convinced it's in slot
3863 // 4 what apparently works and saves us some spills.
3864 return_addr(STACK 4);
3865
3866 // This is the body of the function
3867 //
3868 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3869 // uint length, // length of array
3870 // bool is_outgoing)
3871 //
3872 // The `sig' array is to be updated. sig[j] represents the location
3873 // of the j-th argument, either a register or a stack slot.
3874
3875 // Comment taken from i486.ad:
3876 // Body of function which returns an integer array locating
3877 // arguments either in registers or in stack slots. Passed an array
3878 // of ideal registers called "sig" and a "length" count. Stack-slot
3879 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3880 // arguments for a CALLEE. Incoming stack arguments are
3881 // automatically biased by the preserve_stack_slots field above.
3882 calling_convention %{
3883 // No difference between ingoing/outgoing. Just pass false.
3884 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3885 %}
3886
3887 // Comment taken from i486.ad:
3888 // Body of function which returns an integer array locating
3889 // arguments either in registers or in stack slots. Passed an array
3890 // of ideal registers called "sig" and a "length" count. Stack-slot
3891 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3892 // arguments for a CALLEE. Incoming stack arguments are
3893 // automatically biased by the preserve_stack_slots field above.
3894 c_calling_convention %{
3895 // This is obviously always outgoing.
3896 // C argument in register AND stack slot.
3897 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3898 %}
3899
3900 // Location of native (C/C++) and interpreter return values. This
3901 // is specified to be the same as Java. In the 32-bit VM, long
3902 // values are actually returned from native calls in O0:O1 and
3903 // returned to the interpreter in I0:I1. The copying to and from
3904 // the register pairs is done by the appropriate call and epilog
3905 // opcodes. This simplifies the register allocator.
3906 c_return_value %{
3907 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3908 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3909 "only return normal values");
3910 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3911 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3912 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3913 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3914 %}
3915
3916 // Location of compiled Java return values. Same as C
3917 return_value %{
3918 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3919 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3920 "only return normal values");
3921 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3922 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3923 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3924 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3925 %}
3926 %}
3927
3928
3929 //----------ATTRIBUTES---------------------------------------------------------
3930
3931 //----------Operand Attributes-------------------------------------------------
3932 op_attrib op_cost(1); // Required cost attribute.
3933
3934 //----------Instruction Attributes---------------------------------------------
3935
3936 // Cost attribute. required.
3937 ins_attrib ins_cost(DEFAULT_COST);
3938
3939 // Is this instruction a non-matching short branch variant of some
3940 // long branch? Not required.
3941 ins_attrib ins_short_branch(0);
3942
3943 // This instruction does implicit checks at the given machine-instruction offset
3944 // (optional attribute).
3945 ins_attrib ins_implicit_check_offset(-1); // TODO: PPC port
3946
3947 ins_attrib ins_implicit_check_follows_matched_true_path(true);
3948 ins_attrib ins_is_TrapBasedCheckNode(true);
3949
3950 // Number of constants.
3951 // This instruction uses the given number of constants
3952 // (optional attribute).
3953 // This is needed to determine in time whether the constant pool will
3954 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3955 // is determined. It's also used to compute the constant pool size
3956 // in Output().
3957 ins_attrib ins_num_consts(0);
3958
3959 // Required alignment attribute (must be a power of 2) specifies the
3960 // alignment that some part of the instruction (not necessarily the
3961 // start) requires. If > 1, a compute_padding() function must be
3962 // provided for the instruction.
3963 ins_attrib ins_alignment(1);
3964
3965 // Enforce/prohibit rematerializations.
3966 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3967 // then rematerialization of that instruction is prohibited and the
3968 // instruction's value will be spilled if necessary.
3969 // Causes that MachNode::rematerialize() returns false.
3970 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3971 // then rematerialization should be enforced and a copy of the instruction
3972 // should be inserted if possible; rematerialization is not guaranteed.
3973 // Note: this may result in rematerializations in front of every use.
3974 // Causes that MachNode::rematerialize() can return true.
3975 // (optional attribute)
3976 ins_attrib ins_cannot_rematerialize(false);
3977 ins_attrib ins_should_rematerialize(false);
3978
3979 // Instruction has variable size depending on alignment.
3980 ins_attrib ins_variable_size_depending_on_alignment(false);
3981
3982 // Instruction is a nop.
3983 ins_attrib ins_is_nop(false);
3984
3985 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3986 ins_attrib ins_use_mach_if_fast_lock_node(false);
3987
3988 // Field for the toc offset of a constant.
3989 //
3990 // This is needed if the toc offset is not encodable as an immediate in
3991 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3992 // added to the toc, and from this a load with immediate is performed.
3993 // With postalloc expand, we get two nodes that require the same offset
3994 // but which don't know about each other. The offset is only known
3995 // when the constant is added to the constant pool during emitting.
3996 // It is generated in the 'hi'-node adding the upper bits, and saved
3997 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3998 // the offset from there when it gets encoded.
3999 ins_attrib ins_field_const_toc_offset(0);
4000 ins_attrib ins_field_const_toc_offset_hi_node(0);
4001
4002 // A field that can hold the instructions offset in the code buffer.
4003 // Set in the nodes emitter.
4004 ins_attrib ins_field_cbuf_insts_offset(-1);
4005
4006 // Fields for referencing a call's load-IC-node.
4007 // If the toc offset can not be encoded as an immediate in a load, we
4008 // use two nodes.
4009 ins_attrib ins_field_load_ic_hi_node(0);
4010 ins_attrib ins_field_load_ic_node(0);
4011
4012 //----------OPERANDS-----------------------------------------------------------
4013 // Operand definitions must precede instruction definitions for correct
4014 // parsing in the ADLC because operands constitute user defined types
4015 // which are used in instruction definitions.
4016 //
4017 // Formats are generated automatically for constants and base registers.
4018
4019 //----------Simple Operands----------------------------------------------------
4020 // Immediate Operands
4021
4022 // Integer Immediate: 32-bit
4023 operand immI() %{
4024 match(ConI);
4025 op_cost(40);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4029
4030 operand immI8() %{
4031 predicate(Assembler::is_simm(n->get_int(), 8));
4032 op_cost(0);
4033 match(ConI);
4034 format %{ %}
4035 interface(CONST_INTER);
4036 %}
4037
4038 // Integer Immediate: 16-bit
4039 operand immI16() %{
4040 predicate(Assembler::is_simm(n->get_int(), 16));
4041 op_cost(0);
4042 match(ConI);
4043 format %{ %}
4044 interface(CONST_INTER);
4045 %}
4046
4047 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4048 operand immIhi16() %{
4049 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4050 match(ConI);
4051 op_cost(0);
4052 format %{ %}
4053 interface(CONST_INTER);
4054 %}
4055
4056 operand immInegpow2() %{
4057 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4058 match(ConI);
4059 op_cost(0);
4060 format %{ %}
4061 interface(CONST_INTER);
4062 %}
4063
4064 operand immIpow2minus1() %{
4065 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4066 match(ConI);
4067 op_cost(0);
4068 format %{ %}
4069 interface(CONST_INTER);
4070 %}
4071
4072 operand immIpowerOf2() %{
4073 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4074 match(ConI);
4075 op_cost(0);
4076 format %{ %}
4077 interface(CONST_INTER);
4078 %}
4079
4080 // Unsigned Integer Immediate: the values 0-31
4081 operand uimmI5() %{
4082 predicate(Assembler::is_uimm(n->get_int(), 5));
4083 match(ConI);
4084 op_cost(0);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4088
4089 // Unsigned Integer Immediate: 6-bit
4090 operand uimmI6() %{
4091 predicate(Assembler::is_uimm(n->get_int(), 6));
4092 match(ConI);
4093 op_cost(0);
4094 format %{ %}
4095 interface(CONST_INTER);
4096 %}
4097
4098 // Unsigned Integer Immediate: 6-bit int, greater than 32
4099 operand uimmI6_ge32() %{
4100 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4101 match(ConI);
4102 op_cost(0);
4103 format %{ %}
4104 interface(CONST_INTER);
4105 %}
4106
4107 // Unsigned Integer Immediate: 15-bit
4108 operand uimmI15() %{
4109 predicate(Assembler::is_uimm(n->get_int(), 15));
4110 match(ConI);
4111 op_cost(0);
4112 format %{ %}
4113 interface(CONST_INTER);
4114 %}
4115
4116 // Unsigned Integer Immediate: 16-bit
4117 operand uimmI16() %{
4118 predicate(Assembler::is_uimm(n->get_int(), 16));
4119 match(ConI);
4120 op_cost(0);
4121 format %{ %}
4122 interface(CONST_INTER);
4123 %}
4124
4125 // constant 'int 0'.
4126 operand immI_0() %{
4127 predicate(n->get_int() == 0);
4128 match(ConI);
4129 op_cost(0);
4130 format %{ %}
4131 interface(CONST_INTER);
4132 %}
4133
4134 // constant 'int 1'.
4135 operand immI_1() %{
4136 predicate(n->get_int() == 1);
4137 match(ConI);
4138 op_cost(0);
4139 format %{ %}
4140 interface(CONST_INTER);
4141 %}
4142
4143 // constant 'int -1'.
4144 operand immI_minus1() %{
4145 predicate(n->get_int() == -1);
4146 match(ConI);
4147 op_cost(0);
4148 format %{ %}
4149 interface(CONST_INTER);
4150 %}
4151
4152 // int value 16.
4153 operand immI_16() %{
4154 predicate(n->get_int() == 16);
4155 match(ConI);
4156 op_cost(0);
4157 format %{ %}
4158 interface(CONST_INTER);
4159 %}
4160
4161 // int value 24.
4162 operand immI_24() %{
4163 predicate(n->get_int() == 24);
4164 match(ConI);
4165 op_cost(0);
4166 format %{ %}
4167 interface(CONST_INTER);
4168 %}
4169
4170 // Compressed oops constants
4171 // Pointer Immediate
4172 operand immN() %{
4173 match(ConN);
4174
4175 op_cost(10);
4176 format %{ %}
4177 interface(CONST_INTER);
4178 %}
4179
4180 // NULL Pointer Immediate
4181 operand immN_0() %{
4182 predicate(n->get_narrowcon() == 0);
4183 match(ConN);
4184
4185 op_cost(0);
4186 format %{ %}
4187 interface(CONST_INTER);
4188 %}
4189
4190 // Compressed klass constants
4191 operand immNKlass() %{
4192 match(ConNKlass);
4193
4194 op_cost(0);
4195 format %{ %}
4196 interface(CONST_INTER);
4197 %}
4198
4199 // This operand can be used to avoid matching of an instruct
4200 // with chain rule.
4201 operand immNKlass_NM() %{
4202 match(ConNKlass);
4203 predicate(false);
4204 op_cost(0);
4205 format %{ %}
4206 interface(CONST_INTER);
4207 %}
4208
4209 // Pointer Immediate: 64-bit
4210 operand immP() %{
4211 match(ConP);
4212 op_cost(0);
4213 format %{ %}
4214 interface(CONST_INTER);
4215 %}
4216
4217 // Operand to avoid match of loadConP.
4218 // This operand can be used to avoid matching of an instruct
4219 // with chain rule.
4220 operand immP_NM() %{
4221 match(ConP);
4222 predicate(false);
4223 op_cost(0);
4224 format %{ %}
4225 interface(CONST_INTER);
4226 %}
4227
4228 // costant 'pointer 0'.
4229 operand immP_0() %{
4230 predicate(n->get_ptr() == 0);
4231 match(ConP);
4232 op_cost(0);
4233 format %{ %}
4234 interface(CONST_INTER);
4235 %}
4236
4237 // pointer 0x0 or 0x1
4238 operand immP_0or1() %{
4239 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4240 match(ConP);
4241 op_cost(0);
4242 format %{ %}
4243 interface(CONST_INTER);
4244 %}
4245
4246 operand immL() %{
4247 match(ConL);
4248 op_cost(40);
4249 format %{ %}
4250 interface(CONST_INTER);
4251 %}
4252
4253 // Long Immediate: 16-bit
4254 operand immL16() %{
4255 predicate(Assembler::is_simm(n->get_long(), 16));
4256 match(ConL);
4257 op_cost(0);
4258 format %{ %}
4259 interface(CONST_INTER);
4260 %}
4261
4262 // Long Immediate: 16-bit, 4-aligned
4263 operand immL16Alg4() %{
4264 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4265 match(ConL);
4266 op_cost(0);
4267 format %{ %}
4268 interface(CONST_INTER);
4269 %}
4270
4271 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4272 operand immL32hi16() %{
4273 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4274 match(ConL);
4275 op_cost(0);
4276 format %{ %}
4277 interface(CONST_INTER);
4278 %}
4279
4280 // Long Immediate: 32-bit
4281 operand immL32() %{
4282 predicate(Assembler::is_simm(n->get_long(), 32));
4283 match(ConL);
4284 op_cost(0);
4285 format %{ %}
4286 interface(CONST_INTER);
4287 %}
4288
4289 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4290 operand immLhighest16() %{
4291 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4292 match(ConL);
4293 op_cost(0);
4294 format %{ %}
4295 interface(CONST_INTER);
4296 %}
4297
4298 operand immLnegpow2() %{
4299 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4300 match(ConL);
4301 op_cost(0);
4302 format %{ %}
4303 interface(CONST_INTER);
4304 %}
4305
4306 operand immLpow2minus1() %{
4307 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4308 (n->get_long() != (jlong)0xffffffffffffffffL));
4309 match(ConL);
4310 op_cost(0);
4311 format %{ %}
4312 interface(CONST_INTER);
4313 %}
4314
4315 // constant 'long 0'.
4316 operand immL_0() %{
4317 predicate(n->get_long() == 0L);
4318 match(ConL);
4319 op_cost(0);
4320 format %{ %}
4321 interface(CONST_INTER);
4322 %}
4323
4324 // constat ' long -1'.
4325 operand immL_minus1() %{
4326 predicate(n->get_long() == -1L);
4327 match(ConL);
4328 op_cost(0);
4329 format %{ %}
4330 interface(CONST_INTER);
4331 %}
4332
4333 // Long Immediate: low 32-bit mask
4334 operand immL_32bits() %{
4335 predicate(n->get_long() == 0xFFFFFFFFL);
4336 match(ConL);
4337 op_cost(0);
4338 format %{ %}
4339 interface(CONST_INTER);
4340 %}
4341
4342 // Unsigned Long Immediate: 16-bit
4343 operand uimmL16() %{
4344 predicate(Assembler::is_uimm(n->get_long(), 16));
4345 match(ConL);
4346 op_cost(0);
4347 format %{ %}
4348 interface(CONST_INTER);
4349 %}
4350
4351 // Float Immediate
4352 operand immF() %{
4353 match(ConF);
4354 op_cost(40);
4355 format %{ %}
4356 interface(CONST_INTER);
4357 %}
4358
4359 // constant 'float +0.0'.
4360 operand immF_0() %{
4361 predicate((n->getf() == 0) &&
4362 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4363 match(ConF);
4364 op_cost(0);
4365 format %{ %}
4366 interface(CONST_INTER);
4367 %}
4368
4369 // Double Immediate
4370 operand immD() %{
4371 match(ConD);
4372 op_cost(40);
4373 format %{ %}
4374 interface(CONST_INTER);
4375 %}
4376
4377 // Integer Register Operands
4378 // Integer Destination Register
4379 // See definition of reg_class bits32_reg_rw.
4380 operand iRegIdst() %{
4381 constraint(ALLOC_IN_RC(bits32_reg_rw));
4382 match(RegI);
4383 match(rscratch1RegI);
4384 match(rscratch2RegI);
4385 match(rarg1RegI);
4386 match(rarg2RegI);
4387 match(rarg3RegI);
4388 match(rarg4RegI);
4389 format %{ %}
4390 interface(REG_INTER);
4391 %}
4392
4393 // Integer Source Register
4394 // See definition of reg_class bits32_reg_ro.
4395 operand iRegIsrc() %{
4396 constraint(ALLOC_IN_RC(bits32_reg_ro));
4397 match(RegI);
4398 match(rscratch1RegI);
4399 match(rscratch2RegI);
4400 match(rarg1RegI);
4401 match(rarg2RegI);
4402 match(rarg3RegI);
4403 match(rarg4RegI);
4404 format %{ %}
4405 interface(REG_INTER);
4406 %}
4407
4408 operand rscratch1RegI() %{
4409 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4410 match(iRegIdst);
4411 format %{ %}
4412 interface(REG_INTER);
4413 %}
4414
4415 operand rscratch2RegI() %{
4416 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4417 match(iRegIdst);
4418 format %{ %}
4419 interface(REG_INTER);
4420 %}
4421
4422 operand rarg1RegI() %{
4423 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4424 match(iRegIdst);
4425 format %{ %}
4426 interface(REG_INTER);
4427 %}
4428
4429 operand rarg2RegI() %{
4430 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4431 match(iRegIdst);
4432 format %{ %}
4433 interface(REG_INTER);
4434 %}
4435
4436 operand rarg3RegI() %{
4437 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4438 match(iRegIdst);
4439 format %{ %}
4440 interface(REG_INTER);
4441 %}
4442
4443 operand rarg4RegI() %{
4444 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4445 match(iRegIdst);
4446 format %{ %}
4447 interface(REG_INTER);
4448 %}
4449
4450 operand rarg1RegL() %{
4451 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4452 match(iRegLdst);
4453 format %{ %}
4454 interface(REG_INTER);
4455 %}
4456
4457 operand rarg2RegL() %{
4458 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4459 match(iRegLdst);
4460 format %{ %}
4461 interface(REG_INTER);
4462 %}
4463
4464 operand rarg3RegL() %{
4465 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4466 match(iRegLdst);
4467 format %{ %}
4468 interface(REG_INTER);
4469 %}
4470
4471 operand rarg4RegL() %{
4472 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4473 match(iRegLdst);
4474 format %{ %}
4475 interface(REG_INTER);
4476 %}
4477
4478 // Pointer Destination Register
4479 // See definition of reg_class bits64_reg_rw.
4480 operand iRegPdst() %{
4481 constraint(ALLOC_IN_RC(bits64_reg_rw));
4482 match(RegP);
4483 match(rscratch1RegP);
4484 match(rscratch2RegP);
4485 match(rarg1RegP);
4486 match(rarg2RegP);
4487 match(rarg3RegP);
4488 match(rarg4RegP);
4489 format %{ %}
4490 interface(REG_INTER);
4491 %}
4492
4493 // Pointer Destination Register
4494 // Operand not using r11 and r12 (killed in epilog).
4495 operand iRegPdstNoScratch() %{
4496 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4497 match(RegP);
4498 match(rarg1RegP);
4499 match(rarg2RegP);
4500 match(rarg3RegP);
4501 match(rarg4RegP);
4502 format %{ %}
4503 interface(REG_INTER);
4504 %}
4505
4506 // Pointer Source Register
4507 // See definition of reg_class bits64_reg_ro.
4508 operand iRegPsrc() %{
4509 constraint(ALLOC_IN_RC(bits64_reg_ro));
4510 match(RegP);
4511 match(iRegPdst);
4512 match(rscratch1RegP);
4513 match(rscratch2RegP);
4514 match(rarg1RegP);
4515 match(rarg2RegP);
4516 match(rarg3RegP);
4517 match(rarg4RegP);
4518 match(threadRegP);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4522
4523 // Thread operand.
4524 operand threadRegP() %{
4525 constraint(ALLOC_IN_RC(thread_bits64_reg));
4526 match(iRegPdst);
4527 format %{ "R16" %}
4528 interface(REG_INTER);
4529 %}
4530
4531 operand rscratch1RegP() %{
4532 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4533 match(iRegPdst);
4534 format %{ "R11" %}
4535 interface(REG_INTER);
4536 %}
4537
4538 operand rscratch2RegP() %{
4539 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4540 match(iRegPdst);
4541 format %{ %}
4542 interface(REG_INTER);
4543 %}
4544
4545 operand rarg1RegP() %{
4546 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4547 match(iRegPdst);
4548 format %{ %}
4549 interface(REG_INTER);
4550 %}
4551
4552 operand rarg2RegP() %{
4553 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4554 match(iRegPdst);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4558
4559 operand rarg3RegP() %{
4560 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4561 match(iRegPdst);
4562 format %{ %}
4563 interface(REG_INTER);
4564 %}
4565
4566 operand rarg4RegP() %{
4567 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4568 match(iRegPdst);
4569 format %{ %}
4570 interface(REG_INTER);
4571 %}
4572
4573 operand iRegNsrc() %{
4574 constraint(ALLOC_IN_RC(bits32_reg_ro));
4575 match(RegN);
4576 match(iRegNdst);
4577
4578 format %{ %}
4579 interface(REG_INTER);
4580 %}
4581
4582 operand iRegNdst() %{
4583 constraint(ALLOC_IN_RC(bits32_reg_rw));
4584 match(RegN);
4585
4586 format %{ %}
4587 interface(REG_INTER);
4588 %}
4589
4590 // Long Destination Register
4591 // See definition of reg_class bits64_reg_rw.
4592 operand iRegLdst() %{
4593 constraint(ALLOC_IN_RC(bits64_reg_rw));
4594 match(RegL);
4595 match(rscratch1RegL);
4596 match(rscratch2RegL);
4597 format %{ %}
4598 interface(REG_INTER);
4599 %}
4600
4601 // Long Source Register
4602 // See definition of reg_class bits64_reg_ro.
4603 operand iRegLsrc() %{
4604 constraint(ALLOC_IN_RC(bits64_reg_ro));
4605 match(RegL);
4606 match(iRegLdst);
4607 match(rscratch1RegL);
4608 match(rscratch2RegL);
4609 format %{ %}
4610 interface(REG_INTER);
4611 %}
4612
4613 // Special operand for ConvL2I.
4614 operand iRegL2Isrc(iRegLsrc reg) %{
4615 constraint(ALLOC_IN_RC(bits64_reg_ro));
4616 match(ConvL2I reg);
4617 format %{ "ConvL2I($reg)" %}
4618 interface(REG_INTER)
4619 %}
4620
4621 operand rscratch1RegL() %{
4622 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4623 match(RegL);
4624 format %{ %}
4625 interface(REG_INTER);
4626 %}
4627
4628 operand rscratch2RegL() %{
4629 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4630 match(RegL);
4631 format %{ %}
4632 interface(REG_INTER);
4633 %}
4634
4635 // Condition Code Flag Registers
4636 operand flagsReg() %{
4637 constraint(ALLOC_IN_RC(int_flags));
4638 match(RegFlags);
4639 format %{ %}
4640 interface(REG_INTER);
4641 %}
4642
4643 // Condition Code Flag Register CR0
4644 operand flagsRegCR0() %{
4645 constraint(ALLOC_IN_RC(int_flags_CR0));
4646 match(RegFlags);
4647 format %{ "CR0" %}
4648 interface(REG_INTER);
4649 %}
4650
4651 operand flagsRegCR1() %{
4652 constraint(ALLOC_IN_RC(int_flags_CR1));
4653 match(RegFlags);
4654 format %{ "CR1" %}
4655 interface(REG_INTER);
4656 %}
4657
4658 operand flagsRegCR6() %{
4659 constraint(ALLOC_IN_RC(int_flags_CR6));
4660 match(RegFlags);
4661 format %{ "CR6" %}
4662 interface(REG_INTER);
4663 %}
4664
4665 operand regCTR() %{
4666 constraint(ALLOC_IN_RC(ctr_reg));
4667 // RegFlags should work. Introducing a RegSpecial type would cause a
4668 // lot of changes.
4669 match(RegFlags);
4670 format %{"SR_CTR" %}
4671 interface(REG_INTER);
4672 %}
4673
4674 operand regD() %{
4675 constraint(ALLOC_IN_RC(dbl_reg));
4676 match(RegD);
4677 format %{ %}
4678 interface(REG_INTER);
4679 %}
4680
4681 operand regF() %{
4682 constraint(ALLOC_IN_RC(flt_reg));
4683 match(RegF);
4684 format %{ %}
4685 interface(REG_INTER);
4686 %}
4687
4688 // Special Registers
4689
4690 // Method Register
4691 operand inline_cache_regP(iRegPdst reg) %{
4692 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4693 match(reg);
4694 format %{ %}
4695 interface(REG_INTER);
4696 %}
4697
4698 operand compiler_method_oop_regP(iRegPdst reg) %{
4699 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4700 match(reg);
4701 format %{ %}
4702 interface(REG_INTER);
4703 %}
4704
4705 operand interpreter_method_oop_regP(iRegPdst reg) %{
4706 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4707 match(reg);
4708 format %{ %}
4709 interface(REG_INTER);
4710 %}
4711
4712 // Operands to remove register moves in unscaled mode.
4713 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4714 operand iRegP2N(iRegPsrc reg) %{
4715 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4716 constraint(ALLOC_IN_RC(bits64_reg_ro));
4717 match(EncodeP reg);
4718 format %{ "$reg" %}
4719 interface(REG_INTER)
4720 %}
4721
4722 operand iRegN2P(iRegNsrc reg) %{
4723 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4724 constraint(ALLOC_IN_RC(bits32_reg_ro));
4725 match(DecodeN reg);
4726 match(DecodeNKlass reg);
4727 format %{ "$reg" %}
4728 interface(REG_INTER)
4729 %}
4730
4731 //----------Complex Operands---------------------------------------------------
4732 // Indirect Memory Reference
4733 operand indirect(iRegPsrc reg) %{
4734 constraint(ALLOC_IN_RC(bits64_reg_ro));
4735 match(reg);
4736 op_cost(100);
4737 format %{ "[$reg]" %}
4738 interface(MEMORY_INTER) %{
4739 base($reg);
4740 index(0x0);
4741 scale(0x0);
4742 disp(0x0);
4743 %}
4744 %}
4745
4746 // Indirect with Offset
4747 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4748 constraint(ALLOC_IN_RC(bits64_reg_ro));
4749 match(AddP reg offset);
4750 op_cost(100);
4751 format %{ "[$reg + $offset]" %}
4752 interface(MEMORY_INTER) %{
4753 base($reg);
4754 index(0x0);
4755 scale(0x0);
4756 disp($offset);
4757 %}
4758 %}
4759
4760 // Indirect with 4-aligned Offset
4761 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4762 constraint(ALLOC_IN_RC(bits64_reg_ro));
4763 match(AddP reg offset);
4764 op_cost(100);
4765 format %{ "[$reg + $offset]" %}
4766 interface(MEMORY_INTER) %{
4767 base($reg);
4768 index(0x0);
4769 scale(0x0);
4770 disp($offset);
4771 %}
4772 %}
4773
4774 //----------Complex Operands for Compressed OOPs-------------------------------
4775 // Compressed OOPs with narrow_oop_shift == 0.
4776
4777 // Indirect Memory Reference, compressed OOP
4778 operand indirectNarrow(iRegNsrc reg) %{
4779 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4780 constraint(ALLOC_IN_RC(bits64_reg_ro));
4781 match(DecodeN reg);
4782 match(DecodeNKlass reg);
4783 op_cost(100);
4784 format %{ "[$reg]" %}
4785 interface(MEMORY_INTER) %{
4786 base($reg);
4787 index(0x0);
4788 scale(0x0);
4789 disp(0x0);
4790 %}
4791 %}
4792
4793 // Indirect with Offset, compressed OOP
4794 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4795 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4796 constraint(ALLOC_IN_RC(bits64_reg_ro));
4797 match(AddP (DecodeN reg) offset);
4798 match(AddP (DecodeNKlass reg) offset);
4799 op_cost(100);
4800 format %{ "[$reg + $offset]" %}
4801 interface(MEMORY_INTER) %{
4802 base($reg);
4803 index(0x0);
4804 scale(0x0);
4805 disp($offset);
4806 %}
4807 %}
4808
4809 // Indirect with 4-aligned Offset, compressed OOP
4810 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4811 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4812 constraint(ALLOC_IN_RC(bits64_reg_ro));
4813 match(AddP (DecodeN reg) offset);
4814 match(AddP (DecodeNKlass reg) offset);
4815 op_cost(100);
4816 format %{ "[$reg + $offset]" %}
4817 interface(MEMORY_INTER) %{
4818 base($reg);
4819 index(0x0);
4820 scale(0x0);
4821 disp($offset);
4822 %}
4823 %}
4824
4825 //----------Special Memory Operands--------------------------------------------
4826 // Stack Slot Operand
4827 //
4828 // This operand is used for loading and storing temporary values on
4829 // the stack where a match requires a value to flow through memory.
4830 operand stackSlotI(sRegI reg) %{
4831 constraint(ALLOC_IN_RC(stack_slots));
4832 op_cost(100);
4833 //match(RegI);
4834 format %{ "[sp+$reg]" %}
4835 interface(MEMORY_INTER) %{
4836 base(0x1); // R1_SP
4837 index(0x0);
4838 scale(0x0);
4839 disp($reg); // Stack Offset
4840 %}
4841 %}
4842
4843 operand stackSlotL(sRegL reg) %{
4844 constraint(ALLOC_IN_RC(stack_slots));
4845 op_cost(100);
4846 //match(RegL);
4847 format %{ "[sp+$reg]" %}
4848 interface(MEMORY_INTER) %{
4849 base(0x1); // R1_SP
4850 index(0x0);
4851 scale(0x0);
4852 disp($reg); // Stack Offset
4853 %}
4854 %}
4855
4856 operand stackSlotP(sRegP reg) %{
4857 constraint(ALLOC_IN_RC(stack_slots));
4858 op_cost(100);
4859 //match(RegP);
4860 format %{ "[sp+$reg]" %}
4861 interface(MEMORY_INTER) %{
4862 base(0x1); // R1_SP
4863 index(0x0);
4864 scale(0x0);
4865 disp($reg); // Stack Offset
4866 %}
4867 %}
4868
4869 operand stackSlotF(sRegF reg) %{
4870 constraint(ALLOC_IN_RC(stack_slots));
4871 op_cost(100);
4872 //match(RegF);
4873 format %{ "[sp+$reg]" %}
4874 interface(MEMORY_INTER) %{
4875 base(0x1); // R1_SP
4876 index(0x0);
4877 scale(0x0);
4878 disp($reg); // Stack Offset
4879 %}
4880 %}
4881
4882 operand stackSlotD(sRegD reg) %{
4883 constraint(ALLOC_IN_RC(stack_slots));
4884 op_cost(100);
4885 //match(RegD);
4886 format %{ "[sp+$reg]" %}
4887 interface(MEMORY_INTER) %{
4888 base(0x1); // R1_SP
4889 index(0x0);
4890 scale(0x0);
4891 disp($reg); // Stack Offset
4892 %}
4893 %}
4894
4895 // Operands for expressing Control Flow
4896 // NOTE: Label is a predefined operand which should not be redefined in
4897 // the AD file. It is generically handled within the ADLC.
4898
4899 //----------Conditional Branch Operands----------------------------------------
4900 // Comparison Op
4901 //
4902 // This is the operation of the comparison, and is limited to the
4903 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4904 // (!=).
4905 //
4906 // Other attributes of the comparison, such as unsignedness, are specified
4907 // by the comparison instruction that sets a condition code flags register.
4908 // That result is represented by a flags operand whose subtype is appropriate
4909 // to the unsignedness (etc.) of the comparison.
4910 //
4911 // Later, the instruction which matches both the Comparison Op (a Bool) and
4912 // the flags (produced by the Cmp) specifies the coding of the comparison op
4913 // by matching a specific subtype of Bool operand below.
4914
4915 // When used for floating point comparisons: unordered same as less.
4916 operand cmpOp() %{
4917 match(Bool);
4918 format %{ "" %}
4919 interface(COND_INTER) %{
4920 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4921 // BO & BI
4922 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4923 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4924 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4925 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4926 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4927 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4928 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4929 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4930 %}
4931 %}
4932
4933 //----------OPERAND CLASSES----------------------------------------------------
4934 // Operand Classes are groups of operands that are used to simplify
4935 // instruction definitions by not requiring the AD writer to specify
4936 // seperate instructions for every form of operand when the
4937 // instruction accepts multiple operand types with the same basic
4938 // encoding and format. The classic case of this is memory operands.
4939 // Indirect is not included since its use is limited to Compare & Swap.
4940
4941 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4942 // Memory operand where offsets are 4-aligned. Required for ld, std.
4943 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
4944 opclass indirectMemory(indirect, indirectNarrow);
4945
4946 // Special opclass for I and ConvL2I.
4947 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4948
4949 // Operand classes to match encode and decode. iRegN_P2N is only used
4950 // for storeN. I have never seen an encode node elsewhere.
4951 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4952 opclass iRegP_N2P(iRegPsrc, iRegN2P);
4953
4954 //----------PIPELINE-----------------------------------------------------------
4955
4956 pipeline %{
4957
4958 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4959 // J. Res. & Dev., No. 1, Jan. 2002.
4960
4961 //----------ATTRIBUTES---------------------------------------------------------
4962 attributes %{
4963
4964 // Power4 instructions are of fixed length.
4965 fixed_size_instructions;
4966
4967 // TODO: if `bundle' means number of instructions fetched
4968 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4969 // max instructions issued per cycle, this is 5.
4970 max_instructions_per_bundle = 8;
4971
4972 // A Power4 instruction is 4 bytes long.
4973 instruction_unit_size = 4;
4974
4975 // The Power4 processor fetches 64 bytes...
4976 instruction_fetch_unit_size = 64;
4977
4978 // ...in one line
4979 instruction_fetch_units = 1
4980
4981 // Unused, list one so that array generated by adlc is not empty.
4982 // Aix compiler chokes if _nop_count = 0.
4983 nops(fxNop);
4984 %}
4985
4986 //----------RESOURCES----------------------------------------------------------
4987 // Resources are the functional units available to the machine
4988 resources(
4989 PPC_BR, // branch unit
4990 PPC_CR, // condition unit
4991 PPC_FX1, // integer arithmetic unit 1
4992 PPC_FX2, // integer arithmetic unit 2
4993 PPC_LDST1, // load/store unit 1
4994 PPC_LDST2, // load/store unit 2
4995 PPC_FP1, // float arithmetic unit 1
4996 PPC_FP2, // float arithmetic unit 2
4997 PPC_LDST = PPC_LDST1 | PPC_LDST2,
4998 PPC_FX = PPC_FX1 | PPC_FX2,
4999 PPC_FP = PPC_FP1 | PPC_FP2
5000 );
5001
5002 //----------PIPELINE DESCRIPTION-----------------------------------------------
5003 // Pipeline Description specifies the stages in the machine's pipeline
5004 pipe_desc(
5005 // Power4 longest pipeline path
5006 PPC_IF, // instruction fetch
5007 PPC_IC,
5008 //PPC_BP, // branch prediction
5009 PPC_D0, // decode
5010 PPC_D1, // decode
5011 PPC_D2, // decode
5012 PPC_D3, // decode
5013 PPC_Xfer1,
5014 PPC_GD, // group definition
5015 PPC_MP, // map
5016 PPC_ISS, // issue
5017 PPC_RF, // resource fetch
5018 PPC_EX1, // execute (all units)
5019 PPC_EX2, // execute (FP, LDST)
5020 PPC_EX3, // execute (FP, LDST)
5021 PPC_EX4, // execute (FP)
5022 PPC_EX5, // execute (FP)
5023 PPC_EX6, // execute (FP)
5024 PPC_WB, // write back
5025 PPC_Xfer2,
5026 PPC_CP
5027 );
5028
5029 //----------PIPELINE CLASSES---------------------------------------------------
5030 // Pipeline Classes describe the stages in which input and output are
5031 // referenced by the hardware pipeline.
5032
5033 // Simple pipeline classes.
5034
5035 // Default pipeline class.
5036 pipe_class pipe_class_default() %{
5037 single_instruction;
5038 fixed_latency(2);
5039 %}
5040
5041 // Pipeline class for empty instructions.
5042 pipe_class pipe_class_empty() %{
5043 single_instruction;
5044 fixed_latency(0);
5045 %}
5046
5047 // Pipeline class for compares.
5048 pipe_class pipe_class_compare() %{
5049 single_instruction;
5050 fixed_latency(16);
5051 %}
5052
5053 // Pipeline class for traps.
5054 pipe_class pipe_class_trap() %{
5055 single_instruction;
5056 fixed_latency(100);
5057 %}
5058
5059 // Pipeline class for memory operations.
5060 pipe_class pipe_class_memory() %{
5061 single_instruction;
5062 fixed_latency(16);
5063 %}
5064
5065 // Pipeline class for call.
5066 pipe_class pipe_class_call() %{
5067 single_instruction;
5068 fixed_latency(100);
5069 %}
5070
5071 // Define the class for the Nop node.
5072 define %{
5073 MachNop = pipe_class_default;
5074 %}
5075
5076 %}
5077
5078 //----------INSTRUCTIONS-------------------------------------------------------
5079
5080 // Naming of instructions:
5081 // opA_operB / opA_operB_operC:
5082 // Operation 'op' with one or two source operands 'oper'. Result
5083 // type is A, source operand types are B and C.
5084 // Iff A == B == C, B and C are left out.
5085 //
5086 // The instructions are ordered according to the following scheme:
5087 // - loads
5088 // - load constants
5089 // - prefetch
5090 // - store
5091 // - encode/decode
5092 // - membar
5093 // - conditional moves
5094 // - compare & swap
5095 // - arithmetic and logic operations
5096 // * int: Add, Sub, Mul, Div, Mod
5097 // * int: lShift, arShift, urShift, rot
5098 // * float: Add, Sub, Mul, Div
5099 // * and, or, xor ...
5100 // - register moves: float <-> int, reg <-> stack, repl
5101 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5102 // - conv (low level type cast requiring bit changes (sign extend etc)
5103 // - compares, range & zero checks.
5104 // - branches
5105 // - complex operations, intrinsics, min, max, replicate
5106 // - lock
5107 // - Calls
5108 //
5109 // If there are similar instructions with different types they are sorted:
5110 // int before float
5111 // small before big
5112 // signed before unsigned
5113 // e.g., loadS before loadUS before loadI before loadF.
5114
5115
5116 //----------Load/Store Instructions--------------------------------------------
5117
5118 //----------Load Instructions--------------------------------------------------
5119
5120 // Converts byte to int.
5121 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5122 // reuses the 'amount' operand, but adlc expects that operand specification
5123 // and operands in match rule are equivalent.
5124 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5125 effect(DEF dst, USE src);
5126 format %{ "EXTSB $dst, $src \t// byte->int" %}
5127 size(4);
5128 ins_encode %{
5129 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5130 __ extsb($dst$$Register, $src$$Register);
5131 %}
5132 ins_pipe(pipe_class_default);
5133 %}
5134
5135 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5136 // match-rule, false predicate
5137 match(Set dst (LoadB mem));
5138 predicate(false);
5139
5140 format %{ "LBZ $dst, $mem" %}
5141 size(4);
5142 ins_encode( enc_lbz(dst, mem) );
5143 ins_pipe(pipe_class_memory);
5144 %}
5145
5146 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5147 // match-rule, false predicate
5148 match(Set dst (LoadB mem));
5149 predicate(false);
5150
5151 format %{ "LBZ $dst, $mem\n\t"
5152 "TWI $dst\n\t"
5153 "ISYNC" %}
5154 size(12);
5155 ins_encode( enc_lbz_ac(dst, mem) );
5156 ins_pipe(pipe_class_memory);
5157 %}
5158
5159 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5160 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5161 match(Set dst (LoadB mem));
5162 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5163 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5164 expand %{
5165 iRegIdst tmp;
5166 loadUB_indirect(tmp, mem);
5167 convB2I_reg_2(dst, tmp);
5168 %}
5169 %}
5170
5171 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5172 match(Set dst (LoadB mem));
5173 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5174 expand %{
5175 iRegIdst tmp;
5176 loadUB_indirect_ac(tmp, mem);
5177 convB2I_reg_2(dst, tmp);
5178 %}
5179 %}
5180
5181 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5182 // match-rule, false predicate
5183 match(Set dst (LoadB mem));
5184 predicate(false);
5185
5186 format %{ "LBZ $dst, $mem" %}
5187 size(4);
5188 ins_encode( enc_lbz(dst, mem) );
5189 ins_pipe(pipe_class_memory);
5190 %}
5191
5192 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5193 // match-rule, false predicate
5194 match(Set dst (LoadB mem));
5195 predicate(false);
5196
5197 format %{ "LBZ $dst, $mem\n\t"
5198 "TWI $dst\n\t"
5199 "ISYNC" %}
5200 size(12);
5201 ins_encode( enc_lbz_ac(dst, mem) );
5202 ins_pipe(pipe_class_memory);
5203 %}
5204
5205 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5206 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5207 match(Set dst (LoadB mem));
5208 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5209 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5210
5211 expand %{
5212 iRegIdst tmp;
5213 loadUB_indOffset16(tmp, mem);
5214 convB2I_reg_2(dst, tmp);
5215 %}
5216 %}
5217
5218 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5219 match(Set dst (LoadB mem));
5220 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5221
5222 expand %{
5223 iRegIdst tmp;
5224 loadUB_indOffset16_ac(tmp, mem);
5225 convB2I_reg_2(dst, tmp);
5226 %}
5227 %}
5228
5229 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5230 instruct loadUB(iRegIdst dst, memory mem) %{
5231 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5232 match(Set dst (LoadUB mem));
5233 ins_cost(MEMORY_REF_COST);
5234
5235 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5236 size(4);
5237 ins_encode( enc_lbz(dst, mem) );
5238 ins_pipe(pipe_class_memory);
5239 %}
5240
5241 // Load Unsigned Byte (8bit UNsigned) acquire.
5242 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5243 match(Set dst (LoadUB mem));
5244 ins_cost(3*MEMORY_REF_COST);
5245
5246 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5247 "TWI $dst\n\t"
5248 "ISYNC" %}
5249 size(12);
5250 ins_encode( enc_lbz_ac(dst, mem) );
5251 ins_pipe(pipe_class_memory);
5252 %}
5253
5254 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5255 instruct loadUB2L(iRegLdst dst, memory mem) %{
5256 match(Set dst (ConvI2L (LoadUB mem)));
5257 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5258 ins_cost(MEMORY_REF_COST);
5259
5260 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5261 size(4);
5262 ins_encode( enc_lbz(dst, mem) );
5263 ins_pipe(pipe_class_memory);
5264 %}
5265
5266 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5267 match(Set dst (ConvI2L (LoadUB mem)));
5268 ins_cost(3*MEMORY_REF_COST);
5269
5270 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5271 "TWI $dst\n\t"
5272 "ISYNC" %}
5273 size(12);
5274 ins_encode( enc_lbz_ac(dst, mem) );
5275 ins_pipe(pipe_class_memory);
5276 %}
5277
5278 // Load Short (16bit signed)
5279 instruct loadS(iRegIdst dst, memory mem) %{
5280 match(Set dst (LoadS mem));
5281 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5282 ins_cost(MEMORY_REF_COST);
5283
5284 format %{ "LHA $dst, $mem" %}
5285 size(4);
5286 ins_encode %{
5287 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5288 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5289 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5290 %}
5291 ins_pipe(pipe_class_memory);
5292 %}
5293
5294 // Load Short (16bit signed) acquire.
5295 instruct loadS_ac(iRegIdst dst, memory mem) %{
5296 match(Set dst (LoadS mem));
5297 ins_cost(3*MEMORY_REF_COST);
5298
5299 format %{ "LHA $dst, $mem\t acquire\n\t"
5300 "TWI $dst\n\t"
5301 "ISYNC" %}
5302 size(12);
5303 ins_encode %{
5304 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5305 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5306 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5307 __ twi_0($dst$$Register);
5308 __ isync();
5309 %}
5310 ins_pipe(pipe_class_memory);
5311 %}
5312
5313 // Load Char (16bit unsigned)
5314 instruct loadUS(iRegIdst dst, memory mem) %{
5315 match(Set dst (LoadUS mem));
5316 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5317 ins_cost(MEMORY_REF_COST);
5318
5319 format %{ "LHZ $dst, $mem" %}
5320 size(4);
5321 ins_encode( enc_lhz(dst, mem) );
5322 ins_pipe(pipe_class_memory);
5323 %}
5324
5325 // Load Char (16bit unsigned) acquire.
5326 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5327 match(Set dst (LoadUS mem));
5328 ins_cost(3*MEMORY_REF_COST);
5329
5330 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5331 "TWI $dst\n\t"
5332 "ISYNC" %}
5333 size(12);
5334 ins_encode( enc_lhz_ac(dst, mem) );
5335 ins_pipe(pipe_class_memory);
5336 %}
5337
5338 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5339 instruct loadUS2L(iRegLdst dst, memory mem) %{
5340 match(Set dst (ConvI2L (LoadUS mem)));
5341 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5342 ins_cost(MEMORY_REF_COST);
5343
5344 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5345 size(4);
5346 ins_encode( enc_lhz(dst, mem) );
5347 ins_pipe(pipe_class_memory);
5348 %}
5349
5350 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5351 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5352 match(Set dst (ConvI2L (LoadUS mem)));
5353 ins_cost(3*MEMORY_REF_COST);
5354
5355 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5356 "TWI $dst\n\t"
5357 "ISYNC" %}
5358 size(12);
5359 ins_encode( enc_lhz_ac(dst, mem) );
5360 ins_pipe(pipe_class_memory);
5361 %}
5362
5363 // Load Integer.
5364 instruct loadI(iRegIdst dst, memory mem) %{
5365 match(Set dst (LoadI mem));
5366 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5367 ins_cost(MEMORY_REF_COST);
5368
5369 format %{ "LWZ $dst, $mem" %}
5370 size(4);
5371 ins_encode( enc_lwz(dst, mem) );
5372 ins_pipe(pipe_class_memory);
5373 %}
5374
5375 // Load Integer acquire.
5376 instruct loadI_ac(iRegIdst dst, memory mem) %{
5377 match(Set dst (LoadI mem));
5378 ins_cost(3*MEMORY_REF_COST);
5379
5380 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5381 "TWI $dst\n\t"
5382 "ISYNC" %}
5383 size(12);
5384 ins_encode( enc_lwz_ac(dst, mem) );
5385 ins_pipe(pipe_class_memory);
5386 %}
5387
5388 // Match loading integer and casting it to unsigned int in
5389 // long register.
5390 // LoadI + ConvI2L + AndL 0xffffffff.
5391 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5392 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5393 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5394 ins_cost(MEMORY_REF_COST);
5395
5396 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5397 size(4);
5398 ins_encode( enc_lwz(dst, mem) );
5399 ins_pipe(pipe_class_memory);
5400 %}
5401
5402 // Match loading integer and casting it to long.
5403 instruct loadI2L(iRegLdst dst, memory mem) %{
5404 match(Set dst (ConvI2L (LoadI mem)));
5405 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5406 ins_cost(MEMORY_REF_COST);
5407
5408 format %{ "LWA $dst, $mem \t// loadI2L" %}
5409 size(4);
5410 ins_encode %{
5411 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5412 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5413 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5414 %}
5415 ins_pipe(pipe_class_memory);
5416 %}
5417
5418 // Match loading integer and casting it to long - acquire.
5419 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5420 match(Set dst (ConvI2L (LoadI mem)));
5421 ins_cost(3*MEMORY_REF_COST);
5422
5423 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5424 "TWI $dst\n\t"
5425 "ISYNC" %}
5426 size(12);
5427 ins_encode %{
5428 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5429 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5430 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5431 __ twi_0($dst$$Register);
5432 __ isync();
5433 %}
5434 ins_pipe(pipe_class_memory);
5435 %}
5436
5437 // Load Long - aligned
5438 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5439 match(Set dst (LoadL mem));
5440 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5441 ins_cost(MEMORY_REF_COST);
5442
5443 format %{ "LD $dst, $mem \t// long" %}
5444 size(4);
5445 ins_encode( enc_ld(dst, mem) );
5446 ins_pipe(pipe_class_memory);
5447 %}
5448
5449 // Load Long - aligned acquire.
5450 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5451 match(Set dst (LoadL mem));
5452 ins_cost(3*MEMORY_REF_COST);
5453
5454 format %{ "LD $dst, $mem \t// long acquire\n\t"
5455 "TWI $dst\n\t"
5456 "ISYNC" %}
5457 size(12);
5458 ins_encode( enc_ld_ac(dst, mem) );
5459 ins_pipe(pipe_class_memory);
5460 %}
5461
5462 // Load Long - UNaligned
5463 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5464 match(Set dst (LoadL_unaligned mem));
5465 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5466 ins_cost(MEMORY_REF_COST);
5467
5468 format %{ "LD $dst, $mem \t// unaligned long" %}
5469 size(4);
5470 ins_encode( enc_ld(dst, mem) );
5471 ins_pipe(pipe_class_memory);
5472 %}
5473
5474 // Load nodes for superwords
5475
5476 // Load Aligned Packed Byte
5477 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5478 predicate(n->as_LoadVector()->memory_size() == 8);
5479 match(Set dst (LoadVector mem));
5480 ins_cost(MEMORY_REF_COST);
5481
5482 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5483 size(4);
5484 ins_encode( enc_ld(dst, mem) );
5485 ins_pipe(pipe_class_memory);
5486 %}
5487
5488 // Load Range, range = array length (=jint)
5489 instruct loadRange(iRegIdst dst, memory mem) %{
5490 match(Set dst (LoadRange mem));
5491 ins_cost(MEMORY_REF_COST);
5492
5493 format %{ "LWZ $dst, $mem \t// range" %}
5494 size(4);
5495 ins_encode( enc_lwz(dst, mem) );
5496 ins_pipe(pipe_class_memory);
5497 %}
5498
5499 // Load Compressed Pointer
5500 instruct loadN(iRegNdst dst, memory mem) %{
5501 match(Set dst (LoadN mem));
5502 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5503 ins_cost(MEMORY_REF_COST);
5504
5505 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5506 size(4);
5507 ins_encode( enc_lwz(dst, mem) );
5508 ins_pipe(pipe_class_memory);
5509 %}
5510
5511 // Load Compressed Pointer acquire.
5512 instruct loadN_ac(iRegNdst dst, memory mem) %{
5513 match(Set dst (LoadN mem));
5514 ins_cost(3*MEMORY_REF_COST);
5515
5516 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5517 "TWI $dst\n\t"
5518 "ISYNC" %}
5519 size(12);
5520 ins_encode( enc_lwz_ac(dst, mem) );
5521 ins_pipe(pipe_class_memory);
5522 %}
5523
5524 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5525 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5526 match(Set dst (DecodeN (LoadN mem)));
5527 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5528 ins_cost(MEMORY_REF_COST);
5529
5530 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5531 size(4);
5532 ins_encode( enc_lwz(dst, mem) );
5533 ins_pipe(pipe_class_memory);
5534 %}
5535
5536 // Load Pointer
5537 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5538 match(Set dst (LoadP mem));
5539 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5540 ins_cost(MEMORY_REF_COST);
5541
5542 format %{ "LD $dst, $mem \t// ptr" %}
5543 size(4);
5544 ins_encode( enc_ld(dst, mem) );
5545 ins_pipe(pipe_class_memory);
5546 %}
5547
5548 // Load Pointer acquire.
5549 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5550 match(Set dst (LoadP mem));
5551 ins_cost(3*MEMORY_REF_COST);
5552
5553 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5554 "TWI $dst\n\t"
5555 "ISYNC" %}
5556 size(12);
5557 ins_encode( enc_ld_ac(dst, mem) );
5558 ins_pipe(pipe_class_memory);
5559 %}
5560
5561 // LoadP + CastP2L
5562 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5563 match(Set dst (CastP2X (LoadP mem)));
5564 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5565 ins_cost(MEMORY_REF_COST);
5566
5567 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5568 size(4);
5569 ins_encode( enc_ld(dst, mem) );
5570 ins_pipe(pipe_class_memory);
5571 %}
5572
5573 // Load compressed klass pointer.
5574 instruct loadNKlass(iRegNdst dst, memory mem) %{
5575 match(Set dst (LoadNKlass mem));
5576 ins_cost(MEMORY_REF_COST);
5577
5578 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5579 size(4);
5580 ins_encode( enc_lwz(dst, mem) );
5581 ins_pipe(pipe_class_memory);
5582 %}
5583
5584 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5585 //// TODO: will narrow_klass_shift ever be 0?
5586 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5587 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5588 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5589 // ins_cost(MEMORY_REF_COST);
5590 //
5591 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5592 // size(4);
5593 // ins_encode( enc_lwz(dst, mem) );
5594 // ins_pipe(pipe_class_memory);
5595 //%}
5596
5597 // Load Klass Pointer
5598 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5599 match(Set dst (LoadKlass mem));
5600 ins_cost(MEMORY_REF_COST);
5601
5602 format %{ "LD $dst, $mem \t// klass ptr" %}
5603 size(4);
5604 ins_encode( enc_ld(dst, mem) );
5605 ins_pipe(pipe_class_memory);
5606 %}
5607
5608 // Load Float
5609 instruct loadF(regF dst, memory mem) %{
5610 match(Set dst (LoadF mem));
5611 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5612 ins_cost(MEMORY_REF_COST);
5613
5614 format %{ "LFS $dst, $mem" %}
5615 size(4);
5616 ins_encode %{
5617 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5618 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5619 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5620 %}
5621 ins_pipe(pipe_class_memory);
5622 %}
5623
5624 // Load Float acquire.
5625 instruct loadF_ac(regF dst, memory mem) %{
5626 match(Set dst (LoadF mem));
5627 ins_cost(3*MEMORY_REF_COST);
5628
5629 format %{ "LFS $dst, $mem \t// acquire\n\t"
5630 "FCMPU cr0, $dst, $dst\n\t"
5631 "BNE cr0, next\n"
5632 "next:\n\t"
5633 "ISYNC" %}
5634 size(16);
5635 ins_encode %{
5636 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5637 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5638 Label next;
5639 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5640 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5641 __ bne(CCR0, next);
5642 __ bind(next);
5643 __ isync();
5644 %}
5645 ins_pipe(pipe_class_memory);
5646 %}
5647
5648 // Load Double - aligned
5649 instruct loadD(regD dst, memory mem) %{
5650 match(Set dst (LoadD mem));
5651 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5652 ins_cost(MEMORY_REF_COST);
5653
5654 format %{ "LFD $dst, $mem" %}
5655 size(4);
5656 ins_encode( enc_lfd(dst, mem) );
5657 ins_pipe(pipe_class_memory);
5658 %}
5659
5660 // Load Double - aligned acquire.
5661 instruct loadD_ac(regD dst, memory mem) %{
5662 match(Set dst (LoadD mem));
5663 ins_cost(3*MEMORY_REF_COST);
5664
5665 format %{ "LFD $dst, $mem \t// acquire\n\t"
5666 "FCMPU cr0, $dst, $dst\n\t"
5667 "BNE cr0, next\n"
5668 "next:\n\t"
5669 "ISYNC" %}
5670 size(16);
5671 ins_encode %{
5672 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5673 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5674 Label next;
5675 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5676 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5677 __ bne(CCR0, next);
5678 __ bind(next);
5679 __ isync();
5680 %}
5681 ins_pipe(pipe_class_memory);
5682 %}
5683
5684 // Load Double - UNaligned
5685 instruct loadD_unaligned(regD dst, memory mem) %{
5686 match(Set dst (LoadD_unaligned mem));
5687 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5688 ins_cost(MEMORY_REF_COST);
5689
5690 format %{ "LFD $dst, $mem" %}
5691 size(4);
5692 ins_encode( enc_lfd(dst, mem) );
5693 ins_pipe(pipe_class_memory);
5694 %}
5695
5696 //----------Constants--------------------------------------------------------
5697
5698 // Load MachConstantTableBase: add hi offset to global toc.
5699 // TODO: Handle hidden register r29 in bundler!
5700 instruct loadToc_hi(iRegLdst dst) %{
5701 effect(DEF dst);
5702 ins_cost(DEFAULT_COST);
5703
5704 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5705 size(4);
5706 ins_encode %{
5707 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5708 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5709 %}
5710 ins_pipe(pipe_class_default);
5711 %}
5712
5713 // Load MachConstantTableBase: add lo offset to global toc.
5714 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5715 effect(DEF dst, USE src);
5716 ins_cost(DEFAULT_COST);
5717
5718 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5719 size(4);
5720 ins_encode %{
5721 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5722 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5723 %}
5724 ins_pipe(pipe_class_default);
5725 %}
5726
5727 // Load 16-bit integer constant 0xssss????
5728 instruct loadConI16(iRegIdst dst, immI16 src) %{
5729 match(Set dst src);
5730
5731 format %{ "LI $dst, $src" %}
5732 size(4);
5733 ins_encode %{
5734 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5735 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5736 %}
5737 ins_pipe(pipe_class_default);
5738 %}
5739
5740 // Load integer constant 0x????0000
5741 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5742 match(Set dst src);
5743 ins_cost(DEFAULT_COST);
5744
5745 format %{ "LIS $dst, $src.hi" %}
5746 size(4);
5747 ins_encode %{
5748 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5749 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5750 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5751 %}
5752 ins_pipe(pipe_class_default);
5753 %}
5754
5755 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5756 // and sign extended), this adds the low 16 bits.
5757 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5758 // no match-rule, false predicate
5759 effect(DEF dst, USE src1, USE src2);
5760 predicate(false);
5761
5762 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5763 size(4);
5764 ins_encode %{
5765 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5766 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5767 %}
5768 ins_pipe(pipe_class_default);
5769 %}
5770
5771 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5772 match(Set dst src);
5773 ins_cost(DEFAULT_COST*2);
5774
5775 expand %{
5776 // Would like to use $src$$constant.
5777 immI16 srcLo %{ _opnds[1]->constant() %}
5778 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5779 immIhi16 srcHi %{ _opnds[1]->constant() %}
5780 iRegIdst tmpI;
5781 loadConIhi16(tmpI, srcHi);
5782 loadConI32_lo16(dst, tmpI, srcLo);
5783 %}
5784 %}
5785
5786 // No constant pool entries required.
5787 instruct loadConL16(iRegLdst dst, immL16 src) %{
5788 match(Set dst src);
5789
5790 format %{ "LI $dst, $src \t// long" %}
5791 size(4);
5792 ins_encode %{
5793 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5794 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5795 %}
5796 ins_pipe(pipe_class_default);
5797 %}
5798
5799 // Load long constant 0xssssssss????0000
5800 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5801 match(Set dst src);
5802 ins_cost(DEFAULT_COST);
5803
5804 format %{ "LIS $dst, $src.hi \t// long" %}
5805 size(4);
5806 ins_encode %{
5807 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5808 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5809 %}
5810 ins_pipe(pipe_class_default);
5811 %}
5812
5813 // To load a 32 bit constant: merge lower 16 bits into already loaded
5814 // high 16 bits.
5815 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5816 // no match-rule, false predicate
5817 effect(DEF dst, USE src1, USE src2);
5818 predicate(false);
5819
5820 format %{ "ORI $dst, $src1, $src2.lo" %}
5821 size(4);
5822 ins_encode %{
5823 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5824 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5825 %}
5826 ins_pipe(pipe_class_default);
5827 %}
5828
5829 // Load 32-bit long constant
5830 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5831 match(Set dst src);
5832 ins_cost(DEFAULT_COST*2);
5833
5834 expand %{
5835 // Would like to use $src$$constant.
5836 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5837 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5838 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5839 iRegLdst tmpL;
5840 loadConL32hi16(tmpL, srcHi);
5841 loadConL32_lo16(dst, tmpL, srcLo);
5842 %}
5843 %}
5844
5845 // Load long constant 0x????000000000000.
5846 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5847 match(Set dst src);
5848 ins_cost(DEFAULT_COST);
5849
5850 expand %{
5851 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5852 immI shift32 %{ 32 %}
5853 iRegLdst tmpL;
5854 loadConL32hi16(tmpL, srcHi);
5855 lshiftL_regL_immI(dst, tmpL, shift32);
5856 %}
5857 %}
5858
5859 // Expand node for constant pool load: small offset.
5860 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5861 effect(DEF dst, USE src, USE toc);
5862 ins_cost(MEMORY_REF_COST);
5863
5864 ins_num_consts(1);
5865 // Needed so that CallDynamicJavaDirect can compute the address of this
5866 // instruction for relocation.
5867 ins_field_cbuf_insts_offset(int);
5868
5869 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5870 size(4);
5871 ins_encode( enc_load_long_constL(dst, src, toc) );
5872 ins_pipe(pipe_class_memory);
5873 %}
5874
5875 // Expand node for constant pool load: large offset.
5876 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5877 effect(DEF dst, USE src, USE toc);
5878 predicate(false);
5879
5880 ins_num_consts(1);
5881 ins_field_const_toc_offset(int);
5882 // Needed so that CallDynamicJavaDirect can compute the address of this
5883 // instruction for relocation.
5884 ins_field_cbuf_insts_offset(int);
5885
5886 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5887 size(4);
5888 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5889 ins_pipe(pipe_class_default);
5890 %}
5891
5892 // Expand node for constant pool load: large offset.
5893 // No constant pool entries required.
5894 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5895 effect(DEF dst, USE src, USE base);
5896 predicate(false);
5897
5898 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5899
5900 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5901 size(4);
5902 ins_encode %{
5903 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5904 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5905 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5906 %}
5907 ins_pipe(pipe_class_memory);
5908 %}
5909
5910 // Load long constant from constant table. Expand in case of
5911 // offset > 16 bit is needed.
5912 // Adlc adds toc node MachConstantTableBase.
5913 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5914 match(Set dst src);
5915 ins_cost(MEMORY_REF_COST);
5916
5917 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5918 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5919 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5920 %}
5921
5922 // Load NULL as compressed oop.
5923 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5924 match(Set dst src);
5925 ins_cost(DEFAULT_COST);
5926
5927 format %{ "LI $dst, $src \t// compressed ptr" %}
5928 size(4);
5929 ins_encode %{
5930 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5931 __ li($dst$$Register, 0);
5932 %}
5933 ins_pipe(pipe_class_default);
5934 %}
5935
5936 // Load hi part of compressed oop constant.
5937 instruct loadConN_hi(iRegNdst dst, immN src) %{
5938 effect(DEF dst, USE src);
5939 ins_cost(DEFAULT_COST);
5940
5941 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5942 size(4);
5943 ins_encode %{
5944 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5945 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5946 %}
5947 ins_pipe(pipe_class_default);
5948 %}
5949
5950 // Add lo part of compressed oop constant to already loaded hi part.
5951 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5952 effect(DEF dst, USE src1, USE src2);
5953 ins_cost(DEFAULT_COST);
5954
5955 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5956 size(4);
5957 ins_encode %{
5958 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5959 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5960 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5961 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5962 __ relocate(rspec, 1);
5963 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5964 %}
5965 ins_pipe(pipe_class_default);
5966 %}
5967
5968 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5969 // leaving the upper 32 bits with sign-extension bits.
5970 // This clears these bits: dst = src & 0xFFFFFFFF.
5971 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5972 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5973 effect(DEF dst, USE src);
5974 predicate(false);
5975
5976 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
5977 size(4);
5978 ins_encode %{
5979 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5980 __ clrldi($dst$$Register, $src$$Register, 0x20);
5981 %}
5982 ins_pipe(pipe_class_default);
5983 %}
5984
5985 // Loading ConN must be postalloc expanded so that edges between
5986 // the nodes are safe. They may not interfere with a safepoint.
5987 // GL TODO: This needs three instructions: better put this into the constant pool.
5988 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5989 match(Set dst src);
5990 ins_cost(DEFAULT_COST*2);
5991
5992 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
5993 postalloc_expand %{
5994 MachNode *m1 = new (C) loadConN_hiNode();
5995 MachNode *m2 = new (C) loadConN_loNode();
5996 MachNode *m3 = new (C) clearMs32bNode();
5997 m1->add_req(NULL);
5998 m2->add_req(NULL, m1);
5999 m3->add_req(NULL, m2);
6000 m1->_opnds[0] = op_dst;
6001 m1->_opnds[1] = op_src;
6002 m2->_opnds[0] = op_dst;
6003 m2->_opnds[1] = op_dst;
6004 m2->_opnds[2] = op_src;
6005 m3->_opnds[0] = op_dst;
6006 m3->_opnds[1] = op_dst;
6007 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6008 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6009 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6010 nodes->push(m1);
6011 nodes->push(m2);
6012 nodes->push(m3);
6013 %}
6014 %}
6015
6016 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6017 effect(DEF dst, USE src);
6018 ins_cost(DEFAULT_COST);
6019
6020 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6021 size(4);
6022 ins_encode %{
6023 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6024 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6025 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6026 %}
6027 ins_pipe(pipe_class_default);
6028 %}
6029
6030 // This needs a match rule so that build_oop_map knows this is
6031 // not a narrow oop.
6032 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6033 match(Set dst src1);
6034 effect(TEMP src2);
6035 ins_cost(DEFAULT_COST);
6036
6037 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6038 size(4);
6039 ins_encode %{
6040 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6041 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6042 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6043 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6044 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6045
6046 __ relocate(rspec, 1);
6047 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6048 %}
6049 ins_pipe(pipe_class_default);
6050 %}
6051
6052 // Loading ConNKlass must be postalloc expanded so that edges between
6053 // the nodes are safe. They may not interfere with a safepoint.
6054 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6055 match(Set dst src);
6056 ins_cost(DEFAULT_COST*2);
6057
6058 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6059 postalloc_expand %{
6060 // Load high bits into register. Sign extended.
6061 MachNode *m1 = new (C) loadConNKlass_hiNode();
6062 m1->add_req(NULL);
6063 m1->_opnds[0] = op_dst;
6064 m1->_opnds[1] = op_src;
6065 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6066 nodes->push(m1);
6067
6068 MachNode *m2 = m1;
6069 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6070 // Value might be 1-extended. Mask out these bits.
6071 m2 = new (C) clearMs32bNode();
6072 m2->add_req(NULL, m1);
6073 m2->_opnds[0] = op_dst;
6074 m2->_opnds[1] = op_dst;
6075 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6076 nodes->push(m2);
6077 }
6078
6079 MachNode *m3 = new (C) loadConNKlass_loNode();
6080 m3->add_req(NULL, m2);
6081 m3->_opnds[0] = op_dst;
6082 m3->_opnds[1] = op_src;
6083 m3->_opnds[2] = op_dst;
6084 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6085 nodes->push(m3);
6086 %}
6087 %}
6088
6089 // 0x1 is used in object initialization (initial object header).
6090 // No constant pool entries required.
6091 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6092 match(Set dst src);
6093
6094 format %{ "LI $dst, $src \t// ptr" %}
6095 size(4);
6096 ins_encode %{
6097 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6098 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6099 %}
6100 ins_pipe(pipe_class_default);
6101 %}
6102
6103 // Expand node for constant pool load: small offset.
6104 // The match rule is needed to generate the correct bottom_type(),
6105 // however this node should never match. The use of predicate is not
6106 // possible since ADLC forbids predicates for chain rules. The higher
6107 // costs do not prevent matching in this case. For that reason the
6108 // operand immP_NM with predicate(false) is used.
6109 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6110 match(Set dst src);
6111 effect(TEMP toc);
6112
6113 ins_num_consts(1);
6114
6115 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6116 size(4);
6117 ins_encode( enc_load_long_constP(dst, src, toc) );
6118 ins_pipe(pipe_class_memory);
6119 %}
6120
6121 // Expand node for constant pool load: large offset.
6122 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6123 effect(DEF dst, USE src, USE toc);
6124 predicate(false);
6125
6126 ins_num_consts(1);
6127 ins_field_const_toc_offset(int);
6128
6129 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6130 size(4);
6131 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6132 ins_pipe(pipe_class_default);
6133 %}
6134
6135 // Expand node for constant pool load: large offset.
6136 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6137 match(Set dst src);
6138 effect(TEMP base);
6139
6140 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6141
6142 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6143 size(4);
6144 ins_encode %{
6145 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6146 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6147 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6148 %}
6149 ins_pipe(pipe_class_memory);
6150 %}
6151
6152 // Load pointer constant from constant table. Expand in case an
6153 // offset > 16 bit is needed.
6154 // Adlc adds toc node MachConstantTableBase.
6155 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6156 match(Set dst src);
6157 ins_cost(MEMORY_REF_COST);
6158
6159 // This rule does not use "expand" because then
6160 // the result type is not known to be an Oop. An ADLC
6161 // enhancement will be needed to make that work - not worth it!
6162
6163 // If this instruction rematerializes, it prolongs the live range
6164 // of the toc node, causing illegal graphs.
6165 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6166 ins_cannot_rematerialize(true);
6167
6168 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6169 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6170 %}
6171
6172 // Expand node for constant pool load: small offset.
6173 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6174 effect(DEF dst, USE src, USE toc);
6175 ins_cost(MEMORY_REF_COST);
6176
6177 ins_num_consts(1);
6178
6179 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6180 size(4);
6181 ins_encode %{
6182 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6183 address float_address = __ float_constant($src$$constant);
6184 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6185 %}
6186 ins_pipe(pipe_class_memory);
6187 %}
6188
6189 // Expand node for constant pool load: large offset.
6190 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6191 effect(DEF dst, USE src, USE toc);
6192 ins_cost(MEMORY_REF_COST);
6193
6194 ins_num_consts(1);
6195
6196 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6197 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6198 "ADDIS $toc, $toc, -offset_hi"%}
6199 size(12);
6200 ins_encode %{
6201 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6202 FloatRegister Rdst = $dst$$FloatRegister;
6203 Register Rtoc = $toc$$Register;
6204 address float_address = __ float_constant($src$$constant);
6205 int offset = __ offset_to_method_toc(float_address);
6206 int hi = (offset + (1<<15))>>16;
6207 int lo = offset - hi * (1<<16);
6208
6209 __ addis(Rtoc, Rtoc, hi);
6210 __ lfs(Rdst, lo, Rtoc);
6211 __ addis(Rtoc, Rtoc, -hi);
6212 %}
6213 ins_pipe(pipe_class_memory);
6214 %}
6215
6216 // Adlc adds toc node MachConstantTableBase.
6217 instruct loadConF_Ex(regF dst, immF src) %{
6218 match(Set dst src);
6219 ins_cost(MEMORY_REF_COST);
6220
6221 // See loadConP.
6222 ins_cannot_rematerialize(true);
6223
6224 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6225 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6226 %}
6227
6228 // Expand node for constant pool load: small offset.
6229 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6230 effect(DEF dst, USE src, USE toc);
6231 ins_cost(MEMORY_REF_COST);
6232
6233 ins_num_consts(1);
6234
6235 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6236 size(4);
6237 ins_encode %{
6238 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6239 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6240 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6241 %}
6242 ins_pipe(pipe_class_memory);
6243 %}
6244
6245 // Expand node for constant pool load: large offset.
6246 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6247 effect(DEF dst, USE src, USE toc);
6248 ins_cost(MEMORY_REF_COST);
6249
6250 ins_num_consts(1);
6251
6252 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6253 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6254 "ADDIS $toc, $toc, -offset_hi" %}
6255 size(12);
6256 ins_encode %{
6257 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6258 FloatRegister Rdst = $dst$$FloatRegister;
6259 Register Rtoc = $toc$$Register;
6260 address float_address = __ double_constant($src$$constant);
6261 int offset = __ offset_to_method_toc(float_address);
6262 int hi = (offset + (1<<15))>>16;
6263 int lo = offset - hi * (1<<16);
6264
6265 __ addis(Rtoc, Rtoc, hi);
6266 __ lfd(Rdst, lo, Rtoc);
6267 __ addis(Rtoc, Rtoc, -hi);
6268 %}
6269 ins_pipe(pipe_class_memory);
6270 %}
6271
6272 // Adlc adds toc node MachConstantTableBase.
6273 instruct loadConD_Ex(regD dst, immD src) %{
6274 match(Set dst src);
6275 ins_cost(MEMORY_REF_COST);
6276
6277 // See loadConP.
6278 ins_cannot_rematerialize(true);
6279
6280 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6281 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6282 %}
6283
6284 // Prefetch instructions.
6285 // Must be safe to execute with invalid address (cannot fault).
6286
6287 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6288 match(PrefetchRead (AddP mem src));
6289 ins_cost(MEMORY_REF_COST);
6290
6291 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6292 size(4);
6293 ins_encode %{
6294 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6295 __ dcbt($src$$Register, $mem$$base$$Register);
6296 %}
6297 ins_pipe(pipe_class_memory);
6298 %}
6299
6300 instruct prefetchr_no_offset(indirectMemory mem) %{
6301 match(PrefetchRead mem);
6302 ins_cost(MEMORY_REF_COST);
6303
6304 format %{ "PREFETCH $mem" %}
6305 size(4);
6306 ins_encode %{
6307 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6308 __ dcbt($mem$$base$$Register);
6309 %}
6310 ins_pipe(pipe_class_memory);
6311 %}
6312
6313 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6314 match(PrefetchWrite (AddP mem src));
6315 ins_cost(MEMORY_REF_COST);
6316
6317 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6318 size(4);
6319 ins_encode %{
6320 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6321 __ dcbtst($src$$Register, $mem$$base$$Register);
6322 %}
6323 ins_pipe(pipe_class_memory);
6324 %}
6325
6326 instruct prefetchw_no_offset(indirectMemory mem) %{
6327 match(PrefetchWrite mem);
6328 ins_cost(MEMORY_REF_COST);
6329
6330 format %{ "PREFETCH $mem" %}
6331 size(4);
6332 ins_encode %{
6333 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6334 __ dcbtst($mem$$base$$Register);
6335 %}
6336 ins_pipe(pipe_class_memory);
6337 %}
6338
6339 // Special prefetch versions which use the dcbz instruction.
6340 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6341 match(PrefetchAllocation (AddP mem src));
6342 predicate(AllocatePrefetchStyle == 3);
6343 ins_cost(MEMORY_REF_COST);
6344
6345 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6346 size(4);
6347 ins_encode %{
6348 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6349 __ dcbz($src$$Register, $mem$$base$$Register);
6350 %}
6351 ins_pipe(pipe_class_memory);
6352 %}
6353
6354 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6355 match(PrefetchAllocation mem);
6356 predicate(AllocatePrefetchStyle == 3);
6357 ins_cost(MEMORY_REF_COST);
6358
6359 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6360 size(4);
6361 ins_encode %{
6362 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6363 __ dcbz($mem$$base$$Register);
6364 %}
6365 ins_pipe(pipe_class_memory);
6366 %}
6367
6368 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6369 match(PrefetchAllocation (AddP mem src));
6370 predicate(AllocatePrefetchStyle != 3);
6371 ins_cost(MEMORY_REF_COST);
6372
6373 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6374 size(4);
6375 ins_encode %{
6376 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6377 __ dcbtst($src$$Register, $mem$$base$$Register);
6378 %}
6379 ins_pipe(pipe_class_memory);
6380 %}
6381
6382 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6383 match(PrefetchAllocation mem);
6384 predicate(AllocatePrefetchStyle != 3);
6385 ins_cost(MEMORY_REF_COST);
6386
6387 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6388 size(4);
6389 ins_encode %{
6390 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6391 __ dcbtst($mem$$base$$Register);
6392 %}
6393 ins_pipe(pipe_class_memory);
6394 %}
6395
6396 //----------Store Instructions-------------------------------------------------
6397
6398 // Store Byte
6399 instruct storeB(memory mem, iRegIsrc src) %{
6400 match(Set mem (StoreB mem src));
6401 ins_cost(MEMORY_REF_COST);
6402
6403 format %{ "STB $src, $mem \t// byte" %}
6404 size(4);
6405 ins_encode %{
6406 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6407 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6408 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6409 %}
6410 ins_pipe(pipe_class_memory);
6411 %}
6412
6413 // Store Char/Short
6414 instruct storeC(memory mem, iRegIsrc src) %{
6415 match(Set mem (StoreC mem src));
6416 ins_cost(MEMORY_REF_COST);
6417
6418 format %{ "STH $src, $mem \t// short" %}
6419 size(4);
6420 ins_encode %{
6421 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6422 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6423 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6424 %}
6425 ins_pipe(pipe_class_memory);
6426 %}
6427
6428 // Store Integer
6429 instruct storeI(memory mem, iRegIsrc src) %{
6430 match(Set mem (StoreI mem src));
6431 ins_cost(MEMORY_REF_COST);
6432
6433 format %{ "STW $src, $mem" %}
6434 size(4);
6435 ins_encode( enc_stw(src, mem) );
6436 ins_pipe(pipe_class_memory);
6437 %}
6438
6439 // ConvL2I + StoreI.
6440 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6441 match(Set mem (StoreI mem (ConvL2I src)));
6442 ins_cost(MEMORY_REF_COST);
6443
6444 format %{ "STW l2i($src), $mem" %}
6445 size(4);
6446 ins_encode( enc_stw(src, mem) );
6447 ins_pipe(pipe_class_memory);
6448 %}
6449
6450 // Store Long
6451 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6452 match(Set mem (StoreL mem src));
6453 ins_cost(MEMORY_REF_COST);
6454
6455 format %{ "STD $src, $mem \t// long" %}
6456 size(4);
6457 ins_encode( enc_std(src, mem) );
6458 ins_pipe(pipe_class_memory);
6459 %}
6460
6461 // Store super word nodes.
6462
6463 // Store Aligned Packed Byte long register to memory
6464 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6465 predicate(n->as_StoreVector()->memory_size() == 8);
6466 match(Set mem (StoreVector mem src));
6467 ins_cost(MEMORY_REF_COST);
6468
6469 format %{ "STD $mem, $src \t// packed8B" %}
6470 size(4);
6471 ins_encode( enc_std(src, mem) );
6472 ins_pipe(pipe_class_memory);
6473 %}
6474
6475 // Store Compressed Oop
6476 instruct storeN(memory dst, iRegN_P2N src) %{
6477 match(Set dst (StoreN dst src));
6478 ins_cost(MEMORY_REF_COST);
6479
6480 format %{ "STW $src, $dst \t// compressed oop" %}
6481 size(4);
6482 ins_encode( enc_stw(src, dst) );
6483 ins_pipe(pipe_class_memory);
6484 %}
6485
6486 // Store Compressed KLass
6487 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6488 match(Set dst (StoreNKlass dst src));
6489 ins_cost(MEMORY_REF_COST);
6490
6491 format %{ "STW $src, $dst \t// compressed klass" %}
6492 size(4);
6493 ins_encode( enc_stw(src, dst) );
6494 ins_pipe(pipe_class_memory);
6495 %}
6496
6497 // Store Pointer
6498 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6499 match(Set dst (StoreP dst src));
6500 ins_cost(MEMORY_REF_COST);
6501
6502 format %{ "STD $src, $dst \t// ptr" %}
6503 size(4);
6504 ins_encode( enc_std(src, dst) );
6505 ins_pipe(pipe_class_memory);
6506 %}
6507
6508 // Store Float
6509 instruct storeF(memory mem, regF src) %{
6510 match(Set mem (StoreF mem src));
6511 ins_cost(MEMORY_REF_COST);
6512
6513 format %{ "STFS $src, $mem" %}
6514 size(4);
6515 ins_encode( enc_stfs(src, mem) );
6516 ins_pipe(pipe_class_memory);
6517 %}
6518
6519 // Store Double
6520 instruct storeD(memory mem, regD src) %{
6521 match(Set mem (StoreD mem src));
6522 ins_cost(MEMORY_REF_COST);
6523
6524 format %{ "STFD $src, $mem" %}
6525 size(4);
6526 ins_encode( enc_stfd(src, mem) );
6527 ins_pipe(pipe_class_memory);
6528 %}
6529
6530 //----------Store Instructions With Zeros--------------------------------------
6531
6532 // Card-mark for CMS garbage collection.
6533 // This cardmark does an optimization so that it must not always
6534 // do a releasing store. For this, it gets the address of
6535 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6536 // (Using releaseFieldAddr in the match rule is a hack.)
6537 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6538 match(Set mem (StoreCM mem releaseFieldAddr));
6539 predicate(false);
6540 ins_cost(MEMORY_REF_COST);
6541
6542 // See loadConP.
6543 ins_cannot_rematerialize(true);
6544
6545 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6546 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6547 ins_pipe(pipe_class_memory);
6548 %}
6549
6550 // Card-mark for CMS garbage collection.
6551 // This cardmark does an optimization so that it must not always
6552 // do a releasing store. For this, it needs the constant address of
6553 // CMSCollectorCardTableModRefBSExt::_requires_release.
6554 // This constant address is split off here by expand so we can use
6555 // adlc / matcher functionality to load it from the constant section.
6556 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6557 match(Set mem (StoreCM mem zero));
6558 predicate(UseConcMarkSweepGC);
6559
6560 expand %{
6561 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6562 iRegLdst releaseFieldAddress;
6563 loadConL_Ex(releaseFieldAddress, baseImm);
6564 storeCM_CMS(mem, releaseFieldAddress);
6565 %}
6566 %}
6567
6568 instruct storeCM_G1(memory mem, immI_0 zero) %{
6569 match(Set mem (StoreCM mem zero));
6570 predicate(UseG1GC);
6571 ins_cost(MEMORY_REF_COST);
6572
6573 ins_cannot_rematerialize(true);
6574
6575 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6576 size(8);
6577 ins_encode %{
6578 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6579 __ li(R0, 0);
6580 //__ release(); // G1: oops are allowed to get visible after dirty marking
6581 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6582 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6583 %}
6584 ins_pipe(pipe_class_memory);
6585 %}
6586
6587 // Convert oop pointer into compressed form.
6588
6589 // Nodes for postalloc expand.
6590
6591 // Shift node for expand.
6592 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6593 // The match rule is needed to make it a 'MachTypeNode'!
6594 match(Set dst (EncodeP src));
6595 predicate(false);
6596
6597 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6598 size(4);
6599 ins_encode %{
6600 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6601 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6602 %}
6603 ins_pipe(pipe_class_default);
6604 %}
6605
6606 // Add node for expand.
6607 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6608 // The match rule is needed to make it a 'MachTypeNode'!
6609 match(Set dst (EncodeP src));
6610 predicate(false);
6611
6612 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6613 size(4);
6614 ins_encode %{
6615 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6616 __ subf($dst$$Register, R30, $src$$Register);
6617 %}
6618 ins_pipe(pipe_class_default);
6619 %}
6620
6621 // Conditional sub base.
6622 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6623 // The match rule is needed to make it a 'MachTypeNode'!
6624 match(Set dst (EncodeP (Binary crx src1)));
6625 predicate(false);
6626
6627 ins_variable_size_depending_on_alignment(true);
6628
6629 format %{ "BEQ $crx, done\n\t"
6630 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6631 "done:" %}
6632 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6633 ins_encode %{
6634 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6635 Label done;
6636 __ beq($crx$$CondRegister, done);
6637 __ subf($dst$$Register, R30, $src1$$Register);
6638 // TODO PPC port __ endgroup_if_needed(_size == 12);
6639 __ bind(done);
6640 %}
6641 ins_pipe(pipe_class_default);
6642 %}
6643
6644 // Power 7 can use isel instruction
6645 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6646 // The match rule is needed to make it a 'MachTypeNode'!
6647 match(Set dst (EncodeP (Binary crx src1)));
6648 predicate(false);
6649
6650 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6651 size(4);
6652 ins_encode %{
6653 // This is a Power7 instruction for which no machine description exists.
6654 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6655 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6656 %}
6657 ins_pipe(pipe_class_default);
6658 %}
6659
6660 // base != 0
6661 // 32G aligned narrow oop base.
6662 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6663 match(Set dst (EncodeP src));
6664 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6665
6666 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6667 size(4);
6668 ins_encode %{
6669 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6670 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6671 %}
6672 ins_pipe(pipe_class_default);
6673 %}
6674
6675 // shift != 0, base != 0
6676 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6677 match(Set dst (EncodeP src));
6678 effect(TEMP crx);
6679 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6680 Universe::narrow_oop_shift() != 0 &&
6681 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6682
6683 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6684 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6685 %}
6686
6687 // shift != 0, base != 0
6688 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6689 match(Set dst (EncodeP src));
6690 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6691 Universe::narrow_oop_shift() != 0 &&
6692 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6693
6694 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6695 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6696 %}
6697
6698 // shift != 0, base == 0
6699 // TODO: This is the same as encodeP_shift. Merge!
6700 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6701 match(Set dst (EncodeP src));
6702 predicate(Universe::narrow_oop_shift() != 0 &&
6703 Universe::narrow_oop_base() ==0);
6704
6705 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6706 size(4);
6707 ins_encode %{
6708 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6709 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6710 %}
6711 ins_pipe(pipe_class_default);
6712 %}
6713
6714 // Compressed OOPs with narrow_oop_shift == 0.
6715 // shift == 0, base == 0
6716 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6717 match(Set dst (EncodeP src));
6718 predicate(Universe::narrow_oop_shift() == 0);
6719
6720 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6721 // variable size, 0 or 4.
6722 ins_encode %{
6723 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6724 __ mr_if_needed($dst$$Register, $src$$Register);
6725 %}
6726 ins_pipe(pipe_class_default);
6727 %}
6728
6729 // Decode nodes.
6730
6731 // Shift node for expand.
6732 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6733 // The match rule is needed to make it a 'MachTypeNode'!
6734 match(Set dst (DecodeN src));
6735 predicate(false);
6736
6737 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6738 size(4);
6739 ins_encode %{
6740 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6741 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6742 %}
6743 ins_pipe(pipe_class_default);
6744 %}
6745
6746 // Add node for expand.
6747 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6748 // The match rule is needed to make it a 'MachTypeNode'!
6749 match(Set dst (DecodeN src));
6750 predicate(false);
6751
6752 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6753 size(4);
6754 ins_encode %{
6755 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6756 __ add($dst$$Register, $src$$Register, R30);
6757 %}
6758 ins_pipe(pipe_class_default);
6759 %}
6760
6761 // conditianal add base for expand
6762 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6763 // The match rule is needed to make it a 'MachTypeNode'!
6764 // NOTICE that the rule is nonsense - we just have to make sure that:
6765 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6766 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6767 match(Set dst (DecodeN (Binary crx src1)));
6768 predicate(false);
6769
6770 ins_variable_size_depending_on_alignment(true);
6771
6772 format %{ "BEQ $crx, done\n\t"
6773 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6774 "done:" %}
6775 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6776 ins_encode %{
6777 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6778 Label done;
6779 __ beq($crx$$CondRegister, done);
6780 __ add($dst$$Register, $src1$$Register, R30);
6781 // TODO PPC port __ endgroup_if_needed(_size == 12);
6782 __ bind(done);
6783 %}
6784 ins_pipe(pipe_class_default);
6785 %}
6786
6787 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6788 // The match rule is needed to make it a 'MachTypeNode'!
6789 // NOTICE that the rule is nonsense - we just have to make sure that:
6790 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6791 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6792 match(Set dst (DecodeN (Binary crx src1)));
6793 predicate(false);
6794
6795 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6796 size(4);
6797 ins_encode %{
6798 // This is a Power7 instruction for which no machine description exists.
6799 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6800 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6801 %}
6802 ins_pipe(pipe_class_default);
6803 %}
6804
6805 // shift != 0, base != 0
6806 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6807 match(Set dst (DecodeN src));
6808 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6809 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6810 Universe::narrow_oop_shift() != 0 &&
6811 Universe::narrow_oop_base() != 0);
6812 effect(TEMP crx);
6813
6814 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6815 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6816 %}
6817
6818 // shift != 0, base == 0
6819 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6820 match(Set dst (DecodeN src));
6821 predicate(Universe::narrow_oop_shift() != 0 &&
6822 Universe::narrow_oop_base() == 0);
6823
6824 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6825 size(4);
6826 ins_encode %{
6827 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6828 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6829 %}
6830 ins_pipe(pipe_class_default);
6831 %}
6832
6833 // src != 0, shift != 0, base != 0
6834 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6835 match(Set dst (DecodeN src));
6836 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6837 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6838 Universe::narrow_oop_shift() != 0 &&
6839 Universe::narrow_oop_base() != 0);
6840
6841 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6842 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6843 %}
6844
6845 // Compressed OOPs with narrow_oop_shift == 0.
6846 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6847 match(Set dst (DecodeN src));
6848 predicate(Universe::narrow_oop_shift() == 0);
6849 ins_cost(DEFAULT_COST);
6850
6851 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6852 // variable size, 0 or 4.
6853 ins_encode %{
6854 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6855 __ mr_if_needed($dst$$Register, $src$$Register);
6856 %}
6857 ins_pipe(pipe_class_default);
6858 %}
6859
6860 // Convert compressed oop into int for vectors alignment masking.
6861 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6862 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6863 predicate(Universe::narrow_oop_shift() == 0);
6864 ins_cost(DEFAULT_COST);
6865
6866 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6867 // variable size, 0 or 4.
6868 ins_encode %{
6869 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6870 __ mr_if_needed($dst$$Register, $src$$Register);
6871 %}
6872 ins_pipe(pipe_class_default);
6873 %}
6874
6875 // Convert klass pointer into compressed form.
6876
6877 // Nodes for postalloc expand.
6878
6879 // Shift node for expand.
6880 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6881 // The match rule is needed to make it a 'MachTypeNode'!
6882 match(Set dst (EncodePKlass src));
6883 predicate(false);
6884
6885 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6886 size(4);
6887 ins_encode %{
6888 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6889 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6890 %}
6891 ins_pipe(pipe_class_default);
6892 %}
6893
6894 // Add node for expand.
6895 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6896 // The match rule is needed to make it a 'MachTypeNode'!
6897 match(Set dst (EncodePKlass (Binary base src)));
6898 predicate(false);
6899
6900 format %{ "SUB $dst, $base, $src \t// encode" %}
6901 size(4);
6902 ins_encode %{
6903 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6904 __ subf($dst$$Register, $base$$Register, $src$$Register);
6905 %}
6906 ins_pipe(pipe_class_default);
6907 %}
6908
6909 // base != 0
6910 // 32G aligned narrow oop base.
6911 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6912 match(Set dst (EncodePKlass src));
6913 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6914
6915 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6916 size(4);
6917 ins_encode %{
6918 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6919 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6920 %}
6921 ins_pipe(pipe_class_default);
6922 %}
6923
6924 // shift != 0, base != 0
6925 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6926 match(Set dst (EncodePKlass (Binary base src)));
6927 predicate(false);
6928
6929 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6930 postalloc_expand %{
6931 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
6932 n1->add_req(n_region, n_base, n_src);
6933 n1->_opnds[0] = op_dst;
6934 n1->_opnds[1] = op_base;
6935 n1->_opnds[2] = op_src;
6936 n1->_bottom_type = _bottom_type;
6937
6938 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
6939 n2->add_req(n_region, n1);
6940 n2->_opnds[0] = op_dst;
6941 n2->_opnds[1] = op_dst;
6942 n2->_bottom_type = _bottom_type;
6943 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6944 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6945
6946 nodes->push(n1);
6947 nodes->push(n2);
6948 %}
6949 %}
6950
6951 // shift != 0, base != 0
6952 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
6953 match(Set dst (EncodePKlass src));
6954 //predicate(Universe::narrow_klass_shift() != 0 &&
6955 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
6956
6957 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6958 ins_cost(DEFAULT_COST*2); // Don't count constant.
6959 expand %{
6960 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
6961 iRegLdst base;
6962 loadConL_Ex(base, baseImm);
6963 encodePKlass_not_null_Ex(dst, base, src);
6964 %}
6965 %}
6966
6967 // Decode nodes.
6968
6969 // Shift node for expand.
6970 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
6971 // The match rule is needed to make it a 'MachTypeNode'!
6972 match(Set dst (DecodeNKlass src));
6973 predicate(false);
6974
6975 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
6976 size(4);
6977 ins_encode %{
6978 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6979 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6980 %}
6981 ins_pipe(pipe_class_default);
6982 %}
6983
6984 // Add node for expand.
6985
6986 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6987 // The match rule is needed to make it a 'MachTypeNode'!
6988 match(Set dst (DecodeNKlass (Binary base src)));
6989 predicate(false);
6990
6991 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
6992 size(4);
6993 ins_encode %{
6994 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6995 __ add($dst$$Register, $base$$Register, $src$$Register);
6996 %}
6997 ins_pipe(pipe_class_default);
6998 %}
6999
7000 // src != 0, shift != 0, base != 0
7001 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7002 match(Set dst (DecodeNKlass (Binary base src)));
7003 //effect(kill src); // We need a register for the immediate result after shifting.
7004 predicate(false);
7005
7006 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7007 postalloc_expand %{
7008 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7009 n1->add_req(n_region, n_base, n_src);
7010 n1->_opnds[0] = op_dst;
7011 n1->_opnds[1] = op_base;
7012 n1->_opnds[2] = op_src;
7013 n1->_bottom_type = _bottom_type;
7014
7015 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7016 n2->add_req(n_region, n2);
7017 n2->_opnds[0] = op_dst;
7018 n2->_opnds[1] = op_dst;
7019 n2->_bottom_type = _bottom_type;
7020
7021 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7022 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7023
7024 nodes->push(n1);
7025 nodes->push(n2);
7026 %}
7027 %}
7028
7029 // src != 0, shift != 0, base != 0
7030 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7031 match(Set dst (DecodeNKlass src));
7032 // predicate(Universe::narrow_klass_shift() != 0 &&
7033 // Universe::narrow_klass_base() != 0);
7034
7035 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7036
7037 ins_cost(DEFAULT_COST*2); // Don't count constant.
7038 expand %{
7039 // We add first, then we shift. Like this, we can get along with one register less.
7040 // But we have to load the base pre-shifted.
7041 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7042 iRegLdst base;
7043 loadConL_Ex(base, baseImm);
7044 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7045 %}
7046 %}
7047
7048 //----------MemBar Instructions-----------------------------------------------
7049 // Memory barrier flavors
7050
7051 instruct membar_acquire() %{
7052 match(LoadFence);
7053 ins_cost(4*MEMORY_REF_COST);
7054
7055 format %{ "MEMBAR-acquire" %}
7056 size(4);
7057 ins_encode %{
7058 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7059 __ acquire();
7060 %}
7061 ins_pipe(pipe_class_default);
7062 %}
7063
7064 instruct unnecessary_membar_acquire() %{
7065 match(MemBarAcquire);
7066 ins_cost(0);
7067
7068 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7069 size(0);
7070 ins_encode( /*empty*/ );
7071 ins_pipe(pipe_class_default);
7072 %}
7073
7074 instruct membar_acquire_lock() %{
7075 match(MemBarAcquireLock);
7076 ins_cost(0);
7077
7078 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7079 size(0);
7080 ins_encode( /*empty*/ );
7081 ins_pipe(pipe_class_default);
7082 %}
7083
7084 instruct membar_release() %{
7085 match(MemBarRelease);
7086 match(StoreFence);
7087 ins_cost(4*MEMORY_REF_COST);
7088
7089 format %{ "MEMBAR-release" %}
7090 size(4);
7091 ins_encode %{
7092 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7093 __ release();
7094 %}
7095 ins_pipe(pipe_class_default);
7096 %}
7097
7098 instruct membar_storestore() %{
7099 match(MemBarStoreStore);
7100 ins_cost(4*MEMORY_REF_COST);
7101
7102 format %{ "MEMBAR-store-store" %}
7103 size(4);
7104 ins_encode %{
7105 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7106 __ membar(Assembler::StoreStore);
7107 %}
7108 ins_pipe(pipe_class_default);
7109 %}
7110
7111 instruct membar_release_lock() %{
7112 match(MemBarReleaseLock);
7113 ins_cost(0);
7114
7115 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7116 size(0);
7117 ins_encode( /*empty*/ );
7118 ins_pipe(pipe_class_default);
7119 %}
7120
7121 instruct membar_volatile() %{
7122 match(MemBarVolatile);
7123 ins_cost(4*MEMORY_REF_COST);
7124
7125 format %{ "MEMBAR-volatile" %}
7126 size(4);
7127 ins_encode %{
7128 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7129 __ fence();
7130 %}
7131 ins_pipe(pipe_class_default);
7132 %}
7133
7134 // This optimization is wrong on PPC. The following pattern is not supported:
7135 // MemBarVolatile
7136 // ^ ^
7137 // | |
7138 // CtrlProj MemProj
7139 // ^ ^
7140 // | |
7141 // | Load
7142 // |
7143 // MemBarVolatile
7144 //
7145 // The first MemBarVolatile could get optimized out! According to
7146 // Vladimir, this pattern can not occur on Oracle platforms.
7147 // However, it does occur on PPC64 (because of membars in
7148 // inline_unsafe_load_store).
7149 //
7150 // Add this node again if we found a good solution for inline_unsafe_load_store().
7151 // Don't forget to look at the implementation of post_store_load_barrier again,
7152 // we did other fixes in that method.
7153 //instruct unnecessary_membar_volatile() %{
7154 // match(MemBarVolatile);
7155 // predicate(Matcher::post_store_load_barrier(n));
7156 // ins_cost(0);
7157 //
7158 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7159 // size(0);
7160 // ins_encode( /*empty*/ );
7161 // ins_pipe(pipe_class_default);
7162 //%}
7163
7164 instruct membar_CPUOrder() %{
7165 match(MemBarCPUOrder);
7166 ins_cost(0);
7167
7168 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7169 size(0);
7170 ins_encode( /*empty*/ );
7171 ins_pipe(pipe_class_default);
7172 %}
7173
7174 //----------Conditional Move---------------------------------------------------
7175
7176 // Cmove using isel.
7177 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7178 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7179 predicate(VM_Version::has_isel());
7180 ins_cost(DEFAULT_COST);
7181
7182 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7183 size(4);
7184 ins_encode %{
7185 // This is a Power7 instruction for which no machine description
7186 // exists. Anyways, the scheduler should be off on Power7.
7187 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7188 int cc = $cmp$$cmpcode;
7189 __ isel($dst$$Register, $crx$$CondRegister,
7190 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7191 %}
7192 ins_pipe(pipe_class_default);
7193 %}
7194
7195 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7196 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7197 predicate(!VM_Version::has_isel());
7198 ins_cost(DEFAULT_COST+BRANCH_COST);
7199
7200 ins_variable_size_depending_on_alignment(true);
7201
7202 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7203 // Worst case is branch + move + stop, no stop without scheduler
7204 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7205 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7206 ins_pipe(pipe_class_default);
7207 %}
7208
7209 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7210 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7211 ins_cost(DEFAULT_COST+BRANCH_COST);
7212
7213 ins_variable_size_depending_on_alignment(true);
7214
7215 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7216 // Worst case is branch + move + stop, no stop without scheduler
7217 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7218 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7219 ins_pipe(pipe_class_default);
7220 %}
7221
7222 // Cmove using isel.
7223 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7224 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7225 predicate(VM_Version::has_isel());
7226 ins_cost(DEFAULT_COST);
7227
7228 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7229 size(4);
7230 ins_encode %{
7231 // This is a Power7 instruction for which no machine description
7232 // exists. Anyways, the scheduler should be off on Power7.
7233 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7234 int cc = $cmp$$cmpcode;
7235 __ isel($dst$$Register, $crx$$CondRegister,
7236 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7237 %}
7238 ins_pipe(pipe_class_default);
7239 %}
7240
7241 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7242 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7243 predicate(!VM_Version::has_isel());
7244 ins_cost(DEFAULT_COST+BRANCH_COST);
7245
7246 ins_variable_size_depending_on_alignment(true);
7247
7248 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7249 // Worst case is branch + move + stop, no stop without scheduler.
7250 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7251 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7252 ins_pipe(pipe_class_default);
7253 %}
7254
7255 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7256 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7257 ins_cost(DEFAULT_COST+BRANCH_COST);
7258
7259 ins_variable_size_depending_on_alignment(true);
7260
7261 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7262 // Worst case is branch + move + stop, no stop without scheduler.
7263 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7264 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7265 ins_pipe(pipe_class_default);
7266 %}
7267
7268 // Cmove using isel.
7269 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7270 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7271 predicate(VM_Version::has_isel());
7272 ins_cost(DEFAULT_COST);
7273
7274 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7275 size(4);
7276 ins_encode %{
7277 // This is a Power7 instruction for which no machine description
7278 // exists. Anyways, the scheduler should be off on Power7.
7279 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7280 int cc = $cmp$$cmpcode;
7281 __ isel($dst$$Register, $crx$$CondRegister,
7282 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7283 %}
7284 ins_pipe(pipe_class_default);
7285 %}
7286
7287 // Conditional move for RegN. Only cmov(reg, reg).
7288 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7289 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7290 predicate(!VM_Version::has_isel());
7291 ins_cost(DEFAULT_COST+BRANCH_COST);
7292
7293 ins_variable_size_depending_on_alignment(true);
7294
7295 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7296 // Worst case is branch + move + stop, no stop without scheduler.
7297 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7298 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7299 ins_pipe(pipe_class_default);
7300 %}
7301
7302 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7303 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7304 ins_cost(DEFAULT_COST+BRANCH_COST);
7305
7306 ins_variable_size_depending_on_alignment(true);
7307
7308 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7309 // Worst case is branch + move + stop, no stop without scheduler.
7310 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7311 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7312 ins_pipe(pipe_class_default);
7313 %}
7314
7315 // Cmove using isel.
7316 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7317 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7318 predicate(VM_Version::has_isel());
7319 ins_cost(DEFAULT_COST);
7320
7321 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7322 size(4);
7323 ins_encode %{
7324 // This is a Power7 instruction for which no machine description
7325 // exists. Anyways, the scheduler should be off on Power7.
7326 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7327 int cc = $cmp$$cmpcode;
7328 __ isel($dst$$Register, $crx$$CondRegister,
7329 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7330 %}
7331 ins_pipe(pipe_class_default);
7332 %}
7333
7334 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7335 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7336 predicate(!VM_Version::has_isel());
7337 ins_cost(DEFAULT_COST+BRANCH_COST);
7338
7339 ins_variable_size_depending_on_alignment(true);
7340
7341 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7342 // Worst case is branch + move + stop, no stop without scheduler.
7343 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7344 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7345 ins_pipe(pipe_class_default);
7346 %}
7347
7348 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7349 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7350 ins_cost(DEFAULT_COST+BRANCH_COST);
7351
7352 ins_variable_size_depending_on_alignment(true);
7353
7354 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7355 // Worst case is branch + move + stop, no stop without scheduler.
7356 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7357 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7358 ins_pipe(pipe_class_default);
7359 %}
7360
7361 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7362 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7363 ins_cost(DEFAULT_COST+BRANCH_COST);
7364
7365 ins_variable_size_depending_on_alignment(true);
7366
7367 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7368 // Worst case is branch + move + stop, no stop without scheduler.
7369 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7370 ins_encode %{
7371 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7372 Label done;
7373 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7374 // Branch if not (cmp crx).
7375 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7376 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7377 // TODO PPC port __ endgroup_if_needed(_size == 12);
7378 __ bind(done);
7379 %}
7380 ins_pipe(pipe_class_default);
7381 %}
7382
7383 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7384 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7385 ins_cost(DEFAULT_COST+BRANCH_COST);
7386
7387 ins_variable_size_depending_on_alignment(true);
7388
7389 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7390 // Worst case is branch + move + stop, no stop without scheduler.
7391 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7392 ins_encode %{
7393 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7394 Label done;
7395 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7396 // Branch if not (cmp crx).
7397 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7398 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7399 // TODO PPC port __ endgroup_if_needed(_size == 12);
7400 __ bind(done);
7401 %}
7402 ins_pipe(pipe_class_default);
7403 %}
7404
7405 //----------Conditional_store--------------------------------------------------
7406 // Conditional-store of the updated heap-top.
7407 // Used during allocation of the shared heap.
7408 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7409
7410 // As compareAndSwapL, but return flag register instead of boolean value in
7411 // int register.
7412 // Used by sun/misc/AtomicLongCSImpl.java.
7413 // Mem_ptr must be a memory operand, else this node does not get
7414 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7415 // can be rematerialized which leads to errors.
7416 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7417 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7418 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7419 ins_encode %{
7420 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7421 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7422 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7423 noreg, NULL, true);
7424 %}
7425 ins_pipe(pipe_class_default);
7426 %}
7427
7428 // As compareAndSwapP, but return flag register instead of boolean value in
7429 // int register.
7430 // This instruction is matched if UseTLAB is off.
7431 // Mem_ptr must be a memory operand, else this node does not get
7432 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7433 // can be rematerialized which leads to errors.
7434 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7435 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7436 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7437 ins_encode %{
7438 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7439 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7440 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7441 noreg, NULL, true);
7442 %}
7443 ins_pipe(pipe_class_default);
7444 %}
7445
7446 // Implement LoadPLocked. Must be ordered against changes of the memory location
7447 // by storePConditional.
7448 // Don't know whether this is ever used.
7449 instruct loadPLocked(iRegPdst dst, memory mem) %{
7450 match(Set dst (LoadPLocked mem));
7451 ins_cost(MEMORY_REF_COST);
7452
7453 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7454 "TWI $dst\n\t"
7455 "ISYNC" %}
7456 size(12);
7457 ins_encode( enc_ld_ac(dst, mem) );
7458 ins_pipe(pipe_class_memory);
7459 %}
7460
7461 //----------Compare-And-Swap---------------------------------------------------
7462
7463 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7464 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7465 // matched.
7466
7467 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7468 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7469 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7470 // Variable size: instruction count smaller if regs are disjoint.
7471 ins_encode %{
7472 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7473 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7474 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7475 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7476 $res$$Register, true);
7477 %}
7478 ins_pipe(pipe_class_default);
7479 %}
7480
7481 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7482 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7483 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7484 // Variable size: instruction count smaller if regs are disjoint.
7485 ins_encode %{
7486 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7487 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7488 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7489 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7490 $res$$Register, true);
7491 %}
7492 ins_pipe(pipe_class_default);
7493 %}
7494
7495 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7496 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7497 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7498 // Variable size: instruction count smaller if regs are disjoint.
7499 ins_encode %{
7500 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7501 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7502 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7503 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7504 $res$$Register, NULL, true);
7505 %}
7506 ins_pipe(pipe_class_default);
7507 %}
7508
7509 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7510 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7511 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7512 // Variable size: instruction count smaller if regs are disjoint.
7513 ins_encode %{
7514 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7515 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7516 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7517 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7518 $res$$Register, NULL, true);
7519 %}
7520 ins_pipe(pipe_class_default);
7521 %}
7522
7523 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7524 match(Set res (GetAndAddI mem_ptr src));
7525 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7526 // Variable size: instruction count smaller if regs are disjoint.
7527 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7528 ins_pipe(pipe_class_default);
7529 %}
7530
7531 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7532 match(Set res (GetAndAddL mem_ptr src));
7533 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7534 // Variable size: instruction count smaller if regs are disjoint.
7535 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7536 ins_pipe(pipe_class_default);
7537 %}
7538
7539 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7540 match(Set res (GetAndSetI mem_ptr src));
7541 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7542 // Variable size: instruction count smaller if regs are disjoint.
7543 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7544 ins_pipe(pipe_class_default);
7545 %}
7546
7547 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7548 match(Set res (GetAndSetL mem_ptr src));
7549 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7550 // Variable size: instruction count smaller if regs are disjoint.
7551 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7552 ins_pipe(pipe_class_default);
7553 %}
7554
7555 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7556 match(Set res (GetAndSetP mem_ptr src));
7557 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7558 // Variable size: instruction count smaller if regs are disjoint.
7559 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7560 ins_pipe(pipe_class_default);
7561 %}
7562
7563 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7564 match(Set res (GetAndSetN mem_ptr src));
7565 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7566 // Variable size: instruction count smaller if regs are disjoint.
7567 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7568 ins_pipe(pipe_class_default);
7569 %}
7570
7571 //----------Arithmetic Instructions--------------------------------------------
7572 // Addition Instructions
7573
7574 // PPC has no instruction setting overflow of 32-bit integer.
7575 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{
7576 // match(AddExactI dst src);
7577 // effect(DEF cr);
7578 //
7579 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %}
7580 // ins_encode( enc_add(dst, dst, src) );
7581 // ins_pipe(pipe_class_default);
7582 //%}
7583
7584 // Register Addition
7585 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7586 match(Set dst (AddI src1 src2));
7587 format %{ "ADD $dst, $src1, $src2" %}
7588 size(4);
7589 ins_encode %{
7590 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7591 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7592 %}
7593 ins_pipe(pipe_class_default);
7594 %}
7595
7596 // Expand does not work with above instruct. (??)
7597 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7598 // no match-rule
7599 effect(DEF dst, USE src1, USE src2);
7600 format %{ "ADD $dst, $src1, $src2" %}
7601 size(4);
7602 ins_encode %{
7603 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7604 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7605 %}
7606 ins_pipe(pipe_class_default);
7607 %}
7608
7609 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7610 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7611 ins_cost(DEFAULT_COST*3);
7612
7613 expand %{
7614 // FIXME: we should do this in the ideal world.
7615 iRegIdst tmp1;
7616 iRegIdst tmp2;
7617 addI_reg_reg(tmp1, src1, src2);
7618 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7619 addI_reg_reg(dst, tmp1, tmp2);
7620 %}
7621 %}
7622
7623 // Immediate Addition
7624 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7625 match(Set dst (AddI src1 src2));
7626 format %{ "ADDI $dst, $src1, $src2" %}
7627 size(4);
7628 ins_encode %{
7629 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7630 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7631 %}
7632 ins_pipe(pipe_class_default);
7633 %}
7634
7635 // Immediate Addition with 16-bit shifted operand
7636 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7637 match(Set dst (AddI src1 src2));
7638 format %{ "ADDIS $dst, $src1, $src2" %}
7639 size(4);
7640 ins_encode %{
7641 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7642 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7643 %}
7644 ins_pipe(pipe_class_default);
7645 %}
7646
7647 // Long Addition
7648 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7649 match(Set dst (AddL src1 src2));
7650 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7651 size(4);
7652 ins_encode %{
7653 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7654 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7655 %}
7656 ins_pipe(pipe_class_default);
7657 %}
7658
7659 // Expand does not work with above instruct. (??)
7660 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7661 // no match-rule
7662 effect(DEF dst, USE src1, USE src2);
7663 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7664 size(4);
7665 ins_encode %{
7666 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7667 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7668 %}
7669 ins_pipe(pipe_class_default);
7670 %}
7671
7672 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7673 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7674 ins_cost(DEFAULT_COST*3);
7675
7676 expand %{
7677 // FIXME: we should do this in the ideal world.
7678 iRegLdst tmp1;
7679 iRegLdst tmp2;
7680 addL_reg_reg(tmp1, src1, src2);
7681 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7682 addL_reg_reg(dst, tmp1, tmp2);
7683 %}
7684 %}
7685
7686 // AddL + ConvL2I.
7687 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7688 match(Set dst (ConvL2I (AddL src1 src2)));
7689
7690 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7691 size(4);
7692 ins_encode %{
7693 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7694 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7695 %}
7696 ins_pipe(pipe_class_default);
7697 %}
7698
7699 // No constant pool entries required.
7700 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7701 match(Set dst (AddL src1 src2));
7702
7703 format %{ "ADDI $dst, $src1, $src2" %}
7704 size(4);
7705 ins_encode %{
7706 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7707 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7708 %}
7709 ins_pipe(pipe_class_default);
7710 %}
7711
7712 // Long Immediate Addition with 16-bit shifted operand.
7713 // No constant pool entries required.
7714 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7715 match(Set dst (AddL src1 src2));
7716
7717 format %{ "ADDIS $dst, $src1, $src2" %}
7718 size(4);
7719 ins_encode %{
7720 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7721 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7722 %}
7723 ins_pipe(pipe_class_default);
7724 %}
7725
7726 // Pointer Register Addition
7727 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7728 match(Set dst (AddP src1 src2));
7729 format %{ "ADD $dst, $src1, $src2" %}
7730 size(4);
7731 ins_encode %{
7732 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7733 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7734 %}
7735 ins_pipe(pipe_class_default);
7736 %}
7737
7738 // Pointer Immediate Addition
7739 // No constant pool entries required.
7740 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7741 match(Set dst (AddP src1 src2));
7742
7743 format %{ "ADDI $dst, $src1, $src2" %}
7744 size(4);
7745 ins_encode %{
7746 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7747 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7748 %}
7749 ins_pipe(pipe_class_default);
7750 %}
7751
7752 // Pointer Immediate Addition with 16-bit shifted operand.
7753 // No constant pool entries required.
7754 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7755 match(Set dst (AddP src1 src2));
7756
7757 format %{ "ADDIS $dst, $src1, $src2" %}
7758 size(4);
7759 ins_encode %{
7760 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7761 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7762 %}
7763 ins_pipe(pipe_class_default);
7764 %}
7765
7766 //---------------------
7767 // Subtraction Instructions
7768
7769 // Register Subtraction
7770 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7771 match(Set dst (SubI src1 src2));
7772 format %{ "SUBF $dst, $src2, $src1" %}
7773 size(4);
7774 ins_encode %{
7775 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7776 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7777 %}
7778 ins_pipe(pipe_class_default);
7779 %}
7780
7781 // Immediate Subtraction
7782 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7783 // so this rule seems to be unused.
7784 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7785 match(Set dst (SubI src1 src2));
7786 format %{ "SUBI $dst, $src1, $src2" %}
7787 size(4);
7788 ins_encode %{
7789 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7790 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7791 %}
7792 ins_pipe(pipe_class_default);
7793 %}
7794
7795 // SubI from constant (using subfic).
7796 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7797 match(Set dst (SubI src1 src2));
7798 format %{ "SUBI $dst, $src1, $src2" %}
7799
7800 size(4);
7801 ins_encode %{
7802 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7803 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7804 %}
7805 ins_pipe(pipe_class_default);
7806 %}
7807
7808 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7809 // positive integers and 0xF...F for negative ones.
7810 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7811 // no match-rule, false predicate
7812 effect(DEF dst, USE src);
7813 predicate(false);
7814
7815 format %{ "SRAWI $dst, $src, #31" %}
7816 size(4);
7817 ins_encode %{
7818 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7819 __ srawi($dst$$Register, $src$$Register, 0x1f);
7820 %}
7821 ins_pipe(pipe_class_default);
7822 %}
7823
7824 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7825 match(Set dst (AbsI src));
7826 ins_cost(DEFAULT_COST*3);
7827
7828 expand %{
7829 iRegIdst tmp1;
7830 iRegIdst tmp2;
7831 signmask32I_regI(tmp1, src);
7832 xorI_reg_reg(tmp2, tmp1, src);
7833 subI_reg_reg(dst, tmp2, tmp1);
7834 %}
7835 %}
7836
7837 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7838 match(Set dst (SubI zero src2));
7839 format %{ "NEG $dst, $src2" %}
7840 size(4);
7841 ins_encode %{
7842 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7843 __ neg($dst$$Register, $src2$$Register);
7844 %}
7845 ins_pipe(pipe_class_default);
7846 %}
7847
7848 // Long subtraction
7849 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7850 match(Set dst (SubL src1 src2));
7851 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7852 size(4);
7853 ins_encode %{
7854 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7855 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7856 %}
7857 ins_pipe(pipe_class_default);
7858 %}
7859
7860 // SubL + convL2I.
7861 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7862 match(Set dst (ConvL2I (SubL src1 src2)));
7863
7864 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7865 size(4);
7866 ins_encode %{
7867 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7868 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7869 %}
7870 ins_pipe(pipe_class_default);
7871 %}
7872
7873 // Immediate Subtraction
7874 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7875 // so this rule seems to be unused.
7876 // No constant pool entries required.
7877 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7878 match(Set dst (SubL src1 src2));
7879
7880 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7881 size(4);
7882 ins_encode %{
7883 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7884 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7885 %}
7886 ins_pipe(pipe_class_default);
7887 %}
7888
7889 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7890 // positive longs and 0xF...F for negative ones.
7891 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
7892 // no match-rule, false predicate
7893 effect(DEF dst, USE src);
7894 predicate(false);
7895
7896 format %{ "SRADI $dst, $src, #63" %}
7897 size(4);
7898 ins_encode %{
7899 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7900 __ sradi($dst$$Register, $src$$Register, 0x3f);
7901 %}
7902 ins_pipe(pipe_class_default);
7903 %}
7904
7905 // Long negation
7906 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7907 match(Set dst (SubL zero src2));
7908 format %{ "NEG $dst, $src2 \t// long" %}
7909 size(4);
7910 ins_encode %{
7911 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7912 __ neg($dst$$Register, $src2$$Register);
7913 %}
7914 ins_pipe(pipe_class_default);
7915 %}
7916
7917 // NegL + ConvL2I.
7918 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7919 match(Set dst (ConvL2I (SubL zero src2)));
7920
7921 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7922 size(4);
7923 ins_encode %{
7924 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7925 __ neg($dst$$Register, $src2$$Register);
7926 %}
7927 ins_pipe(pipe_class_default);
7928 %}
7929
7930 // Multiplication Instructions
7931 // Integer Multiplication
7932
7933 // Register Multiplication
7934 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7935 match(Set dst (MulI src1 src2));
7936 ins_cost(DEFAULT_COST);
7937
7938 format %{ "MULLW $dst, $src1, $src2" %}
7939 size(4);
7940 ins_encode %{
7941 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
7942 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
7943 %}
7944 ins_pipe(pipe_class_default);
7945 %}
7946
7947 // Immediate Multiplication
7948 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7949 match(Set dst (MulI src1 src2));
7950 ins_cost(DEFAULT_COST);
7951
7952 format %{ "MULLI $dst, $src1, $src2" %}
7953 size(4);
7954 ins_encode %{
7955 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7956 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7957 %}
7958 ins_pipe(pipe_class_default);
7959 %}
7960
7961 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7962 match(Set dst (MulL src1 src2));
7963 ins_cost(DEFAULT_COST);
7964
7965 format %{ "MULLD $dst $src1, $src2 \t// long" %}
7966 size(4);
7967 ins_encode %{
7968 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
7969 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
7970 %}
7971 ins_pipe(pipe_class_default);
7972 %}
7973
7974 // Multiply high for optimized long division by constant.
7975 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7976 match(Set dst (MulHiL src1 src2));
7977 ins_cost(DEFAULT_COST);
7978
7979 format %{ "MULHD $dst $src1, $src2 \t// long" %}
7980 size(4);
7981 ins_encode %{
7982 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
7983 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
7984 %}
7985 ins_pipe(pipe_class_default);
7986 %}
7987
7988 // Immediate Multiplication
7989 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7990 match(Set dst (MulL src1 src2));
7991 ins_cost(DEFAULT_COST);
7992
7993 format %{ "MULLI $dst, $src1, $src2" %}
7994 size(4);
7995 ins_encode %{
7996 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7997 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7998 %}
7999 ins_pipe(pipe_class_default);
8000 %}
8001
8002 // Integer Division with Immediate -1: Negate.
8003 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8004 match(Set dst (DivI src1 src2));
8005 ins_cost(DEFAULT_COST);
8006
8007 format %{ "NEG $dst, $src1 \t// /-1" %}
8008 size(4);
8009 ins_encode %{
8010 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8011 __ neg($dst$$Register, $src1$$Register);
8012 %}
8013 ins_pipe(pipe_class_default);
8014 %}
8015
8016 // Integer Division with constant, but not -1.
8017 // We should be able to improve this by checking the type of src2.
8018 // It might well be that src2 is known to be positive.
8019 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8020 match(Set dst (DivI src1 src2));
8021 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8022 ins_cost(2*DEFAULT_COST);
8023
8024 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8025 size(4);
8026 ins_encode %{
8027 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8028 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8029 %}
8030 ins_pipe(pipe_class_default);
8031 %}
8032
8033 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8034 effect(USE_DEF dst, USE src1, USE crx);
8035 predicate(false);
8036
8037 ins_variable_size_depending_on_alignment(true);
8038
8039 format %{ "CMOVE $dst, neg($src1), $crx" %}
8040 // Worst case is branch + move + stop, no stop without scheduler.
8041 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8042 ins_encode %{
8043 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8044 Label done;
8045 __ bne($crx$$CondRegister, done);
8046 __ neg($dst$$Register, $src1$$Register);
8047 // TODO PPC port __ endgroup_if_needed(_size == 12);
8048 __ bind(done);
8049 %}
8050 ins_pipe(pipe_class_default);
8051 %}
8052
8053 // Integer Division with Registers not containing constants.
8054 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8055 match(Set dst (DivI src1 src2));
8056 ins_cost(10*DEFAULT_COST);
8057
8058 expand %{
8059 immI16 imm %{ (int)-1 %}
8060 flagsReg tmp1;
8061 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8062 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8063 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8064 %}
8065 %}
8066
8067 // Long Division with Immediate -1: Negate.
8068 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8069 match(Set dst (DivL src1 src2));
8070 ins_cost(DEFAULT_COST);
8071
8072 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8073 size(4);
8074 ins_encode %{
8075 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8076 __ neg($dst$$Register, $src1$$Register);
8077 %}
8078 ins_pipe(pipe_class_default);
8079 %}
8080
8081 // Long Division with constant, but not -1.
8082 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8083 match(Set dst (DivL src1 src2));
8084 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8085 ins_cost(2*DEFAULT_COST);
8086
8087 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8088 size(4);
8089 ins_encode %{
8090 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8091 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8092 %}
8093 ins_pipe(pipe_class_default);
8094 %}
8095
8096 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8097 effect(USE_DEF dst, USE src1, USE crx);
8098 predicate(false);
8099
8100 ins_variable_size_depending_on_alignment(true);
8101
8102 format %{ "CMOVE $dst, neg($src1), $crx" %}
8103 // Worst case is branch + move + stop, no stop without scheduler.
8104 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8105 ins_encode %{
8106 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8107 Label done;
8108 __ bne($crx$$CondRegister, done);
8109 __ neg($dst$$Register, $src1$$Register);
8110 // TODO PPC port __ endgroup_if_needed(_size == 12);
8111 __ bind(done);
8112 %}
8113 ins_pipe(pipe_class_default);
8114 %}
8115
8116 // Long Division with Registers not containing constants.
8117 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8118 match(Set dst (DivL src1 src2));
8119 ins_cost(10*DEFAULT_COST);
8120
8121 expand %{
8122 immL16 imm %{ (int)-1 %}
8123 flagsReg tmp1;
8124 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8125 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8126 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8127 %}
8128 %}
8129
8130 // Integer Remainder with registers.
8131 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8132 match(Set dst (ModI src1 src2));
8133 ins_cost(10*DEFAULT_COST);
8134
8135 expand %{
8136 immI16 imm %{ (int)-1 %}
8137 flagsReg tmp1;
8138 iRegIdst tmp2;
8139 iRegIdst tmp3;
8140 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8141 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8142 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8143 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8144 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8145 %}
8146 %}
8147
8148 // Long Remainder with registers
8149 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8150 match(Set dst (ModL src1 src2));
8151 ins_cost(10*DEFAULT_COST);
8152
8153 expand %{
8154 immL16 imm %{ (int)-1 %}
8155 flagsReg tmp1;
8156 iRegLdst tmp2;
8157 iRegLdst tmp3;
8158 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8159 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8160 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8161 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8162 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8163 %}
8164 %}
8165
8166 // Integer Shift Instructions
8167
8168 // Register Shift Left
8169
8170 // Clear all but the lowest #mask bits.
8171 // Used to normalize shift amounts in registers.
8172 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8173 // no match-rule, false predicate
8174 effect(DEF dst, USE src, USE mask);
8175 predicate(false);
8176
8177 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8178 size(4);
8179 ins_encode %{
8180 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8181 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8182 %}
8183 ins_pipe(pipe_class_default);
8184 %}
8185
8186 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8187 // no match-rule, false predicate
8188 effect(DEF dst, USE src1, USE src2);
8189 predicate(false);
8190
8191 format %{ "SLW $dst, $src1, $src2" %}
8192 size(4);
8193 ins_encode %{
8194 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8195 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8196 %}
8197 ins_pipe(pipe_class_default);
8198 %}
8199
8200 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8201 match(Set dst (LShiftI src1 src2));
8202 ins_cost(DEFAULT_COST*2);
8203 expand %{
8204 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8205 iRegIdst tmpI;
8206 maskI_reg_imm(tmpI, src2, mask);
8207 lShiftI_reg_reg(dst, src1, tmpI);
8208 %}
8209 %}
8210
8211 // Register Shift Left Immediate
8212 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8213 match(Set dst (LShiftI src1 src2));
8214
8215 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8216 size(4);
8217 ins_encode %{
8218 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8219 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8220 %}
8221 ins_pipe(pipe_class_default);
8222 %}
8223
8224 // AndI with negpow2-constant + LShiftI
8225 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8226 match(Set dst (LShiftI (AndI src1 src2) src3));
8227 predicate(UseRotateAndMaskInstructionsPPC64);
8228
8229 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8230 size(4);
8231 ins_encode %{
8232 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8233 long src2 = $src2$$constant;
8234 long src3 = $src3$$constant;
8235 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8236 if (maskbits >= 32) {
8237 __ li($dst$$Register, 0); // addi
8238 } else {
8239 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8240 }
8241 %}
8242 ins_pipe(pipe_class_default);
8243 %}
8244
8245 // RShiftI + AndI with negpow2-constant + LShiftI
8246 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8247 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8248 predicate(UseRotateAndMaskInstructionsPPC64);
8249
8250 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8251 size(4);
8252 ins_encode %{
8253 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8254 long src2 = $src2$$constant;
8255 long src3 = $src3$$constant;
8256 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8257 if (maskbits >= 32) {
8258 __ li($dst$$Register, 0); // addi
8259 } else {
8260 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8261 }
8262 %}
8263 ins_pipe(pipe_class_default);
8264 %}
8265
8266 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8267 // no match-rule, false predicate
8268 effect(DEF dst, USE src1, USE src2);
8269 predicate(false);
8270
8271 format %{ "SLD $dst, $src1, $src2" %}
8272 size(4);
8273 ins_encode %{
8274 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8275 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8276 %}
8277 ins_pipe(pipe_class_default);
8278 %}
8279
8280 // Register Shift Left
8281 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8282 match(Set dst (LShiftL src1 src2));
8283 ins_cost(DEFAULT_COST*2);
8284 expand %{
8285 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8286 iRegIdst tmpI;
8287 maskI_reg_imm(tmpI, src2, mask);
8288 lShiftL_regL_regI(dst, src1, tmpI);
8289 %}
8290 %}
8291
8292 // Register Shift Left Immediate
8293 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8294 match(Set dst (LShiftL src1 src2));
8295 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8296 size(4);
8297 ins_encode %{
8298 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8299 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8300 %}
8301 ins_pipe(pipe_class_default);
8302 %}
8303
8304 // If we shift more than 32 bits, we need not convert I2L.
8305 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8306 match(Set dst (LShiftL (ConvI2L src1) src2));
8307 ins_cost(DEFAULT_COST);
8308
8309 size(4);
8310 format %{ "SLDI $dst, i2l($src1), $src2" %}
8311 ins_encode %{
8312 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8313 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8314 %}
8315 ins_pipe(pipe_class_default);
8316 %}
8317
8318 // Shift a postivie int to the left.
8319 // Clrlsldi clears the upper 32 bits and shifts.
8320 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8321 match(Set dst (LShiftL (ConvI2L src1) src2));
8322 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8323
8324 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8325 size(4);
8326 ins_encode %{
8327 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8328 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8329 %}
8330 ins_pipe(pipe_class_default);
8331 %}
8332
8333 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8334 // no match-rule, false predicate
8335 effect(DEF dst, USE src1, USE src2);
8336 predicate(false);
8337
8338 format %{ "SRAW $dst, $src1, $src2" %}
8339 size(4);
8340 ins_encode %{
8341 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8342 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8343 %}
8344 ins_pipe(pipe_class_default);
8345 %}
8346
8347 // Register Arithmetic Shift Right
8348 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8349 match(Set dst (RShiftI src1 src2));
8350 ins_cost(DEFAULT_COST*2);
8351 expand %{
8352 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8353 iRegIdst tmpI;
8354 maskI_reg_imm(tmpI, src2, mask);
8355 arShiftI_reg_reg(dst, src1, tmpI);
8356 %}
8357 %}
8358
8359 // Register Arithmetic Shift Right Immediate
8360 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8361 match(Set dst (RShiftI src1 src2));
8362
8363 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8364 size(4);
8365 ins_encode %{
8366 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8367 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8368 %}
8369 ins_pipe(pipe_class_default);
8370 %}
8371
8372 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8373 // no match-rule, false predicate
8374 effect(DEF dst, USE src1, USE src2);
8375 predicate(false);
8376
8377 format %{ "SRAD $dst, $src1, $src2" %}
8378 size(4);
8379 ins_encode %{
8380 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8381 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8382 %}
8383 ins_pipe(pipe_class_default);
8384 %}
8385
8386 // Register Shift Right Arithmetic Long
8387 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8388 match(Set dst (RShiftL src1 src2));
8389 ins_cost(DEFAULT_COST*2);
8390
8391 expand %{
8392 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8393 iRegIdst tmpI;
8394 maskI_reg_imm(tmpI, src2, mask);
8395 arShiftL_regL_regI(dst, src1, tmpI);
8396 %}
8397 %}
8398
8399 // Register Shift Right Immediate
8400 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8401 match(Set dst (RShiftL src1 src2));
8402
8403 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8404 size(4);
8405 ins_encode %{
8406 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8407 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8408 %}
8409 ins_pipe(pipe_class_default);
8410 %}
8411
8412 // RShiftL + ConvL2I
8413 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8414 match(Set dst (ConvL2I (RShiftL src1 src2)));
8415
8416 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8417 size(4);
8418 ins_encode %{
8419 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8420 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8421 %}
8422 ins_pipe(pipe_class_default);
8423 %}
8424
8425 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8426 // no match-rule, false predicate
8427 effect(DEF dst, USE src1, USE src2);
8428 predicate(false);
8429
8430 format %{ "SRW $dst, $src1, $src2" %}
8431 size(4);
8432 ins_encode %{
8433 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8434 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8435 %}
8436 ins_pipe(pipe_class_default);
8437 %}
8438
8439 // Register Shift Right
8440 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8441 match(Set dst (URShiftI src1 src2));
8442 ins_cost(DEFAULT_COST*2);
8443
8444 expand %{
8445 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8446 iRegIdst tmpI;
8447 maskI_reg_imm(tmpI, src2, mask);
8448 urShiftI_reg_reg(dst, src1, tmpI);
8449 %}
8450 %}
8451
8452 // Register Shift Right Immediate
8453 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8454 match(Set dst (URShiftI src1 src2));
8455
8456 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8457 size(4);
8458 ins_encode %{
8459 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8460 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8461 %}
8462 ins_pipe(pipe_class_default);
8463 %}
8464
8465 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8466 // no match-rule, false predicate
8467 effect(DEF dst, USE src1, USE src2);
8468 predicate(false);
8469
8470 format %{ "SRD $dst, $src1, $src2" %}
8471 size(4);
8472 ins_encode %{
8473 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8474 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8475 %}
8476 ins_pipe(pipe_class_default);
8477 %}
8478
8479 // Register Shift Right
8480 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8481 match(Set dst (URShiftL src1 src2));
8482 ins_cost(DEFAULT_COST*2);
8483
8484 expand %{
8485 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8486 iRegIdst tmpI;
8487 maskI_reg_imm(tmpI, src2, mask);
8488 urShiftL_regL_regI(dst, src1, tmpI);
8489 %}
8490 %}
8491
8492 // Register Shift Right Immediate
8493 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8494 match(Set dst (URShiftL src1 src2));
8495
8496 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8497 size(4);
8498 ins_encode %{
8499 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8500 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8501 %}
8502 ins_pipe(pipe_class_default);
8503 %}
8504
8505 // URShiftL + ConvL2I.
8506 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8507 match(Set dst (ConvL2I (URShiftL src1 src2)));
8508
8509 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8510 size(4);
8511 ins_encode %{
8512 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8513 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8514 %}
8515 ins_pipe(pipe_class_default);
8516 %}
8517
8518 // Register Shift Right Immediate with a CastP2X
8519 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8520 match(Set dst (URShiftL (CastP2X src1) src2));
8521
8522 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8523 size(4);
8524 ins_encode %{
8525 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8526 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8527 %}
8528 ins_pipe(pipe_class_default);
8529 %}
8530
8531 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8532 match(Set dst (ConvL2I (ConvI2L src)));
8533
8534 format %{ "EXTSW $dst, $src \t// int->int" %}
8535 size(4);
8536 ins_encode %{
8537 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8538 __ extsw($dst$$Register, $src$$Register);
8539 %}
8540 ins_pipe(pipe_class_default);
8541 %}
8542
8543 //----------Rotate Instructions------------------------------------------------
8544
8545 // Rotate Left by 8-bit immediate
8546 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8547 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8548 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8549
8550 format %{ "ROTLWI $dst, $src, $lshift" %}
8551 size(4);
8552 ins_encode %{
8553 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8554 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8555 %}
8556 ins_pipe(pipe_class_default);
8557 %}
8558
8559 // Rotate Right by 8-bit immediate
8560 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8561 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8562 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8563
8564 format %{ "ROTRWI $dst, $rshift" %}
8565 size(4);
8566 ins_encode %{
8567 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8568 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8569 %}
8570 ins_pipe(pipe_class_default);
8571 %}
8572
8573 //----------Floating Point Arithmetic Instructions-----------------------------
8574
8575 // Add float single precision
8576 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8577 match(Set dst (AddF src1 src2));
8578
8579 format %{ "FADDS $dst, $src1, $src2" %}
8580 size(4);
8581 ins_encode %{
8582 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8583 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8584 %}
8585 ins_pipe(pipe_class_default);
8586 %}
8587
8588 // Add float double precision
8589 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8590 match(Set dst (AddD src1 src2));
8591
8592 format %{ "FADD $dst, $src1, $src2" %}
8593 size(4);
8594 ins_encode %{
8595 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8596 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8597 %}
8598 ins_pipe(pipe_class_default);
8599 %}
8600
8601 // Sub float single precision
8602 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8603 match(Set dst (SubF src1 src2));
8604
8605 format %{ "FSUBS $dst, $src1, $src2" %}
8606 size(4);
8607 ins_encode %{
8608 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8609 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8610 %}
8611 ins_pipe(pipe_class_default);
8612 %}
8613
8614 // Sub float double precision
8615 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8616 match(Set dst (SubD src1 src2));
8617 format %{ "FSUB $dst, $src1, $src2" %}
8618 size(4);
8619 ins_encode %{
8620 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8621 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8622 %}
8623 ins_pipe(pipe_class_default);
8624 %}
8625
8626 // Mul float single precision
8627 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8628 match(Set dst (MulF src1 src2));
8629 format %{ "FMULS $dst, $src1, $src2" %}
8630 size(4);
8631 ins_encode %{
8632 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8633 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8634 %}
8635 ins_pipe(pipe_class_default);
8636 %}
8637
8638 // Mul float double precision
8639 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8640 match(Set dst (MulD src1 src2));
8641 format %{ "FMUL $dst, $src1, $src2" %}
8642 size(4);
8643 ins_encode %{
8644 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8645 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8646 %}
8647 ins_pipe(pipe_class_default);
8648 %}
8649
8650 // Div float single precision
8651 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8652 match(Set dst (DivF src1 src2));
8653 format %{ "FDIVS $dst, $src1, $src2" %}
8654 size(4);
8655 ins_encode %{
8656 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8657 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8658 %}
8659 ins_pipe(pipe_class_default);
8660 %}
8661
8662 // Div float double precision
8663 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8664 match(Set dst (DivD src1 src2));
8665 format %{ "FDIV $dst, $src1, $src2" %}
8666 size(4);
8667 ins_encode %{
8668 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8669 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8670 %}
8671 ins_pipe(pipe_class_default);
8672 %}
8673
8674 // Absolute float single precision
8675 instruct absF_reg(regF dst, regF src) %{
8676 match(Set dst (AbsF src));
8677 format %{ "FABS $dst, $src \t// float" %}
8678 size(4);
8679 ins_encode %{
8680 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8681 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8682 %}
8683 ins_pipe(pipe_class_default);
8684 %}
8685
8686 // Absolute float double precision
8687 instruct absD_reg(regD dst, regD src) %{
8688 match(Set dst (AbsD src));
8689 format %{ "FABS $dst, $src \t// double" %}
8690 size(4);
8691 ins_encode %{
8692 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8693 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8694 %}
8695 ins_pipe(pipe_class_default);
8696 %}
8697
8698 instruct negF_reg(regF dst, regF src) %{
8699 match(Set dst (NegF src));
8700 format %{ "FNEG $dst, $src \t// float" %}
8701 size(4);
8702 ins_encode %{
8703 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8704 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8705 %}
8706 ins_pipe(pipe_class_default);
8707 %}
8708
8709 instruct negD_reg(regD dst, regD src) %{
8710 match(Set dst (NegD src));
8711 format %{ "FNEG $dst, $src \t// double" %}
8712 size(4);
8713 ins_encode %{
8714 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8715 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8716 %}
8717 ins_pipe(pipe_class_default);
8718 %}
8719
8720 // AbsF + NegF.
8721 instruct negF_absF_reg(regF dst, regF src) %{
8722 match(Set dst (NegF (AbsF src)));
8723 format %{ "FNABS $dst, $src \t// float" %}
8724 size(4);
8725 ins_encode %{
8726 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8727 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8728 %}
8729 ins_pipe(pipe_class_default);
8730 %}
8731
8732 // AbsD + NegD.
8733 instruct negD_absD_reg(regD dst, regD src) %{
8734 match(Set dst (NegD (AbsD src)));
8735 format %{ "FNABS $dst, $src \t// double" %}
8736 size(4);
8737 ins_encode %{
8738 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8739 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8740 %}
8741 ins_pipe(pipe_class_default);
8742 %}
8743
8744 // VM_Version::has_sqrt() decides if this node will be used.
8745 // Sqrt float double precision
8746 instruct sqrtD_reg(regD dst, regD src) %{
8747 match(Set dst (SqrtD src));
8748 format %{ "FSQRT $dst, $src" %}
8749 size(4);
8750 ins_encode %{
8751 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8752 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8753 %}
8754 ins_pipe(pipe_class_default);
8755 %}
8756
8757 // Single-precision sqrt.
8758 instruct sqrtF_reg(regF dst, regF src) %{
8759 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8760 ins_cost(DEFAULT_COST);
8761
8762 format %{ "FSQRTS $dst, $src" %}
8763 size(4);
8764 ins_encode %{
8765 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8766 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8767 %}
8768 ins_pipe(pipe_class_default);
8769 %}
8770
8771 instruct roundDouble_nop(regD dst) %{
8772 match(Set dst (RoundDouble dst));
8773 ins_cost(0);
8774
8775 format %{ " -- \t// RoundDouble not needed - empty" %}
8776 size(0);
8777 // PPC results are already "rounded" (i.e., normal-format IEEE).
8778 ins_encode( /*empty*/ );
8779 ins_pipe(pipe_class_default);
8780 %}
8781
8782 instruct roundFloat_nop(regF dst) %{
8783 match(Set dst (RoundFloat dst));
8784 ins_cost(0);
8785
8786 format %{ " -- \t// RoundFloat not needed - empty" %}
8787 size(0);
8788 // PPC results are already "rounded" (i.e., normal-format IEEE).
8789 ins_encode( /*empty*/ );
8790 ins_pipe(pipe_class_default);
8791 %}
8792
8793 //----------Logical Instructions-----------------------------------------------
8794
8795 // And Instructions
8796
8797 // Register And
8798 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8799 match(Set dst (AndI src1 src2));
8800 format %{ "AND $dst, $src1, $src2" %}
8801 size(4);
8802 ins_encode %{
8803 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8804 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8805 %}
8806 ins_pipe(pipe_class_default);
8807 %}
8808
8809 // Immediate And
8810 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8811 match(Set dst (AndI src1 src2));
8812 effect(KILL cr0);
8813
8814 format %{ "ANDI $dst, $src1, $src2" %}
8815 size(4);
8816 ins_encode %{
8817 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8818 // FIXME: avoid andi_ ?
8819 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8820 %}
8821 ins_pipe(pipe_class_default);
8822 %}
8823
8824 // Immediate And where the immediate is a negative power of 2.
8825 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8826 match(Set dst (AndI src1 src2));
8827 format %{ "ANDWI $dst, $src1, $src2" %}
8828 size(4);
8829 ins_encode %{
8830 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8831 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8832 %}
8833 ins_pipe(pipe_class_default);
8834 %}
8835
8836 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8837 match(Set dst (AndI src1 src2));
8838 format %{ "ANDWI $dst, $src1, $src2" %}
8839 size(4);
8840 ins_encode %{
8841 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8842 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8843 %}
8844 ins_pipe(pipe_class_default);
8845 %}
8846
8847 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8848 match(Set dst (AndI src1 src2));
8849 predicate(UseRotateAndMaskInstructionsPPC64);
8850 format %{ "ANDWI $dst, $src1, $src2" %}
8851 size(4);
8852 ins_encode %{
8853 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8854 __ rlwinm($dst$$Register, $src1$$Register, 0,
8855 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8856 %}
8857 ins_pipe(pipe_class_default);
8858 %}
8859
8860 // Register And Long
8861 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8862 match(Set dst (AndL src1 src2));
8863 ins_cost(DEFAULT_COST);
8864
8865 format %{ "AND $dst, $src1, $src2 \t// long" %}
8866 size(4);
8867 ins_encode %{
8868 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8869 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8870 %}
8871 ins_pipe(pipe_class_default);
8872 %}
8873
8874 // Immediate And long
8875 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8876 match(Set dst (AndL src1 src2));
8877 effect(KILL cr0);
8878 ins_cost(DEFAULT_COST);
8879
8880 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8881 size(4);
8882 ins_encode %{
8883 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8884 // FIXME: avoid andi_ ?
8885 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8886 %}
8887 ins_pipe(pipe_class_default);
8888 %}
8889
8890 // Immediate And Long where the immediate is a negative power of 2.
8891 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8892 match(Set dst (AndL src1 src2));
8893 format %{ "ANDDI $dst, $src1, $src2" %}
8894 size(4);
8895 ins_encode %{
8896 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8897 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8898 %}
8899 ins_pipe(pipe_class_default);
8900 %}
8901
8902 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8903 match(Set dst (AndL src1 src2));
8904 format %{ "ANDDI $dst, $src1, $src2" %}
8905 size(4);
8906 ins_encode %{
8907 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8908 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8909 %}
8910 ins_pipe(pipe_class_default);
8911 %}
8912
8913 // AndL + ConvL2I.
8914 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8915 match(Set dst (ConvL2I (AndL src1 src2)));
8916 ins_cost(DEFAULT_COST);
8917
8918 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8919 size(4);
8920 ins_encode %{
8921 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8922 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8923 %}
8924 ins_pipe(pipe_class_default);
8925 %}
8926
8927 // Or Instructions
8928
8929 // Register Or
8930 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8931 match(Set dst (OrI src1 src2));
8932 format %{ "OR $dst, $src1, $src2" %}
8933 size(4);
8934 ins_encode %{
8935 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8936 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8937 %}
8938 ins_pipe(pipe_class_default);
8939 %}
8940
8941 // Expand does not work with above instruct. (??)
8942 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8943 // no match-rule
8944 effect(DEF dst, USE src1, USE src2);
8945 format %{ "OR $dst, $src1, $src2" %}
8946 size(4);
8947 ins_encode %{
8948 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8949 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8950 %}
8951 ins_pipe(pipe_class_default);
8952 %}
8953
8954 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8955 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
8956 ins_cost(DEFAULT_COST*3);
8957
8958 expand %{
8959 // FIXME: we should do this in the ideal world.
8960 iRegIdst tmp1;
8961 iRegIdst tmp2;
8962 orI_reg_reg(tmp1, src1, src2);
8963 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8964 orI_reg_reg(dst, tmp1, tmp2);
8965 %}
8966 %}
8967
8968 // Immediate Or
8969 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
8970 match(Set dst (OrI src1 src2));
8971 format %{ "ORI $dst, $src1, $src2" %}
8972 size(4);
8973 ins_encode %{
8974 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
8975 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
8976 %}
8977 ins_pipe(pipe_class_default);
8978 %}
8979
8980 // Register Or Long
8981 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8982 match(Set dst (OrL src1 src2));
8983 ins_cost(DEFAULT_COST);
8984
8985 size(4);
8986 format %{ "OR $dst, $src1, $src2 \t// long" %}
8987 ins_encode %{
8988 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8989 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8990 %}
8991 ins_pipe(pipe_class_default);
8992 %}
8993
8994 // OrL + ConvL2I.
8995 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8996 match(Set dst (ConvL2I (OrL src1 src2)));
8997 ins_cost(DEFAULT_COST);
8998
8999 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9000 size(4);
9001 ins_encode %{
9002 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9003 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9004 %}
9005 ins_pipe(pipe_class_default);
9006 %}
9007
9008 // Immediate Or long
9009 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9010 match(Set dst (OrL src1 con));
9011 ins_cost(DEFAULT_COST);
9012
9013 format %{ "ORI $dst, $src1, $con \t// long" %}
9014 size(4);
9015 ins_encode %{
9016 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9017 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9018 %}
9019 ins_pipe(pipe_class_default);
9020 %}
9021
9022 // Xor Instructions
9023
9024 // Register Xor
9025 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9026 match(Set dst (XorI src1 src2));
9027 format %{ "XOR $dst, $src1, $src2" %}
9028 size(4);
9029 ins_encode %{
9030 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9031 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9032 %}
9033 ins_pipe(pipe_class_default);
9034 %}
9035
9036 // Expand does not work with above instruct. (??)
9037 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9038 // no match-rule
9039 effect(DEF dst, USE src1, USE src2);
9040 format %{ "XOR $dst, $src1, $src2" %}
9041 size(4);
9042 ins_encode %{
9043 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9044 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9045 %}
9046 ins_pipe(pipe_class_default);
9047 %}
9048
9049 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9050 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9051 ins_cost(DEFAULT_COST*3);
9052
9053 expand %{
9054 // FIXME: we should do this in the ideal world.
9055 iRegIdst tmp1;
9056 iRegIdst tmp2;
9057 xorI_reg_reg(tmp1, src1, src2);
9058 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9059 xorI_reg_reg(dst, tmp1, tmp2);
9060 %}
9061 %}
9062
9063 // Immediate Xor
9064 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9065 match(Set dst (XorI src1 src2));
9066 format %{ "XORI $dst, $src1, $src2" %}
9067 size(4);
9068 ins_encode %{
9069 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9070 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9071 %}
9072 ins_pipe(pipe_class_default);
9073 %}
9074
9075 // Register Xor Long
9076 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9077 match(Set dst (XorL src1 src2));
9078 ins_cost(DEFAULT_COST);
9079
9080 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9081 size(4);
9082 ins_encode %{
9083 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9084 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9085 %}
9086 ins_pipe(pipe_class_default);
9087 %}
9088
9089 // XorL + ConvL2I.
9090 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9091 match(Set dst (ConvL2I (XorL src1 src2)));
9092 ins_cost(DEFAULT_COST);
9093
9094 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9095 size(4);
9096 ins_encode %{
9097 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9098 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9099 %}
9100 ins_pipe(pipe_class_default);
9101 %}
9102
9103 // Immediate Xor Long
9104 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9105 match(Set dst (XorL src1 src2));
9106 ins_cost(DEFAULT_COST);
9107
9108 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9109 size(4);
9110 ins_encode %{
9111 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9112 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9113 %}
9114 ins_pipe(pipe_class_default);
9115 %}
9116
9117 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9118 match(Set dst (XorI src1 src2));
9119 ins_cost(DEFAULT_COST);
9120
9121 format %{ "NOT $dst, $src1 ($src2)" %}
9122 size(4);
9123 ins_encode %{
9124 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9125 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9126 %}
9127 ins_pipe(pipe_class_default);
9128 %}
9129
9130 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9131 match(Set dst (XorL src1 src2));
9132 ins_cost(DEFAULT_COST);
9133
9134 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9135 size(4);
9136 ins_encode %{
9137 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9138 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9139 %}
9140 ins_pipe(pipe_class_default);
9141 %}
9142
9143 // And-complement
9144 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9145 match(Set dst (AndI (XorI src1 src2) src3));
9146 ins_cost(DEFAULT_COST);
9147
9148 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9149 size(4);
9150 ins_encode( enc_andc(dst, src3, src1) );
9151 ins_pipe(pipe_class_default);
9152 %}
9153
9154 // And-complement
9155 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9156 // no match-rule, false predicate
9157 effect(DEF dst, USE src1, USE src2);
9158 predicate(false);
9159
9160 format %{ "ANDC $dst, $src1, $src2" %}
9161 size(4);
9162 ins_encode %{
9163 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9164 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9165 %}
9166 ins_pipe(pipe_class_default);
9167 %}
9168
9169 //----------Moves between int/long and float/double----------------------------
9170 //
9171 // The following rules move values from int/long registers/stack-locations
9172 // to float/double registers/stack-locations and vice versa, without doing any
9173 // conversions. These rules are used to implement the bit-conversion methods
9174 // of java.lang.Float etc., e.g.
9175 // int floatToIntBits(float value)
9176 // float intBitsToFloat(int bits)
9177 //
9178 // Notes on the implementation on ppc64:
9179 // We only provide rules which move between a register and a stack-location,
9180 // because we always have to go through memory when moving between a float
9181 // register and an integer register.
9182
9183 //---------- Chain stack slots between similar types --------
9184
9185 // These are needed so that the rules below can match.
9186
9187 // Load integer from stack slot
9188 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9189 match(Set dst src);
9190 ins_cost(MEMORY_REF_COST);
9191
9192 format %{ "LWZ $dst, $src" %}
9193 size(4);
9194 ins_encode( enc_lwz(dst, src) );
9195 ins_pipe(pipe_class_memory);
9196 %}
9197
9198 // Store integer to stack slot
9199 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9200 match(Set dst src);
9201 ins_cost(MEMORY_REF_COST);
9202
9203 format %{ "STW $src, $dst \t// stk" %}
9204 size(4);
9205 ins_encode( enc_stw(src, dst) ); // rs=rt
9206 ins_pipe(pipe_class_memory);
9207 %}
9208
9209 // Load long from stack slot
9210 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9211 match(Set dst src);
9212 ins_cost(MEMORY_REF_COST);
9213
9214 format %{ "LD $dst, $src \t// long" %}
9215 size(4);
9216 ins_encode( enc_ld(dst, src) );
9217 ins_pipe(pipe_class_memory);
9218 %}
9219
9220 // Store long to stack slot
9221 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9222 match(Set dst src);
9223 ins_cost(MEMORY_REF_COST);
9224
9225 format %{ "STD $src, $dst \t// long" %}
9226 size(4);
9227 ins_encode( enc_std(src, dst) ); // rs=rt
9228 ins_pipe(pipe_class_memory);
9229 %}
9230
9231 //----------Moves between int and float
9232
9233 // Move float value from float stack-location to integer register.
9234 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9235 match(Set dst (MoveF2I src));
9236 ins_cost(MEMORY_REF_COST);
9237
9238 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9239 size(4);
9240 ins_encode( enc_lwz(dst, src) );
9241 ins_pipe(pipe_class_memory);
9242 %}
9243
9244 // Move float value from float register to integer stack-location.
9245 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9246 match(Set dst (MoveF2I src));
9247 ins_cost(MEMORY_REF_COST);
9248
9249 format %{ "STFS $src, $dst \t// MoveF2I" %}
9250 size(4);
9251 ins_encode( enc_stfs(src, dst) );
9252 ins_pipe(pipe_class_memory);
9253 %}
9254
9255 // Move integer value from integer stack-location to float register.
9256 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9257 match(Set dst (MoveI2F src));
9258 ins_cost(MEMORY_REF_COST);
9259
9260 format %{ "LFS $dst, $src \t// MoveI2F" %}
9261 size(4);
9262 ins_encode %{
9263 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9264 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9265 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9266 %}
9267 ins_pipe(pipe_class_memory);
9268 %}
9269
9270 // Move integer value from integer register to float stack-location.
9271 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9272 match(Set dst (MoveI2F src));
9273 ins_cost(MEMORY_REF_COST);
9274
9275 format %{ "STW $src, $dst \t// MoveI2F" %}
9276 size(4);
9277 ins_encode( enc_stw(src, dst) );
9278 ins_pipe(pipe_class_memory);
9279 %}
9280
9281 //----------Moves between long and float
9282
9283 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9284 // no match-rule, false predicate
9285 effect(DEF dst, USE src);
9286 predicate(false);
9287
9288 format %{ "storeD $src, $dst \t// STACK" %}
9289 size(4);
9290 ins_encode( enc_stfd(src, dst) );
9291 ins_pipe(pipe_class_default);
9292 %}
9293
9294 //----------Moves between long and double
9295
9296 // Move double value from double stack-location to long register.
9297 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9298 match(Set dst (MoveD2L src));
9299 ins_cost(MEMORY_REF_COST);
9300 size(4);
9301 format %{ "LD $dst, $src \t// MoveD2L" %}
9302 ins_encode( enc_ld(dst, src) );
9303 ins_pipe(pipe_class_memory);
9304 %}
9305
9306 // Move double value from double register to long stack-location.
9307 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9308 match(Set dst (MoveD2L src));
9309 effect(DEF dst, USE src);
9310 ins_cost(MEMORY_REF_COST);
9311
9312 format %{ "STFD $src, $dst \t// MoveD2L" %}
9313 size(4);
9314 ins_encode( enc_stfd(src, dst) );
9315 ins_pipe(pipe_class_memory);
9316 %}
9317
9318 // Move long value from long stack-location to double register.
9319 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9320 match(Set dst (MoveL2D src));
9321 ins_cost(MEMORY_REF_COST);
9322
9323 format %{ "LFD $dst, $src \t// MoveL2D" %}
9324 size(4);
9325 ins_encode( enc_lfd(dst, src) );
9326 ins_pipe(pipe_class_memory);
9327 %}
9328
9329 // Move long value from long register to double stack-location.
9330 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9331 match(Set dst (MoveL2D src));
9332 ins_cost(MEMORY_REF_COST);
9333
9334 format %{ "STD $src, $dst \t// MoveL2D" %}
9335 size(4);
9336 ins_encode( enc_std(src, dst) );
9337 ins_pipe(pipe_class_memory);
9338 %}
9339
9340 //----------Register Move Instructions-----------------------------------------
9341
9342 // Replicate for Superword
9343
9344 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9345 predicate(false);
9346 effect(DEF dst, USE src);
9347
9348 format %{ "MR $dst, $src \t// replicate " %}
9349 // variable size, 0 or 4.
9350 ins_encode %{
9351 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9352 __ mr_if_needed($dst$$Register, $src$$Register);
9353 %}
9354 ins_pipe(pipe_class_default);
9355 %}
9356
9357 //----------Cast instructions (Java-level type cast)---------------------------
9358
9359 // Cast Long to Pointer for unsafe natives.
9360 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9361 match(Set dst (CastX2P src));
9362
9363 format %{ "MR $dst, $src \t// Long->Ptr" %}
9364 // variable size, 0 or 4.
9365 ins_encode %{
9366 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9367 __ mr_if_needed($dst$$Register, $src$$Register);
9368 %}
9369 ins_pipe(pipe_class_default);
9370 %}
9371
9372 // Cast Pointer to Long for unsafe natives.
9373 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9374 match(Set dst (CastP2X src));
9375
9376 format %{ "MR $dst, $src \t// Ptr->Long" %}
9377 // variable size, 0 or 4.
9378 ins_encode %{
9379 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9380 __ mr_if_needed($dst$$Register, $src$$Register);
9381 %}
9382 ins_pipe(pipe_class_default);
9383 %}
9384
9385 instruct castPP(iRegPdst dst) %{
9386 match(Set dst (CastPP dst));
9387 format %{ " -- \t// castPP of $dst" %}
9388 size(0);
9389 ins_encode( /*empty*/ );
9390 ins_pipe(pipe_class_default);
9391 %}
9392
9393 instruct castII(iRegIdst dst) %{
9394 match(Set dst (CastII dst));
9395 format %{ " -- \t// castII of $dst" %}
9396 size(0);
9397 ins_encode( /*empty*/ );
9398 ins_pipe(pipe_class_default);
9399 %}
9400
9401 instruct checkCastPP(iRegPdst dst) %{
9402 match(Set dst (CheckCastPP dst));
9403 format %{ " -- \t// checkcastPP of $dst" %}
9404 size(0);
9405 ins_encode( /*empty*/ );
9406 ins_pipe(pipe_class_default);
9407 %}
9408
9409 //----------Convert instructions-----------------------------------------------
9410
9411 // Convert to boolean.
9412
9413 // int_to_bool(src) : { 1 if src != 0
9414 // { 0 else
9415 //
9416 // strategy:
9417 // 1) Count leading zeros of 32 bit-value src,
9418 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9419 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9420 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9421
9422 // convI2Bool
9423 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9424 match(Set dst (Conv2B src));
9425 predicate(UseCountLeadingZerosInstructionsPPC64);
9426 ins_cost(DEFAULT_COST);
9427
9428 expand %{
9429 immI shiftAmount %{ 0x5 %}
9430 uimmI16 mask %{ 0x1 %}
9431 iRegIdst tmp1;
9432 iRegIdst tmp2;
9433 countLeadingZerosI(tmp1, src);
9434 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9435 xorI_reg_uimm16(dst, tmp2, mask);
9436 %}
9437 %}
9438
9439 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9440 match(Set dst (Conv2B src));
9441 effect(TEMP crx);
9442 predicate(!UseCountLeadingZerosInstructionsPPC64);
9443 ins_cost(DEFAULT_COST);
9444
9445 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9446 "LI $dst, #0\n\t"
9447 "BEQ $crx, done\n\t"
9448 "LI $dst, #1\n"
9449 "done:" %}
9450 size(16);
9451 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9452 ins_pipe(pipe_class_compare);
9453 %}
9454
9455 // ConvI2B + XorI
9456 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9457 match(Set dst (XorI (Conv2B src) mask));
9458 predicate(UseCountLeadingZerosInstructionsPPC64);
9459 ins_cost(DEFAULT_COST);
9460
9461 expand %{
9462 immI shiftAmount %{ 0x5 %}
9463 iRegIdst tmp1;
9464 countLeadingZerosI(tmp1, src);
9465 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9466 %}
9467 %}
9468
9469 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9470 match(Set dst (XorI (Conv2B src) mask));
9471 effect(TEMP crx);
9472 predicate(!UseCountLeadingZerosInstructionsPPC64);
9473 ins_cost(DEFAULT_COST);
9474
9475 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9476 "LI $dst, #1\n\t"
9477 "BEQ $crx, done\n\t"
9478 "LI $dst, #0\n"
9479 "done:" %}
9480 size(16);
9481 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9482 ins_pipe(pipe_class_compare);
9483 %}
9484
9485 // AndI 0b0..010..0 + ConvI2B
9486 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9487 match(Set dst (Conv2B (AndI src mask)));
9488 predicate(UseRotateAndMaskInstructionsPPC64);
9489 ins_cost(DEFAULT_COST);
9490
9491 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9492 size(4);
9493 ins_encode %{
9494 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9495 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9496 %}
9497 ins_pipe(pipe_class_default);
9498 %}
9499
9500 // Convert pointer to boolean.
9501 //
9502 // ptr_to_bool(src) : { 1 if src != 0
9503 // { 0 else
9504 //
9505 // strategy:
9506 // 1) Count leading zeros of 64 bit-value src,
9507 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9508 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9509 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9510
9511 // ConvP2B
9512 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9513 match(Set dst (Conv2B src));
9514 predicate(UseCountLeadingZerosInstructionsPPC64);
9515 ins_cost(DEFAULT_COST);
9516
9517 expand %{
9518 immI shiftAmount %{ 0x6 %}
9519 uimmI16 mask %{ 0x1 %}
9520 iRegIdst tmp1;
9521 iRegIdst tmp2;
9522 countLeadingZerosP(tmp1, src);
9523 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9524 xorI_reg_uimm16(dst, tmp2, mask);
9525 %}
9526 %}
9527
9528 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9529 match(Set dst (Conv2B src));
9530 effect(TEMP crx);
9531 predicate(!UseCountLeadingZerosInstructionsPPC64);
9532 ins_cost(DEFAULT_COST);
9533
9534 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9535 "LI $dst, #0\n\t"
9536 "BEQ $crx, done\n\t"
9537 "LI $dst, #1\n"
9538 "done:" %}
9539 size(16);
9540 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9541 ins_pipe(pipe_class_compare);
9542 %}
9543
9544 // ConvP2B + XorI
9545 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9546 match(Set dst (XorI (Conv2B src) mask));
9547 predicate(UseCountLeadingZerosInstructionsPPC64);
9548 ins_cost(DEFAULT_COST);
9549
9550 expand %{
9551 immI shiftAmount %{ 0x6 %}
9552 iRegIdst tmp1;
9553 countLeadingZerosP(tmp1, src);
9554 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9555 %}
9556 %}
9557
9558 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9559 match(Set dst (XorI (Conv2B src) mask));
9560 effect(TEMP crx);
9561 predicate(!UseCountLeadingZerosInstructionsPPC64);
9562 ins_cost(DEFAULT_COST);
9563
9564 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9565 "LI $dst, #1\n\t"
9566 "BEQ $crx, done\n\t"
9567 "LI $dst, #0\n"
9568 "done:" %}
9569 size(16);
9570 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9571 ins_pipe(pipe_class_compare);
9572 %}
9573
9574 // if src1 < src2, return -1 else return 0
9575 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9576 match(Set dst (CmpLTMask src1 src2));
9577 ins_cost(DEFAULT_COST*4);
9578
9579 expand %{
9580 iRegIdst src1s;
9581 iRegIdst src2s;
9582 iRegIdst diff;
9583 sxtI_reg(src1s, src1); // ensure proper sign extention
9584 sxtI_reg(src2s, src2); // ensure proper sign extention
9585 subI_reg_reg(diff, src1s, src2s);
9586 // Need to consider >=33 bit result, therefore we need signmaskL.
9587 signmask64I_regI(dst, diff);
9588 %}
9589 %}
9590
9591 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9592 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9593 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9594 size(4);
9595 ins_encode %{
9596 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9597 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9598 %}
9599 ins_pipe(pipe_class_default);
9600 %}
9601
9602 //----------Arithmetic Conversion Instructions---------------------------------
9603
9604 // Convert to Byte -- nop
9605 // Convert to Short -- nop
9606
9607 // Convert to Int
9608
9609 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9610 match(Set dst (RShiftI (LShiftI src amount) amount));
9611 format %{ "EXTSB $dst, $src \t// byte->int" %}
9612 size(4);
9613 ins_encode %{
9614 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9615 __ extsb($dst$$Register, $src$$Register);
9616 %}
9617 ins_pipe(pipe_class_default);
9618 %}
9619
9620 // LShiftI 16 + RShiftI 16 converts short to int.
9621 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9622 match(Set dst (RShiftI (LShiftI src amount) amount));
9623 format %{ "EXTSH $dst, $src \t// short->int" %}
9624 size(4);
9625 ins_encode %{
9626 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9627 __ extsh($dst$$Register, $src$$Register);
9628 %}
9629 ins_pipe(pipe_class_default);
9630 %}
9631
9632 // ConvL2I + ConvI2L: Sign extend int in long register.
9633 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9634 match(Set dst (ConvI2L (ConvL2I src)));
9635
9636 format %{ "EXTSW $dst, $src \t// long->long" %}
9637 size(4);
9638 ins_encode %{
9639 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9640 __ extsw($dst$$Register, $src$$Register);
9641 %}
9642 ins_pipe(pipe_class_default);
9643 %}
9644
9645 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9646 match(Set dst (ConvL2I src));
9647 format %{ "MR $dst, $src \t// long->int" %}
9648 // variable size, 0 or 4
9649 ins_encode %{
9650 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9651 __ mr_if_needed($dst$$Register, $src$$Register);
9652 %}
9653 ins_pipe(pipe_class_default);
9654 %}
9655
9656 instruct convD2IRaw_regD(regD dst, regD src) %{
9657 // no match-rule, false predicate
9658 effect(DEF dst, USE src);
9659 predicate(false);
9660
9661 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9662 size(4);
9663 ins_encode %{
9664 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9665 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9666 %}
9667 ins_pipe(pipe_class_default);
9668 %}
9669
9670 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9671 // no match-rule, false predicate
9672 effect(DEF dst, USE crx, USE src);
9673 predicate(false);
9674
9675 ins_variable_size_depending_on_alignment(true);
9676
9677 format %{ "cmovI $crx, $dst, $src" %}
9678 // Worst case is branch + move + stop, no stop without scheduler.
9679 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9680 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9681 ins_pipe(pipe_class_default);
9682 %}
9683
9684 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9685 // no match-rule, false predicate
9686 effect(DEF dst, USE crx, USE mem);
9687 predicate(false);
9688
9689 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9690 postalloc_expand %{
9691 //
9692 // replaces
9693 //
9694 // region dst crx mem
9695 // \ | | /
9696 // dst=cmovI_bso_stackSlotL_conLvalue0
9697 //
9698 // with
9699 //
9700 // region dst
9701 // \ /
9702 // dst=loadConI16(0)
9703 // |
9704 // ^ region dst crx mem
9705 // | \ | | /
9706 // dst=cmovI_bso_stackSlotL
9707 //
9708
9709 // Create new nodes.
9710 MachNode *m1 = new (C) loadConI16Node();
9711 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9712
9713 // inputs for new nodes
9714 m1->add_req(n_region);
9715 m2->add_req(n_region, n_crx, n_mem);
9716
9717 // precedences for new nodes
9718 m2->add_prec(m1);
9719
9720 // operands for new nodes
9721 m1->_opnds[0] = op_dst;
9722 m1->_opnds[1] = new (C) immI16Oper(0);
9723
9724 m2->_opnds[0] = op_dst;
9725 m2->_opnds[1] = op_crx;
9726 m2->_opnds[2] = op_mem;
9727
9728 // registers for new nodes
9729 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9730 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9731
9732 // Insert new nodes.
9733 nodes->push(m1);
9734 nodes->push(m2);
9735 %}
9736 %}
9737
9738 // Double to Int conversion, NaN is mapped to 0.
9739 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9740 match(Set dst (ConvD2I src));
9741 ins_cost(DEFAULT_COST);
9742
9743 expand %{
9744 regD tmpD;
9745 stackSlotL tmpS;
9746 flagsReg crx;
9747 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9748 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9749 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9750 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9751 %}
9752 %}
9753
9754 instruct convF2IRaw_regF(regF dst, regF src) %{
9755 // no match-rule, false predicate
9756 effect(DEF dst, USE src);
9757 predicate(false);
9758
9759 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9760 size(4);
9761 ins_encode %{
9762 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9763 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9764 %}
9765 ins_pipe(pipe_class_default);
9766 %}
9767
9768 // Float to Int conversion, NaN is mapped to 0.
9769 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9770 match(Set dst (ConvF2I src));
9771 ins_cost(DEFAULT_COST);
9772
9773 expand %{
9774 regF tmpF;
9775 stackSlotL tmpS;
9776 flagsReg crx;
9777 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9778 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9779 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9780 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9781 %}
9782 %}
9783
9784 // Convert to Long
9785
9786 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9787 match(Set dst (ConvI2L src));
9788 format %{ "EXTSW $dst, $src \t// int->long" %}
9789 size(4);
9790 ins_encode %{
9791 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9792 __ extsw($dst$$Register, $src$$Register);
9793 %}
9794 ins_pipe(pipe_class_default);
9795 %}
9796
9797 // Zero-extend: convert unsigned int to long (convUI2L).
9798 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9799 match(Set dst (AndL (ConvI2L src) mask));
9800 ins_cost(DEFAULT_COST);
9801
9802 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9803 size(4);
9804 ins_encode %{
9805 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9806 __ clrldi($dst$$Register, $src$$Register, 32);
9807 %}
9808 ins_pipe(pipe_class_default);
9809 %}
9810
9811 // Zero-extend: convert unsigned int to long in long register.
9812 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9813 match(Set dst (AndL src mask));
9814 ins_cost(DEFAULT_COST);
9815
9816 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9817 size(4);
9818 ins_encode %{
9819 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9820 __ clrldi($dst$$Register, $src$$Register, 32);
9821 %}
9822 ins_pipe(pipe_class_default);
9823 %}
9824
9825 instruct convF2LRaw_regF(regF dst, regF src) %{
9826 // no match-rule, false predicate
9827 effect(DEF dst, USE src);
9828 predicate(false);
9829
9830 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9831 size(4);
9832 ins_encode %{
9833 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9834 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9835 %}
9836 ins_pipe(pipe_class_default);
9837 %}
9838
9839 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9840 // no match-rule, false predicate
9841 effect(DEF dst, USE crx, USE src);
9842 predicate(false);
9843
9844 ins_variable_size_depending_on_alignment(true);
9845
9846 format %{ "cmovL $crx, $dst, $src" %}
9847 // Worst case is branch + move + stop, no stop without scheduler.
9848 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9849 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9850 ins_pipe(pipe_class_default);
9851 %}
9852
9853 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9854 // no match-rule, false predicate
9855 effect(DEF dst, USE crx, USE mem);
9856 predicate(false);
9857
9858 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9859 postalloc_expand %{
9860 //
9861 // replaces
9862 //
9863 // region dst crx mem
9864 // \ | | /
9865 // dst=cmovL_bso_stackSlotL_conLvalue0
9866 //
9867 // with
9868 //
9869 // region dst
9870 // \ /
9871 // dst=loadConL16(0)
9872 // |
9873 // ^ region dst crx mem
9874 // | \ | | /
9875 // dst=cmovL_bso_stackSlotL
9876 //
9877
9878 // Create new nodes.
9879 MachNode *m1 = new (C) loadConL16Node();
9880 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9881
9882 // inputs for new nodes
9883 m1->add_req(n_region);
9884 m2->add_req(n_region, n_crx, n_mem);
9885 m2->add_prec(m1);
9886
9887 // operands for new nodes
9888 m1->_opnds[0] = op_dst;
9889 m1->_opnds[1] = new (C) immL16Oper(0);
9890 m2->_opnds[0] = op_dst;
9891 m2->_opnds[1] = op_crx;
9892 m2->_opnds[2] = op_mem;
9893
9894 // registers for new nodes
9895 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9896 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9897
9898 // Insert new nodes.
9899 nodes->push(m1);
9900 nodes->push(m2);
9901 %}
9902 %}
9903
9904 // Float to Long conversion, NaN is mapped to 0.
9905 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9906 match(Set dst (ConvF2L src));
9907 ins_cost(DEFAULT_COST);
9908
9909 expand %{
9910 regF tmpF;
9911 stackSlotL tmpS;
9912 flagsReg crx;
9913 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9914 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9915 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9916 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9917 %}
9918 %}
9919
9920 instruct convD2LRaw_regD(regD dst, regD src) %{
9921 // no match-rule, false predicate
9922 effect(DEF dst, USE src);
9923 predicate(false);
9924
9925 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9926 size(4);
9927 ins_encode %{
9928 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9929 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9930 %}
9931 ins_pipe(pipe_class_default);
9932 %}
9933
9934 // Double to Long conversion, NaN is mapped to 0.
9935 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
9936 match(Set dst (ConvD2L src));
9937 ins_cost(DEFAULT_COST);
9938
9939 expand %{
9940 regD tmpD;
9941 stackSlotL tmpS;
9942 flagsReg crx;
9943 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9944 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
9945 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9946 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9947 %}
9948 %}
9949
9950 // Convert to Float
9951
9952 // Placed here as needed in expand.
9953 instruct convL2DRaw_regD(regD dst, regD src) %{
9954 // no match-rule, false predicate
9955 effect(DEF dst, USE src);
9956 predicate(false);
9957
9958 format %{ "FCFID $dst, $src \t// convL2D" %}
9959 size(4);
9960 ins_encode %{
9961 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
9962 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
9963 %}
9964 ins_pipe(pipe_class_default);
9965 %}
9966
9967 // Placed here as needed in expand.
9968 instruct convD2F_reg(regF dst, regD src) %{
9969 match(Set dst (ConvD2F src));
9970 format %{ "FRSP $dst, $src \t// convD2F" %}
9971 size(4);
9972 ins_encode %{
9973 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
9974 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
9975 %}
9976 ins_pipe(pipe_class_default);
9977 %}
9978
9979 // Integer to Float conversion.
9980 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
9981 match(Set dst (ConvI2F src));
9982 predicate(!VM_Version::has_fcfids());
9983 ins_cost(DEFAULT_COST);
9984
9985 expand %{
9986 iRegLdst tmpL;
9987 stackSlotL tmpS;
9988 regD tmpD;
9989 regD tmpD2;
9990 convI2L_reg(tmpL, src); // Sign-extension int to long.
9991 regL_to_stkL(tmpS, tmpL); // Store long to stack.
9992 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
9993 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
9994 convD2F_reg(dst, tmpD2); // Convert double to float.
9995 %}
9996 %}
9997
9998 instruct convL2FRaw_regF(regF dst, regD src) %{
9999 // no match-rule, false predicate
10000 effect(DEF dst, USE src);
10001 predicate(false);
10002
10003 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10004 size(4);
10005 ins_encode %{
10006 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10007 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10008 %}
10009 ins_pipe(pipe_class_default);
10010 %}
10011
10012 // Integer to Float conversion. Special version for Power7.
10013 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10014 match(Set dst (ConvI2F src));
10015 predicate(VM_Version::has_fcfids());
10016 ins_cost(DEFAULT_COST);
10017
10018 expand %{
10019 iRegLdst tmpL;
10020 stackSlotL tmpS;
10021 regD tmpD;
10022 convI2L_reg(tmpL, src); // Sign-extension int to long.
10023 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10024 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10025 convL2FRaw_regF(dst, tmpD); // Convert to float.
10026 %}
10027 %}
10028
10029 // L2F to avoid runtime call.
10030 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10031 match(Set dst (ConvL2F src));
10032 predicate(VM_Version::has_fcfids());
10033 ins_cost(DEFAULT_COST);
10034
10035 expand %{
10036 stackSlotL tmpS;
10037 regD tmpD;
10038 regL_to_stkL(tmpS, src); // Store long to stack.
10039 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10040 convL2FRaw_regF(dst, tmpD); // Convert to float.
10041 %}
10042 %}
10043
10044 // Moved up as used in expand.
10045 //instruct convD2F_reg(regF dst, regD src) %{%}
10046
10047 // Convert to Double
10048
10049 // Integer to Double conversion.
10050 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10051 match(Set dst (ConvI2D src));
10052 ins_cost(DEFAULT_COST);
10053
10054 expand %{
10055 iRegLdst tmpL;
10056 stackSlotL tmpS;
10057 regD tmpD;
10058 convI2L_reg(tmpL, src); // Sign-extension int to long.
10059 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10060 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10061 convL2DRaw_regD(dst, tmpD); // Convert to double.
10062 %}
10063 %}
10064
10065 // Long to Double conversion
10066 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10067 match(Set dst (ConvL2D src));
10068 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10069
10070 expand %{
10071 regD tmpD;
10072 moveL2D_stack_reg(tmpD, src);
10073 convL2DRaw_regD(dst, tmpD);
10074 %}
10075 %}
10076
10077 instruct convF2D_reg(regD dst, regF src) %{
10078 match(Set dst (ConvF2D src));
10079 format %{ "FMR $dst, $src \t// float->double" %}
10080 // variable size, 0 or 4
10081 ins_encode %{
10082 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10083 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10084 %}
10085 ins_pipe(pipe_class_default);
10086 %}
10087
10088 //----------Control Flow Instructions------------------------------------------
10089 // Compare Instructions
10090
10091 // Compare Integers
10092 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10093 match(Set crx (CmpI src1 src2));
10094 size(4);
10095 format %{ "CMPW $crx, $src1, $src2" %}
10096 ins_encode %{
10097 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10098 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10099 %}
10100 ins_pipe(pipe_class_compare);
10101 %}
10102
10103 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10104 match(Set crx (CmpI src1 src2));
10105 format %{ "CMPWI $crx, $src1, $src2" %}
10106 size(4);
10107 ins_encode %{
10108 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10109 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10110 %}
10111 ins_pipe(pipe_class_compare);
10112 %}
10113
10114 // (src1 & src2) == 0?
10115 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10116 match(Set cr0 (CmpI (AndI src1 src2) zero));
10117 // r0 is killed
10118 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10119 size(4);
10120 ins_encode %{
10121 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10122 // FIXME: avoid andi_ ?
10123 __ andi_(R0, $src1$$Register, $src2$$constant);
10124 %}
10125 ins_pipe(pipe_class_compare);
10126 %}
10127
10128 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10129 match(Set crx (CmpL src1 src2));
10130 format %{ "CMPD $crx, $src1, $src2" %}
10131 size(4);
10132 ins_encode %{
10133 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10134 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10135 %}
10136 ins_pipe(pipe_class_compare);
10137 %}
10138
10139 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10140 match(Set crx (CmpL src1 src2));
10141 format %{ "CMPDI $crx, $src1, $src2" %}
10142 size(4);
10143 ins_encode %{
10144 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10145 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10146 %}
10147 ins_pipe(pipe_class_compare);
10148 %}
10149
10150 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10151 match(Set cr0 (CmpL (AndL src1 src2) zero));
10152 // r0 is killed
10153 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10154 size(4);
10155 ins_encode %{
10156 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10157 __ and_(R0, $src1$$Register, $src2$$Register);
10158 %}
10159 ins_pipe(pipe_class_compare);
10160 %}
10161
10162 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10163 match(Set cr0 (CmpL (AndL src1 src2) zero));
10164 // r0 is killed
10165 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10166 size(4);
10167 ins_encode %{
10168 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10169 // FIXME: avoid andi_ ?
10170 __ andi_(R0, $src1$$Register, $src2$$constant);
10171 %}
10172 ins_pipe(pipe_class_compare);
10173 %}
10174
10175 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10176 // no match-rule, false predicate
10177 effect(DEF dst, USE crx);
10178 predicate(false);
10179
10180 ins_variable_size_depending_on_alignment(true);
10181
10182 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10183 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10184 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10185 ins_encode %{
10186 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10187 Label done;
10188 // li(Rdst, 0); // equal -> 0
10189 __ beq($crx$$CondRegister, done);
10190 __ li($dst$$Register, 1); // greater -> +1
10191 __ bgt($crx$$CondRegister, done);
10192 __ li($dst$$Register, -1); // unordered or less -> -1
10193 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10194 __ bind(done);
10195 %}
10196 ins_pipe(pipe_class_compare);
10197 %}
10198
10199 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10200 // no match-rule, false predicate
10201 effect(DEF dst, USE crx);
10202 predicate(false);
10203
10204 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10205 postalloc_expand %{
10206 //
10207 // replaces
10208 //
10209 // region crx
10210 // \ |
10211 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10212 //
10213 // with
10214 //
10215 // region
10216 // \
10217 // dst=loadConI16(0)
10218 // |
10219 // ^ region crx
10220 // | \ |
10221 // dst=cmovI_conIvalueMinus1_conIvalue1
10222 //
10223
10224 // Create new nodes.
10225 MachNode *m1 = new (C) loadConI16Node();
10226 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10227
10228 // inputs for new nodes
10229 m1->add_req(n_region);
10230 m2->add_req(n_region, n_crx);
10231 m2->add_prec(m1);
10232
10233 // operands for new nodes
10234 m1->_opnds[0] = op_dst;
10235 m1->_opnds[1] = new (C) immI16Oper(0);
10236 m2->_opnds[0] = op_dst;
10237 m2->_opnds[1] = op_crx;
10238
10239 // registers for new nodes
10240 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10241 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10242
10243 // Insert new nodes.
10244 nodes->push(m1);
10245 nodes->push(m2);
10246 %}
10247 %}
10248
10249 // Manifest a CmpL3 result in an integer register. Very painful.
10250 // This is the test to avoid.
10251 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10252 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10253 match(Set dst (CmpL3 src1 src2));
10254 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10255
10256 expand %{
10257 flagsReg tmp1;
10258 cmpL_reg_reg(tmp1, src1, src2);
10259 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10260 %}
10261 %}
10262
10263 // Implicit range checks.
10264 // A range check in the ideal world has one of the following shapes:
10265 // - (If le (CmpU length index)), (IfTrue throw exception)
10266 // - (If lt (CmpU index length)), (IfFalse throw exception)
10267 //
10268 // Match range check 'If le (CmpU length index)'.
10269 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10270 match(If cmp (CmpU src_length index));
10271 effect(USE labl);
10272 predicate(TrapBasedRangeChecks &&
10273 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10274 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10275 (Matcher::branches_to_uncommon_trap(_leaf)));
10276
10277 ins_is_TrapBasedCheckNode(true);
10278
10279 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10280 size(4);
10281 ins_encode %{
10282 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10283 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10284 __ trap_range_check_le($src_length$$Register, $index$$constant);
10285 } else {
10286 // Both successors are uncommon traps, probability is 0.
10287 // Node got flipped during fixup flow.
10288 assert($cmp$$cmpcode == 0x9, "must be greater");
10289 __ trap_range_check_g($src_length$$Register, $index$$constant);
10290 }
10291 %}
10292 ins_pipe(pipe_class_trap);
10293 %}
10294
10295 // Match range check 'If lt (CmpU index length)'.
10296 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10297 match(If cmp (CmpU src_index src_length));
10298 effect(USE labl);
10299 predicate(TrapBasedRangeChecks &&
10300 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10301 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10302 (Matcher::branches_to_uncommon_trap(_leaf)));
10303
10304 ins_is_TrapBasedCheckNode(true);
10305
10306 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10307 size(4);
10308 ins_encode %{
10309 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10310 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10311 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10312 } else {
10313 // Both successors are uncommon traps, probability is 0.
10314 // Node got flipped during fixup flow.
10315 assert($cmp$$cmpcode == 0x8, "must be less");
10316 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10317 }
10318 %}
10319 ins_pipe(pipe_class_trap);
10320 %}
10321
10322 // Match range check 'If lt (CmpU index length)'.
10323 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10324 match(If cmp (CmpU src_index length));
10325 effect(USE labl);
10326 predicate(TrapBasedRangeChecks &&
10327 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10328 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10329 (Matcher::branches_to_uncommon_trap(_leaf)));
10330
10331 ins_is_TrapBasedCheckNode(true);
10332
10333 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10334 size(4);
10335 ins_encode %{
10336 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10337 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10338 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10339 } else {
10340 // Both successors are uncommon traps, probability is 0.
10341 // Node got flipped during fixup flow.
10342 assert($cmp$$cmpcode == 0x8, "must be less");
10343 __ trap_range_check_l($src_index$$Register, $length$$constant);
10344 }
10345 %}
10346 ins_pipe(pipe_class_trap);
10347 %}
10348
10349 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10350 match(Set crx (CmpU src1 src2));
10351 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10352 size(4);
10353 ins_encode %{
10354 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10355 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10356 %}
10357 ins_pipe(pipe_class_compare);
10358 %}
10359
10360 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10361 match(Set crx (CmpU src1 src2));
10362 size(4);
10363 format %{ "CMPLWI $crx, $src1, $src2" %}
10364 ins_encode %{
10365 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10366 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10367 %}
10368 ins_pipe(pipe_class_compare);
10369 %}
10370
10371 // Implicit zero checks (more implicit null checks).
10372 // No constant pool entries required.
10373 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10374 match(If cmp (CmpN value zero));
10375 effect(USE labl);
10376 predicate(TrapBasedNullChecks &&
10377 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10378 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10379 Matcher::branches_to_uncommon_trap(_leaf));
10380 ins_cost(1);
10381
10382 ins_is_TrapBasedCheckNode(true);
10383
10384 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10385 size(4);
10386 ins_encode %{
10387 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10388 if ($cmp$$cmpcode == 0xA) {
10389 __ trap_null_check($value$$Register);
10390 } else {
10391 // Both successors are uncommon traps, probability is 0.
10392 // Node got flipped during fixup flow.
10393 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10394 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10395 }
10396 %}
10397 ins_pipe(pipe_class_trap);
10398 %}
10399
10400 // Compare narrow oops.
10401 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10402 match(Set crx (CmpN src1 src2));
10403
10404 size(4);
10405 ins_cost(DEFAULT_COST);
10406 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10407 ins_encode %{
10408 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10409 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10410 %}
10411 ins_pipe(pipe_class_compare);
10412 %}
10413
10414 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10415 match(Set crx (CmpN src1 src2));
10416 // Make this more expensive than zeroCheckN_iReg_imm0.
10417 ins_cost(DEFAULT_COST);
10418
10419 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10420 size(4);
10421 ins_encode %{
10422 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10423 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10424 %}
10425 ins_pipe(pipe_class_compare);
10426 %}
10427
10428 // Implicit zero checks (more implicit null checks).
10429 // No constant pool entries required.
10430 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10431 match(If cmp (CmpP value zero));
10432 effect(USE labl);
10433 predicate(TrapBasedNullChecks &&
10434 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10435 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10436 Matcher::branches_to_uncommon_trap(_leaf));
10437
10438 ins_is_TrapBasedCheckNode(true);
10439
10440 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10441 size(4);
10442 ins_encode %{
10443 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10444 if ($cmp$$cmpcode == 0xA) {
10445 __ trap_null_check($value$$Register);
10446 } else {
10447 // Both successors are uncommon traps, probability is 0.
10448 // Node got flipped during fixup flow.
10449 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10450 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10451 }
10452 %}
10453 ins_pipe(pipe_class_trap);
10454 %}
10455
10456 // Compare Pointers
10457 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10458 match(Set crx (CmpP src1 src2));
10459 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10460 size(4);
10461 ins_encode %{
10462 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10463 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10464 %}
10465 ins_pipe(pipe_class_compare);
10466 %}
10467
10468 // Used in postalloc expand.
10469 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10470 // This match rule prevents reordering of node before a safepoint.
10471 // This only makes sense if this instructions is used exclusively
10472 // for the expansion of EncodeP!
10473 match(Set crx (CmpP src1 src2));
10474 predicate(false);
10475
10476 format %{ "CMPDI $crx, $src1, $src2" %}
10477 size(4);
10478 ins_encode %{
10479 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10480 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10481 %}
10482 ins_pipe(pipe_class_compare);
10483 %}
10484
10485 //----------Float Compares----------------------------------------------------
10486
10487 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10488 // no match-rule, false predicate
10489 effect(DEF crx, USE src1, USE src2);
10490 predicate(false);
10491
10492 format %{ "cmpFUrd $crx, $src1, $src2" %}
10493 size(4);
10494 ins_encode %{
10495 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10496 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10497 %}
10498 ins_pipe(pipe_class_default);
10499 %}
10500
10501 instruct cmov_bns_less(flagsReg crx) %{
10502 // no match-rule, false predicate
10503 effect(DEF crx);
10504 predicate(false);
10505
10506 ins_variable_size_depending_on_alignment(true);
10507
10508 format %{ "cmov $crx" %}
10509 // Worst case is branch + move + stop, no stop without scheduler.
10510 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10511 ins_encode %{
10512 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10513 Label done;
10514 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10515 __ li(R0, 0);
10516 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10517 // TODO PPC port __ endgroup_if_needed(_size == 16);
10518 __ bind(done);
10519 %}
10520 ins_pipe(pipe_class_default);
10521 %}
10522
10523 // Compare floating, generate condition code.
10524 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10525 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10526 //
10527 // The following code sequence occurs a lot in mpegaudio:
10528 //
10529 // block BXX:
10530 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10531 // cmpFUrd CCR6, F11, F9
10532 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10533 // cmov CCR6
10534 // 8: instruct branchConSched:
10535 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10536 match(Set crx (CmpF src1 src2));
10537 ins_cost(DEFAULT_COST+BRANCH_COST);
10538
10539 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10540 postalloc_expand %{
10541 //
10542 // replaces
10543 //
10544 // region src1 src2
10545 // \ | |
10546 // crx=cmpF_reg_reg
10547 //
10548 // with
10549 //
10550 // region src1 src2
10551 // \ | |
10552 // crx=cmpFUnordered_reg_reg
10553 // |
10554 // ^ region
10555 // | \
10556 // crx=cmov_bns_less
10557 //
10558
10559 // Create new nodes.
10560 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10561 MachNode *m2 = new (C) cmov_bns_lessNode();
10562
10563 // inputs for new nodes
10564 m1->add_req(n_region, n_src1, n_src2);
10565 m2->add_req(n_region);
10566 m2->add_prec(m1);
10567
10568 // operands for new nodes
10569 m1->_opnds[0] = op_crx;
10570 m1->_opnds[1] = op_src1;
10571 m1->_opnds[2] = op_src2;
10572 m2->_opnds[0] = op_crx;
10573
10574 // registers for new nodes
10575 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10576 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10577
10578 // Insert new nodes.
10579 nodes->push(m1);
10580 nodes->push(m2);
10581 %}
10582 %}
10583
10584 // Compare float, generate -1,0,1
10585 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10586 match(Set dst (CmpF3 src1 src2));
10587 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10588
10589 expand %{
10590 flagsReg tmp1;
10591 cmpFUnordered_reg_reg(tmp1, src1, src2);
10592 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10593 %}
10594 %}
10595
10596 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10597 // no match-rule, false predicate
10598 effect(DEF crx, USE src1, USE src2);
10599 predicate(false);
10600
10601 format %{ "cmpFUrd $crx, $src1, $src2" %}
10602 size(4);
10603 ins_encode %{
10604 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10605 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10606 %}
10607 ins_pipe(pipe_class_default);
10608 %}
10609
10610 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10611 match(Set crx (CmpD src1 src2));
10612 ins_cost(DEFAULT_COST+BRANCH_COST);
10613
10614 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10615 postalloc_expand %{
10616 //
10617 // replaces
10618 //
10619 // region src1 src2
10620 // \ | |
10621 // crx=cmpD_reg_reg
10622 //
10623 // with
10624 //
10625 // region src1 src2
10626 // \ | |
10627 // crx=cmpDUnordered_reg_reg
10628 // |
10629 // ^ region
10630 // | \
10631 // crx=cmov_bns_less
10632 //
10633
10634 // create new nodes
10635 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10636 MachNode *m2 = new (C) cmov_bns_lessNode();
10637
10638 // inputs for new nodes
10639 m1->add_req(n_region, n_src1, n_src2);
10640 m2->add_req(n_region);
10641 m2->add_prec(m1);
10642
10643 // operands for new nodes
10644 m1->_opnds[0] = op_crx;
10645 m1->_opnds[1] = op_src1;
10646 m1->_opnds[2] = op_src2;
10647 m2->_opnds[0] = op_crx;
10648
10649 // registers for new nodes
10650 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10651 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10652
10653 // Insert new nodes.
10654 nodes->push(m1);
10655 nodes->push(m2);
10656 %}
10657 %}
10658
10659 // Compare double, generate -1,0,1
10660 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10661 match(Set dst (CmpD3 src1 src2));
10662 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10663
10664 expand %{
10665 flagsReg tmp1;
10666 cmpDUnordered_reg_reg(tmp1, src1, src2);
10667 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10668 %}
10669 %}
10670
10671 //----------Branches---------------------------------------------------------
10672 // Jump
10673
10674 // Direct Branch.
10675 instruct branch(label labl) %{
10676 match(Goto);
10677 effect(USE labl);
10678 ins_cost(BRANCH_COST);
10679
10680 format %{ "B $labl" %}
10681 size(4);
10682 ins_encode %{
10683 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10684 Label d; // dummy
10685 __ bind(d);
10686 Label* p = $labl$$label;
10687 // `p' is `NULL' when this encoding class is used only to
10688 // determine the size of the encoded instruction.
10689 Label& l = (NULL == p)? d : *(p);
10690 __ b(l);
10691 %}
10692 ins_pipe(pipe_class_default);
10693 %}
10694
10695 // Conditional Near Branch
10696 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10697 // Same match rule as `branchConFar'.
10698 match(If cmp crx);
10699 effect(USE lbl);
10700 ins_cost(BRANCH_COST);
10701
10702 // If set to 1 this indicates that the current instruction is a
10703 // short variant of a long branch. This avoids using this
10704 // instruction in first-pass matching. It will then only be used in
10705 // the `Shorten_branches' pass.
10706 ins_short_branch(1);
10707
10708 format %{ "B$cmp $crx, $lbl" %}
10709 size(4);
10710 ins_encode( enc_bc(crx, cmp, lbl) );
10711 ins_pipe(pipe_class_default);
10712 %}
10713
10714 // This is for cases when the ppc64 `bc' instruction does not
10715 // reach far enough. So we emit a far branch here, which is more
10716 // expensive.
10717 //
10718 // Conditional Far Branch
10719 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10720 // Same match rule as `branchCon'.
10721 match(If cmp crx);
10722 effect(USE crx, USE lbl);
10723 predicate(!false /* TODO: PPC port HB_Schedule*/);
10724 // Higher cost than `branchCon'.
10725 ins_cost(5*BRANCH_COST);
10726
10727 // This is not a short variant of a branch, but the long variant.
10728 ins_short_branch(0);
10729
10730 format %{ "B_FAR$cmp $crx, $lbl" %}
10731 size(8);
10732 ins_encode( enc_bc_far(crx, cmp, lbl) );
10733 ins_pipe(pipe_class_default);
10734 %}
10735
10736 // Conditional Branch used with Power6 scheduler (can be far or short).
10737 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10738 // Same match rule as `branchCon'.
10739 match(If cmp crx);
10740 effect(USE crx, USE lbl);
10741 predicate(false /* TODO: PPC port HB_Schedule*/);
10742 // Higher cost than `branchCon'.
10743 ins_cost(5*BRANCH_COST);
10744
10745 // Actually size doesn't depend on alignment but on shortening.
10746 ins_variable_size_depending_on_alignment(true);
10747 // long variant.
10748 ins_short_branch(0);
10749
10750 format %{ "B_FAR$cmp $crx, $lbl" %}
10751 size(8); // worst case
10752 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10753 ins_pipe(pipe_class_default);
10754 %}
10755
10756 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10757 match(CountedLoopEnd cmp crx);
10758 effect(USE labl);
10759 ins_cost(BRANCH_COST);
10760
10761 // short variant.
10762 ins_short_branch(1);
10763
10764 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10765 size(4);
10766 ins_encode( enc_bc(crx, cmp, labl) );
10767 ins_pipe(pipe_class_default);
10768 %}
10769
10770 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10771 match(CountedLoopEnd cmp crx);
10772 effect(USE labl);
10773 predicate(!false /* TODO: PPC port HB_Schedule */);
10774 ins_cost(BRANCH_COST);
10775
10776 // Long variant.
10777 ins_short_branch(0);
10778
10779 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10780 size(8);
10781 ins_encode( enc_bc_far(crx, cmp, labl) );
10782 ins_pipe(pipe_class_default);
10783 %}
10784
10785 // Conditional Branch used with Power6 scheduler (can be far or short).
10786 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10787 match(CountedLoopEnd cmp crx);
10788 effect(USE labl);
10789 predicate(false /* TODO: PPC port HB_Schedule */);
10790 // Higher cost than `branchCon'.
10791 ins_cost(5*BRANCH_COST);
10792
10793 // Actually size doesn't depend on alignment but on shortening.
10794 ins_variable_size_depending_on_alignment(true);
10795 // Long variant.
10796 ins_short_branch(0);
10797
10798 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10799 size(8); // worst case
10800 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10801 ins_pipe(pipe_class_default);
10802 %}
10803
10804 // ============================================================================
10805 // Java runtime operations, intrinsics and other complex operations.
10806
10807 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10808 // array for an instance of the superklass. Set a hidden internal cache on a
10809 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10810 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10811 //
10812 // GL TODO: Improve this.
10813 // - result should not be a TEMP
10814 // - Add match rule as on sparc avoiding additional Cmp.
10815 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10816 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10817 match(Set result (PartialSubtypeCheck subklass superklass));
10818 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10819 ins_cost(DEFAULT_COST*10);
10820
10821 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10822 ins_encode %{
10823 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10824 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10825 $tmp_klass$$Register, NULL, $result$$Register);
10826 %}
10827 ins_pipe(pipe_class_default);
10828 %}
10829
10830 // inlined locking and unlocking
10831
10832 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10833 match(Set crx (FastLock oop box));
10834 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10835 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10836
10837 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10838 ins_encode %{
10839 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10840 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10841 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10842 // If locking was successfull, crx should indicate 'EQ'.
10843 // The compiler generates a branch to the runtime call to
10844 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10845 %}
10846 ins_pipe(pipe_class_compare);
10847 %}
10848
10849 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10850 match(Set crx (FastUnlock oop box));
10851 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10852
10853 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10854 ins_encode %{
10855 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10856 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10857 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10858 // If unlocking was successfull, crx should indicate 'EQ'.
10859 // The compiler generates a branch to the runtime call to
10860 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10861 %}
10862 ins_pipe(pipe_class_compare);
10863 %}
10864
10865 // Align address.
10866 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10867 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10868
10869 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10870 size(4);
10871 ins_encode %{
10872 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10873 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10874 %}
10875 ins_pipe(pipe_class_default);
10876 %}
10877
10878 // Array size computation.
10879 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10880 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10881
10882 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10883 size(4);
10884 ins_encode %{
10885 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10886 __ subf($dst$$Register, $start$$Register, $end$$Register);
10887 %}
10888 ins_pipe(pipe_class_default);
10889 %}
10890
10891 // Clear-array with dynamic array-size.
10892 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10893 match(Set dummy (ClearArray cnt base));
10894 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10895 ins_cost(MEMORY_REF_COST);
10896
10897 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10898
10899 format %{ "ClearArray $cnt, $base" %}
10900 ins_encode %{
10901 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10902 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10903 %}
10904 ins_pipe(pipe_class_default);
10905 %}
10906
10907 // String_IndexOf for needle of length 1.
10908 //
10909 // Match needle into immediate operands: no loadConP node needed. Saves one
10910 // register and two instructions over string_indexOf_imm1Node.
10911 //
10912 // Assumes register result differs from all input registers.
10913 //
10914 // Preserves registers haystack, haycnt
10915 // Kills registers tmp1, tmp2
10916 // Defines registers result
10917 //
10918 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10919 //
10920 // Unfortunately this does not match too often. In many situations the AddP is used
10921 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10922 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10923 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10924 iRegIdst tmp1, iRegIdst tmp2,
10925 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10926 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10927 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10928
10929 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10930
10931 ins_cost(150);
10932 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10933 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10934
10935 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
10936 ins_encode %{
10937 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10938 immPOper *needleOper = (immPOper *)$needleImm;
10939 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10940 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10941
10942 __ string_indexof_1($result$$Register,
10943 $haystack$$Register, $haycnt$$Register,
10944 R0, needle_values->char_at(0),
10945 $tmp1$$Register, $tmp2$$Register);
10946 %}
10947 ins_pipe(pipe_class_compare);
10948 %}
10949
10950 // String_IndexOf for needle of length 1.
10951 //
10952 // Special case requires less registers and emits less instructions.
10953 //
10954 // Assumes register result differs from all input registers.
10955 //
10956 // Preserves registers haystack, haycnt
10957 // Kills registers tmp1, tmp2, needle
10958 // Defines registers result
10959 //
10960 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10961 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10962 rscratch2RegP needle, immI_1 needlecntImm,
10963 iRegIdst tmp1, iRegIdst tmp2,
10964 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10965 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10966 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
10967 TEMP tmp1, TEMP tmp2);
10968 // Required for EA: check if it is still a type_array.
10969 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
10970 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
10971 ins_cost(180);
10972
10973 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10974
10975 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
10976 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
10977 ins_encode %{
10978 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10979 Node *ndl = in(operand_index($needle)); // The node that defines needle.
10980 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
10981 guarantee(needle_values, "sanity");
10982 if (needle_values != NULL) {
10983 __ string_indexof_1($result$$Register,
10984 $haystack$$Register, $haycnt$$Register,
10985 R0, needle_values->char_at(0),
10986 $tmp1$$Register, $tmp2$$Register);
10987 } else {
10988 __ string_indexof_1($result$$Register,
10989 $haystack$$Register, $haycnt$$Register,
10990 $needle$$Register, 0,
10991 $tmp1$$Register, $tmp2$$Register);
10992 }
10993 %}
10994 ins_pipe(pipe_class_compare);
10995 %}
10996
10997 // String_IndexOf.
10998 //
10999 // Length of needle as immediate. This saves instruction loading constant needle
11000 // length.
11001 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11002 // completely or do it in vector instruction. This should save registers for
11003 // needlecnt and needle.
11004 //
11005 // Assumes register result differs from all input registers.
11006 // Overwrites haycnt, needlecnt.
11007 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11008 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11009 iRegPsrc needle, uimmI15 needlecntImm,
11010 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11011 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11012 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11013 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11014 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11015 // Required for EA: check if it is still a type_array.
11016 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11017 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11018 ins_cost(250);
11019
11020 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11021
11022 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11023 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11024 ins_encode %{
11025 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11026 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11027 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11028
11029 __ string_indexof($result$$Register,
11030 $haystack$$Register, $haycnt$$Register,
11031 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11032 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11033 %}
11034 ins_pipe(pipe_class_compare);
11035 %}
11036
11037 // StrIndexOf node.
11038 //
11039 // Assumes register result differs from all input registers.
11040 // Overwrites haycnt, needlecnt.
11041 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11042 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11043 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11044 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11045 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11046 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11047 TEMP result,
11048 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11049 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11050 ins_cost(300);
11051
11052 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11053
11054 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11055 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11056 ins_encode %{
11057 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11058 __ string_indexof($result$$Register,
11059 $haystack$$Register, $haycnt$$Register,
11060 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11061 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11062 %}
11063 ins_pipe(pipe_class_compare);
11064 %}
11065
11066 // String equals with immediate.
11067 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11068 iRegPdst tmp1, iRegPdst tmp2,
11069 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11070 match(Set result (StrEquals (Binary str1 str2) cntImm));
11071 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11072 KILL cr0, KILL cr6, KILL ctr);
11073 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11074 ins_cost(250);
11075
11076 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11077
11078 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11079 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11080 ins_encode %{
11081 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11082 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11083 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11084 %}
11085 ins_pipe(pipe_class_compare);
11086 %}
11087
11088 // String equals.
11089 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11090 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11091 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11092 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11093 match(Set result (StrEquals (Binary str1 str2) cnt));
11094 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11095 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11096 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11097 ins_cost(300);
11098
11099 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11100
11101 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11102 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11103 ins_encode %{
11104 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11105 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11106 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11107 %}
11108 ins_pipe(pipe_class_compare);
11109 %}
11110
11111 // String compare.
11112 // Char[] pointers are passed in.
11113 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11114 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11115 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11116 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11117 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11118 ins_cost(300);
11119
11120 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11121
11122 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11123 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11124 ins_encode %{
11125 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11126 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11127 $result$$Register, $tmp$$Register);
11128 %}
11129 ins_pipe(pipe_class_compare);
11130 %}
11131
11132 //---------- Min/Max Instructions ---------------------------------------------
11133
11134 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11135 match(Set dst (MinI src1 src2));
11136 ins_cost(DEFAULT_COST*6);
11137
11138 expand %{
11139 iRegIdst src1s;
11140 iRegIdst src2s;
11141 iRegIdst diff;
11142 iRegIdst sm;
11143 iRegIdst doz; // difference or zero
11144 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11145 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11146 subI_reg_reg(diff, src2s, src1s);
11147 // Need to consider >=33 bit result, therefore we need signmaskL.
11148 signmask64I_regI(sm, diff);
11149 andI_reg_reg(doz, diff, sm); // <=0
11150 addI_reg_reg(dst, doz, src1s);
11151 %}
11152 %}
11153
11154 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11155 match(Set dst (MaxI src1 src2));
11156 ins_cost(DEFAULT_COST*6);
11157
11158 expand %{
11159 immI_minus1 m1 %{ -1 %}
11160 iRegIdst src1s;
11161 iRegIdst src2s;
11162 iRegIdst diff;
11163 iRegIdst sm;
11164 iRegIdst doz; // difference or zero
11165 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11166 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11167 subI_reg_reg(diff, src2s, src1s);
11168 // Need to consider >=33 bit result, therefore we need signmaskL.
11169 signmask64I_regI(sm, diff);
11170 andcI_reg_reg(doz, sm, m1, diff); // >=0
11171 addI_reg_reg(dst, doz, src1s);
11172 %}
11173 %}
11174
11175 //---------- Population Count Instructions ------------------------------------
11176
11177 // Popcnt for Power7.
11178 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11179 match(Set dst (PopCountI src));
11180 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11181 ins_cost(DEFAULT_COST);
11182
11183 format %{ "POPCNTW $dst, $src" %}
11184 size(4);
11185 ins_encode %{
11186 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11187 __ popcntw($dst$$Register, $src$$Register);
11188 %}
11189 ins_pipe(pipe_class_default);
11190 %}
11191
11192 // Popcnt for Power7.
11193 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11194 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11195 match(Set dst (PopCountL src));
11196 ins_cost(DEFAULT_COST);
11197
11198 format %{ "POPCNTD $dst, $src" %}
11199 size(4);
11200 ins_encode %{
11201 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11202 __ popcntd($dst$$Register, $src$$Register);
11203 %}
11204 ins_pipe(pipe_class_default);
11205 %}
11206
11207 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11208 match(Set dst (CountLeadingZerosI src));
11209 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11210 ins_cost(DEFAULT_COST);
11211
11212 format %{ "CNTLZW $dst, $src" %}
11213 size(4);
11214 ins_encode %{
11215 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11216 __ cntlzw($dst$$Register, $src$$Register);
11217 %}
11218 ins_pipe(pipe_class_default);
11219 %}
11220
11221 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11222 match(Set dst (CountLeadingZerosL src));
11223 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11224 ins_cost(DEFAULT_COST);
11225
11226 format %{ "CNTLZD $dst, $src" %}
11227 size(4);
11228 ins_encode %{
11229 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11230 __ cntlzd($dst$$Register, $src$$Register);
11231 %}
11232 ins_pipe(pipe_class_default);
11233 %}
11234
11235 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11236 // no match-rule, false predicate
11237 effect(DEF dst, USE src);
11238 predicate(false);
11239
11240 format %{ "CNTLZD $dst, $src" %}
11241 size(4);
11242 ins_encode %{
11243 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11244 __ cntlzd($dst$$Register, $src$$Register);
11245 %}
11246 ins_pipe(pipe_class_default);
11247 %}
11248
11249 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11250 match(Set dst (CountTrailingZerosI src));
11251 predicate(UseCountLeadingZerosInstructionsPPC64);
11252 ins_cost(DEFAULT_COST);
11253
11254 expand %{
11255 immI16 imm1 %{ (int)-1 %}
11256 immI16 imm2 %{ (int)32 %}
11257 immI_minus1 m1 %{ -1 %}
11258 iRegIdst tmpI1;
11259 iRegIdst tmpI2;
11260 iRegIdst tmpI3;
11261 addI_reg_imm16(tmpI1, src, imm1);
11262 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11263 countLeadingZerosI(tmpI3, tmpI2);
11264 subI_imm16_reg(dst, imm2, tmpI3);
11265 %}
11266 %}
11267
11268 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11269 match(Set dst (CountTrailingZerosL src));
11270 predicate(UseCountLeadingZerosInstructionsPPC64);
11271 ins_cost(DEFAULT_COST);
11272
11273 expand %{
11274 immL16 imm1 %{ (long)-1 %}
11275 immI16 imm2 %{ (int)64 %}
11276 iRegLdst tmpL1;
11277 iRegLdst tmpL2;
11278 iRegIdst tmpL3;
11279 addL_reg_imm16(tmpL1, src, imm1);
11280 andcL_reg_reg(tmpL2, tmpL1, src);
11281 countLeadingZerosL(tmpL3, tmpL2);
11282 subI_imm16_reg(dst, imm2, tmpL3);
11283 %}
11284 %}
11285
11286 // Expand nodes for byte_reverse_int.
11287 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11288 effect(DEF dst, USE src, USE pos, USE shift);
11289 predicate(false);
11290
11291 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11292 size(4);
11293 ins_encode %{
11294 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11295 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11296 %}
11297 ins_pipe(pipe_class_default);
11298 %}
11299
11300 // As insrwi_a, but with USE_DEF.
11301 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11302 effect(USE_DEF dst, USE src, USE pos, USE shift);
11303 predicate(false);
11304
11305 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11306 size(4);
11307 ins_encode %{
11308 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11309 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11310 %}
11311 ins_pipe(pipe_class_default);
11312 %}
11313
11314 // Just slightly faster than java implementation.
11315 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11316 match(Set dst (ReverseBytesI src));
11317 predicate(UseCountLeadingZerosInstructionsPPC64);
11318 ins_cost(DEFAULT_COST);
11319
11320 expand %{
11321 immI16 imm24 %{ (int) 24 %}
11322 immI16 imm16 %{ (int) 16 %}
11323 immI16 imm8 %{ (int) 8 %}
11324 immI16 imm4 %{ (int) 4 %}
11325 immI16 imm0 %{ (int) 0 %}
11326 iRegLdst tmpI1;
11327 iRegLdst tmpI2;
11328 iRegLdst tmpI3;
11329
11330 urShiftI_reg_imm(tmpI1, src, imm24);
11331 insrwi_a(dst, tmpI1, imm24, imm8);
11332 urShiftI_reg_imm(tmpI2, src, imm16);
11333 insrwi(dst, tmpI2, imm8, imm16);
11334 urShiftI_reg_imm(tmpI3, src, imm8);
11335 insrwi(dst, tmpI3, imm8, imm8);
11336 insrwi(dst, src, imm0, imm8);
11337 %}
11338 %}
11339
11340 //---------- Replicate Vector Instructions ------------------------------------
11341
11342 // Insrdi does replicate if src == dst.
11343 instruct repl32(iRegLdst dst) %{
11344 predicate(false);
11345 effect(USE_DEF dst);
11346
11347 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11348 size(4);
11349 ins_encode %{
11350 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11351 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11352 %}
11353 ins_pipe(pipe_class_default);
11354 %}
11355
11356 // Insrdi does replicate if src == dst.
11357 instruct repl48(iRegLdst dst) %{
11358 predicate(false);
11359 effect(USE_DEF dst);
11360
11361 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11362 size(4);
11363 ins_encode %{
11364 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11365 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11366 %}
11367 ins_pipe(pipe_class_default);
11368 %}
11369
11370 // Insrdi does replicate if src == dst.
11371 instruct repl56(iRegLdst dst) %{
11372 predicate(false);
11373 effect(USE_DEF dst);
11374
11375 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11376 size(4);
11377 ins_encode %{
11378 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11379 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11380 %}
11381 ins_pipe(pipe_class_default);
11382 %}
11383
11384 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11385 match(Set dst (ReplicateB src));
11386 predicate(n->as_Vector()->length() == 8);
11387 expand %{
11388 moveReg(dst, src);
11389 repl56(dst);
11390 repl48(dst);
11391 repl32(dst);
11392 %}
11393 %}
11394
11395 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11396 match(Set dst (ReplicateB zero));
11397 predicate(n->as_Vector()->length() == 8);
11398 format %{ "LI $dst, #0 \t// replicate8B" %}
11399 size(4);
11400 ins_encode %{
11401 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11402 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11403 %}
11404 ins_pipe(pipe_class_default);
11405 %}
11406
11407 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11408 match(Set dst (ReplicateB src));
11409 predicate(n->as_Vector()->length() == 8);
11410 format %{ "LI $dst, #-1 \t// replicate8B" %}
11411 size(4);
11412 ins_encode %{
11413 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11414 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11415 %}
11416 ins_pipe(pipe_class_default);
11417 %}
11418
11419 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11420 match(Set dst (ReplicateS src));
11421 predicate(n->as_Vector()->length() == 4);
11422 expand %{
11423 moveReg(dst, src);
11424 repl48(dst);
11425 repl32(dst);
11426 %}
11427 %}
11428
11429 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11430 match(Set dst (ReplicateS zero));
11431 predicate(n->as_Vector()->length() == 4);
11432 format %{ "LI $dst, #0 \t// replicate4C" %}
11433 size(4);
11434 ins_encode %{
11435 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11436 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11437 %}
11438 ins_pipe(pipe_class_default);
11439 %}
11440
11441 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11442 match(Set dst (ReplicateS src));
11443 predicate(n->as_Vector()->length() == 4);
11444 format %{ "LI $dst, -1 \t// replicate4C" %}
11445 size(4);
11446 ins_encode %{
11447 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11448 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11449 %}
11450 ins_pipe(pipe_class_default);
11451 %}
11452
11453 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11454 match(Set dst (ReplicateI src));
11455 predicate(n->as_Vector()->length() == 2);
11456 ins_cost(2 * DEFAULT_COST);
11457 expand %{
11458 moveReg(dst, src);
11459 repl32(dst);
11460 %}
11461 %}
11462
11463 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11464 match(Set dst (ReplicateI zero));
11465 predicate(n->as_Vector()->length() == 2);
11466 format %{ "LI $dst, #0 \t// replicate4C" %}
11467 size(4);
11468 ins_encode %{
11469 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11470 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11471 %}
11472 ins_pipe(pipe_class_default);
11473 %}
11474
11475 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11476 match(Set dst (ReplicateI src));
11477 predicate(n->as_Vector()->length() == 2);
11478 format %{ "LI $dst, -1 \t// replicate4C" %}
11479 size(4);
11480 ins_encode %{
11481 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11482 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11483 %}
11484 ins_pipe(pipe_class_default);
11485 %}
11486
11487 // Move float to int register via stack, replicate.
11488 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11489 match(Set dst (ReplicateF src));
11490 predicate(n->as_Vector()->length() == 2);
11491 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11492 expand %{
11493 stackSlotL tmpS;
11494 iRegIdst tmpI;
11495 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11496 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11497 moveReg(dst, tmpI); // Move int to long reg.
11498 repl32(dst); // Replicate bitpattern.
11499 %}
11500 %}
11501
11502 // Replicate scalar constant to packed float values in Double register
11503 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11504 match(Set dst (ReplicateF src));
11505 predicate(n->as_Vector()->length() == 2);
11506 ins_cost(5 * DEFAULT_COST);
11507
11508 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11509 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11510 %}
11511
11512 // Replicate scalar zero constant to packed float values in Double register
11513 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11514 match(Set dst (ReplicateF zero));
11515 predicate(n->as_Vector()->length() == 2);
11516
11517 format %{ "LI $dst, #0 \t// replicate2F" %}
11518 ins_encode %{
11519 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11520 __ li($dst$$Register, 0x0);
11521 %}
11522 ins_pipe(pipe_class_default);
11523 %}
11524
11525 // ============================================================================
11526 // Safepoint Instruction
11527
11528 instruct safePoint_poll(iRegPdst poll) %{
11529 match(SafePoint poll);
11530 predicate(LoadPollAddressFromThread);
11531
11532 // It caused problems to add the effect that r0 is killed, but this
11533 // effect no longer needs to be mentioned, since r0 is not contained
11534 // in a reg_class.
11535
11536 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11537 size(4);
11538 ins_encode( enc_poll(0x0, poll) );
11539 ins_pipe(pipe_class_default);
11540 %}
11541
11542 // Safepoint without per-thread support. Load address of page to poll
11543 // as constant.
11544 // Rscratch2RegP is R12.
11545 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11546 // a seperate node so that the oop map is at the right location.
11547 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11548 match(SafePoint poll);
11549 predicate(!LoadPollAddressFromThread);
11550
11551 // It caused problems to add the effect that r0 is killed, but this
11552 // effect no longer needs to be mentioned, since r0 is not contained
11553 // in a reg_class.
11554
11555 format %{ "LD R12, addr of polling page\n\t"
11556 "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11557 ins_encode( enc_poll(0x0, poll) );
11558 ins_pipe(pipe_class_default);
11559 %}
11560
11561 // ============================================================================
11562 // Call Instructions
11563
11564 // Call Java Static Instruction
11565
11566 // Schedulable version of call static node.
11567 instruct CallStaticJavaDirect(method meth) %{
11568 match(CallStaticJava);
11569 effect(USE meth);
11570 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11571 ins_cost(CALL_COST);
11572
11573 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11574
11575 format %{ "CALL,static $meth \t// ==> " %}
11576 size(4);
11577 ins_encode( enc_java_static_call(meth) );
11578 ins_pipe(pipe_class_call);
11579 %}
11580
11581 // Schedulable version of call static node.
11582 instruct CallStaticJavaDirectHandle(method meth) %{
11583 match(CallStaticJava);
11584 effect(USE meth);
11585 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11586 ins_cost(CALL_COST);
11587
11588 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11589
11590 format %{ "CALL,static $meth \t// ==> " %}
11591 ins_encode( enc_java_handle_call(meth) );
11592 ins_pipe(pipe_class_call);
11593 %}
11594
11595 // Call Java Dynamic Instruction
11596
11597 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11598 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11599 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11600 // The call destination must still be placed in the constant pool.
11601 instruct CallDynamicJavaDirectSched(method meth) %{
11602 match(CallDynamicJava); // To get all the data fields we need ...
11603 effect(USE meth);
11604 predicate(false); // ... but never match.
11605
11606 ins_field_load_ic_hi_node(loadConL_hiNode*);
11607 ins_field_load_ic_node(loadConLNode*);
11608 ins_num_consts(1 /* 1 patchable constant: call destination */);
11609
11610 format %{ "BL \t// dynamic $meth ==> " %}
11611 size(4);
11612 ins_encode( enc_java_dynamic_call_sched(meth) );
11613 ins_pipe(pipe_class_call);
11614 %}
11615
11616 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11617 // We use postalloc expanded calls if we use inline caches
11618 // and do not update method data.
11619 //
11620 // This instruction has two constants: inline cache (IC) and call destination.
11621 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11622 // one constant.
11623 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11624 match(CallDynamicJava);
11625 effect(USE meth);
11626 predicate(UseInlineCaches);
11627 ins_cost(CALL_COST);
11628
11629 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11630
11631 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11632 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11633 %}
11634
11635 // Compound version of call dynamic java
11636 // We use postalloc expanded calls if we use inline caches
11637 // and do not update method data.
11638 instruct CallDynamicJavaDirect(method meth) %{
11639 match(CallDynamicJava);
11640 effect(USE meth);
11641 predicate(!UseInlineCaches);
11642 ins_cost(CALL_COST);
11643
11644 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11645 ins_num_consts(4);
11646
11647 format %{ "CALL,dynamic $meth \t// ==> " %}
11648 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11649 ins_pipe(pipe_class_call);
11650 %}
11651
11652 // Call Runtime Instruction
11653
11654 instruct CallRuntimeDirect(method meth) %{
11655 match(CallRuntime);
11656 effect(USE meth);
11657 ins_cost(CALL_COST);
11658
11659 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11660 // env for callee, C-toc.
11661 ins_num_consts(3);
11662
11663 format %{ "CALL,runtime" %}
11664 ins_encode( enc_java_to_runtime_call(meth) );
11665 ins_pipe(pipe_class_call);
11666 %}
11667
11668 // Call Leaf
11669
11670 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11671 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11672 effect(DEF dst, USE src);
11673
11674 ins_num_consts(1);
11675
11676 format %{ "MTCTR $src" %}
11677 size(4);
11678 ins_encode( enc_leaf_call_mtctr(src) );
11679 ins_pipe(pipe_class_default);
11680 %}
11681
11682 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11683 instruct CallLeafDirect(method meth) %{
11684 match(CallLeaf); // To get the data all the data fields we need ...
11685 effect(USE meth);
11686 predicate(false); // but never match.
11687
11688 format %{ "BCTRL \t// leaf call $meth ==> " %}
11689 size(4);
11690 ins_encode %{
11691 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11692 __ bctrl();
11693 %}
11694 ins_pipe(pipe_class_call);
11695 %}
11696
11697 // postalloc expand of CallLeafDirect.
11698 // Load adress to call from TOC, then bl to it.
11699 instruct CallLeafDirect_Ex(method meth) %{
11700 match(CallLeaf);
11701 effect(USE meth);
11702 ins_cost(CALL_COST);
11703
11704 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11705 // env for callee, C-toc.
11706 ins_num_consts(3);
11707
11708 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11709 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11710 %}
11711
11712 // Call runtime without safepoint - same as CallLeaf.
11713 // postalloc expand of CallLeafNoFPDirect.
11714 // Load adress to call from TOC, then bl to it.
11715 instruct CallLeafNoFPDirect_Ex(method meth) %{
11716 match(CallLeafNoFP);
11717 effect(USE meth);
11718 ins_cost(CALL_COST);
11719
11720 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11721 // env for callee, C-toc.
11722 ins_num_consts(3);
11723
11724 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11725 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11726 %}
11727
11728 // Tail Call; Jump from runtime stub to Java code.
11729 // Also known as an 'interprocedural jump'.
11730 // Target of jump will eventually return to caller.
11731 // TailJump below removes the return address.
11732 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11733 match(TailCall jump_target method_oop);
11734 ins_cost(CALL_COST);
11735
11736 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11737 "BCTR \t// tail call" %}
11738 size(8);
11739 ins_encode %{
11740 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11741 __ mtctr($jump_target$$Register);
11742 __ bctr();
11743 %}
11744 ins_pipe(pipe_class_call);
11745 %}
11746
11747 // Return Instruction
11748 instruct Ret() %{
11749 match(Return);
11750 format %{ "BLR \t// branch to link register" %}
11751 size(4);
11752 ins_encode %{
11753 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11754 // LR is restored in MachEpilogNode. Just do the RET here.
11755 __ blr();
11756 %}
11757 ins_pipe(pipe_class_default);
11758 %}
11759
11760 // Tail Jump; remove the return address; jump to target.
11761 // TailCall above leaves the return address around.
11762 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11763 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11764 // "restore" before this instruction (in Epilogue), we need to materialize it
11765 // in %i0.
11766 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11767 match(TailJump jump_target ex_oop);
11768 ins_cost(CALL_COST);
11769
11770 format %{ "LD R4_ARG2 = LR\n\t"
11771 "MTCTR $jump_target\n\t"
11772 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11773 size(12);
11774 ins_encode %{
11775 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11776 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11777 __ mtctr($jump_target$$Register);
11778 __ bctr();
11779 %}
11780 ins_pipe(pipe_class_call);
11781 %}
11782
11783 // Create exception oop: created by stack-crawling runtime code.
11784 // Created exception is now available to this handler, and is setup
11785 // just prior to jumping to this handler. No code emitted.
11786 instruct CreateException(rarg1RegP ex_oop) %{
11787 match(Set ex_oop (CreateEx));
11788 ins_cost(0);
11789
11790 format %{ " -- \t// exception oop; no code emitted" %}
11791 size(0);
11792 ins_encode( /*empty*/ );
11793 ins_pipe(pipe_class_default);
11794 %}
11795
11796 // Rethrow exception: The exception oop will come in the first
11797 // argument position. Then JUMP (not call) to the rethrow stub code.
11798 instruct RethrowException() %{
11799 match(Rethrow);
11800 ins_cost(CALL_COST);
11801
11802 format %{ "Jmp rethrow_stub" %}
11803 ins_encode %{
11804 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11805 cbuf.set_insts_mark();
11806 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11807 %}
11808 ins_pipe(pipe_class_call);
11809 %}
11810
11811 // Die now.
11812 instruct ShouldNotReachHere() %{
11813 match(Halt);
11814 ins_cost(CALL_COST);
11815
11816 format %{ "ShouldNotReachHere" %}
11817 size(4);
11818 ins_encode %{
11819 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11820 __ trap_should_not_reach_here();
11821 %}
11822 ins_pipe(pipe_class_default);
11823 %}
11824
11825 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11826 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11827 // Get a DEF on threadRegP, no costs, no encoding, use
11828 // 'ins_should_rematerialize(true)' to avoid spilling.
11829 instruct tlsLoadP(threadRegP dst) %{
11830 match(Set dst (ThreadLocal));
11831 ins_cost(0);
11832
11833 ins_should_rematerialize(true);
11834
11835 format %{ " -- \t// $dst=Thread::current(), empty" %}
11836 size(0);
11837 ins_encode( /*empty*/ );
11838 ins_pipe(pipe_class_empty);
11839 %}
11840
11841 //---Some PPC specific nodes---------------------------------------------------
11842
11843 // Stop a group.
11844 instruct endGroup() %{
11845 ins_cost(0);
11846
11847 ins_is_nop(true);
11848
11849 format %{ "End Bundle (ori r1, r1, 0)" %}
11850 size(4);
11851 ins_encode %{
11852 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11853 __ endgroup();
11854 %}
11855 ins_pipe(pipe_class_default);
11856 %}
11857
11858 // Nop instructions
11859
11860 instruct fxNop() %{
11861 ins_cost(0);
11862
11863 ins_is_nop(true);
11864
11865 format %{ "fxNop" %}
11866 size(4);
11867 ins_encode %{
11868 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11869 __ nop();
11870 %}
11871 ins_pipe(pipe_class_default);
11872 %}
11873
11874 instruct fpNop0() %{
11875 ins_cost(0);
11876
11877 ins_is_nop(true);
11878
11879 format %{ "fpNop0" %}
11880 size(4);
11881 ins_encode %{
11882 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11883 __ fpnop0();
11884 %}
11885 ins_pipe(pipe_class_default);
11886 %}
11887
11888 instruct fpNop1() %{
11889 ins_cost(0);
11890
11891 ins_is_nop(true);
11892
11893 format %{ "fpNop1" %}
11894 size(4);
11895 ins_encode %{
11896 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11897 __ fpnop1();
11898 %}
11899 ins_pipe(pipe_class_default);
11900 %}
11901
11902 instruct brNop0() %{
11903 ins_cost(0);
11904 size(4);
11905 format %{ "brNop0" %}
11906 ins_encode %{
11907 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11908 __ brnop0();
11909 %}
11910 ins_is_nop(true);
11911 ins_pipe(pipe_class_default);
11912 %}
11913
11914 instruct brNop1() %{
11915 ins_cost(0);
11916
11917 ins_is_nop(true);
11918
11919 format %{ "brNop1" %}
11920 size(4);
11921 ins_encode %{
11922 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11923 __ brnop1();
11924 %}
11925 ins_pipe(pipe_class_default);
11926 %}
11927
11928 instruct brNop2() %{
11929 ins_cost(0);
11930
11931 ins_is_nop(true);
11932
11933 format %{ "brNop2" %}
11934 size(4);
11935 ins_encode %{
11936 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11937 __ brnop2();
11938 %}
11939 ins_pipe(pipe_class_default);
11940 %}
11941
11942 //----------PEEPHOLE RULES-----------------------------------------------------
11943 // These must follow all instruction definitions as they use the names
11944 // defined in the instructions definitions.
11945 //
11946 // peepmatch ( root_instr_name [preceeding_instruction]* );
11947 //
11948 // peepconstraint %{
11949 // (instruction_number.operand_name relational_op instruction_number.operand_name
11950 // [, ...] );
11951 // // instruction numbers are zero-based using left to right order in peepmatch
11952 //
11953 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11954 // // provide an instruction_number.operand_name for each operand that appears
11955 // // in the replacement instruction's match rule
11956 //
11957 // ---------VM FLAGS---------------------------------------------------------
11958 //
11959 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11960 //
11961 // Each peephole rule is given an identifying number starting with zero and
11962 // increasing by one in the order seen by the parser. An individual peephole
11963 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11964 // on the command-line.
11965 //
11966 // ---------CURRENT LIMITATIONS----------------------------------------------
11967 //
11968 // Only match adjacent instructions in same basic block
11969 // Only equality constraints
11970 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11971 // Only one replacement instruction
11972 //
11973 // ---------EXAMPLE----------------------------------------------------------
11974 //
11975 // // pertinent parts of existing instructions in architecture description
11976 // instruct movI(eRegI dst, eRegI src) %{
11977 // match(Set dst (CopyI src));
11978 // %}
11979 //
11980 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
11981 // match(Set dst (AddI dst src));
11982 // effect(KILL cr);
11983 // %}
11984 //
11985 // // Change (inc mov) to lea
11986 // peephole %{
11987 // // increment preceeded by register-register move
11988 // peepmatch ( incI_eReg movI );
11989 // // require that the destination register of the increment
11990 // // match the destination register of the move
11991 // peepconstraint ( 0.dst == 1.dst );
11992 // // construct a replacement instruction that sets
11993 // // the destination to ( move's source register + one )
11994 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
11995 // %}
11996 //
11997 // Implementation no longer uses movX instructions since
11998 // machine-independent system no longer uses CopyX nodes.
11999 //
12000 // peephole %{
12001 // peepmatch ( incI_eReg movI );
12002 // peepconstraint ( 0.dst == 1.dst );
12003 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12004 // %}
12005 //
12006 // peephole %{
12007 // peepmatch ( decI_eReg movI );
12008 // peepconstraint ( 0.dst == 1.dst );
12009 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12010 // %}
12011 //
12012 // peephole %{
12013 // peepmatch ( addI_eReg_imm movI );
12014 // peepconstraint ( 0.dst == 1.dst );
12015 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12016 // %}
12017 //
12018 // peephole %{
12019 // peepmatch ( addP_eReg_imm movP );
12020 // peepconstraint ( 0.dst == 1.dst );
12021 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12022 // %}
12023
12024 // // Change load of spilled value to only a spill
12025 // instruct storeI(memory mem, eRegI src) %{
12026 // match(Set mem (StoreI mem src));
12027 // %}
12028 //
12029 // instruct loadI(eRegI dst, memory mem) %{
12030 // match(Set dst (LoadI mem));
12031 // %}
12032 //
12033 peephole %{
12034 peepmatch ( loadI storeI );
12035 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12036 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12037 %}
12038
12039 peephole %{
12040 peepmatch ( loadL storeL );
12041 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12042 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12043 %}
12044
12045 peephole %{
12046 peepmatch ( loadP storeP );
12047 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12048 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12049 %}
12050
12051 //----------SMARTSPILL RULES---------------------------------------------------
12052 // These must follow all instruction definitions as they use the names
12053 // defined in the instructions definitions.