1 //
2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2013 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Returns true if Node n is followed by a MemBar node that
895 // will do an acquire. If so, this node must not do the acquire
896 // operation.
897 bool followed_by_acquire(const Node *n);
898 %}
899
900 source %{
901
902 // Optimize load-acquire.
903 //
904 // Check if acquire is unnecessary due to following operation that does
905 // acquire anyways.
906 // Walk the pattern:
907 //
908 // n: Load.acq
909 // |
910 // MemBarAcquire
911 // | |
912 // Proj(ctrl) Proj(mem)
913 // | |
914 // MemBarRelease/Volatile
915 //
916 bool followed_by_acquire(const Node *load) {
917 assert(load->is_Load(), "So far implemented only for loads.");
918
919 // Find MemBarAcquire.
920 const Node *mba = NULL;
921 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
922 const Node *out = load->fast_out(i);
923 if (out->Opcode() == Op_MemBarAcquire) {
924 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
925 mba = out;
926 break;
927 }
928 }
929 if (!mba) return false;
930
931 // Find following MemBar node.
932 //
933 // The following node must be reachable by control AND memory
934 // edge to assure no other operations are in between the two nodes.
935 //
936 // So first get the Proj node, mem_proj, to use it to iterate forward.
937 Node *mem_proj = NULL;
938 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
939 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
940 assert(mem_proj->is_Proj(), "only projections here");
941 ProjNode *proj = mem_proj->as_Proj();
942 if (proj->_con == TypeFunc::Memory &&
943 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
944 break;
945 }
946 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
947
948 // Search MemBar behind Proj. If there are other memory operations
949 // behind the Proj we lost.
950 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
951 Node *x = mem_proj->fast_out(j);
952 // Proj might have an edge to a store or load node which precedes the membar.
953 if (x->is_Mem()) return false;
954
955 // On PPC64 release and volatile are implemented by an instruction
956 // that also has acquire semantics. I.e. there is no need for an
957 // acquire before these.
958 int xop = x->Opcode();
959 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
960 // Make sure we're not missing Call/Phi/MergeMem by checking
961 // control edges. The control edge must directly lead back
962 // to the MemBarAcquire
963 Node *ctrl_proj = x->in(0);
964 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
965 return true;
966 }
967 }
968 }
969
970 return false;
971 }
972
973 #define __ _masm.
974
975 // Tertiary op of a LoadP or StoreP encoding.
976 #define REGP_OP true
977
978 // ****************************************************************************
979
980 // REQUIRED FUNCTIONALITY
981
982 // !!!!! Special hack to get all type of calls to specify the byte offset
983 // from the start of the call to the point where the return address
984 // will point.
985
986 // PPC port: Removed use of lazy constant construct.
987
988 int MachCallStaticJavaNode::ret_addr_offset() {
989 // It's only a single branch-and-link instruction.
990 return 4;
991 }
992
993 int MachCallDynamicJavaNode::ret_addr_offset() {
994 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
995 // postalloc expanded calls if we use inline caches and do not update method data.
996 if (UseInlineCaches)
997 return 4;
998
999 int vtable_index = this->_vtable_index;
1000 if (vtable_index < 0) {
1001 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1002 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1003 return 12;
1004 } else {
1005 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1006 return 24;
1007 }
1008 }
1009
1010 int MachCallRuntimeNode::ret_addr_offset() {
1011 return 40;
1012 }
1013
1014 //=============================================================================
1015
1016 // condition code conversions
1017
1018 static int cc_to_boint(int cc) {
1019 return Assembler::bcondCRbiIs0 | (cc & 8);
1020 }
1021
1022 static int cc_to_inverse_boint(int cc) {
1023 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1024 }
1025
1026 static int cc_to_biint(int cc, int flags_reg) {
1027 return (flags_reg << 2) | (cc & 3);
1028 }
1029
1030 //=============================================================================
1031
1032 // Compute padding required for nodes which need alignment. The padding
1033 // is the number of bytes (not instructions) which will be inserted before
1034 // the instruction. The padding must match the size of a NOP instruction.
1035
1036 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1037 return (3*4-current_offset)&31;
1038 }
1039
1040 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1041 return (2*4-current_offset)&31;
1042 }
1043
1044 int string_indexOf_immNode::compute_padding(int current_offset) const {
1045 return (3*4-current_offset)&31;
1046 }
1047
1048 int string_indexOfNode::compute_padding(int current_offset) const {
1049 return (1*4-current_offset)&31;
1050 }
1051
1052 int string_compareNode::compute_padding(int current_offset) const {
1053 return (4*4-current_offset)&31;
1054 }
1055
1056 int string_equals_immNode::compute_padding(int current_offset) const {
1057 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1058 return (2*4-current_offset)&31;
1059 }
1060
1061 int string_equalsNode::compute_padding(int current_offset) const {
1062 return (7*4-current_offset)&31;
1063 }
1064
1065 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1066 return (2*4-current_offset)&31;
1067 }
1068
1069 //=============================================================================
1070
1071 // Indicate if the safepoint node needs the polling page as an input.
1072 bool SafePointNode::needs_polling_address_input() {
1073 // The address is loaded from thread by a seperate node.
1074 return true;
1075 }
1076
1077 //=============================================================================
1078
1079 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1080 void emit_break(CodeBuffer &cbuf) {
1081 MacroAssembler _masm(&cbuf);
1082 __ illtrap();
1083 }
1084
1085 #ifndef PRODUCT
1086 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1087 st->print("BREAKPOINT");
1088 }
1089 #endif
1090
1091 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1092 emit_break(cbuf);
1093 }
1094
1095 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1096 return MachNode::size(ra_);
1097 }
1098
1099 //=============================================================================
1100
1101 void emit_nop(CodeBuffer &cbuf) {
1102 MacroAssembler _masm(&cbuf);
1103 __ nop();
1104 }
1105
1106 static inline void emit_long(CodeBuffer &cbuf, int value) {
1107 *((int*)(cbuf.insts_end())) = value;
1108 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1109 }
1110
1111 //=============================================================================
1112
1113 // Emit a trampoline stub for a call to a target which is too far away.
1114 //
1115 // code sequences:
1116 //
1117 // call-site:
1118 // branch-and-link to <destination> or <trampoline stub>
1119 //
1120 // Related trampoline stub for this call-site in the stub section:
1121 // load the call target from the constant pool
1122 // branch via CTR (LR/link still points to the call-site above)
1123
1124 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1125
1126 void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1127 // Start the stub.
1128 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1129 if (stub == NULL) {
1130 Compile::current()->env()->record_out_of_memory_failure();
1131 return;
1132 }
1133
1134 // For java_to_interp stubs we use R11_scratch1 as scratch register
1135 // and in call trampoline stubs we use R12_scratch2. This way we
1136 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1137 Register reg_scratch = R12_scratch2;
1138
1139 // Create a trampoline stub relocation which relates this trampoline stub
1140 // with the call instruction at insts_call_instruction_offset in the
1141 // instructions code-section.
1142 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1143 const int stub_start_offset = __ offset();
1144
1145 // Now, create the trampoline stub's code:
1146 // - load the TOC
1147 // - load the call target from the constant pool
1148 // - call
1149 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1150 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1151 __ mtctr(reg_scratch);
1152 __ bctr();
1153
1154 const address stub_start_addr = __ addr_at(stub_start_offset);
1155
1156 // FIXME: Assert that the trampoline stub can be identified and patched.
1157
1158 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1159 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1160 "encoded offset into the constant pool must match");
1161 // Trampoline_stub_size should be good.
1162 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1163 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1164
1165 // End the stub.
1166 __ end_a_stub();
1167 }
1168
1169 // Size of trampoline stub, this doesn't need to be accurate but it must
1170 // be larger or equal to the real size of the stub.
1171 // Used for optimization in Compile::Shorten_branches.
1172 uint size_call_trampoline() {
1173 return trampoline_stub_size;
1174 }
1175
1176 // Number of relocation entries needed by trampoline stub.
1177 // Used for optimization in Compile::Shorten_branches.
1178 uint reloc_call_trampoline() {
1179 return 5;
1180 }
1181
1182 //=============================================================================
1183
1184 // Emit an inline branch-and-link call and a related trampoline stub.
1185 //
1186 // code sequences:
1187 //
1188 // call-site:
1189 // branch-and-link to <destination> or <trampoline stub>
1190 //
1191 // Related trampoline stub for this call-site in the stub section:
1192 // load the call target from the constant pool
1193 // branch via CTR (LR/link still points to the call-site above)
1194 //
1195
1196 typedef struct {
1197 int insts_call_instruction_offset;
1198 int ret_addr_offset;
1199 } EmitCallOffsets;
1200
1201 // Emit a branch-and-link instruction that branches to a trampoline.
1202 // - Remember the offset of the branch-and-link instruction.
1203 // - Add a relocation at the branch-and-link instruction.
1204 // - Emit a branch-and-link.
1205 // - Remember the return pc offset.
1206 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1207 EmitCallOffsets offsets = { -1, -1 };
1208 const int start_offset = __ offset();
1209 offsets.insts_call_instruction_offset = __ offset();
1210
1211 // No entry point given, use the current pc.
1212 if (entry_point == NULL) entry_point = __ pc();
1213
1214 if (!Compile::current()->in_scratch_emit_size()) {
1215 // Put the entry point as a constant into the constant pool.
1216 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1217 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1218
1219 // Emit the trampoline stub which will be related to the branch-and-link below.
1220 emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1221 __ relocate(rtype);
1222 }
1223
1224 // Note: At this point we do not have the address of the trampoline
1225 // stub, and the entry point might be too far away for bl, so __ pc()
1226 // serves as dummy and the bl will be patched later.
1227 __ bl((address) __ pc());
1228
1229 offsets.ret_addr_offset = __ offset() - start_offset;
1230
1231 return offsets;
1232 }
1233
1234 //=============================================================================
1235
1236 // Factory for creating loadConL* nodes for large/small constant pool.
1237
1238 static inline jlong replicate_immF(float con) {
1239 // Replicate float con 2 times and pack into vector.
1240 int val = *((int*)&con);
1241 jlong lval = val;
1242 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1243 return lval;
1244 }
1245
1246 //=============================================================================
1247
1248 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1249 int Compile::ConstantTable::calculate_table_base_offset() const {
1250 return 0; // absolute addressing, no offset
1251 }
1252
1253 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1254 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1255 Compile *C = ra_->C;
1256
1257 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1258 MachNode *m1 = new (C) loadToc_hiNode();
1259 MachNode *m2 = new (C) loadToc_loNode();
1260
1261 m1->add_req(NULL);
1262 m2->add_req(NULL, m1);
1263 m1->_opnds[0] = op_dst;
1264 m2->_opnds[0] = op_dst;
1265 m2->_opnds[1] = op_dst;
1266 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1267 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1268 nodes->push(m1);
1269 nodes->push(m2);
1270 }
1271
1272 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1273 // Is postalloc expanded.
1274 ShouldNotReachHere();
1275 }
1276
1277 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1278 return 0;
1279 }
1280
1281 #ifndef PRODUCT
1282 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1283 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1284 }
1285 #endif
1286
1287 //=============================================================================
1288
1289 #ifndef PRODUCT
1290 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1291 Compile* C = ra_->C;
1292 const long framesize = C->frame_slots() << LogBytesPerInt;
1293
1294 st->print("PROLOG\n\t");
1295 if (C->need_stack_bang(framesize)) {
1296 st->print("stack_overflow_check\n\t");
1297 }
1298
1299 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1300 st->print("save return pc\n\t");
1301 st->print("push frame %d\n\t", -framesize);
1302 }
1303 }
1304 #endif
1305
1306 // Macro used instead of the common __ to emulate the pipes of PPC.
1307 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1308 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1309 // still no scheduling of this code is possible, the micro scheduler is aware of the
1310 // code and can update its internal data. The following mechanism is used to achieve this:
1311 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1312 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1313 #if 0 // TODO: PPC port
1314 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1315 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1316 _masm.
1317 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1318 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1319 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1320 C->hb_scheduling()->_pdScheduling->advance_offset
1321 #else
1322 #define ___(op) if (UsePower6SchedulerPPC64) \
1323 Unimplemented(); \
1324 _masm.
1325 #define ___stop if (UsePower6SchedulerPPC64) \
1326 Unimplemented()
1327 #define ___advance if (UsePower6SchedulerPPC64) \
1328 Unimplemented()
1329 #endif
1330
1331 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1332 Compile* C = ra_->C;
1333 MacroAssembler _masm(&cbuf);
1334
1335 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1336 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1337
1338 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1339
1340 const Register return_pc = R20; // Must match return_addr() in frame section.
1341 const Register callers_sp = R21;
1342 const Register push_frame_temp = R22;
1343 const Register toc_temp = R23;
1344 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1345
1346 if (method_is_frameless) {
1347 // Add nop at beginning of all frameless methods to prevent any
1348 // oop instructions from getting overwritten by make_not_entrant
1349 // (patching attempt would fail).
1350 ___(nop) nop();
1351 } else {
1352 // Get return pc.
1353 ___(mflr) mflr(return_pc);
1354 }
1355
1356 // Calls to C2R adapters often do not accept exceptional returns.
1357 // We require that their callers must bang for them. But be
1358 // careful, because some VM calls (such as call site linkage) can
1359 // use several kilobytes of stack. But the stack safety zone should
1360 // account for that. See bugs 4446381, 4468289, 4497237.
1361 if (C->need_stack_bang(framesize) && UseStackBanging) {
1362 // Unfortunately we cannot use the function provided in
1363 // assembler.cpp as we have to emulate the pipes. So I had to
1364 // insert the code of generate_stack_overflow_check(), see
1365 // assembler.cpp for some illuminative comments.
1366 const int page_size = os::vm_page_size();
1367 int bang_end = StackShadowPages*page_size;
1368
1369 // This is how far the previous frame's stack banging extended.
1370 const int bang_end_safe = bang_end;
1371
1372 if (framesize > page_size) {
1373 bang_end += framesize;
1374 }
1375
1376 int bang_offset = bang_end_safe;
1377
1378 while (bang_offset <= bang_end) {
1379 // Need at least one stack bang at end of shadow zone.
1380
1381 // Again I had to copy code, this time from assembler_ppc64.cpp,
1382 // bang_stack_with_offset - see there for comments.
1383
1384 // Stack grows down, caller passes positive offset.
1385 assert(bang_offset > 0, "must bang with positive offset");
1386
1387 long stdoffset = -bang_offset;
1388
1389 if (Assembler::is_simm(stdoffset, 16)) {
1390 // Signed 16 bit offset, a simple std is ok.
1391 if (UseLoadInstructionsForStackBangingPPC64) {
1392 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1393 } else {
1394 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1395 }
1396 } else if (Assembler::is_simm(stdoffset, 31)) {
1397 // Use largeoffset calculations for addis & ld/std.
1398 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1399 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1400
1401 Register tmp = R11;
1402 ___(addis) addis(tmp, R1_SP, hi);
1403 if (UseLoadInstructionsForStackBangingPPC64) {
1404 ___(ld) ld(R0, lo, tmp);
1405 } else {
1406 ___(std) std(R0, lo, tmp);
1407 }
1408 } else {
1409 ShouldNotReachHere();
1410 }
1411
1412 bang_offset += page_size;
1413 }
1414 // R11 trashed
1415 } // C->need_stack_bang(framesize) && UseStackBanging
1416
1417 unsigned int bytes = (unsigned int)framesize;
1418 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1419 ciMethod *currMethod = C -> method();
1420
1421 // Optimized version for most common case.
1422 if (UsePower6SchedulerPPC64 &&
1423 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1424 !(false /* ConstantsALot TODO: PPC port*/)) {
1425 ___(or) mr(callers_sp, R1_SP);
1426 ___(std) std(return_pc, _abi(lr), R1_SP);
1427 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1428 return;
1429 }
1430
1431 if (!method_is_frameless) {
1432 // Get callers sp.
1433 ___(or) mr(callers_sp, R1_SP);
1434
1435 // Push method's frame, modifies SP.
1436 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1437 // The ABI is already accounted for in 'framesize' via the
1438 // 'out_preserve' area.
1439 Register tmp = push_frame_temp;
1440 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1441 if (Assembler::is_simm(-offset, 16)) {
1442 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1443 } else {
1444 long x = -offset;
1445 // Had to insert load_const(tmp, -offset).
1446 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1447 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1448 ___(rldicr) sldi(tmp, tmp, 32);
1449 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1450 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1451
1452 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1453 }
1454 }
1455 #if 0 // TODO: PPC port
1456 // For testing large constant pools, emit a lot of constants to constant pool.
1457 // "Randomize" const_size.
1458 if (ConstantsALot) {
1459 const int num_consts = const_size();
1460 for (int i = 0; i < num_consts; i++) {
1461 __ long_constant(0xB0B5B00BBABE);
1462 }
1463 }
1464 #endif
1465 if (!method_is_frameless) {
1466 // Save return pc.
1467 ___(std) std(return_pc, _abi(lr), callers_sp);
1468 }
1469 }
1470 #undef ___
1471 #undef ___stop
1472 #undef ___advance
1473
1474 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1475 // Variable size. determine dynamically.
1476 return MachNode::size(ra_);
1477 }
1478
1479 int MachPrologNode::reloc() const {
1480 // Return number of relocatable values contained in this instruction.
1481 return 1; // 1 reloc entry for load_const(toc).
1482 }
1483
1484 //=============================================================================
1485
1486 #ifndef PRODUCT
1487 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1488 Compile* C = ra_->C;
1489
1490 st->print("EPILOG\n\t");
1491 st->print("restore return pc\n\t");
1492 st->print("pop frame\n\t");
1493
1494 if (do_polling() && C->is_method_compilation()) {
1495 st->print("touch polling page\n\t");
1496 }
1497 }
1498 #endif
1499
1500 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1501 Compile* C = ra_->C;
1502 MacroAssembler _masm(&cbuf);
1503
1504 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1505 assert(framesize >= 0, "negative frame-size?");
1506
1507 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1508 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1509 const Register return_pc = R11;
1510 const Register polling_page = R12;
1511
1512 if (!method_is_frameless) {
1513 // Restore return pc relative to callers' sp.
1514 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1515 }
1516
1517 if (method_needs_polling) {
1518 if (LoadPollAddressFromThread) {
1519 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1520 Unimplemented();
1521 } else {
1522 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1523 }
1524 }
1525
1526 if (!method_is_frameless) {
1527 // Move return pc to LR.
1528 __ mtlr(return_pc);
1529 // Pop frame (fixed frame-size).
1530 __ addi(R1_SP, R1_SP, (int)framesize);
1531 }
1532
1533 if (method_needs_polling) {
1534 // We need to mark the code position where the load from the safepoint
1535 // polling page was emitted as relocInfo::poll_return_type here.
1536 __ relocate(relocInfo::poll_return_type);
1537 __ load_from_polling_page(polling_page);
1538 }
1539 }
1540
1541 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1542 // Variable size. Determine dynamically.
1543 return MachNode::size(ra_);
1544 }
1545
1546 int MachEpilogNode::reloc() const {
1547 // Return number of relocatable values contained in this instruction.
1548 return 1; // 1 for load_from_polling_page.
1549 }
1550
1551 const Pipeline * MachEpilogNode::pipeline() const {
1552 return MachNode::pipeline_class();
1553 }
1554
1555 // This method seems to be obsolete. It is declared in machnode.hpp
1556 // and defined in all *.ad files, but it is never called. Should we
1557 // get rid of it?
1558 int MachEpilogNode::safepoint_offset() const {
1559 assert(do_polling(), "no return for this epilog node");
1560 return 0;
1561 }
1562
1563 #if 0 // TODO: PPC port
1564 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1565 MacroAssembler _masm(&cbuf);
1566 if (LoadPollAddressFromThread) {
1567 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1568 } else {
1569 _masm.nop();
1570 }
1571 }
1572
1573 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1574 if (LoadPollAddressFromThread) {
1575 return 4;
1576 } else {
1577 return 4;
1578 }
1579 }
1580
1581 #ifndef PRODUCT
1582 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1583 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1584 }
1585 #endif
1586
1587 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1588 return RSCRATCH1_BITS64_REG_mask();
1589 }
1590 #endif // PPC port
1591
1592 // =============================================================================
1593
1594 // Figure out which register class each belongs in: rc_int, rc_float or
1595 // rc_stack.
1596 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1597
1598 static enum RC rc_class(OptoReg::Name reg) {
1599 // Return the register class for the given register. The given register
1600 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1601 // enumeration in adGlobals_ppc64.hpp.
1602
1603 if (reg == OptoReg::Bad) return rc_bad;
1604
1605 // We have 64 integer register halves, starting at index 0.
1606 if (reg < 64) return rc_int;
1607
1608 // We have 64 floating-point register halves, starting at index 64.
1609 if (reg < 64+64) return rc_float;
1610
1611 // Between float regs & stack are the flags regs.
1612 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1613
1614 return rc_stack;
1615 }
1616
1617 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1618 bool do_print, Compile* C, outputStream *st) {
1619
1620 assert(opcode == Assembler::LD_OPCODE ||
1621 opcode == Assembler::STD_OPCODE ||
1622 opcode == Assembler::LWZ_OPCODE ||
1623 opcode == Assembler::STW_OPCODE ||
1624 opcode == Assembler::LFD_OPCODE ||
1625 opcode == Assembler::STFD_OPCODE ||
1626 opcode == Assembler::LFS_OPCODE ||
1627 opcode == Assembler::STFS_OPCODE,
1628 "opcode not supported");
1629
1630 if (cbuf) {
1631 int d =
1632 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1633 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1634 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1635 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1636 }
1637 #ifndef PRODUCT
1638 else if (do_print) {
1639 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1640 op_str,
1641 Matcher::regName[reg],
1642 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1643 }
1644 #endif
1645 return 4; // size
1646 }
1647
1648 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1649 Compile* C = ra_->C;
1650
1651 // Get registers to move.
1652 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1653 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1654 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1655 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1656
1657 enum RC src_hi_rc = rc_class(src_hi);
1658 enum RC src_lo_rc = rc_class(src_lo);
1659 enum RC dst_hi_rc = rc_class(dst_hi);
1660 enum RC dst_lo_rc = rc_class(dst_lo);
1661
1662 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1663 if (src_hi != OptoReg::Bad)
1664 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1665 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1666 "expected aligned-adjacent pairs");
1667 // Generate spill code!
1668 int size = 0;
1669
1670 if (src_lo == dst_lo && src_hi == dst_hi)
1671 return size; // Self copy, no move.
1672
1673 // --------------------------------------
1674 // Memory->Memory Spill. Use R0 to hold the value.
1675 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1676 int src_offset = ra_->reg2offset(src_lo);
1677 int dst_offset = ra_->reg2offset(dst_lo);
1678 if (src_hi != OptoReg::Bad) {
1679 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1680 "expected same type of move for high parts");
1681 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1682 if (!cbuf && !do_size) st->print("\n\t");
1683 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1684 } else {
1685 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1686 if (!cbuf && !do_size) st->print("\n\t");
1687 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1688 }
1689 return size;
1690 }
1691
1692 // --------------------------------------
1693 // Check for float->int copy; requires a trip through memory.
1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1695 Unimplemented();
1696 }
1697
1698 // --------------------------------------
1699 // Check for integer reg-reg copy.
1700 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1701 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1702 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1703 size = (Rsrc != Rdst) ? 4 : 0;
1704
1705 if (cbuf) {
1706 MacroAssembler _masm(cbuf);
1707 if (size) {
1708 __ mr(Rdst, Rsrc);
1709 }
1710 }
1711 #ifndef PRODUCT
1712 else if (!do_size) {
1713 if (size) {
1714 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1715 } else {
1716 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1717 }
1718 }
1719 #endif
1720 return size;
1721 }
1722
1723 // Check for integer store.
1724 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1725 int dst_offset = ra_->reg2offset(dst_lo);
1726 if (src_hi != OptoReg::Bad) {
1727 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1728 "expected same type of move for high parts");
1729 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1730 } else {
1731 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1732 }
1733 return size;
1734 }
1735
1736 // Check for integer load.
1737 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1738 int src_offset = ra_->reg2offset(src_lo);
1739 if (src_hi != OptoReg::Bad) {
1740 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1741 "expected same type of move for high parts");
1742 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1743 } else {
1744 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1745 }
1746 return size;
1747 }
1748
1749 // Check for float reg-reg copy.
1750 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1751 if (cbuf) {
1752 MacroAssembler _masm(cbuf);
1753 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1754 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1755 __ fmr(Rdst, Rsrc);
1756 }
1757 #ifndef PRODUCT
1758 else if (!do_size) {
1759 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1760 }
1761 #endif
1762 return 4;
1763 }
1764
1765 // Check for float store.
1766 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1767 int dst_offset = ra_->reg2offset(dst_lo);
1768 if (src_hi != OptoReg::Bad) {
1769 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1770 "expected same type of move for high parts");
1771 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1772 } else {
1773 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1774 }
1775 return size;
1776 }
1777
1778 // Check for float load.
1779 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1780 int src_offset = ra_->reg2offset(src_lo);
1781 if (src_hi != OptoReg::Bad) {
1782 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1783 "expected same type of move for high parts");
1784 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1785 } else {
1786 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1787 }
1788 return size;
1789 }
1790
1791 // --------------------------------------------------------------------
1792 // Check for hi bits still needing moving. Only happens for misaligned
1793 // arguments to native calls.
1794 if (src_hi == dst_hi)
1795 return size; // Self copy; no move.
1796
1797 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1798 ShouldNotReachHere(); // Unimplemented
1799 return 0;
1800 }
1801
1802 #ifndef PRODUCT
1803 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1804 if (!ra_)
1805 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1806 else
1807 implementation(NULL, ra_, false, st);
1808 }
1809 #endif
1810
1811 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1812 implementation(&cbuf, ra_, false, NULL);
1813 }
1814
1815 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1816 return implementation(NULL, ra_, true, NULL);
1817 }
1818
1819 #if 0 // TODO: PPC port
1820 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1821 #ifndef PRODUCT
1822 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1823 #endif
1824 assert(ra_->node_regs_max_index() != 0, "");
1825
1826 // Get registers to move.
1827 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1828 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1829 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1830 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1831
1832 enum RC src_lo_rc = rc_class(src_lo);
1833 enum RC dst_lo_rc = rc_class(dst_lo);
1834
1835 if (src_lo == dst_lo && src_hi == dst_hi)
1836 return ppc64Opcode_none; // Self copy, no move.
1837
1838 // --------------------------------------
1839 // Memory->Memory Spill. Use R0 to hold the value.
1840 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1841 return ppc64Opcode_compound;
1842 }
1843
1844 // --------------------------------------
1845 // Check for float->int copy; requires a trip through memory.
1846 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1847 Unimplemented();
1848 }
1849
1850 // --------------------------------------
1851 // Check for integer reg-reg copy.
1852 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1853 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1854 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1855 if (Rsrc == Rdst) {
1856 return ppc64Opcode_none;
1857 } else {
1858 return ppc64Opcode_or;
1859 }
1860 }
1861
1862 // Check for integer store.
1863 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1864 if (src_hi != OptoReg::Bad) {
1865 return ppc64Opcode_std;
1866 } else {
1867 return ppc64Opcode_stw;
1868 }
1869 }
1870
1871 // Check for integer load.
1872 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1873 if (src_hi != OptoReg::Bad) {
1874 return ppc64Opcode_ld;
1875 } else {
1876 return ppc64Opcode_lwz;
1877 }
1878 }
1879
1880 // Check for float reg-reg copy.
1881 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1882 return ppc64Opcode_fmr;
1883 }
1884
1885 // Check for float store.
1886 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1887 if (src_hi != OptoReg::Bad) {
1888 return ppc64Opcode_stfd;
1889 } else {
1890 return ppc64Opcode_stfs;
1891 }
1892 }
1893
1894 // Check for float load.
1895 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1896 if (src_hi != OptoReg::Bad) {
1897 return ppc64Opcode_lfd;
1898 } else {
1899 return ppc64Opcode_lfs;
1900 }
1901 }
1902
1903 // --------------------------------------------------------------------
1904 // Check for hi bits still needing moving. Only happens for misaligned
1905 // arguments to native calls.
1906 if (src_hi == dst_hi)
1907 return ppc64Opcode_none; // Self copy; no move.
1908
1909 ShouldNotReachHere();
1910 return ppc64Opcode_undefined;
1911 }
1912 #endif // PPC port
1913
1914 #ifndef PRODUCT
1915 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1916 st->print("NOP \t// %d nops to pad for loops.", _count);
1917 }
1918 #endif
1919
1920 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1921 MacroAssembler _masm(&cbuf);
1922 // _count contains the number of nops needed for padding.
1923 for (int i = 0; i < _count; i++) {
1924 __ nop();
1925 }
1926 }
1927
1928 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1929 return _count * 4;
1930 }
1931
1932 #ifndef PRODUCT
1933 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1934 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1935 int reg = ra_->get_reg_first(this);
1936 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1937 }
1938 #endif
1939
1940 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1941 MacroAssembler _masm(&cbuf);
1942
1943 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1944 int reg = ra_->get_encode(this);
1945
1946 if (Assembler::is_simm(offset, 16)) {
1947 __ addi(as_Register(reg), R1, offset);
1948 } else {
1949 ShouldNotReachHere();
1950 }
1951 }
1952
1953 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1954 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1955 return 4;
1956 }
1957
1958 #ifndef PRODUCT
1959 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1960 st->print_cr("---- MachUEPNode ----");
1961 st->print_cr("...");
1962 }
1963 #endif
1964
1965 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1966 // This is the unverified entry point.
1967 MacroAssembler _masm(&cbuf);
1968
1969 // Inline_cache contains a klass.
1970 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1971 Register receiver_klass = R0; // tmp
1972
1973 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1974 assert(R11_scratch1 == R11, "need prologue scratch register");
1975
1976 // Check for NULL argument if we don't have implicit null checks.
1977 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1978 if (TrapBasedNullChecks) {
1979 __ trap_null_check(R3_ARG1);
1980 } else {
1981 Label valid;
1982 __ cmpdi(CCR0, R3_ARG1, 0);
1983 __ bne_predict_taken(CCR0, valid);
1984 // We have a null argument, branch to ic_miss_stub.
1985 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1986 relocInfo::runtime_call_type);
1987 __ bind(valid);
1988 }
1989 }
1990 // Assume argument is not NULL, load klass from receiver.
1991 __ load_klass(receiver_klass, R3_ARG1);
1992
1993 if (TrapBasedICMissChecks) {
1994 __ trap_ic_miss_check(receiver_klass, ic_klass);
1995 } else {
1996 Label valid;
1997 __ cmpd(CCR0, receiver_klass, ic_klass);
1998 __ beq_predict_taken(CCR0, valid);
1999 // We have an unexpected klass, branch to ic_miss_stub.
2000 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2001 relocInfo::runtime_call_type);
2002 __ bind(valid);
2003 }
2004
2005 // Argument is valid and klass is as expected, continue.
2006 }
2007
2008 #if 0 // TODO: PPC port
2009 // Optimize UEP code on z (save a load_const() call in main path).
2010 int MachUEPNode::ep_offset() {
2011 return 0;
2012 }
2013 #endif
2014
2015 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2016 // Variable size. Determine dynamically.
2017 return MachNode::size(ra_);
2018 }
2019
2020 //=============================================================================
2021
2022 uint size_exception_handler() {
2023 // The exception_handler is a b64_patchable.
2024 return MacroAssembler::b64_patchable_size;
2025 }
2026
2027 uint size_deopt_handler() {
2028 // The deopt_handler is a bl64_patchable.
2029 return MacroAssembler::bl64_patchable_size;
2030 }
2031
2032 int emit_exception_handler(CodeBuffer &cbuf) {
2033 MacroAssembler _masm(&cbuf);
2034
2035 address base = __ start_a_stub(size_exception_handler());
2036 if (base == NULL) return 0; // CodeBuffer::expand failed
2037
2038 int offset = __ offset();
2039 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2040 relocInfo::runtime_call_type);
2041 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2042 __ end_a_stub();
2043
2044 return offset;
2045 }
2046
2047 // The deopt_handler is like the exception handler, but it calls to
2048 // the deoptimization blob instead of jumping to the exception blob.
2049 int emit_deopt_handler(CodeBuffer& cbuf) {
2050 MacroAssembler _masm(&cbuf);
2051
2052 address base = __ start_a_stub(size_deopt_handler());
2053 if (base == NULL) return 0; // CodeBuffer::expand failed
2054
2055 int offset = __ offset();
2056 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2057 relocInfo::runtime_call_type);
2058 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2059 __ end_a_stub();
2060
2061 return offset;
2062 }
2063
2064 //=============================================================================
2065
2066 // Use a frame slots bias for frameless methods if accessing the stack.
2067 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2068 if (as_Register(reg_enc) == R1_SP) {
2069 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2070 }
2071 return 0;
2072 }
2073
2074 const bool Matcher::match_rule_supported(int opcode) {
2075 if (!has_match_rule(opcode))
2076 return false;
2077
2078 switch (opcode) {
2079 case Op_SqrtD:
2080 return VM_Version::has_fsqrt();
2081 case Op_CountLeadingZerosI:
2082 case Op_CountLeadingZerosL:
2083 case Op_CountTrailingZerosI:
2084 case Op_CountTrailingZerosL:
2085 if (!UseCountLeadingZerosInstructionsPPC64)
2086 return false;
2087 break;
2088
2089 case Op_PopCountI:
2090 case Op_PopCountL:
2091 return (UsePopCountInstruction && VM_Version::has_popcntw());
2092
2093 case Op_StrComp:
2094 return SpecialStringCompareTo;
2095 case Op_StrEquals:
2096 return SpecialStringEquals;
2097 case Op_StrIndexOf:
2098 return SpecialStringIndexOf;
2099 }
2100
2101 return true; // Per default match rules are supported.
2102 }
2103
2104 int Matcher::regnum_to_fpu_offset(int regnum) {
2105 // No user for this method?
2106 Unimplemented();
2107 return 999;
2108 }
2109
2110 const bool Matcher::convL2FSupported(void) {
2111 // fcfids can do the conversion (>= Power7).
2112 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2113 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2114 }
2115
2116 // Vector width in bytes.
2117 const int Matcher::vector_width_in_bytes(BasicType bt) {
2118 assert(MaxVectorSize == 8, "");
2119 return 8;
2120 }
2121
2122 // Vector ideal reg.
2123 const int Matcher::vector_ideal_reg(int size) {
2124 assert(MaxVectorSize == 8 && size == 8, "");
2125 return Op_RegL;
2126 }
2127
2128 const int Matcher::vector_shift_count_ideal_reg(int size) {
2129 fatal("vector shift is not supported");
2130 return Node::NotAMachineReg;
2131 }
2132
2133 // Limits on vector size (number of elements) loaded into vector.
2134 const int Matcher::max_vector_size(const BasicType bt) {
2135 assert(is_java_primitive(bt), "only primitive type vectors");
2136 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2137 }
2138
2139 const int Matcher::min_vector_size(const BasicType bt) {
2140 return max_vector_size(bt); // Same as max.
2141 }
2142
2143 // PPC doesn't support misaligned vectors store/load.
2144 const bool Matcher::misaligned_vectors_ok() {
2145 return false;
2146 }
2147
2148 // PPC AES support not yet implemented
2149 const bool Matcher::pass_original_key_for_aes() {
2150 return false;
2151 }
2152
2153 // RETURNS: whether this branch offset is short enough that a short
2154 // branch can be used.
2155 //
2156 // If the platform does not provide any short branch variants, then
2157 // this method should return `false' for offset 0.
2158 //
2159 // `Compile::Fill_buffer' will decide on basis of this information
2160 // whether to do the pass `Compile::Shorten_branches' at all.
2161 //
2162 // And `Compile::Shorten_branches' will decide on basis of this
2163 // information whether to replace particular branch sites by short
2164 // ones.
2165 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2166 // Is the offset within the range of a ppc64 pc relative branch?
2167 bool b;
2168
2169 const int safety_zone = 3 * BytesPerInstWord;
2170 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2171 29 - 16 + 1 + 2);
2172 return b;
2173 }
2174
2175 const bool Matcher::isSimpleConstant64(jlong value) {
2176 // Probably always true, even if a temp register is required.
2177 return true;
2178 }
2179 /* TODO: PPC port
2180 // Make a new machine dependent decode node (with its operands).
2181 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2182 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2183 "This method is only implemented for unscaled cOops mode so far");
2184 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2185 decode->set_opnd_array(0, new (C) iRegPdstOper());
2186 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2187 return decode;
2188 }
2189 */
2190 // Threshold size for cleararray.
2191 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2192
2193 // false => size gets scaled to BytesPerLong, ok.
2194 const bool Matcher::init_array_count_is_in_bytes = false;
2195
2196 // Use conditional move (CMOVL) on Power7.
2197 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2198
2199 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2200 // fsel doesn't accept a condition register as input, so this would be slightly different.
2201 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2202
2203 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2204 const bool Matcher::require_postalloc_expand = true;
2205
2206 // Should the Matcher clone shifts on addressing modes, expecting them to
2207 // be subsumed into complex addressing expressions or compute them into
2208 // registers? True for Intel but false for most RISCs.
2209 const bool Matcher::clone_shift_expressions = false;
2210
2211 // Do we need to mask the count passed to shift instructions or does
2212 // the cpu only look at the lower 5/6 bits anyway?
2213 // Off, as masks are generated in expand rules where required.
2214 // Constant shift counts are handled in Ideal phase.
2215 const bool Matcher::need_masked_shift_count = false;
2216
2217 // This affects two different things:
2218 // - how Decode nodes are matched
2219 // - how ImplicitNullCheck opportunities are recognized
2220 // If true, the matcher will try to remove all Decodes and match them
2221 // (as operands) into nodes. NullChecks are not prepared to deal with
2222 // Decodes by final_graph_reshaping().
2223 // If false, final_graph_reshaping() forces the decode behind the Cmp
2224 // for a NullCheck. The matcher matches the Decode node into a register.
2225 // Implicit_null_check optimization moves the Decode along with the
2226 // memory operation back up before the NullCheck.
2227 bool Matcher::narrow_oop_use_complex_address() {
2228 // TODO: PPC port if (MatchDecodeNodes) return true;
2229 return false;
2230 }
2231
2232 bool Matcher::narrow_klass_use_complex_address() {
2233 NOT_LP64(ShouldNotCallThis());
2234 assert(UseCompressedClassPointers, "only for compressed klass code");
2235 // TODO: PPC port if (MatchDecodeNodes) return true;
2236 return false;
2237 }
2238
2239 // Is it better to copy float constants, or load them directly from memory?
2240 // Intel can load a float constant from a direct address, requiring no
2241 // extra registers. Most RISCs will have to materialize an address into a
2242 // register first, so they would do better to copy the constant from stack.
2243 const bool Matcher::rematerialize_float_constants = false;
2244
2245 // If CPU can load and store mis-aligned doubles directly then no fixup is
2246 // needed. Else we split the double into 2 integer pieces and move it
2247 // piece-by-piece. Only happens when passing doubles into C code as the
2248 // Java calling convention forces doubles to be aligned.
2249 const bool Matcher::misaligned_doubles_ok = true;
2250
2251 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2252 Unimplemented();
2253 }
2254
2255 // Advertise here if the CPU requires explicit rounding operations
2256 // to implement the UseStrictFP mode.
2257 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2258
2259 // Do floats take an entire double register or just half?
2260 //
2261 // A float occupies a ppc64 double register. For the allocator, a
2262 // ppc64 double register appears as a pair of float registers.
2263 bool Matcher::float_in_double() { return true; }
2264
2265 // Do ints take an entire long register or just half?
2266 // The relevant question is how the int is callee-saved:
2267 // the whole long is written but de-opt'ing will have to extract
2268 // the relevant 32 bits.
2269 const bool Matcher::int_in_long = true;
2270
2271 // Constants for c2c and c calling conventions.
2272
2273 const MachRegisterNumbers iarg_reg[8] = {
2274 R3_num, R4_num, R5_num, R6_num,
2275 R7_num, R8_num, R9_num, R10_num
2276 };
2277
2278 const MachRegisterNumbers farg_reg[13] = {
2279 F1_num, F2_num, F3_num, F4_num,
2280 F5_num, F6_num, F7_num, F8_num,
2281 F9_num, F10_num, F11_num, F12_num,
2282 F13_num
2283 };
2284
2285 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2286
2287 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2288
2289 // Return whether or not this register is ever used as an argument. This
2290 // function is used on startup to build the trampoline stubs in generateOptoStub.
2291 // Registers not mentioned will be killed by the VM call in the trampoline, and
2292 // arguments in those registers not be available to the callee.
2293 bool Matcher::can_be_java_arg(int reg) {
2294 // We return true for all registers contained in iarg_reg[] and
2295 // farg_reg[] and their virtual halves.
2296 // We must include the virtual halves in order to get STDs and LDs
2297 // instead of STWs and LWs in the trampoline stubs.
2298
2299 if ( reg == R3_num || reg == R3_H_num
2300 || reg == R4_num || reg == R4_H_num
2301 || reg == R5_num || reg == R5_H_num
2302 || reg == R6_num || reg == R6_H_num
2303 || reg == R7_num || reg == R7_H_num
2304 || reg == R8_num || reg == R8_H_num
2305 || reg == R9_num || reg == R9_H_num
2306 || reg == R10_num || reg == R10_H_num)
2307 return true;
2308
2309 if ( reg == F1_num || reg == F1_H_num
2310 || reg == F2_num || reg == F2_H_num
2311 || reg == F3_num || reg == F3_H_num
2312 || reg == F4_num || reg == F4_H_num
2313 || reg == F5_num || reg == F5_H_num
2314 || reg == F6_num || reg == F6_H_num
2315 || reg == F7_num || reg == F7_H_num
2316 || reg == F8_num || reg == F8_H_num
2317 || reg == F9_num || reg == F9_H_num
2318 || reg == F10_num || reg == F10_H_num
2319 || reg == F11_num || reg == F11_H_num
2320 || reg == F12_num || reg == F12_H_num
2321 || reg == F13_num || reg == F13_H_num)
2322 return true;
2323
2324 return false;
2325 }
2326
2327 bool Matcher::is_spillable_arg(int reg) {
2328 return can_be_java_arg(reg);
2329 }
2330
2331 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2332 return false;
2333 }
2334
2335 // Register for DIVI projection of divmodI.
2336 RegMask Matcher::divI_proj_mask() {
2337 ShouldNotReachHere();
2338 return RegMask();
2339 }
2340
2341 // Register for MODI projection of divmodI.
2342 RegMask Matcher::modI_proj_mask() {
2343 ShouldNotReachHere();
2344 return RegMask();
2345 }
2346
2347 // Register for DIVL projection of divmodL.
2348 RegMask Matcher::divL_proj_mask() {
2349 ShouldNotReachHere();
2350 return RegMask();
2351 }
2352
2353 // Register for MODL projection of divmodL.
2354 RegMask Matcher::modL_proj_mask() {
2355 ShouldNotReachHere();
2356 return RegMask();
2357 }
2358
2359 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2360 return RegMask();
2361 }
2362
2363 const RegMask Matcher::mathExactI_result_proj_mask() {
2364 return RARG4_BITS64_REG_mask();
2365 }
2366
2367 const RegMask Matcher::mathExactL_result_proj_mask() {
2368 return RARG4_BITS64_REG_mask();
2369 }
2370
2371 const RegMask Matcher::mathExactI_flags_proj_mask() {
2372 return INT_FLAGS_mask();
2373 }
2374
2375 %}
2376
2377 //----------ENCODING BLOCK-----------------------------------------------------
2378 // This block specifies the encoding classes used by the compiler to output
2379 // byte streams. Encoding classes are parameterized macros used by
2380 // Machine Instruction Nodes in order to generate the bit encoding of the
2381 // instruction. Operands specify their base encoding interface with the
2382 // interface keyword. There are currently supported four interfaces,
2383 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2384 // operand to generate a function which returns its register number when
2385 // queried. CONST_INTER causes an operand to generate a function which
2386 // returns the value of the constant when queried. MEMORY_INTER causes an
2387 // operand to generate four functions which return the Base Register, the
2388 // Index Register, the Scale Value, and the Offset Value of the operand when
2389 // queried. COND_INTER causes an operand to generate six functions which
2390 // return the encoding code (ie - encoding bits for the instruction)
2391 // associated with each basic boolean condition for a conditional instruction.
2392 //
2393 // Instructions specify two basic values for encoding. Again, a function
2394 // is available to check if the constant displacement is an oop. They use the
2395 // ins_encode keyword to specify their encoding classes (which must be
2396 // a sequence of enc_class names, and their parameters, specified in
2397 // the encoding block), and they use the
2398 // opcode keyword to specify, in order, their primary, secondary, and
2399 // tertiary opcode. Only the opcode sections which a particular instruction
2400 // needs for encoding need to be specified.
2401 encode %{
2402 enc_class enc_unimplemented %{
2403 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2404 MacroAssembler _masm(&cbuf);
2405 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2406 %}
2407
2408 enc_class enc_untested %{
2409 #ifdef ASSERT
2410 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2411 MacroAssembler _masm(&cbuf);
2412 __ untested("Untested mach node encoding in AD file.");
2413 #else
2414 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2415 #endif
2416 %}
2417
2418 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2419 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2420 MacroAssembler _masm(&cbuf);
2421 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2422 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2423 %}
2424
2425 // Load acquire.
2426 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2427 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2428 MacroAssembler _masm(&cbuf);
2429 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2430 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2431 __ twi_0($dst$$Register);
2432 __ isync();
2433 %}
2434
2435 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2436 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2437
2438 MacroAssembler _masm(&cbuf);
2439 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2440 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2441 %}
2442
2443 // Load acquire.
2444 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2445 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2446
2447 MacroAssembler _masm(&cbuf);
2448 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2449 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2450 __ twi_0($dst$$Register);
2451 __ isync();
2452 %}
2453
2454 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2455 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2456
2457 MacroAssembler _masm(&cbuf);
2458 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2459 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2460 %}
2461
2462 // Load acquire.
2463 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2464 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2465
2466 MacroAssembler _masm(&cbuf);
2467 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2468 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2469 __ twi_0($dst$$Register);
2470 __ isync();
2471 %}
2472
2473 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2474 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2475 MacroAssembler _masm(&cbuf);
2476 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2477 // Operand 'ds' requires 4-alignment.
2478 assert((Idisp & 0x3) == 0, "unaligned offset");
2479 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2480 %}
2481
2482 // Load acquire.
2483 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2484 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2485 MacroAssembler _masm(&cbuf);
2486 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2487 // Operand 'ds' requires 4-alignment.
2488 assert((Idisp & 0x3) == 0, "unaligned offset");
2489 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2490 __ twi_0($dst$$Register);
2491 __ isync();
2492 %}
2493
2494 enc_class enc_lfd(RegF dst, memory mem) %{
2495 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2496 MacroAssembler _masm(&cbuf);
2497 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2498 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2499 %}
2500
2501 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2502 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2503
2504 MacroAssembler _masm(&cbuf);
2505 int toc_offset = 0;
2506
2507 if (!ra_->C->in_scratch_emit_size()) {
2508 address const_toc_addr;
2509 // Create a non-oop constant, no relocation needed.
2510 // If it is an IC, it has a virtual_call_Relocation.
2511 const_toc_addr = __ long_constant((jlong)$src$$constant);
2512
2513 // Get the constant's TOC offset.
2514 toc_offset = __ offset_to_method_toc(const_toc_addr);
2515
2516 // Keep the current instruction offset in mind.
2517 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2518 }
2519
2520 __ ld($dst$$Register, toc_offset, $toc$$Register);
2521 %}
2522
2523 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2524 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2525
2526 MacroAssembler _masm(&cbuf);
2527
2528 if (!ra_->C->in_scratch_emit_size()) {
2529 address const_toc_addr;
2530 // Create a non-oop constant, no relocation needed.
2531 // If it is an IC, it has a virtual_call_Relocation.
2532 const_toc_addr = __ long_constant((jlong)$src$$constant);
2533
2534 // Get the constant's TOC offset.
2535 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2536 // Store the toc offset of the constant.
2537 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2538
2539 // Also keep the current instruction offset in mind.
2540 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2541 }
2542
2543 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2544 %}
2545
2546 %} // encode
2547
2548 source %{
2549
2550 typedef struct {
2551 loadConL_hiNode *_large_hi;
2552 loadConL_loNode *_large_lo;
2553 loadConLNode *_small;
2554 MachNode *_last;
2555 } loadConLNodesTuple;
2556
2557 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2558 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2559 loadConLNodesTuple nodes;
2560
2561 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2562 if (large_constant_pool) {
2563 // Create new nodes.
2564 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2565 loadConL_loNode *m2 = new (C) loadConL_loNode();
2566
2567 // inputs for new nodes
2568 m1->add_req(NULL, toc);
2569 m2->add_req(NULL, m1);
2570
2571 // operands for new nodes
2572 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2573 m1->_opnds[1] = immSrc; // src
2574 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2575 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2576 m2->_opnds[1] = immSrc; // src
2577 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2578
2579 // Initialize ins_attrib TOC fields.
2580 m1->_const_toc_offset = -1;
2581 m2->_const_toc_offset_hi_node = m1;
2582
2583 // Initialize ins_attrib instruction offset.
2584 m1->_cbuf_insts_offset = -1;
2585
2586 // register allocation for new nodes
2587 ra_->set_pair(m1->_idx, reg_second, reg_first);
2588 ra_->set_pair(m2->_idx, reg_second, reg_first);
2589
2590 // Create result.
2591 nodes._large_hi = m1;
2592 nodes._large_lo = m2;
2593 nodes._small = NULL;
2594 nodes._last = nodes._large_lo;
2595 assert(m2->bottom_type()->isa_long(), "must be long");
2596 } else {
2597 loadConLNode *m2 = new (C) loadConLNode();
2598
2599 // inputs for new nodes
2600 m2->add_req(NULL, toc);
2601
2602 // operands for new nodes
2603 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2604 m2->_opnds[1] = immSrc; // src
2605 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2606
2607 // Initialize ins_attrib instruction offset.
2608 m2->_cbuf_insts_offset = -1;
2609
2610 // register allocation for new nodes
2611 ra_->set_pair(m2->_idx, reg_second, reg_first);
2612
2613 // Create result.
2614 nodes._large_hi = NULL;
2615 nodes._large_lo = NULL;
2616 nodes._small = m2;
2617 nodes._last = nodes._small;
2618 assert(m2->bottom_type()->isa_long(), "must be long");
2619 }
2620
2621 return nodes;
2622 }
2623
2624 %} // source
2625
2626 encode %{
2627 // Postalloc expand emitter for loading a long constant from the method's TOC.
2628 // Enc_class needed as consttanttablebase is not supported by postalloc
2629 // expand.
2630 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2631 // Create new nodes.
2632 loadConLNodesTuple loadConLNodes =
2633 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2634 ra_->get_reg_second(this), ra_->get_reg_first(this));
2635
2636 // Push new nodes.
2637 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2638 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2639
2640 // some asserts
2641 assert(nodes->length() >= 1, "must have created at least 1 node");
2642 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2643 %}
2644
2645 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2646 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2647
2648 MacroAssembler _masm(&cbuf);
2649 int toc_offset = 0;
2650
2651 if (!ra_->C->in_scratch_emit_size()) {
2652 intptr_t val = $src$$constant;
2653 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2654 address const_toc_addr;
2655 if (constant_reloc == relocInfo::oop_type) {
2656 // Create an oop constant and a corresponding relocation.
2657 AddressLiteral a = __ allocate_oop_address((jobject)val);
2658 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2659 __ relocate(a.rspec());
2660 } else if (constant_reloc == relocInfo::metadata_type) {
2661 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2662 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2663 __ relocate(a.rspec());
2664 } else {
2665 // Create a non-oop constant, no relocation needed.
2666 const_toc_addr = __ long_constant((jlong)$src$$constant);
2667 }
2668
2669 // Get the constant's TOC offset.
2670 toc_offset = __ offset_to_method_toc(const_toc_addr);
2671 }
2672
2673 __ ld($dst$$Register, toc_offset, $toc$$Register);
2674 %}
2675
2676 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2677 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2678
2679 MacroAssembler _masm(&cbuf);
2680 if (!ra_->C->in_scratch_emit_size()) {
2681 intptr_t val = $src$$constant;
2682 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2683 address const_toc_addr;
2684 if (constant_reloc == relocInfo::oop_type) {
2685 // Create an oop constant and a corresponding relocation.
2686 AddressLiteral a = __ allocate_oop_address((jobject)val);
2687 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2688 __ relocate(a.rspec());
2689 } else if (constant_reloc == relocInfo::metadata_type) {
2690 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2691 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2692 __ relocate(a.rspec());
2693 } else { // non-oop pointers, e.g. card mark base, heap top
2694 // Create a non-oop constant, no relocation needed.
2695 const_toc_addr = __ long_constant((jlong)$src$$constant);
2696 }
2697
2698 // Get the constant's TOC offset.
2699 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2700 // Store the toc offset of the constant.
2701 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2702 }
2703
2704 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2705 %}
2706
2707 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2708 // Enc_class needed as consttanttablebase is not supported by postalloc
2709 // expand.
2710 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2711 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2712 if (large_constant_pool) {
2713 // Create new nodes.
2714 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2715 loadConP_loNode *m2 = new (C) loadConP_loNode();
2716
2717 // inputs for new nodes
2718 m1->add_req(NULL, n_toc);
2719 m2->add_req(NULL, m1);
2720
2721 // operands for new nodes
2722 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2723 m1->_opnds[1] = op_src; // src
2724 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2725 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2726 m2->_opnds[1] = op_src; // src
2727 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2728
2729 // Initialize ins_attrib TOC fields.
2730 m1->_const_toc_offset = -1;
2731 m2->_const_toc_offset_hi_node = m1;
2732
2733 // Register allocation for new nodes.
2734 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2735 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2736
2737 nodes->push(m1);
2738 nodes->push(m2);
2739 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2740 } else {
2741 loadConPNode *m2 = new (C) loadConPNode();
2742
2743 // inputs for new nodes
2744 m2->add_req(NULL, n_toc);
2745
2746 // operands for new nodes
2747 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2748 m2->_opnds[1] = op_src; // src
2749 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2750
2751 // Register allocation for new nodes.
2752 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2753
2754 nodes->push(m2);
2755 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2756 }
2757 %}
2758
2759 // Enc_class needed as consttanttablebase is not supported by postalloc
2760 // expand.
2761 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2762 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2763
2764 MachNode *m2;
2765 if (large_constant_pool) {
2766 m2 = new (C) loadConFCompNode();
2767 } else {
2768 m2 = new (C) loadConFNode();
2769 }
2770 // inputs for new nodes
2771 m2->add_req(NULL, n_toc);
2772
2773 // operands for new nodes
2774 m2->_opnds[0] = op_dst;
2775 m2->_opnds[1] = op_src;
2776 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2777
2778 // register allocation for new nodes
2779 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2780 nodes->push(m2);
2781 %}
2782
2783 // Enc_class needed as consttanttablebase is not supported by postalloc
2784 // expand.
2785 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2786 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2787
2788 MachNode *m2;
2789 if (large_constant_pool) {
2790 m2 = new (C) loadConDCompNode();
2791 } else {
2792 m2 = new (C) loadConDNode();
2793 }
2794 // inputs for new nodes
2795 m2->add_req(NULL, n_toc);
2796
2797 // operands for new nodes
2798 m2->_opnds[0] = op_dst;
2799 m2->_opnds[1] = op_src;
2800 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2801
2802 // register allocation for new nodes
2803 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2804 nodes->push(m2);
2805 %}
2806
2807 enc_class enc_stw(iRegIsrc src, memory mem) %{
2808 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2809 MacroAssembler _masm(&cbuf);
2810 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2811 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2812 %}
2813
2814 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2815 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2816 MacroAssembler _masm(&cbuf);
2817 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2818 // Operand 'ds' requires 4-alignment.
2819 assert((Idisp & 0x3) == 0, "unaligned offset");
2820 __ std($src$$Register, Idisp, $mem$$base$$Register);
2821 %}
2822
2823 enc_class enc_stfs(RegF src, memory mem) %{
2824 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2825 MacroAssembler _masm(&cbuf);
2826 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2827 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2828 %}
2829
2830 enc_class enc_stfd(RegF src, memory mem) %{
2831 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2832 MacroAssembler _masm(&cbuf);
2833 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2834 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2835 %}
2836
2837 // Use release_store for card-marking to ensure that previous
2838 // oop-stores are visible before the card-mark change.
2839 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2840 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2841 // FIXME: Implement this as a cmove and use a fixed condition code
2842 // register which is written on every transition to compiled code,
2843 // e.g. in call-stub and when returning from runtime stubs.
2844 //
2845 // Proposed code sequence for the cmove implementation:
2846 //
2847 // Label skip_release;
2848 // __ beq(CCRfixed, skip_release);
2849 // __ release();
2850 // __ bind(skip_release);
2851 // __ stb(card mark);
2852
2853 MacroAssembler _masm(&cbuf);
2854 Label skip_storestore;
2855
2856 #if 0 // TODO: PPC port
2857 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2858 // StoreStore barrier conditionally.
2859 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2860 __ cmpwi(CCR0, R0, 0);
2861 __ beq_predict_taken(CCR0, skip_storestore);
2862 #endif
2863 __ li(R0, 0);
2864 __ membar(Assembler::StoreStore);
2865 #if 0 // TODO: PPC port
2866 __ bind(skip_storestore);
2867 #endif
2868
2869 // Do the store.
2870 if ($mem$$index == 0) {
2871 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2872 } else {
2873 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2874 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2875 }
2876 %}
2877
2878 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2879
2880 if (VM_Version::has_isel()) {
2881 // use isel instruction with Power 7
2882 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2883 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2884 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2885 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2886
2887 n_compare->add_req(n_region, n_src);
2888 n_compare->_opnds[0] = op_crx;
2889 n_compare->_opnds[1] = op_src;
2890 n_compare->_opnds[2] = new (C) immL16Oper(0);
2891
2892 n_sub_base->add_req(n_region, n_src);
2893 n_sub_base->_opnds[0] = op_dst;
2894 n_sub_base->_opnds[1] = op_src;
2895 n_sub_base->_bottom_type = _bottom_type;
2896
2897 n_shift->add_req(n_region, n_sub_base);
2898 n_shift->_opnds[0] = op_dst;
2899 n_shift->_opnds[1] = op_dst;
2900 n_shift->_bottom_type = _bottom_type;
2901
2902 n_cond_set->add_req(n_region, n_compare, n_shift);
2903 n_cond_set->_opnds[0] = op_dst;
2904 n_cond_set->_opnds[1] = op_crx;
2905 n_cond_set->_opnds[2] = op_dst;
2906 n_cond_set->_bottom_type = _bottom_type;
2907
2908 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2909 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2910 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2911 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2912
2913 nodes->push(n_compare);
2914 nodes->push(n_sub_base);
2915 nodes->push(n_shift);
2916 nodes->push(n_cond_set);
2917
2918 } else {
2919 // before Power 7
2920 moveRegNode *n_move = new (C) moveRegNode();
2921 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2922 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2923 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2924
2925 n_move->add_req(n_region, n_src);
2926 n_move->_opnds[0] = op_dst;
2927 n_move->_opnds[1] = op_src;
2928 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2929
2930 n_compare->add_req(n_region, n_src);
2931 n_compare->add_prec(n_move);
2932
2933 n_compare->_opnds[0] = op_crx;
2934 n_compare->_opnds[1] = op_src;
2935 n_compare->_opnds[2] = new (C) immL16Oper(0);
2936
2937 n_sub_base->add_req(n_region, n_compare, n_src);
2938 n_sub_base->_opnds[0] = op_dst;
2939 n_sub_base->_opnds[1] = op_crx;
2940 n_sub_base->_opnds[2] = op_src;
2941 n_sub_base->_bottom_type = _bottom_type;
2942
2943 n_shift->add_req(n_region, n_sub_base);
2944 n_shift->_opnds[0] = op_dst;
2945 n_shift->_opnds[1] = op_dst;
2946 n_shift->_bottom_type = _bottom_type;
2947
2948 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2949 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2950 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2951 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2952
2953 nodes->push(n_move);
2954 nodes->push(n_compare);
2955 nodes->push(n_sub_base);
2956 nodes->push(n_shift);
2957 }
2958
2959 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2960 %}
2961
2962 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2963
2964 encodeP_subNode *n1 = new (C) encodeP_subNode();
2965 n1->add_req(n_region, n_src);
2966 n1->_opnds[0] = op_dst;
2967 n1->_opnds[1] = op_src;
2968 n1->_bottom_type = _bottom_type;
2969
2970 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
2971 n2->add_req(n_region, n1);
2972 n2->_opnds[0] = op_dst;
2973 n2->_opnds[1] = op_dst;
2974 n2->_bottom_type = _bottom_type;
2975 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2976 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2977
2978 nodes->push(n1);
2979 nodes->push(n2);
2980 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2981 %}
2982
2983 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2984 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
2985 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
2986
2987 n_compare->add_req(n_region, n_src);
2988 n_compare->_opnds[0] = op_crx;
2989 n_compare->_opnds[1] = op_src;
2990 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
2991
2992 n_shift->add_req(n_region, n_src);
2993 n_shift->_opnds[0] = op_dst;
2994 n_shift->_opnds[1] = op_src;
2995 n_shift->_bottom_type = _bottom_type;
2996
2997 if (VM_Version::has_isel()) {
2998 // use isel instruction with Power 7
2999
3000 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
3001 n_add_base->add_req(n_region, n_shift);
3002 n_add_base->_opnds[0] = op_dst;
3003 n_add_base->_opnds[1] = op_dst;
3004 n_add_base->_bottom_type = _bottom_type;
3005
3006 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3007 n_cond_set->add_req(n_region, n_compare, n_add_base);
3008 n_cond_set->_opnds[0] = op_dst;
3009 n_cond_set->_opnds[1] = op_crx;
3010 n_cond_set->_opnds[2] = op_dst;
3011 n_cond_set->_bottom_type = _bottom_type;
3012
3013 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3014 ra_->set_oop(n_cond_set, true);
3015
3016 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3018 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3019 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3020
3021 nodes->push(n_compare);
3022 nodes->push(n_shift);
3023 nodes->push(n_add_base);
3024 nodes->push(n_cond_set);
3025
3026 } else {
3027 // before Power 7
3028 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3029
3030 n_add_base->add_req(n_region, n_compare, n_shift);
3031 n_add_base->_opnds[0] = op_dst;
3032 n_add_base->_opnds[1] = op_crx;
3033 n_add_base->_opnds[2] = op_dst;
3034 n_add_base->_bottom_type = _bottom_type;
3035
3036 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3037 ra_->set_oop(n_add_base, true);
3038
3039 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3040 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3041 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3042
3043 nodes->push(n_compare);
3044 nodes->push(n_shift);
3045 nodes->push(n_add_base);
3046 }
3047 %}
3048
3049 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3050 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3051 n1->add_req(n_region, n_src);
3052 n1->_opnds[0] = op_dst;
3053 n1->_opnds[1] = op_src;
3054 n1->_bottom_type = _bottom_type;
3055
3056 decodeN_addNode *n2 = new (C) decodeN_addNode();
3057 n2->add_req(n_region, n1);
3058 n2->_opnds[0] = op_dst;
3059 n2->_opnds[1] = op_dst;
3060 n2->_bottom_type = _bottom_type;
3061 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3062 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3063
3064 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3065 ra_->set_oop(n2, true);
3066
3067 nodes->push(n1);
3068 nodes->push(n2);
3069 %}
3070
3071 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3072 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3073
3074 MacroAssembler _masm(&cbuf);
3075 int cc = $cmp$$cmpcode;
3076 int flags_reg = $crx$$reg;
3077 Label done;
3078 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3079 // Branch if not (cmp crx).
3080 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3081 __ mr($dst$$Register, $src$$Register);
3082 // TODO PPC port __ endgroup_if_needed(_size == 12);
3083 __ bind(done);
3084 %}
3085
3086 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3087 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3088
3089 MacroAssembler _masm(&cbuf);
3090 Label done;
3091 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3092 // Branch if not (cmp crx).
3093 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3094 __ li($dst$$Register, $src$$constant);
3095 // TODO PPC port __ endgroup_if_needed(_size == 12);
3096 __ bind(done);
3097 %}
3098
3099 // New atomics.
3100 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3101 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3102
3103 MacroAssembler _masm(&cbuf);
3104 Register Rtmp = R0;
3105 Register Rres = $res$$Register;
3106 Register Rsrc = $src$$Register;
3107 Register Rptr = $mem_ptr$$Register;
3108 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3109 Register Rold = RegCollision ? Rtmp : Rres;
3110
3111 Label Lretry;
3112 __ bind(Lretry);
3113 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3114 __ add(Rtmp, Rsrc, Rold);
3115 __ stwcx_(Rtmp, Rptr);
3116 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3117 __ bne_predict_not_taken(CCR0, Lretry);
3118 } else {
3119 __ bne( CCR0, Lretry);
3120 }
3121 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3122 __ fence();
3123 %}
3124
3125 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3126 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3127
3128 MacroAssembler _masm(&cbuf);
3129 Register Rtmp = R0;
3130 Register Rres = $res$$Register;
3131 Register Rsrc = $src$$Register;
3132 Register Rptr = $mem_ptr$$Register;
3133 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3134 Register Rold = RegCollision ? Rtmp : Rres;
3135
3136 Label Lretry;
3137 __ bind(Lretry);
3138 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3139 __ add(Rtmp, Rsrc, Rold);
3140 __ stdcx_(Rtmp, Rptr);
3141 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3142 __ bne_predict_not_taken(CCR0, Lretry);
3143 } else {
3144 __ bne( CCR0, Lretry);
3145 }
3146 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3147 __ fence();
3148 %}
3149
3150 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3151 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3152
3153 MacroAssembler _masm(&cbuf);
3154 Register Rtmp = R0;
3155 Register Rres = $res$$Register;
3156 Register Rsrc = $src$$Register;
3157 Register Rptr = $mem_ptr$$Register;
3158 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3159 Register Rold = RegCollision ? Rtmp : Rres;
3160
3161 Label Lretry;
3162 __ bind(Lretry);
3163 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3164 __ stwcx_(Rsrc, Rptr);
3165 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3166 __ bne_predict_not_taken(CCR0, Lretry);
3167 } else {
3168 __ bne( CCR0, Lretry);
3169 }
3170 if (RegCollision) __ mr(Rres, Rtmp);
3171 __ fence();
3172 %}
3173
3174 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3175 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3176
3177 MacroAssembler _masm(&cbuf);
3178 Register Rtmp = R0;
3179 Register Rres = $res$$Register;
3180 Register Rsrc = $src$$Register;
3181 Register Rptr = $mem_ptr$$Register;
3182 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3183 Register Rold = RegCollision ? Rtmp : Rres;
3184
3185 Label Lretry;
3186 __ bind(Lretry);
3187 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3188 __ stdcx_(Rsrc, Rptr);
3189 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3190 __ bne_predict_not_taken(CCR0, Lretry);
3191 } else {
3192 __ bne( CCR0, Lretry);
3193 }
3194 if (RegCollision) __ mr(Rres, Rtmp);
3195 __ fence();
3196 %}
3197
3198 // This enc_class is needed so that scheduler gets proper
3199 // input mapping for latency computation.
3200 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3201 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3202 MacroAssembler _masm(&cbuf);
3203 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3204 %}
3205
3206 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3207 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3208
3209 MacroAssembler _masm(&cbuf);
3210
3211 Label done;
3212 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3213 __ li($dst$$Register, $zero$$constant);
3214 __ beq($crx$$CondRegister, done);
3215 __ li($dst$$Register, $notzero$$constant);
3216 __ bind(done);
3217 %}
3218
3219 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3220 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3221
3222 MacroAssembler _masm(&cbuf);
3223
3224 Label done;
3225 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3226 __ li($dst$$Register, $zero$$constant);
3227 __ beq($crx$$CondRegister, done);
3228 __ li($dst$$Register, $notzero$$constant);
3229 __ bind(done);
3230 %}
3231
3232 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3233 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3234
3235 MacroAssembler _masm(&cbuf);
3236 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3237 Label done;
3238 __ bso($crx$$CondRegister, done);
3239 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3240 // TODO PPC port __ endgroup_if_needed(_size == 12);
3241 __ bind(done);
3242 %}
3243
3244 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3245 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3246
3247 MacroAssembler _masm(&cbuf);
3248 Label d; // dummy
3249 __ bind(d);
3250 Label* p = ($lbl$$label);
3251 // `p' is `NULL' when this encoding class is used only to
3252 // determine the size of the encoded instruction.
3253 Label& l = (NULL == p)? d : *(p);
3254 int cc = $cmp$$cmpcode;
3255 int flags_reg = $crx$$reg;
3256 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3257 int bhint = Assembler::bhintNoHint;
3258
3259 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3260 if (_prob <= PROB_NEVER) {
3261 bhint = Assembler::bhintIsNotTaken;
3262 } else if (_prob >= PROB_ALWAYS) {
3263 bhint = Assembler::bhintIsTaken;
3264 }
3265 }
3266
3267 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3268 cc_to_biint(cc, flags_reg),
3269 l);
3270 %}
3271
3272 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3273 // The scheduler doesn't know about branch shortening, so we set the opcode
3274 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3275 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3276
3277 MacroAssembler _masm(&cbuf);
3278 Label d; // dummy
3279 __ bind(d);
3280 Label* p = ($lbl$$label);
3281 // `p' is `NULL' when this encoding class is used only to
3282 // determine the size of the encoded instruction.
3283 Label& l = (NULL == p)? d : *(p);
3284 int cc = $cmp$$cmpcode;
3285 int flags_reg = $crx$$reg;
3286 int bhint = Assembler::bhintNoHint;
3287
3288 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3289 if (_prob <= PROB_NEVER) {
3290 bhint = Assembler::bhintIsNotTaken;
3291 } else if (_prob >= PROB_ALWAYS) {
3292 bhint = Assembler::bhintIsTaken;
3293 }
3294 }
3295
3296 // Tell the conditional far branch to optimize itself when being relocated.
3297 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3298 cc_to_biint(cc, flags_reg),
3299 l,
3300 MacroAssembler::bc_far_optimize_on_relocate);
3301 %}
3302
3303 // Branch used with Power6 scheduling (can be shortened without changing the node).
3304 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3305 // The scheduler doesn't know about branch shortening, so we set the opcode
3306 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3307 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3308
3309 MacroAssembler _masm(&cbuf);
3310 Label d; // dummy
3311 __ bind(d);
3312 Label* p = ($lbl$$label);
3313 // `p' is `NULL' when this encoding class is used only to
3314 // determine the size of the encoded instruction.
3315 Label& l = (NULL == p)? d : *(p);
3316 int cc = $cmp$$cmpcode;
3317 int flags_reg = $crx$$reg;
3318 int bhint = Assembler::bhintNoHint;
3319
3320 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3321 if (_prob <= PROB_NEVER) {
3322 bhint = Assembler::bhintIsNotTaken;
3323 } else if (_prob >= PROB_ALWAYS) {
3324 bhint = Assembler::bhintIsTaken;
3325 }
3326 }
3327
3328 #if 0 // TODO: PPC port
3329 if (_size == 8) {
3330 // Tell the conditional far branch to optimize itself when being relocated.
3331 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3332 cc_to_biint(cc, flags_reg),
3333 l,
3334 MacroAssembler::bc_far_optimize_on_relocate);
3335 } else {
3336 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3337 cc_to_biint(cc, flags_reg),
3338 l);
3339 }
3340 #endif
3341 Unimplemented();
3342 %}
3343
3344 // Postalloc expand emitter for loading a replicatef float constant from
3345 // the method's TOC.
3346 // Enc_class needed as consttanttablebase is not supported by postalloc
3347 // expand.
3348 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3349 // Create new nodes.
3350
3351 // Make an operand with the bit pattern to load as float.
3352 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3353
3354 loadConLNodesTuple loadConLNodes =
3355 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3356 ra_->get_reg_second(this), ra_->get_reg_first(this));
3357
3358 // Push new nodes.
3359 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3360 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3361
3362 assert(nodes->length() >= 1, "must have created at least 1 node");
3363 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3364 %}
3365
3366 // This enc_class is needed so that scheduler gets proper
3367 // input mapping for latency computation.
3368 enc_class enc_poll(immI dst, iRegLdst poll) %{
3369 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3370 // Fake operand dst needed for PPC scheduler.
3371 assert($dst$$constant == 0x0, "dst must be 0x0");
3372
3373 MacroAssembler _masm(&cbuf);
3374 // Mark the code position where the load from the safepoint
3375 // polling page was emitted as relocInfo::poll_type.
3376 __ relocate(relocInfo::poll_type);
3377 __ load_from_polling_page($poll$$Register);
3378 %}
3379
3380 // A Java static call or a runtime call.
3381 //
3382 // Branch-and-link relative to a trampoline.
3383 // The trampoline loads the target address and does a long branch to there.
3384 // In case we call java, the trampoline branches to a interpreter_stub
3385 // which loads the inline cache and the real call target from the constant pool.
3386 //
3387 // This basically looks like this:
3388 //
3389 // >>>> consts -+ -+
3390 // | |- offset1
3391 // [call target1] | <-+
3392 // [IC cache] |- offset2
3393 // [call target2] <--+
3394 //
3395 // <<<< consts
3396 // >>>> insts
3397 //
3398 // bl offset16 -+ -+ ??? // How many bits available?
3399 // | |
3400 // <<<< insts | |
3401 // >>>> stubs | |
3402 // | |- trampoline_stub_Reloc
3403 // trampoline stub: | <-+
3404 // r2 = toc |
3405 // r2 = [r2 + offset1] | // Load call target1 from const section
3406 // mtctr r2 |
3407 // bctr |- static_stub_Reloc
3408 // comp_to_interp_stub: <---+
3409 // r1 = toc
3410 // ICreg = [r1 + IC_offset] // Load IC from const section
3411 // r1 = [r1 + offset2] // Load call target2 from const section
3412 // mtctr r1
3413 // bctr
3414 //
3415 // <<<< stubs
3416 //
3417 // The call instruction in the code either
3418 // - Branches directly to a compiled method if the offset is encodable in instruction.
3419 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3420 // - Branches to the compiled_to_interp stub if the target is interpreted.
3421 //
3422 // Further there are three relocations from the loads to the constants in
3423 // the constant section.
3424 //
3425 // Usage of r1 and r2 in the stubs allows to distinguish them.
3426 enc_class enc_java_static_call(method meth) %{
3427 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3428
3429 MacroAssembler _masm(&cbuf);
3430 address entry_point = (address)$meth$$method;
3431
3432 if (!_method) {
3433 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3434 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3435 } else {
3436 // Remember the offset not the address.
3437 const int start_offset = __ offset();
3438 // The trampoline stub.
3439 if (!Compile::current()->in_scratch_emit_size()) {
3440 // No entry point given, use the current pc.
3441 // Make sure branch fits into
3442 if (entry_point == 0) entry_point = __ pc();
3443
3444 // Put the entry point as a constant into the constant pool.
3445 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3446 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3447
3448 // Emit the trampoline stub which will be related to the branch-and-link below.
3449 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3450 __ relocate(_optimized_virtual ?
3451 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3452 }
3453
3454 // The real call.
3455 // Note: At this point we do not have the address of the trampoline
3456 // stub, and the entry point might be too far away for bl, so __ pc()
3457 // serves as dummy and the bl will be patched later.
3458 cbuf.set_insts_mark();
3459 __ bl(__ pc()); // Emits a relocation.
3460
3461 // The stub for call to interpreter.
3462 CompiledStaticCall::emit_to_interp_stub(cbuf);
3463 }
3464 %}
3465
3466 // Emit a method handle call.
3467 //
3468 // Method handle calls from compiled to compiled are going thru a
3469 // c2i -> i2c adapter, extending the frame for their arguments. The
3470 // caller however, returns directly to the compiled callee, that has
3471 // to cope with the extended frame. We restore the original frame by
3472 // loading the callers sp and adding the calculated framesize.
3473 enc_class enc_java_handle_call(method meth) %{
3474 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3475
3476 MacroAssembler _masm(&cbuf);
3477 address entry_point = (address)$meth$$method;
3478
3479 // Remember the offset not the address.
3480 const int start_offset = __ offset();
3481 // The trampoline stub.
3482 if (!ra_->C->in_scratch_emit_size()) {
3483 // No entry point given, use the current pc.
3484 // Make sure branch fits into
3485 if (entry_point == 0) entry_point = __ pc();
3486
3487 // Put the entry point as a constant into the constant pool.
3488 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3489 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3490
3491 // Emit the trampoline stub which will be related to the branch-and-link below.
3492 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3493 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3494 __ relocate(relocInfo::opt_virtual_call_type);
3495 }
3496
3497 // The real call.
3498 // Note: At this point we do not have the address of the trampoline
3499 // stub, and the entry point might be too far away for bl, so __ pc()
3500 // serves as dummy and the bl will be patched later.
3501 cbuf.set_insts_mark();
3502 __ bl(__ pc()); // Emits a relocation.
3503
3504 assert(_method, "execute next statement conditionally");
3505 // The stub for call to interpreter.
3506 CompiledStaticCall::emit_to_interp_stub(cbuf);
3507
3508 // Restore original sp.
3509 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3510 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3511 unsigned int bytes = (unsigned int)framesize;
3512 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3513 if (Assembler::is_simm(-offset, 16)) {
3514 __ addi(R1_SP, R11_scratch1, -offset);
3515 } else {
3516 __ load_const_optimized(R12_scratch2, -offset);
3517 __ add(R1_SP, R11_scratch1, R12_scratch2);
3518 }
3519 #ifdef ASSERT
3520 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3521 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3522 __ asm_assert_eq("backlink changed", 0x8000);
3523 #endif
3524 // If fails should store backlink before unextending.
3525
3526 if (ra_->C->env()->failing()) {
3527 return;
3528 }
3529 %}
3530
3531 // Second node of expanded dynamic call - the call.
3532 enc_class enc_java_dynamic_call_sched(method meth) %{
3533 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3534
3535 MacroAssembler _masm(&cbuf);
3536
3537 if (!ra_->C->in_scratch_emit_size()) {
3538 // Create a call trampoline stub for the given method.
3539 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3540 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3541 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3542 emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3543
3544 if (ra_->C->env()->failing())
3545 return;
3546
3547 // Build relocation at call site with ic position as data.
3548 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3549 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3550 "must have one, but can't have both");
3551 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3552 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3553 "must contain instruction offset");
3554 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3555 ? _load_ic_hi_node->_cbuf_insts_offset
3556 : _load_ic_node->_cbuf_insts_offset;
3557 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3558 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3559 "should be load from TOC");
3560
3561 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3562 }
3563
3564 // At this point I do not have the address of the trampoline stub,
3565 // and the entry point might be too far away for bl. Pc() serves
3566 // as dummy and bl will be patched later.
3567 __ bl((address) __ pc());
3568 %}
3569
3570 // postalloc expand emitter for virtual calls.
3571 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3572
3573 // Create the nodes for loading the IC from the TOC.
3574 loadConLNodesTuple loadConLNodes_IC =
3575 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3576 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3577
3578 // Create the call node.
3579 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3580 call->_method_handle_invoke = _method_handle_invoke;
3581 call->_vtable_index = _vtable_index;
3582 call->_method = _method;
3583 call->_bci = _bci;
3584 call->_optimized_virtual = _optimized_virtual;
3585 call->_tf = _tf;
3586 call->_entry_point = _entry_point;
3587 call->_cnt = _cnt;
3588 call->_argsize = _argsize;
3589 call->_oop_map = _oop_map;
3590 call->_jvms = _jvms;
3591 call->_jvmadj = _jvmadj;
3592 call->_in_rms = _in_rms;
3593 call->_nesting = _nesting;
3594
3595 // New call needs all inputs of old call.
3596 // Req...
3597 for (uint i = 0; i < req(); ++i) {
3598 // The expanded node does not need toc any more.
3599 // Add the inline cache constant here instead. This expresses the
3600 // register of the inline cache must be live at the call.
3601 // Else we would have to adapt JVMState by -1.
3602 if (i == mach_constant_base_node_input()) {
3603 call->add_req(loadConLNodes_IC._last);
3604 } else {
3605 call->add_req(in(i));
3606 }
3607 }
3608 // ...as well as prec
3609 for (uint i = req(); i < len(); ++i) {
3610 call->add_prec(in(i));
3611 }
3612
3613 // Remember nodes loading the inline cache into r19.
3614 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3615 call->_load_ic_node = loadConLNodes_IC._small;
3616
3617 // Operands for new nodes.
3618 call->_opnds[0] = _opnds[0];
3619 call->_opnds[1] = _opnds[1];
3620
3621 // Only the inline cache is associated with a register.
3622 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3623
3624 // Push new nodes.
3625 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3626 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3627 nodes->push(call);
3628 %}
3629
3630 // Compound version of call dynamic
3631 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3632 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3633 MacroAssembler _masm(&cbuf);
3634 int start_offset = __ offset();
3635
3636 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3637 #if 0
3638 if (_vtable_index < 0) {
3639 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3640 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3641 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3642 AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word());
3643
3644 address virtual_call_meta_addr = __ pc();
3645 __ load_const_from_method_toc(ic_reg, meta, Rtoc);
3646 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3647 // to determine who we intended to call.
3648 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3649 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3650 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3651 "Fix constant in ret_addr_offset()");
3652 } else {
3653 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3654 // Go thru the vtable. Get receiver klass. Receiver already
3655 // checked for non-null. If we'll go thru a C2I adapter, the
3656 // interpreter expects method in R19_method.
3657
3658 __ load_klass(R11_scratch1, R3);
3659
3660 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3661 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3662 __ li(R19_method, v_off);
3663 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3664 // NOTE: for vtable dispatches, the vtable entry will never be
3665 // null. However it may very well end up in handle_wrong_method
3666 // if the method is abstract for the particular class.
3667 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3668 // Call target. Either compiled code or C2I adapter.
3669 __ mtctr(R11_scratch1);
3670 __ bctrl();
3671 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3672 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3673 }
3674 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3675 "Fix constant in ret_addr_offset()");
3676 }
3677 #endif
3678 guarantee(0, "Fix handling of toc edge: messes up derived/base pairs.");
3679 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3680 %}
3681
3682 // a runtime call
3683 enc_class enc_java_to_runtime_call (method meth) %{
3684 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3685
3686 MacroAssembler _masm(&cbuf);
3687 const address start_pc = __ pc();
3688
3689 // The function we're going to call.
3690 FunctionDescriptor fdtemp;
3691 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3692
3693 Register Rtoc = R12_scratch2;
3694 // Calculate the method's TOC.
3695 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3696 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3697 // pool entries; call_c_using_toc will optimize the call.
3698 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3699
3700 // Check the ret_addr_offset.
3701 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3702 "Fix constant in ret_addr_offset()");
3703 %}
3704
3705 // Move to ctr for leaf call.
3706 // This enc_class is needed so that scheduler gets proper
3707 // input mapping for latency computation.
3708 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3709 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3710 MacroAssembler _masm(&cbuf);
3711 __ mtctr($src$$Register);
3712 %}
3713
3714 // postalloc expand emitter for runtime leaf calls.
3715 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3716 // Get the struct that describes the function we are about to call.
3717 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3718 assert(fd, "need fd here");
3719 // new nodes
3720 loadConLNodesTuple loadConLNodes_Entry;
3721 loadConLNodesTuple loadConLNodes_Env;
3722 loadConLNodesTuple loadConLNodes_Toc;
3723 MachNode *mtctr = NULL;
3724 MachCallLeafNode *call = NULL;
3725
3726 // Create nodes and operands for loading the entry point.
3727 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->entry()),
3728 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3729
3730
3731 // Create nodes and operands for loading the env pointer.
3732 if (fd->env() != NULL) {
3733 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3734 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3735 } else {
3736 loadConLNodes_Env._large_hi = NULL;
3737 loadConLNodes_Env._large_lo = NULL;
3738 loadConLNodes_Env._small = NULL;
3739 loadConLNodes_Env._last = new (C) loadConL16Node();
3740 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3741 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3742 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3743 }
3744
3745 // Create nodes and operands for loading the Toc point.
3746 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3747 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3748 // mtctr node
3749 mtctr = new (C) CallLeafDirect_mtctrNode();
3750
3751 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3752 mtctr->add_req(0, loadConLNodes_Entry._last);
3753
3754 mtctr->_opnds[0] = new (C) iRegLdstOper();
3755 mtctr->_opnds[1] = new (C) iRegLdstOper();
3756
3757 // call node
3758 call = new (C) CallLeafDirectNode();
3759
3760 call->_opnds[0] = _opnds[0];
3761 call->_opnds[1] = new (C) methodOper((intptr_t) fd->entry()); // may get set later
3762
3763 // Make the new call node look like the old one.
3764 call->_name = _name;
3765 call->_tf = _tf;
3766 call->_entry_point = _entry_point;
3767 call->_cnt = _cnt;
3768 call->_argsize = _argsize;
3769 call->_oop_map = _oop_map;
3770 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3771 call->_jvms = NULL;
3772 call->_jvmadj = _jvmadj;
3773 call->_in_rms = _in_rms;
3774 call->_nesting = _nesting;
3775
3776
3777 // New call needs all inputs of old call.
3778 // Req...
3779 for (uint i = 0; i < req(); ++i) {
3780 if (i != mach_constant_base_node_input()) {
3781 call->add_req(in(i));
3782 }
3783 }
3784
3785 // These must be reqired edges, as the registers are live up to
3786 // the call. Else the constants are handled as kills.
3787 call->add_req(mtctr);
3788 call->add_req(loadConLNodes_Env._last);
3789 call->add_req(loadConLNodes_Toc._last);
3790
3791 // ...as well as prec
3792 for (uint i = req(); i < len(); ++i) {
3793 call->add_prec(in(i));
3794 }
3795
3796 // registers
3797 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3798
3799 // Insert the new nodes.
3800 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3801 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3802 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3803 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3804 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3805 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3806 nodes->push(mtctr);
3807 nodes->push(call);
3808 %}
3809 %}
3810
3811 //----------FRAME--------------------------------------------------------------
3812 // Definition of frame structure and management information.
3813
3814 frame %{
3815 // What direction does stack grow in (assumed to be same for native & Java).
3816 stack_direction(TOWARDS_LOW);
3817
3818 // These two registers define part of the calling convention between
3819 // compiled code and the interpreter.
3820
3821 // Inline Cache Register or method for I2C.
3822 inline_cache_reg(R19); // R19_method
3823
3824 // Method Oop Register when calling interpreter.
3825 interpreter_method_oop_reg(R19); // R19_method
3826
3827 // Optional: name the operand used by cisc-spilling to access
3828 // [stack_pointer + offset].
3829 cisc_spilling_operand_name(indOffset);
3830
3831 // Number of stack slots consumed by a Monitor enter.
3832 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3833
3834 // Compiled code's Frame Pointer.
3835 frame_pointer(R1); // R1_SP
3836
3837 // Interpreter stores its frame pointer in a register which is
3838 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3839 // interpreted java to compiled java.
3840 //
3841 // R14_state holds pointer to caller's cInterpreter.
3842 interpreter_frame_pointer(R14); // R14_state
3843
3844 stack_alignment(frame::alignment_in_bytes);
3845
3846 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3847
3848 // Number of outgoing stack slots killed above the
3849 // out_preserve_stack_slots for calls to C. Supports the var-args
3850 // backing area for register parms.
3851 //
3852 varargs_C_out_slots_killed(((frame::abi_112_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3853
3854 // The after-PROLOG location of the return address. Location of
3855 // return address specifies a type (REG or STACK) and a number
3856 // representing the register number (i.e. - use a register name) or
3857 // stack slot.
3858 //
3859 // A: Link register is stored in stack slot ...
3860 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3861 // J: Therefore, we make sure that the link register is also in R11_scratch1
3862 // at the end of the prolog.
3863 // B: We use R20, now.
3864 //return_addr(REG R20);
3865
3866 // G: After reading the comments made by all the luminaries on their
3867 // failure to tell the compiler where the return address really is,
3868 // I hardly dare to try myself. However, I'm convinced it's in slot
3869 // 4 what apparently works and saves us some spills.
3870 return_addr(STACK 4);
3871
3872 // This is the body of the function
3873 //
3874 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3875 // uint length, // length of array
3876 // bool is_outgoing)
3877 //
3878 // The `sig' array is to be updated. sig[j] represents the location
3879 // of the j-th argument, either a register or a stack slot.
3880
3881 // Comment taken from i486.ad:
3882 // Body of function which returns an integer array locating
3883 // arguments either in registers or in stack slots. Passed an array
3884 // of ideal registers called "sig" and a "length" count. Stack-slot
3885 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3886 // arguments for a CALLEE. Incoming stack arguments are
3887 // automatically biased by the preserve_stack_slots field above.
3888 calling_convention %{
3889 // No difference between ingoing/outgoing. Just pass false.
3890 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3891 %}
3892
3893 // Comment taken from i486.ad:
3894 // Body of function which returns an integer array locating
3895 // arguments either in registers or in stack slots. Passed an array
3896 // of ideal registers called "sig" and a "length" count. Stack-slot
3897 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3898 // arguments for a CALLEE. Incoming stack arguments are
3899 // automatically biased by the preserve_stack_slots field above.
3900 c_calling_convention %{
3901 // This is obviously always outgoing.
3902 // C argument in register AND stack slot.
3903 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3904 %}
3905
3906 // Location of native (C/C++) and interpreter return values. This
3907 // is specified to be the same as Java. In the 32-bit VM, long
3908 // values are actually returned from native calls in O0:O1 and
3909 // returned to the interpreter in I0:I1. The copying to and from
3910 // the register pairs is done by the appropriate call and epilog
3911 // opcodes. This simplifies the register allocator.
3912 c_return_value %{
3913 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3914 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3915 "only return normal values");
3916 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3917 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3918 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3919 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3920 %}
3921
3922 // Location of compiled Java return values. Same as C
3923 return_value %{
3924 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3925 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3926 "only return normal values");
3927 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3928 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3929 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3930 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3931 %}
3932 %}
3933
3934
3935 //----------ATTRIBUTES---------------------------------------------------------
3936
3937 //----------Operand Attributes-------------------------------------------------
3938 op_attrib op_cost(1); // Required cost attribute.
3939
3940 //----------Instruction Attributes---------------------------------------------
3941
3942 // Cost attribute. required.
3943 ins_attrib ins_cost(DEFAULT_COST);
3944
3945 // Is this instruction a non-matching short branch variant of some
3946 // long branch? Not required.
3947 ins_attrib ins_short_branch(0);
3948
3949 ins_attrib ins_is_TrapBasedCheckNode(true);
3950
3951 // Number of constants.
3952 // This instruction uses the given number of constants
3953 // (optional attribute).
3954 // This is needed to determine in time whether the constant pool will
3955 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3956 // is determined. It's also used to compute the constant pool size
3957 // in Output().
3958 ins_attrib ins_num_consts(0);
3959
3960 // Required alignment attribute (must be a power of 2) specifies the
3961 // alignment that some part of the instruction (not necessarily the
3962 // start) requires. If > 1, a compute_padding() function must be
3963 // provided for the instruction.
3964 ins_attrib ins_alignment(1);
3965
3966 // Enforce/prohibit rematerializations.
3967 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3968 // then rematerialization of that instruction is prohibited and the
3969 // instruction's value will be spilled if necessary.
3970 // Causes that MachNode::rematerialize() returns false.
3971 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3972 // then rematerialization should be enforced and a copy of the instruction
3973 // should be inserted if possible; rematerialization is not guaranteed.
3974 // Note: this may result in rematerializations in front of every use.
3975 // Causes that MachNode::rematerialize() can return true.
3976 // (optional attribute)
3977 ins_attrib ins_cannot_rematerialize(false);
3978 ins_attrib ins_should_rematerialize(false);
3979
3980 // Instruction has variable size depending on alignment.
3981 ins_attrib ins_variable_size_depending_on_alignment(false);
3982
3983 // Instruction is a nop.
3984 ins_attrib ins_is_nop(false);
3985
3986 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3987 ins_attrib ins_use_mach_if_fast_lock_node(false);
3988
3989 // Field for the toc offset of a constant.
3990 //
3991 // This is needed if the toc offset is not encodable as an immediate in
3992 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3993 // added to the toc, and from this a load with immediate is performed.
3994 // With postalloc expand, we get two nodes that require the same offset
3995 // but which don't know about each other. The offset is only known
3996 // when the constant is added to the constant pool during emitting.
3997 // It is generated in the 'hi'-node adding the upper bits, and saved
3998 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3999 // the offset from there when it gets encoded.
4000 ins_attrib ins_field_const_toc_offset(0);
4001 ins_attrib ins_field_const_toc_offset_hi_node(0);
4002
4003 // A field that can hold the instructions offset in the code buffer.
4004 // Set in the nodes emitter.
4005 ins_attrib ins_field_cbuf_insts_offset(-1);
4006
4007 // Fields for referencing a call's load-IC-node.
4008 // If the toc offset can not be encoded as an immediate in a load, we
4009 // use two nodes.
4010 ins_attrib ins_field_load_ic_hi_node(0);
4011 ins_attrib ins_field_load_ic_node(0);
4012
4013 //----------OPERANDS-----------------------------------------------------------
4014 // Operand definitions must precede instruction definitions for correct
4015 // parsing in the ADLC because operands constitute user defined types
4016 // which are used in instruction definitions.
4017 //
4018 // Formats are generated automatically for constants and base registers.
4019
4020 //----------Simple Operands----------------------------------------------------
4021 // Immediate Operands
4022
4023 // Integer Immediate: 32-bit
4024 operand immI() %{
4025 match(ConI);
4026 op_cost(40);
4027 format %{ %}
4028 interface(CONST_INTER);
4029 %}
4030
4031 operand immI8() %{
4032 predicate(Assembler::is_simm(n->get_int(), 8));
4033 op_cost(0);
4034 match(ConI);
4035 format %{ %}
4036 interface(CONST_INTER);
4037 %}
4038
4039 // Integer Immediate: 16-bit
4040 operand immI16() %{
4041 predicate(Assembler::is_simm(n->get_int(), 16));
4042 op_cost(0);
4043 match(ConI);
4044 format %{ %}
4045 interface(CONST_INTER);
4046 %}
4047
4048 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4049 operand immIhi16() %{
4050 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4051 match(ConI);
4052 op_cost(0);
4053 format %{ %}
4054 interface(CONST_INTER);
4055 %}
4056
4057 operand immInegpow2() %{
4058 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4059 match(ConI);
4060 op_cost(0);
4061 format %{ %}
4062 interface(CONST_INTER);
4063 %}
4064
4065 operand immIpow2minus1() %{
4066 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4067 match(ConI);
4068 op_cost(0);
4069 format %{ %}
4070 interface(CONST_INTER);
4071 %}
4072
4073 operand immIpowerOf2() %{
4074 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4075 match(ConI);
4076 op_cost(0);
4077 format %{ %}
4078 interface(CONST_INTER);
4079 %}
4080
4081 // Unsigned Integer Immediate: the values 0-31
4082 operand uimmI5() %{
4083 predicate(Assembler::is_uimm(n->get_int(), 5));
4084 match(ConI);
4085 op_cost(0);
4086 format %{ %}
4087 interface(CONST_INTER);
4088 %}
4089
4090 // Unsigned Integer Immediate: 6-bit
4091 operand uimmI6() %{
4092 predicate(Assembler::is_uimm(n->get_int(), 6));
4093 match(ConI);
4094 op_cost(0);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4098
4099 // Unsigned Integer Immediate: 6-bit int, greater than 32
4100 operand uimmI6_ge32() %{
4101 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4102 match(ConI);
4103 op_cost(0);
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4107
4108 // Unsigned Integer Immediate: 15-bit
4109 operand uimmI15() %{
4110 predicate(Assembler::is_uimm(n->get_int(), 15));
4111 match(ConI);
4112 op_cost(0);
4113 format %{ %}
4114 interface(CONST_INTER);
4115 %}
4116
4117 // Unsigned Integer Immediate: 16-bit
4118 operand uimmI16() %{
4119 predicate(Assembler::is_uimm(n->get_int(), 16));
4120 match(ConI);
4121 op_cost(0);
4122 format %{ %}
4123 interface(CONST_INTER);
4124 %}
4125
4126 // constant 'int 0'.
4127 operand immI_0() %{
4128 predicate(n->get_int() == 0);
4129 match(ConI);
4130 op_cost(0);
4131 format %{ %}
4132 interface(CONST_INTER);
4133 %}
4134
4135 // constant 'int 1'.
4136 operand immI_1() %{
4137 predicate(n->get_int() == 1);
4138 match(ConI);
4139 op_cost(0);
4140 format %{ %}
4141 interface(CONST_INTER);
4142 %}
4143
4144 // constant 'int -1'.
4145 operand immI_minus1() %{
4146 predicate(n->get_int() == -1);
4147 match(ConI);
4148 op_cost(0);
4149 format %{ %}
4150 interface(CONST_INTER);
4151 %}
4152
4153 // int value 16.
4154 operand immI_16() %{
4155 predicate(n->get_int() == 16);
4156 match(ConI);
4157 op_cost(0);
4158 format %{ %}
4159 interface(CONST_INTER);
4160 %}
4161
4162 // int value 24.
4163 operand immI_24() %{
4164 predicate(n->get_int() == 24);
4165 match(ConI);
4166 op_cost(0);
4167 format %{ %}
4168 interface(CONST_INTER);
4169 %}
4170
4171 // Compressed oops constants
4172 // Pointer Immediate
4173 operand immN() %{
4174 match(ConN);
4175
4176 op_cost(10);
4177 format %{ %}
4178 interface(CONST_INTER);
4179 %}
4180
4181 // NULL Pointer Immediate
4182 operand immN_0() %{
4183 predicate(n->get_narrowcon() == 0);
4184 match(ConN);
4185
4186 op_cost(0);
4187 format %{ %}
4188 interface(CONST_INTER);
4189 %}
4190
4191 // Compressed klass constants
4192 operand immNKlass() %{
4193 match(ConNKlass);
4194
4195 op_cost(0);
4196 format %{ %}
4197 interface(CONST_INTER);
4198 %}
4199
4200 // This operand can be used to avoid matching of an instruct
4201 // with chain rule.
4202 operand immNKlass_NM() %{
4203 match(ConNKlass);
4204 predicate(false);
4205 op_cost(0);
4206 format %{ %}
4207 interface(CONST_INTER);
4208 %}
4209
4210 // Pointer Immediate: 64-bit
4211 operand immP() %{
4212 match(ConP);
4213 op_cost(0);
4214 format %{ %}
4215 interface(CONST_INTER);
4216 %}
4217
4218 // Operand to avoid match of loadConP.
4219 // This operand can be used to avoid matching of an instruct
4220 // with chain rule.
4221 operand immP_NM() %{
4222 match(ConP);
4223 predicate(false);
4224 op_cost(0);
4225 format %{ %}
4226 interface(CONST_INTER);
4227 %}
4228
4229 // costant 'pointer 0'.
4230 operand immP_0() %{
4231 predicate(n->get_ptr() == 0);
4232 match(ConP);
4233 op_cost(0);
4234 format %{ %}
4235 interface(CONST_INTER);
4236 %}
4237
4238 // pointer 0x0 or 0x1
4239 operand immP_0or1() %{
4240 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4241 match(ConP);
4242 op_cost(0);
4243 format %{ %}
4244 interface(CONST_INTER);
4245 %}
4246
4247 operand immL() %{
4248 match(ConL);
4249 op_cost(40);
4250 format %{ %}
4251 interface(CONST_INTER);
4252 %}
4253
4254 // Long Immediate: 16-bit
4255 operand immL16() %{
4256 predicate(Assembler::is_simm(n->get_long(), 16));
4257 match(ConL);
4258 op_cost(0);
4259 format %{ %}
4260 interface(CONST_INTER);
4261 %}
4262
4263 // Long Immediate: 16-bit, 4-aligned
4264 operand immL16Alg4() %{
4265 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4266 match(ConL);
4267 op_cost(0);
4268 format %{ %}
4269 interface(CONST_INTER);
4270 %}
4271
4272 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4273 operand immL32hi16() %{
4274 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4275 match(ConL);
4276 op_cost(0);
4277 format %{ %}
4278 interface(CONST_INTER);
4279 %}
4280
4281 // Long Immediate: 32-bit
4282 operand immL32() %{
4283 predicate(Assembler::is_simm(n->get_long(), 32));
4284 match(ConL);
4285 op_cost(0);
4286 format %{ %}
4287 interface(CONST_INTER);
4288 %}
4289
4290 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4291 operand immLhighest16() %{
4292 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4293 match(ConL);
4294 op_cost(0);
4295 format %{ %}
4296 interface(CONST_INTER);
4297 %}
4298
4299 operand immLnegpow2() %{
4300 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4301 match(ConL);
4302 op_cost(0);
4303 format %{ %}
4304 interface(CONST_INTER);
4305 %}
4306
4307 operand immLpow2minus1() %{
4308 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4309 (n->get_long() != (jlong)0xffffffffffffffffL));
4310 match(ConL);
4311 op_cost(0);
4312 format %{ %}
4313 interface(CONST_INTER);
4314 %}
4315
4316 // constant 'long 0'.
4317 operand immL_0() %{
4318 predicate(n->get_long() == 0L);
4319 match(ConL);
4320 op_cost(0);
4321 format %{ %}
4322 interface(CONST_INTER);
4323 %}
4324
4325 // constat ' long -1'.
4326 operand immL_minus1() %{
4327 predicate(n->get_long() == -1L);
4328 match(ConL);
4329 op_cost(0);
4330 format %{ %}
4331 interface(CONST_INTER);
4332 %}
4333
4334 // Long Immediate: low 32-bit mask
4335 operand immL_32bits() %{
4336 predicate(n->get_long() == 0xFFFFFFFFL);
4337 match(ConL);
4338 op_cost(0);
4339 format %{ %}
4340 interface(CONST_INTER);
4341 %}
4342
4343 // Unsigned Long Immediate: 16-bit
4344 operand uimmL16() %{
4345 predicate(Assembler::is_uimm(n->get_long(), 16));
4346 match(ConL);
4347 op_cost(0);
4348 format %{ %}
4349 interface(CONST_INTER);
4350 %}
4351
4352 // Float Immediate
4353 operand immF() %{
4354 match(ConF);
4355 op_cost(40);
4356 format %{ %}
4357 interface(CONST_INTER);
4358 %}
4359
4360 // constant 'float +0.0'.
4361 operand immF_0() %{
4362 predicate((n->getf() == 0) &&
4363 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4364 match(ConF);
4365 op_cost(0);
4366 format %{ %}
4367 interface(CONST_INTER);
4368 %}
4369
4370 // Double Immediate
4371 operand immD() %{
4372 match(ConD);
4373 op_cost(40);
4374 format %{ %}
4375 interface(CONST_INTER);
4376 %}
4377
4378 // Integer Register Operands
4379 // Integer Destination Register
4380 // See definition of reg_class bits32_reg_rw.
4381 operand iRegIdst() %{
4382 constraint(ALLOC_IN_RC(bits32_reg_rw));
4383 match(RegI);
4384 match(rscratch1RegI);
4385 match(rscratch2RegI);
4386 match(rarg1RegI);
4387 match(rarg2RegI);
4388 match(rarg3RegI);
4389 match(rarg4RegI);
4390 format %{ %}
4391 interface(REG_INTER);
4392 %}
4393
4394 // Integer Source Register
4395 // See definition of reg_class bits32_reg_ro.
4396 operand iRegIsrc() %{
4397 constraint(ALLOC_IN_RC(bits32_reg_ro));
4398 match(RegI);
4399 match(rscratch1RegI);
4400 match(rscratch2RegI);
4401 match(rarg1RegI);
4402 match(rarg2RegI);
4403 match(rarg3RegI);
4404 match(rarg4RegI);
4405 format %{ %}
4406 interface(REG_INTER);
4407 %}
4408
4409 operand rscratch1RegI() %{
4410 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4411 match(iRegIdst);
4412 format %{ %}
4413 interface(REG_INTER);
4414 %}
4415
4416 operand rscratch2RegI() %{
4417 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4418 match(iRegIdst);
4419 format %{ %}
4420 interface(REG_INTER);
4421 %}
4422
4423 operand rarg1RegI() %{
4424 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4425 match(iRegIdst);
4426 format %{ %}
4427 interface(REG_INTER);
4428 %}
4429
4430 operand rarg2RegI() %{
4431 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4432 match(iRegIdst);
4433 format %{ %}
4434 interface(REG_INTER);
4435 %}
4436
4437 operand rarg3RegI() %{
4438 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4439 match(iRegIdst);
4440 format %{ %}
4441 interface(REG_INTER);
4442 %}
4443
4444 operand rarg4RegI() %{
4445 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4446 match(iRegIdst);
4447 format %{ %}
4448 interface(REG_INTER);
4449 %}
4450
4451 operand rarg1RegL() %{
4452 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4453 match(iRegLdst);
4454 format %{ %}
4455 interface(REG_INTER);
4456 %}
4457
4458 operand rarg2RegL() %{
4459 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4460 match(iRegLdst);
4461 format %{ %}
4462 interface(REG_INTER);
4463 %}
4464
4465 operand rarg3RegL() %{
4466 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4467 match(iRegLdst);
4468 format %{ %}
4469 interface(REG_INTER);
4470 %}
4471
4472 operand rarg4RegL() %{
4473 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4474 match(iRegLdst);
4475 format %{ %}
4476 interface(REG_INTER);
4477 %}
4478
4479 // Pointer Destination Register
4480 // See definition of reg_class bits64_reg_rw.
4481 operand iRegPdst() %{
4482 constraint(ALLOC_IN_RC(bits64_reg_rw));
4483 match(RegP);
4484 match(rscratch1RegP);
4485 match(rscratch2RegP);
4486 match(rarg1RegP);
4487 match(rarg2RegP);
4488 match(rarg3RegP);
4489 match(rarg4RegP);
4490 format %{ %}
4491 interface(REG_INTER);
4492 %}
4493
4494 // Pointer Destination Register
4495 // Operand not using r11 and r12 (killed in epilog).
4496 operand iRegPdstNoScratch() %{
4497 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4498 match(RegP);
4499 match(rarg1RegP);
4500 match(rarg2RegP);
4501 match(rarg3RegP);
4502 match(rarg4RegP);
4503 format %{ %}
4504 interface(REG_INTER);
4505 %}
4506
4507 // Pointer Source Register
4508 // See definition of reg_class bits64_reg_ro.
4509 operand iRegPsrc() %{
4510 constraint(ALLOC_IN_RC(bits64_reg_ro));
4511 match(RegP);
4512 match(iRegPdst);
4513 match(rscratch1RegP);
4514 match(rscratch2RegP);
4515 match(rarg1RegP);
4516 match(rarg2RegP);
4517 match(rarg3RegP);
4518 match(rarg4RegP);
4519 match(threadRegP);
4520 format %{ %}
4521 interface(REG_INTER);
4522 %}
4523
4524 // Thread operand.
4525 operand threadRegP() %{
4526 constraint(ALLOC_IN_RC(thread_bits64_reg));
4527 match(iRegPdst);
4528 format %{ "R16" %}
4529 interface(REG_INTER);
4530 %}
4531
4532 operand rscratch1RegP() %{
4533 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4534 match(iRegPdst);
4535 format %{ "R11" %}
4536 interface(REG_INTER);
4537 %}
4538
4539 operand rscratch2RegP() %{
4540 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4541 match(iRegPdst);
4542 format %{ %}
4543 interface(REG_INTER);
4544 %}
4545
4546 operand rarg1RegP() %{
4547 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4548 match(iRegPdst);
4549 format %{ %}
4550 interface(REG_INTER);
4551 %}
4552
4553 operand rarg2RegP() %{
4554 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4555 match(iRegPdst);
4556 format %{ %}
4557 interface(REG_INTER);
4558 %}
4559
4560 operand rarg3RegP() %{
4561 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4562 match(iRegPdst);
4563 format %{ %}
4564 interface(REG_INTER);
4565 %}
4566
4567 operand rarg4RegP() %{
4568 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4569 match(iRegPdst);
4570 format %{ %}
4571 interface(REG_INTER);
4572 %}
4573
4574 operand iRegNsrc() %{
4575 constraint(ALLOC_IN_RC(bits32_reg_ro));
4576 match(RegN);
4577 match(iRegNdst);
4578
4579 format %{ %}
4580 interface(REG_INTER);
4581 %}
4582
4583 operand iRegNdst() %{
4584 constraint(ALLOC_IN_RC(bits32_reg_rw));
4585 match(RegN);
4586
4587 format %{ %}
4588 interface(REG_INTER);
4589 %}
4590
4591 // Long Destination Register
4592 // See definition of reg_class bits64_reg_rw.
4593 operand iRegLdst() %{
4594 constraint(ALLOC_IN_RC(bits64_reg_rw));
4595 match(RegL);
4596 match(rscratch1RegL);
4597 match(rscratch2RegL);
4598 format %{ %}
4599 interface(REG_INTER);
4600 %}
4601
4602 // Long Source Register
4603 // See definition of reg_class bits64_reg_ro.
4604 operand iRegLsrc() %{
4605 constraint(ALLOC_IN_RC(bits64_reg_ro));
4606 match(RegL);
4607 match(iRegLdst);
4608 match(rscratch1RegL);
4609 match(rscratch2RegL);
4610 format %{ %}
4611 interface(REG_INTER);
4612 %}
4613
4614 // Special operand for ConvL2I.
4615 operand iRegL2Isrc(iRegLsrc reg) %{
4616 constraint(ALLOC_IN_RC(bits64_reg_ro));
4617 match(ConvL2I reg);
4618 format %{ "ConvL2I($reg)" %}
4619 interface(REG_INTER)
4620 %}
4621
4622 operand rscratch1RegL() %{
4623 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4624 match(RegL);
4625 format %{ %}
4626 interface(REG_INTER);
4627 %}
4628
4629 operand rscratch2RegL() %{
4630 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4631 match(RegL);
4632 format %{ %}
4633 interface(REG_INTER);
4634 %}
4635
4636 // Condition Code Flag Registers
4637 operand flagsReg() %{
4638 constraint(ALLOC_IN_RC(int_flags));
4639 match(RegFlags);
4640 format %{ %}
4641 interface(REG_INTER);
4642 %}
4643
4644 // Condition Code Flag Register CR0
4645 operand flagsRegCR0() %{
4646 constraint(ALLOC_IN_RC(int_flags_CR0));
4647 match(RegFlags);
4648 format %{ "CR0" %}
4649 interface(REG_INTER);
4650 %}
4651
4652 operand flagsRegCR1() %{
4653 constraint(ALLOC_IN_RC(int_flags_CR1));
4654 match(RegFlags);
4655 format %{ "CR1" %}
4656 interface(REG_INTER);
4657 %}
4658
4659 operand flagsRegCR6() %{
4660 constraint(ALLOC_IN_RC(int_flags_CR6));
4661 match(RegFlags);
4662 format %{ "CR6" %}
4663 interface(REG_INTER);
4664 %}
4665
4666 operand regCTR() %{
4667 constraint(ALLOC_IN_RC(ctr_reg));
4668 // RegFlags should work. Introducing a RegSpecial type would cause a
4669 // lot of changes.
4670 match(RegFlags);
4671 format %{"SR_CTR" %}
4672 interface(REG_INTER);
4673 %}
4674
4675 operand regD() %{
4676 constraint(ALLOC_IN_RC(dbl_reg));
4677 match(RegD);
4678 format %{ %}
4679 interface(REG_INTER);
4680 %}
4681
4682 operand regF() %{
4683 constraint(ALLOC_IN_RC(flt_reg));
4684 match(RegF);
4685 format %{ %}
4686 interface(REG_INTER);
4687 %}
4688
4689 // Special Registers
4690
4691 // Method Register
4692 operand inline_cache_regP(iRegPdst reg) %{
4693 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4694 match(reg);
4695 format %{ %}
4696 interface(REG_INTER);
4697 %}
4698
4699 operand compiler_method_oop_regP(iRegPdst reg) %{
4700 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4701 match(reg);
4702 format %{ %}
4703 interface(REG_INTER);
4704 %}
4705
4706 operand interpreter_method_oop_regP(iRegPdst reg) %{
4707 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4708 match(reg);
4709 format %{ %}
4710 interface(REG_INTER);
4711 %}
4712
4713 // Operands to remove register moves in unscaled mode.
4714 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4715 operand iRegP2N(iRegPsrc reg) %{
4716 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4717 constraint(ALLOC_IN_RC(bits64_reg_ro));
4718 match(EncodeP reg);
4719 format %{ "$reg" %}
4720 interface(REG_INTER)
4721 %}
4722
4723 operand iRegN2P(iRegNsrc reg) %{
4724 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4725 constraint(ALLOC_IN_RC(bits32_reg_ro));
4726 match(DecodeN reg);
4727 match(DecodeNKlass reg);
4728 format %{ "$reg" %}
4729 interface(REG_INTER)
4730 %}
4731
4732 //----------Complex Operands---------------------------------------------------
4733 // Indirect Memory Reference
4734 operand indirect(iRegPsrc reg) %{
4735 constraint(ALLOC_IN_RC(bits64_reg_ro));
4736 match(reg);
4737 op_cost(100);
4738 format %{ "[$reg]" %}
4739 interface(MEMORY_INTER) %{
4740 base($reg);
4741 index(0x0);
4742 scale(0x0);
4743 disp(0x0);
4744 %}
4745 %}
4746
4747 // Indirect with Offset
4748 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4749 constraint(ALLOC_IN_RC(bits64_reg_ro));
4750 match(AddP reg offset);
4751 op_cost(100);
4752 format %{ "[$reg + $offset]" %}
4753 interface(MEMORY_INTER) %{
4754 base($reg);
4755 index(0x0);
4756 scale(0x0);
4757 disp($offset);
4758 %}
4759 %}
4760
4761 // Indirect with 4-aligned Offset
4762 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4763 constraint(ALLOC_IN_RC(bits64_reg_ro));
4764 match(AddP reg offset);
4765 op_cost(100);
4766 format %{ "[$reg + $offset]" %}
4767 interface(MEMORY_INTER) %{
4768 base($reg);
4769 index(0x0);
4770 scale(0x0);
4771 disp($offset);
4772 %}
4773 %}
4774
4775 //----------Complex Operands for Compressed OOPs-------------------------------
4776 // Compressed OOPs with narrow_oop_shift == 0.
4777
4778 // Indirect Memory Reference, compressed OOP
4779 operand indirectNarrow(iRegNsrc reg) %{
4780 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4781 constraint(ALLOC_IN_RC(bits64_reg_ro));
4782 match(DecodeN reg);
4783 match(DecodeNKlass reg);
4784 op_cost(100);
4785 format %{ "[$reg]" %}
4786 interface(MEMORY_INTER) %{
4787 base($reg);
4788 index(0x0);
4789 scale(0x0);
4790 disp(0x0);
4791 %}
4792 %}
4793
4794 // Indirect with Offset, compressed OOP
4795 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4796 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4797 constraint(ALLOC_IN_RC(bits64_reg_ro));
4798 match(AddP (DecodeN reg) offset);
4799 match(AddP (DecodeNKlass reg) offset);
4800 op_cost(100);
4801 format %{ "[$reg + $offset]" %}
4802 interface(MEMORY_INTER) %{
4803 base($reg);
4804 index(0x0);
4805 scale(0x0);
4806 disp($offset);
4807 %}
4808 %}
4809
4810 // Indirect with 4-aligned Offset, compressed OOP
4811 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4812 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4813 constraint(ALLOC_IN_RC(bits64_reg_ro));
4814 match(AddP (DecodeN reg) offset);
4815 match(AddP (DecodeNKlass reg) offset);
4816 op_cost(100);
4817 format %{ "[$reg + $offset]" %}
4818 interface(MEMORY_INTER) %{
4819 base($reg);
4820 index(0x0);
4821 scale(0x0);
4822 disp($offset);
4823 %}
4824 %}
4825
4826 //----------Special Memory Operands--------------------------------------------
4827 // Stack Slot Operand
4828 //
4829 // This operand is used for loading and storing temporary values on
4830 // the stack where a match requires a value to flow through memory.
4831 operand stackSlotI(sRegI reg) %{
4832 constraint(ALLOC_IN_RC(stack_slots));
4833 op_cost(100);
4834 //match(RegI);
4835 format %{ "[sp+$reg]" %}
4836 interface(MEMORY_INTER) %{
4837 base(0x1); // R1_SP
4838 index(0x0);
4839 scale(0x0);
4840 disp($reg); // Stack Offset
4841 %}
4842 %}
4843
4844 operand stackSlotL(sRegL reg) %{
4845 constraint(ALLOC_IN_RC(stack_slots));
4846 op_cost(100);
4847 //match(RegL);
4848 format %{ "[sp+$reg]" %}
4849 interface(MEMORY_INTER) %{
4850 base(0x1); // R1_SP
4851 index(0x0);
4852 scale(0x0);
4853 disp($reg); // Stack Offset
4854 %}
4855 %}
4856
4857 operand stackSlotP(sRegP reg) %{
4858 constraint(ALLOC_IN_RC(stack_slots));
4859 op_cost(100);
4860 //match(RegP);
4861 format %{ "[sp+$reg]" %}
4862 interface(MEMORY_INTER) %{
4863 base(0x1); // R1_SP
4864 index(0x0);
4865 scale(0x0);
4866 disp($reg); // Stack Offset
4867 %}
4868 %}
4869
4870 operand stackSlotF(sRegF reg) %{
4871 constraint(ALLOC_IN_RC(stack_slots));
4872 op_cost(100);
4873 //match(RegF);
4874 format %{ "[sp+$reg]" %}
4875 interface(MEMORY_INTER) %{
4876 base(0x1); // R1_SP
4877 index(0x0);
4878 scale(0x0);
4879 disp($reg); // Stack Offset
4880 %}
4881 %}
4882
4883 operand stackSlotD(sRegD reg) %{
4884 constraint(ALLOC_IN_RC(stack_slots));
4885 op_cost(100);
4886 //match(RegD);
4887 format %{ "[sp+$reg]" %}
4888 interface(MEMORY_INTER) %{
4889 base(0x1); // R1_SP
4890 index(0x0);
4891 scale(0x0);
4892 disp($reg); // Stack Offset
4893 %}
4894 %}
4895
4896 // Operands for expressing Control Flow
4897 // NOTE: Label is a predefined operand which should not be redefined in
4898 // the AD file. It is generically handled within the ADLC.
4899
4900 //----------Conditional Branch Operands----------------------------------------
4901 // Comparison Op
4902 //
4903 // This is the operation of the comparison, and is limited to the
4904 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4905 // (!=).
4906 //
4907 // Other attributes of the comparison, such as unsignedness, are specified
4908 // by the comparison instruction that sets a condition code flags register.
4909 // That result is represented by a flags operand whose subtype is appropriate
4910 // to the unsignedness (etc.) of the comparison.
4911 //
4912 // Later, the instruction which matches both the Comparison Op (a Bool) and
4913 // the flags (produced by the Cmp) specifies the coding of the comparison op
4914 // by matching a specific subtype of Bool operand below.
4915
4916 // When used for floating point comparisons: unordered same as less.
4917 operand cmpOp() %{
4918 match(Bool);
4919 format %{ "" %}
4920 interface(COND_INTER) %{
4921 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4922 // BO & BI
4923 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4924 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4925 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4926 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4927 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4928 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4929 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4930 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4931 %}
4932 %}
4933
4934 //----------OPERAND CLASSES----------------------------------------------------
4935 // Operand Classes are groups of operands that are used to simplify
4936 // instruction definitions by not requiring the AD writer to specify
4937 // seperate instructions for every form of operand when the
4938 // instruction accepts multiple operand types with the same basic
4939 // encoding and format. The classic case of this is memory operands.
4940 // Indirect is not included since its use is limited to Compare & Swap.
4941
4942 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4943 // Memory operand where offsets are 4-aligned. Required for ld, std.
4944 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
4945 opclass indirectMemory(indirect, indirectNarrow);
4946
4947 // Special opclass for I and ConvL2I.
4948 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4949
4950 // Operand classes to match encode and decode. iRegN_P2N is only used
4951 // for storeN. I have never seen an encode node elsewhere.
4952 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4953 opclass iRegP_N2P(iRegPsrc, iRegN2P);
4954
4955 //----------PIPELINE-----------------------------------------------------------
4956
4957 pipeline %{
4958
4959 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4960 // J. Res. & Dev., No. 1, Jan. 2002.
4961
4962 //----------ATTRIBUTES---------------------------------------------------------
4963 attributes %{
4964
4965 // Power4 instructions are of fixed length.
4966 fixed_size_instructions;
4967
4968 // TODO: if `bundle' means number of instructions fetched
4969 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4970 // max instructions issued per cycle, this is 5.
4971 max_instructions_per_bundle = 8;
4972
4973 // A Power4 instruction is 4 bytes long.
4974 instruction_unit_size = 4;
4975
4976 // The Power4 processor fetches 64 bytes...
4977 instruction_fetch_unit_size = 64;
4978
4979 // ...in one line
4980 instruction_fetch_units = 1
4981
4982 // Unused, list one so that array generated by adlc is not empty.
4983 // Aix compiler chokes if _nop_count = 0.
4984 nops(fxNop);
4985 %}
4986
4987 //----------RESOURCES----------------------------------------------------------
4988 // Resources are the functional units available to the machine
4989 resources(
4990 PPC_BR, // branch unit
4991 PPC_CR, // condition unit
4992 PPC_FX1, // integer arithmetic unit 1
4993 PPC_FX2, // integer arithmetic unit 2
4994 PPC_LDST1, // load/store unit 1
4995 PPC_LDST2, // load/store unit 2
4996 PPC_FP1, // float arithmetic unit 1
4997 PPC_FP2, // float arithmetic unit 2
4998 PPC_LDST = PPC_LDST1 | PPC_LDST2,
4999 PPC_FX = PPC_FX1 | PPC_FX2,
5000 PPC_FP = PPC_FP1 | PPC_FP2
5001 );
5002
5003 //----------PIPELINE DESCRIPTION-----------------------------------------------
5004 // Pipeline Description specifies the stages in the machine's pipeline
5005 pipe_desc(
5006 // Power4 longest pipeline path
5007 PPC_IF, // instruction fetch
5008 PPC_IC,
5009 //PPC_BP, // branch prediction
5010 PPC_D0, // decode
5011 PPC_D1, // decode
5012 PPC_D2, // decode
5013 PPC_D3, // decode
5014 PPC_Xfer1,
5015 PPC_GD, // group definition
5016 PPC_MP, // map
5017 PPC_ISS, // issue
5018 PPC_RF, // resource fetch
5019 PPC_EX1, // execute (all units)
5020 PPC_EX2, // execute (FP, LDST)
5021 PPC_EX3, // execute (FP, LDST)
5022 PPC_EX4, // execute (FP)
5023 PPC_EX5, // execute (FP)
5024 PPC_EX6, // execute (FP)
5025 PPC_WB, // write back
5026 PPC_Xfer2,
5027 PPC_CP
5028 );
5029
5030 //----------PIPELINE CLASSES---------------------------------------------------
5031 // Pipeline Classes describe the stages in which input and output are
5032 // referenced by the hardware pipeline.
5033
5034 // Simple pipeline classes.
5035
5036 // Default pipeline class.
5037 pipe_class pipe_class_default() %{
5038 single_instruction;
5039 fixed_latency(2);
5040 %}
5041
5042 // Pipeline class for empty instructions.
5043 pipe_class pipe_class_empty() %{
5044 single_instruction;
5045 fixed_latency(0);
5046 %}
5047
5048 // Pipeline class for compares.
5049 pipe_class pipe_class_compare() %{
5050 single_instruction;
5051 fixed_latency(16);
5052 %}
5053
5054 // Pipeline class for traps.
5055 pipe_class pipe_class_trap() %{
5056 single_instruction;
5057 fixed_latency(100);
5058 %}
5059
5060 // Pipeline class for memory operations.
5061 pipe_class pipe_class_memory() %{
5062 single_instruction;
5063 fixed_latency(16);
5064 %}
5065
5066 // Pipeline class for call.
5067 pipe_class pipe_class_call() %{
5068 single_instruction;
5069 fixed_latency(100);
5070 %}
5071
5072 // Define the class for the Nop node.
5073 define %{
5074 MachNop = pipe_class_default;
5075 %}
5076
5077 %}
5078
5079 //----------INSTRUCTIONS-------------------------------------------------------
5080
5081 // Naming of instructions:
5082 // opA_operB / opA_operB_operC:
5083 // Operation 'op' with one or two source operands 'oper'. Result
5084 // type is A, source operand types are B and C.
5085 // Iff A == B == C, B and C are left out.
5086 //
5087 // The instructions are ordered according to the following scheme:
5088 // - loads
5089 // - load constants
5090 // - prefetch
5091 // - store
5092 // - encode/decode
5093 // - membar
5094 // - conditional moves
5095 // - compare & swap
5096 // - arithmetic and logic operations
5097 // * int: Add, Sub, Mul, Div, Mod
5098 // * int: lShift, arShift, urShift, rot
5099 // * float: Add, Sub, Mul, Div
5100 // * and, or, xor ...
5101 // - register moves: float <-> int, reg <-> stack, repl
5102 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5103 // - conv (low level type cast requiring bit changes (sign extend etc)
5104 // - compares, range & zero checks.
5105 // - branches
5106 // - complex operations, intrinsics, min, max, replicate
5107 // - lock
5108 // - Calls
5109 //
5110 // If there are similar instructions with different types they are sorted:
5111 // int before float
5112 // small before big
5113 // signed before unsigned
5114 // e.g., loadS before loadUS before loadI before loadF.
5115
5116
5117 //----------Load/Store Instructions--------------------------------------------
5118
5119 //----------Load Instructions--------------------------------------------------
5120
5121 // Converts byte to int.
5122 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5123 // reuses the 'amount' operand, but adlc expects that operand specification
5124 // and operands in match rule are equivalent.
5125 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5126 effect(DEF dst, USE src);
5127 format %{ "EXTSB $dst, $src \t// byte->int" %}
5128 size(4);
5129 ins_encode %{
5130 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5131 __ extsb($dst$$Register, $src$$Register);
5132 %}
5133 ins_pipe(pipe_class_default);
5134 %}
5135
5136 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5137 // match-rule, false predicate
5138 match(Set dst (LoadB mem));
5139 predicate(false);
5140
5141 format %{ "LBZ $dst, $mem" %}
5142 size(4);
5143 ins_encode( enc_lbz(dst, mem) );
5144 ins_pipe(pipe_class_memory);
5145 %}
5146
5147 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5148 // match-rule, false predicate
5149 match(Set dst (LoadB mem));
5150 predicate(false);
5151
5152 format %{ "LBZ $dst, $mem\n\t"
5153 "TWI $dst\n\t"
5154 "ISYNC" %}
5155 size(12);
5156 ins_encode( enc_lbz_ac(dst, mem) );
5157 ins_pipe(pipe_class_memory);
5158 %}
5159
5160 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5161 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5162 match(Set dst (LoadB mem));
5163 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5164 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5165 expand %{
5166 iRegIdst tmp;
5167 loadUB_indirect(tmp, mem);
5168 convB2I_reg_2(dst, tmp);
5169 %}
5170 %}
5171
5172 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5173 match(Set dst (LoadB mem));
5174 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5175 expand %{
5176 iRegIdst tmp;
5177 loadUB_indirect_ac(tmp, mem);
5178 convB2I_reg_2(dst, tmp);
5179 %}
5180 %}
5181
5182 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5183 // match-rule, false predicate
5184 match(Set dst (LoadB mem));
5185 predicate(false);
5186
5187 format %{ "LBZ $dst, $mem" %}
5188 size(4);
5189 ins_encode( enc_lbz(dst, mem) );
5190 ins_pipe(pipe_class_memory);
5191 %}
5192
5193 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5194 // match-rule, false predicate
5195 match(Set dst (LoadB mem));
5196 predicate(false);
5197
5198 format %{ "LBZ $dst, $mem\n\t"
5199 "TWI $dst\n\t"
5200 "ISYNC" %}
5201 size(12);
5202 ins_encode( enc_lbz_ac(dst, mem) );
5203 ins_pipe(pipe_class_memory);
5204 %}
5205
5206 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5207 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5208 match(Set dst (LoadB mem));
5209 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5210 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5211
5212 expand %{
5213 iRegIdst tmp;
5214 loadUB_indOffset16(tmp, mem);
5215 convB2I_reg_2(dst, tmp);
5216 %}
5217 %}
5218
5219 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5220 match(Set dst (LoadB mem));
5221 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5222
5223 expand %{
5224 iRegIdst tmp;
5225 loadUB_indOffset16_ac(tmp, mem);
5226 convB2I_reg_2(dst, tmp);
5227 %}
5228 %}
5229
5230 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5231 instruct loadUB(iRegIdst dst, memory mem) %{
5232 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5233 match(Set dst (LoadUB mem));
5234 ins_cost(MEMORY_REF_COST);
5235
5236 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5237 size(4);
5238 ins_encode( enc_lbz(dst, mem) );
5239 ins_pipe(pipe_class_memory);
5240 %}
5241
5242 // Load Unsigned Byte (8bit UNsigned) acquire.
5243 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5244 match(Set dst (LoadUB mem));
5245 ins_cost(3*MEMORY_REF_COST);
5246
5247 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5248 "TWI $dst\n\t"
5249 "ISYNC" %}
5250 size(12);
5251 ins_encode( enc_lbz_ac(dst, mem) );
5252 ins_pipe(pipe_class_memory);
5253 %}
5254
5255 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5256 instruct loadUB2L(iRegLdst dst, memory mem) %{
5257 match(Set dst (ConvI2L (LoadUB mem)));
5258 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5259 ins_cost(MEMORY_REF_COST);
5260
5261 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5262 size(4);
5263 ins_encode( enc_lbz(dst, mem) );
5264 ins_pipe(pipe_class_memory);
5265 %}
5266
5267 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5268 match(Set dst (ConvI2L (LoadUB mem)));
5269 ins_cost(3*MEMORY_REF_COST);
5270
5271 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5272 "TWI $dst\n\t"
5273 "ISYNC" %}
5274 size(12);
5275 ins_encode( enc_lbz_ac(dst, mem) );
5276 ins_pipe(pipe_class_memory);
5277 %}
5278
5279 // Load Short (16bit signed)
5280 instruct loadS(iRegIdst dst, memory mem) %{
5281 match(Set dst (LoadS mem));
5282 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5283 ins_cost(MEMORY_REF_COST);
5284
5285 format %{ "LHA $dst, $mem" %}
5286 size(4);
5287 ins_encode %{
5288 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5289 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5290 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5291 %}
5292 ins_pipe(pipe_class_memory);
5293 %}
5294
5295 // Load Short (16bit signed) acquire.
5296 instruct loadS_ac(iRegIdst dst, memory mem) %{
5297 match(Set dst (LoadS mem));
5298 ins_cost(3*MEMORY_REF_COST);
5299
5300 format %{ "LHA $dst, $mem\t acquire\n\t"
5301 "TWI $dst\n\t"
5302 "ISYNC" %}
5303 size(12);
5304 ins_encode %{
5305 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5306 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5307 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5308 __ twi_0($dst$$Register);
5309 __ isync();
5310 %}
5311 ins_pipe(pipe_class_memory);
5312 %}
5313
5314 // Load Char (16bit unsigned)
5315 instruct loadUS(iRegIdst dst, memory mem) %{
5316 match(Set dst (LoadUS mem));
5317 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5318 ins_cost(MEMORY_REF_COST);
5319
5320 format %{ "LHZ $dst, $mem" %}
5321 size(4);
5322 ins_encode( enc_lhz(dst, mem) );
5323 ins_pipe(pipe_class_memory);
5324 %}
5325
5326 // Load Char (16bit unsigned) acquire.
5327 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5328 match(Set dst (LoadUS mem));
5329 ins_cost(3*MEMORY_REF_COST);
5330
5331 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5332 "TWI $dst\n\t"
5333 "ISYNC" %}
5334 size(12);
5335 ins_encode( enc_lhz_ac(dst, mem) );
5336 ins_pipe(pipe_class_memory);
5337 %}
5338
5339 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5340 instruct loadUS2L(iRegLdst dst, memory mem) %{
5341 match(Set dst (ConvI2L (LoadUS mem)));
5342 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5343 ins_cost(MEMORY_REF_COST);
5344
5345 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5346 size(4);
5347 ins_encode( enc_lhz(dst, mem) );
5348 ins_pipe(pipe_class_memory);
5349 %}
5350
5351 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5352 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5353 match(Set dst (ConvI2L (LoadUS mem)));
5354 ins_cost(3*MEMORY_REF_COST);
5355
5356 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5357 "TWI $dst\n\t"
5358 "ISYNC" %}
5359 size(12);
5360 ins_encode( enc_lhz_ac(dst, mem) );
5361 ins_pipe(pipe_class_memory);
5362 %}
5363
5364 // Load Integer.
5365 instruct loadI(iRegIdst dst, memory mem) %{
5366 match(Set dst (LoadI mem));
5367 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5368 ins_cost(MEMORY_REF_COST);
5369
5370 format %{ "LWZ $dst, $mem" %}
5371 size(4);
5372 ins_encode( enc_lwz(dst, mem) );
5373 ins_pipe(pipe_class_memory);
5374 %}
5375
5376 // Load Integer acquire.
5377 instruct loadI_ac(iRegIdst dst, memory mem) %{
5378 match(Set dst (LoadI mem));
5379 ins_cost(3*MEMORY_REF_COST);
5380
5381 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5382 "TWI $dst\n\t"
5383 "ISYNC" %}
5384 size(12);
5385 ins_encode( enc_lwz_ac(dst, mem) );
5386 ins_pipe(pipe_class_memory);
5387 %}
5388
5389 // Match loading integer and casting it to unsigned int in
5390 // long register.
5391 // LoadI + ConvI2L + AndL 0xffffffff.
5392 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5393 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5394 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5395 ins_cost(MEMORY_REF_COST);
5396
5397 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5398 size(4);
5399 ins_encode( enc_lwz(dst, mem) );
5400 ins_pipe(pipe_class_memory);
5401 %}
5402
5403 // Match loading integer and casting it to long.
5404 instruct loadI2L(iRegLdst dst, memory mem) %{
5405 match(Set dst (ConvI2L (LoadI mem)));
5406 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5407 ins_cost(MEMORY_REF_COST);
5408
5409 format %{ "LWA $dst, $mem \t// loadI2L" %}
5410 size(4);
5411 ins_encode %{
5412 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5413 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5414 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5415 %}
5416 ins_pipe(pipe_class_memory);
5417 %}
5418
5419 // Match loading integer and casting it to long - acquire.
5420 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5421 match(Set dst (ConvI2L (LoadI mem)));
5422 ins_cost(3*MEMORY_REF_COST);
5423
5424 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5425 "TWI $dst\n\t"
5426 "ISYNC" %}
5427 size(12);
5428 ins_encode %{
5429 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5430 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5431 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5432 __ twi_0($dst$$Register);
5433 __ isync();
5434 %}
5435 ins_pipe(pipe_class_memory);
5436 %}
5437
5438 // Load Long - aligned
5439 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5440 match(Set dst (LoadL mem));
5441 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5442 ins_cost(MEMORY_REF_COST);
5443
5444 format %{ "LD $dst, $mem \t// long" %}
5445 size(4);
5446 ins_encode( enc_ld(dst, mem) );
5447 ins_pipe(pipe_class_memory);
5448 %}
5449
5450 // Load Long - aligned acquire.
5451 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5452 match(Set dst (LoadL mem));
5453 ins_cost(3*MEMORY_REF_COST);
5454
5455 format %{ "LD $dst, $mem \t// long acquire\n\t"
5456 "TWI $dst\n\t"
5457 "ISYNC" %}
5458 size(12);
5459 ins_encode( enc_ld_ac(dst, mem) );
5460 ins_pipe(pipe_class_memory);
5461 %}
5462
5463 // Load Long - UNaligned
5464 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5465 match(Set dst (LoadL_unaligned mem));
5466 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5467 ins_cost(MEMORY_REF_COST);
5468
5469 format %{ "LD $dst, $mem \t// unaligned long" %}
5470 size(4);
5471 ins_encode( enc_ld(dst, mem) );
5472 ins_pipe(pipe_class_memory);
5473 %}
5474
5475 // Load nodes for superwords
5476
5477 // Load Aligned Packed Byte
5478 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5479 predicate(n->as_LoadVector()->memory_size() == 8);
5480 match(Set dst (LoadVector mem));
5481 ins_cost(MEMORY_REF_COST);
5482
5483 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5484 size(4);
5485 ins_encode( enc_ld(dst, mem) );
5486 ins_pipe(pipe_class_memory);
5487 %}
5488
5489 // Load Range, range = array length (=jint)
5490 instruct loadRange(iRegIdst dst, memory mem) %{
5491 match(Set dst (LoadRange mem));
5492 ins_cost(MEMORY_REF_COST);
5493
5494 format %{ "LWZ $dst, $mem \t// range" %}
5495 size(4);
5496 ins_encode( enc_lwz(dst, mem) );
5497 ins_pipe(pipe_class_memory);
5498 %}
5499
5500 // Load Compressed Pointer
5501 instruct loadN(iRegNdst dst, memory mem) %{
5502 match(Set dst (LoadN mem));
5503 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5504 ins_cost(MEMORY_REF_COST);
5505
5506 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5507 size(4);
5508 ins_encode( enc_lwz(dst, mem) );
5509 ins_pipe(pipe_class_memory);
5510 %}
5511
5512 // Load Compressed Pointer acquire.
5513 instruct loadN_ac(iRegNdst dst, memory mem) %{
5514 match(Set dst (LoadN mem));
5515 ins_cost(3*MEMORY_REF_COST);
5516
5517 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5518 "TWI $dst\n\t"
5519 "ISYNC" %}
5520 size(12);
5521 ins_encode( enc_lwz_ac(dst, mem) );
5522 ins_pipe(pipe_class_memory);
5523 %}
5524
5525 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5526 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5527 match(Set dst (DecodeN (LoadN mem)));
5528 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5529 ins_cost(MEMORY_REF_COST);
5530
5531 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5532 size(4);
5533 ins_encode( enc_lwz(dst, mem) );
5534 ins_pipe(pipe_class_memory);
5535 %}
5536
5537 // Load Pointer
5538 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5539 match(Set dst (LoadP mem));
5540 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5541 ins_cost(MEMORY_REF_COST);
5542
5543 format %{ "LD $dst, $mem \t// ptr" %}
5544 size(4);
5545 ins_encode( enc_ld(dst, mem) );
5546 ins_pipe(pipe_class_memory);
5547 %}
5548
5549 // Load Pointer acquire.
5550 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5551 match(Set dst (LoadP mem));
5552 ins_cost(3*MEMORY_REF_COST);
5553
5554 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5555 "TWI $dst\n\t"
5556 "ISYNC" %}
5557 size(12);
5558 ins_encode( enc_ld_ac(dst, mem) );
5559 ins_pipe(pipe_class_memory);
5560 %}
5561
5562 // LoadP + CastP2L
5563 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5564 match(Set dst (CastP2X (LoadP mem)));
5565 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5566 ins_cost(MEMORY_REF_COST);
5567
5568 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5569 size(4);
5570 ins_encode( enc_ld(dst, mem) );
5571 ins_pipe(pipe_class_memory);
5572 %}
5573
5574 // Load compressed klass pointer.
5575 instruct loadNKlass(iRegNdst dst, memory mem) %{
5576 match(Set dst (LoadNKlass mem));
5577 ins_cost(MEMORY_REF_COST);
5578
5579 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5580 size(4);
5581 ins_encode( enc_lwz(dst, mem) );
5582 ins_pipe(pipe_class_memory);
5583 %}
5584
5585 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5586 //// TODO: will narrow_klass_shift ever be 0?
5587 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5588 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5589 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5590 // ins_cost(MEMORY_REF_COST);
5591 //
5592 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5593 // size(4);
5594 // ins_encode( enc_lwz(dst, mem) );
5595 // ins_pipe(pipe_class_memory);
5596 //%}
5597
5598 // Load Klass Pointer
5599 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5600 match(Set dst (LoadKlass mem));
5601 ins_cost(MEMORY_REF_COST);
5602
5603 format %{ "LD $dst, $mem \t// klass ptr" %}
5604 size(4);
5605 ins_encode( enc_ld(dst, mem) );
5606 ins_pipe(pipe_class_memory);
5607 %}
5608
5609 // Load Float
5610 instruct loadF(regF dst, memory mem) %{
5611 match(Set dst (LoadF mem));
5612 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5613 ins_cost(MEMORY_REF_COST);
5614
5615 format %{ "LFS $dst, $mem" %}
5616 size(4);
5617 ins_encode %{
5618 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5619 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5620 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5621 %}
5622 ins_pipe(pipe_class_memory);
5623 %}
5624
5625 // Load Float acquire.
5626 instruct loadF_ac(regF dst, memory mem) %{
5627 match(Set dst (LoadF mem));
5628 ins_cost(3*MEMORY_REF_COST);
5629
5630 format %{ "LFS $dst, $mem \t// acquire\n\t"
5631 "FCMPU cr0, $dst, $dst\n\t"
5632 "BNE cr0, next\n"
5633 "next:\n\t"
5634 "ISYNC" %}
5635 size(16);
5636 ins_encode %{
5637 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5638 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5639 Label next;
5640 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5641 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5642 __ bne(CCR0, next);
5643 __ bind(next);
5644 __ isync();
5645 %}
5646 ins_pipe(pipe_class_memory);
5647 %}
5648
5649 // Load Double - aligned
5650 instruct loadD(regD dst, memory mem) %{
5651 match(Set dst (LoadD mem));
5652 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5653 ins_cost(MEMORY_REF_COST);
5654
5655 format %{ "LFD $dst, $mem" %}
5656 size(4);
5657 ins_encode( enc_lfd(dst, mem) );
5658 ins_pipe(pipe_class_memory);
5659 %}
5660
5661 // Load Double - aligned acquire.
5662 instruct loadD_ac(regD dst, memory mem) %{
5663 match(Set dst (LoadD mem));
5664 ins_cost(3*MEMORY_REF_COST);
5665
5666 format %{ "LFD $dst, $mem \t// acquire\n\t"
5667 "FCMPU cr0, $dst, $dst\n\t"
5668 "BNE cr0, next\n"
5669 "next:\n\t"
5670 "ISYNC" %}
5671 size(16);
5672 ins_encode %{
5673 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5674 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5675 Label next;
5676 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5677 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5678 __ bne(CCR0, next);
5679 __ bind(next);
5680 __ isync();
5681 %}
5682 ins_pipe(pipe_class_memory);
5683 %}
5684
5685 // Load Double - UNaligned
5686 instruct loadD_unaligned(regD dst, memory mem) %{
5687 match(Set dst (LoadD_unaligned mem));
5688 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5689 ins_cost(MEMORY_REF_COST);
5690
5691 format %{ "LFD $dst, $mem" %}
5692 size(4);
5693 ins_encode( enc_lfd(dst, mem) );
5694 ins_pipe(pipe_class_memory);
5695 %}
5696
5697 //----------Constants--------------------------------------------------------
5698
5699 // Load MachConstantTableBase: add hi offset to global toc.
5700 // TODO: Handle hidden register r29 in bundler!
5701 instruct loadToc_hi(iRegLdst dst) %{
5702 effect(DEF dst);
5703 ins_cost(DEFAULT_COST);
5704
5705 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5706 size(4);
5707 ins_encode %{
5708 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5709 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5710 %}
5711 ins_pipe(pipe_class_default);
5712 %}
5713
5714 // Load MachConstantTableBase: add lo offset to global toc.
5715 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5716 effect(DEF dst, USE src);
5717 ins_cost(DEFAULT_COST);
5718
5719 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5720 size(4);
5721 ins_encode %{
5722 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5723 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5724 %}
5725 ins_pipe(pipe_class_default);
5726 %}
5727
5728 // Load 16-bit integer constant 0xssss????
5729 instruct loadConI16(iRegIdst dst, immI16 src) %{
5730 match(Set dst src);
5731
5732 format %{ "LI $dst, $src" %}
5733 size(4);
5734 ins_encode %{
5735 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5736 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5737 %}
5738 ins_pipe(pipe_class_default);
5739 %}
5740
5741 // Load integer constant 0x????0000
5742 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5743 match(Set dst src);
5744 ins_cost(DEFAULT_COST);
5745
5746 format %{ "LIS $dst, $src.hi" %}
5747 size(4);
5748 ins_encode %{
5749 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5750 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5751 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5752 %}
5753 ins_pipe(pipe_class_default);
5754 %}
5755
5756 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5757 // and sign extended), this adds the low 16 bits.
5758 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5759 // no match-rule, false predicate
5760 effect(DEF dst, USE src1, USE src2);
5761 predicate(false);
5762
5763 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5764 size(4);
5765 ins_encode %{
5766 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5767 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5768 %}
5769 ins_pipe(pipe_class_default);
5770 %}
5771
5772 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5773 match(Set dst src);
5774 ins_cost(DEFAULT_COST*2);
5775
5776 expand %{
5777 // Would like to use $src$$constant.
5778 immI16 srcLo %{ _opnds[1]->constant() %}
5779 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5780 immIhi16 srcHi %{ _opnds[1]->constant() %}
5781 iRegIdst tmpI;
5782 loadConIhi16(tmpI, srcHi);
5783 loadConI32_lo16(dst, tmpI, srcLo);
5784 %}
5785 %}
5786
5787 // No constant pool entries required.
5788 instruct loadConL16(iRegLdst dst, immL16 src) %{
5789 match(Set dst src);
5790
5791 format %{ "LI $dst, $src \t// long" %}
5792 size(4);
5793 ins_encode %{
5794 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5795 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5796 %}
5797 ins_pipe(pipe_class_default);
5798 %}
5799
5800 // Load long constant 0xssssssss????0000
5801 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5802 match(Set dst src);
5803 ins_cost(DEFAULT_COST);
5804
5805 format %{ "LIS $dst, $src.hi \t// long" %}
5806 size(4);
5807 ins_encode %{
5808 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5809 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5810 %}
5811 ins_pipe(pipe_class_default);
5812 %}
5813
5814 // To load a 32 bit constant: merge lower 16 bits into already loaded
5815 // high 16 bits.
5816 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5817 // no match-rule, false predicate
5818 effect(DEF dst, USE src1, USE src2);
5819 predicate(false);
5820
5821 format %{ "ORI $dst, $src1, $src2.lo" %}
5822 size(4);
5823 ins_encode %{
5824 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5825 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5826 %}
5827 ins_pipe(pipe_class_default);
5828 %}
5829
5830 // Load 32-bit long constant
5831 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5832 match(Set dst src);
5833 ins_cost(DEFAULT_COST*2);
5834
5835 expand %{
5836 // Would like to use $src$$constant.
5837 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5838 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5839 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5840 iRegLdst tmpL;
5841 loadConL32hi16(tmpL, srcHi);
5842 loadConL32_lo16(dst, tmpL, srcLo);
5843 %}
5844 %}
5845
5846 // Load long constant 0x????000000000000.
5847 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5848 match(Set dst src);
5849 ins_cost(DEFAULT_COST);
5850
5851 expand %{
5852 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5853 immI shift32 %{ 32 %}
5854 iRegLdst tmpL;
5855 loadConL32hi16(tmpL, srcHi);
5856 lshiftL_regL_immI(dst, tmpL, shift32);
5857 %}
5858 %}
5859
5860 // Expand node for constant pool load: small offset.
5861 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5862 effect(DEF dst, USE src, USE toc);
5863 ins_cost(MEMORY_REF_COST);
5864
5865 ins_num_consts(1);
5866 // Needed so that CallDynamicJavaDirect can compute the address of this
5867 // instruction for relocation.
5868 ins_field_cbuf_insts_offset(int);
5869
5870 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5871 size(4);
5872 ins_encode( enc_load_long_constL(dst, src, toc) );
5873 ins_pipe(pipe_class_memory);
5874 %}
5875
5876 // Expand node for constant pool load: large offset.
5877 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5878 effect(DEF dst, USE src, USE toc);
5879 predicate(false);
5880
5881 ins_num_consts(1);
5882 ins_field_const_toc_offset(int);
5883 // Needed so that CallDynamicJavaDirect can compute the address of this
5884 // instruction for relocation.
5885 ins_field_cbuf_insts_offset(int);
5886
5887 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5888 size(4);
5889 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5890 ins_pipe(pipe_class_default);
5891 %}
5892
5893 // Expand node for constant pool load: large offset.
5894 // No constant pool entries required.
5895 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5896 effect(DEF dst, USE src, USE base);
5897 predicate(false);
5898
5899 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5900
5901 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5902 size(4);
5903 ins_encode %{
5904 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5905 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5906 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5907 %}
5908 ins_pipe(pipe_class_memory);
5909 %}
5910
5911 // Load long constant from constant table. Expand in case of
5912 // offset > 16 bit is needed.
5913 // Adlc adds toc node MachConstantTableBase.
5914 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5915 match(Set dst src);
5916 ins_cost(MEMORY_REF_COST);
5917
5918 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5919 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5920 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5921 %}
5922
5923 // Load NULL as compressed oop.
5924 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5925 match(Set dst src);
5926 ins_cost(DEFAULT_COST);
5927
5928 format %{ "LI $dst, $src \t// compressed ptr" %}
5929 size(4);
5930 ins_encode %{
5931 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5932 __ li($dst$$Register, 0);
5933 %}
5934 ins_pipe(pipe_class_default);
5935 %}
5936
5937 // Load hi part of compressed oop constant.
5938 instruct loadConN_hi(iRegNdst dst, immN src) %{
5939 effect(DEF dst, USE src);
5940 ins_cost(DEFAULT_COST);
5941
5942 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5943 size(4);
5944 ins_encode %{
5945 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5946 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5947 %}
5948 ins_pipe(pipe_class_default);
5949 %}
5950
5951 // Add lo part of compressed oop constant to already loaded hi part.
5952 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5953 effect(DEF dst, USE src1, USE src2);
5954 ins_cost(DEFAULT_COST);
5955
5956 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5957 size(4);
5958 ins_encode %{
5959 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5960 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5961 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5962 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5963 __ relocate(rspec, 1);
5964 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5965 %}
5966 ins_pipe(pipe_class_default);
5967 %}
5968
5969 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5970 // leaving the upper 32 bits with sign-extension bits.
5971 // This clears these bits: dst = src & 0xFFFFFFFF.
5972 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5973 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5974 effect(DEF dst, USE src);
5975 predicate(false);
5976
5977 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
5978 size(4);
5979 ins_encode %{
5980 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5981 __ clrldi($dst$$Register, $src$$Register, 0x20);
5982 %}
5983 ins_pipe(pipe_class_default);
5984 %}
5985
5986 // Loading ConN must be postalloc expanded so that edges between
5987 // the nodes are safe. They may not interfere with a safepoint.
5988 // GL TODO: This needs three instructions: better put this into the constant pool.
5989 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5990 match(Set dst src);
5991 ins_cost(DEFAULT_COST*2);
5992
5993 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
5994 postalloc_expand %{
5995 MachNode *m1 = new (C) loadConN_hiNode();
5996 MachNode *m2 = new (C) loadConN_loNode();
5997 MachNode *m3 = new (C) clearMs32bNode();
5998 m1->add_req(NULL);
5999 m2->add_req(NULL, m1);
6000 m3->add_req(NULL, m2);
6001 m1->_opnds[0] = op_dst;
6002 m1->_opnds[1] = op_src;
6003 m2->_opnds[0] = op_dst;
6004 m2->_opnds[1] = op_dst;
6005 m2->_opnds[2] = op_src;
6006 m3->_opnds[0] = op_dst;
6007 m3->_opnds[1] = op_dst;
6008 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6009 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6010 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6011 nodes->push(m1);
6012 nodes->push(m2);
6013 nodes->push(m3);
6014 %}
6015 %}
6016
6017 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6018 effect(DEF dst, USE src);
6019 ins_cost(DEFAULT_COST);
6020
6021 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6022 size(4);
6023 ins_encode %{
6024 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6025 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6026 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6027 %}
6028 ins_pipe(pipe_class_default);
6029 %}
6030
6031 // This needs a match rule so that build_oop_map knows this is
6032 // not a narrow oop.
6033 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6034 match(Set dst src1);
6035 effect(TEMP src2);
6036 ins_cost(DEFAULT_COST);
6037
6038 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6039 size(4);
6040 ins_encode %{
6041 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6042 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6043 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6044 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6045 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6046
6047 __ relocate(rspec, 1);
6048 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6049 %}
6050 ins_pipe(pipe_class_default);
6051 %}
6052
6053 // Loading ConNKlass must be postalloc expanded so that edges between
6054 // the nodes are safe. They may not interfere with a safepoint.
6055 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6056 match(Set dst src);
6057 ins_cost(DEFAULT_COST*2);
6058
6059 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6060 postalloc_expand %{
6061 // Load high bits into register. Sign extended.
6062 MachNode *m1 = new (C) loadConNKlass_hiNode();
6063 m1->add_req(NULL);
6064 m1->_opnds[0] = op_dst;
6065 m1->_opnds[1] = op_src;
6066 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6067 nodes->push(m1);
6068
6069 MachNode *m2 = m1;
6070 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6071 // Value might be 1-extended. Mask out these bits.
6072 m2 = new (C) clearMs32bNode();
6073 m2->add_req(NULL, m1);
6074 m2->_opnds[0] = op_dst;
6075 m2->_opnds[1] = op_dst;
6076 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6077 nodes->push(m2);
6078 }
6079
6080 MachNode *m3 = new (C) loadConNKlass_loNode();
6081 m3->add_req(NULL, m2);
6082 m3->_opnds[0] = op_dst;
6083 m3->_opnds[1] = op_src;
6084 m3->_opnds[2] = op_dst;
6085 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6086 nodes->push(m3);
6087 %}
6088 %}
6089
6090 // 0x1 is used in object initialization (initial object header).
6091 // No constant pool entries required.
6092 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6093 match(Set dst src);
6094
6095 format %{ "LI $dst, $src \t// ptr" %}
6096 size(4);
6097 ins_encode %{
6098 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6099 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6100 %}
6101 ins_pipe(pipe_class_default);
6102 %}
6103
6104 // Expand node for constant pool load: small offset.
6105 // The match rule is needed to generate the correct bottom_type(),
6106 // however this node should never match. The use of predicate is not
6107 // possible since ADLC forbids predicates for chain rules. The higher
6108 // costs do not prevent matching in this case. For that reason the
6109 // operand immP_NM with predicate(false) is used.
6110 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6111 match(Set dst src);
6112 effect(TEMP toc);
6113
6114 ins_num_consts(1);
6115
6116 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6117 size(4);
6118 ins_encode( enc_load_long_constP(dst, src, toc) );
6119 ins_pipe(pipe_class_memory);
6120 %}
6121
6122 // Expand node for constant pool load: large offset.
6123 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6124 effect(DEF dst, USE src, USE toc);
6125 predicate(false);
6126
6127 ins_num_consts(1);
6128 ins_field_const_toc_offset(int);
6129
6130 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6131 size(4);
6132 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6133 ins_pipe(pipe_class_default);
6134 %}
6135
6136 // Expand node for constant pool load: large offset.
6137 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6138 match(Set dst src);
6139 effect(TEMP base);
6140
6141 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6142
6143 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6144 size(4);
6145 ins_encode %{
6146 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6147 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6148 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6149 %}
6150 ins_pipe(pipe_class_memory);
6151 %}
6152
6153 // Load pointer constant from constant table. Expand in case an
6154 // offset > 16 bit is needed.
6155 // Adlc adds toc node MachConstantTableBase.
6156 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6157 match(Set dst src);
6158 ins_cost(MEMORY_REF_COST);
6159
6160 // This rule does not use "expand" because then
6161 // the result type is not known to be an Oop. An ADLC
6162 // enhancement will be needed to make that work - not worth it!
6163
6164 // If this instruction rematerializes, it prolongs the live range
6165 // of the toc node, causing illegal graphs.
6166 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6167 ins_cannot_rematerialize(true);
6168
6169 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6170 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6171 %}
6172
6173 // Expand node for constant pool load: small offset.
6174 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6175 effect(DEF dst, USE src, USE toc);
6176 ins_cost(MEMORY_REF_COST);
6177
6178 ins_num_consts(1);
6179
6180 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6181 size(4);
6182 ins_encode %{
6183 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6184 address float_address = __ float_constant($src$$constant);
6185 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6186 %}
6187 ins_pipe(pipe_class_memory);
6188 %}
6189
6190 // Expand node for constant pool load: large offset.
6191 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6192 effect(DEF dst, USE src, USE toc);
6193 ins_cost(MEMORY_REF_COST);
6194
6195 ins_num_consts(1);
6196
6197 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6198 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6199 "ADDIS $toc, $toc, -offset_hi"%}
6200 size(12);
6201 ins_encode %{
6202 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6203 FloatRegister Rdst = $dst$$FloatRegister;
6204 Register Rtoc = $toc$$Register;
6205 address float_address = __ float_constant($src$$constant);
6206 int offset = __ offset_to_method_toc(float_address);
6207 int hi = (offset + (1<<15))>>16;
6208 int lo = offset - hi * (1<<16);
6209
6210 __ addis(Rtoc, Rtoc, hi);
6211 __ lfs(Rdst, lo, Rtoc);
6212 __ addis(Rtoc, Rtoc, -hi);
6213 %}
6214 ins_pipe(pipe_class_memory);
6215 %}
6216
6217 // Adlc adds toc node MachConstantTableBase.
6218 instruct loadConF_Ex(regF dst, immF src) %{
6219 match(Set dst src);
6220 ins_cost(MEMORY_REF_COST);
6221
6222 // See loadConP.
6223 ins_cannot_rematerialize(true);
6224
6225 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6226 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6227 %}
6228
6229 // Expand node for constant pool load: small offset.
6230 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6231 effect(DEF dst, USE src, USE toc);
6232 ins_cost(MEMORY_REF_COST);
6233
6234 ins_num_consts(1);
6235
6236 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6237 size(4);
6238 ins_encode %{
6239 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6240 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6241 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6242 %}
6243 ins_pipe(pipe_class_memory);
6244 %}
6245
6246 // Expand node for constant pool load: large offset.
6247 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6248 effect(DEF dst, USE src, USE toc);
6249 ins_cost(MEMORY_REF_COST);
6250
6251 ins_num_consts(1);
6252
6253 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6254 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6255 "ADDIS $toc, $toc, -offset_hi" %}
6256 size(12);
6257 ins_encode %{
6258 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6259 FloatRegister Rdst = $dst$$FloatRegister;
6260 Register Rtoc = $toc$$Register;
6261 address float_address = __ double_constant($src$$constant);
6262 int offset = __ offset_to_method_toc(float_address);
6263 int hi = (offset + (1<<15))>>16;
6264 int lo = offset - hi * (1<<16);
6265
6266 __ addis(Rtoc, Rtoc, hi);
6267 __ lfd(Rdst, lo, Rtoc);
6268 __ addis(Rtoc, Rtoc, -hi);
6269 %}
6270 ins_pipe(pipe_class_memory);
6271 %}
6272
6273 // Adlc adds toc node MachConstantTableBase.
6274 instruct loadConD_Ex(regD dst, immD src) %{
6275 match(Set dst src);
6276 ins_cost(MEMORY_REF_COST);
6277
6278 // See loadConP.
6279 ins_cannot_rematerialize(true);
6280
6281 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6282 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6283 %}
6284
6285 // Prefetch instructions.
6286 // Must be safe to execute with invalid address (cannot fault).
6287
6288 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6289 match(PrefetchRead (AddP mem src));
6290 ins_cost(MEMORY_REF_COST);
6291
6292 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6293 size(4);
6294 ins_encode %{
6295 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6296 __ dcbt($src$$Register, $mem$$base$$Register);
6297 %}
6298 ins_pipe(pipe_class_memory);
6299 %}
6300
6301 instruct prefetchr_no_offset(indirectMemory mem) %{
6302 match(PrefetchRead mem);
6303 ins_cost(MEMORY_REF_COST);
6304
6305 format %{ "PREFETCH $mem" %}
6306 size(4);
6307 ins_encode %{
6308 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6309 __ dcbt($mem$$base$$Register);
6310 %}
6311 ins_pipe(pipe_class_memory);
6312 %}
6313
6314 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6315 match(PrefetchWrite (AddP mem src));
6316 ins_cost(MEMORY_REF_COST);
6317
6318 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6319 size(4);
6320 ins_encode %{
6321 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6322 __ dcbtst($src$$Register, $mem$$base$$Register);
6323 %}
6324 ins_pipe(pipe_class_memory);
6325 %}
6326
6327 instruct prefetchw_no_offset(indirectMemory mem) %{
6328 match(PrefetchWrite mem);
6329 ins_cost(MEMORY_REF_COST);
6330
6331 format %{ "PREFETCH $mem" %}
6332 size(4);
6333 ins_encode %{
6334 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6335 __ dcbtst($mem$$base$$Register);
6336 %}
6337 ins_pipe(pipe_class_memory);
6338 %}
6339
6340 // Special prefetch versions which use the dcbz instruction.
6341 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6342 match(PrefetchAllocation (AddP mem src));
6343 predicate(AllocatePrefetchStyle == 3);
6344 ins_cost(MEMORY_REF_COST);
6345
6346 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6347 size(4);
6348 ins_encode %{
6349 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6350 __ dcbz($src$$Register, $mem$$base$$Register);
6351 %}
6352 ins_pipe(pipe_class_memory);
6353 %}
6354
6355 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6356 match(PrefetchAllocation mem);
6357 predicate(AllocatePrefetchStyle == 3);
6358 ins_cost(MEMORY_REF_COST);
6359
6360 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6361 size(4);
6362 ins_encode %{
6363 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6364 __ dcbz($mem$$base$$Register);
6365 %}
6366 ins_pipe(pipe_class_memory);
6367 %}
6368
6369 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6370 match(PrefetchAllocation (AddP mem src));
6371 predicate(AllocatePrefetchStyle != 3);
6372 ins_cost(MEMORY_REF_COST);
6373
6374 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6375 size(4);
6376 ins_encode %{
6377 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6378 __ dcbtst($src$$Register, $mem$$base$$Register);
6379 %}
6380 ins_pipe(pipe_class_memory);
6381 %}
6382
6383 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6384 match(PrefetchAllocation mem);
6385 predicate(AllocatePrefetchStyle != 3);
6386 ins_cost(MEMORY_REF_COST);
6387
6388 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6389 size(4);
6390 ins_encode %{
6391 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6392 __ dcbtst($mem$$base$$Register);
6393 %}
6394 ins_pipe(pipe_class_memory);
6395 %}
6396
6397 //----------Store Instructions-------------------------------------------------
6398
6399 // Store Byte
6400 instruct storeB(memory mem, iRegIsrc src) %{
6401 match(Set mem (StoreB mem src));
6402 ins_cost(MEMORY_REF_COST);
6403
6404 format %{ "STB $src, $mem \t// byte" %}
6405 size(4);
6406 ins_encode %{
6407 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6408 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6409 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6410 %}
6411 ins_pipe(pipe_class_memory);
6412 %}
6413
6414 // Store Char/Short
6415 instruct storeC(memory mem, iRegIsrc src) %{
6416 match(Set mem (StoreC mem src));
6417 ins_cost(MEMORY_REF_COST);
6418
6419 format %{ "STH $src, $mem \t// short" %}
6420 size(4);
6421 ins_encode %{
6422 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6423 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6424 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6425 %}
6426 ins_pipe(pipe_class_memory);
6427 %}
6428
6429 // Store Integer
6430 instruct storeI(memory mem, iRegIsrc src) %{
6431 match(Set mem (StoreI mem src));
6432 ins_cost(MEMORY_REF_COST);
6433
6434 format %{ "STW $src, $mem" %}
6435 size(4);
6436 ins_encode( enc_stw(src, mem) );
6437 ins_pipe(pipe_class_memory);
6438 %}
6439
6440 // ConvL2I + StoreI.
6441 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6442 match(Set mem (StoreI mem (ConvL2I src)));
6443 ins_cost(MEMORY_REF_COST);
6444
6445 format %{ "STW l2i($src), $mem" %}
6446 size(4);
6447 ins_encode( enc_stw(src, mem) );
6448 ins_pipe(pipe_class_memory);
6449 %}
6450
6451 // Store Long
6452 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6453 match(Set mem (StoreL mem src));
6454 ins_cost(MEMORY_REF_COST);
6455
6456 format %{ "STD $src, $mem \t// long" %}
6457 size(4);
6458 ins_encode( enc_std(src, mem) );
6459 ins_pipe(pipe_class_memory);
6460 %}
6461
6462 // Store super word nodes.
6463
6464 // Store Aligned Packed Byte long register to memory
6465 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6466 predicate(n->as_StoreVector()->memory_size() == 8);
6467 match(Set mem (StoreVector mem src));
6468 ins_cost(MEMORY_REF_COST);
6469
6470 format %{ "STD $mem, $src \t// packed8B" %}
6471 size(4);
6472 ins_encode( enc_std(src, mem) );
6473 ins_pipe(pipe_class_memory);
6474 %}
6475
6476 // Store Compressed Oop
6477 instruct storeN(memory dst, iRegN_P2N src) %{
6478 match(Set dst (StoreN dst src));
6479 ins_cost(MEMORY_REF_COST);
6480
6481 format %{ "STW $src, $dst \t// compressed oop" %}
6482 size(4);
6483 ins_encode( enc_stw(src, dst) );
6484 ins_pipe(pipe_class_memory);
6485 %}
6486
6487 // Store Compressed KLass
6488 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6489 match(Set dst (StoreNKlass dst src));
6490 ins_cost(MEMORY_REF_COST);
6491
6492 format %{ "STW $src, $dst \t// compressed klass" %}
6493 size(4);
6494 ins_encode( enc_stw(src, dst) );
6495 ins_pipe(pipe_class_memory);
6496 %}
6497
6498 // Store Pointer
6499 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6500 match(Set dst (StoreP dst src));
6501 ins_cost(MEMORY_REF_COST);
6502
6503 format %{ "STD $src, $dst \t// ptr" %}
6504 size(4);
6505 ins_encode( enc_std(src, dst) );
6506 ins_pipe(pipe_class_memory);
6507 %}
6508
6509 // Store Float
6510 instruct storeF(memory mem, regF src) %{
6511 match(Set mem (StoreF mem src));
6512 ins_cost(MEMORY_REF_COST);
6513
6514 format %{ "STFS $src, $mem" %}
6515 size(4);
6516 ins_encode( enc_stfs(src, mem) );
6517 ins_pipe(pipe_class_memory);
6518 %}
6519
6520 // Store Double
6521 instruct storeD(memory mem, regD src) %{
6522 match(Set mem (StoreD mem src));
6523 ins_cost(MEMORY_REF_COST);
6524
6525 format %{ "STFD $src, $mem" %}
6526 size(4);
6527 ins_encode( enc_stfd(src, mem) );
6528 ins_pipe(pipe_class_memory);
6529 %}
6530
6531 //----------Store Instructions With Zeros--------------------------------------
6532
6533 // Card-mark for CMS garbage collection.
6534 // This cardmark does an optimization so that it must not always
6535 // do a releasing store. For this, it gets the address of
6536 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6537 // (Using releaseFieldAddr in the match rule is a hack.)
6538 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6539 match(Set mem (StoreCM mem releaseFieldAddr));
6540 predicate(false);
6541 ins_cost(MEMORY_REF_COST);
6542
6543 // See loadConP.
6544 ins_cannot_rematerialize(true);
6545
6546 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6547 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6548 ins_pipe(pipe_class_memory);
6549 %}
6550
6551 // Card-mark for CMS garbage collection.
6552 // This cardmark does an optimization so that it must not always
6553 // do a releasing store. For this, it needs the constant address of
6554 // CMSCollectorCardTableModRefBSExt::_requires_release.
6555 // This constant address is split off here by expand so we can use
6556 // adlc / matcher functionality to load it from the constant section.
6557 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6558 match(Set mem (StoreCM mem zero));
6559 predicate(UseConcMarkSweepGC);
6560
6561 expand %{
6562 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6563 iRegLdst releaseFieldAddress;
6564 loadConL_Ex(releaseFieldAddress, baseImm);
6565 storeCM_CMS(mem, releaseFieldAddress);
6566 %}
6567 %}
6568
6569 instruct storeCM_G1(memory mem, immI_0 zero) %{
6570 match(Set mem (StoreCM mem zero));
6571 predicate(UseG1GC);
6572 ins_cost(MEMORY_REF_COST);
6573
6574 ins_cannot_rematerialize(true);
6575
6576 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6577 size(8);
6578 ins_encode %{
6579 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6580 __ li(R0, 0);
6581 //__ release(); // G1: oops are allowed to get visible after dirty marking
6582 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6583 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6584 %}
6585 ins_pipe(pipe_class_memory);
6586 %}
6587
6588 // Convert oop pointer into compressed form.
6589
6590 // Nodes for postalloc expand.
6591
6592 // Shift node for expand.
6593 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6594 // The match rule is needed to make it a 'MachTypeNode'!
6595 match(Set dst (EncodeP src));
6596 predicate(false);
6597
6598 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6599 size(4);
6600 ins_encode %{
6601 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6602 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6603 %}
6604 ins_pipe(pipe_class_default);
6605 %}
6606
6607 // Add node for expand.
6608 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6609 // The match rule is needed to make it a 'MachTypeNode'!
6610 match(Set dst (EncodeP src));
6611 predicate(false);
6612
6613 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6614 size(4);
6615 ins_encode %{
6616 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6617 __ subf($dst$$Register, R30, $src$$Register);
6618 %}
6619 ins_pipe(pipe_class_default);
6620 %}
6621
6622 // Conditional sub base.
6623 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6624 // The match rule is needed to make it a 'MachTypeNode'!
6625 match(Set dst (EncodeP (Binary crx src1)));
6626 predicate(false);
6627
6628 ins_variable_size_depending_on_alignment(true);
6629
6630 format %{ "BEQ $crx, done\n\t"
6631 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6632 "done:" %}
6633 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6634 ins_encode %{
6635 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6636 Label done;
6637 __ beq($crx$$CondRegister, done);
6638 __ subf($dst$$Register, R30, $src1$$Register);
6639 // TODO PPC port __ endgroup_if_needed(_size == 12);
6640 __ bind(done);
6641 %}
6642 ins_pipe(pipe_class_default);
6643 %}
6644
6645 // Power 7 can use isel instruction
6646 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6647 // The match rule is needed to make it a 'MachTypeNode'!
6648 match(Set dst (EncodeP (Binary crx src1)));
6649 predicate(false);
6650
6651 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6652 size(4);
6653 ins_encode %{
6654 // This is a Power7 instruction for which no machine description exists.
6655 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6656 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6657 %}
6658 ins_pipe(pipe_class_default);
6659 %}
6660
6661 // base != 0
6662 // 32G aligned narrow oop base.
6663 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6664 match(Set dst (EncodeP src));
6665 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6666
6667 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6668 size(4);
6669 ins_encode %{
6670 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6671 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6672 %}
6673 ins_pipe(pipe_class_default);
6674 %}
6675
6676 // shift != 0, base != 0
6677 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6678 match(Set dst (EncodeP src));
6679 effect(TEMP crx);
6680 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6681 Universe::narrow_oop_shift() != 0 &&
6682 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6683
6684 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6685 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6686 %}
6687
6688 // shift != 0, base != 0
6689 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6690 match(Set dst (EncodeP src));
6691 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6692 Universe::narrow_oop_shift() != 0 &&
6693 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6694
6695 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6696 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6697 %}
6698
6699 // shift != 0, base == 0
6700 // TODO: This is the same as encodeP_shift. Merge!
6701 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6702 match(Set dst (EncodeP src));
6703 predicate(Universe::narrow_oop_shift() != 0 &&
6704 Universe::narrow_oop_base() ==0);
6705
6706 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6707 size(4);
6708 ins_encode %{
6709 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6710 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6711 %}
6712 ins_pipe(pipe_class_default);
6713 %}
6714
6715 // Compressed OOPs with narrow_oop_shift == 0.
6716 // shift == 0, base == 0
6717 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6718 match(Set dst (EncodeP src));
6719 predicate(Universe::narrow_oop_shift() == 0);
6720
6721 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6722 // variable size, 0 or 4.
6723 ins_encode %{
6724 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6725 __ mr_if_needed($dst$$Register, $src$$Register);
6726 %}
6727 ins_pipe(pipe_class_default);
6728 %}
6729
6730 // Decode nodes.
6731
6732 // Shift node for expand.
6733 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6734 // The match rule is needed to make it a 'MachTypeNode'!
6735 match(Set dst (DecodeN src));
6736 predicate(false);
6737
6738 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6739 size(4);
6740 ins_encode %{
6741 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6742 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6743 %}
6744 ins_pipe(pipe_class_default);
6745 %}
6746
6747 // Add node for expand.
6748 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6749 // The match rule is needed to make it a 'MachTypeNode'!
6750 match(Set dst (DecodeN src));
6751 predicate(false);
6752
6753 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6754 size(4);
6755 ins_encode %{
6756 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6757 __ add($dst$$Register, $src$$Register, R30);
6758 %}
6759 ins_pipe(pipe_class_default);
6760 %}
6761
6762 // conditianal add base for expand
6763 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6764 // The match rule is needed to make it a 'MachTypeNode'!
6765 // NOTICE that the rule is nonsense - we just have to make sure that:
6766 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6767 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6768 match(Set dst (DecodeN (Binary crx src1)));
6769 predicate(false);
6770
6771 ins_variable_size_depending_on_alignment(true);
6772
6773 format %{ "BEQ $crx, done\n\t"
6774 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6775 "done:" %}
6776 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6777 ins_encode %{
6778 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6779 Label done;
6780 __ beq($crx$$CondRegister, done);
6781 __ add($dst$$Register, $src1$$Register, R30);
6782 // TODO PPC port __ endgroup_if_needed(_size == 12);
6783 __ bind(done);
6784 %}
6785 ins_pipe(pipe_class_default);
6786 %}
6787
6788 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6789 // The match rule is needed to make it a 'MachTypeNode'!
6790 // NOTICE that the rule is nonsense - we just have to make sure that:
6791 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6792 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6793 match(Set dst (DecodeN (Binary crx src1)));
6794 predicate(false);
6795
6796 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6797 size(4);
6798 ins_encode %{
6799 // This is a Power7 instruction for which no machine description exists.
6800 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6801 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6802 %}
6803 ins_pipe(pipe_class_default);
6804 %}
6805
6806 // shift != 0, base != 0
6807 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6808 match(Set dst (DecodeN src));
6809 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6810 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6811 Universe::narrow_oop_shift() != 0 &&
6812 Universe::narrow_oop_base() != 0);
6813 effect(TEMP crx);
6814
6815 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6816 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6817 %}
6818
6819 // shift != 0, base == 0
6820 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6821 match(Set dst (DecodeN src));
6822 predicate(Universe::narrow_oop_shift() != 0 &&
6823 Universe::narrow_oop_base() == 0);
6824
6825 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6826 size(4);
6827 ins_encode %{
6828 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6829 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6830 %}
6831 ins_pipe(pipe_class_default);
6832 %}
6833
6834 // src != 0, shift != 0, base != 0
6835 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6836 match(Set dst (DecodeN src));
6837 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6838 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6839 Universe::narrow_oop_shift() != 0 &&
6840 Universe::narrow_oop_base() != 0);
6841
6842 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6843 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6844 %}
6845
6846 // Compressed OOPs with narrow_oop_shift == 0.
6847 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6848 match(Set dst (DecodeN src));
6849 predicate(Universe::narrow_oop_shift() == 0);
6850 ins_cost(DEFAULT_COST);
6851
6852 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6853 // variable size, 0 or 4.
6854 ins_encode %{
6855 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6856 __ mr_if_needed($dst$$Register, $src$$Register);
6857 %}
6858 ins_pipe(pipe_class_default);
6859 %}
6860
6861 // Convert compressed oop into int for vectors alignment masking.
6862 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6863 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6864 predicate(Universe::narrow_oop_shift() == 0);
6865 ins_cost(DEFAULT_COST);
6866
6867 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6868 // variable size, 0 or 4.
6869 ins_encode %{
6870 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6871 __ mr_if_needed($dst$$Register, $src$$Register);
6872 %}
6873 ins_pipe(pipe_class_default);
6874 %}
6875
6876 // Convert klass pointer into compressed form.
6877
6878 // Nodes for postalloc expand.
6879
6880 // Shift node for expand.
6881 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6882 // The match rule is needed to make it a 'MachTypeNode'!
6883 match(Set dst (EncodePKlass src));
6884 predicate(false);
6885
6886 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6887 size(4);
6888 ins_encode %{
6889 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6890 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6891 %}
6892 ins_pipe(pipe_class_default);
6893 %}
6894
6895 // Add node for expand.
6896 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6897 // The match rule is needed to make it a 'MachTypeNode'!
6898 match(Set dst (EncodePKlass (Binary base src)));
6899 predicate(false);
6900
6901 format %{ "SUB $dst, $base, $src \t// encode" %}
6902 size(4);
6903 ins_encode %{
6904 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6905 __ subf($dst$$Register, $base$$Register, $src$$Register);
6906 %}
6907 ins_pipe(pipe_class_default);
6908 %}
6909
6910 // base != 0
6911 // 32G aligned narrow oop base.
6912 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6913 match(Set dst (EncodePKlass src));
6914 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6915
6916 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6917 size(4);
6918 ins_encode %{
6919 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6920 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6921 %}
6922 ins_pipe(pipe_class_default);
6923 %}
6924
6925 // shift != 0, base != 0
6926 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6927 match(Set dst (EncodePKlass (Binary base src)));
6928 predicate(false);
6929
6930 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6931 postalloc_expand %{
6932 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
6933 n1->add_req(n_region, n_base, n_src);
6934 n1->_opnds[0] = op_dst;
6935 n1->_opnds[1] = op_base;
6936 n1->_opnds[2] = op_src;
6937 n1->_bottom_type = _bottom_type;
6938
6939 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
6940 n2->add_req(n_region, n1);
6941 n2->_opnds[0] = op_dst;
6942 n2->_opnds[1] = op_dst;
6943 n2->_bottom_type = _bottom_type;
6944 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6945 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6946
6947 nodes->push(n1);
6948 nodes->push(n2);
6949 %}
6950 %}
6951
6952 // shift != 0, base != 0
6953 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
6954 match(Set dst (EncodePKlass src));
6955 //predicate(Universe::narrow_klass_shift() != 0 &&
6956 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
6957
6958 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6959 ins_cost(DEFAULT_COST*2); // Don't count constant.
6960 expand %{
6961 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
6962 iRegLdst base;
6963 loadConL_Ex(base, baseImm);
6964 encodePKlass_not_null_Ex(dst, base, src);
6965 %}
6966 %}
6967
6968 // Decode nodes.
6969
6970 // Shift node for expand.
6971 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
6972 // The match rule is needed to make it a 'MachTypeNode'!
6973 match(Set dst (DecodeNKlass src));
6974 predicate(false);
6975
6976 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
6977 size(4);
6978 ins_encode %{
6979 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6980 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6981 %}
6982 ins_pipe(pipe_class_default);
6983 %}
6984
6985 // Add node for expand.
6986
6987 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6988 // The match rule is needed to make it a 'MachTypeNode'!
6989 match(Set dst (DecodeNKlass (Binary base src)));
6990 predicate(false);
6991
6992 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
6993 size(4);
6994 ins_encode %{
6995 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6996 __ add($dst$$Register, $base$$Register, $src$$Register);
6997 %}
6998 ins_pipe(pipe_class_default);
6999 %}
7000
7001 // src != 0, shift != 0, base != 0
7002 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7003 match(Set dst (DecodeNKlass (Binary base src)));
7004 //effect(kill src); // We need a register for the immediate result after shifting.
7005 predicate(false);
7006
7007 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7008 postalloc_expand %{
7009 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7010 n1->add_req(n_region, n_base, n_src);
7011 n1->_opnds[0] = op_dst;
7012 n1->_opnds[1] = op_base;
7013 n1->_opnds[2] = op_src;
7014 n1->_bottom_type = _bottom_type;
7015
7016 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7017 n2->add_req(n_region, n2);
7018 n2->_opnds[0] = op_dst;
7019 n2->_opnds[1] = op_dst;
7020 n2->_bottom_type = _bottom_type;
7021
7022 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7023 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7024
7025 nodes->push(n1);
7026 nodes->push(n2);
7027 %}
7028 %}
7029
7030 // src != 0, shift != 0, base != 0
7031 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7032 match(Set dst (DecodeNKlass src));
7033 // predicate(Universe::narrow_klass_shift() != 0 &&
7034 // Universe::narrow_klass_base() != 0);
7035
7036 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7037
7038 ins_cost(DEFAULT_COST*2); // Don't count constant.
7039 expand %{
7040 // We add first, then we shift. Like this, we can get along with one register less.
7041 // But we have to load the base pre-shifted.
7042 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7043 iRegLdst base;
7044 loadConL_Ex(base, baseImm);
7045 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7046 %}
7047 %}
7048
7049 //----------MemBar Instructions-----------------------------------------------
7050 // Memory barrier flavors
7051
7052 instruct membar_acquire() %{
7053 match(LoadFence);
7054 ins_cost(4*MEMORY_REF_COST);
7055
7056 format %{ "MEMBAR-acquire" %}
7057 size(4);
7058 ins_encode %{
7059 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7060 __ acquire();
7061 %}
7062 ins_pipe(pipe_class_default);
7063 %}
7064
7065 instruct unnecessary_membar_acquire() %{
7066 match(MemBarAcquire);
7067 ins_cost(0);
7068
7069 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7070 size(0);
7071 ins_encode( /*empty*/ );
7072 ins_pipe(pipe_class_default);
7073 %}
7074
7075 instruct membar_acquire_lock() %{
7076 match(MemBarAcquireLock);
7077 ins_cost(0);
7078
7079 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7080 size(0);
7081 ins_encode( /*empty*/ );
7082 ins_pipe(pipe_class_default);
7083 %}
7084
7085 instruct membar_release() %{
7086 match(MemBarRelease);
7087 match(StoreFence);
7088 ins_cost(4*MEMORY_REF_COST);
7089
7090 format %{ "MEMBAR-release" %}
7091 size(4);
7092 ins_encode %{
7093 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7094 __ release();
7095 %}
7096 ins_pipe(pipe_class_default);
7097 %}
7098
7099 instruct membar_storestore() %{
7100 match(MemBarStoreStore);
7101 ins_cost(4*MEMORY_REF_COST);
7102
7103 format %{ "MEMBAR-store-store" %}
7104 size(4);
7105 ins_encode %{
7106 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7107 __ membar(Assembler::StoreStore);
7108 %}
7109 ins_pipe(pipe_class_default);
7110 %}
7111
7112 instruct membar_release_lock() %{
7113 match(MemBarReleaseLock);
7114 ins_cost(0);
7115
7116 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7117 size(0);
7118 ins_encode( /*empty*/ );
7119 ins_pipe(pipe_class_default);
7120 %}
7121
7122 instruct membar_volatile() %{
7123 match(MemBarVolatile);
7124 ins_cost(4*MEMORY_REF_COST);
7125
7126 format %{ "MEMBAR-volatile" %}
7127 size(4);
7128 ins_encode %{
7129 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7130 __ fence();
7131 %}
7132 ins_pipe(pipe_class_default);
7133 %}
7134
7135 // This optimization is wrong on PPC. The following pattern is not supported:
7136 // MemBarVolatile
7137 // ^ ^
7138 // | |
7139 // CtrlProj MemProj
7140 // ^ ^
7141 // | |
7142 // | Load
7143 // |
7144 // MemBarVolatile
7145 //
7146 // The first MemBarVolatile could get optimized out! According to
7147 // Vladimir, this pattern can not occur on Oracle platforms.
7148 // However, it does occur on PPC64 (because of membars in
7149 // inline_unsafe_load_store).
7150 //
7151 // Add this node again if we found a good solution for inline_unsafe_load_store().
7152 // Don't forget to look at the implementation of post_store_load_barrier again,
7153 // we did other fixes in that method.
7154 //instruct unnecessary_membar_volatile() %{
7155 // match(MemBarVolatile);
7156 // predicate(Matcher::post_store_load_barrier(n));
7157 // ins_cost(0);
7158 //
7159 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7160 // size(0);
7161 // ins_encode( /*empty*/ );
7162 // ins_pipe(pipe_class_default);
7163 //%}
7164
7165 instruct membar_CPUOrder() %{
7166 match(MemBarCPUOrder);
7167 ins_cost(0);
7168
7169 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7170 size(0);
7171 ins_encode( /*empty*/ );
7172 ins_pipe(pipe_class_default);
7173 %}
7174
7175 //----------Conditional Move---------------------------------------------------
7176
7177 // Cmove using isel.
7178 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7179 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7180 predicate(VM_Version::has_isel());
7181 ins_cost(DEFAULT_COST);
7182
7183 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7184 size(4);
7185 ins_encode %{
7186 // This is a Power7 instruction for which no machine description
7187 // exists. Anyways, the scheduler should be off on Power7.
7188 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7189 int cc = $cmp$$cmpcode;
7190 __ isel($dst$$Register, $crx$$CondRegister,
7191 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7192 %}
7193 ins_pipe(pipe_class_default);
7194 %}
7195
7196 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7197 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7198 predicate(!VM_Version::has_isel());
7199 ins_cost(DEFAULT_COST+BRANCH_COST);
7200
7201 ins_variable_size_depending_on_alignment(true);
7202
7203 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7204 // Worst case is branch + move + stop, no stop without scheduler
7205 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7206 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7207 ins_pipe(pipe_class_default);
7208 %}
7209
7210 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7211 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7212 ins_cost(DEFAULT_COST+BRANCH_COST);
7213
7214 ins_variable_size_depending_on_alignment(true);
7215
7216 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7217 // Worst case is branch + move + stop, no stop without scheduler
7218 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7219 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7220 ins_pipe(pipe_class_default);
7221 %}
7222
7223 // Cmove using isel.
7224 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7225 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7226 predicate(VM_Version::has_isel());
7227 ins_cost(DEFAULT_COST);
7228
7229 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7230 size(4);
7231 ins_encode %{
7232 // This is a Power7 instruction for which no machine description
7233 // exists. Anyways, the scheduler should be off on Power7.
7234 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7235 int cc = $cmp$$cmpcode;
7236 __ isel($dst$$Register, $crx$$CondRegister,
7237 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7238 %}
7239 ins_pipe(pipe_class_default);
7240 %}
7241
7242 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7243 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7244 predicate(!VM_Version::has_isel());
7245 ins_cost(DEFAULT_COST+BRANCH_COST);
7246
7247 ins_variable_size_depending_on_alignment(true);
7248
7249 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7250 // Worst case is branch + move + stop, no stop without scheduler.
7251 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7252 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7253 ins_pipe(pipe_class_default);
7254 %}
7255
7256 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7257 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7258 ins_cost(DEFAULT_COST+BRANCH_COST);
7259
7260 ins_variable_size_depending_on_alignment(true);
7261
7262 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7263 // Worst case is branch + move + stop, no stop without scheduler.
7264 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7265 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7266 ins_pipe(pipe_class_default);
7267 %}
7268
7269 // Cmove using isel.
7270 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7271 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7272 predicate(VM_Version::has_isel());
7273 ins_cost(DEFAULT_COST);
7274
7275 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7276 size(4);
7277 ins_encode %{
7278 // This is a Power7 instruction for which no machine description
7279 // exists. Anyways, the scheduler should be off on Power7.
7280 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7281 int cc = $cmp$$cmpcode;
7282 __ isel($dst$$Register, $crx$$CondRegister,
7283 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7284 %}
7285 ins_pipe(pipe_class_default);
7286 %}
7287
7288 // Conditional move for RegN. Only cmov(reg, reg).
7289 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7290 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7291 predicate(!VM_Version::has_isel());
7292 ins_cost(DEFAULT_COST+BRANCH_COST);
7293
7294 ins_variable_size_depending_on_alignment(true);
7295
7296 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7297 // Worst case is branch + move + stop, no stop without scheduler.
7298 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7299 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7300 ins_pipe(pipe_class_default);
7301 %}
7302
7303 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7304 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7305 ins_cost(DEFAULT_COST+BRANCH_COST);
7306
7307 ins_variable_size_depending_on_alignment(true);
7308
7309 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7310 // Worst case is branch + move + stop, no stop without scheduler.
7311 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7312 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7313 ins_pipe(pipe_class_default);
7314 %}
7315
7316 // Cmove using isel.
7317 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7318 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7319 predicate(VM_Version::has_isel());
7320 ins_cost(DEFAULT_COST);
7321
7322 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7323 size(4);
7324 ins_encode %{
7325 // This is a Power7 instruction for which no machine description
7326 // exists. Anyways, the scheduler should be off on Power7.
7327 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7328 int cc = $cmp$$cmpcode;
7329 __ isel($dst$$Register, $crx$$CondRegister,
7330 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7331 %}
7332 ins_pipe(pipe_class_default);
7333 %}
7334
7335 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7336 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7337 predicate(!VM_Version::has_isel());
7338 ins_cost(DEFAULT_COST+BRANCH_COST);
7339
7340 ins_variable_size_depending_on_alignment(true);
7341
7342 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7343 // Worst case is branch + move + stop, no stop without scheduler.
7344 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7345 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7346 ins_pipe(pipe_class_default);
7347 %}
7348
7349 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7350 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7351 ins_cost(DEFAULT_COST+BRANCH_COST);
7352
7353 ins_variable_size_depending_on_alignment(true);
7354
7355 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7356 // Worst case is branch + move + stop, no stop without scheduler.
7357 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7358 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7359 ins_pipe(pipe_class_default);
7360 %}
7361
7362 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7363 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7364 ins_cost(DEFAULT_COST+BRANCH_COST);
7365
7366 ins_variable_size_depending_on_alignment(true);
7367
7368 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7369 // Worst case is branch + move + stop, no stop without scheduler.
7370 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7371 ins_encode %{
7372 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7373 Label done;
7374 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7375 // Branch if not (cmp crx).
7376 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7377 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7378 // TODO PPC port __ endgroup_if_needed(_size == 12);
7379 __ bind(done);
7380 %}
7381 ins_pipe(pipe_class_default);
7382 %}
7383
7384 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7385 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7386 ins_cost(DEFAULT_COST+BRANCH_COST);
7387
7388 ins_variable_size_depending_on_alignment(true);
7389
7390 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7391 // Worst case is branch + move + stop, no stop without scheduler.
7392 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7393 ins_encode %{
7394 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7395 Label done;
7396 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7397 // Branch if not (cmp crx).
7398 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7399 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7400 // TODO PPC port __ endgroup_if_needed(_size == 12);
7401 __ bind(done);
7402 %}
7403 ins_pipe(pipe_class_default);
7404 %}
7405
7406 //----------Conditional_store--------------------------------------------------
7407 // Conditional-store of the updated heap-top.
7408 // Used during allocation of the shared heap.
7409 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7410
7411 // As compareAndSwapL, but return flag register instead of boolean value in
7412 // int register.
7413 // Used by sun/misc/AtomicLongCSImpl.java.
7414 // Mem_ptr must be a memory operand, else this node does not get
7415 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7416 // can be rematerialized which leads to errors.
7417 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7418 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7419 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7420 ins_encode %{
7421 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7422 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7423 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7424 noreg, NULL, true);
7425 %}
7426 ins_pipe(pipe_class_default);
7427 %}
7428
7429 // As compareAndSwapP, but return flag register instead of boolean value in
7430 // int register.
7431 // This instruction is matched if UseTLAB is off.
7432 // Mem_ptr must be a memory operand, else this node does not get
7433 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7434 // can be rematerialized which leads to errors.
7435 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7436 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7437 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7438 ins_encode %{
7439 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7440 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7441 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7442 noreg, NULL, true);
7443 %}
7444 ins_pipe(pipe_class_default);
7445 %}
7446
7447 // Implement LoadPLocked. Must be ordered against changes of the memory location
7448 // by storePConditional.
7449 // Don't know whether this is ever used.
7450 instruct loadPLocked(iRegPdst dst, memory mem) %{
7451 match(Set dst (LoadPLocked mem));
7452 ins_cost(MEMORY_REF_COST);
7453
7454 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7455 "TWI $dst\n\t"
7456 "ISYNC" %}
7457 size(12);
7458 ins_encode( enc_ld_ac(dst, mem) );
7459 ins_pipe(pipe_class_memory);
7460 %}
7461
7462 //----------Compare-And-Swap---------------------------------------------------
7463
7464 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7465 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7466 // matched.
7467
7468 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7469 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7470 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7471 // Variable size: instruction count smaller if regs are disjoint.
7472 ins_encode %{
7473 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7474 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7475 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7476 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7477 $res$$Register, true);
7478 %}
7479 ins_pipe(pipe_class_default);
7480 %}
7481
7482 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7483 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7484 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7485 // Variable size: instruction count smaller if regs are disjoint.
7486 ins_encode %{
7487 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7488 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7489 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7490 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7491 $res$$Register, true);
7492 %}
7493 ins_pipe(pipe_class_default);
7494 %}
7495
7496 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7497 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7498 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7499 // Variable size: instruction count smaller if regs are disjoint.
7500 ins_encode %{
7501 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7502 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7503 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7504 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7505 $res$$Register, NULL, true);
7506 %}
7507 ins_pipe(pipe_class_default);
7508 %}
7509
7510 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7511 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7512 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7513 // Variable size: instruction count smaller if regs are disjoint.
7514 ins_encode %{
7515 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7516 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7517 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7518 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7519 $res$$Register, NULL, true);
7520 %}
7521 ins_pipe(pipe_class_default);
7522 %}
7523
7524 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7525 match(Set res (GetAndAddI mem_ptr src));
7526 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7527 // Variable size: instruction count smaller if regs are disjoint.
7528 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7529 ins_pipe(pipe_class_default);
7530 %}
7531
7532 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7533 match(Set res (GetAndAddL mem_ptr src));
7534 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7535 // Variable size: instruction count smaller if regs are disjoint.
7536 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7537 ins_pipe(pipe_class_default);
7538 %}
7539
7540 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7541 match(Set res (GetAndSetI mem_ptr src));
7542 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7543 // Variable size: instruction count smaller if regs are disjoint.
7544 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7545 ins_pipe(pipe_class_default);
7546 %}
7547
7548 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7549 match(Set res (GetAndSetL mem_ptr src));
7550 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7551 // Variable size: instruction count smaller if regs are disjoint.
7552 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7553 ins_pipe(pipe_class_default);
7554 %}
7555
7556 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7557 match(Set res (GetAndSetP mem_ptr src));
7558 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7559 // Variable size: instruction count smaller if regs are disjoint.
7560 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7561 ins_pipe(pipe_class_default);
7562 %}
7563
7564 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7565 match(Set res (GetAndSetN mem_ptr src));
7566 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7567 // Variable size: instruction count smaller if regs are disjoint.
7568 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7569 ins_pipe(pipe_class_default);
7570 %}
7571
7572 //----------Arithmetic Instructions--------------------------------------------
7573 // Addition Instructions
7574
7575 // PPC has no instruction setting overflow of 32-bit integer.
7576 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{
7577 // match(AddExactI dst src);
7578 // effect(DEF cr);
7579 //
7580 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %}
7581 // ins_encode( enc_add(dst, dst, src) );
7582 // ins_pipe(pipe_class_default);
7583 //%}
7584
7585 // Register Addition
7586 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7587 match(Set dst (AddI src1 src2));
7588 format %{ "ADD $dst, $src1, $src2" %}
7589 size(4);
7590 ins_encode %{
7591 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7592 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7593 %}
7594 ins_pipe(pipe_class_default);
7595 %}
7596
7597 // Expand does not work with above instruct. (??)
7598 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7599 // no match-rule
7600 effect(DEF dst, USE src1, USE src2);
7601 format %{ "ADD $dst, $src1, $src2" %}
7602 size(4);
7603 ins_encode %{
7604 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7605 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7606 %}
7607 ins_pipe(pipe_class_default);
7608 %}
7609
7610 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7611 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7612 ins_cost(DEFAULT_COST*3);
7613
7614 expand %{
7615 // FIXME: we should do this in the ideal world.
7616 iRegIdst tmp1;
7617 iRegIdst tmp2;
7618 addI_reg_reg(tmp1, src1, src2);
7619 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7620 addI_reg_reg(dst, tmp1, tmp2);
7621 %}
7622 %}
7623
7624 // Immediate Addition
7625 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7626 match(Set dst (AddI src1 src2));
7627 format %{ "ADDI $dst, $src1, $src2" %}
7628 size(4);
7629 ins_encode %{
7630 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7631 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7632 %}
7633 ins_pipe(pipe_class_default);
7634 %}
7635
7636 // Immediate Addition with 16-bit shifted operand
7637 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7638 match(Set dst (AddI src1 src2));
7639 format %{ "ADDIS $dst, $src1, $src2" %}
7640 size(4);
7641 ins_encode %{
7642 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7643 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7644 %}
7645 ins_pipe(pipe_class_default);
7646 %}
7647
7648 // Long Addition
7649 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7650 match(Set dst (AddL src1 src2));
7651 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7652 size(4);
7653 ins_encode %{
7654 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7655 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7656 %}
7657 ins_pipe(pipe_class_default);
7658 %}
7659
7660 // Expand does not work with above instruct. (??)
7661 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7662 // no match-rule
7663 effect(DEF dst, USE src1, USE src2);
7664 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7665 size(4);
7666 ins_encode %{
7667 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7668 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7669 %}
7670 ins_pipe(pipe_class_default);
7671 %}
7672
7673 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7674 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7675 ins_cost(DEFAULT_COST*3);
7676
7677 expand %{
7678 // FIXME: we should do this in the ideal world.
7679 iRegLdst tmp1;
7680 iRegLdst tmp2;
7681 addL_reg_reg(tmp1, src1, src2);
7682 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7683 addL_reg_reg(dst, tmp1, tmp2);
7684 %}
7685 %}
7686
7687 // AddL + ConvL2I.
7688 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7689 match(Set dst (ConvL2I (AddL src1 src2)));
7690
7691 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7692 size(4);
7693 ins_encode %{
7694 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7695 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7696 %}
7697 ins_pipe(pipe_class_default);
7698 %}
7699
7700 // No constant pool entries required.
7701 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7702 match(Set dst (AddL src1 src2));
7703
7704 format %{ "ADDI $dst, $src1, $src2" %}
7705 size(4);
7706 ins_encode %{
7707 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7708 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7709 %}
7710 ins_pipe(pipe_class_default);
7711 %}
7712
7713 // Long Immediate Addition with 16-bit shifted operand.
7714 // No constant pool entries required.
7715 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7716 match(Set dst (AddL src1 src2));
7717
7718 format %{ "ADDIS $dst, $src1, $src2" %}
7719 size(4);
7720 ins_encode %{
7721 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7722 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7723 %}
7724 ins_pipe(pipe_class_default);
7725 %}
7726
7727 // Pointer Register Addition
7728 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7729 match(Set dst (AddP src1 src2));
7730 format %{ "ADD $dst, $src1, $src2" %}
7731 size(4);
7732 ins_encode %{
7733 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7734 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7735 %}
7736 ins_pipe(pipe_class_default);
7737 %}
7738
7739 // Pointer Immediate Addition
7740 // No constant pool entries required.
7741 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7742 match(Set dst (AddP src1 src2));
7743
7744 format %{ "ADDI $dst, $src1, $src2" %}
7745 size(4);
7746 ins_encode %{
7747 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7748 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7749 %}
7750 ins_pipe(pipe_class_default);
7751 %}
7752
7753 // Pointer Immediate Addition with 16-bit shifted operand.
7754 // No constant pool entries required.
7755 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7756 match(Set dst (AddP src1 src2));
7757
7758 format %{ "ADDIS $dst, $src1, $src2" %}
7759 size(4);
7760 ins_encode %{
7761 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7762 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7763 %}
7764 ins_pipe(pipe_class_default);
7765 %}
7766
7767 //---------------------
7768 // Subtraction Instructions
7769
7770 // Register Subtraction
7771 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7772 match(Set dst (SubI src1 src2));
7773 format %{ "SUBF $dst, $src2, $src1" %}
7774 size(4);
7775 ins_encode %{
7776 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7777 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7778 %}
7779 ins_pipe(pipe_class_default);
7780 %}
7781
7782 // Immediate Subtraction
7783 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7784 // so this rule seems to be unused.
7785 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7786 match(Set dst (SubI src1 src2));
7787 format %{ "SUBI $dst, $src1, $src2" %}
7788 size(4);
7789 ins_encode %{
7790 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7791 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7792 %}
7793 ins_pipe(pipe_class_default);
7794 %}
7795
7796 // SubI from constant (using subfic).
7797 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7798 match(Set dst (SubI src1 src2));
7799 format %{ "SUBI $dst, $src1, $src2" %}
7800
7801 size(4);
7802 ins_encode %{
7803 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7804 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7805 %}
7806 ins_pipe(pipe_class_default);
7807 %}
7808
7809 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7810 // positive integers and 0xF...F for negative ones.
7811 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7812 // no match-rule, false predicate
7813 effect(DEF dst, USE src);
7814 predicate(false);
7815
7816 format %{ "SRAWI $dst, $src, #31" %}
7817 size(4);
7818 ins_encode %{
7819 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7820 __ srawi($dst$$Register, $src$$Register, 0x1f);
7821 %}
7822 ins_pipe(pipe_class_default);
7823 %}
7824
7825 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7826 match(Set dst (AbsI src));
7827 ins_cost(DEFAULT_COST*3);
7828
7829 expand %{
7830 iRegIdst tmp1;
7831 iRegIdst tmp2;
7832 signmask32I_regI(tmp1, src);
7833 xorI_reg_reg(tmp2, tmp1, src);
7834 subI_reg_reg(dst, tmp2, tmp1);
7835 %}
7836 %}
7837
7838 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7839 match(Set dst (SubI zero src2));
7840 format %{ "NEG $dst, $src2" %}
7841 size(4);
7842 ins_encode %{
7843 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7844 __ neg($dst$$Register, $src2$$Register);
7845 %}
7846 ins_pipe(pipe_class_default);
7847 %}
7848
7849 // Long subtraction
7850 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7851 match(Set dst (SubL src1 src2));
7852 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7853 size(4);
7854 ins_encode %{
7855 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7856 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7857 %}
7858 ins_pipe(pipe_class_default);
7859 %}
7860
7861 // SubL + convL2I.
7862 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7863 match(Set dst (ConvL2I (SubL src1 src2)));
7864
7865 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7866 size(4);
7867 ins_encode %{
7868 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7869 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7870 %}
7871 ins_pipe(pipe_class_default);
7872 %}
7873
7874 // Immediate Subtraction
7875 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7876 // so this rule seems to be unused.
7877 // No constant pool entries required.
7878 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7879 match(Set dst (SubL src1 src2));
7880
7881 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7882 size(4);
7883 ins_encode %{
7884 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7885 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7886 %}
7887 ins_pipe(pipe_class_default);
7888 %}
7889
7890 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7891 // positive longs and 0xF...F for negative ones.
7892 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
7893 // no match-rule, false predicate
7894 effect(DEF dst, USE src);
7895 predicate(false);
7896
7897 format %{ "SRADI $dst, $src, #63" %}
7898 size(4);
7899 ins_encode %{
7900 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7901 __ sradi($dst$$Register, $src$$Register, 0x3f);
7902 %}
7903 ins_pipe(pipe_class_default);
7904 %}
7905
7906 // Long negation
7907 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7908 match(Set dst (SubL zero src2));
7909 format %{ "NEG $dst, $src2 \t// long" %}
7910 size(4);
7911 ins_encode %{
7912 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7913 __ neg($dst$$Register, $src2$$Register);
7914 %}
7915 ins_pipe(pipe_class_default);
7916 %}
7917
7918 // NegL + ConvL2I.
7919 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7920 match(Set dst (ConvL2I (SubL zero src2)));
7921
7922 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7923 size(4);
7924 ins_encode %{
7925 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7926 __ neg($dst$$Register, $src2$$Register);
7927 %}
7928 ins_pipe(pipe_class_default);
7929 %}
7930
7931 // Multiplication Instructions
7932 // Integer Multiplication
7933
7934 // Register Multiplication
7935 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7936 match(Set dst (MulI src1 src2));
7937 ins_cost(DEFAULT_COST);
7938
7939 format %{ "MULLW $dst, $src1, $src2" %}
7940 size(4);
7941 ins_encode %{
7942 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
7943 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
7944 %}
7945 ins_pipe(pipe_class_default);
7946 %}
7947
7948 // Immediate Multiplication
7949 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7950 match(Set dst (MulI src1 src2));
7951 ins_cost(DEFAULT_COST);
7952
7953 format %{ "MULLI $dst, $src1, $src2" %}
7954 size(4);
7955 ins_encode %{
7956 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7957 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7958 %}
7959 ins_pipe(pipe_class_default);
7960 %}
7961
7962 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7963 match(Set dst (MulL src1 src2));
7964 ins_cost(DEFAULT_COST);
7965
7966 format %{ "MULLD $dst $src1, $src2 \t// long" %}
7967 size(4);
7968 ins_encode %{
7969 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
7970 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
7971 %}
7972 ins_pipe(pipe_class_default);
7973 %}
7974
7975 // Multiply high for optimized long division by constant.
7976 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7977 match(Set dst (MulHiL src1 src2));
7978 ins_cost(DEFAULT_COST);
7979
7980 format %{ "MULHD $dst $src1, $src2 \t// long" %}
7981 size(4);
7982 ins_encode %{
7983 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
7984 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
7985 %}
7986 ins_pipe(pipe_class_default);
7987 %}
7988
7989 // Immediate Multiplication
7990 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7991 match(Set dst (MulL src1 src2));
7992 ins_cost(DEFAULT_COST);
7993
7994 format %{ "MULLI $dst, $src1, $src2" %}
7995 size(4);
7996 ins_encode %{
7997 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7998 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7999 %}
8000 ins_pipe(pipe_class_default);
8001 %}
8002
8003 // Integer Division with Immediate -1: Negate.
8004 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8005 match(Set dst (DivI src1 src2));
8006 ins_cost(DEFAULT_COST);
8007
8008 format %{ "NEG $dst, $src1 \t// /-1" %}
8009 size(4);
8010 ins_encode %{
8011 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8012 __ neg($dst$$Register, $src1$$Register);
8013 %}
8014 ins_pipe(pipe_class_default);
8015 %}
8016
8017 // Integer Division with constant, but not -1.
8018 // We should be able to improve this by checking the type of src2.
8019 // It might well be that src2 is known to be positive.
8020 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8021 match(Set dst (DivI src1 src2));
8022 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8023 ins_cost(2*DEFAULT_COST);
8024
8025 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8026 size(4);
8027 ins_encode %{
8028 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8029 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8030 %}
8031 ins_pipe(pipe_class_default);
8032 %}
8033
8034 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8035 effect(USE_DEF dst, USE src1, USE crx);
8036 predicate(false);
8037
8038 ins_variable_size_depending_on_alignment(true);
8039
8040 format %{ "CMOVE $dst, neg($src1), $crx" %}
8041 // Worst case is branch + move + stop, no stop without scheduler.
8042 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8043 ins_encode %{
8044 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8045 Label done;
8046 __ bne($crx$$CondRegister, done);
8047 __ neg($dst$$Register, $src1$$Register);
8048 // TODO PPC port __ endgroup_if_needed(_size == 12);
8049 __ bind(done);
8050 %}
8051 ins_pipe(pipe_class_default);
8052 %}
8053
8054 // Integer Division with Registers not containing constants.
8055 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8056 match(Set dst (DivI src1 src2));
8057 ins_cost(10*DEFAULT_COST);
8058
8059 expand %{
8060 immI16 imm %{ (int)-1 %}
8061 flagsReg tmp1;
8062 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8063 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8064 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8065 %}
8066 %}
8067
8068 // Long Division with Immediate -1: Negate.
8069 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8070 match(Set dst (DivL src1 src2));
8071 ins_cost(DEFAULT_COST);
8072
8073 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8074 size(4);
8075 ins_encode %{
8076 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8077 __ neg($dst$$Register, $src1$$Register);
8078 %}
8079 ins_pipe(pipe_class_default);
8080 %}
8081
8082 // Long Division with constant, but not -1.
8083 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8084 match(Set dst (DivL src1 src2));
8085 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8086 ins_cost(2*DEFAULT_COST);
8087
8088 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8089 size(4);
8090 ins_encode %{
8091 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8092 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8093 %}
8094 ins_pipe(pipe_class_default);
8095 %}
8096
8097 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8098 effect(USE_DEF dst, USE src1, USE crx);
8099 predicate(false);
8100
8101 ins_variable_size_depending_on_alignment(true);
8102
8103 format %{ "CMOVE $dst, neg($src1), $crx" %}
8104 // Worst case is branch + move + stop, no stop without scheduler.
8105 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8106 ins_encode %{
8107 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8108 Label done;
8109 __ bne($crx$$CondRegister, done);
8110 __ neg($dst$$Register, $src1$$Register);
8111 // TODO PPC port __ endgroup_if_needed(_size == 12);
8112 __ bind(done);
8113 %}
8114 ins_pipe(pipe_class_default);
8115 %}
8116
8117 // Long Division with Registers not containing constants.
8118 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8119 match(Set dst (DivL src1 src2));
8120 ins_cost(10*DEFAULT_COST);
8121
8122 expand %{
8123 immL16 imm %{ (int)-1 %}
8124 flagsReg tmp1;
8125 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8126 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8127 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8128 %}
8129 %}
8130
8131 // Integer Remainder with registers.
8132 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8133 match(Set dst (ModI src1 src2));
8134 ins_cost(10*DEFAULT_COST);
8135
8136 expand %{
8137 immI16 imm %{ (int)-1 %}
8138 flagsReg tmp1;
8139 iRegIdst tmp2;
8140 iRegIdst tmp3;
8141 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8142 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8143 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8144 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8145 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8146 %}
8147 %}
8148
8149 // Long Remainder with registers
8150 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8151 match(Set dst (ModL src1 src2));
8152 ins_cost(10*DEFAULT_COST);
8153
8154 expand %{
8155 immL16 imm %{ (int)-1 %}
8156 flagsReg tmp1;
8157 iRegLdst tmp2;
8158 iRegLdst tmp3;
8159 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8160 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8161 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8162 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8163 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8164 %}
8165 %}
8166
8167 // Integer Shift Instructions
8168
8169 // Register Shift Left
8170
8171 // Clear all but the lowest #mask bits.
8172 // Used to normalize shift amounts in registers.
8173 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8174 // no match-rule, false predicate
8175 effect(DEF dst, USE src, USE mask);
8176 predicate(false);
8177
8178 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8179 size(4);
8180 ins_encode %{
8181 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8182 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8183 %}
8184 ins_pipe(pipe_class_default);
8185 %}
8186
8187 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8188 // no match-rule, false predicate
8189 effect(DEF dst, USE src1, USE src2);
8190 predicate(false);
8191
8192 format %{ "SLW $dst, $src1, $src2" %}
8193 size(4);
8194 ins_encode %{
8195 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8196 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8197 %}
8198 ins_pipe(pipe_class_default);
8199 %}
8200
8201 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8202 match(Set dst (LShiftI src1 src2));
8203 ins_cost(DEFAULT_COST*2);
8204 expand %{
8205 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8206 iRegIdst tmpI;
8207 maskI_reg_imm(tmpI, src2, mask);
8208 lShiftI_reg_reg(dst, src1, tmpI);
8209 %}
8210 %}
8211
8212 // Register Shift Left Immediate
8213 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8214 match(Set dst (LShiftI src1 src2));
8215
8216 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8217 size(4);
8218 ins_encode %{
8219 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8220 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8221 %}
8222 ins_pipe(pipe_class_default);
8223 %}
8224
8225 // AndI with negpow2-constant + LShiftI
8226 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8227 match(Set dst (LShiftI (AndI src1 src2) src3));
8228 predicate(UseRotateAndMaskInstructionsPPC64);
8229
8230 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8231 size(4);
8232 ins_encode %{
8233 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8234 long src2 = $src2$$constant;
8235 long src3 = $src3$$constant;
8236 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8237 if (maskbits >= 32) {
8238 __ li($dst$$Register, 0); // addi
8239 } else {
8240 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8241 }
8242 %}
8243 ins_pipe(pipe_class_default);
8244 %}
8245
8246 // RShiftI + AndI with negpow2-constant + LShiftI
8247 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8248 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8249 predicate(UseRotateAndMaskInstructionsPPC64);
8250
8251 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8252 size(4);
8253 ins_encode %{
8254 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8255 long src2 = $src2$$constant;
8256 long src3 = $src3$$constant;
8257 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8258 if (maskbits >= 32) {
8259 __ li($dst$$Register, 0); // addi
8260 } else {
8261 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8262 }
8263 %}
8264 ins_pipe(pipe_class_default);
8265 %}
8266
8267 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8268 // no match-rule, false predicate
8269 effect(DEF dst, USE src1, USE src2);
8270 predicate(false);
8271
8272 format %{ "SLD $dst, $src1, $src2" %}
8273 size(4);
8274 ins_encode %{
8275 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8276 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8277 %}
8278 ins_pipe(pipe_class_default);
8279 %}
8280
8281 // Register Shift Left
8282 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8283 match(Set dst (LShiftL src1 src2));
8284 ins_cost(DEFAULT_COST*2);
8285 expand %{
8286 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8287 iRegIdst tmpI;
8288 maskI_reg_imm(tmpI, src2, mask);
8289 lShiftL_regL_regI(dst, src1, tmpI);
8290 %}
8291 %}
8292
8293 // Register Shift Left Immediate
8294 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8295 match(Set dst (LShiftL src1 src2));
8296 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8297 size(4);
8298 ins_encode %{
8299 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8300 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8301 %}
8302 ins_pipe(pipe_class_default);
8303 %}
8304
8305 // If we shift more than 32 bits, we need not convert I2L.
8306 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8307 match(Set dst (LShiftL (ConvI2L src1) src2));
8308 ins_cost(DEFAULT_COST);
8309
8310 size(4);
8311 format %{ "SLDI $dst, i2l($src1), $src2" %}
8312 ins_encode %{
8313 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8314 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8315 %}
8316 ins_pipe(pipe_class_default);
8317 %}
8318
8319 // Shift a postivie int to the left.
8320 // Clrlsldi clears the upper 32 bits and shifts.
8321 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8322 match(Set dst (LShiftL (ConvI2L src1) src2));
8323 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8324
8325 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8326 size(4);
8327 ins_encode %{
8328 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8329 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8330 %}
8331 ins_pipe(pipe_class_default);
8332 %}
8333
8334 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8335 // no match-rule, false predicate
8336 effect(DEF dst, USE src1, USE src2);
8337 predicate(false);
8338
8339 format %{ "SRAW $dst, $src1, $src2" %}
8340 size(4);
8341 ins_encode %{
8342 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8343 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8344 %}
8345 ins_pipe(pipe_class_default);
8346 %}
8347
8348 // Register Arithmetic Shift Right
8349 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8350 match(Set dst (RShiftI src1 src2));
8351 ins_cost(DEFAULT_COST*2);
8352 expand %{
8353 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8354 iRegIdst tmpI;
8355 maskI_reg_imm(tmpI, src2, mask);
8356 arShiftI_reg_reg(dst, src1, tmpI);
8357 %}
8358 %}
8359
8360 // Register Arithmetic Shift Right Immediate
8361 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8362 match(Set dst (RShiftI src1 src2));
8363
8364 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8365 size(4);
8366 ins_encode %{
8367 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8368 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8369 %}
8370 ins_pipe(pipe_class_default);
8371 %}
8372
8373 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8374 // no match-rule, false predicate
8375 effect(DEF dst, USE src1, USE src2);
8376 predicate(false);
8377
8378 format %{ "SRAD $dst, $src1, $src2" %}
8379 size(4);
8380 ins_encode %{
8381 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8382 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8383 %}
8384 ins_pipe(pipe_class_default);
8385 %}
8386
8387 // Register Shift Right Arithmetic Long
8388 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8389 match(Set dst (RShiftL src1 src2));
8390 ins_cost(DEFAULT_COST*2);
8391
8392 expand %{
8393 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8394 iRegIdst tmpI;
8395 maskI_reg_imm(tmpI, src2, mask);
8396 arShiftL_regL_regI(dst, src1, tmpI);
8397 %}
8398 %}
8399
8400 // Register Shift Right Immediate
8401 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8402 match(Set dst (RShiftL src1 src2));
8403
8404 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8405 size(4);
8406 ins_encode %{
8407 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8408 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8409 %}
8410 ins_pipe(pipe_class_default);
8411 %}
8412
8413 // RShiftL + ConvL2I
8414 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8415 match(Set dst (ConvL2I (RShiftL src1 src2)));
8416
8417 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8418 size(4);
8419 ins_encode %{
8420 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8421 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8422 %}
8423 ins_pipe(pipe_class_default);
8424 %}
8425
8426 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8427 // no match-rule, false predicate
8428 effect(DEF dst, USE src1, USE src2);
8429 predicate(false);
8430
8431 format %{ "SRW $dst, $src1, $src2" %}
8432 size(4);
8433 ins_encode %{
8434 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8435 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8436 %}
8437 ins_pipe(pipe_class_default);
8438 %}
8439
8440 // Register Shift Right
8441 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8442 match(Set dst (URShiftI src1 src2));
8443 ins_cost(DEFAULT_COST*2);
8444
8445 expand %{
8446 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8447 iRegIdst tmpI;
8448 maskI_reg_imm(tmpI, src2, mask);
8449 urShiftI_reg_reg(dst, src1, tmpI);
8450 %}
8451 %}
8452
8453 // Register Shift Right Immediate
8454 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8455 match(Set dst (URShiftI src1 src2));
8456
8457 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8458 size(4);
8459 ins_encode %{
8460 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8461 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8462 %}
8463 ins_pipe(pipe_class_default);
8464 %}
8465
8466 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8467 // no match-rule, false predicate
8468 effect(DEF dst, USE src1, USE src2);
8469 predicate(false);
8470
8471 format %{ "SRD $dst, $src1, $src2" %}
8472 size(4);
8473 ins_encode %{
8474 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8475 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8476 %}
8477 ins_pipe(pipe_class_default);
8478 %}
8479
8480 // Register Shift Right
8481 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8482 match(Set dst (URShiftL src1 src2));
8483 ins_cost(DEFAULT_COST*2);
8484
8485 expand %{
8486 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8487 iRegIdst tmpI;
8488 maskI_reg_imm(tmpI, src2, mask);
8489 urShiftL_regL_regI(dst, src1, tmpI);
8490 %}
8491 %}
8492
8493 // Register Shift Right Immediate
8494 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8495 match(Set dst (URShiftL src1 src2));
8496
8497 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8498 size(4);
8499 ins_encode %{
8500 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8501 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8502 %}
8503 ins_pipe(pipe_class_default);
8504 %}
8505
8506 // URShiftL + ConvL2I.
8507 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8508 match(Set dst (ConvL2I (URShiftL src1 src2)));
8509
8510 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8511 size(4);
8512 ins_encode %{
8513 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8514 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8515 %}
8516 ins_pipe(pipe_class_default);
8517 %}
8518
8519 // Register Shift Right Immediate with a CastP2X
8520 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8521 match(Set dst (URShiftL (CastP2X src1) src2));
8522
8523 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8524 size(4);
8525 ins_encode %{
8526 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8527 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8528 %}
8529 ins_pipe(pipe_class_default);
8530 %}
8531
8532 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8533 match(Set dst (ConvL2I (ConvI2L src)));
8534
8535 format %{ "EXTSW $dst, $src \t// int->int" %}
8536 size(4);
8537 ins_encode %{
8538 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8539 __ extsw($dst$$Register, $src$$Register);
8540 %}
8541 ins_pipe(pipe_class_default);
8542 %}
8543
8544 //----------Rotate Instructions------------------------------------------------
8545
8546 // Rotate Left by 8-bit immediate
8547 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8548 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8549 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8550
8551 format %{ "ROTLWI $dst, $src, $lshift" %}
8552 size(4);
8553 ins_encode %{
8554 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8555 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8556 %}
8557 ins_pipe(pipe_class_default);
8558 %}
8559
8560 // Rotate Right by 8-bit immediate
8561 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8562 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8563 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8564
8565 format %{ "ROTRWI $dst, $rshift" %}
8566 size(4);
8567 ins_encode %{
8568 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8569 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8570 %}
8571 ins_pipe(pipe_class_default);
8572 %}
8573
8574 //----------Floating Point Arithmetic Instructions-----------------------------
8575
8576 // Add float single precision
8577 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8578 match(Set dst (AddF src1 src2));
8579
8580 format %{ "FADDS $dst, $src1, $src2" %}
8581 size(4);
8582 ins_encode %{
8583 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8584 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8585 %}
8586 ins_pipe(pipe_class_default);
8587 %}
8588
8589 // Add float double precision
8590 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8591 match(Set dst (AddD src1 src2));
8592
8593 format %{ "FADD $dst, $src1, $src2" %}
8594 size(4);
8595 ins_encode %{
8596 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8597 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8598 %}
8599 ins_pipe(pipe_class_default);
8600 %}
8601
8602 // Sub float single precision
8603 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8604 match(Set dst (SubF src1 src2));
8605
8606 format %{ "FSUBS $dst, $src1, $src2" %}
8607 size(4);
8608 ins_encode %{
8609 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8610 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8611 %}
8612 ins_pipe(pipe_class_default);
8613 %}
8614
8615 // Sub float double precision
8616 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8617 match(Set dst (SubD src1 src2));
8618 format %{ "FSUB $dst, $src1, $src2" %}
8619 size(4);
8620 ins_encode %{
8621 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8622 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8623 %}
8624 ins_pipe(pipe_class_default);
8625 %}
8626
8627 // Mul float single precision
8628 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8629 match(Set dst (MulF src1 src2));
8630 format %{ "FMULS $dst, $src1, $src2" %}
8631 size(4);
8632 ins_encode %{
8633 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8634 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8635 %}
8636 ins_pipe(pipe_class_default);
8637 %}
8638
8639 // Mul float double precision
8640 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8641 match(Set dst (MulD src1 src2));
8642 format %{ "FMUL $dst, $src1, $src2" %}
8643 size(4);
8644 ins_encode %{
8645 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8646 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8647 %}
8648 ins_pipe(pipe_class_default);
8649 %}
8650
8651 // Div float single precision
8652 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8653 match(Set dst (DivF src1 src2));
8654 format %{ "FDIVS $dst, $src1, $src2" %}
8655 size(4);
8656 ins_encode %{
8657 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8658 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8659 %}
8660 ins_pipe(pipe_class_default);
8661 %}
8662
8663 // Div float double precision
8664 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8665 match(Set dst (DivD src1 src2));
8666 format %{ "FDIV $dst, $src1, $src2" %}
8667 size(4);
8668 ins_encode %{
8669 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8670 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8671 %}
8672 ins_pipe(pipe_class_default);
8673 %}
8674
8675 // Absolute float single precision
8676 instruct absF_reg(regF dst, regF src) %{
8677 match(Set dst (AbsF src));
8678 format %{ "FABS $dst, $src \t// float" %}
8679 size(4);
8680 ins_encode %{
8681 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8682 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8683 %}
8684 ins_pipe(pipe_class_default);
8685 %}
8686
8687 // Absolute float double precision
8688 instruct absD_reg(regD dst, regD src) %{
8689 match(Set dst (AbsD src));
8690 format %{ "FABS $dst, $src \t// double" %}
8691 size(4);
8692 ins_encode %{
8693 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8694 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8695 %}
8696 ins_pipe(pipe_class_default);
8697 %}
8698
8699 instruct negF_reg(regF dst, regF src) %{
8700 match(Set dst (NegF src));
8701 format %{ "FNEG $dst, $src \t// float" %}
8702 size(4);
8703 ins_encode %{
8704 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8705 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8706 %}
8707 ins_pipe(pipe_class_default);
8708 %}
8709
8710 instruct negD_reg(regD dst, regD src) %{
8711 match(Set dst (NegD src));
8712 format %{ "FNEG $dst, $src \t// double" %}
8713 size(4);
8714 ins_encode %{
8715 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8716 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8717 %}
8718 ins_pipe(pipe_class_default);
8719 %}
8720
8721 // AbsF + NegF.
8722 instruct negF_absF_reg(regF dst, regF src) %{
8723 match(Set dst (NegF (AbsF src)));
8724 format %{ "FNABS $dst, $src \t// float" %}
8725 size(4);
8726 ins_encode %{
8727 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8728 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8729 %}
8730 ins_pipe(pipe_class_default);
8731 %}
8732
8733 // AbsD + NegD.
8734 instruct negD_absD_reg(regD dst, regD src) %{
8735 match(Set dst (NegD (AbsD src)));
8736 format %{ "FNABS $dst, $src \t// double" %}
8737 size(4);
8738 ins_encode %{
8739 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8740 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8741 %}
8742 ins_pipe(pipe_class_default);
8743 %}
8744
8745 // VM_Version::has_fsqrt() decides if this node will be used.
8746 // Sqrt float double precision
8747 instruct sqrtD_reg(regD dst, regD src) %{
8748 match(Set dst (SqrtD src));
8749 format %{ "FSQRT $dst, $src" %}
8750 size(4);
8751 ins_encode %{
8752 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8753 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8754 %}
8755 ins_pipe(pipe_class_default);
8756 %}
8757
8758 // Single-precision sqrt.
8759 instruct sqrtF_reg(regF dst, regF src) %{
8760 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8761 ins_cost(DEFAULT_COST);
8762
8763 format %{ "FSQRTS $dst, $src" %}
8764 size(4);
8765 ins_encode %{
8766 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8767 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8768 %}
8769 ins_pipe(pipe_class_default);
8770 %}
8771
8772 instruct roundDouble_nop(regD dst) %{
8773 match(Set dst (RoundDouble dst));
8774 ins_cost(0);
8775
8776 format %{ " -- \t// RoundDouble not needed - empty" %}
8777 size(0);
8778 // PPC results are already "rounded" (i.e., normal-format IEEE).
8779 ins_encode( /*empty*/ );
8780 ins_pipe(pipe_class_default);
8781 %}
8782
8783 instruct roundFloat_nop(regF dst) %{
8784 match(Set dst (RoundFloat dst));
8785 ins_cost(0);
8786
8787 format %{ " -- \t// RoundFloat not needed - empty" %}
8788 size(0);
8789 // PPC results are already "rounded" (i.e., normal-format IEEE).
8790 ins_encode( /*empty*/ );
8791 ins_pipe(pipe_class_default);
8792 %}
8793
8794 //----------Logical Instructions-----------------------------------------------
8795
8796 // And Instructions
8797
8798 // Register And
8799 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8800 match(Set dst (AndI src1 src2));
8801 format %{ "AND $dst, $src1, $src2" %}
8802 size(4);
8803 ins_encode %{
8804 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8805 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8806 %}
8807 ins_pipe(pipe_class_default);
8808 %}
8809
8810 // Immediate And
8811 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8812 match(Set dst (AndI src1 src2));
8813 effect(KILL cr0);
8814
8815 format %{ "ANDI $dst, $src1, $src2" %}
8816 size(4);
8817 ins_encode %{
8818 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8819 // FIXME: avoid andi_ ?
8820 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8821 %}
8822 ins_pipe(pipe_class_default);
8823 %}
8824
8825 // Immediate And where the immediate is a negative power of 2.
8826 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8827 match(Set dst (AndI src1 src2));
8828 format %{ "ANDWI $dst, $src1, $src2" %}
8829 size(4);
8830 ins_encode %{
8831 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8832 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8833 %}
8834 ins_pipe(pipe_class_default);
8835 %}
8836
8837 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8838 match(Set dst (AndI src1 src2));
8839 format %{ "ANDWI $dst, $src1, $src2" %}
8840 size(4);
8841 ins_encode %{
8842 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8843 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8844 %}
8845 ins_pipe(pipe_class_default);
8846 %}
8847
8848 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8849 match(Set dst (AndI src1 src2));
8850 predicate(UseRotateAndMaskInstructionsPPC64);
8851 format %{ "ANDWI $dst, $src1, $src2" %}
8852 size(4);
8853 ins_encode %{
8854 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8855 __ rlwinm($dst$$Register, $src1$$Register, 0,
8856 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8857 %}
8858 ins_pipe(pipe_class_default);
8859 %}
8860
8861 // Register And Long
8862 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8863 match(Set dst (AndL src1 src2));
8864 ins_cost(DEFAULT_COST);
8865
8866 format %{ "AND $dst, $src1, $src2 \t// long" %}
8867 size(4);
8868 ins_encode %{
8869 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8870 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8871 %}
8872 ins_pipe(pipe_class_default);
8873 %}
8874
8875 // Immediate And long
8876 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8877 match(Set dst (AndL src1 src2));
8878 effect(KILL cr0);
8879 ins_cost(DEFAULT_COST);
8880
8881 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8882 size(4);
8883 ins_encode %{
8884 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8885 // FIXME: avoid andi_ ?
8886 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8887 %}
8888 ins_pipe(pipe_class_default);
8889 %}
8890
8891 // Immediate And Long where the immediate is a negative power of 2.
8892 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8893 match(Set dst (AndL src1 src2));
8894 format %{ "ANDDI $dst, $src1, $src2" %}
8895 size(4);
8896 ins_encode %{
8897 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8898 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8899 %}
8900 ins_pipe(pipe_class_default);
8901 %}
8902
8903 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8904 match(Set dst (AndL src1 src2));
8905 format %{ "ANDDI $dst, $src1, $src2" %}
8906 size(4);
8907 ins_encode %{
8908 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8909 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8910 %}
8911 ins_pipe(pipe_class_default);
8912 %}
8913
8914 // AndL + ConvL2I.
8915 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8916 match(Set dst (ConvL2I (AndL src1 src2)));
8917 ins_cost(DEFAULT_COST);
8918
8919 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8920 size(4);
8921 ins_encode %{
8922 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8923 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8924 %}
8925 ins_pipe(pipe_class_default);
8926 %}
8927
8928 // Or Instructions
8929
8930 // Register Or
8931 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8932 match(Set dst (OrI src1 src2));
8933 format %{ "OR $dst, $src1, $src2" %}
8934 size(4);
8935 ins_encode %{
8936 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8937 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8938 %}
8939 ins_pipe(pipe_class_default);
8940 %}
8941
8942 // Expand does not work with above instruct. (??)
8943 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8944 // no match-rule
8945 effect(DEF dst, USE src1, USE src2);
8946 format %{ "OR $dst, $src1, $src2" %}
8947 size(4);
8948 ins_encode %{
8949 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8950 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8951 %}
8952 ins_pipe(pipe_class_default);
8953 %}
8954
8955 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8956 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
8957 ins_cost(DEFAULT_COST*3);
8958
8959 expand %{
8960 // FIXME: we should do this in the ideal world.
8961 iRegIdst tmp1;
8962 iRegIdst tmp2;
8963 orI_reg_reg(tmp1, src1, src2);
8964 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8965 orI_reg_reg(dst, tmp1, tmp2);
8966 %}
8967 %}
8968
8969 // Immediate Or
8970 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
8971 match(Set dst (OrI src1 src2));
8972 format %{ "ORI $dst, $src1, $src2" %}
8973 size(4);
8974 ins_encode %{
8975 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
8976 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
8977 %}
8978 ins_pipe(pipe_class_default);
8979 %}
8980
8981 // Register Or Long
8982 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8983 match(Set dst (OrL src1 src2));
8984 ins_cost(DEFAULT_COST);
8985
8986 size(4);
8987 format %{ "OR $dst, $src1, $src2 \t// long" %}
8988 ins_encode %{
8989 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8990 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8991 %}
8992 ins_pipe(pipe_class_default);
8993 %}
8994
8995 // OrL + ConvL2I.
8996 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8997 match(Set dst (ConvL2I (OrL src1 src2)));
8998 ins_cost(DEFAULT_COST);
8999
9000 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9001 size(4);
9002 ins_encode %{
9003 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9004 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9005 %}
9006 ins_pipe(pipe_class_default);
9007 %}
9008
9009 // Immediate Or long
9010 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9011 match(Set dst (OrL src1 con));
9012 ins_cost(DEFAULT_COST);
9013
9014 format %{ "ORI $dst, $src1, $con \t// long" %}
9015 size(4);
9016 ins_encode %{
9017 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9018 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9019 %}
9020 ins_pipe(pipe_class_default);
9021 %}
9022
9023 // Xor Instructions
9024
9025 // Register Xor
9026 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9027 match(Set dst (XorI src1 src2));
9028 format %{ "XOR $dst, $src1, $src2" %}
9029 size(4);
9030 ins_encode %{
9031 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9032 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9033 %}
9034 ins_pipe(pipe_class_default);
9035 %}
9036
9037 // Expand does not work with above instruct. (??)
9038 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9039 // no match-rule
9040 effect(DEF dst, USE src1, USE src2);
9041 format %{ "XOR $dst, $src1, $src2" %}
9042 size(4);
9043 ins_encode %{
9044 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9045 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9046 %}
9047 ins_pipe(pipe_class_default);
9048 %}
9049
9050 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9051 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9052 ins_cost(DEFAULT_COST*3);
9053
9054 expand %{
9055 // FIXME: we should do this in the ideal world.
9056 iRegIdst tmp1;
9057 iRegIdst tmp2;
9058 xorI_reg_reg(tmp1, src1, src2);
9059 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9060 xorI_reg_reg(dst, tmp1, tmp2);
9061 %}
9062 %}
9063
9064 // Immediate Xor
9065 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9066 match(Set dst (XorI src1 src2));
9067 format %{ "XORI $dst, $src1, $src2" %}
9068 size(4);
9069 ins_encode %{
9070 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9071 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9072 %}
9073 ins_pipe(pipe_class_default);
9074 %}
9075
9076 // Register Xor Long
9077 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9078 match(Set dst (XorL src1 src2));
9079 ins_cost(DEFAULT_COST);
9080
9081 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9082 size(4);
9083 ins_encode %{
9084 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9085 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9086 %}
9087 ins_pipe(pipe_class_default);
9088 %}
9089
9090 // XorL + ConvL2I.
9091 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9092 match(Set dst (ConvL2I (XorL src1 src2)));
9093 ins_cost(DEFAULT_COST);
9094
9095 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9096 size(4);
9097 ins_encode %{
9098 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9099 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9100 %}
9101 ins_pipe(pipe_class_default);
9102 %}
9103
9104 // Immediate Xor Long
9105 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9106 match(Set dst (XorL src1 src2));
9107 ins_cost(DEFAULT_COST);
9108
9109 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9110 size(4);
9111 ins_encode %{
9112 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9113 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9114 %}
9115 ins_pipe(pipe_class_default);
9116 %}
9117
9118 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9119 match(Set dst (XorI src1 src2));
9120 ins_cost(DEFAULT_COST);
9121
9122 format %{ "NOT $dst, $src1 ($src2)" %}
9123 size(4);
9124 ins_encode %{
9125 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9126 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9127 %}
9128 ins_pipe(pipe_class_default);
9129 %}
9130
9131 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9132 match(Set dst (XorL src1 src2));
9133 ins_cost(DEFAULT_COST);
9134
9135 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9136 size(4);
9137 ins_encode %{
9138 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9139 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9140 %}
9141 ins_pipe(pipe_class_default);
9142 %}
9143
9144 // And-complement
9145 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9146 match(Set dst (AndI (XorI src1 src2) src3));
9147 ins_cost(DEFAULT_COST);
9148
9149 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9150 size(4);
9151 ins_encode( enc_andc(dst, src3, src1) );
9152 ins_pipe(pipe_class_default);
9153 %}
9154
9155 // And-complement
9156 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9157 // no match-rule, false predicate
9158 effect(DEF dst, USE src1, USE src2);
9159 predicate(false);
9160
9161 format %{ "ANDC $dst, $src1, $src2" %}
9162 size(4);
9163 ins_encode %{
9164 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9165 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9166 %}
9167 ins_pipe(pipe_class_default);
9168 %}
9169
9170 //----------Moves between int/long and float/double----------------------------
9171 //
9172 // The following rules move values from int/long registers/stack-locations
9173 // to float/double registers/stack-locations and vice versa, without doing any
9174 // conversions. These rules are used to implement the bit-conversion methods
9175 // of java.lang.Float etc., e.g.
9176 // int floatToIntBits(float value)
9177 // float intBitsToFloat(int bits)
9178 //
9179 // Notes on the implementation on ppc64:
9180 // We only provide rules which move between a register and a stack-location,
9181 // because we always have to go through memory when moving between a float
9182 // register and an integer register.
9183
9184 //---------- Chain stack slots between similar types --------
9185
9186 // These are needed so that the rules below can match.
9187
9188 // Load integer from stack slot
9189 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9190 match(Set dst src);
9191 ins_cost(MEMORY_REF_COST);
9192
9193 format %{ "LWZ $dst, $src" %}
9194 size(4);
9195 ins_encode( enc_lwz(dst, src) );
9196 ins_pipe(pipe_class_memory);
9197 %}
9198
9199 // Store integer to stack slot
9200 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9201 match(Set dst src);
9202 ins_cost(MEMORY_REF_COST);
9203
9204 format %{ "STW $src, $dst \t// stk" %}
9205 size(4);
9206 ins_encode( enc_stw(src, dst) ); // rs=rt
9207 ins_pipe(pipe_class_memory);
9208 %}
9209
9210 // Load long from stack slot
9211 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9212 match(Set dst src);
9213 ins_cost(MEMORY_REF_COST);
9214
9215 format %{ "LD $dst, $src \t// long" %}
9216 size(4);
9217 ins_encode( enc_ld(dst, src) );
9218 ins_pipe(pipe_class_memory);
9219 %}
9220
9221 // Store long to stack slot
9222 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9223 match(Set dst src);
9224 ins_cost(MEMORY_REF_COST);
9225
9226 format %{ "STD $src, $dst \t// long" %}
9227 size(4);
9228 ins_encode( enc_std(src, dst) ); // rs=rt
9229 ins_pipe(pipe_class_memory);
9230 %}
9231
9232 //----------Moves between int and float
9233
9234 // Move float value from float stack-location to integer register.
9235 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9236 match(Set dst (MoveF2I src));
9237 ins_cost(MEMORY_REF_COST);
9238
9239 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9240 size(4);
9241 ins_encode( enc_lwz(dst, src) );
9242 ins_pipe(pipe_class_memory);
9243 %}
9244
9245 // Move float value from float register to integer stack-location.
9246 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9247 match(Set dst (MoveF2I src));
9248 ins_cost(MEMORY_REF_COST);
9249
9250 format %{ "STFS $src, $dst \t// MoveF2I" %}
9251 size(4);
9252 ins_encode( enc_stfs(src, dst) );
9253 ins_pipe(pipe_class_memory);
9254 %}
9255
9256 // Move integer value from integer stack-location to float register.
9257 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9258 match(Set dst (MoveI2F src));
9259 ins_cost(MEMORY_REF_COST);
9260
9261 format %{ "LFS $dst, $src \t// MoveI2F" %}
9262 size(4);
9263 ins_encode %{
9264 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9265 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9266 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9267 %}
9268 ins_pipe(pipe_class_memory);
9269 %}
9270
9271 // Move integer value from integer register to float stack-location.
9272 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9273 match(Set dst (MoveI2F src));
9274 ins_cost(MEMORY_REF_COST);
9275
9276 format %{ "STW $src, $dst \t// MoveI2F" %}
9277 size(4);
9278 ins_encode( enc_stw(src, dst) );
9279 ins_pipe(pipe_class_memory);
9280 %}
9281
9282 //----------Moves between long and float
9283
9284 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9285 // no match-rule, false predicate
9286 effect(DEF dst, USE src);
9287 predicate(false);
9288
9289 format %{ "storeD $src, $dst \t// STACK" %}
9290 size(4);
9291 ins_encode( enc_stfd(src, dst) );
9292 ins_pipe(pipe_class_default);
9293 %}
9294
9295 //----------Moves between long and double
9296
9297 // Move double value from double stack-location to long register.
9298 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9299 match(Set dst (MoveD2L src));
9300 ins_cost(MEMORY_REF_COST);
9301 size(4);
9302 format %{ "LD $dst, $src \t// MoveD2L" %}
9303 ins_encode( enc_ld(dst, src) );
9304 ins_pipe(pipe_class_memory);
9305 %}
9306
9307 // Move double value from double register to long stack-location.
9308 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9309 match(Set dst (MoveD2L src));
9310 effect(DEF dst, USE src);
9311 ins_cost(MEMORY_REF_COST);
9312
9313 format %{ "STFD $src, $dst \t// MoveD2L" %}
9314 size(4);
9315 ins_encode( enc_stfd(src, dst) );
9316 ins_pipe(pipe_class_memory);
9317 %}
9318
9319 // Move long value from long stack-location to double register.
9320 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9321 match(Set dst (MoveL2D src));
9322 ins_cost(MEMORY_REF_COST);
9323
9324 format %{ "LFD $dst, $src \t// MoveL2D" %}
9325 size(4);
9326 ins_encode( enc_lfd(dst, src) );
9327 ins_pipe(pipe_class_memory);
9328 %}
9329
9330 // Move long value from long register to double stack-location.
9331 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9332 match(Set dst (MoveL2D src));
9333 ins_cost(MEMORY_REF_COST);
9334
9335 format %{ "STD $src, $dst \t// MoveL2D" %}
9336 size(4);
9337 ins_encode( enc_std(src, dst) );
9338 ins_pipe(pipe_class_memory);
9339 %}
9340
9341 //----------Register Move Instructions-----------------------------------------
9342
9343 // Replicate for Superword
9344
9345 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9346 predicate(false);
9347 effect(DEF dst, USE src);
9348
9349 format %{ "MR $dst, $src \t// replicate " %}
9350 // variable size, 0 or 4.
9351 ins_encode %{
9352 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9353 __ mr_if_needed($dst$$Register, $src$$Register);
9354 %}
9355 ins_pipe(pipe_class_default);
9356 %}
9357
9358 //----------Cast instructions (Java-level type cast)---------------------------
9359
9360 // Cast Long to Pointer for unsafe natives.
9361 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9362 match(Set dst (CastX2P src));
9363
9364 format %{ "MR $dst, $src \t// Long->Ptr" %}
9365 // variable size, 0 or 4.
9366 ins_encode %{
9367 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9368 __ mr_if_needed($dst$$Register, $src$$Register);
9369 %}
9370 ins_pipe(pipe_class_default);
9371 %}
9372
9373 // Cast Pointer to Long for unsafe natives.
9374 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9375 match(Set dst (CastP2X src));
9376
9377 format %{ "MR $dst, $src \t// Ptr->Long" %}
9378 // variable size, 0 or 4.
9379 ins_encode %{
9380 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9381 __ mr_if_needed($dst$$Register, $src$$Register);
9382 %}
9383 ins_pipe(pipe_class_default);
9384 %}
9385
9386 instruct castPP(iRegPdst dst) %{
9387 match(Set dst (CastPP dst));
9388 format %{ " -- \t// castPP of $dst" %}
9389 size(0);
9390 ins_encode( /*empty*/ );
9391 ins_pipe(pipe_class_default);
9392 %}
9393
9394 instruct castII(iRegIdst dst) %{
9395 match(Set dst (CastII dst));
9396 format %{ " -- \t// castII of $dst" %}
9397 size(0);
9398 ins_encode( /*empty*/ );
9399 ins_pipe(pipe_class_default);
9400 %}
9401
9402 instruct checkCastPP(iRegPdst dst) %{
9403 match(Set dst (CheckCastPP dst));
9404 format %{ " -- \t// checkcastPP of $dst" %}
9405 size(0);
9406 ins_encode( /*empty*/ );
9407 ins_pipe(pipe_class_default);
9408 %}
9409
9410 //----------Convert instructions-----------------------------------------------
9411
9412 // Convert to boolean.
9413
9414 // int_to_bool(src) : { 1 if src != 0
9415 // { 0 else
9416 //
9417 // strategy:
9418 // 1) Count leading zeros of 32 bit-value src,
9419 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9420 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9421 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9422
9423 // convI2Bool
9424 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9425 match(Set dst (Conv2B src));
9426 predicate(UseCountLeadingZerosInstructionsPPC64);
9427 ins_cost(DEFAULT_COST);
9428
9429 expand %{
9430 immI shiftAmount %{ 0x5 %}
9431 uimmI16 mask %{ 0x1 %}
9432 iRegIdst tmp1;
9433 iRegIdst tmp2;
9434 countLeadingZerosI(tmp1, src);
9435 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9436 xorI_reg_uimm16(dst, tmp2, mask);
9437 %}
9438 %}
9439
9440 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9441 match(Set dst (Conv2B src));
9442 effect(TEMP crx);
9443 predicate(!UseCountLeadingZerosInstructionsPPC64);
9444 ins_cost(DEFAULT_COST);
9445
9446 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9447 "LI $dst, #0\n\t"
9448 "BEQ $crx, done\n\t"
9449 "LI $dst, #1\n"
9450 "done:" %}
9451 size(16);
9452 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9453 ins_pipe(pipe_class_compare);
9454 %}
9455
9456 // ConvI2B + XorI
9457 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9458 match(Set dst (XorI (Conv2B src) mask));
9459 predicate(UseCountLeadingZerosInstructionsPPC64);
9460 ins_cost(DEFAULT_COST);
9461
9462 expand %{
9463 immI shiftAmount %{ 0x5 %}
9464 iRegIdst tmp1;
9465 countLeadingZerosI(tmp1, src);
9466 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9467 %}
9468 %}
9469
9470 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9471 match(Set dst (XorI (Conv2B src) mask));
9472 effect(TEMP crx);
9473 predicate(!UseCountLeadingZerosInstructionsPPC64);
9474 ins_cost(DEFAULT_COST);
9475
9476 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9477 "LI $dst, #1\n\t"
9478 "BEQ $crx, done\n\t"
9479 "LI $dst, #0\n"
9480 "done:" %}
9481 size(16);
9482 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9483 ins_pipe(pipe_class_compare);
9484 %}
9485
9486 // AndI 0b0..010..0 + ConvI2B
9487 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9488 match(Set dst (Conv2B (AndI src mask)));
9489 predicate(UseRotateAndMaskInstructionsPPC64);
9490 ins_cost(DEFAULT_COST);
9491
9492 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9493 size(4);
9494 ins_encode %{
9495 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9496 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9497 %}
9498 ins_pipe(pipe_class_default);
9499 %}
9500
9501 // Convert pointer to boolean.
9502 //
9503 // ptr_to_bool(src) : { 1 if src != 0
9504 // { 0 else
9505 //
9506 // strategy:
9507 // 1) Count leading zeros of 64 bit-value src,
9508 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9509 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9510 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9511
9512 // ConvP2B
9513 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9514 match(Set dst (Conv2B src));
9515 predicate(UseCountLeadingZerosInstructionsPPC64);
9516 ins_cost(DEFAULT_COST);
9517
9518 expand %{
9519 immI shiftAmount %{ 0x6 %}
9520 uimmI16 mask %{ 0x1 %}
9521 iRegIdst tmp1;
9522 iRegIdst tmp2;
9523 countLeadingZerosP(tmp1, src);
9524 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9525 xorI_reg_uimm16(dst, tmp2, mask);
9526 %}
9527 %}
9528
9529 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9530 match(Set dst (Conv2B src));
9531 effect(TEMP crx);
9532 predicate(!UseCountLeadingZerosInstructionsPPC64);
9533 ins_cost(DEFAULT_COST);
9534
9535 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9536 "LI $dst, #0\n\t"
9537 "BEQ $crx, done\n\t"
9538 "LI $dst, #1\n"
9539 "done:" %}
9540 size(16);
9541 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9542 ins_pipe(pipe_class_compare);
9543 %}
9544
9545 // ConvP2B + XorI
9546 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9547 match(Set dst (XorI (Conv2B src) mask));
9548 predicate(UseCountLeadingZerosInstructionsPPC64);
9549 ins_cost(DEFAULT_COST);
9550
9551 expand %{
9552 immI shiftAmount %{ 0x6 %}
9553 iRegIdst tmp1;
9554 countLeadingZerosP(tmp1, src);
9555 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9556 %}
9557 %}
9558
9559 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9560 match(Set dst (XorI (Conv2B src) mask));
9561 effect(TEMP crx);
9562 predicate(!UseCountLeadingZerosInstructionsPPC64);
9563 ins_cost(DEFAULT_COST);
9564
9565 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9566 "LI $dst, #1\n\t"
9567 "BEQ $crx, done\n\t"
9568 "LI $dst, #0\n"
9569 "done:" %}
9570 size(16);
9571 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9572 ins_pipe(pipe_class_compare);
9573 %}
9574
9575 // if src1 < src2, return -1 else return 0
9576 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9577 match(Set dst (CmpLTMask src1 src2));
9578 ins_cost(DEFAULT_COST*4);
9579
9580 expand %{
9581 iRegIdst src1s;
9582 iRegIdst src2s;
9583 iRegIdst diff;
9584 sxtI_reg(src1s, src1); // ensure proper sign extention
9585 sxtI_reg(src2s, src2); // ensure proper sign extention
9586 subI_reg_reg(diff, src1s, src2s);
9587 // Need to consider >=33 bit result, therefore we need signmaskL.
9588 signmask64I_regI(dst, diff);
9589 %}
9590 %}
9591
9592 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9593 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9594 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9595 size(4);
9596 ins_encode %{
9597 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9598 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9599 %}
9600 ins_pipe(pipe_class_default);
9601 %}
9602
9603 //----------Arithmetic Conversion Instructions---------------------------------
9604
9605 // Convert to Byte -- nop
9606 // Convert to Short -- nop
9607
9608 // Convert to Int
9609
9610 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9611 match(Set dst (RShiftI (LShiftI src amount) amount));
9612 format %{ "EXTSB $dst, $src \t// byte->int" %}
9613 size(4);
9614 ins_encode %{
9615 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9616 __ extsb($dst$$Register, $src$$Register);
9617 %}
9618 ins_pipe(pipe_class_default);
9619 %}
9620
9621 // LShiftI 16 + RShiftI 16 converts short to int.
9622 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9623 match(Set dst (RShiftI (LShiftI src amount) amount));
9624 format %{ "EXTSH $dst, $src \t// short->int" %}
9625 size(4);
9626 ins_encode %{
9627 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9628 __ extsh($dst$$Register, $src$$Register);
9629 %}
9630 ins_pipe(pipe_class_default);
9631 %}
9632
9633 // ConvL2I + ConvI2L: Sign extend int in long register.
9634 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9635 match(Set dst (ConvI2L (ConvL2I src)));
9636
9637 format %{ "EXTSW $dst, $src \t// long->long" %}
9638 size(4);
9639 ins_encode %{
9640 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9641 __ extsw($dst$$Register, $src$$Register);
9642 %}
9643 ins_pipe(pipe_class_default);
9644 %}
9645
9646 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9647 match(Set dst (ConvL2I src));
9648 format %{ "MR $dst, $src \t// long->int" %}
9649 // variable size, 0 or 4
9650 ins_encode %{
9651 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9652 __ mr_if_needed($dst$$Register, $src$$Register);
9653 %}
9654 ins_pipe(pipe_class_default);
9655 %}
9656
9657 instruct convD2IRaw_regD(regD dst, regD src) %{
9658 // no match-rule, false predicate
9659 effect(DEF dst, USE src);
9660 predicate(false);
9661
9662 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9663 size(4);
9664 ins_encode %{
9665 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9666 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9667 %}
9668 ins_pipe(pipe_class_default);
9669 %}
9670
9671 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9672 // no match-rule, false predicate
9673 effect(DEF dst, USE crx, USE src);
9674 predicate(false);
9675
9676 ins_variable_size_depending_on_alignment(true);
9677
9678 format %{ "cmovI $crx, $dst, $src" %}
9679 // Worst case is branch + move + stop, no stop without scheduler.
9680 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9681 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9682 ins_pipe(pipe_class_default);
9683 %}
9684
9685 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9686 // no match-rule, false predicate
9687 effect(DEF dst, USE crx, USE mem);
9688 predicate(false);
9689
9690 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9691 postalloc_expand %{
9692 //
9693 // replaces
9694 //
9695 // region dst crx mem
9696 // \ | | /
9697 // dst=cmovI_bso_stackSlotL_conLvalue0
9698 //
9699 // with
9700 //
9701 // region dst
9702 // \ /
9703 // dst=loadConI16(0)
9704 // |
9705 // ^ region dst crx mem
9706 // | \ | | /
9707 // dst=cmovI_bso_stackSlotL
9708 //
9709
9710 // Create new nodes.
9711 MachNode *m1 = new (C) loadConI16Node();
9712 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9713
9714 // inputs for new nodes
9715 m1->add_req(n_region);
9716 m2->add_req(n_region, n_crx, n_mem);
9717
9718 // precedences for new nodes
9719 m2->add_prec(m1);
9720
9721 // operands for new nodes
9722 m1->_opnds[0] = op_dst;
9723 m1->_opnds[1] = new (C) immI16Oper(0);
9724
9725 m2->_opnds[0] = op_dst;
9726 m2->_opnds[1] = op_crx;
9727 m2->_opnds[2] = op_mem;
9728
9729 // registers for new nodes
9730 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9731 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9732
9733 // Insert new nodes.
9734 nodes->push(m1);
9735 nodes->push(m2);
9736 %}
9737 %}
9738
9739 // Double to Int conversion, NaN is mapped to 0.
9740 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9741 match(Set dst (ConvD2I src));
9742 ins_cost(DEFAULT_COST);
9743
9744 expand %{
9745 regD tmpD;
9746 stackSlotL tmpS;
9747 flagsReg crx;
9748 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9749 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9750 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9751 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9752 %}
9753 %}
9754
9755 instruct convF2IRaw_regF(regF dst, regF src) %{
9756 // no match-rule, false predicate
9757 effect(DEF dst, USE src);
9758 predicate(false);
9759
9760 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9761 size(4);
9762 ins_encode %{
9763 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9764 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9765 %}
9766 ins_pipe(pipe_class_default);
9767 %}
9768
9769 // Float to Int conversion, NaN is mapped to 0.
9770 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9771 match(Set dst (ConvF2I src));
9772 ins_cost(DEFAULT_COST);
9773
9774 expand %{
9775 regF tmpF;
9776 stackSlotL tmpS;
9777 flagsReg crx;
9778 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9779 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9780 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9781 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9782 %}
9783 %}
9784
9785 // Convert to Long
9786
9787 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9788 match(Set dst (ConvI2L src));
9789 format %{ "EXTSW $dst, $src \t// int->long" %}
9790 size(4);
9791 ins_encode %{
9792 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9793 __ extsw($dst$$Register, $src$$Register);
9794 %}
9795 ins_pipe(pipe_class_default);
9796 %}
9797
9798 // Zero-extend: convert unsigned int to long (convUI2L).
9799 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9800 match(Set dst (AndL (ConvI2L src) mask));
9801 ins_cost(DEFAULT_COST);
9802
9803 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9804 size(4);
9805 ins_encode %{
9806 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9807 __ clrldi($dst$$Register, $src$$Register, 32);
9808 %}
9809 ins_pipe(pipe_class_default);
9810 %}
9811
9812 // Zero-extend: convert unsigned int to long in long register.
9813 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9814 match(Set dst (AndL src mask));
9815 ins_cost(DEFAULT_COST);
9816
9817 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9818 size(4);
9819 ins_encode %{
9820 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9821 __ clrldi($dst$$Register, $src$$Register, 32);
9822 %}
9823 ins_pipe(pipe_class_default);
9824 %}
9825
9826 instruct convF2LRaw_regF(regF dst, regF src) %{
9827 // no match-rule, false predicate
9828 effect(DEF dst, USE src);
9829 predicate(false);
9830
9831 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9832 size(4);
9833 ins_encode %{
9834 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9835 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9836 %}
9837 ins_pipe(pipe_class_default);
9838 %}
9839
9840 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9841 // no match-rule, false predicate
9842 effect(DEF dst, USE crx, USE src);
9843 predicate(false);
9844
9845 ins_variable_size_depending_on_alignment(true);
9846
9847 format %{ "cmovL $crx, $dst, $src" %}
9848 // Worst case is branch + move + stop, no stop without scheduler.
9849 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9850 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9851 ins_pipe(pipe_class_default);
9852 %}
9853
9854 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9855 // no match-rule, false predicate
9856 effect(DEF dst, USE crx, USE mem);
9857 predicate(false);
9858
9859 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9860 postalloc_expand %{
9861 //
9862 // replaces
9863 //
9864 // region dst crx mem
9865 // \ | | /
9866 // dst=cmovL_bso_stackSlotL_conLvalue0
9867 //
9868 // with
9869 //
9870 // region dst
9871 // \ /
9872 // dst=loadConL16(0)
9873 // |
9874 // ^ region dst crx mem
9875 // | \ | | /
9876 // dst=cmovL_bso_stackSlotL
9877 //
9878
9879 // Create new nodes.
9880 MachNode *m1 = new (C) loadConL16Node();
9881 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9882
9883 // inputs for new nodes
9884 m1->add_req(n_region);
9885 m2->add_req(n_region, n_crx, n_mem);
9886 m2->add_prec(m1);
9887
9888 // operands for new nodes
9889 m1->_opnds[0] = op_dst;
9890 m1->_opnds[1] = new (C) immL16Oper(0);
9891 m2->_opnds[0] = op_dst;
9892 m2->_opnds[1] = op_crx;
9893 m2->_opnds[2] = op_mem;
9894
9895 // registers for new nodes
9896 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9897 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9898
9899 // Insert new nodes.
9900 nodes->push(m1);
9901 nodes->push(m2);
9902 %}
9903 %}
9904
9905 // Float to Long conversion, NaN is mapped to 0.
9906 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9907 match(Set dst (ConvF2L src));
9908 ins_cost(DEFAULT_COST);
9909
9910 expand %{
9911 regF tmpF;
9912 stackSlotL tmpS;
9913 flagsReg crx;
9914 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9915 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9916 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9917 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9918 %}
9919 %}
9920
9921 instruct convD2LRaw_regD(regD dst, regD src) %{
9922 // no match-rule, false predicate
9923 effect(DEF dst, USE src);
9924 predicate(false);
9925
9926 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9927 size(4);
9928 ins_encode %{
9929 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9930 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9931 %}
9932 ins_pipe(pipe_class_default);
9933 %}
9934
9935 // Double to Long conversion, NaN is mapped to 0.
9936 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
9937 match(Set dst (ConvD2L src));
9938 ins_cost(DEFAULT_COST);
9939
9940 expand %{
9941 regD tmpD;
9942 stackSlotL tmpS;
9943 flagsReg crx;
9944 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9945 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
9946 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9947 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9948 %}
9949 %}
9950
9951 // Convert to Float
9952
9953 // Placed here as needed in expand.
9954 instruct convL2DRaw_regD(regD dst, regD src) %{
9955 // no match-rule, false predicate
9956 effect(DEF dst, USE src);
9957 predicate(false);
9958
9959 format %{ "FCFID $dst, $src \t// convL2D" %}
9960 size(4);
9961 ins_encode %{
9962 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
9963 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
9964 %}
9965 ins_pipe(pipe_class_default);
9966 %}
9967
9968 // Placed here as needed in expand.
9969 instruct convD2F_reg(regF dst, regD src) %{
9970 match(Set dst (ConvD2F src));
9971 format %{ "FRSP $dst, $src \t// convD2F" %}
9972 size(4);
9973 ins_encode %{
9974 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
9975 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
9976 %}
9977 ins_pipe(pipe_class_default);
9978 %}
9979
9980 // Integer to Float conversion.
9981 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
9982 match(Set dst (ConvI2F src));
9983 predicate(!VM_Version::has_fcfids());
9984 ins_cost(DEFAULT_COST);
9985
9986 expand %{
9987 iRegLdst tmpL;
9988 stackSlotL tmpS;
9989 regD tmpD;
9990 regD tmpD2;
9991 convI2L_reg(tmpL, src); // Sign-extension int to long.
9992 regL_to_stkL(tmpS, tmpL); // Store long to stack.
9993 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
9994 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
9995 convD2F_reg(dst, tmpD2); // Convert double to float.
9996 %}
9997 %}
9998
9999 instruct convL2FRaw_regF(regF dst, regD src) %{
10000 // no match-rule, false predicate
10001 effect(DEF dst, USE src);
10002 predicate(false);
10003
10004 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10005 size(4);
10006 ins_encode %{
10007 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10008 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10009 %}
10010 ins_pipe(pipe_class_default);
10011 %}
10012
10013 // Integer to Float conversion. Special version for Power7.
10014 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10015 match(Set dst (ConvI2F src));
10016 predicate(VM_Version::has_fcfids());
10017 ins_cost(DEFAULT_COST);
10018
10019 expand %{
10020 iRegLdst tmpL;
10021 stackSlotL tmpS;
10022 regD tmpD;
10023 convI2L_reg(tmpL, src); // Sign-extension int to long.
10024 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10025 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10026 convL2FRaw_regF(dst, tmpD); // Convert to float.
10027 %}
10028 %}
10029
10030 // L2F to avoid runtime call.
10031 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10032 match(Set dst (ConvL2F src));
10033 predicate(VM_Version::has_fcfids());
10034 ins_cost(DEFAULT_COST);
10035
10036 expand %{
10037 stackSlotL tmpS;
10038 regD tmpD;
10039 regL_to_stkL(tmpS, src); // Store long to stack.
10040 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10041 convL2FRaw_regF(dst, tmpD); // Convert to float.
10042 %}
10043 %}
10044
10045 // Moved up as used in expand.
10046 //instruct convD2F_reg(regF dst, regD src) %{%}
10047
10048 // Convert to Double
10049
10050 // Integer to Double conversion.
10051 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10052 match(Set dst (ConvI2D src));
10053 ins_cost(DEFAULT_COST);
10054
10055 expand %{
10056 iRegLdst tmpL;
10057 stackSlotL tmpS;
10058 regD tmpD;
10059 convI2L_reg(tmpL, src); // Sign-extension int to long.
10060 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10061 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10062 convL2DRaw_regD(dst, tmpD); // Convert to double.
10063 %}
10064 %}
10065
10066 // Long to Double conversion
10067 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10068 match(Set dst (ConvL2D src));
10069 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10070
10071 expand %{
10072 regD tmpD;
10073 moveL2D_stack_reg(tmpD, src);
10074 convL2DRaw_regD(dst, tmpD);
10075 %}
10076 %}
10077
10078 instruct convF2D_reg(regD dst, regF src) %{
10079 match(Set dst (ConvF2D src));
10080 format %{ "FMR $dst, $src \t// float->double" %}
10081 // variable size, 0 or 4
10082 ins_encode %{
10083 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10084 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10085 %}
10086 ins_pipe(pipe_class_default);
10087 %}
10088
10089 //----------Control Flow Instructions------------------------------------------
10090 // Compare Instructions
10091
10092 // Compare Integers
10093 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10094 match(Set crx (CmpI src1 src2));
10095 size(4);
10096 format %{ "CMPW $crx, $src1, $src2" %}
10097 ins_encode %{
10098 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10099 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10100 %}
10101 ins_pipe(pipe_class_compare);
10102 %}
10103
10104 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10105 match(Set crx (CmpI src1 src2));
10106 format %{ "CMPWI $crx, $src1, $src2" %}
10107 size(4);
10108 ins_encode %{
10109 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10110 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10111 %}
10112 ins_pipe(pipe_class_compare);
10113 %}
10114
10115 // (src1 & src2) == 0?
10116 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10117 match(Set cr0 (CmpI (AndI src1 src2) zero));
10118 // r0 is killed
10119 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10120 size(4);
10121 ins_encode %{
10122 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10123 // FIXME: avoid andi_ ?
10124 __ andi_(R0, $src1$$Register, $src2$$constant);
10125 %}
10126 ins_pipe(pipe_class_compare);
10127 %}
10128
10129 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10130 match(Set crx (CmpL src1 src2));
10131 format %{ "CMPD $crx, $src1, $src2" %}
10132 size(4);
10133 ins_encode %{
10134 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10135 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10136 %}
10137 ins_pipe(pipe_class_compare);
10138 %}
10139
10140 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10141 match(Set crx (CmpL src1 src2));
10142 format %{ "CMPDI $crx, $src1, $src2" %}
10143 size(4);
10144 ins_encode %{
10145 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10146 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10147 %}
10148 ins_pipe(pipe_class_compare);
10149 %}
10150
10151 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10152 match(Set cr0 (CmpL (AndL src1 src2) zero));
10153 // r0 is killed
10154 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10155 size(4);
10156 ins_encode %{
10157 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10158 __ and_(R0, $src1$$Register, $src2$$Register);
10159 %}
10160 ins_pipe(pipe_class_compare);
10161 %}
10162
10163 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10164 match(Set cr0 (CmpL (AndL src1 src2) zero));
10165 // r0 is killed
10166 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10167 size(4);
10168 ins_encode %{
10169 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10170 // FIXME: avoid andi_ ?
10171 __ andi_(R0, $src1$$Register, $src2$$constant);
10172 %}
10173 ins_pipe(pipe_class_compare);
10174 %}
10175
10176 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10177 // no match-rule, false predicate
10178 effect(DEF dst, USE crx);
10179 predicate(false);
10180
10181 ins_variable_size_depending_on_alignment(true);
10182
10183 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10184 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10185 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10186 ins_encode %{
10187 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10188 Label done;
10189 // li(Rdst, 0); // equal -> 0
10190 __ beq($crx$$CondRegister, done);
10191 __ li($dst$$Register, 1); // greater -> +1
10192 __ bgt($crx$$CondRegister, done);
10193 __ li($dst$$Register, -1); // unordered or less -> -1
10194 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10195 __ bind(done);
10196 %}
10197 ins_pipe(pipe_class_compare);
10198 %}
10199
10200 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10201 // no match-rule, false predicate
10202 effect(DEF dst, USE crx);
10203 predicate(false);
10204
10205 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10206 postalloc_expand %{
10207 //
10208 // replaces
10209 //
10210 // region crx
10211 // \ |
10212 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10213 //
10214 // with
10215 //
10216 // region
10217 // \
10218 // dst=loadConI16(0)
10219 // |
10220 // ^ region crx
10221 // | \ |
10222 // dst=cmovI_conIvalueMinus1_conIvalue1
10223 //
10224
10225 // Create new nodes.
10226 MachNode *m1 = new (C) loadConI16Node();
10227 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10228
10229 // inputs for new nodes
10230 m1->add_req(n_region);
10231 m2->add_req(n_region, n_crx);
10232 m2->add_prec(m1);
10233
10234 // operands for new nodes
10235 m1->_opnds[0] = op_dst;
10236 m1->_opnds[1] = new (C) immI16Oper(0);
10237 m2->_opnds[0] = op_dst;
10238 m2->_opnds[1] = op_crx;
10239
10240 // registers for new nodes
10241 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10242 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10243
10244 // Insert new nodes.
10245 nodes->push(m1);
10246 nodes->push(m2);
10247 %}
10248 %}
10249
10250 // Manifest a CmpL3 result in an integer register. Very painful.
10251 // This is the test to avoid.
10252 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10253 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10254 match(Set dst (CmpL3 src1 src2));
10255 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10256
10257 expand %{
10258 flagsReg tmp1;
10259 cmpL_reg_reg(tmp1, src1, src2);
10260 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10261 %}
10262 %}
10263
10264 // Implicit range checks.
10265 // A range check in the ideal world has one of the following shapes:
10266 // - (If le (CmpU length index)), (IfTrue throw exception)
10267 // - (If lt (CmpU index length)), (IfFalse throw exception)
10268 //
10269 // Match range check 'If le (CmpU length index)'.
10270 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10271 match(If cmp (CmpU src_length index));
10272 effect(USE labl);
10273 predicate(TrapBasedRangeChecks &&
10274 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10275 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10276 (Matcher::branches_to_uncommon_trap(_leaf)));
10277
10278 ins_is_TrapBasedCheckNode(true);
10279
10280 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10281 size(4);
10282 ins_encode %{
10283 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10284 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10285 __ trap_range_check_le($src_length$$Register, $index$$constant);
10286 } else {
10287 // Both successors are uncommon traps, probability is 0.
10288 // Node got flipped during fixup flow.
10289 assert($cmp$$cmpcode == 0x9, "must be greater");
10290 __ trap_range_check_g($src_length$$Register, $index$$constant);
10291 }
10292 %}
10293 ins_pipe(pipe_class_trap);
10294 %}
10295
10296 // Match range check 'If lt (CmpU index length)'.
10297 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10298 match(If cmp (CmpU src_index src_length));
10299 effect(USE labl);
10300 predicate(TrapBasedRangeChecks &&
10301 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10302 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10303 (Matcher::branches_to_uncommon_trap(_leaf)));
10304
10305 ins_is_TrapBasedCheckNode(true);
10306
10307 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10308 size(4);
10309 ins_encode %{
10310 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10311 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10312 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10313 } else {
10314 // Both successors are uncommon traps, probability is 0.
10315 // Node got flipped during fixup flow.
10316 assert($cmp$$cmpcode == 0x8, "must be less");
10317 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10318 }
10319 %}
10320 ins_pipe(pipe_class_trap);
10321 %}
10322
10323 // Match range check 'If lt (CmpU index length)'.
10324 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10325 match(If cmp (CmpU src_index length));
10326 effect(USE labl);
10327 predicate(TrapBasedRangeChecks &&
10328 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10329 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10330 (Matcher::branches_to_uncommon_trap(_leaf)));
10331
10332 ins_is_TrapBasedCheckNode(true);
10333
10334 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10335 size(4);
10336 ins_encode %{
10337 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10338 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10339 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10340 } else {
10341 // Both successors are uncommon traps, probability is 0.
10342 // Node got flipped during fixup flow.
10343 assert($cmp$$cmpcode == 0x8, "must be less");
10344 __ trap_range_check_l($src_index$$Register, $length$$constant);
10345 }
10346 %}
10347 ins_pipe(pipe_class_trap);
10348 %}
10349
10350 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10351 match(Set crx (CmpU src1 src2));
10352 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10353 size(4);
10354 ins_encode %{
10355 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10356 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10357 %}
10358 ins_pipe(pipe_class_compare);
10359 %}
10360
10361 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10362 match(Set crx (CmpU src1 src2));
10363 size(4);
10364 format %{ "CMPLWI $crx, $src1, $src2" %}
10365 ins_encode %{
10366 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10367 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10368 %}
10369 ins_pipe(pipe_class_compare);
10370 %}
10371
10372 // Implicit zero checks (more implicit null checks).
10373 // No constant pool entries required.
10374 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10375 match(If cmp (CmpN value zero));
10376 effect(USE labl);
10377 predicate(TrapBasedNullChecks &&
10378 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10379 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10380 Matcher::branches_to_uncommon_trap(_leaf));
10381 ins_cost(1);
10382
10383 ins_is_TrapBasedCheckNode(true);
10384
10385 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10386 size(4);
10387 ins_encode %{
10388 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10389 if ($cmp$$cmpcode == 0xA) {
10390 __ trap_null_check($value$$Register);
10391 } else {
10392 // Both successors are uncommon traps, probability is 0.
10393 // Node got flipped during fixup flow.
10394 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10395 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10396 }
10397 %}
10398 ins_pipe(pipe_class_trap);
10399 %}
10400
10401 // Compare narrow oops.
10402 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10403 match(Set crx (CmpN src1 src2));
10404
10405 size(4);
10406 ins_cost(DEFAULT_COST);
10407 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10408 ins_encode %{
10409 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10410 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10411 %}
10412 ins_pipe(pipe_class_compare);
10413 %}
10414
10415 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10416 match(Set crx (CmpN src1 src2));
10417 // Make this more expensive than zeroCheckN_iReg_imm0.
10418 ins_cost(DEFAULT_COST);
10419
10420 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10421 size(4);
10422 ins_encode %{
10423 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10424 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10425 %}
10426 ins_pipe(pipe_class_compare);
10427 %}
10428
10429 // Implicit zero checks (more implicit null checks).
10430 // No constant pool entries required.
10431 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10432 match(If cmp (CmpP value zero));
10433 effect(USE labl);
10434 predicate(TrapBasedNullChecks &&
10435 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10436 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10437 Matcher::branches_to_uncommon_trap(_leaf));
10438
10439 ins_is_TrapBasedCheckNode(true);
10440
10441 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10442 size(4);
10443 ins_encode %{
10444 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10445 if ($cmp$$cmpcode == 0xA) {
10446 __ trap_null_check($value$$Register);
10447 } else {
10448 // Both successors are uncommon traps, probability is 0.
10449 // Node got flipped during fixup flow.
10450 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10451 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10452 }
10453 %}
10454 ins_pipe(pipe_class_trap);
10455 %}
10456
10457 // Compare Pointers
10458 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10459 match(Set crx (CmpP src1 src2));
10460 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10461 size(4);
10462 ins_encode %{
10463 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10464 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10465 %}
10466 ins_pipe(pipe_class_compare);
10467 %}
10468
10469 // Used in postalloc expand.
10470 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10471 // This match rule prevents reordering of node before a safepoint.
10472 // This only makes sense if this instructions is used exclusively
10473 // for the expansion of EncodeP!
10474 match(Set crx (CmpP src1 src2));
10475 predicate(false);
10476
10477 format %{ "CMPDI $crx, $src1, $src2" %}
10478 size(4);
10479 ins_encode %{
10480 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10481 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10482 %}
10483 ins_pipe(pipe_class_compare);
10484 %}
10485
10486 //----------Float Compares----------------------------------------------------
10487
10488 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10489 // no match-rule, false predicate
10490 effect(DEF crx, USE src1, USE src2);
10491 predicate(false);
10492
10493 format %{ "cmpFUrd $crx, $src1, $src2" %}
10494 size(4);
10495 ins_encode %{
10496 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10497 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10498 %}
10499 ins_pipe(pipe_class_default);
10500 %}
10501
10502 instruct cmov_bns_less(flagsReg crx) %{
10503 // no match-rule, false predicate
10504 effect(DEF crx);
10505 predicate(false);
10506
10507 ins_variable_size_depending_on_alignment(true);
10508
10509 format %{ "cmov $crx" %}
10510 // Worst case is branch + move + stop, no stop without scheduler.
10511 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10512 ins_encode %{
10513 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10514 Label done;
10515 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10516 __ li(R0, 0);
10517 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10518 // TODO PPC port __ endgroup_if_needed(_size == 16);
10519 __ bind(done);
10520 %}
10521 ins_pipe(pipe_class_default);
10522 %}
10523
10524 // Compare floating, generate condition code.
10525 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10526 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10527 //
10528 // The following code sequence occurs a lot in mpegaudio:
10529 //
10530 // block BXX:
10531 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10532 // cmpFUrd CCR6, F11, F9
10533 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10534 // cmov CCR6
10535 // 8: instruct branchConSched:
10536 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10537 match(Set crx (CmpF src1 src2));
10538 ins_cost(DEFAULT_COST+BRANCH_COST);
10539
10540 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10541 postalloc_expand %{
10542 //
10543 // replaces
10544 //
10545 // region src1 src2
10546 // \ | |
10547 // crx=cmpF_reg_reg
10548 //
10549 // with
10550 //
10551 // region src1 src2
10552 // \ | |
10553 // crx=cmpFUnordered_reg_reg
10554 // |
10555 // ^ region
10556 // | \
10557 // crx=cmov_bns_less
10558 //
10559
10560 // Create new nodes.
10561 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10562 MachNode *m2 = new (C) cmov_bns_lessNode();
10563
10564 // inputs for new nodes
10565 m1->add_req(n_region, n_src1, n_src2);
10566 m2->add_req(n_region);
10567 m2->add_prec(m1);
10568
10569 // operands for new nodes
10570 m1->_opnds[0] = op_crx;
10571 m1->_opnds[1] = op_src1;
10572 m1->_opnds[2] = op_src2;
10573 m2->_opnds[0] = op_crx;
10574
10575 // registers for new nodes
10576 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10577 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10578
10579 // Insert new nodes.
10580 nodes->push(m1);
10581 nodes->push(m2);
10582 %}
10583 %}
10584
10585 // Compare float, generate -1,0,1
10586 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10587 match(Set dst (CmpF3 src1 src2));
10588 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10589
10590 expand %{
10591 flagsReg tmp1;
10592 cmpFUnordered_reg_reg(tmp1, src1, src2);
10593 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10594 %}
10595 %}
10596
10597 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10598 // no match-rule, false predicate
10599 effect(DEF crx, USE src1, USE src2);
10600 predicate(false);
10601
10602 format %{ "cmpFUrd $crx, $src1, $src2" %}
10603 size(4);
10604 ins_encode %{
10605 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10606 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10607 %}
10608 ins_pipe(pipe_class_default);
10609 %}
10610
10611 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10612 match(Set crx (CmpD src1 src2));
10613 ins_cost(DEFAULT_COST+BRANCH_COST);
10614
10615 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10616 postalloc_expand %{
10617 //
10618 // replaces
10619 //
10620 // region src1 src2
10621 // \ | |
10622 // crx=cmpD_reg_reg
10623 //
10624 // with
10625 //
10626 // region src1 src2
10627 // \ | |
10628 // crx=cmpDUnordered_reg_reg
10629 // |
10630 // ^ region
10631 // | \
10632 // crx=cmov_bns_less
10633 //
10634
10635 // create new nodes
10636 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10637 MachNode *m2 = new (C) cmov_bns_lessNode();
10638
10639 // inputs for new nodes
10640 m1->add_req(n_region, n_src1, n_src2);
10641 m2->add_req(n_region);
10642 m2->add_prec(m1);
10643
10644 // operands for new nodes
10645 m1->_opnds[0] = op_crx;
10646 m1->_opnds[1] = op_src1;
10647 m1->_opnds[2] = op_src2;
10648 m2->_opnds[0] = op_crx;
10649
10650 // registers for new nodes
10651 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10652 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10653
10654 // Insert new nodes.
10655 nodes->push(m1);
10656 nodes->push(m2);
10657 %}
10658 %}
10659
10660 // Compare double, generate -1,0,1
10661 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10662 match(Set dst (CmpD3 src1 src2));
10663 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10664
10665 expand %{
10666 flagsReg tmp1;
10667 cmpDUnordered_reg_reg(tmp1, src1, src2);
10668 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10669 %}
10670 %}
10671
10672 //----------Branches---------------------------------------------------------
10673 // Jump
10674
10675 // Direct Branch.
10676 instruct branch(label labl) %{
10677 match(Goto);
10678 effect(USE labl);
10679 ins_cost(BRANCH_COST);
10680
10681 format %{ "B $labl" %}
10682 size(4);
10683 ins_encode %{
10684 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10685 Label d; // dummy
10686 __ bind(d);
10687 Label* p = $labl$$label;
10688 // `p' is `NULL' when this encoding class is used only to
10689 // determine the size of the encoded instruction.
10690 Label& l = (NULL == p)? d : *(p);
10691 __ b(l);
10692 %}
10693 ins_pipe(pipe_class_default);
10694 %}
10695
10696 // Conditional Near Branch
10697 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10698 // Same match rule as `branchConFar'.
10699 match(If cmp crx);
10700 effect(USE lbl);
10701 ins_cost(BRANCH_COST);
10702
10703 // If set to 1 this indicates that the current instruction is a
10704 // short variant of a long branch. This avoids using this
10705 // instruction in first-pass matching. It will then only be used in
10706 // the `Shorten_branches' pass.
10707 ins_short_branch(1);
10708
10709 format %{ "B$cmp $crx, $lbl" %}
10710 size(4);
10711 ins_encode( enc_bc(crx, cmp, lbl) );
10712 ins_pipe(pipe_class_default);
10713 %}
10714
10715 // This is for cases when the ppc64 `bc' instruction does not
10716 // reach far enough. So we emit a far branch here, which is more
10717 // expensive.
10718 //
10719 // Conditional Far Branch
10720 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10721 // Same match rule as `branchCon'.
10722 match(If cmp crx);
10723 effect(USE crx, USE lbl);
10724 predicate(!false /* TODO: PPC port HB_Schedule*/);
10725 // Higher cost than `branchCon'.
10726 ins_cost(5*BRANCH_COST);
10727
10728 // This is not a short variant of a branch, but the long variant.
10729 ins_short_branch(0);
10730
10731 format %{ "B_FAR$cmp $crx, $lbl" %}
10732 size(8);
10733 ins_encode( enc_bc_far(crx, cmp, lbl) );
10734 ins_pipe(pipe_class_default);
10735 %}
10736
10737 // Conditional Branch used with Power6 scheduler (can be far or short).
10738 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10739 // Same match rule as `branchCon'.
10740 match(If cmp crx);
10741 effect(USE crx, USE lbl);
10742 predicate(false /* TODO: PPC port HB_Schedule*/);
10743 // Higher cost than `branchCon'.
10744 ins_cost(5*BRANCH_COST);
10745
10746 // Actually size doesn't depend on alignment but on shortening.
10747 ins_variable_size_depending_on_alignment(true);
10748 // long variant.
10749 ins_short_branch(0);
10750
10751 format %{ "B_FAR$cmp $crx, $lbl" %}
10752 size(8); // worst case
10753 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10754 ins_pipe(pipe_class_default);
10755 %}
10756
10757 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10758 match(CountedLoopEnd cmp crx);
10759 effect(USE labl);
10760 ins_cost(BRANCH_COST);
10761
10762 // short variant.
10763 ins_short_branch(1);
10764
10765 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10766 size(4);
10767 ins_encode( enc_bc(crx, cmp, labl) );
10768 ins_pipe(pipe_class_default);
10769 %}
10770
10771 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10772 match(CountedLoopEnd cmp crx);
10773 effect(USE labl);
10774 predicate(!false /* TODO: PPC port HB_Schedule */);
10775 ins_cost(BRANCH_COST);
10776
10777 // Long variant.
10778 ins_short_branch(0);
10779
10780 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10781 size(8);
10782 ins_encode( enc_bc_far(crx, cmp, labl) );
10783 ins_pipe(pipe_class_default);
10784 %}
10785
10786 // Conditional Branch used with Power6 scheduler (can be far or short).
10787 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10788 match(CountedLoopEnd cmp crx);
10789 effect(USE labl);
10790 predicate(false /* TODO: PPC port HB_Schedule */);
10791 // Higher cost than `branchCon'.
10792 ins_cost(5*BRANCH_COST);
10793
10794 // Actually size doesn't depend on alignment but on shortening.
10795 ins_variable_size_depending_on_alignment(true);
10796 // Long variant.
10797 ins_short_branch(0);
10798
10799 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10800 size(8); // worst case
10801 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10802 ins_pipe(pipe_class_default);
10803 %}
10804
10805 // ============================================================================
10806 // Java runtime operations, intrinsics and other complex operations.
10807
10808 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10809 // array for an instance of the superklass. Set a hidden internal cache on a
10810 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10811 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10812 //
10813 // GL TODO: Improve this.
10814 // - result should not be a TEMP
10815 // - Add match rule as on sparc avoiding additional Cmp.
10816 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10817 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10818 match(Set result (PartialSubtypeCheck subklass superklass));
10819 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10820 ins_cost(DEFAULT_COST*10);
10821
10822 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10823 ins_encode %{
10824 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10825 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10826 $tmp_klass$$Register, NULL, $result$$Register);
10827 %}
10828 ins_pipe(pipe_class_default);
10829 %}
10830
10831 // inlined locking and unlocking
10832
10833 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10834 match(Set crx (FastLock oop box));
10835 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10836 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10837
10838 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10839 ins_encode %{
10840 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10841 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10842 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10843 // If locking was successfull, crx should indicate 'EQ'.
10844 // The compiler generates a branch to the runtime call to
10845 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10846 %}
10847 ins_pipe(pipe_class_compare);
10848 %}
10849
10850 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10851 match(Set crx (FastUnlock oop box));
10852 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10853
10854 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10855 ins_encode %{
10856 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10857 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10858 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10859 // If unlocking was successfull, crx should indicate 'EQ'.
10860 // The compiler generates a branch to the runtime call to
10861 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10862 %}
10863 ins_pipe(pipe_class_compare);
10864 %}
10865
10866 // Align address.
10867 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10868 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10869
10870 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10871 size(4);
10872 ins_encode %{
10873 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10874 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10875 %}
10876 ins_pipe(pipe_class_default);
10877 %}
10878
10879 // Array size computation.
10880 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10881 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10882
10883 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10884 size(4);
10885 ins_encode %{
10886 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10887 __ subf($dst$$Register, $start$$Register, $end$$Register);
10888 %}
10889 ins_pipe(pipe_class_default);
10890 %}
10891
10892 // Clear-array with dynamic array-size.
10893 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10894 match(Set dummy (ClearArray cnt base));
10895 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10896 ins_cost(MEMORY_REF_COST);
10897
10898 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10899
10900 format %{ "ClearArray $cnt, $base" %}
10901 ins_encode %{
10902 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10903 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10904 %}
10905 ins_pipe(pipe_class_default);
10906 %}
10907
10908 // String_IndexOf for needle of length 1.
10909 //
10910 // Match needle into immediate operands: no loadConP node needed. Saves one
10911 // register and two instructions over string_indexOf_imm1Node.
10912 //
10913 // Assumes register result differs from all input registers.
10914 //
10915 // Preserves registers haystack, haycnt
10916 // Kills registers tmp1, tmp2
10917 // Defines registers result
10918 //
10919 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10920 //
10921 // Unfortunately this does not match too often. In many situations the AddP is used
10922 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10923 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10924 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10925 iRegIdst tmp1, iRegIdst tmp2,
10926 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10927 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10928 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10929
10930 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10931
10932 ins_cost(150);
10933 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10934 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10935
10936 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
10937 ins_encode %{
10938 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10939 immPOper *needleOper = (immPOper *)$needleImm;
10940 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10941 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10942
10943 __ string_indexof_1($result$$Register,
10944 $haystack$$Register, $haycnt$$Register,
10945 R0, needle_values->char_at(0),
10946 $tmp1$$Register, $tmp2$$Register);
10947 %}
10948 ins_pipe(pipe_class_compare);
10949 %}
10950
10951 // String_IndexOf for needle of length 1.
10952 //
10953 // Special case requires less registers and emits less instructions.
10954 //
10955 // Assumes register result differs from all input registers.
10956 //
10957 // Preserves registers haystack, haycnt
10958 // Kills registers tmp1, tmp2, needle
10959 // Defines registers result
10960 //
10961 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10962 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10963 rscratch2RegP needle, immI_1 needlecntImm,
10964 iRegIdst tmp1, iRegIdst tmp2,
10965 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10966 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10967 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
10968 TEMP tmp1, TEMP tmp2);
10969 // Required for EA: check if it is still a type_array.
10970 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
10971 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
10972 ins_cost(180);
10973
10974 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10975
10976 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
10977 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
10978 ins_encode %{
10979 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10980 Node *ndl = in(operand_index($needle)); // The node that defines needle.
10981 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
10982 guarantee(needle_values, "sanity");
10983 if (needle_values != NULL) {
10984 __ string_indexof_1($result$$Register,
10985 $haystack$$Register, $haycnt$$Register,
10986 R0, needle_values->char_at(0),
10987 $tmp1$$Register, $tmp2$$Register);
10988 } else {
10989 __ string_indexof_1($result$$Register,
10990 $haystack$$Register, $haycnt$$Register,
10991 $needle$$Register, 0,
10992 $tmp1$$Register, $tmp2$$Register);
10993 }
10994 %}
10995 ins_pipe(pipe_class_compare);
10996 %}
10997
10998 // String_IndexOf.
10999 //
11000 // Length of needle as immediate. This saves instruction loading constant needle
11001 // length.
11002 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11003 // completely or do it in vector instruction. This should save registers for
11004 // needlecnt and needle.
11005 //
11006 // Assumes register result differs from all input registers.
11007 // Overwrites haycnt, needlecnt.
11008 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11009 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11010 iRegPsrc needle, uimmI15 needlecntImm,
11011 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11012 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11013 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11014 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11015 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11016 // Required for EA: check if it is still a type_array.
11017 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11018 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11019 ins_cost(250);
11020
11021 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11022
11023 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11024 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11025 ins_encode %{
11026 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11027 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11028 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11029
11030 __ string_indexof($result$$Register,
11031 $haystack$$Register, $haycnt$$Register,
11032 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11033 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11034 %}
11035 ins_pipe(pipe_class_compare);
11036 %}
11037
11038 // StrIndexOf node.
11039 //
11040 // Assumes register result differs from all input registers.
11041 // Overwrites haycnt, needlecnt.
11042 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11043 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11044 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11045 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11046 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11047 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11048 TEMP result,
11049 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11050 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11051 ins_cost(300);
11052
11053 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11054
11055 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11056 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11057 ins_encode %{
11058 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11059 __ string_indexof($result$$Register,
11060 $haystack$$Register, $haycnt$$Register,
11061 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11062 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11063 %}
11064 ins_pipe(pipe_class_compare);
11065 %}
11066
11067 // String equals with immediate.
11068 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11069 iRegPdst tmp1, iRegPdst tmp2,
11070 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11071 match(Set result (StrEquals (Binary str1 str2) cntImm));
11072 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11073 KILL cr0, KILL cr6, KILL ctr);
11074 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11075 ins_cost(250);
11076
11077 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11078
11079 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11080 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11081 ins_encode %{
11082 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11083 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11084 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11085 %}
11086 ins_pipe(pipe_class_compare);
11087 %}
11088
11089 // String equals.
11090 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11091 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11092 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11093 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11094 match(Set result (StrEquals (Binary str1 str2) cnt));
11095 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11096 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11097 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11098 ins_cost(300);
11099
11100 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11101
11102 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11103 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11104 ins_encode %{
11105 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11106 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11107 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11108 %}
11109 ins_pipe(pipe_class_compare);
11110 %}
11111
11112 // String compare.
11113 // Char[] pointers are passed in.
11114 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11115 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11116 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11117 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11118 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11119 ins_cost(300);
11120
11121 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11122
11123 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11124 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11125 ins_encode %{
11126 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11127 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11128 $result$$Register, $tmp$$Register);
11129 %}
11130 ins_pipe(pipe_class_compare);
11131 %}
11132
11133 //---------- Min/Max Instructions ---------------------------------------------
11134
11135 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11136 match(Set dst (MinI src1 src2));
11137 ins_cost(DEFAULT_COST*6);
11138
11139 expand %{
11140 iRegIdst src1s;
11141 iRegIdst src2s;
11142 iRegIdst diff;
11143 iRegIdst sm;
11144 iRegIdst doz; // difference or zero
11145 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11146 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11147 subI_reg_reg(diff, src2s, src1s);
11148 // Need to consider >=33 bit result, therefore we need signmaskL.
11149 signmask64I_regI(sm, diff);
11150 andI_reg_reg(doz, diff, sm); // <=0
11151 addI_reg_reg(dst, doz, src1s);
11152 %}
11153 %}
11154
11155 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11156 match(Set dst (MaxI src1 src2));
11157 ins_cost(DEFAULT_COST*6);
11158
11159 expand %{
11160 immI_minus1 m1 %{ -1 %}
11161 iRegIdst src1s;
11162 iRegIdst src2s;
11163 iRegIdst diff;
11164 iRegIdst sm;
11165 iRegIdst doz; // difference or zero
11166 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11167 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11168 subI_reg_reg(diff, src2s, src1s);
11169 // Need to consider >=33 bit result, therefore we need signmaskL.
11170 signmask64I_regI(sm, diff);
11171 andcI_reg_reg(doz, sm, m1, diff); // >=0
11172 addI_reg_reg(dst, doz, src1s);
11173 %}
11174 %}
11175
11176 //---------- Population Count Instructions ------------------------------------
11177
11178 // Popcnt for Power7.
11179 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11180 match(Set dst (PopCountI src));
11181 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11182 ins_cost(DEFAULT_COST);
11183
11184 format %{ "POPCNTW $dst, $src" %}
11185 size(4);
11186 ins_encode %{
11187 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11188 __ popcntw($dst$$Register, $src$$Register);
11189 %}
11190 ins_pipe(pipe_class_default);
11191 %}
11192
11193 // Popcnt for Power7.
11194 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11195 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11196 match(Set dst (PopCountL src));
11197 ins_cost(DEFAULT_COST);
11198
11199 format %{ "POPCNTD $dst, $src" %}
11200 size(4);
11201 ins_encode %{
11202 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11203 __ popcntd($dst$$Register, $src$$Register);
11204 %}
11205 ins_pipe(pipe_class_default);
11206 %}
11207
11208 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11209 match(Set dst (CountLeadingZerosI src));
11210 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11211 ins_cost(DEFAULT_COST);
11212
11213 format %{ "CNTLZW $dst, $src" %}
11214 size(4);
11215 ins_encode %{
11216 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11217 __ cntlzw($dst$$Register, $src$$Register);
11218 %}
11219 ins_pipe(pipe_class_default);
11220 %}
11221
11222 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11223 match(Set dst (CountLeadingZerosL src));
11224 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11225 ins_cost(DEFAULT_COST);
11226
11227 format %{ "CNTLZD $dst, $src" %}
11228 size(4);
11229 ins_encode %{
11230 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11231 __ cntlzd($dst$$Register, $src$$Register);
11232 %}
11233 ins_pipe(pipe_class_default);
11234 %}
11235
11236 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11237 // no match-rule, false predicate
11238 effect(DEF dst, USE src);
11239 predicate(false);
11240
11241 format %{ "CNTLZD $dst, $src" %}
11242 size(4);
11243 ins_encode %{
11244 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11245 __ cntlzd($dst$$Register, $src$$Register);
11246 %}
11247 ins_pipe(pipe_class_default);
11248 %}
11249
11250 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11251 match(Set dst (CountTrailingZerosI src));
11252 predicate(UseCountLeadingZerosInstructionsPPC64);
11253 ins_cost(DEFAULT_COST);
11254
11255 expand %{
11256 immI16 imm1 %{ (int)-1 %}
11257 immI16 imm2 %{ (int)32 %}
11258 immI_minus1 m1 %{ -1 %}
11259 iRegIdst tmpI1;
11260 iRegIdst tmpI2;
11261 iRegIdst tmpI3;
11262 addI_reg_imm16(tmpI1, src, imm1);
11263 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11264 countLeadingZerosI(tmpI3, tmpI2);
11265 subI_imm16_reg(dst, imm2, tmpI3);
11266 %}
11267 %}
11268
11269 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11270 match(Set dst (CountTrailingZerosL src));
11271 predicate(UseCountLeadingZerosInstructionsPPC64);
11272 ins_cost(DEFAULT_COST);
11273
11274 expand %{
11275 immL16 imm1 %{ (long)-1 %}
11276 immI16 imm2 %{ (int)64 %}
11277 iRegLdst tmpL1;
11278 iRegLdst tmpL2;
11279 iRegIdst tmpL3;
11280 addL_reg_imm16(tmpL1, src, imm1);
11281 andcL_reg_reg(tmpL2, tmpL1, src);
11282 countLeadingZerosL(tmpL3, tmpL2);
11283 subI_imm16_reg(dst, imm2, tmpL3);
11284 %}
11285 %}
11286
11287 // Expand nodes for byte_reverse_int.
11288 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11289 effect(DEF dst, USE src, USE pos, USE shift);
11290 predicate(false);
11291
11292 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11293 size(4);
11294 ins_encode %{
11295 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11296 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11297 %}
11298 ins_pipe(pipe_class_default);
11299 %}
11300
11301 // As insrwi_a, but with USE_DEF.
11302 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11303 effect(USE_DEF dst, USE src, USE pos, USE shift);
11304 predicate(false);
11305
11306 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11307 size(4);
11308 ins_encode %{
11309 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11310 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11311 %}
11312 ins_pipe(pipe_class_default);
11313 %}
11314
11315 // Just slightly faster than java implementation.
11316 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11317 match(Set dst (ReverseBytesI src));
11318 predicate(UseCountLeadingZerosInstructionsPPC64);
11319 ins_cost(DEFAULT_COST);
11320
11321 expand %{
11322 immI16 imm24 %{ (int) 24 %}
11323 immI16 imm16 %{ (int) 16 %}
11324 immI16 imm8 %{ (int) 8 %}
11325 immI16 imm4 %{ (int) 4 %}
11326 immI16 imm0 %{ (int) 0 %}
11327 iRegLdst tmpI1;
11328 iRegLdst tmpI2;
11329 iRegLdst tmpI3;
11330
11331 urShiftI_reg_imm(tmpI1, src, imm24);
11332 insrwi_a(dst, tmpI1, imm24, imm8);
11333 urShiftI_reg_imm(tmpI2, src, imm16);
11334 insrwi(dst, tmpI2, imm8, imm16);
11335 urShiftI_reg_imm(tmpI3, src, imm8);
11336 insrwi(dst, tmpI3, imm8, imm8);
11337 insrwi(dst, src, imm0, imm8);
11338 %}
11339 %}
11340
11341 //---------- Replicate Vector Instructions ------------------------------------
11342
11343 // Insrdi does replicate if src == dst.
11344 instruct repl32(iRegLdst dst) %{
11345 predicate(false);
11346 effect(USE_DEF dst);
11347
11348 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11349 size(4);
11350 ins_encode %{
11351 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11352 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11353 %}
11354 ins_pipe(pipe_class_default);
11355 %}
11356
11357 // Insrdi does replicate if src == dst.
11358 instruct repl48(iRegLdst dst) %{
11359 predicate(false);
11360 effect(USE_DEF dst);
11361
11362 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11363 size(4);
11364 ins_encode %{
11365 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11366 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11367 %}
11368 ins_pipe(pipe_class_default);
11369 %}
11370
11371 // Insrdi does replicate if src == dst.
11372 instruct repl56(iRegLdst dst) %{
11373 predicate(false);
11374 effect(USE_DEF dst);
11375
11376 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11377 size(4);
11378 ins_encode %{
11379 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11380 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11381 %}
11382 ins_pipe(pipe_class_default);
11383 %}
11384
11385 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11386 match(Set dst (ReplicateB src));
11387 predicate(n->as_Vector()->length() == 8);
11388 expand %{
11389 moveReg(dst, src);
11390 repl56(dst);
11391 repl48(dst);
11392 repl32(dst);
11393 %}
11394 %}
11395
11396 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11397 match(Set dst (ReplicateB zero));
11398 predicate(n->as_Vector()->length() == 8);
11399 format %{ "LI $dst, #0 \t// replicate8B" %}
11400 size(4);
11401 ins_encode %{
11402 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11403 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11404 %}
11405 ins_pipe(pipe_class_default);
11406 %}
11407
11408 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11409 match(Set dst (ReplicateB src));
11410 predicate(n->as_Vector()->length() == 8);
11411 format %{ "LI $dst, #-1 \t// replicate8B" %}
11412 size(4);
11413 ins_encode %{
11414 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11415 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11416 %}
11417 ins_pipe(pipe_class_default);
11418 %}
11419
11420 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11421 match(Set dst (ReplicateS src));
11422 predicate(n->as_Vector()->length() == 4);
11423 expand %{
11424 moveReg(dst, src);
11425 repl48(dst);
11426 repl32(dst);
11427 %}
11428 %}
11429
11430 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11431 match(Set dst (ReplicateS zero));
11432 predicate(n->as_Vector()->length() == 4);
11433 format %{ "LI $dst, #0 \t// replicate4C" %}
11434 size(4);
11435 ins_encode %{
11436 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11437 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11438 %}
11439 ins_pipe(pipe_class_default);
11440 %}
11441
11442 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11443 match(Set dst (ReplicateS src));
11444 predicate(n->as_Vector()->length() == 4);
11445 format %{ "LI $dst, -1 \t// replicate4C" %}
11446 size(4);
11447 ins_encode %{
11448 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11449 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11450 %}
11451 ins_pipe(pipe_class_default);
11452 %}
11453
11454 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11455 match(Set dst (ReplicateI src));
11456 predicate(n->as_Vector()->length() == 2);
11457 ins_cost(2 * DEFAULT_COST);
11458 expand %{
11459 moveReg(dst, src);
11460 repl32(dst);
11461 %}
11462 %}
11463
11464 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11465 match(Set dst (ReplicateI zero));
11466 predicate(n->as_Vector()->length() == 2);
11467 format %{ "LI $dst, #0 \t// replicate4C" %}
11468 size(4);
11469 ins_encode %{
11470 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11471 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11472 %}
11473 ins_pipe(pipe_class_default);
11474 %}
11475
11476 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11477 match(Set dst (ReplicateI src));
11478 predicate(n->as_Vector()->length() == 2);
11479 format %{ "LI $dst, -1 \t// replicate4C" %}
11480 size(4);
11481 ins_encode %{
11482 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11483 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11484 %}
11485 ins_pipe(pipe_class_default);
11486 %}
11487
11488 // Move float to int register via stack, replicate.
11489 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11490 match(Set dst (ReplicateF src));
11491 predicate(n->as_Vector()->length() == 2);
11492 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11493 expand %{
11494 stackSlotL tmpS;
11495 iRegIdst tmpI;
11496 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11497 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11498 moveReg(dst, tmpI); // Move int to long reg.
11499 repl32(dst); // Replicate bitpattern.
11500 %}
11501 %}
11502
11503 // Replicate scalar constant to packed float values in Double register
11504 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11505 match(Set dst (ReplicateF src));
11506 predicate(n->as_Vector()->length() == 2);
11507 ins_cost(5 * DEFAULT_COST);
11508
11509 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11510 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11511 %}
11512
11513 // Replicate scalar zero constant to packed float values in Double register
11514 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11515 match(Set dst (ReplicateF zero));
11516 predicate(n->as_Vector()->length() == 2);
11517
11518 format %{ "LI $dst, #0 \t// replicate2F" %}
11519 ins_encode %{
11520 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11521 __ li($dst$$Register, 0x0);
11522 %}
11523 ins_pipe(pipe_class_default);
11524 %}
11525
11526 // ============================================================================
11527 // Safepoint Instruction
11528
11529 instruct safePoint_poll(iRegPdst poll) %{
11530 match(SafePoint poll);
11531 predicate(LoadPollAddressFromThread);
11532
11533 // It caused problems to add the effect that r0 is killed, but this
11534 // effect no longer needs to be mentioned, since r0 is not contained
11535 // in a reg_class.
11536
11537 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11538 size(4);
11539 ins_encode( enc_poll(0x0, poll) );
11540 ins_pipe(pipe_class_default);
11541 %}
11542
11543 // Safepoint without per-thread support. Load address of page to poll
11544 // as constant.
11545 // Rscratch2RegP is R12.
11546 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11547 // a seperate node so that the oop map is at the right location.
11548 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11549 match(SafePoint poll);
11550 predicate(!LoadPollAddressFromThread);
11551
11552 // It caused problems to add the effect that r0 is killed, but this
11553 // effect no longer needs to be mentioned, since r0 is not contained
11554 // in a reg_class.
11555
11556 format %{ "LD R12, addr of polling page\n\t"
11557 "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11558 ins_encode( enc_poll(0x0, poll) );
11559 ins_pipe(pipe_class_default);
11560 %}
11561
11562 // ============================================================================
11563 // Call Instructions
11564
11565 // Call Java Static Instruction
11566
11567 // Schedulable version of call static node.
11568 instruct CallStaticJavaDirect(method meth) %{
11569 match(CallStaticJava);
11570 effect(USE meth);
11571 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11572 ins_cost(CALL_COST);
11573
11574 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11575
11576 format %{ "CALL,static $meth \t// ==> " %}
11577 size(4);
11578 ins_encode( enc_java_static_call(meth) );
11579 ins_pipe(pipe_class_call);
11580 %}
11581
11582 // Schedulable version of call static node.
11583 instruct CallStaticJavaDirectHandle(method meth) %{
11584 match(CallStaticJava);
11585 effect(USE meth);
11586 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11587 ins_cost(CALL_COST);
11588
11589 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11590
11591 format %{ "CALL,static $meth \t// ==> " %}
11592 ins_encode( enc_java_handle_call(meth) );
11593 ins_pipe(pipe_class_call);
11594 %}
11595
11596 // Call Java Dynamic Instruction
11597
11598 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11599 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11600 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11601 // The call destination must still be placed in the constant pool.
11602 instruct CallDynamicJavaDirectSched(method meth) %{
11603 match(CallDynamicJava); // To get all the data fields we need ...
11604 effect(USE meth);
11605 predicate(false); // ... but never match.
11606
11607 ins_field_load_ic_hi_node(loadConL_hiNode*);
11608 ins_field_load_ic_node(loadConLNode*);
11609 ins_num_consts(1 /* 1 patchable constant: call destination */);
11610
11611 format %{ "BL \t// dynamic $meth ==> " %}
11612 size(4);
11613 ins_encode( enc_java_dynamic_call_sched(meth) );
11614 ins_pipe(pipe_class_call);
11615 %}
11616
11617 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11618 // We use postalloc expanded calls if we use inline caches
11619 // and do not update method data.
11620 //
11621 // This instruction has two constants: inline cache (IC) and call destination.
11622 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11623 // one constant.
11624 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11625 match(CallDynamicJava);
11626 effect(USE meth);
11627 predicate(UseInlineCaches);
11628 ins_cost(CALL_COST);
11629
11630 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11631
11632 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11633 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11634 %}
11635
11636 // Compound version of call dynamic java
11637 // We use postalloc expanded calls if we use inline caches
11638 // and do not update method data.
11639 instruct CallDynamicJavaDirect(method meth) %{
11640 match(CallDynamicJava);
11641 effect(USE meth);
11642 predicate(!UseInlineCaches);
11643 ins_cost(CALL_COST);
11644
11645 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11646 ins_num_consts(4);
11647
11648 format %{ "CALL,dynamic $meth \t// ==> " %}
11649 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11650 ins_pipe(pipe_class_call);
11651 %}
11652
11653 // Call Runtime Instruction
11654
11655 instruct CallRuntimeDirect(method meth) %{
11656 match(CallRuntime);
11657 effect(USE meth);
11658 ins_cost(CALL_COST);
11659
11660 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11661 // env for callee, C-toc.
11662 ins_num_consts(3);
11663
11664 format %{ "CALL,runtime" %}
11665 ins_encode( enc_java_to_runtime_call(meth) );
11666 ins_pipe(pipe_class_call);
11667 %}
11668
11669 // Call Leaf
11670
11671 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11672 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11673 effect(DEF dst, USE src);
11674
11675 ins_num_consts(1);
11676
11677 format %{ "MTCTR $src" %}
11678 size(4);
11679 ins_encode( enc_leaf_call_mtctr(src) );
11680 ins_pipe(pipe_class_default);
11681 %}
11682
11683 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11684 instruct CallLeafDirect(method meth) %{
11685 match(CallLeaf); // To get the data all the data fields we need ...
11686 effect(USE meth);
11687 predicate(false); // but never match.
11688
11689 format %{ "BCTRL \t// leaf call $meth ==> " %}
11690 size(4);
11691 ins_encode %{
11692 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11693 __ bctrl();
11694 %}
11695 ins_pipe(pipe_class_call);
11696 %}
11697
11698 // postalloc expand of CallLeafDirect.
11699 // Load adress to call from TOC, then bl to it.
11700 instruct CallLeafDirect_Ex(method meth) %{
11701 match(CallLeaf);
11702 effect(USE meth);
11703 ins_cost(CALL_COST);
11704
11705 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11706 // env for callee, C-toc.
11707 ins_num_consts(3);
11708
11709 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11710 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11711 %}
11712
11713 // Call runtime without safepoint - same as CallLeaf.
11714 // postalloc expand of CallLeafNoFPDirect.
11715 // Load adress to call from TOC, then bl to it.
11716 instruct CallLeafNoFPDirect_Ex(method meth) %{
11717 match(CallLeafNoFP);
11718 effect(USE meth);
11719 ins_cost(CALL_COST);
11720
11721 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11722 // env for callee, C-toc.
11723 ins_num_consts(3);
11724
11725 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11726 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11727 %}
11728
11729 // Tail Call; Jump from runtime stub to Java code.
11730 // Also known as an 'interprocedural jump'.
11731 // Target of jump will eventually return to caller.
11732 // TailJump below removes the return address.
11733 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11734 match(TailCall jump_target method_oop);
11735 ins_cost(CALL_COST);
11736
11737 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11738 "BCTR \t// tail call" %}
11739 size(8);
11740 ins_encode %{
11741 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11742 __ mtctr($jump_target$$Register);
11743 __ bctr();
11744 %}
11745 ins_pipe(pipe_class_call);
11746 %}
11747
11748 // Return Instruction
11749 instruct Ret() %{
11750 match(Return);
11751 format %{ "BLR \t// branch to link register" %}
11752 size(4);
11753 ins_encode %{
11754 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11755 // LR is restored in MachEpilogNode. Just do the RET here.
11756 __ blr();
11757 %}
11758 ins_pipe(pipe_class_default);
11759 %}
11760
11761 // Tail Jump; remove the return address; jump to target.
11762 // TailCall above leaves the return address around.
11763 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11764 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11765 // "restore" before this instruction (in Epilogue), we need to materialize it
11766 // in %i0.
11767 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11768 match(TailJump jump_target ex_oop);
11769 ins_cost(CALL_COST);
11770
11771 format %{ "LD R4_ARG2 = LR\n\t"
11772 "MTCTR $jump_target\n\t"
11773 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11774 size(12);
11775 ins_encode %{
11776 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11777 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11778 __ mtctr($jump_target$$Register);
11779 __ bctr();
11780 %}
11781 ins_pipe(pipe_class_call);
11782 %}
11783
11784 // Create exception oop: created by stack-crawling runtime code.
11785 // Created exception is now available to this handler, and is setup
11786 // just prior to jumping to this handler. No code emitted.
11787 instruct CreateException(rarg1RegP ex_oop) %{
11788 match(Set ex_oop (CreateEx));
11789 ins_cost(0);
11790
11791 format %{ " -- \t// exception oop; no code emitted" %}
11792 size(0);
11793 ins_encode( /*empty*/ );
11794 ins_pipe(pipe_class_default);
11795 %}
11796
11797 // Rethrow exception: The exception oop will come in the first
11798 // argument position. Then JUMP (not call) to the rethrow stub code.
11799 instruct RethrowException() %{
11800 match(Rethrow);
11801 ins_cost(CALL_COST);
11802
11803 format %{ "Jmp rethrow_stub" %}
11804 ins_encode %{
11805 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11806 cbuf.set_insts_mark();
11807 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11808 %}
11809 ins_pipe(pipe_class_call);
11810 %}
11811
11812 // Die now.
11813 instruct ShouldNotReachHere() %{
11814 match(Halt);
11815 ins_cost(CALL_COST);
11816
11817 format %{ "ShouldNotReachHere" %}
11818 size(4);
11819 ins_encode %{
11820 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11821 __ trap_should_not_reach_here();
11822 %}
11823 ins_pipe(pipe_class_default);
11824 %}
11825
11826 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11827 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11828 // Get a DEF on threadRegP, no costs, no encoding, use
11829 // 'ins_should_rematerialize(true)' to avoid spilling.
11830 instruct tlsLoadP(threadRegP dst) %{
11831 match(Set dst (ThreadLocal));
11832 ins_cost(0);
11833
11834 ins_should_rematerialize(true);
11835
11836 format %{ " -- \t// $dst=Thread::current(), empty" %}
11837 size(0);
11838 ins_encode( /*empty*/ );
11839 ins_pipe(pipe_class_empty);
11840 %}
11841
11842 //---Some PPC specific nodes---------------------------------------------------
11843
11844 // Stop a group.
11845 instruct endGroup() %{
11846 ins_cost(0);
11847
11848 ins_is_nop(true);
11849
11850 format %{ "End Bundle (ori r1, r1, 0)" %}
11851 size(4);
11852 ins_encode %{
11853 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11854 __ endgroup();
11855 %}
11856 ins_pipe(pipe_class_default);
11857 %}
11858
11859 // Nop instructions
11860
11861 instruct fxNop() %{
11862 ins_cost(0);
11863
11864 ins_is_nop(true);
11865
11866 format %{ "fxNop" %}
11867 size(4);
11868 ins_encode %{
11869 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11870 __ nop();
11871 %}
11872 ins_pipe(pipe_class_default);
11873 %}
11874
11875 instruct fpNop0() %{
11876 ins_cost(0);
11877
11878 ins_is_nop(true);
11879
11880 format %{ "fpNop0" %}
11881 size(4);
11882 ins_encode %{
11883 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11884 __ fpnop0();
11885 %}
11886 ins_pipe(pipe_class_default);
11887 %}
11888
11889 instruct fpNop1() %{
11890 ins_cost(0);
11891
11892 ins_is_nop(true);
11893
11894 format %{ "fpNop1" %}
11895 size(4);
11896 ins_encode %{
11897 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11898 __ fpnop1();
11899 %}
11900 ins_pipe(pipe_class_default);
11901 %}
11902
11903 instruct brNop0() %{
11904 ins_cost(0);
11905 size(4);
11906 format %{ "brNop0" %}
11907 ins_encode %{
11908 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11909 __ brnop0();
11910 %}
11911 ins_is_nop(true);
11912 ins_pipe(pipe_class_default);
11913 %}
11914
11915 instruct brNop1() %{
11916 ins_cost(0);
11917
11918 ins_is_nop(true);
11919
11920 format %{ "brNop1" %}
11921 size(4);
11922 ins_encode %{
11923 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11924 __ brnop1();
11925 %}
11926 ins_pipe(pipe_class_default);
11927 %}
11928
11929 instruct brNop2() %{
11930 ins_cost(0);
11931
11932 ins_is_nop(true);
11933
11934 format %{ "brNop2" %}
11935 size(4);
11936 ins_encode %{
11937 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11938 __ brnop2();
11939 %}
11940 ins_pipe(pipe_class_default);
11941 %}
11942
11943 //----------PEEPHOLE RULES-----------------------------------------------------
11944 // These must follow all instruction definitions as they use the names
11945 // defined in the instructions definitions.
11946 //
11947 // peepmatch ( root_instr_name [preceeding_instruction]* );
11948 //
11949 // peepconstraint %{
11950 // (instruction_number.operand_name relational_op instruction_number.operand_name
11951 // [, ...] );
11952 // // instruction numbers are zero-based using left to right order in peepmatch
11953 //
11954 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11955 // // provide an instruction_number.operand_name for each operand that appears
11956 // // in the replacement instruction's match rule
11957 //
11958 // ---------VM FLAGS---------------------------------------------------------
11959 //
11960 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11961 //
11962 // Each peephole rule is given an identifying number starting with zero and
11963 // increasing by one in the order seen by the parser. An individual peephole
11964 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11965 // on the command-line.
11966 //
11967 // ---------CURRENT LIMITATIONS----------------------------------------------
11968 //
11969 // Only match adjacent instructions in same basic block
11970 // Only equality constraints
11971 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11972 // Only one replacement instruction
11973 //
11974 // ---------EXAMPLE----------------------------------------------------------
11975 //
11976 // // pertinent parts of existing instructions in architecture description
11977 // instruct movI(eRegI dst, eRegI src) %{
11978 // match(Set dst (CopyI src));
11979 // %}
11980 //
11981 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
11982 // match(Set dst (AddI dst src));
11983 // effect(KILL cr);
11984 // %}
11985 //
11986 // // Change (inc mov) to lea
11987 // peephole %{
11988 // // increment preceeded by register-register move
11989 // peepmatch ( incI_eReg movI );
11990 // // require that the destination register of the increment
11991 // // match the destination register of the move
11992 // peepconstraint ( 0.dst == 1.dst );
11993 // // construct a replacement instruction that sets
11994 // // the destination to ( move's source register + one )
11995 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
11996 // %}
11997 //
11998 // Implementation no longer uses movX instructions since
11999 // machine-independent system no longer uses CopyX nodes.
12000 //
12001 // peephole %{
12002 // peepmatch ( incI_eReg movI );
12003 // peepconstraint ( 0.dst == 1.dst );
12004 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12005 // %}
12006 //
12007 // peephole %{
12008 // peepmatch ( decI_eReg movI );
12009 // peepconstraint ( 0.dst == 1.dst );
12010 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12011 // %}
12012 //
12013 // peephole %{
12014 // peepmatch ( addI_eReg_imm movI );
12015 // peepconstraint ( 0.dst == 1.dst );
12016 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12017 // %}
12018 //
12019 // peephole %{
12020 // peepmatch ( addP_eReg_imm movP );
12021 // peepconstraint ( 0.dst == 1.dst );
12022 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12023 // %}
12024
12025 // // Change load of spilled value to only a spill
12026 // instruct storeI(memory mem, eRegI src) %{
12027 // match(Set mem (StoreI mem src));
12028 // %}
12029 //
12030 // instruct loadI(eRegI dst, memory mem) %{
12031 // match(Set dst (LoadI mem));
12032 // %}
12033 //
12034 peephole %{
12035 peepmatch ( loadI storeI );
12036 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12037 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12038 %}
12039
12040 peephole %{
12041 peepmatch ( loadL storeL );
12042 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12043 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12044 %}
12045
12046 peephole %{
12047 peepmatch ( loadP storeP );
12048 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12049 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12050 %}
12051
12052 //----------SMARTSPILL RULES---------------------------------------------------
12053 // These must follow all instruction definitions as they use the names
12054 // defined in the instructions definitions.