1 //
2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2013 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
900
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
906
907 source %{
908
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
925
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
937
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
954
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
961
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
976
977 return false;
978 }
979
980 #define __ _masm.
981
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
984
985 // ****************************************************************************
986
987 // REQUIRED FUNCTIONALITY
988
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
992
993 // PPC port: Removed use of lazy constant construct.
994
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
999
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1005
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1016
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1024
1025 //=============================================================================
1026
1027 // condition code conversions
1028
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1032
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1036
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1040
1041 //=============================================================================
1042
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1046
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1050
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1054
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1058
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1062
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1066
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1071
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1075
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1079
1080 //=============================================================================
1081
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1087
1088 //=============================================================================
1089
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1095
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1101
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1105
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1109
1110 //=============================================================================
1111
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1116
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1121
1122 //=============================================================================
1123
1124 %} // interrupt source
1125
1126 source_hpp %{ // Header information of the source block.
1127
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1131
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1133
1134 class CallStubImpl {
1135
1136 public:
1137
1138 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1139
1140 // Size of call trampoline stub.
1141 // This doesn't need to be accurate to the byte, but it
1142 // must be larger than or equal to the real size of the stub.
1143 static uint size_call_trampoline() {
1144 return trampoline_stub_size;
1145 }
1146
1147 // number of relocations needed by a call trampoline stub
1148 static uint reloc_call_trampoline() {
1149 return 5;
1150 }
1151
1152 };
1153
1154 %} // end source_hpp
1155
1156 source %{
1157
1158 // Emit a trampoline stub for a call to a target which is too far away.
1159 //
1160 // code sequences:
1161 //
1162 // call-site:
1163 // branch-and-link to <destination> or <trampoline stub>
1164 //
1165 // Related trampoline stub for this call-site in the stub section:
1166 // load the call target from the constant pool
1167 // branch via CTR (LR/link still points to the call-site above)
1168
1169 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1170 // Start the stub.
1171 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1172 if (stub == NULL) {
1173 Compile::current()->env()->record_out_of_memory_failure();
1174 return;
1175 }
1176
1177 // For java_to_interp stubs we use R11_scratch1 as scratch register
1178 // and in call trampoline stubs we use R12_scratch2. This way we
1179 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1180 Register reg_scratch = R12_scratch2;
1181
1182 // Create a trampoline stub relocation which relates this trampoline stub
1183 // with the call instruction at insts_call_instruction_offset in the
1184 // instructions code-section.
1185 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1186 const int stub_start_offset = __ offset();
1187
1188 // Now, create the trampoline stub's code:
1189 // - load the TOC
1190 // - load the call target from the constant pool
1191 // - call
1192 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1193 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1194 __ mtctr(reg_scratch);
1195 __ bctr();
1196
1197 const address stub_start_addr = __ addr_at(stub_start_offset);
1198
1199 // FIXME: Assert that the trampoline stub can be identified and patched.
1200
1201 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1202 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1203 "encoded offset into the constant pool must match");
1204 // Trampoline_stub_size should be good.
1205 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1206 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1207
1208 // End the stub.
1209 __ end_a_stub();
1210 }
1211
1212 //=============================================================================
1213
1214 // Emit an inline branch-and-link call and a related trampoline stub.
1215 //
1216 // code sequences:
1217 //
1218 // call-site:
1219 // branch-and-link to <destination> or <trampoline stub>
1220 //
1221 // Related trampoline stub for this call-site in the stub section:
1222 // load the call target from the constant pool
1223 // branch via CTR (LR/link still points to the call-site above)
1224 //
1225
1226 typedef struct {
1227 int insts_call_instruction_offset;
1228 int ret_addr_offset;
1229 } EmitCallOffsets;
1230
1231 // Emit a branch-and-link instruction that branches to a trampoline.
1232 // - Remember the offset of the branch-and-link instruction.
1233 // - Add a relocation at the branch-and-link instruction.
1234 // - Emit a branch-and-link.
1235 // - Remember the return pc offset.
1236 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1237 EmitCallOffsets offsets = { -1, -1 };
1238 const int start_offset = __ offset();
1239 offsets.insts_call_instruction_offset = __ offset();
1240
1241 // No entry point given, use the current pc.
1242 if (entry_point == NULL) entry_point = __ pc();
1243
1244 if (!Compile::current()->in_scratch_emit_size()) {
1245 // Put the entry point as a constant into the constant pool.
1246 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1247 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1248
1249 // Emit the trampoline stub which will be related to the branch-and-link below.
1250 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1251 __ relocate(rtype);
1252 }
1253
1254 // Note: At this point we do not have the address of the trampoline
1255 // stub, and the entry point might be too far away for bl, so __ pc()
1256 // serves as dummy and the bl will be patched later.
1257 __ bl((address) __ pc());
1258
1259 offsets.ret_addr_offset = __ offset() - start_offset;
1260
1261 return offsets;
1262 }
1263
1264 //=============================================================================
1265
1266 // Factory for creating loadConL* nodes for large/small constant pool.
1267
1268 static inline jlong replicate_immF(float con) {
1269 // Replicate float con 2 times and pack into vector.
1270 int val = *((int*)&con);
1271 jlong lval = val;
1272 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1273 return lval;
1274 }
1275
1276 //=============================================================================
1277
1278 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1279 int Compile::ConstantTable::calculate_table_base_offset() const {
1280 return 0; // absolute addressing, no offset
1281 }
1282
1283 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1284 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1285 Compile *C = ra_->C;
1286
1287 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1288 MachNode *m1 = new (C) loadToc_hiNode();
1289 MachNode *m2 = new (C) loadToc_loNode();
1290
1291 m1->add_req(NULL);
1292 m2->add_req(NULL, m1);
1293 m1->_opnds[0] = op_dst;
1294 m2->_opnds[0] = op_dst;
1295 m2->_opnds[1] = op_dst;
1296 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1297 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1298 nodes->push(m1);
1299 nodes->push(m2);
1300 }
1301
1302 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1303 // Is postalloc expanded.
1304 ShouldNotReachHere();
1305 }
1306
1307 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1308 return 0;
1309 }
1310
1311 #ifndef PRODUCT
1312 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1313 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1314 }
1315 #endif
1316
1317 //=============================================================================
1318
1319 #ifndef PRODUCT
1320 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1321 Compile* C = ra_->C;
1322 const long framesize = C->frame_slots() << LogBytesPerInt;
1323
1324 st->print("PROLOG\n\t");
1325 if (C->need_stack_bang(framesize)) {
1326 st->print("stack_overflow_check\n\t");
1327 }
1328
1329 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1330 st->print("save return pc\n\t");
1331 st->print("push frame %d\n\t", -framesize);
1332 }
1333 }
1334 #endif
1335
1336 // Macro used instead of the common __ to emulate the pipes of PPC.
1337 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1338 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1339 // still no scheduling of this code is possible, the micro scheduler is aware of the
1340 // code and can update its internal data. The following mechanism is used to achieve this:
1341 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1342 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1343 #if 0 // TODO: PPC port
1344 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1345 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1346 _masm.
1347 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1348 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1349 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1350 C->hb_scheduling()->_pdScheduling->advance_offset
1351 #else
1352 #define ___(op) if (UsePower6SchedulerPPC64) \
1353 Unimplemented(); \
1354 _masm.
1355 #define ___stop if (UsePower6SchedulerPPC64) \
1356 Unimplemented()
1357 #define ___advance if (UsePower6SchedulerPPC64) \
1358 Unimplemented()
1359 #endif
1360
1361 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1362 Compile* C = ra_->C;
1363 MacroAssembler _masm(&cbuf);
1364
1365 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1366 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1367
1368 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1369
1370 const Register return_pc = R20; // Must match return_addr() in frame section.
1371 const Register callers_sp = R21;
1372 const Register push_frame_temp = R22;
1373 const Register toc_temp = R23;
1374 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1375
1376 if (method_is_frameless) {
1377 // Add nop at beginning of all frameless methods to prevent any
1378 // oop instructions from getting overwritten by make_not_entrant
1379 // (patching attempt would fail).
1380 ___(nop) nop();
1381 } else {
1382 // Get return pc.
1383 ___(mflr) mflr(return_pc);
1384 }
1385
1386 // Calls to C2R adapters often do not accept exceptional returns.
1387 // We require that their callers must bang for them. But be
1388 // careful, because some VM calls (such as call site linkage) can
1389 // use several kilobytes of stack. But the stack safety zone should
1390 // account for that. See bugs 4446381, 4468289, 4497237.
1391 if (C->need_stack_bang(framesize) && UseStackBanging) {
1392 // Unfortunately we cannot use the function provided in
1393 // assembler.cpp as we have to emulate the pipes. So I had to
1394 // insert the code of generate_stack_overflow_check(), see
1395 // assembler.cpp for some illuminative comments.
1396 const int page_size = os::vm_page_size();
1397 int bang_end = StackShadowPages*page_size;
1398
1399 // This is how far the previous frame's stack banging extended.
1400 const int bang_end_safe = bang_end;
1401
1402 if (framesize > page_size) {
1403 bang_end += framesize;
1404 }
1405
1406 int bang_offset = bang_end_safe;
1407
1408 while (bang_offset <= bang_end) {
1409 // Need at least one stack bang at end of shadow zone.
1410
1411 // Again I had to copy code, this time from assembler_ppc64.cpp,
1412 // bang_stack_with_offset - see there for comments.
1413
1414 // Stack grows down, caller passes positive offset.
1415 assert(bang_offset > 0, "must bang with positive offset");
1416
1417 long stdoffset = -bang_offset;
1418
1419 if (Assembler::is_simm(stdoffset, 16)) {
1420 // Signed 16 bit offset, a simple std is ok.
1421 if (UseLoadInstructionsForStackBangingPPC64) {
1422 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1423 } else {
1424 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1425 }
1426 } else if (Assembler::is_simm(stdoffset, 31)) {
1427 // Use largeoffset calculations for addis & ld/std.
1428 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1429 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1430
1431 Register tmp = R11;
1432 ___(addis) addis(tmp, R1_SP, hi);
1433 if (UseLoadInstructionsForStackBangingPPC64) {
1434 ___(ld) ld(R0, lo, tmp);
1435 } else {
1436 ___(std) std(R0, lo, tmp);
1437 }
1438 } else {
1439 ShouldNotReachHere();
1440 }
1441
1442 bang_offset += page_size;
1443 }
1444 // R11 trashed
1445 } // C->need_stack_bang(framesize) && UseStackBanging
1446
1447 unsigned int bytes = (unsigned int)framesize;
1448 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1449 ciMethod *currMethod = C -> method();
1450
1451 // Optimized version for most common case.
1452 if (UsePower6SchedulerPPC64 &&
1453 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1454 !(false /* ConstantsALot TODO: PPC port*/)) {
1455 ___(or) mr(callers_sp, R1_SP);
1456 ___(std) std(return_pc, _abi(lr), R1_SP);
1457 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1458 return;
1459 }
1460
1461 if (!method_is_frameless) {
1462 // Get callers sp.
1463 ___(or) mr(callers_sp, R1_SP);
1464
1465 // Push method's frame, modifies SP.
1466 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1467 // The ABI is already accounted for in 'framesize' via the
1468 // 'out_preserve' area.
1469 Register tmp = push_frame_temp;
1470 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1471 if (Assembler::is_simm(-offset, 16)) {
1472 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1473 } else {
1474 long x = -offset;
1475 // Had to insert load_const(tmp, -offset).
1476 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1477 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1478 ___(rldicr) sldi(tmp, tmp, 32);
1479 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1480 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1481
1482 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1483 }
1484 }
1485 #if 0 // TODO: PPC port
1486 // For testing large constant pools, emit a lot of constants to constant pool.
1487 // "Randomize" const_size.
1488 if (ConstantsALot) {
1489 const int num_consts = const_size();
1490 for (int i = 0; i < num_consts; i++) {
1491 __ long_constant(0xB0B5B00BBABE);
1492 }
1493 }
1494 #endif
1495 if (!method_is_frameless) {
1496 // Save return pc.
1497 ___(std) std(return_pc, _abi(lr), callers_sp);
1498 }
1499 }
1500 #undef ___
1501 #undef ___stop
1502 #undef ___advance
1503
1504 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1505 // Variable size. determine dynamically.
1506 return MachNode::size(ra_);
1507 }
1508
1509 int MachPrologNode::reloc() const {
1510 // Return number of relocatable values contained in this instruction.
1511 return 1; // 1 reloc entry for load_const(toc).
1512 }
1513
1514 //=============================================================================
1515
1516 #ifndef PRODUCT
1517 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1518 Compile* C = ra_->C;
1519
1520 st->print("EPILOG\n\t");
1521 st->print("restore return pc\n\t");
1522 st->print("pop frame\n\t");
1523
1524 if (do_polling() && C->is_method_compilation()) {
1525 st->print("touch polling page\n\t");
1526 }
1527 }
1528 #endif
1529
1530 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1531 Compile* C = ra_->C;
1532 MacroAssembler _masm(&cbuf);
1533
1534 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1535 assert(framesize >= 0, "negative frame-size?");
1536
1537 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1538 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1539 const Register return_pc = R11;
1540 const Register polling_page = R12;
1541
1542 if (!method_is_frameless) {
1543 // Restore return pc relative to callers' sp.
1544 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1545 }
1546
1547 if (method_needs_polling) {
1548 if (LoadPollAddressFromThread) {
1549 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1550 Unimplemented();
1551 } else {
1552 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1553 }
1554 }
1555
1556 if (!method_is_frameless) {
1557 // Move return pc to LR.
1558 __ mtlr(return_pc);
1559 // Pop frame (fixed frame-size).
1560 __ addi(R1_SP, R1_SP, (int)framesize);
1561 }
1562
1563 if (method_needs_polling) {
1564 // We need to mark the code position where the load from the safepoint
1565 // polling page was emitted as relocInfo::poll_return_type here.
1566 __ relocate(relocInfo::poll_return_type);
1567 __ load_from_polling_page(polling_page);
1568 }
1569 }
1570
1571 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1572 // Variable size. Determine dynamically.
1573 return MachNode::size(ra_);
1574 }
1575
1576 int MachEpilogNode::reloc() const {
1577 // Return number of relocatable values contained in this instruction.
1578 return 1; // 1 for load_from_polling_page.
1579 }
1580
1581 const Pipeline * MachEpilogNode::pipeline() const {
1582 return MachNode::pipeline_class();
1583 }
1584
1585 // This method seems to be obsolete. It is declared in machnode.hpp
1586 // and defined in all *.ad files, but it is never called. Should we
1587 // get rid of it?
1588 int MachEpilogNode::safepoint_offset() const {
1589 assert(do_polling(), "no return for this epilog node");
1590 return 0;
1591 }
1592
1593 #if 0 // TODO: PPC port
1594 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1595 MacroAssembler _masm(&cbuf);
1596 if (LoadPollAddressFromThread) {
1597 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1598 } else {
1599 _masm.nop();
1600 }
1601 }
1602
1603 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1604 if (LoadPollAddressFromThread) {
1605 return 4;
1606 } else {
1607 return 4;
1608 }
1609 }
1610
1611 #ifndef PRODUCT
1612 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1613 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1614 }
1615 #endif
1616
1617 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1618 return RSCRATCH1_BITS64_REG_mask();
1619 }
1620 #endif // PPC port
1621
1622 // =============================================================================
1623
1624 // Figure out which register class each belongs in: rc_int, rc_float or
1625 // rc_stack.
1626 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1627
1628 static enum RC rc_class(OptoReg::Name reg) {
1629 // Return the register class for the given register. The given register
1630 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1631 // enumeration in adGlobals_ppc64.hpp.
1632
1633 if (reg == OptoReg::Bad) return rc_bad;
1634
1635 // We have 64 integer register halves, starting at index 0.
1636 if (reg < 64) return rc_int;
1637
1638 // We have 64 floating-point register halves, starting at index 64.
1639 if (reg < 64+64) return rc_float;
1640
1641 // Between float regs & stack are the flags regs.
1642 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1643
1644 return rc_stack;
1645 }
1646
1647 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1648 bool do_print, Compile* C, outputStream *st) {
1649
1650 assert(opcode == Assembler::LD_OPCODE ||
1651 opcode == Assembler::STD_OPCODE ||
1652 opcode == Assembler::LWZ_OPCODE ||
1653 opcode == Assembler::STW_OPCODE ||
1654 opcode == Assembler::LFD_OPCODE ||
1655 opcode == Assembler::STFD_OPCODE ||
1656 opcode == Assembler::LFS_OPCODE ||
1657 opcode == Assembler::STFS_OPCODE,
1658 "opcode not supported");
1659
1660 if (cbuf) {
1661 int d =
1662 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1663 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1664 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1665 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1666 }
1667 #ifndef PRODUCT
1668 else if (do_print) {
1669 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1670 op_str,
1671 Matcher::regName[reg],
1672 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1673 }
1674 #endif
1675 return 4; // size
1676 }
1677
1678 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1679 Compile* C = ra_->C;
1680
1681 // Get registers to move.
1682 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1683 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1684 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1685 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1686
1687 enum RC src_hi_rc = rc_class(src_hi);
1688 enum RC src_lo_rc = rc_class(src_lo);
1689 enum RC dst_hi_rc = rc_class(dst_hi);
1690 enum RC dst_lo_rc = rc_class(dst_lo);
1691
1692 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1693 if (src_hi != OptoReg::Bad)
1694 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1695 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1696 "expected aligned-adjacent pairs");
1697 // Generate spill code!
1698 int size = 0;
1699
1700 if (src_lo == dst_lo && src_hi == dst_hi)
1701 return size; // Self copy, no move.
1702
1703 // --------------------------------------
1704 // Memory->Memory Spill. Use R0 to hold the value.
1705 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1706 int src_offset = ra_->reg2offset(src_lo);
1707 int dst_offset = ra_->reg2offset(dst_lo);
1708 if (src_hi != OptoReg::Bad) {
1709 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1710 "expected same type of move for high parts");
1711 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1712 if (!cbuf && !do_size) st->print("\n\t");
1713 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1714 } else {
1715 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1716 if (!cbuf && !do_size) st->print("\n\t");
1717 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1718 }
1719 return size;
1720 }
1721
1722 // --------------------------------------
1723 // Check for float->int copy; requires a trip through memory.
1724 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1725 Unimplemented();
1726 }
1727
1728 // --------------------------------------
1729 // Check for integer reg-reg copy.
1730 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1731 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1732 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1733 size = (Rsrc != Rdst) ? 4 : 0;
1734
1735 if (cbuf) {
1736 MacroAssembler _masm(cbuf);
1737 if (size) {
1738 __ mr(Rdst, Rsrc);
1739 }
1740 }
1741 #ifndef PRODUCT
1742 else if (!do_size) {
1743 if (size) {
1744 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1745 } else {
1746 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1747 }
1748 }
1749 #endif
1750 return size;
1751 }
1752
1753 // Check for integer store.
1754 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1755 int dst_offset = ra_->reg2offset(dst_lo);
1756 if (src_hi != OptoReg::Bad) {
1757 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1758 "expected same type of move for high parts");
1759 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1760 } else {
1761 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1762 }
1763 return size;
1764 }
1765
1766 // Check for integer load.
1767 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1768 int src_offset = ra_->reg2offset(src_lo);
1769 if (src_hi != OptoReg::Bad) {
1770 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1771 "expected same type of move for high parts");
1772 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1773 } else {
1774 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1775 }
1776 return size;
1777 }
1778
1779 // Check for float reg-reg copy.
1780 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1781 if (cbuf) {
1782 MacroAssembler _masm(cbuf);
1783 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1784 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1785 __ fmr(Rdst, Rsrc);
1786 }
1787 #ifndef PRODUCT
1788 else if (!do_size) {
1789 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1790 }
1791 #endif
1792 return 4;
1793 }
1794
1795 // Check for float store.
1796 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1797 int dst_offset = ra_->reg2offset(dst_lo);
1798 if (src_hi != OptoReg::Bad) {
1799 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1800 "expected same type of move for high parts");
1801 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1802 } else {
1803 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1804 }
1805 return size;
1806 }
1807
1808 // Check for float load.
1809 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1810 int src_offset = ra_->reg2offset(src_lo);
1811 if (src_hi != OptoReg::Bad) {
1812 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1813 "expected same type of move for high parts");
1814 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1815 } else {
1816 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1817 }
1818 return size;
1819 }
1820
1821 // --------------------------------------------------------------------
1822 // Check for hi bits still needing moving. Only happens for misaligned
1823 // arguments to native calls.
1824 if (src_hi == dst_hi)
1825 return size; // Self copy; no move.
1826
1827 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1828 ShouldNotReachHere(); // Unimplemented
1829 return 0;
1830 }
1831
1832 #ifndef PRODUCT
1833 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1834 if (!ra_)
1835 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1836 else
1837 implementation(NULL, ra_, false, st);
1838 }
1839 #endif
1840
1841 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1842 implementation(&cbuf, ra_, false, NULL);
1843 }
1844
1845 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1846 return implementation(NULL, ra_, true, NULL);
1847 }
1848
1849 #if 0 // TODO: PPC port
1850 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1851 #ifndef PRODUCT
1852 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1853 #endif
1854 assert(ra_->node_regs_max_index() != 0, "");
1855
1856 // Get registers to move.
1857 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1858 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1859 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1860 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1861
1862 enum RC src_lo_rc = rc_class(src_lo);
1863 enum RC dst_lo_rc = rc_class(dst_lo);
1864
1865 if (src_lo == dst_lo && src_hi == dst_hi)
1866 return ppc64Opcode_none; // Self copy, no move.
1867
1868 // --------------------------------------
1869 // Memory->Memory Spill. Use R0 to hold the value.
1870 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1871 return ppc64Opcode_compound;
1872 }
1873
1874 // --------------------------------------
1875 // Check for float->int copy; requires a trip through memory.
1876 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1877 Unimplemented();
1878 }
1879
1880 // --------------------------------------
1881 // Check for integer reg-reg copy.
1882 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1883 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1884 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1885 if (Rsrc == Rdst) {
1886 return ppc64Opcode_none;
1887 } else {
1888 return ppc64Opcode_or;
1889 }
1890 }
1891
1892 // Check for integer store.
1893 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1894 if (src_hi != OptoReg::Bad) {
1895 return ppc64Opcode_std;
1896 } else {
1897 return ppc64Opcode_stw;
1898 }
1899 }
1900
1901 // Check for integer load.
1902 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1903 if (src_hi != OptoReg::Bad) {
1904 return ppc64Opcode_ld;
1905 } else {
1906 return ppc64Opcode_lwz;
1907 }
1908 }
1909
1910 // Check for float reg-reg copy.
1911 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1912 return ppc64Opcode_fmr;
1913 }
1914
1915 // Check for float store.
1916 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1917 if (src_hi != OptoReg::Bad) {
1918 return ppc64Opcode_stfd;
1919 } else {
1920 return ppc64Opcode_stfs;
1921 }
1922 }
1923
1924 // Check for float load.
1925 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1926 if (src_hi != OptoReg::Bad) {
1927 return ppc64Opcode_lfd;
1928 } else {
1929 return ppc64Opcode_lfs;
1930 }
1931 }
1932
1933 // --------------------------------------------------------------------
1934 // Check for hi bits still needing moving. Only happens for misaligned
1935 // arguments to native calls.
1936 if (src_hi == dst_hi)
1937 return ppc64Opcode_none; // Self copy; no move.
1938
1939 ShouldNotReachHere();
1940 return ppc64Opcode_undefined;
1941 }
1942 #endif // PPC port
1943
1944 #ifndef PRODUCT
1945 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1946 st->print("NOP \t// %d nops to pad for loops.", _count);
1947 }
1948 #endif
1949
1950 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1951 MacroAssembler _masm(&cbuf);
1952 // _count contains the number of nops needed for padding.
1953 for (int i = 0; i < _count; i++) {
1954 __ nop();
1955 }
1956 }
1957
1958 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1959 return _count * 4;
1960 }
1961
1962 #ifndef PRODUCT
1963 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1964 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1965 int reg = ra_->get_reg_first(this);
1966 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1967 }
1968 #endif
1969
1970 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1971 MacroAssembler _masm(&cbuf);
1972
1973 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1974 int reg = ra_->get_encode(this);
1975
1976 if (Assembler::is_simm(offset, 16)) {
1977 __ addi(as_Register(reg), R1, offset);
1978 } else {
1979 ShouldNotReachHere();
1980 }
1981 }
1982
1983 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1984 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1985 return 4;
1986 }
1987
1988 #ifndef PRODUCT
1989 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1990 st->print_cr("---- MachUEPNode ----");
1991 st->print_cr("...");
1992 }
1993 #endif
1994
1995 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1996 // This is the unverified entry point.
1997 MacroAssembler _masm(&cbuf);
1998
1999 // Inline_cache contains a klass.
2000 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2001 Register receiver_klass = R0; // tmp
2002
2003 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2004 assert(R11_scratch1 == R11, "need prologue scratch register");
2005
2006 // Check for NULL argument if we don't have implicit null checks.
2007 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2008 if (TrapBasedNullChecks) {
2009 __ trap_null_check(R3_ARG1);
2010 } else {
2011 Label valid;
2012 __ cmpdi(CCR0, R3_ARG1, 0);
2013 __ bne_predict_taken(CCR0, valid);
2014 // We have a null argument, branch to ic_miss_stub.
2015 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2016 relocInfo::runtime_call_type);
2017 __ bind(valid);
2018 }
2019 }
2020 // Assume argument is not NULL, load klass from receiver.
2021 __ load_klass(receiver_klass, R3_ARG1);
2022
2023 if (TrapBasedICMissChecks) {
2024 __ trap_ic_miss_check(receiver_klass, ic_klass);
2025 } else {
2026 Label valid;
2027 __ cmpd(CCR0, receiver_klass, ic_klass);
2028 __ beq_predict_taken(CCR0, valid);
2029 // We have an unexpected klass, branch to ic_miss_stub.
2030 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2031 relocInfo::runtime_call_type);
2032 __ bind(valid);
2033 }
2034
2035 // Argument is valid and klass is as expected, continue.
2036 }
2037
2038 #if 0 // TODO: PPC port
2039 // Optimize UEP code on z (save a load_const() call in main path).
2040 int MachUEPNode::ep_offset() {
2041 return 0;
2042 }
2043 #endif
2044
2045 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2046 // Variable size. Determine dynamically.
2047 return MachNode::size(ra_);
2048 }
2049
2050 //=============================================================================
2051
2052 %} // interrupt source
2053
2054 source_hpp %{ // Header information of the source block.
2055
2056 class HandlerImpl {
2057
2058 public:
2059
2060 static int emit_exception_handler(CodeBuffer &cbuf);
2061 static int emit_deopt_handler(CodeBuffer& cbuf);
2062
2063 static uint size_exception_handler() {
2064 // The exception_handler is a b64_patchable.
2065 return MacroAssembler::b64_patchable_size;
2066 }
2067
2068 static uint size_deopt_handler() {
2069 // The deopt_handler is a bl64_patchable.
2070 return MacroAssembler::bl64_patchable_size;
2071 }
2072
2073 };
2074
2075 %} // end source_hpp
2076
2077 source %{
2078
2079 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2080 MacroAssembler _masm(&cbuf);
2081
2082 address base = __ start_a_stub(size_exception_handler());
2083 if (base == NULL) return 0; // CodeBuffer::expand failed
2084
2085 int offset = __ offset();
2086 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2087 relocInfo::runtime_call_type);
2088 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2089 __ end_a_stub();
2090
2091 return offset;
2092 }
2093
2094 // The deopt_handler is like the exception handler, but it calls to
2095 // the deoptimization blob instead of jumping to the exception blob.
2096 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2097 MacroAssembler _masm(&cbuf);
2098
2099 address base = __ start_a_stub(size_deopt_handler());
2100 if (base == NULL) return 0; // CodeBuffer::expand failed
2101
2102 int offset = __ offset();
2103 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2104 relocInfo::runtime_call_type);
2105 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2106 __ end_a_stub();
2107
2108 return offset;
2109 }
2110
2111 //=============================================================================
2112
2113 // Use a frame slots bias for frameless methods if accessing the stack.
2114 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2115 if (as_Register(reg_enc) == R1_SP) {
2116 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2117 }
2118 return 0;
2119 }
2120
2121 const bool Matcher::match_rule_supported(int opcode) {
2122 if (!has_match_rule(opcode))
2123 return false;
2124
2125 switch (opcode) {
2126 case Op_SqrtD:
2127 return VM_Version::has_fsqrt();
2128 case Op_CountLeadingZerosI:
2129 case Op_CountLeadingZerosL:
2130 case Op_CountTrailingZerosI:
2131 case Op_CountTrailingZerosL:
2132 if (!UseCountLeadingZerosInstructionsPPC64)
2133 return false;
2134 break;
2135
2136 case Op_PopCountI:
2137 case Op_PopCountL:
2138 return (UsePopCountInstruction && VM_Version::has_popcntw());
2139
2140 case Op_StrComp:
2141 return SpecialStringCompareTo;
2142 case Op_StrEquals:
2143 return SpecialStringEquals;
2144 case Op_StrIndexOf:
2145 return SpecialStringIndexOf;
2146 }
2147
2148 return true; // Per default match rules are supported.
2149 }
2150
2151 int Matcher::regnum_to_fpu_offset(int regnum) {
2152 // No user for this method?
2153 Unimplemented();
2154 return 999;
2155 }
2156
2157 const bool Matcher::convL2FSupported(void) {
2158 // fcfids can do the conversion (>= Power7).
2159 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2160 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2161 }
2162
2163 // Vector width in bytes.
2164 const int Matcher::vector_width_in_bytes(BasicType bt) {
2165 assert(MaxVectorSize == 8, "");
2166 return 8;
2167 }
2168
2169 // Vector ideal reg.
2170 const int Matcher::vector_ideal_reg(int size) {
2171 assert(MaxVectorSize == 8 && size == 8, "");
2172 return Op_RegL;
2173 }
2174
2175 const int Matcher::vector_shift_count_ideal_reg(int size) {
2176 fatal("vector shift is not supported");
2177 return Node::NotAMachineReg;
2178 }
2179
2180 // Limits on vector size (number of elements) loaded into vector.
2181 const int Matcher::max_vector_size(const BasicType bt) {
2182 assert(is_java_primitive(bt), "only primitive type vectors");
2183 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2184 }
2185
2186 const int Matcher::min_vector_size(const BasicType bt) {
2187 return max_vector_size(bt); // Same as max.
2188 }
2189
2190 // PPC doesn't support misaligned vectors store/load.
2191 const bool Matcher::misaligned_vectors_ok() {
2192 return false;
2193 }
2194
2195 // PPC AES support not yet implemented
2196 const bool Matcher::pass_original_key_for_aes() {
2197 return false;
2198 }
2199
2200 // RETURNS: whether this branch offset is short enough that a short
2201 // branch can be used.
2202 //
2203 // If the platform does not provide any short branch variants, then
2204 // this method should return `false' for offset 0.
2205 //
2206 // `Compile::Fill_buffer' will decide on basis of this information
2207 // whether to do the pass `Compile::Shorten_branches' at all.
2208 //
2209 // And `Compile::Shorten_branches' will decide on basis of this
2210 // information whether to replace particular branch sites by short
2211 // ones.
2212 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2213 // Is the offset within the range of a ppc64 pc relative branch?
2214 bool b;
2215
2216 const int safety_zone = 3 * BytesPerInstWord;
2217 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2218 29 - 16 + 1 + 2);
2219 return b;
2220 }
2221
2222 const bool Matcher::isSimpleConstant64(jlong value) {
2223 // Probably always true, even if a temp register is required.
2224 return true;
2225 }
2226 /* TODO: PPC port
2227 // Make a new machine dependent decode node (with its operands).
2228 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2229 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2230 "This method is only implemented for unscaled cOops mode so far");
2231 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2232 decode->set_opnd_array(0, new (C) iRegPdstOper());
2233 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2234 return decode;
2235 }
2236 */
2237 // Threshold size for cleararray.
2238 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2239
2240 // false => size gets scaled to BytesPerLong, ok.
2241 const bool Matcher::init_array_count_is_in_bytes = false;
2242
2243 // Use conditional move (CMOVL) on Power7.
2244 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2245
2246 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2247 // fsel doesn't accept a condition register as input, so this would be slightly different.
2248 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2249
2250 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2251 const bool Matcher::require_postalloc_expand = true;
2252
2253 // Should the Matcher clone shifts on addressing modes, expecting them to
2254 // be subsumed into complex addressing expressions or compute them into
2255 // registers? True for Intel but false for most RISCs.
2256 const bool Matcher::clone_shift_expressions = false;
2257
2258 // Do we need to mask the count passed to shift instructions or does
2259 // the cpu only look at the lower 5/6 bits anyway?
2260 // Off, as masks are generated in expand rules where required.
2261 // Constant shift counts are handled in Ideal phase.
2262 const bool Matcher::need_masked_shift_count = false;
2263
2264 // This affects two different things:
2265 // - how Decode nodes are matched
2266 // - how ImplicitNullCheck opportunities are recognized
2267 // If true, the matcher will try to remove all Decodes and match them
2268 // (as operands) into nodes. NullChecks are not prepared to deal with
2269 // Decodes by final_graph_reshaping().
2270 // If false, final_graph_reshaping() forces the decode behind the Cmp
2271 // for a NullCheck. The matcher matches the Decode node into a register.
2272 // Implicit_null_check optimization moves the Decode along with the
2273 // memory operation back up before the NullCheck.
2274 bool Matcher::narrow_oop_use_complex_address() {
2275 // TODO: PPC port if (MatchDecodeNodes) return true;
2276 return false;
2277 }
2278
2279 bool Matcher::narrow_klass_use_complex_address() {
2280 NOT_LP64(ShouldNotCallThis());
2281 assert(UseCompressedClassPointers, "only for compressed klass code");
2282 // TODO: PPC port if (MatchDecodeNodes) return true;
2283 return false;
2284 }
2285
2286 // Is it better to copy float constants, or load them directly from memory?
2287 // Intel can load a float constant from a direct address, requiring no
2288 // extra registers. Most RISCs will have to materialize an address into a
2289 // register first, so they would do better to copy the constant from stack.
2290 const bool Matcher::rematerialize_float_constants = false;
2291
2292 // If CPU can load and store mis-aligned doubles directly then no fixup is
2293 // needed. Else we split the double into 2 integer pieces and move it
2294 // piece-by-piece. Only happens when passing doubles into C code as the
2295 // Java calling convention forces doubles to be aligned.
2296 const bool Matcher::misaligned_doubles_ok = true;
2297
2298 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2299 Unimplemented();
2300 }
2301
2302 // Advertise here if the CPU requires explicit rounding operations
2303 // to implement the UseStrictFP mode.
2304 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2305
2306 // Do floats take an entire double register or just half?
2307 //
2308 // A float occupies a ppc64 double register. For the allocator, a
2309 // ppc64 double register appears as a pair of float registers.
2310 bool Matcher::float_in_double() { return true; }
2311
2312 // Do ints take an entire long register or just half?
2313 // The relevant question is how the int is callee-saved:
2314 // the whole long is written but de-opt'ing will have to extract
2315 // the relevant 32 bits.
2316 const bool Matcher::int_in_long = true;
2317
2318 // Constants for c2c and c calling conventions.
2319
2320 const MachRegisterNumbers iarg_reg[8] = {
2321 R3_num, R4_num, R5_num, R6_num,
2322 R7_num, R8_num, R9_num, R10_num
2323 };
2324
2325 const MachRegisterNumbers farg_reg[13] = {
2326 F1_num, F2_num, F3_num, F4_num,
2327 F5_num, F6_num, F7_num, F8_num,
2328 F9_num, F10_num, F11_num, F12_num,
2329 F13_num
2330 };
2331
2332 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2333
2334 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2335
2336 // Return whether or not this register is ever used as an argument. This
2337 // function is used on startup to build the trampoline stubs in generateOptoStub.
2338 // Registers not mentioned will be killed by the VM call in the trampoline, and
2339 // arguments in those registers not be available to the callee.
2340 bool Matcher::can_be_java_arg(int reg) {
2341 // We return true for all registers contained in iarg_reg[] and
2342 // farg_reg[] and their virtual halves.
2343 // We must include the virtual halves in order to get STDs and LDs
2344 // instead of STWs and LWs in the trampoline stubs.
2345
2346 if ( reg == R3_num || reg == R3_H_num
2347 || reg == R4_num || reg == R4_H_num
2348 || reg == R5_num || reg == R5_H_num
2349 || reg == R6_num || reg == R6_H_num
2350 || reg == R7_num || reg == R7_H_num
2351 || reg == R8_num || reg == R8_H_num
2352 || reg == R9_num || reg == R9_H_num
2353 || reg == R10_num || reg == R10_H_num)
2354 return true;
2355
2356 if ( reg == F1_num || reg == F1_H_num
2357 || reg == F2_num || reg == F2_H_num
2358 || reg == F3_num || reg == F3_H_num
2359 || reg == F4_num || reg == F4_H_num
2360 || reg == F5_num || reg == F5_H_num
2361 || reg == F6_num || reg == F6_H_num
2362 || reg == F7_num || reg == F7_H_num
2363 || reg == F8_num || reg == F8_H_num
2364 || reg == F9_num || reg == F9_H_num
2365 || reg == F10_num || reg == F10_H_num
2366 || reg == F11_num || reg == F11_H_num
2367 || reg == F12_num || reg == F12_H_num
2368 || reg == F13_num || reg == F13_H_num)
2369 return true;
2370
2371 return false;
2372 }
2373
2374 bool Matcher::is_spillable_arg(int reg) {
2375 return can_be_java_arg(reg);
2376 }
2377
2378 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2379 return false;
2380 }
2381
2382 // Register for DIVI projection of divmodI.
2383 RegMask Matcher::divI_proj_mask() {
2384 ShouldNotReachHere();
2385 return RegMask();
2386 }
2387
2388 // Register for MODI projection of divmodI.
2389 RegMask Matcher::modI_proj_mask() {
2390 ShouldNotReachHere();
2391 return RegMask();
2392 }
2393
2394 // Register for DIVL projection of divmodL.
2395 RegMask Matcher::divL_proj_mask() {
2396 ShouldNotReachHere();
2397 return RegMask();
2398 }
2399
2400 // Register for MODL projection of divmodL.
2401 RegMask Matcher::modL_proj_mask() {
2402 ShouldNotReachHere();
2403 return RegMask();
2404 }
2405
2406 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2407 return RegMask();
2408 }
2409
2410 %}
2411
2412 //----------ENCODING BLOCK-----------------------------------------------------
2413 // This block specifies the encoding classes used by the compiler to output
2414 // byte streams. Encoding classes are parameterized macros used by
2415 // Machine Instruction Nodes in order to generate the bit encoding of the
2416 // instruction. Operands specify their base encoding interface with the
2417 // interface keyword. There are currently supported four interfaces,
2418 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2419 // operand to generate a function which returns its register number when
2420 // queried. CONST_INTER causes an operand to generate a function which
2421 // returns the value of the constant when queried. MEMORY_INTER causes an
2422 // operand to generate four functions which return the Base Register, the
2423 // Index Register, the Scale Value, and the Offset Value of the operand when
2424 // queried. COND_INTER causes an operand to generate six functions which
2425 // return the encoding code (ie - encoding bits for the instruction)
2426 // associated with each basic boolean condition for a conditional instruction.
2427 //
2428 // Instructions specify two basic values for encoding. Again, a function
2429 // is available to check if the constant displacement is an oop. They use the
2430 // ins_encode keyword to specify their encoding classes (which must be
2431 // a sequence of enc_class names, and their parameters, specified in
2432 // the encoding block), and they use the
2433 // opcode keyword to specify, in order, their primary, secondary, and
2434 // tertiary opcode. Only the opcode sections which a particular instruction
2435 // needs for encoding need to be specified.
2436 encode %{
2437 enc_class enc_unimplemented %{
2438 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2439 MacroAssembler _masm(&cbuf);
2440 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2441 %}
2442
2443 enc_class enc_untested %{
2444 #ifdef ASSERT
2445 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2446 MacroAssembler _masm(&cbuf);
2447 __ untested("Untested mach node encoding in AD file.");
2448 #else
2449 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2450 #endif
2451 %}
2452
2453 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2454 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2455 MacroAssembler _masm(&cbuf);
2456 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2457 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2458 %}
2459
2460 // Load acquire.
2461 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2462 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2463 MacroAssembler _masm(&cbuf);
2464 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2465 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2466 __ twi_0($dst$$Register);
2467 __ isync();
2468 %}
2469
2470 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2471 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2472
2473 MacroAssembler _masm(&cbuf);
2474 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2475 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2476 %}
2477
2478 // Load acquire.
2479 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2480 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2481
2482 MacroAssembler _masm(&cbuf);
2483 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2484 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2485 __ twi_0($dst$$Register);
2486 __ isync();
2487 %}
2488
2489 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2490 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2491
2492 MacroAssembler _masm(&cbuf);
2493 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2494 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2495 %}
2496
2497 // Load acquire.
2498 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2499 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2500
2501 MacroAssembler _masm(&cbuf);
2502 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2503 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2504 __ twi_0($dst$$Register);
2505 __ isync();
2506 %}
2507
2508 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2509 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2510 MacroAssembler _masm(&cbuf);
2511 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2512 // Operand 'ds' requires 4-alignment.
2513 assert((Idisp & 0x3) == 0, "unaligned offset");
2514 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2515 %}
2516
2517 // Load acquire.
2518 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2519 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2520 MacroAssembler _masm(&cbuf);
2521 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2522 // Operand 'ds' requires 4-alignment.
2523 assert((Idisp & 0x3) == 0, "unaligned offset");
2524 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2525 __ twi_0($dst$$Register);
2526 __ isync();
2527 %}
2528
2529 enc_class enc_lfd(RegF dst, memory mem) %{
2530 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2531 MacroAssembler _masm(&cbuf);
2532 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2533 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2534 %}
2535
2536 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2537 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2538
2539 MacroAssembler _masm(&cbuf);
2540 int toc_offset = 0;
2541
2542 if (!ra_->C->in_scratch_emit_size()) {
2543 address const_toc_addr;
2544 // Create a non-oop constant, no relocation needed.
2545 // If it is an IC, it has a virtual_call_Relocation.
2546 const_toc_addr = __ long_constant((jlong)$src$$constant);
2547
2548 // Get the constant's TOC offset.
2549 toc_offset = __ offset_to_method_toc(const_toc_addr);
2550
2551 // Keep the current instruction offset in mind.
2552 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2553 }
2554
2555 __ ld($dst$$Register, toc_offset, $toc$$Register);
2556 %}
2557
2558 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2559 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2560
2561 MacroAssembler _masm(&cbuf);
2562
2563 if (!ra_->C->in_scratch_emit_size()) {
2564 address const_toc_addr;
2565 // Create a non-oop constant, no relocation needed.
2566 // If it is an IC, it has a virtual_call_Relocation.
2567 const_toc_addr = __ long_constant((jlong)$src$$constant);
2568
2569 // Get the constant's TOC offset.
2570 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2571 // Store the toc offset of the constant.
2572 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2573
2574 // Also keep the current instruction offset in mind.
2575 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2576 }
2577
2578 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2579 %}
2580
2581 %} // encode
2582
2583 source %{
2584
2585 typedef struct {
2586 loadConL_hiNode *_large_hi;
2587 loadConL_loNode *_large_lo;
2588 loadConLNode *_small;
2589 MachNode *_last;
2590 } loadConLNodesTuple;
2591
2592 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2593 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2594 loadConLNodesTuple nodes;
2595
2596 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2597 if (large_constant_pool) {
2598 // Create new nodes.
2599 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2600 loadConL_loNode *m2 = new (C) loadConL_loNode();
2601
2602 // inputs for new nodes
2603 m1->add_req(NULL, toc);
2604 m2->add_req(NULL, m1);
2605
2606 // operands for new nodes
2607 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2608 m1->_opnds[1] = immSrc; // src
2609 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2610 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2611 m2->_opnds[1] = immSrc; // src
2612 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2613
2614 // Initialize ins_attrib TOC fields.
2615 m1->_const_toc_offset = -1;
2616 m2->_const_toc_offset_hi_node = m1;
2617
2618 // Initialize ins_attrib instruction offset.
2619 m1->_cbuf_insts_offset = -1;
2620
2621 // register allocation for new nodes
2622 ra_->set_pair(m1->_idx, reg_second, reg_first);
2623 ra_->set_pair(m2->_idx, reg_second, reg_first);
2624
2625 // Create result.
2626 nodes._large_hi = m1;
2627 nodes._large_lo = m2;
2628 nodes._small = NULL;
2629 nodes._last = nodes._large_lo;
2630 assert(m2->bottom_type()->isa_long(), "must be long");
2631 } else {
2632 loadConLNode *m2 = new (C) loadConLNode();
2633
2634 // inputs for new nodes
2635 m2->add_req(NULL, toc);
2636
2637 // operands for new nodes
2638 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2639 m2->_opnds[1] = immSrc; // src
2640 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2641
2642 // Initialize ins_attrib instruction offset.
2643 m2->_cbuf_insts_offset = -1;
2644
2645 // register allocation for new nodes
2646 ra_->set_pair(m2->_idx, reg_second, reg_first);
2647
2648 // Create result.
2649 nodes._large_hi = NULL;
2650 nodes._large_lo = NULL;
2651 nodes._small = m2;
2652 nodes._last = nodes._small;
2653 assert(m2->bottom_type()->isa_long(), "must be long");
2654 }
2655
2656 return nodes;
2657 }
2658
2659 %} // source
2660
2661 encode %{
2662 // Postalloc expand emitter for loading a long constant from the method's TOC.
2663 // Enc_class needed as consttanttablebase is not supported by postalloc
2664 // expand.
2665 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2666 // Create new nodes.
2667 loadConLNodesTuple loadConLNodes =
2668 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2669 ra_->get_reg_second(this), ra_->get_reg_first(this));
2670
2671 // Push new nodes.
2672 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2673 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2674
2675 // some asserts
2676 assert(nodes->length() >= 1, "must have created at least 1 node");
2677 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2678 %}
2679
2680 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2681 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2682
2683 MacroAssembler _masm(&cbuf);
2684 int toc_offset = 0;
2685
2686 if (!ra_->C->in_scratch_emit_size()) {
2687 intptr_t val = $src$$constant;
2688 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2689 address const_toc_addr;
2690 if (constant_reloc == relocInfo::oop_type) {
2691 // Create an oop constant and a corresponding relocation.
2692 AddressLiteral a = __ allocate_oop_address((jobject)val);
2693 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2694 __ relocate(a.rspec());
2695 } else if (constant_reloc == relocInfo::metadata_type) {
2696 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2697 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2698 __ relocate(a.rspec());
2699 } else {
2700 // Create a non-oop constant, no relocation needed.
2701 const_toc_addr = __ long_constant((jlong)$src$$constant);
2702 }
2703
2704 // Get the constant's TOC offset.
2705 toc_offset = __ offset_to_method_toc(const_toc_addr);
2706 }
2707
2708 __ ld($dst$$Register, toc_offset, $toc$$Register);
2709 %}
2710
2711 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2712 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2713
2714 MacroAssembler _masm(&cbuf);
2715 if (!ra_->C->in_scratch_emit_size()) {
2716 intptr_t val = $src$$constant;
2717 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2718 address const_toc_addr;
2719 if (constant_reloc == relocInfo::oop_type) {
2720 // Create an oop constant and a corresponding relocation.
2721 AddressLiteral a = __ allocate_oop_address((jobject)val);
2722 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2723 __ relocate(a.rspec());
2724 } else if (constant_reloc == relocInfo::metadata_type) {
2725 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2726 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2727 __ relocate(a.rspec());
2728 } else { // non-oop pointers, e.g. card mark base, heap top
2729 // Create a non-oop constant, no relocation needed.
2730 const_toc_addr = __ long_constant((jlong)$src$$constant);
2731 }
2732
2733 // Get the constant's TOC offset.
2734 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2735 // Store the toc offset of the constant.
2736 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2737 }
2738
2739 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2740 %}
2741
2742 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2743 // Enc_class needed as consttanttablebase is not supported by postalloc
2744 // expand.
2745 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2746 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2747 if (large_constant_pool) {
2748 // Create new nodes.
2749 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2750 loadConP_loNode *m2 = new (C) loadConP_loNode();
2751
2752 // inputs for new nodes
2753 m1->add_req(NULL, n_toc);
2754 m2->add_req(NULL, m1);
2755
2756 // operands for new nodes
2757 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2758 m1->_opnds[1] = op_src; // src
2759 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2760 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2761 m2->_opnds[1] = op_src; // src
2762 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2763
2764 // Initialize ins_attrib TOC fields.
2765 m1->_const_toc_offset = -1;
2766 m2->_const_toc_offset_hi_node = m1;
2767
2768 // Register allocation for new nodes.
2769 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2770 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2771
2772 nodes->push(m1);
2773 nodes->push(m2);
2774 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2775 } else {
2776 loadConPNode *m2 = new (C) loadConPNode();
2777
2778 // inputs for new nodes
2779 m2->add_req(NULL, n_toc);
2780
2781 // operands for new nodes
2782 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2783 m2->_opnds[1] = op_src; // src
2784 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2785
2786 // Register allocation for new nodes.
2787 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2788
2789 nodes->push(m2);
2790 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2791 }
2792 %}
2793
2794 // Enc_class needed as consttanttablebase is not supported by postalloc
2795 // expand.
2796 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2797 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2798
2799 MachNode *m2;
2800 if (large_constant_pool) {
2801 m2 = new (C) loadConFCompNode();
2802 } else {
2803 m2 = new (C) loadConFNode();
2804 }
2805 // inputs for new nodes
2806 m2->add_req(NULL, n_toc);
2807
2808 // operands for new nodes
2809 m2->_opnds[0] = op_dst;
2810 m2->_opnds[1] = op_src;
2811 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2812
2813 // register allocation for new nodes
2814 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2815 nodes->push(m2);
2816 %}
2817
2818 // Enc_class needed as consttanttablebase is not supported by postalloc
2819 // expand.
2820 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2821 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2822
2823 MachNode *m2;
2824 if (large_constant_pool) {
2825 m2 = new (C) loadConDCompNode();
2826 } else {
2827 m2 = new (C) loadConDNode();
2828 }
2829 // inputs for new nodes
2830 m2->add_req(NULL, n_toc);
2831
2832 // operands for new nodes
2833 m2->_opnds[0] = op_dst;
2834 m2->_opnds[1] = op_src;
2835 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2836
2837 // register allocation for new nodes
2838 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2839 nodes->push(m2);
2840 %}
2841
2842 enc_class enc_stw(iRegIsrc src, memory mem) %{
2843 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2844 MacroAssembler _masm(&cbuf);
2845 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2846 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2847 %}
2848
2849 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2850 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2851 MacroAssembler _masm(&cbuf);
2852 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2853 // Operand 'ds' requires 4-alignment.
2854 assert((Idisp & 0x3) == 0, "unaligned offset");
2855 __ std($src$$Register, Idisp, $mem$$base$$Register);
2856 %}
2857
2858 enc_class enc_stfs(RegF src, memory mem) %{
2859 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2860 MacroAssembler _masm(&cbuf);
2861 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2862 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2863 %}
2864
2865 enc_class enc_stfd(RegF src, memory mem) %{
2866 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2867 MacroAssembler _masm(&cbuf);
2868 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2869 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2870 %}
2871
2872 // Use release_store for card-marking to ensure that previous
2873 // oop-stores are visible before the card-mark change.
2874 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2875 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2876 // FIXME: Implement this as a cmove and use a fixed condition code
2877 // register which is written on every transition to compiled code,
2878 // e.g. in call-stub and when returning from runtime stubs.
2879 //
2880 // Proposed code sequence for the cmove implementation:
2881 //
2882 // Label skip_release;
2883 // __ beq(CCRfixed, skip_release);
2884 // __ release();
2885 // __ bind(skip_release);
2886 // __ stb(card mark);
2887
2888 MacroAssembler _masm(&cbuf);
2889 Label skip_storestore;
2890
2891 #if 0 // TODO: PPC port
2892 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2893 // StoreStore barrier conditionally.
2894 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2895 __ cmpwi(CCR0, R0, 0);
2896 __ beq_predict_taken(CCR0, skip_storestore);
2897 #endif
2898 __ li(R0, 0);
2899 __ membar(Assembler::StoreStore);
2900 #if 0 // TODO: PPC port
2901 __ bind(skip_storestore);
2902 #endif
2903
2904 // Do the store.
2905 if ($mem$$index == 0) {
2906 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2907 } else {
2908 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2909 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2910 }
2911 %}
2912
2913 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2914
2915 if (VM_Version::has_isel()) {
2916 // use isel instruction with Power 7
2917 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2918 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2919 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2920 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2921
2922 n_compare->add_req(n_region, n_src);
2923 n_compare->_opnds[0] = op_crx;
2924 n_compare->_opnds[1] = op_src;
2925 n_compare->_opnds[2] = new (C) immL16Oper(0);
2926
2927 n_sub_base->add_req(n_region, n_src);
2928 n_sub_base->_opnds[0] = op_dst;
2929 n_sub_base->_opnds[1] = op_src;
2930 n_sub_base->_bottom_type = _bottom_type;
2931
2932 n_shift->add_req(n_region, n_sub_base);
2933 n_shift->_opnds[0] = op_dst;
2934 n_shift->_opnds[1] = op_dst;
2935 n_shift->_bottom_type = _bottom_type;
2936
2937 n_cond_set->add_req(n_region, n_compare, n_shift);
2938 n_cond_set->_opnds[0] = op_dst;
2939 n_cond_set->_opnds[1] = op_crx;
2940 n_cond_set->_opnds[2] = op_dst;
2941 n_cond_set->_bottom_type = _bottom_type;
2942
2943 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2944 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2945 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2946 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2947
2948 nodes->push(n_compare);
2949 nodes->push(n_sub_base);
2950 nodes->push(n_shift);
2951 nodes->push(n_cond_set);
2952
2953 } else {
2954 // before Power 7
2955 moveRegNode *n_move = new (C) moveRegNode();
2956 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2957 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2958 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2959
2960 n_move->add_req(n_region, n_src);
2961 n_move->_opnds[0] = op_dst;
2962 n_move->_opnds[1] = op_src;
2963 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2964
2965 n_compare->add_req(n_region, n_src);
2966 n_compare->add_prec(n_move);
2967
2968 n_compare->_opnds[0] = op_crx;
2969 n_compare->_opnds[1] = op_src;
2970 n_compare->_opnds[2] = new (C) immL16Oper(0);
2971
2972 n_sub_base->add_req(n_region, n_compare, n_src);
2973 n_sub_base->_opnds[0] = op_dst;
2974 n_sub_base->_opnds[1] = op_crx;
2975 n_sub_base->_opnds[2] = op_src;
2976 n_sub_base->_bottom_type = _bottom_type;
2977
2978 n_shift->add_req(n_region, n_sub_base);
2979 n_shift->_opnds[0] = op_dst;
2980 n_shift->_opnds[1] = op_dst;
2981 n_shift->_bottom_type = _bottom_type;
2982
2983 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2984 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2985 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2986 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2987
2988 nodes->push(n_move);
2989 nodes->push(n_compare);
2990 nodes->push(n_sub_base);
2991 nodes->push(n_shift);
2992 }
2993
2994 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2995 %}
2996
2997 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2998
2999 encodeP_subNode *n1 = new (C) encodeP_subNode();
3000 n1->add_req(n_region, n_src);
3001 n1->_opnds[0] = op_dst;
3002 n1->_opnds[1] = op_src;
3003 n1->_bottom_type = _bottom_type;
3004
3005 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
3006 n2->add_req(n_region, n1);
3007 n2->_opnds[0] = op_dst;
3008 n2->_opnds[1] = op_dst;
3009 n2->_bottom_type = _bottom_type;
3010 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3011 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3012
3013 nodes->push(n1);
3014 nodes->push(n2);
3015 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3016 %}
3017
3018 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3019 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
3020 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
3021
3022 n_compare->add_req(n_region, n_src);
3023 n_compare->_opnds[0] = op_crx;
3024 n_compare->_opnds[1] = op_src;
3025 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
3026
3027 n_shift->add_req(n_region, n_src);
3028 n_shift->_opnds[0] = op_dst;
3029 n_shift->_opnds[1] = op_src;
3030 n_shift->_bottom_type = _bottom_type;
3031
3032 if (VM_Version::has_isel()) {
3033 // use isel instruction with Power 7
3034
3035 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
3036 n_add_base->add_req(n_region, n_shift);
3037 n_add_base->_opnds[0] = op_dst;
3038 n_add_base->_opnds[1] = op_dst;
3039 n_add_base->_bottom_type = _bottom_type;
3040
3041 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3042 n_cond_set->add_req(n_region, n_compare, n_add_base);
3043 n_cond_set->_opnds[0] = op_dst;
3044 n_cond_set->_opnds[1] = op_crx;
3045 n_cond_set->_opnds[2] = op_dst;
3046 n_cond_set->_bottom_type = _bottom_type;
3047
3048 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3049 ra_->set_oop(n_cond_set, true);
3050
3051 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3052 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3053 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3054 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3055
3056 nodes->push(n_compare);
3057 nodes->push(n_shift);
3058 nodes->push(n_add_base);
3059 nodes->push(n_cond_set);
3060
3061 } else {
3062 // before Power 7
3063 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3064
3065 n_add_base->add_req(n_region, n_compare, n_shift);
3066 n_add_base->_opnds[0] = op_dst;
3067 n_add_base->_opnds[1] = op_crx;
3068 n_add_base->_opnds[2] = op_dst;
3069 n_add_base->_bottom_type = _bottom_type;
3070
3071 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3072 ra_->set_oop(n_add_base, true);
3073
3074 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3075 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3076 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3077
3078 nodes->push(n_compare);
3079 nodes->push(n_shift);
3080 nodes->push(n_add_base);
3081 }
3082 %}
3083
3084 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3085 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3086 n1->add_req(n_region, n_src);
3087 n1->_opnds[0] = op_dst;
3088 n1->_opnds[1] = op_src;
3089 n1->_bottom_type = _bottom_type;
3090
3091 decodeN_addNode *n2 = new (C) decodeN_addNode();
3092 n2->add_req(n_region, n1);
3093 n2->_opnds[0] = op_dst;
3094 n2->_opnds[1] = op_dst;
3095 n2->_bottom_type = _bottom_type;
3096 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3097 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3098
3099 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3100 ra_->set_oop(n2, true);
3101
3102 nodes->push(n1);
3103 nodes->push(n2);
3104 %}
3105
3106 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3107 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3108
3109 MacroAssembler _masm(&cbuf);
3110 int cc = $cmp$$cmpcode;
3111 int flags_reg = $crx$$reg;
3112 Label done;
3113 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3114 // Branch if not (cmp crx).
3115 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3116 __ mr($dst$$Register, $src$$Register);
3117 // TODO PPC port __ endgroup_if_needed(_size == 12);
3118 __ bind(done);
3119 %}
3120
3121 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3122 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3123
3124 MacroAssembler _masm(&cbuf);
3125 Label done;
3126 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3127 // Branch if not (cmp crx).
3128 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3129 __ li($dst$$Register, $src$$constant);
3130 // TODO PPC port __ endgroup_if_needed(_size == 12);
3131 __ bind(done);
3132 %}
3133
3134 // New atomics.
3135 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3136 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3137
3138 MacroAssembler _masm(&cbuf);
3139 Register Rtmp = R0;
3140 Register Rres = $res$$Register;
3141 Register Rsrc = $src$$Register;
3142 Register Rptr = $mem_ptr$$Register;
3143 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3144 Register Rold = RegCollision ? Rtmp : Rres;
3145
3146 Label Lretry;
3147 __ bind(Lretry);
3148 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3149 __ add(Rtmp, Rsrc, Rold);
3150 __ stwcx_(Rtmp, Rptr);
3151 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3152 __ bne_predict_not_taken(CCR0, Lretry);
3153 } else {
3154 __ bne( CCR0, Lretry);
3155 }
3156 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3157 __ fence();
3158 %}
3159
3160 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3161 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3162
3163 MacroAssembler _masm(&cbuf);
3164 Register Rtmp = R0;
3165 Register Rres = $res$$Register;
3166 Register Rsrc = $src$$Register;
3167 Register Rptr = $mem_ptr$$Register;
3168 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3169 Register Rold = RegCollision ? Rtmp : Rres;
3170
3171 Label Lretry;
3172 __ bind(Lretry);
3173 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3174 __ add(Rtmp, Rsrc, Rold);
3175 __ stdcx_(Rtmp, Rptr);
3176 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3177 __ bne_predict_not_taken(CCR0, Lretry);
3178 } else {
3179 __ bne( CCR0, Lretry);
3180 }
3181 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3182 __ fence();
3183 %}
3184
3185 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3186 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3187
3188 MacroAssembler _masm(&cbuf);
3189 Register Rtmp = R0;
3190 Register Rres = $res$$Register;
3191 Register Rsrc = $src$$Register;
3192 Register Rptr = $mem_ptr$$Register;
3193 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3194 Register Rold = RegCollision ? Rtmp : Rres;
3195
3196 Label Lretry;
3197 __ bind(Lretry);
3198 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3199 __ stwcx_(Rsrc, Rptr);
3200 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3201 __ bne_predict_not_taken(CCR0, Lretry);
3202 } else {
3203 __ bne( CCR0, Lretry);
3204 }
3205 if (RegCollision) __ mr(Rres, Rtmp);
3206 __ fence();
3207 %}
3208
3209 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3210 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3211
3212 MacroAssembler _masm(&cbuf);
3213 Register Rtmp = R0;
3214 Register Rres = $res$$Register;
3215 Register Rsrc = $src$$Register;
3216 Register Rptr = $mem_ptr$$Register;
3217 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3218 Register Rold = RegCollision ? Rtmp : Rres;
3219
3220 Label Lretry;
3221 __ bind(Lretry);
3222 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3223 __ stdcx_(Rsrc, Rptr);
3224 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3225 __ bne_predict_not_taken(CCR0, Lretry);
3226 } else {
3227 __ bne( CCR0, Lretry);
3228 }
3229 if (RegCollision) __ mr(Rres, Rtmp);
3230 __ fence();
3231 %}
3232
3233 // This enc_class is needed so that scheduler gets proper
3234 // input mapping for latency computation.
3235 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3236 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3237 MacroAssembler _masm(&cbuf);
3238 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3239 %}
3240
3241 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3242 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3243
3244 MacroAssembler _masm(&cbuf);
3245
3246 Label done;
3247 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3248 __ li($dst$$Register, $zero$$constant);
3249 __ beq($crx$$CondRegister, done);
3250 __ li($dst$$Register, $notzero$$constant);
3251 __ bind(done);
3252 %}
3253
3254 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3255 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3256
3257 MacroAssembler _masm(&cbuf);
3258
3259 Label done;
3260 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3261 __ li($dst$$Register, $zero$$constant);
3262 __ beq($crx$$CondRegister, done);
3263 __ li($dst$$Register, $notzero$$constant);
3264 __ bind(done);
3265 %}
3266
3267 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3268 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3269
3270 MacroAssembler _masm(&cbuf);
3271 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3272 Label done;
3273 __ bso($crx$$CondRegister, done);
3274 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3275 // TODO PPC port __ endgroup_if_needed(_size == 12);
3276 __ bind(done);
3277 %}
3278
3279 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3280 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3281
3282 MacroAssembler _masm(&cbuf);
3283 Label d; // dummy
3284 __ bind(d);
3285 Label* p = ($lbl$$label);
3286 // `p' is `NULL' when this encoding class is used only to
3287 // determine the size of the encoded instruction.
3288 Label& l = (NULL == p)? d : *(p);
3289 int cc = $cmp$$cmpcode;
3290 int flags_reg = $crx$$reg;
3291 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3292 int bhint = Assembler::bhintNoHint;
3293
3294 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3295 if (_prob <= PROB_NEVER) {
3296 bhint = Assembler::bhintIsNotTaken;
3297 } else if (_prob >= PROB_ALWAYS) {
3298 bhint = Assembler::bhintIsTaken;
3299 }
3300 }
3301
3302 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3303 cc_to_biint(cc, flags_reg),
3304 l);
3305 %}
3306
3307 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3308 // The scheduler doesn't know about branch shortening, so we set the opcode
3309 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3310 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3311
3312 MacroAssembler _masm(&cbuf);
3313 Label d; // dummy
3314 __ bind(d);
3315 Label* p = ($lbl$$label);
3316 // `p' is `NULL' when this encoding class is used only to
3317 // determine the size of the encoded instruction.
3318 Label& l = (NULL == p)? d : *(p);
3319 int cc = $cmp$$cmpcode;
3320 int flags_reg = $crx$$reg;
3321 int bhint = Assembler::bhintNoHint;
3322
3323 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3324 if (_prob <= PROB_NEVER) {
3325 bhint = Assembler::bhintIsNotTaken;
3326 } else if (_prob >= PROB_ALWAYS) {
3327 bhint = Assembler::bhintIsTaken;
3328 }
3329 }
3330
3331 // Tell the conditional far branch to optimize itself when being relocated.
3332 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3333 cc_to_biint(cc, flags_reg),
3334 l,
3335 MacroAssembler::bc_far_optimize_on_relocate);
3336 %}
3337
3338 // Branch used with Power6 scheduling (can be shortened without changing the node).
3339 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3340 // The scheduler doesn't know about branch shortening, so we set the opcode
3341 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3342 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3343
3344 MacroAssembler _masm(&cbuf);
3345 Label d; // dummy
3346 __ bind(d);
3347 Label* p = ($lbl$$label);
3348 // `p' is `NULL' when this encoding class is used only to
3349 // determine the size of the encoded instruction.
3350 Label& l = (NULL == p)? d : *(p);
3351 int cc = $cmp$$cmpcode;
3352 int flags_reg = $crx$$reg;
3353 int bhint = Assembler::bhintNoHint;
3354
3355 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3356 if (_prob <= PROB_NEVER) {
3357 bhint = Assembler::bhintIsNotTaken;
3358 } else if (_prob >= PROB_ALWAYS) {
3359 bhint = Assembler::bhintIsTaken;
3360 }
3361 }
3362
3363 #if 0 // TODO: PPC port
3364 if (_size == 8) {
3365 // Tell the conditional far branch to optimize itself when being relocated.
3366 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3367 cc_to_biint(cc, flags_reg),
3368 l,
3369 MacroAssembler::bc_far_optimize_on_relocate);
3370 } else {
3371 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3372 cc_to_biint(cc, flags_reg),
3373 l);
3374 }
3375 #endif
3376 Unimplemented();
3377 %}
3378
3379 // Postalloc expand emitter for loading a replicatef float constant from
3380 // the method's TOC.
3381 // Enc_class needed as consttanttablebase is not supported by postalloc
3382 // expand.
3383 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3384 // Create new nodes.
3385
3386 // Make an operand with the bit pattern to load as float.
3387 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3388
3389 loadConLNodesTuple loadConLNodes =
3390 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3391 ra_->get_reg_second(this), ra_->get_reg_first(this));
3392
3393 // Push new nodes.
3394 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3395 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3396
3397 assert(nodes->length() >= 1, "must have created at least 1 node");
3398 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3399 %}
3400
3401 // This enc_class is needed so that scheduler gets proper
3402 // input mapping for latency computation.
3403 enc_class enc_poll(immI dst, iRegLdst poll) %{
3404 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3405 // Fake operand dst needed for PPC scheduler.
3406 assert($dst$$constant == 0x0, "dst must be 0x0");
3407
3408 MacroAssembler _masm(&cbuf);
3409 // Mark the code position where the load from the safepoint
3410 // polling page was emitted as relocInfo::poll_type.
3411 __ relocate(relocInfo::poll_type);
3412 __ load_from_polling_page($poll$$Register);
3413 %}
3414
3415 // A Java static call or a runtime call.
3416 //
3417 // Branch-and-link relative to a trampoline.
3418 // The trampoline loads the target address and does a long branch to there.
3419 // In case we call java, the trampoline branches to a interpreter_stub
3420 // which loads the inline cache and the real call target from the constant pool.
3421 //
3422 // This basically looks like this:
3423 //
3424 // >>>> consts -+ -+
3425 // | |- offset1
3426 // [call target1] | <-+
3427 // [IC cache] |- offset2
3428 // [call target2] <--+
3429 //
3430 // <<<< consts
3431 // >>>> insts
3432 //
3433 // bl offset16 -+ -+ ??? // How many bits available?
3434 // | |
3435 // <<<< insts | |
3436 // >>>> stubs | |
3437 // | |- trampoline_stub_Reloc
3438 // trampoline stub: | <-+
3439 // r2 = toc |
3440 // r2 = [r2 + offset1] | // Load call target1 from const section
3441 // mtctr r2 |
3442 // bctr |- static_stub_Reloc
3443 // comp_to_interp_stub: <---+
3444 // r1 = toc
3445 // ICreg = [r1 + IC_offset] // Load IC from const section
3446 // r1 = [r1 + offset2] // Load call target2 from const section
3447 // mtctr r1
3448 // bctr
3449 //
3450 // <<<< stubs
3451 //
3452 // The call instruction in the code either
3453 // - Branches directly to a compiled method if the offset is encodable in instruction.
3454 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3455 // - Branches to the compiled_to_interp stub if the target is interpreted.
3456 //
3457 // Further there are three relocations from the loads to the constants in
3458 // the constant section.
3459 //
3460 // Usage of r1 and r2 in the stubs allows to distinguish them.
3461 enc_class enc_java_static_call(method meth) %{
3462 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3463
3464 MacroAssembler _masm(&cbuf);
3465 address entry_point = (address)$meth$$method;
3466
3467 if (!_method) {
3468 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3469 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3470 } else {
3471 // Remember the offset not the address.
3472 const int start_offset = __ offset();
3473 // The trampoline stub.
3474 if (!Compile::current()->in_scratch_emit_size()) {
3475 // No entry point given, use the current pc.
3476 // Make sure branch fits into
3477 if (entry_point == 0) entry_point = __ pc();
3478
3479 // Put the entry point as a constant into the constant pool.
3480 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3481 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3482
3483 // Emit the trampoline stub which will be related to the branch-and-link below.
3484 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3485 __ relocate(_optimized_virtual ?
3486 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3487 }
3488
3489 // The real call.
3490 // Note: At this point we do not have the address of the trampoline
3491 // stub, and the entry point might be too far away for bl, so __ pc()
3492 // serves as dummy and the bl will be patched later.
3493 cbuf.set_insts_mark();
3494 __ bl(__ pc()); // Emits a relocation.
3495
3496 // The stub for call to interpreter.
3497 CompiledStaticCall::emit_to_interp_stub(cbuf);
3498 }
3499 %}
3500
3501 // Emit a method handle call.
3502 //
3503 // Method handle calls from compiled to compiled are going thru a
3504 // c2i -> i2c adapter, extending the frame for their arguments. The
3505 // caller however, returns directly to the compiled callee, that has
3506 // to cope with the extended frame. We restore the original frame by
3507 // loading the callers sp and adding the calculated framesize.
3508 enc_class enc_java_handle_call(method meth) %{
3509 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3510
3511 MacroAssembler _masm(&cbuf);
3512 address entry_point = (address)$meth$$method;
3513
3514 // Remember the offset not the address.
3515 const int start_offset = __ offset();
3516 // The trampoline stub.
3517 if (!ra_->C->in_scratch_emit_size()) {
3518 // No entry point given, use the current pc.
3519 // Make sure branch fits into
3520 if (entry_point == 0) entry_point = __ pc();
3521
3522 // Put the entry point as a constant into the constant pool.
3523 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3524 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3525
3526 // Emit the trampoline stub which will be related to the branch-and-link below.
3527 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3528 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3529 __ relocate(relocInfo::opt_virtual_call_type);
3530 }
3531
3532 // The real call.
3533 // Note: At this point we do not have the address of the trampoline
3534 // stub, and the entry point might be too far away for bl, so __ pc()
3535 // serves as dummy and the bl will be patched later.
3536 cbuf.set_insts_mark();
3537 __ bl(__ pc()); // Emits a relocation.
3538
3539 assert(_method, "execute next statement conditionally");
3540 // The stub for call to interpreter.
3541 CompiledStaticCall::emit_to_interp_stub(cbuf);
3542
3543 // Restore original sp.
3544 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3545 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3546 unsigned int bytes = (unsigned int)framesize;
3547 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3548 if (Assembler::is_simm(-offset, 16)) {
3549 __ addi(R1_SP, R11_scratch1, -offset);
3550 } else {
3551 __ load_const_optimized(R12_scratch2, -offset);
3552 __ add(R1_SP, R11_scratch1, R12_scratch2);
3553 }
3554 #ifdef ASSERT
3555 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3556 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3557 __ asm_assert_eq("backlink changed", 0x8000);
3558 #endif
3559 // If fails should store backlink before unextending.
3560
3561 if (ra_->C->env()->failing()) {
3562 return;
3563 }
3564 %}
3565
3566 // Second node of expanded dynamic call - the call.
3567 enc_class enc_java_dynamic_call_sched(method meth) %{
3568 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3569
3570 MacroAssembler _masm(&cbuf);
3571
3572 if (!ra_->C->in_scratch_emit_size()) {
3573 // Create a call trampoline stub for the given method.
3574 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3575 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3576 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3577 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3578
3579 if (ra_->C->env()->failing())
3580 return;
3581
3582 // Build relocation at call site with ic position as data.
3583 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3584 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3585 "must have one, but can't have both");
3586 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3587 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3588 "must contain instruction offset");
3589 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3590 ? _load_ic_hi_node->_cbuf_insts_offset
3591 : _load_ic_node->_cbuf_insts_offset;
3592 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3593 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3594 "should be load from TOC");
3595
3596 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3597 }
3598
3599 // At this point I do not have the address of the trampoline stub,
3600 // and the entry point might be too far away for bl. Pc() serves
3601 // as dummy and bl will be patched later.
3602 __ bl((address) __ pc());
3603 %}
3604
3605 // postalloc expand emitter for virtual calls.
3606 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3607
3608 // Create the nodes for loading the IC from the TOC.
3609 loadConLNodesTuple loadConLNodes_IC =
3610 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3611 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3612
3613 // Create the call node.
3614 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3615 call->_method_handle_invoke = _method_handle_invoke;
3616 call->_vtable_index = _vtable_index;
3617 call->_method = _method;
3618 call->_bci = _bci;
3619 call->_optimized_virtual = _optimized_virtual;
3620 call->_tf = _tf;
3621 call->_entry_point = _entry_point;
3622 call->_cnt = _cnt;
3623 call->_argsize = _argsize;
3624 call->_oop_map = _oop_map;
3625 call->_jvms = _jvms;
3626 call->_jvmadj = _jvmadj;
3627 call->_in_rms = _in_rms;
3628 call->_nesting = _nesting;
3629
3630 // New call needs all inputs of old call.
3631 // Req...
3632 for (uint i = 0; i < req(); ++i) {
3633 // The expanded node does not need toc any more.
3634 // Add the inline cache constant here instead. This expresses the
3635 // register of the inline cache must be live at the call.
3636 // Else we would have to adapt JVMState by -1.
3637 if (i == mach_constant_base_node_input()) {
3638 call->add_req(loadConLNodes_IC._last);
3639 } else {
3640 call->add_req(in(i));
3641 }
3642 }
3643 // ...as well as prec
3644 for (uint i = req(); i < len(); ++i) {
3645 call->add_prec(in(i));
3646 }
3647
3648 // Remember nodes loading the inline cache into r19.
3649 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3650 call->_load_ic_node = loadConLNodes_IC._small;
3651
3652 // Operands for new nodes.
3653 call->_opnds[0] = _opnds[0];
3654 call->_opnds[1] = _opnds[1];
3655
3656 // Only the inline cache is associated with a register.
3657 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3658
3659 // Push new nodes.
3660 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3661 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3662 nodes->push(call);
3663 %}
3664
3665 // Compound version of call dynamic
3666 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3667 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3668 MacroAssembler _masm(&cbuf);
3669 int start_offset = __ offset();
3670
3671 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3672 #if 0
3673 if (_vtable_index < 0) {
3674 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3675 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3676 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3677 AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word());
3678
3679 address virtual_call_meta_addr = __ pc();
3680 __ load_const_from_method_toc(ic_reg, meta, Rtoc);
3681 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3682 // to determine who we intended to call.
3683 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3684 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3685 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3686 "Fix constant in ret_addr_offset()");
3687 } else {
3688 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3689 // Go thru the vtable. Get receiver klass. Receiver already
3690 // checked for non-null. If we'll go thru a C2I adapter, the
3691 // interpreter expects method in R19_method.
3692
3693 __ load_klass(R11_scratch1, R3);
3694
3695 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3696 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3697 __ li(R19_method, v_off);
3698 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3699 // NOTE: for vtable dispatches, the vtable entry will never be
3700 // null. However it may very well end up in handle_wrong_method
3701 // if the method is abstract for the particular class.
3702 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3703 // Call target. Either compiled code or C2I adapter.
3704 __ mtctr(R11_scratch1);
3705 __ bctrl();
3706 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3707 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3708 }
3709 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3710 "Fix constant in ret_addr_offset()");
3711 }
3712 #endif
3713 guarantee(0, "Fix handling of toc edge: messes up derived/base pairs.");
3714 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3715 %}
3716
3717 // a runtime call
3718 enc_class enc_java_to_runtime_call (method meth) %{
3719 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3720
3721 MacroAssembler _masm(&cbuf);
3722 const address start_pc = __ pc();
3723
3724 #if defined(ABI_ELFv2)
3725 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3726 __ call_c(entry, relocInfo::runtime_call_type);
3727 #else
3728 // The function we're going to call.
3729 FunctionDescriptor fdtemp;
3730 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3731
3732 Register Rtoc = R12_scratch2;
3733 // Calculate the method's TOC.
3734 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3735 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3736 // pool entries; call_c_using_toc will optimize the call.
3737 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3738 #endif
3739
3740 // Check the ret_addr_offset.
3741 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3742 "Fix constant in ret_addr_offset()");
3743 %}
3744
3745 // Move to ctr for leaf call.
3746 // This enc_class is needed so that scheduler gets proper
3747 // input mapping for latency computation.
3748 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3749 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3750 MacroAssembler _masm(&cbuf);
3751 __ mtctr($src$$Register);
3752 %}
3753
3754 // Postalloc expand emitter for runtime leaf calls.
3755 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3756 loadConLNodesTuple loadConLNodes_Entry;
3757 #if defined(ABI_ELFv2)
3758 jlong entry_address = (jlong) this->entry_point();
3759 assert(entry_address, "need address here");
3760 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3761 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3762 #else
3763 // Get the struct that describes the function we are about to call.
3764 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3765 assert(fd, "need fd here");
3766 jlong entry_address = (jlong) fd->entry();
3767 // new nodes
3768 loadConLNodesTuple loadConLNodes_Env;
3769 loadConLNodesTuple loadConLNodes_Toc;
3770
3771 // Create nodes and operands for loading the entry point.
3772 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3773 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3774
3775
3776 // Create nodes and operands for loading the env pointer.
3777 if (fd->env() != NULL) {
3778 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3779 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3780 } else {
3781 loadConLNodes_Env._large_hi = NULL;
3782 loadConLNodes_Env._large_lo = NULL;
3783 loadConLNodes_Env._small = NULL;
3784 loadConLNodes_Env._last = new (C) loadConL16Node();
3785 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3786 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3787 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3788 }
3789
3790 // Create nodes and operands for loading the Toc point.
3791 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3792 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3793 #endif // ABI_ELFv2
3794 // mtctr node
3795 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode();
3796
3797 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3798 mtctr->add_req(0, loadConLNodes_Entry._last);
3799
3800 mtctr->_opnds[0] = new (C) iRegLdstOper();
3801 mtctr->_opnds[1] = new (C) iRegLdstOper();
3802
3803 // call node
3804 MachCallLeafNode *call = new (C) CallLeafDirectNode();
3805
3806 call->_opnds[0] = _opnds[0];
3807 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later.
3808
3809 // Make the new call node look like the old one.
3810 call->_name = _name;
3811 call->_tf = _tf;
3812 call->_entry_point = _entry_point;
3813 call->_cnt = _cnt;
3814 call->_argsize = _argsize;
3815 call->_oop_map = _oop_map;
3816 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3817 call->_jvms = NULL;
3818 call->_jvmadj = _jvmadj;
3819 call->_in_rms = _in_rms;
3820 call->_nesting = _nesting;
3821
3822
3823 // New call needs all inputs of old call.
3824 // Req...
3825 for (uint i = 0; i < req(); ++i) {
3826 if (i != mach_constant_base_node_input()) {
3827 call->add_req(in(i));
3828 }
3829 }
3830
3831 // These must be reqired edges, as the registers are live up to
3832 // the call. Else the constants are handled as kills.
3833 call->add_req(mtctr);
3834 #if !defined(ABI_ELFv2)
3835 call->add_req(loadConLNodes_Env._last);
3836 call->add_req(loadConLNodes_Toc._last);
3837 #endif
3838
3839 // ...as well as prec
3840 for (uint i = req(); i < len(); ++i) {
3841 call->add_prec(in(i));
3842 }
3843
3844 // registers
3845 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3846
3847 // Insert the new nodes.
3848 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3849 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3850 #if !defined(ABI_ELFv2)
3851 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3852 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3853 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3854 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3855 #endif
3856 nodes->push(mtctr);
3857 nodes->push(call);
3858 %}
3859 %}
3860
3861 //----------FRAME--------------------------------------------------------------
3862 // Definition of frame structure and management information.
3863
3864 frame %{
3865 // What direction does stack grow in (assumed to be same for native & Java).
3866 stack_direction(TOWARDS_LOW);
3867
3868 // These two registers define part of the calling convention between
3869 // compiled code and the interpreter.
3870
3871 // Inline Cache Register or method for I2C.
3872 inline_cache_reg(R19); // R19_method
3873
3874 // Method Oop Register when calling interpreter.
3875 interpreter_method_oop_reg(R19); // R19_method
3876
3877 // Optional: name the operand used by cisc-spilling to access
3878 // [stack_pointer + offset].
3879 cisc_spilling_operand_name(indOffset);
3880
3881 // Number of stack slots consumed by a Monitor enter.
3882 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3883
3884 // Compiled code's Frame Pointer.
3885 frame_pointer(R1); // R1_SP
3886
3887 // Interpreter stores its frame pointer in a register which is
3888 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3889 // interpreted java to compiled java.
3890 //
3891 // R14_state holds pointer to caller's cInterpreter.
3892 interpreter_frame_pointer(R14); // R14_state
3893
3894 stack_alignment(frame::alignment_in_bytes);
3895
3896 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3897
3898 // Number of outgoing stack slots killed above the
3899 // out_preserve_stack_slots for calls to C. Supports the var-args
3900 // backing area for register parms.
3901 //
3902 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3903
3904 // The after-PROLOG location of the return address. Location of
3905 // return address specifies a type (REG or STACK) and a number
3906 // representing the register number (i.e. - use a register name) or
3907 // stack slot.
3908 //
3909 // A: Link register is stored in stack slot ...
3910 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3911 // J: Therefore, we make sure that the link register is also in R11_scratch1
3912 // at the end of the prolog.
3913 // B: We use R20, now.
3914 //return_addr(REG R20);
3915
3916 // G: After reading the comments made by all the luminaries on their
3917 // failure to tell the compiler where the return address really is,
3918 // I hardly dare to try myself. However, I'm convinced it's in slot
3919 // 4 what apparently works and saves us some spills.
3920 return_addr(STACK 4);
3921
3922 // This is the body of the function
3923 //
3924 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3925 // uint length, // length of array
3926 // bool is_outgoing)
3927 //
3928 // The `sig' array is to be updated. sig[j] represents the location
3929 // of the j-th argument, either a register or a stack slot.
3930
3931 // Comment taken from i486.ad:
3932 // Body of function which returns an integer array locating
3933 // arguments either in registers or in stack slots. Passed an array
3934 // of ideal registers called "sig" and a "length" count. Stack-slot
3935 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3936 // arguments for a CALLEE. Incoming stack arguments are
3937 // automatically biased by the preserve_stack_slots field above.
3938 calling_convention %{
3939 // No difference between ingoing/outgoing. Just pass false.
3940 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3941 %}
3942
3943 // Comment taken from i486.ad:
3944 // Body of function which returns an integer array locating
3945 // arguments either in registers or in stack slots. Passed an array
3946 // of ideal registers called "sig" and a "length" count. Stack-slot
3947 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3948 // arguments for a CALLEE. Incoming stack arguments are
3949 // automatically biased by the preserve_stack_slots field above.
3950 c_calling_convention %{
3951 // This is obviously always outgoing.
3952 // C argument in register AND stack slot.
3953 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3954 %}
3955
3956 // Location of native (C/C++) and interpreter return values. This
3957 // is specified to be the same as Java. In the 32-bit VM, long
3958 // values are actually returned from native calls in O0:O1 and
3959 // returned to the interpreter in I0:I1. The copying to and from
3960 // the register pairs is done by the appropriate call and epilog
3961 // opcodes. This simplifies the register allocator.
3962 c_return_value %{
3963 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3964 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3965 "only return normal values");
3966 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3967 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3968 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3969 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3970 %}
3971
3972 // Location of compiled Java return values. Same as C
3973 return_value %{
3974 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3975 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3976 "only return normal values");
3977 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3978 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3979 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3980 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3981 %}
3982 %}
3983
3984
3985 //----------ATTRIBUTES---------------------------------------------------------
3986
3987 //----------Operand Attributes-------------------------------------------------
3988 op_attrib op_cost(1); // Required cost attribute.
3989
3990 //----------Instruction Attributes---------------------------------------------
3991
3992 // Cost attribute. required.
3993 ins_attrib ins_cost(DEFAULT_COST);
3994
3995 // Is this instruction a non-matching short branch variant of some
3996 // long branch? Not required.
3997 ins_attrib ins_short_branch(0);
3998
3999 ins_attrib ins_is_TrapBasedCheckNode(true);
4000
4001 // Number of constants.
4002 // This instruction uses the given number of constants
4003 // (optional attribute).
4004 // This is needed to determine in time whether the constant pool will
4005 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4006 // is determined. It's also used to compute the constant pool size
4007 // in Output().
4008 ins_attrib ins_num_consts(0);
4009
4010 // Required alignment attribute (must be a power of 2) specifies the
4011 // alignment that some part of the instruction (not necessarily the
4012 // start) requires. If > 1, a compute_padding() function must be
4013 // provided for the instruction.
4014 ins_attrib ins_alignment(1);
4015
4016 // Enforce/prohibit rematerializations.
4017 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4018 // then rematerialization of that instruction is prohibited and the
4019 // instruction's value will be spilled if necessary.
4020 // Causes that MachNode::rematerialize() returns false.
4021 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4022 // then rematerialization should be enforced and a copy of the instruction
4023 // should be inserted if possible; rematerialization is not guaranteed.
4024 // Note: this may result in rematerializations in front of every use.
4025 // Causes that MachNode::rematerialize() can return true.
4026 // (optional attribute)
4027 ins_attrib ins_cannot_rematerialize(false);
4028 ins_attrib ins_should_rematerialize(false);
4029
4030 // Instruction has variable size depending on alignment.
4031 ins_attrib ins_variable_size_depending_on_alignment(false);
4032
4033 // Instruction is a nop.
4034 ins_attrib ins_is_nop(false);
4035
4036 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4037 ins_attrib ins_use_mach_if_fast_lock_node(false);
4038
4039 // Field for the toc offset of a constant.
4040 //
4041 // This is needed if the toc offset is not encodable as an immediate in
4042 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4043 // added to the toc, and from this a load with immediate is performed.
4044 // With postalloc expand, we get two nodes that require the same offset
4045 // but which don't know about each other. The offset is only known
4046 // when the constant is added to the constant pool during emitting.
4047 // It is generated in the 'hi'-node adding the upper bits, and saved
4048 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4049 // the offset from there when it gets encoded.
4050 ins_attrib ins_field_const_toc_offset(0);
4051 ins_attrib ins_field_const_toc_offset_hi_node(0);
4052
4053 // A field that can hold the instructions offset in the code buffer.
4054 // Set in the nodes emitter.
4055 ins_attrib ins_field_cbuf_insts_offset(-1);
4056
4057 // Fields for referencing a call's load-IC-node.
4058 // If the toc offset can not be encoded as an immediate in a load, we
4059 // use two nodes.
4060 ins_attrib ins_field_load_ic_hi_node(0);
4061 ins_attrib ins_field_load_ic_node(0);
4062
4063 //----------OPERANDS-----------------------------------------------------------
4064 // Operand definitions must precede instruction definitions for correct
4065 // parsing in the ADLC because operands constitute user defined types
4066 // which are used in instruction definitions.
4067 //
4068 // Formats are generated automatically for constants and base registers.
4069
4070 //----------Simple Operands----------------------------------------------------
4071 // Immediate Operands
4072
4073 // Integer Immediate: 32-bit
4074 operand immI() %{
4075 match(ConI);
4076 op_cost(40);
4077 format %{ %}
4078 interface(CONST_INTER);
4079 %}
4080
4081 operand immI8() %{
4082 predicate(Assembler::is_simm(n->get_int(), 8));
4083 op_cost(0);
4084 match(ConI);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4088
4089 // Integer Immediate: 16-bit
4090 operand immI16() %{
4091 predicate(Assembler::is_simm(n->get_int(), 16));
4092 op_cost(0);
4093 match(ConI);
4094 format %{ %}
4095 interface(CONST_INTER);
4096 %}
4097
4098 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4099 operand immIhi16() %{
4100 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4101 match(ConI);
4102 op_cost(0);
4103 format %{ %}
4104 interface(CONST_INTER);
4105 %}
4106
4107 operand immInegpow2() %{
4108 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4109 match(ConI);
4110 op_cost(0);
4111 format %{ %}
4112 interface(CONST_INTER);
4113 %}
4114
4115 operand immIpow2minus1() %{
4116 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4117 match(ConI);
4118 op_cost(0);
4119 format %{ %}
4120 interface(CONST_INTER);
4121 %}
4122
4123 operand immIpowerOf2() %{
4124 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4125 match(ConI);
4126 op_cost(0);
4127 format %{ %}
4128 interface(CONST_INTER);
4129 %}
4130
4131 // Unsigned Integer Immediate: the values 0-31
4132 operand uimmI5() %{
4133 predicate(Assembler::is_uimm(n->get_int(), 5));
4134 match(ConI);
4135 op_cost(0);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4139
4140 // Unsigned Integer Immediate: 6-bit
4141 operand uimmI6() %{
4142 predicate(Assembler::is_uimm(n->get_int(), 6));
4143 match(ConI);
4144 op_cost(0);
4145 format %{ %}
4146 interface(CONST_INTER);
4147 %}
4148
4149 // Unsigned Integer Immediate: 6-bit int, greater than 32
4150 operand uimmI6_ge32() %{
4151 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4152 match(ConI);
4153 op_cost(0);
4154 format %{ %}
4155 interface(CONST_INTER);
4156 %}
4157
4158 // Unsigned Integer Immediate: 15-bit
4159 operand uimmI15() %{
4160 predicate(Assembler::is_uimm(n->get_int(), 15));
4161 match(ConI);
4162 op_cost(0);
4163 format %{ %}
4164 interface(CONST_INTER);
4165 %}
4166
4167 // Unsigned Integer Immediate: 16-bit
4168 operand uimmI16() %{
4169 predicate(Assembler::is_uimm(n->get_int(), 16));
4170 match(ConI);
4171 op_cost(0);
4172 format %{ %}
4173 interface(CONST_INTER);
4174 %}
4175
4176 // constant 'int 0'.
4177 operand immI_0() %{
4178 predicate(n->get_int() == 0);
4179 match(ConI);
4180 op_cost(0);
4181 format %{ %}
4182 interface(CONST_INTER);
4183 %}
4184
4185 // constant 'int 1'.
4186 operand immI_1() %{
4187 predicate(n->get_int() == 1);
4188 match(ConI);
4189 op_cost(0);
4190 format %{ %}
4191 interface(CONST_INTER);
4192 %}
4193
4194 // constant 'int -1'.
4195 operand immI_minus1() %{
4196 predicate(n->get_int() == -1);
4197 match(ConI);
4198 op_cost(0);
4199 format %{ %}
4200 interface(CONST_INTER);
4201 %}
4202
4203 // int value 16.
4204 operand immI_16() %{
4205 predicate(n->get_int() == 16);
4206 match(ConI);
4207 op_cost(0);
4208 format %{ %}
4209 interface(CONST_INTER);
4210 %}
4211
4212 // int value 24.
4213 operand immI_24() %{
4214 predicate(n->get_int() == 24);
4215 match(ConI);
4216 op_cost(0);
4217 format %{ %}
4218 interface(CONST_INTER);
4219 %}
4220
4221 // Compressed oops constants
4222 // Pointer Immediate
4223 operand immN() %{
4224 match(ConN);
4225
4226 op_cost(10);
4227 format %{ %}
4228 interface(CONST_INTER);
4229 %}
4230
4231 // NULL Pointer Immediate
4232 operand immN_0() %{
4233 predicate(n->get_narrowcon() == 0);
4234 match(ConN);
4235
4236 op_cost(0);
4237 format %{ %}
4238 interface(CONST_INTER);
4239 %}
4240
4241 // Compressed klass constants
4242 operand immNKlass() %{
4243 match(ConNKlass);
4244
4245 op_cost(0);
4246 format %{ %}
4247 interface(CONST_INTER);
4248 %}
4249
4250 // This operand can be used to avoid matching of an instruct
4251 // with chain rule.
4252 operand immNKlass_NM() %{
4253 match(ConNKlass);
4254 predicate(false);
4255 op_cost(0);
4256 format %{ %}
4257 interface(CONST_INTER);
4258 %}
4259
4260 // Pointer Immediate: 64-bit
4261 operand immP() %{
4262 match(ConP);
4263 op_cost(0);
4264 format %{ %}
4265 interface(CONST_INTER);
4266 %}
4267
4268 // Operand to avoid match of loadConP.
4269 // This operand can be used to avoid matching of an instruct
4270 // with chain rule.
4271 operand immP_NM() %{
4272 match(ConP);
4273 predicate(false);
4274 op_cost(0);
4275 format %{ %}
4276 interface(CONST_INTER);
4277 %}
4278
4279 // costant 'pointer 0'.
4280 operand immP_0() %{
4281 predicate(n->get_ptr() == 0);
4282 match(ConP);
4283 op_cost(0);
4284 format %{ %}
4285 interface(CONST_INTER);
4286 %}
4287
4288 // pointer 0x0 or 0x1
4289 operand immP_0or1() %{
4290 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4291 match(ConP);
4292 op_cost(0);
4293 format %{ %}
4294 interface(CONST_INTER);
4295 %}
4296
4297 operand immL() %{
4298 match(ConL);
4299 op_cost(40);
4300 format %{ %}
4301 interface(CONST_INTER);
4302 %}
4303
4304 // Long Immediate: 16-bit
4305 operand immL16() %{
4306 predicate(Assembler::is_simm(n->get_long(), 16));
4307 match(ConL);
4308 op_cost(0);
4309 format %{ %}
4310 interface(CONST_INTER);
4311 %}
4312
4313 // Long Immediate: 16-bit, 4-aligned
4314 operand immL16Alg4() %{
4315 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4316 match(ConL);
4317 op_cost(0);
4318 format %{ %}
4319 interface(CONST_INTER);
4320 %}
4321
4322 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4323 operand immL32hi16() %{
4324 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4325 match(ConL);
4326 op_cost(0);
4327 format %{ %}
4328 interface(CONST_INTER);
4329 %}
4330
4331 // Long Immediate: 32-bit
4332 operand immL32() %{
4333 predicate(Assembler::is_simm(n->get_long(), 32));
4334 match(ConL);
4335 op_cost(0);
4336 format %{ %}
4337 interface(CONST_INTER);
4338 %}
4339
4340 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4341 operand immLhighest16() %{
4342 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4343 match(ConL);
4344 op_cost(0);
4345 format %{ %}
4346 interface(CONST_INTER);
4347 %}
4348
4349 operand immLnegpow2() %{
4350 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4351 match(ConL);
4352 op_cost(0);
4353 format %{ %}
4354 interface(CONST_INTER);
4355 %}
4356
4357 operand immLpow2minus1() %{
4358 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4359 (n->get_long() != (jlong)0xffffffffffffffffL));
4360 match(ConL);
4361 op_cost(0);
4362 format %{ %}
4363 interface(CONST_INTER);
4364 %}
4365
4366 // constant 'long 0'.
4367 operand immL_0() %{
4368 predicate(n->get_long() == 0L);
4369 match(ConL);
4370 op_cost(0);
4371 format %{ %}
4372 interface(CONST_INTER);
4373 %}
4374
4375 // constat ' long -1'.
4376 operand immL_minus1() %{
4377 predicate(n->get_long() == -1L);
4378 match(ConL);
4379 op_cost(0);
4380 format %{ %}
4381 interface(CONST_INTER);
4382 %}
4383
4384 // Long Immediate: low 32-bit mask
4385 operand immL_32bits() %{
4386 predicate(n->get_long() == 0xFFFFFFFFL);
4387 match(ConL);
4388 op_cost(0);
4389 format %{ %}
4390 interface(CONST_INTER);
4391 %}
4392
4393 // Unsigned Long Immediate: 16-bit
4394 operand uimmL16() %{
4395 predicate(Assembler::is_uimm(n->get_long(), 16));
4396 match(ConL);
4397 op_cost(0);
4398 format %{ %}
4399 interface(CONST_INTER);
4400 %}
4401
4402 // Float Immediate
4403 operand immF() %{
4404 match(ConF);
4405 op_cost(40);
4406 format %{ %}
4407 interface(CONST_INTER);
4408 %}
4409
4410 // constant 'float +0.0'.
4411 operand immF_0() %{
4412 predicate((n->getf() == 0) &&
4413 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4414 match(ConF);
4415 op_cost(0);
4416 format %{ %}
4417 interface(CONST_INTER);
4418 %}
4419
4420 // Double Immediate
4421 operand immD() %{
4422 match(ConD);
4423 op_cost(40);
4424 format %{ %}
4425 interface(CONST_INTER);
4426 %}
4427
4428 // Integer Register Operands
4429 // Integer Destination Register
4430 // See definition of reg_class bits32_reg_rw.
4431 operand iRegIdst() %{
4432 constraint(ALLOC_IN_RC(bits32_reg_rw));
4433 match(RegI);
4434 match(rscratch1RegI);
4435 match(rscratch2RegI);
4436 match(rarg1RegI);
4437 match(rarg2RegI);
4438 match(rarg3RegI);
4439 match(rarg4RegI);
4440 format %{ %}
4441 interface(REG_INTER);
4442 %}
4443
4444 // Integer Source Register
4445 // See definition of reg_class bits32_reg_ro.
4446 operand iRegIsrc() %{
4447 constraint(ALLOC_IN_RC(bits32_reg_ro));
4448 match(RegI);
4449 match(rscratch1RegI);
4450 match(rscratch2RegI);
4451 match(rarg1RegI);
4452 match(rarg2RegI);
4453 match(rarg3RegI);
4454 match(rarg4RegI);
4455 format %{ %}
4456 interface(REG_INTER);
4457 %}
4458
4459 operand rscratch1RegI() %{
4460 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4461 match(iRegIdst);
4462 format %{ %}
4463 interface(REG_INTER);
4464 %}
4465
4466 operand rscratch2RegI() %{
4467 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4468 match(iRegIdst);
4469 format %{ %}
4470 interface(REG_INTER);
4471 %}
4472
4473 operand rarg1RegI() %{
4474 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4475 match(iRegIdst);
4476 format %{ %}
4477 interface(REG_INTER);
4478 %}
4479
4480 operand rarg2RegI() %{
4481 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4482 match(iRegIdst);
4483 format %{ %}
4484 interface(REG_INTER);
4485 %}
4486
4487 operand rarg3RegI() %{
4488 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4489 match(iRegIdst);
4490 format %{ %}
4491 interface(REG_INTER);
4492 %}
4493
4494 operand rarg4RegI() %{
4495 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4496 match(iRegIdst);
4497 format %{ %}
4498 interface(REG_INTER);
4499 %}
4500
4501 operand rarg1RegL() %{
4502 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4503 match(iRegLdst);
4504 format %{ %}
4505 interface(REG_INTER);
4506 %}
4507
4508 operand rarg2RegL() %{
4509 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4510 match(iRegLdst);
4511 format %{ %}
4512 interface(REG_INTER);
4513 %}
4514
4515 operand rarg3RegL() %{
4516 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4517 match(iRegLdst);
4518 format %{ %}
4519 interface(REG_INTER);
4520 %}
4521
4522 operand rarg4RegL() %{
4523 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4524 match(iRegLdst);
4525 format %{ %}
4526 interface(REG_INTER);
4527 %}
4528
4529 // Pointer Destination Register
4530 // See definition of reg_class bits64_reg_rw.
4531 operand iRegPdst() %{
4532 constraint(ALLOC_IN_RC(bits64_reg_rw));
4533 match(RegP);
4534 match(rscratch1RegP);
4535 match(rscratch2RegP);
4536 match(rarg1RegP);
4537 match(rarg2RegP);
4538 match(rarg3RegP);
4539 match(rarg4RegP);
4540 format %{ %}
4541 interface(REG_INTER);
4542 %}
4543
4544 // Pointer Destination Register
4545 // Operand not using r11 and r12 (killed in epilog).
4546 operand iRegPdstNoScratch() %{
4547 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4548 match(RegP);
4549 match(rarg1RegP);
4550 match(rarg2RegP);
4551 match(rarg3RegP);
4552 match(rarg4RegP);
4553 format %{ %}
4554 interface(REG_INTER);
4555 %}
4556
4557 // Pointer Source Register
4558 // See definition of reg_class bits64_reg_ro.
4559 operand iRegPsrc() %{
4560 constraint(ALLOC_IN_RC(bits64_reg_ro));
4561 match(RegP);
4562 match(iRegPdst);
4563 match(rscratch1RegP);
4564 match(rscratch2RegP);
4565 match(rarg1RegP);
4566 match(rarg2RegP);
4567 match(rarg3RegP);
4568 match(rarg4RegP);
4569 match(threadRegP);
4570 format %{ %}
4571 interface(REG_INTER);
4572 %}
4573
4574 // Thread operand.
4575 operand threadRegP() %{
4576 constraint(ALLOC_IN_RC(thread_bits64_reg));
4577 match(iRegPdst);
4578 format %{ "R16" %}
4579 interface(REG_INTER);
4580 %}
4581
4582 operand rscratch1RegP() %{
4583 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4584 match(iRegPdst);
4585 format %{ "R11" %}
4586 interface(REG_INTER);
4587 %}
4588
4589 operand rscratch2RegP() %{
4590 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4591 match(iRegPdst);
4592 format %{ %}
4593 interface(REG_INTER);
4594 %}
4595
4596 operand rarg1RegP() %{
4597 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4598 match(iRegPdst);
4599 format %{ %}
4600 interface(REG_INTER);
4601 %}
4602
4603 operand rarg2RegP() %{
4604 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4605 match(iRegPdst);
4606 format %{ %}
4607 interface(REG_INTER);
4608 %}
4609
4610 operand rarg3RegP() %{
4611 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4612 match(iRegPdst);
4613 format %{ %}
4614 interface(REG_INTER);
4615 %}
4616
4617 operand rarg4RegP() %{
4618 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4619 match(iRegPdst);
4620 format %{ %}
4621 interface(REG_INTER);
4622 %}
4623
4624 operand iRegNsrc() %{
4625 constraint(ALLOC_IN_RC(bits32_reg_ro));
4626 match(RegN);
4627 match(iRegNdst);
4628
4629 format %{ %}
4630 interface(REG_INTER);
4631 %}
4632
4633 operand iRegNdst() %{
4634 constraint(ALLOC_IN_RC(bits32_reg_rw));
4635 match(RegN);
4636
4637 format %{ %}
4638 interface(REG_INTER);
4639 %}
4640
4641 // Long Destination Register
4642 // See definition of reg_class bits64_reg_rw.
4643 operand iRegLdst() %{
4644 constraint(ALLOC_IN_RC(bits64_reg_rw));
4645 match(RegL);
4646 match(rscratch1RegL);
4647 match(rscratch2RegL);
4648 format %{ %}
4649 interface(REG_INTER);
4650 %}
4651
4652 // Long Source Register
4653 // See definition of reg_class bits64_reg_ro.
4654 operand iRegLsrc() %{
4655 constraint(ALLOC_IN_RC(bits64_reg_ro));
4656 match(RegL);
4657 match(iRegLdst);
4658 match(rscratch1RegL);
4659 match(rscratch2RegL);
4660 format %{ %}
4661 interface(REG_INTER);
4662 %}
4663
4664 // Special operand for ConvL2I.
4665 operand iRegL2Isrc(iRegLsrc reg) %{
4666 constraint(ALLOC_IN_RC(bits64_reg_ro));
4667 match(ConvL2I reg);
4668 format %{ "ConvL2I($reg)" %}
4669 interface(REG_INTER)
4670 %}
4671
4672 operand rscratch1RegL() %{
4673 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4674 match(RegL);
4675 format %{ %}
4676 interface(REG_INTER);
4677 %}
4678
4679 operand rscratch2RegL() %{
4680 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4681 match(RegL);
4682 format %{ %}
4683 interface(REG_INTER);
4684 %}
4685
4686 // Condition Code Flag Registers
4687 operand flagsReg() %{
4688 constraint(ALLOC_IN_RC(int_flags));
4689 match(RegFlags);
4690 format %{ %}
4691 interface(REG_INTER);
4692 %}
4693
4694 // Condition Code Flag Register CR0
4695 operand flagsRegCR0() %{
4696 constraint(ALLOC_IN_RC(int_flags_CR0));
4697 match(RegFlags);
4698 format %{ "CR0" %}
4699 interface(REG_INTER);
4700 %}
4701
4702 operand flagsRegCR1() %{
4703 constraint(ALLOC_IN_RC(int_flags_CR1));
4704 match(RegFlags);
4705 format %{ "CR1" %}
4706 interface(REG_INTER);
4707 %}
4708
4709 operand flagsRegCR6() %{
4710 constraint(ALLOC_IN_RC(int_flags_CR6));
4711 match(RegFlags);
4712 format %{ "CR6" %}
4713 interface(REG_INTER);
4714 %}
4715
4716 operand regCTR() %{
4717 constraint(ALLOC_IN_RC(ctr_reg));
4718 // RegFlags should work. Introducing a RegSpecial type would cause a
4719 // lot of changes.
4720 match(RegFlags);
4721 format %{"SR_CTR" %}
4722 interface(REG_INTER);
4723 %}
4724
4725 operand regD() %{
4726 constraint(ALLOC_IN_RC(dbl_reg));
4727 match(RegD);
4728 format %{ %}
4729 interface(REG_INTER);
4730 %}
4731
4732 operand regF() %{
4733 constraint(ALLOC_IN_RC(flt_reg));
4734 match(RegF);
4735 format %{ %}
4736 interface(REG_INTER);
4737 %}
4738
4739 // Special Registers
4740
4741 // Method Register
4742 operand inline_cache_regP(iRegPdst reg) %{
4743 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4744 match(reg);
4745 format %{ %}
4746 interface(REG_INTER);
4747 %}
4748
4749 operand compiler_method_oop_regP(iRegPdst reg) %{
4750 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4751 match(reg);
4752 format %{ %}
4753 interface(REG_INTER);
4754 %}
4755
4756 operand interpreter_method_oop_regP(iRegPdst reg) %{
4757 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4758 match(reg);
4759 format %{ %}
4760 interface(REG_INTER);
4761 %}
4762
4763 // Operands to remove register moves in unscaled mode.
4764 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4765 operand iRegP2N(iRegPsrc reg) %{
4766 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4767 constraint(ALLOC_IN_RC(bits64_reg_ro));
4768 match(EncodeP reg);
4769 format %{ "$reg" %}
4770 interface(REG_INTER)
4771 %}
4772
4773 operand iRegN2P(iRegNsrc reg) %{
4774 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4775 constraint(ALLOC_IN_RC(bits32_reg_ro));
4776 match(DecodeN reg);
4777 match(DecodeNKlass reg);
4778 format %{ "$reg" %}
4779 interface(REG_INTER)
4780 %}
4781
4782 //----------Complex Operands---------------------------------------------------
4783 // Indirect Memory Reference
4784 operand indirect(iRegPsrc reg) %{
4785 constraint(ALLOC_IN_RC(bits64_reg_ro));
4786 match(reg);
4787 op_cost(100);
4788 format %{ "[$reg]" %}
4789 interface(MEMORY_INTER) %{
4790 base($reg);
4791 index(0x0);
4792 scale(0x0);
4793 disp(0x0);
4794 %}
4795 %}
4796
4797 // Indirect with Offset
4798 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4799 constraint(ALLOC_IN_RC(bits64_reg_ro));
4800 match(AddP reg offset);
4801 op_cost(100);
4802 format %{ "[$reg + $offset]" %}
4803 interface(MEMORY_INTER) %{
4804 base($reg);
4805 index(0x0);
4806 scale(0x0);
4807 disp($offset);
4808 %}
4809 %}
4810
4811 // Indirect with 4-aligned Offset
4812 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4813 constraint(ALLOC_IN_RC(bits64_reg_ro));
4814 match(AddP reg offset);
4815 op_cost(100);
4816 format %{ "[$reg + $offset]" %}
4817 interface(MEMORY_INTER) %{
4818 base($reg);
4819 index(0x0);
4820 scale(0x0);
4821 disp($offset);
4822 %}
4823 %}
4824
4825 //----------Complex Operands for Compressed OOPs-------------------------------
4826 // Compressed OOPs with narrow_oop_shift == 0.
4827
4828 // Indirect Memory Reference, compressed OOP
4829 operand indirectNarrow(iRegNsrc reg) %{
4830 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4831 constraint(ALLOC_IN_RC(bits64_reg_ro));
4832 match(DecodeN reg);
4833 match(DecodeNKlass reg);
4834 op_cost(100);
4835 format %{ "[$reg]" %}
4836 interface(MEMORY_INTER) %{
4837 base($reg);
4838 index(0x0);
4839 scale(0x0);
4840 disp(0x0);
4841 %}
4842 %}
4843
4844 // Indirect with Offset, compressed OOP
4845 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4846 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4847 constraint(ALLOC_IN_RC(bits64_reg_ro));
4848 match(AddP (DecodeN reg) offset);
4849 match(AddP (DecodeNKlass reg) offset);
4850 op_cost(100);
4851 format %{ "[$reg + $offset]" %}
4852 interface(MEMORY_INTER) %{
4853 base($reg);
4854 index(0x0);
4855 scale(0x0);
4856 disp($offset);
4857 %}
4858 %}
4859
4860 // Indirect with 4-aligned Offset, compressed OOP
4861 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4862 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4863 constraint(ALLOC_IN_RC(bits64_reg_ro));
4864 match(AddP (DecodeN reg) offset);
4865 match(AddP (DecodeNKlass reg) offset);
4866 op_cost(100);
4867 format %{ "[$reg + $offset]" %}
4868 interface(MEMORY_INTER) %{
4869 base($reg);
4870 index(0x0);
4871 scale(0x0);
4872 disp($offset);
4873 %}
4874 %}
4875
4876 //----------Special Memory Operands--------------------------------------------
4877 // Stack Slot Operand
4878 //
4879 // This operand is used for loading and storing temporary values on
4880 // the stack where a match requires a value to flow through memory.
4881 operand stackSlotI(sRegI reg) %{
4882 constraint(ALLOC_IN_RC(stack_slots));
4883 op_cost(100);
4884 //match(RegI);
4885 format %{ "[sp+$reg]" %}
4886 interface(MEMORY_INTER) %{
4887 base(0x1); // R1_SP
4888 index(0x0);
4889 scale(0x0);
4890 disp($reg); // Stack Offset
4891 %}
4892 %}
4893
4894 operand stackSlotL(sRegL reg) %{
4895 constraint(ALLOC_IN_RC(stack_slots));
4896 op_cost(100);
4897 //match(RegL);
4898 format %{ "[sp+$reg]" %}
4899 interface(MEMORY_INTER) %{
4900 base(0x1); // R1_SP
4901 index(0x0);
4902 scale(0x0);
4903 disp($reg); // Stack Offset
4904 %}
4905 %}
4906
4907 operand stackSlotP(sRegP reg) %{
4908 constraint(ALLOC_IN_RC(stack_slots));
4909 op_cost(100);
4910 //match(RegP);
4911 format %{ "[sp+$reg]" %}
4912 interface(MEMORY_INTER) %{
4913 base(0x1); // R1_SP
4914 index(0x0);
4915 scale(0x0);
4916 disp($reg); // Stack Offset
4917 %}
4918 %}
4919
4920 operand stackSlotF(sRegF reg) %{
4921 constraint(ALLOC_IN_RC(stack_slots));
4922 op_cost(100);
4923 //match(RegF);
4924 format %{ "[sp+$reg]" %}
4925 interface(MEMORY_INTER) %{
4926 base(0x1); // R1_SP
4927 index(0x0);
4928 scale(0x0);
4929 disp($reg); // Stack Offset
4930 %}
4931 %}
4932
4933 operand stackSlotD(sRegD reg) %{
4934 constraint(ALLOC_IN_RC(stack_slots));
4935 op_cost(100);
4936 //match(RegD);
4937 format %{ "[sp+$reg]" %}
4938 interface(MEMORY_INTER) %{
4939 base(0x1); // R1_SP
4940 index(0x0);
4941 scale(0x0);
4942 disp($reg); // Stack Offset
4943 %}
4944 %}
4945
4946 // Operands for expressing Control Flow
4947 // NOTE: Label is a predefined operand which should not be redefined in
4948 // the AD file. It is generically handled within the ADLC.
4949
4950 //----------Conditional Branch Operands----------------------------------------
4951 // Comparison Op
4952 //
4953 // This is the operation of the comparison, and is limited to the
4954 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4955 // (!=).
4956 //
4957 // Other attributes of the comparison, such as unsignedness, are specified
4958 // by the comparison instruction that sets a condition code flags register.
4959 // That result is represented by a flags operand whose subtype is appropriate
4960 // to the unsignedness (etc.) of the comparison.
4961 //
4962 // Later, the instruction which matches both the Comparison Op (a Bool) and
4963 // the flags (produced by the Cmp) specifies the coding of the comparison op
4964 // by matching a specific subtype of Bool operand below.
4965
4966 // When used for floating point comparisons: unordered same as less.
4967 operand cmpOp() %{
4968 match(Bool);
4969 format %{ "" %}
4970 interface(COND_INTER) %{
4971 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4972 // BO & BI
4973 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4974 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4975 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4976 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4977 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4978 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4979 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4980 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4981 %}
4982 %}
4983
4984 //----------OPERAND CLASSES----------------------------------------------------
4985 // Operand Classes are groups of operands that are used to simplify
4986 // instruction definitions by not requiring the AD writer to specify
4987 // seperate instructions for every form of operand when the
4988 // instruction accepts multiple operand types with the same basic
4989 // encoding and format. The classic case of this is memory operands.
4990 // Indirect is not included since its use is limited to Compare & Swap.
4991
4992 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4993 // Memory operand where offsets are 4-aligned. Required for ld, std.
4994 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
4995 opclass indirectMemory(indirect, indirectNarrow);
4996
4997 // Special opclass for I and ConvL2I.
4998 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4999
5000 // Operand classes to match encode and decode. iRegN_P2N is only used
5001 // for storeN. I have never seen an encode node elsewhere.
5002 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5003 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5004
5005 //----------PIPELINE-----------------------------------------------------------
5006
5007 pipeline %{
5008
5009 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5010 // J. Res. & Dev., No. 1, Jan. 2002.
5011
5012 //----------ATTRIBUTES---------------------------------------------------------
5013 attributes %{
5014
5015 // Power4 instructions are of fixed length.
5016 fixed_size_instructions;
5017
5018 // TODO: if `bundle' means number of instructions fetched
5019 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5020 // max instructions issued per cycle, this is 5.
5021 max_instructions_per_bundle = 8;
5022
5023 // A Power4 instruction is 4 bytes long.
5024 instruction_unit_size = 4;
5025
5026 // The Power4 processor fetches 64 bytes...
5027 instruction_fetch_unit_size = 64;
5028
5029 // ...in one line
5030 instruction_fetch_units = 1
5031
5032 // Unused, list one so that array generated by adlc is not empty.
5033 // Aix compiler chokes if _nop_count = 0.
5034 nops(fxNop);
5035 %}
5036
5037 //----------RESOURCES----------------------------------------------------------
5038 // Resources are the functional units available to the machine
5039 resources(
5040 PPC_BR, // branch unit
5041 PPC_CR, // condition unit
5042 PPC_FX1, // integer arithmetic unit 1
5043 PPC_FX2, // integer arithmetic unit 2
5044 PPC_LDST1, // load/store unit 1
5045 PPC_LDST2, // load/store unit 2
5046 PPC_FP1, // float arithmetic unit 1
5047 PPC_FP2, // float arithmetic unit 2
5048 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5049 PPC_FX = PPC_FX1 | PPC_FX2,
5050 PPC_FP = PPC_FP1 | PPC_FP2
5051 );
5052
5053 //----------PIPELINE DESCRIPTION-----------------------------------------------
5054 // Pipeline Description specifies the stages in the machine's pipeline
5055 pipe_desc(
5056 // Power4 longest pipeline path
5057 PPC_IF, // instruction fetch
5058 PPC_IC,
5059 //PPC_BP, // branch prediction
5060 PPC_D0, // decode
5061 PPC_D1, // decode
5062 PPC_D2, // decode
5063 PPC_D3, // decode
5064 PPC_Xfer1,
5065 PPC_GD, // group definition
5066 PPC_MP, // map
5067 PPC_ISS, // issue
5068 PPC_RF, // resource fetch
5069 PPC_EX1, // execute (all units)
5070 PPC_EX2, // execute (FP, LDST)
5071 PPC_EX3, // execute (FP, LDST)
5072 PPC_EX4, // execute (FP)
5073 PPC_EX5, // execute (FP)
5074 PPC_EX6, // execute (FP)
5075 PPC_WB, // write back
5076 PPC_Xfer2,
5077 PPC_CP
5078 );
5079
5080 //----------PIPELINE CLASSES---------------------------------------------------
5081 // Pipeline Classes describe the stages in which input and output are
5082 // referenced by the hardware pipeline.
5083
5084 // Simple pipeline classes.
5085
5086 // Default pipeline class.
5087 pipe_class pipe_class_default() %{
5088 single_instruction;
5089 fixed_latency(2);
5090 %}
5091
5092 // Pipeline class for empty instructions.
5093 pipe_class pipe_class_empty() %{
5094 single_instruction;
5095 fixed_latency(0);
5096 %}
5097
5098 // Pipeline class for compares.
5099 pipe_class pipe_class_compare() %{
5100 single_instruction;
5101 fixed_latency(16);
5102 %}
5103
5104 // Pipeline class for traps.
5105 pipe_class pipe_class_trap() %{
5106 single_instruction;
5107 fixed_latency(100);
5108 %}
5109
5110 // Pipeline class for memory operations.
5111 pipe_class pipe_class_memory() %{
5112 single_instruction;
5113 fixed_latency(16);
5114 %}
5115
5116 // Pipeline class for call.
5117 pipe_class pipe_class_call() %{
5118 single_instruction;
5119 fixed_latency(100);
5120 %}
5121
5122 // Define the class for the Nop node.
5123 define %{
5124 MachNop = pipe_class_default;
5125 %}
5126
5127 %}
5128
5129 //----------INSTRUCTIONS-------------------------------------------------------
5130
5131 // Naming of instructions:
5132 // opA_operB / opA_operB_operC:
5133 // Operation 'op' with one or two source operands 'oper'. Result
5134 // type is A, source operand types are B and C.
5135 // Iff A == B == C, B and C are left out.
5136 //
5137 // The instructions are ordered according to the following scheme:
5138 // - loads
5139 // - load constants
5140 // - prefetch
5141 // - store
5142 // - encode/decode
5143 // - membar
5144 // - conditional moves
5145 // - compare & swap
5146 // - arithmetic and logic operations
5147 // * int: Add, Sub, Mul, Div, Mod
5148 // * int: lShift, arShift, urShift, rot
5149 // * float: Add, Sub, Mul, Div
5150 // * and, or, xor ...
5151 // - register moves: float <-> int, reg <-> stack, repl
5152 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5153 // - conv (low level type cast requiring bit changes (sign extend etc)
5154 // - compares, range & zero checks.
5155 // - branches
5156 // - complex operations, intrinsics, min, max, replicate
5157 // - lock
5158 // - Calls
5159 //
5160 // If there are similar instructions with different types they are sorted:
5161 // int before float
5162 // small before big
5163 // signed before unsigned
5164 // e.g., loadS before loadUS before loadI before loadF.
5165
5166
5167 //----------Load/Store Instructions--------------------------------------------
5168
5169 //----------Load Instructions--------------------------------------------------
5170
5171 // Converts byte to int.
5172 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5173 // reuses the 'amount' operand, but adlc expects that operand specification
5174 // and operands in match rule are equivalent.
5175 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5176 effect(DEF dst, USE src);
5177 format %{ "EXTSB $dst, $src \t// byte->int" %}
5178 size(4);
5179 ins_encode %{
5180 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5181 __ extsb($dst$$Register, $src$$Register);
5182 %}
5183 ins_pipe(pipe_class_default);
5184 %}
5185
5186 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5187 // match-rule, false predicate
5188 match(Set dst (LoadB mem));
5189 predicate(false);
5190
5191 format %{ "LBZ $dst, $mem" %}
5192 size(4);
5193 ins_encode( enc_lbz(dst, mem) );
5194 ins_pipe(pipe_class_memory);
5195 %}
5196
5197 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5198 // match-rule, false predicate
5199 match(Set dst (LoadB mem));
5200 predicate(false);
5201
5202 format %{ "LBZ $dst, $mem\n\t"
5203 "TWI $dst\n\t"
5204 "ISYNC" %}
5205 size(12);
5206 ins_encode( enc_lbz_ac(dst, mem) );
5207 ins_pipe(pipe_class_memory);
5208 %}
5209
5210 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5211 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5212 match(Set dst (LoadB mem));
5213 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5214 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5215 expand %{
5216 iRegIdst tmp;
5217 loadUB_indirect(tmp, mem);
5218 convB2I_reg_2(dst, tmp);
5219 %}
5220 %}
5221
5222 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5223 match(Set dst (LoadB mem));
5224 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5225 expand %{
5226 iRegIdst tmp;
5227 loadUB_indirect_ac(tmp, mem);
5228 convB2I_reg_2(dst, tmp);
5229 %}
5230 %}
5231
5232 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5233 // match-rule, false predicate
5234 match(Set dst (LoadB mem));
5235 predicate(false);
5236
5237 format %{ "LBZ $dst, $mem" %}
5238 size(4);
5239 ins_encode( enc_lbz(dst, mem) );
5240 ins_pipe(pipe_class_memory);
5241 %}
5242
5243 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5244 // match-rule, false predicate
5245 match(Set dst (LoadB mem));
5246 predicate(false);
5247
5248 format %{ "LBZ $dst, $mem\n\t"
5249 "TWI $dst\n\t"
5250 "ISYNC" %}
5251 size(12);
5252 ins_encode( enc_lbz_ac(dst, mem) );
5253 ins_pipe(pipe_class_memory);
5254 %}
5255
5256 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5257 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5258 match(Set dst (LoadB mem));
5259 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5260 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5261
5262 expand %{
5263 iRegIdst tmp;
5264 loadUB_indOffset16(tmp, mem);
5265 convB2I_reg_2(dst, tmp);
5266 %}
5267 %}
5268
5269 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5270 match(Set dst (LoadB mem));
5271 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5272
5273 expand %{
5274 iRegIdst tmp;
5275 loadUB_indOffset16_ac(tmp, mem);
5276 convB2I_reg_2(dst, tmp);
5277 %}
5278 %}
5279
5280 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5281 instruct loadUB(iRegIdst dst, memory mem) %{
5282 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5283 match(Set dst (LoadUB mem));
5284 ins_cost(MEMORY_REF_COST);
5285
5286 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5287 size(4);
5288 ins_encode( enc_lbz(dst, mem) );
5289 ins_pipe(pipe_class_memory);
5290 %}
5291
5292 // Load Unsigned Byte (8bit UNsigned) acquire.
5293 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5294 match(Set dst (LoadUB mem));
5295 ins_cost(3*MEMORY_REF_COST);
5296
5297 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5298 "TWI $dst\n\t"
5299 "ISYNC" %}
5300 size(12);
5301 ins_encode( enc_lbz_ac(dst, mem) );
5302 ins_pipe(pipe_class_memory);
5303 %}
5304
5305 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5306 instruct loadUB2L(iRegLdst dst, memory mem) %{
5307 match(Set dst (ConvI2L (LoadUB mem)));
5308 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5309 ins_cost(MEMORY_REF_COST);
5310
5311 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5312 size(4);
5313 ins_encode( enc_lbz(dst, mem) );
5314 ins_pipe(pipe_class_memory);
5315 %}
5316
5317 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5318 match(Set dst (ConvI2L (LoadUB mem)));
5319 ins_cost(3*MEMORY_REF_COST);
5320
5321 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5322 "TWI $dst\n\t"
5323 "ISYNC" %}
5324 size(12);
5325 ins_encode( enc_lbz_ac(dst, mem) );
5326 ins_pipe(pipe_class_memory);
5327 %}
5328
5329 // Load Short (16bit signed)
5330 instruct loadS(iRegIdst dst, memory mem) %{
5331 match(Set dst (LoadS mem));
5332 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5333 ins_cost(MEMORY_REF_COST);
5334
5335 format %{ "LHA $dst, $mem" %}
5336 size(4);
5337 ins_encode %{
5338 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5339 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5340 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5341 %}
5342 ins_pipe(pipe_class_memory);
5343 %}
5344
5345 // Load Short (16bit signed) acquire.
5346 instruct loadS_ac(iRegIdst dst, memory mem) %{
5347 match(Set dst (LoadS mem));
5348 ins_cost(3*MEMORY_REF_COST);
5349
5350 format %{ "LHA $dst, $mem\t acquire\n\t"
5351 "TWI $dst\n\t"
5352 "ISYNC" %}
5353 size(12);
5354 ins_encode %{
5355 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5356 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5357 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5358 __ twi_0($dst$$Register);
5359 __ isync();
5360 %}
5361 ins_pipe(pipe_class_memory);
5362 %}
5363
5364 // Load Char (16bit unsigned)
5365 instruct loadUS(iRegIdst dst, memory mem) %{
5366 match(Set dst (LoadUS mem));
5367 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5368 ins_cost(MEMORY_REF_COST);
5369
5370 format %{ "LHZ $dst, $mem" %}
5371 size(4);
5372 ins_encode( enc_lhz(dst, mem) );
5373 ins_pipe(pipe_class_memory);
5374 %}
5375
5376 // Load Char (16bit unsigned) acquire.
5377 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5378 match(Set dst (LoadUS mem));
5379 ins_cost(3*MEMORY_REF_COST);
5380
5381 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5382 "TWI $dst\n\t"
5383 "ISYNC" %}
5384 size(12);
5385 ins_encode( enc_lhz_ac(dst, mem) );
5386 ins_pipe(pipe_class_memory);
5387 %}
5388
5389 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5390 instruct loadUS2L(iRegLdst dst, memory mem) %{
5391 match(Set dst (ConvI2L (LoadUS mem)));
5392 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5393 ins_cost(MEMORY_REF_COST);
5394
5395 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5396 size(4);
5397 ins_encode( enc_lhz(dst, mem) );
5398 ins_pipe(pipe_class_memory);
5399 %}
5400
5401 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5402 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5403 match(Set dst (ConvI2L (LoadUS mem)));
5404 ins_cost(3*MEMORY_REF_COST);
5405
5406 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5407 "TWI $dst\n\t"
5408 "ISYNC" %}
5409 size(12);
5410 ins_encode( enc_lhz_ac(dst, mem) );
5411 ins_pipe(pipe_class_memory);
5412 %}
5413
5414 // Load Integer.
5415 instruct loadI(iRegIdst dst, memory mem) %{
5416 match(Set dst (LoadI mem));
5417 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5418 ins_cost(MEMORY_REF_COST);
5419
5420 format %{ "LWZ $dst, $mem" %}
5421 size(4);
5422 ins_encode( enc_lwz(dst, mem) );
5423 ins_pipe(pipe_class_memory);
5424 %}
5425
5426 // Load Integer acquire.
5427 instruct loadI_ac(iRegIdst dst, memory mem) %{
5428 match(Set dst (LoadI mem));
5429 ins_cost(3*MEMORY_REF_COST);
5430
5431 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5432 "TWI $dst\n\t"
5433 "ISYNC" %}
5434 size(12);
5435 ins_encode( enc_lwz_ac(dst, mem) );
5436 ins_pipe(pipe_class_memory);
5437 %}
5438
5439 // Match loading integer and casting it to unsigned int in
5440 // long register.
5441 // LoadI + ConvI2L + AndL 0xffffffff.
5442 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5443 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5444 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5445 ins_cost(MEMORY_REF_COST);
5446
5447 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5448 size(4);
5449 ins_encode( enc_lwz(dst, mem) );
5450 ins_pipe(pipe_class_memory);
5451 %}
5452
5453 // Match loading integer and casting it to long.
5454 instruct loadI2L(iRegLdst dst, memory mem) %{
5455 match(Set dst (ConvI2L (LoadI mem)));
5456 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5457 ins_cost(MEMORY_REF_COST);
5458
5459 format %{ "LWA $dst, $mem \t// loadI2L" %}
5460 size(4);
5461 ins_encode %{
5462 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5463 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5464 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5465 %}
5466 ins_pipe(pipe_class_memory);
5467 %}
5468
5469 // Match loading integer and casting it to long - acquire.
5470 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5471 match(Set dst (ConvI2L (LoadI mem)));
5472 ins_cost(3*MEMORY_REF_COST);
5473
5474 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5475 "TWI $dst\n\t"
5476 "ISYNC" %}
5477 size(12);
5478 ins_encode %{
5479 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5480 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5481 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5482 __ twi_0($dst$$Register);
5483 __ isync();
5484 %}
5485 ins_pipe(pipe_class_memory);
5486 %}
5487
5488 // Load Long - aligned
5489 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5490 match(Set dst (LoadL mem));
5491 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5492 ins_cost(MEMORY_REF_COST);
5493
5494 format %{ "LD $dst, $mem \t// long" %}
5495 size(4);
5496 ins_encode( enc_ld(dst, mem) );
5497 ins_pipe(pipe_class_memory);
5498 %}
5499
5500 // Load Long - aligned acquire.
5501 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5502 match(Set dst (LoadL mem));
5503 ins_cost(3*MEMORY_REF_COST);
5504
5505 format %{ "LD $dst, $mem \t// long acquire\n\t"
5506 "TWI $dst\n\t"
5507 "ISYNC" %}
5508 size(12);
5509 ins_encode( enc_ld_ac(dst, mem) );
5510 ins_pipe(pipe_class_memory);
5511 %}
5512
5513 // Load Long - UNaligned
5514 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5515 match(Set dst (LoadL_unaligned mem));
5516 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5517 ins_cost(MEMORY_REF_COST);
5518
5519 format %{ "LD $dst, $mem \t// unaligned long" %}
5520 size(4);
5521 ins_encode( enc_ld(dst, mem) );
5522 ins_pipe(pipe_class_memory);
5523 %}
5524
5525 // Load nodes for superwords
5526
5527 // Load Aligned Packed Byte
5528 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5529 predicate(n->as_LoadVector()->memory_size() == 8);
5530 match(Set dst (LoadVector mem));
5531 ins_cost(MEMORY_REF_COST);
5532
5533 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5534 size(4);
5535 ins_encode( enc_ld(dst, mem) );
5536 ins_pipe(pipe_class_memory);
5537 %}
5538
5539 // Load Range, range = array length (=jint)
5540 instruct loadRange(iRegIdst dst, memory mem) %{
5541 match(Set dst (LoadRange mem));
5542 ins_cost(MEMORY_REF_COST);
5543
5544 format %{ "LWZ $dst, $mem \t// range" %}
5545 size(4);
5546 ins_encode( enc_lwz(dst, mem) );
5547 ins_pipe(pipe_class_memory);
5548 %}
5549
5550 // Load Compressed Pointer
5551 instruct loadN(iRegNdst dst, memory mem) %{
5552 match(Set dst (LoadN mem));
5553 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5554 ins_cost(MEMORY_REF_COST);
5555
5556 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5557 size(4);
5558 ins_encode( enc_lwz(dst, mem) );
5559 ins_pipe(pipe_class_memory);
5560 %}
5561
5562 // Load Compressed Pointer acquire.
5563 instruct loadN_ac(iRegNdst dst, memory mem) %{
5564 match(Set dst (LoadN mem));
5565 ins_cost(3*MEMORY_REF_COST);
5566
5567 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5568 "TWI $dst\n\t"
5569 "ISYNC" %}
5570 size(12);
5571 ins_encode( enc_lwz_ac(dst, mem) );
5572 ins_pipe(pipe_class_memory);
5573 %}
5574
5575 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5576 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5577 match(Set dst (DecodeN (LoadN mem)));
5578 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5579 ins_cost(MEMORY_REF_COST);
5580
5581 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5582 size(4);
5583 ins_encode( enc_lwz(dst, mem) );
5584 ins_pipe(pipe_class_memory);
5585 %}
5586
5587 // Load Pointer
5588 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5589 match(Set dst (LoadP mem));
5590 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5591 ins_cost(MEMORY_REF_COST);
5592
5593 format %{ "LD $dst, $mem \t// ptr" %}
5594 size(4);
5595 ins_encode( enc_ld(dst, mem) );
5596 ins_pipe(pipe_class_memory);
5597 %}
5598
5599 // Load Pointer acquire.
5600 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5601 match(Set dst (LoadP mem));
5602 ins_cost(3*MEMORY_REF_COST);
5603
5604 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5605 "TWI $dst\n\t"
5606 "ISYNC" %}
5607 size(12);
5608 ins_encode( enc_ld_ac(dst, mem) );
5609 ins_pipe(pipe_class_memory);
5610 %}
5611
5612 // LoadP + CastP2L
5613 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5614 match(Set dst (CastP2X (LoadP mem)));
5615 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5616 ins_cost(MEMORY_REF_COST);
5617
5618 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5619 size(4);
5620 ins_encode( enc_ld(dst, mem) );
5621 ins_pipe(pipe_class_memory);
5622 %}
5623
5624 // Load compressed klass pointer.
5625 instruct loadNKlass(iRegNdst dst, memory mem) %{
5626 match(Set dst (LoadNKlass mem));
5627 ins_cost(MEMORY_REF_COST);
5628
5629 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5630 size(4);
5631 ins_encode( enc_lwz(dst, mem) );
5632 ins_pipe(pipe_class_memory);
5633 %}
5634
5635 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5636 //// TODO: will narrow_klass_shift ever be 0?
5637 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5638 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5639 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5640 // ins_cost(MEMORY_REF_COST);
5641 //
5642 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5643 // size(4);
5644 // ins_encode( enc_lwz(dst, mem) );
5645 // ins_pipe(pipe_class_memory);
5646 //%}
5647
5648 // Load Klass Pointer
5649 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5650 match(Set dst (LoadKlass mem));
5651 ins_cost(MEMORY_REF_COST);
5652
5653 format %{ "LD $dst, $mem \t// klass ptr" %}
5654 size(4);
5655 ins_encode( enc_ld(dst, mem) );
5656 ins_pipe(pipe_class_memory);
5657 %}
5658
5659 // Load Float
5660 instruct loadF(regF dst, memory mem) %{
5661 match(Set dst (LoadF mem));
5662 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5663 ins_cost(MEMORY_REF_COST);
5664
5665 format %{ "LFS $dst, $mem" %}
5666 size(4);
5667 ins_encode %{
5668 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5669 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5670 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5671 %}
5672 ins_pipe(pipe_class_memory);
5673 %}
5674
5675 // Load Float acquire.
5676 instruct loadF_ac(regF dst, memory mem) %{
5677 match(Set dst (LoadF mem));
5678 ins_cost(3*MEMORY_REF_COST);
5679
5680 format %{ "LFS $dst, $mem \t// acquire\n\t"
5681 "FCMPU cr0, $dst, $dst\n\t"
5682 "BNE cr0, next\n"
5683 "next:\n\t"
5684 "ISYNC" %}
5685 size(16);
5686 ins_encode %{
5687 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5688 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5689 Label next;
5690 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5691 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5692 __ bne(CCR0, next);
5693 __ bind(next);
5694 __ isync();
5695 %}
5696 ins_pipe(pipe_class_memory);
5697 %}
5698
5699 // Load Double - aligned
5700 instruct loadD(regD dst, memory mem) %{
5701 match(Set dst (LoadD mem));
5702 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5703 ins_cost(MEMORY_REF_COST);
5704
5705 format %{ "LFD $dst, $mem" %}
5706 size(4);
5707 ins_encode( enc_lfd(dst, mem) );
5708 ins_pipe(pipe_class_memory);
5709 %}
5710
5711 // Load Double - aligned acquire.
5712 instruct loadD_ac(regD dst, memory mem) %{
5713 match(Set dst (LoadD mem));
5714 ins_cost(3*MEMORY_REF_COST);
5715
5716 format %{ "LFD $dst, $mem \t// acquire\n\t"
5717 "FCMPU cr0, $dst, $dst\n\t"
5718 "BNE cr0, next\n"
5719 "next:\n\t"
5720 "ISYNC" %}
5721 size(16);
5722 ins_encode %{
5723 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5724 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5725 Label next;
5726 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5727 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5728 __ bne(CCR0, next);
5729 __ bind(next);
5730 __ isync();
5731 %}
5732 ins_pipe(pipe_class_memory);
5733 %}
5734
5735 // Load Double - UNaligned
5736 instruct loadD_unaligned(regD dst, memory mem) %{
5737 match(Set dst (LoadD_unaligned mem));
5738 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5739 ins_cost(MEMORY_REF_COST);
5740
5741 format %{ "LFD $dst, $mem" %}
5742 size(4);
5743 ins_encode( enc_lfd(dst, mem) );
5744 ins_pipe(pipe_class_memory);
5745 %}
5746
5747 //----------Constants--------------------------------------------------------
5748
5749 // Load MachConstantTableBase: add hi offset to global toc.
5750 // TODO: Handle hidden register r29 in bundler!
5751 instruct loadToc_hi(iRegLdst dst) %{
5752 effect(DEF dst);
5753 ins_cost(DEFAULT_COST);
5754
5755 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5756 size(4);
5757 ins_encode %{
5758 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5759 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5760 %}
5761 ins_pipe(pipe_class_default);
5762 %}
5763
5764 // Load MachConstantTableBase: add lo offset to global toc.
5765 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5766 effect(DEF dst, USE src);
5767 ins_cost(DEFAULT_COST);
5768
5769 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5770 size(4);
5771 ins_encode %{
5772 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5773 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5774 %}
5775 ins_pipe(pipe_class_default);
5776 %}
5777
5778 // Load 16-bit integer constant 0xssss????
5779 instruct loadConI16(iRegIdst dst, immI16 src) %{
5780 match(Set dst src);
5781
5782 format %{ "LI $dst, $src" %}
5783 size(4);
5784 ins_encode %{
5785 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5786 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5787 %}
5788 ins_pipe(pipe_class_default);
5789 %}
5790
5791 // Load integer constant 0x????0000
5792 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5793 match(Set dst src);
5794 ins_cost(DEFAULT_COST);
5795
5796 format %{ "LIS $dst, $src.hi" %}
5797 size(4);
5798 ins_encode %{
5799 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5800 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5801 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5802 %}
5803 ins_pipe(pipe_class_default);
5804 %}
5805
5806 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5807 // and sign extended), this adds the low 16 bits.
5808 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5809 // no match-rule, false predicate
5810 effect(DEF dst, USE src1, USE src2);
5811 predicate(false);
5812
5813 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5814 size(4);
5815 ins_encode %{
5816 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5817 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5818 %}
5819 ins_pipe(pipe_class_default);
5820 %}
5821
5822 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5823 match(Set dst src);
5824 ins_cost(DEFAULT_COST*2);
5825
5826 expand %{
5827 // Would like to use $src$$constant.
5828 immI16 srcLo %{ _opnds[1]->constant() %}
5829 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5830 immIhi16 srcHi %{ _opnds[1]->constant() %}
5831 iRegIdst tmpI;
5832 loadConIhi16(tmpI, srcHi);
5833 loadConI32_lo16(dst, tmpI, srcLo);
5834 %}
5835 %}
5836
5837 // No constant pool entries required.
5838 instruct loadConL16(iRegLdst dst, immL16 src) %{
5839 match(Set dst src);
5840
5841 format %{ "LI $dst, $src \t// long" %}
5842 size(4);
5843 ins_encode %{
5844 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5845 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5846 %}
5847 ins_pipe(pipe_class_default);
5848 %}
5849
5850 // Load long constant 0xssssssss????0000
5851 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5852 match(Set dst src);
5853 ins_cost(DEFAULT_COST);
5854
5855 format %{ "LIS $dst, $src.hi \t// long" %}
5856 size(4);
5857 ins_encode %{
5858 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5859 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5860 %}
5861 ins_pipe(pipe_class_default);
5862 %}
5863
5864 // To load a 32 bit constant: merge lower 16 bits into already loaded
5865 // high 16 bits.
5866 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5867 // no match-rule, false predicate
5868 effect(DEF dst, USE src1, USE src2);
5869 predicate(false);
5870
5871 format %{ "ORI $dst, $src1, $src2.lo" %}
5872 size(4);
5873 ins_encode %{
5874 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5875 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5876 %}
5877 ins_pipe(pipe_class_default);
5878 %}
5879
5880 // Load 32-bit long constant
5881 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5882 match(Set dst src);
5883 ins_cost(DEFAULT_COST*2);
5884
5885 expand %{
5886 // Would like to use $src$$constant.
5887 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5888 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5889 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5890 iRegLdst tmpL;
5891 loadConL32hi16(tmpL, srcHi);
5892 loadConL32_lo16(dst, tmpL, srcLo);
5893 %}
5894 %}
5895
5896 // Load long constant 0x????000000000000.
5897 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5898 match(Set dst src);
5899 ins_cost(DEFAULT_COST);
5900
5901 expand %{
5902 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5903 immI shift32 %{ 32 %}
5904 iRegLdst tmpL;
5905 loadConL32hi16(tmpL, srcHi);
5906 lshiftL_regL_immI(dst, tmpL, shift32);
5907 %}
5908 %}
5909
5910 // Expand node for constant pool load: small offset.
5911 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5912 effect(DEF dst, USE src, USE toc);
5913 ins_cost(MEMORY_REF_COST);
5914
5915 ins_num_consts(1);
5916 // Needed so that CallDynamicJavaDirect can compute the address of this
5917 // instruction for relocation.
5918 ins_field_cbuf_insts_offset(int);
5919
5920 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5921 size(4);
5922 ins_encode( enc_load_long_constL(dst, src, toc) );
5923 ins_pipe(pipe_class_memory);
5924 %}
5925
5926 // Expand node for constant pool load: large offset.
5927 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5928 effect(DEF dst, USE src, USE toc);
5929 predicate(false);
5930
5931 ins_num_consts(1);
5932 ins_field_const_toc_offset(int);
5933 // Needed so that CallDynamicJavaDirect can compute the address of this
5934 // instruction for relocation.
5935 ins_field_cbuf_insts_offset(int);
5936
5937 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5938 size(4);
5939 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5940 ins_pipe(pipe_class_default);
5941 %}
5942
5943 // Expand node for constant pool load: large offset.
5944 // No constant pool entries required.
5945 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5946 effect(DEF dst, USE src, USE base);
5947 predicate(false);
5948
5949 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5950
5951 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5952 size(4);
5953 ins_encode %{
5954 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5955 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5956 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5957 %}
5958 ins_pipe(pipe_class_memory);
5959 %}
5960
5961 // Load long constant from constant table. Expand in case of
5962 // offset > 16 bit is needed.
5963 // Adlc adds toc node MachConstantTableBase.
5964 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5965 match(Set dst src);
5966 ins_cost(MEMORY_REF_COST);
5967
5968 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5969 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5970 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5971 %}
5972
5973 // Load NULL as compressed oop.
5974 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5975 match(Set dst src);
5976 ins_cost(DEFAULT_COST);
5977
5978 format %{ "LI $dst, $src \t// compressed ptr" %}
5979 size(4);
5980 ins_encode %{
5981 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5982 __ li($dst$$Register, 0);
5983 %}
5984 ins_pipe(pipe_class_default);
5985 %}
5986
5987 // Load hi part of compressed oop constant.
5988 instruct loadConN_hi(iRegNdst dst, immN src) %{
5989 effect(DEF dst, USE src);
5990 ins_cost(DEFAULT_COST);
5991
5992 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5993 size(4);
5994 ins_encode %{
5995 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5996 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5997 %}
5998 ins_pipe(pipe_class_default);
5999 %}
6000
6001 // Add lo part of compressed oop constant to already loaded hi part.
6002 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6003 effect(DEF dst, USE src1, USE src2);
6004 ins_cost(DEFAULT_COST);
6005
6006 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6007 size(4);
6008 ins_encode %{
6009 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6010 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6011 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6012 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6013 __ relocate(rspec, 1);
6014 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6015 %}
6016 ins_pipe(pipe_class_default);
6017 %}
6018
6019 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6020 // leaving the upper 32 bits with sign-extension bits.
6021 // This clears these bits: dst = src & 0xFFFFFFFF.
6022 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6023 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6024 effect(DEF dst, USE src);
6025 predicate(false);
6026
6027 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6028 size(4);
6029 ins_encode %{
6030 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6031 __ clrldi($dst$$Register, $src$$Register, 0x20);
6032 %}
6033 ins_pipe(pipe_class_default);
6034 %}
6035
6036 // Loading ConN must be postalloc expanded so that edges between
6037 // the nodes are safe. They may not interfere with a safepoint.
6038 // GL TODO: This needs three instructions: better put this into the constant pool.
6039 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6040 match(Set dst src);
6041 ins_cost(DEFAULT_COST*2);
6042
6043 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6044 postalloc_expand %{
6045 MachNode *m1 = new (C) loadConN_hiNode();
6046 MachNode *m2 = new (C) loadConN_loNode();
6047 MachNode *m3 = new (C) clearMs32bNode();
6048 m1->add_req(NULL);
6049 m2->add_req(NULL, m1);
6050 m3->add_req(NULL, m2);
6051 m1->_opnds[0] = op_dst;
6052 m1->_opnds[1] = op_src;
6053 m2->_opnds[0] = op_dst;
6054 m2->_opnds[1] = op_dst;
6055 m2->_opnds[2] = op_src;
6056 m3->_opnds[0] = op_dst;
6057 m3->_opnds[1] = op_dst;
6058 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6059 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6060 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6061 nodes->push(m1);
6062 nodes->push(m2);
6063 nodes->push(m3);
6064 %}
6065 %}
6066
6067 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6068 effect(DEF dst, USE src);
6069 ins_cost(DEFAULT_COST);
6070
6071 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6072 size(4);
6073 ins_encode %{
6074 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6075 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6076 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6077 %}
6078 ins_pipe(pipe_class_default);
6079 %}
6080
6081 // This needs a match rule so that build_oop_map knows this is
6082 // not a narrow oop.
6083 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6084 match(Set dst src1);
6085 effect(TEMP src2);
6086 ins_cost(DEFAULT_COST);
6087
6088 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6089 size(4);
6090 ins_encode %{
6091 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6092 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6093 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6094 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6095 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6096
6097 __ relocate(rspec, 1);
6098 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6099 %}
6100 ins_pipe(pipe_class_default);
6101 %}
6102
6103 // Loading ConNKlass must be postalloc expanded so that edges between
6104 // the nodes are safe. They may not interfere with a safepoint.
6105 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6106 match(Set dst src);
6107 ins_cost(DEFAULT_COST*2);
6108
6109 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6110 postalloc_expand %{
6111 // Load high bits into register. Sign extended.
6112 MachNode *m1 = new (C) loadConNKlass_hiNode();
6113 m1->add_req(NULL);
6114 m1->_opnds[0] = op_dst;
6115 m1->_opnds[1] = op_src;
6116 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6117 nodes->push(m1);
6118
6119 MachNode *m2 = m1;
6120 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6121 // Value might be 1-extended. Mask out these bits.
6122 m2 = new (C) clearMs32bNode();
6123 m2->add_req(NULL, m1);
6124 m2->_opnds[0] = op_dst;
6125 m2->_opnds[1] = op_dst;
6126 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6127 nodes->push(m2);
6128 }
6129
6130 MachNode *m3 = new (C) loadConNKlass_loNode();
6131 m3->add_req(NULL, m2);
6132 m3->_opnds[0] = op_dst;
6133 m3->_opnds[1] = op_src;
6134 m3->_opnds[2] = op_dst;
6135 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6136 nodes->push(m3);
6137 %}
6138 %}
6139
6140 // 0x1 is used in object initialization (initial object header).
6141 // No constant pool entries required.
6142 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6143 match(Set dst src);
6144
6145 format %{ "LI $dst, $src \t// ptr" %}
6146 size(4);
6147 ins_encode %{
6148 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6149 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6150 %}
6151 ins_pipe(pipe_class_default);
6152 %}
6153
6154 // Expand node for constant pool load: small offset.
6155 // The match rule is needed to generate the correct bottom_type(),
6156 // however this node should never match. The use of predicate is not
6157 // possible since ADLC forbids predicates for chain rules. The higher
6158 // costs do not prevent matching in this case. For that reason the
6159 // operand immP_NM with predicate(false) is used.
6160 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6161 match(Set dst src);
6162 effect(TEMP toc);
6163
6164 ins_num_consts(1);
6165
6166 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6167 size(4);
6168 ins_encode( enc_load_long_constP(dst, src, toc) );
6169 ins_pipe(pipe_class_memory);
6170 %}
6171
6172 // Expand node for constant pool load: large offset.
6173 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6174 effect(DEF dst, USE src, USE toc);
6175 predicate(false);
6176
6177 ins_num_consts(1);
6178 ins_field_const_toc_offset(int);
6179
6180 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6181 size(4);
6182 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6183 ins_pipe(pipe_class_default);
6184 %}
6185
6186 // Expand node for constant pool load: large offset.
6187 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6188 match(Set dst src);
6189 effect(TEMP base);
6190
6191 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6192
6193 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6194 size(4);
6195 ins_encode %{
6196 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6197 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6198 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6199 %}
6200 ins_pipe(pipe_class_memory);
6201 %}
6202
6203 // Load pointer constant from constant table. Expand in case an
6204 // offset > 16 bit is needed.
6205 // Adlc adds toc node MachConstantTableBase.
6206 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6207 match(Set dst src);
6208 ins_cost(MEMORY_REF_COST);
6209
6210 // This rule does not use "expand" because then
6211 // the result type is not known to be an Oop. An ADLC
6212 // enhancement will be needed to make that work - not worth it!
6213
6214 // If this instruction rematerializes, it prolongs the live range
6215 // of the toc node, causing illegal graphs.
6216 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6217 ins_cannot_rematerialize(true);
6218
6219 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6220 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6221 %}
6222
6223 // Expand node for constant pool load: small offset.
6224 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6225 effect(DEF dst, USE src, USE toc);
6226 ins_cost(MEMORY_REF_COST);
6227
6228 ins_num_consts(1);
6229
6230 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6231 size(4);
6232 ins_encode %{
6233 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6234 address float_address = __ float_constant($src$$constant);
6235 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6236 %}
6237 ins_pipe(pipe_class_memory);
6238 %}
6239
6240 // Expand node for constant pool load: large offset.
6241 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6242 effect(DEF dst, USE src, USE toc);
6243 ins_cost(MEMORY_REF_COST);
6244
6245 ins_num_consts(1);
6246
6247 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6248 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6249 "ADDIS $toc, $toc, -offset_hi"%}
6250 size(12);
6251 ins_encode %{
6252 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6253 FloatRegister Rdst = $dst$$FloatRegister;
6254 Register Rtoc = $toc$$Register;
6255 address float_address = __ float_constant($src$$constant);
6256 int offset = __ offset_to_method_toc(float_address);
6257 int hi = (offset + (1<<15))>>16;
6258 int lo = offset - hi * (1<<16);
6259
6260 __ addis(Rtoc, Rtoc, hi);
6261 __ lfs(Rdst, lo, Rtoc);
6262 __ addis(Rtoc, Rtoc, -hi);
6263 %}
6264 ins_pipe(pipe_class_memory);
6265 %}
6266
6267 // Adlc adds toc node MachConstantTableBase.
6268 instruct loadConF_Ex(regF dst, immF src) %{
6269 match(Set dst src);
6270 ins_cost(MEMORY_REF_COST);
6271
6272 // See loadConP.
6273 ins_cannot_rematerialize(true);
6274
6275 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6276 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6277 %}
6278
6279 // Expand node for constant pool load: small offset.
6280 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6281 effect(DEF dst, USE src, USE toc);
6282 ins_cost(MEMORY_REF_COST);
6283
6284 ins_num_consts(1);
6285
6286 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6287 size(4);
6288 ins_encode %{
6289 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6290 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6291 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6292 %}
6293 ins_pipe(pipe_class_memory);
6294 %}
6295
6296 // Expand node for constant pool load: large offset.
6297 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6298 effect(DEF dst, USE src, USE toc);
6299 ins_cost(MEMORY_REF_COST);
6300
6301 ins_num_consts(1);
6302
6303 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6304 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6305 "ADDIS $toc, $toc, -offset_hi" %}
6306 size(12);
6307 ins_encode %{
6308 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6309 FloatRegister Rdst = $dst$$FloatRegister;
6310 Register Rtoc = $toc$$Register;
6311 address float_address = __ double_constant($src$$constant);
6312 int offset = __ offset_to_method_toc(float_address);
6313 int hi = (offset + (1<<15))>>16;
6314 int lo = offset - hi * (1<<16);
6315
6316 __ addis(Rtoc, Rtoc, hi);
6317 __ lfd(Rdst, lo, Rtoc);
6318 __ addis(Rtoc, Rtoc, -hi);
6319 %}
6320 ins_pipe(pipe_class_memory);
6321 %}
6322
6323 // Adlc adds toc node MachConstantTableBase.
6324 instruct loadConD_Ex(regD dst, immD src) %{
6325 match(Set dst src);
6326 ins_cost(MEMORY_REF_COST);
6327
6328 // See loadConP.
6329 ins_cannot_rematerialize(true);
6330
6331 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6332 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6333 %}
6334
6335 // Prefetch instructions.
6336 // Must be safe to execute with invalid address (cannot fault).
6337
6338 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6339 match(PrefetchRead (AddP mem src));
6340 ins_cost(MEMORY_REF_COST);
6341
6342 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6343 size(4);
6344 ins_encode %{
6345 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6346 __ dcbt($src$$Register, $mem$$base$$Register);
6347 %}
6348 ins_pipe(pipe_class_memory);
6349 %}
6350
6351 instruct prefetchr_no_offset(indirectMemory mem) %{
6352 match(PrefetchRead mem);
6353 ins_cost(MEMORY_REF_COST);
6354
6355 format %{ "PREFETCH $mem" %}
6356 size(4);
6357 ins_encode %{
6358 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6359 __ dcbt($mem$$base$$Register);
6360 %}
6361 ins_pipe(pipe_class_memory);
6362 %}
6363
6364 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6365 match(PrefetchWrite (AddP mem src));
6366 ins_cost(MEMORY_REF_COST);
6367
6368 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6369 size(4);
6370 ins_encode %{
6371 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6372 __ dcbtst($src$$Register, $mem$$base$$Register);
6373 %}
6374 ins_pipe(pipe_class_memory);
6375 %}
6376
6377 instruct prefetchw_no_offset(indirectMemory mem) %{
6378 match(PrefetchWrite mem);
6379 ins_cost(MEMORY_REF_COST);
6380
6381 format %{ "PREFETCH $mem" %}
6382 size(4);
6383 ins_encode %{
6384 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6385 __ dcbtst($mem$$base$$Register);
6386 %}
6387 ins_pipe(pipe_class_memory);
6388 %}
6389
6390 // Special prefetch versions which use the dcbz instruction.
6391 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6392 match(PrefetchAllocation (AddP mem src));
6393 predicate(AllocatePrefetchStyle == 3);
6394 ins_cost(MEMORY_REF_COST);
6395
6396 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6397 size(4);
6398 ins_encode %{
6399 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6400 __ dcbz($src$$Register, $mem$$base$$Register);
6401 %}
6402 ins_pipe(pipe_class_memory);
6403 %}
6404
6405 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6406 match(PrefetchAllocation mem);
6407 predicate(AllocatePrefetchStyle == 3);
6408 ins_cost(MEMORY_REF_COST);
6409
6410 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6411 size(4);
6412 ins_encode %{
6413 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6414 __ dcbz($mem$$base$$Register);
6415 %}
6416 ins_pipe(pipe_class_memory);
6417 %}
6418
6419 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6420 match(PrefetchAllocation (AddP mem src));
6421 predicate(AllocatePrefetchStyle != 3);
6422 ins_cost(MEMORY_REF_COST);
6423
6424 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6425 size(4);
6426 ins_encode %{
6427 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6428 __ dcbtst($src$$Register, $mem$$base$$Register);
6429 %}
6430 ins_pipe(pipe_class_memory);
6431 %}
6432
6433 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6434 match(PrefetchAllocation mem);
6435 predicate(AllocatePrefetchStyle != 3);
6436 ins_cost(MEMORY_REF_COST);
6437
6438 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6439 size(4);
6440 ins_encode %{
6441 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6442 __ dcbtst($mem$$base$$Register);
6443 %}
6444 ins_pipe(pipe_class_memory);
6445 %}
6446
6447 //----------Store Instructions-------------------------------------------------
6448
6449 // Store Byte
6450 instruct storeB(memory mem, iRegIsrc src) %{
6451 match(Set mem (StoreB mem src));
6452 ins_cost(MEMORY_REF_COST);
6453
6454 format %{ "STB $src, $mem \t// byte" %}
6455 size(4);
6456 ins_encode %{
6457 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6458 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6459 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6460 %}
6461 ins_pipe(pipe_class_memory);
6462 %}
6463
6464 // Store Char/Short
6465 instruct storeC(memory mem, iRegIsrc src) %{
6466 match(Set mem (StoreC mem src));
6467 ins_cost(MEMORY_REF_COST);
6468
6469 format %{ "STH $src, $mem \t// short" %}
6470 size(4);
6471 ins_encode %{
6472 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6473 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6474 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6475 %}
6476 ins_pipe(pipe_class_memory);
6477 %}
6478
6479 // Store Integer
6480 instruct storeI(memory mem, iRegIsrc src) %{
6481 match(Set mem (StoreI mem src));
6482 ins_cost(MEMORY_REF_COST);
6483
6484 format %{ "STW $src, $mem" %}
6485 size(4);
6486 ins_encode( enc_stw(src, mem) );
6487 ins_pipe(pipe_class_memory);
6488 %}
6489
6490 // ConvL2I + StoreI.
6491 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6492 match(Set mem (StoreI mem (ConvL2I src)));
6493 ins_cost(MEMORY_REF_COST);
6494
6495 format %{ "STW l2i($src), $mem" %}
6496 size(4);
6497 ins_encode( enc_stw(src, mem) );
6498 ins_pipe(pipe_class_memory);
6499 %}
6500
6501 // Store Long
6502 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6503 match(Set mem (StoreL mem src));
6504 ins_cost(MEMORY_REF_COST);
6505
6506 format %{ "STD $src, $mem \t// long" %}
6507 size(4);
6508 ins_encode( enc_std(src, mem) );
6509 ins_pipe(pipe_class_memory);
6510 %}
6511
6512 // Store super word nodes.
6513
6514 // Store Aligned Packed Byte long register to memory
6515 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6516 predicate(n->as_StoreVector()->memory_size() == 8);
6517 match(Set mem (StoreVector mem src));
6518 ins_cost(MEMORY_REF_COST);
6519
6520 format %{ "STD $mem, $src \t// packed8B" %}
6521 size(4);
6522 ins_encode( enc_std(src, mem) );
6523 ins_pipe(pipe_class_memory);
6524 %}
6525
6526 // Store Compressed Oop
6527 instruct storeN(memory dst, iRegN_P2N src) %{
6528 match(Set dst (StoreN dst src));
6529 ins_cost(MEMORY_REF_COST);
6530
6531 format %{ "STW $src, $dst \t// compressed oop" %}
6532 size(4);
6533 ins_encode( enc_stw(src, dst) );
6534 ins_pipe(pipe_class_memory);
6535 %}
6536
6537 // Store Compressed KLass
6538 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6539 match(Set dst (StoreNKlass dst src));
6540 ins_cost(MEMORY_REF_COST);
6541
6542 format %{ "STW $src, $dst \t// compressed klass" %}
6543 size(4);
6544 ins_encode( enc_stw(src, dst) );
6545 ins_pipe(pipe_class_memory);
6546 %}
6547
6548 // Store Pointer
6549 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6550 match(Set dst (StoreP dst src));
6551 ins_cost(MEMORY_REF_COST);
6552
6553 format %{ "STD $src, $dst \t// ptr" %}
6554 size(4);
6555 ins_encode( enc_std(src, dst) );
6556 ins_pipe(pipe_class_memory);
6557 %}
6558
6559 // Store Float
6560 instruct storeF(memory mem, regF src) %{
6561 match(Set mem (StoreF mem src));
6562 ins_cost(MEMORY_REF_COST);
6563
6564 format %{ "STFS $src, $mem" %}
6565 size(4);
6566 ins_encode( enc_stfs(src, mem) );
6567 ins_pipe(pipe_class_memory);
6568 %}
6569
6570 // Store Double
6571 instruct storeD(memory mem, regD src) %{
6572 match(Set mem (StoreD mem src));
6573 ins_cost(MEMORY_REF_COST);
6574
6575 format %{ "STFD $src, $mem" %}
6576 size(4);
6577 ins_encode( enc_stfd(src, mem) );
6578 ins_pipe(pipe_class_memory);
6579 %}
6580
6581 //----------Store Instructions With Zeros--------------------------------------
6582
6583 // Card-mark for CMS garbage collection.
6584 // This cardmark does an optimization so that it must not always
6585 // do a releasing store. For this, it gets the address of
6586 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6587 // (Using releaseFieldAddr in the match rule is a hack.)
6588 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6589 match(Set mem (StoreCM mem releaseFieldAddr));
6590 predicate(false);
6591 ins_cost(MEMORY_REF_COST);
6592
6593 // See loadConP.
6594 ins_cannot_rematerialize(true);
6595
6596 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6597 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6598 ins_pipe(pipe_class_memory);
6599 %}
6600
6601 // Card-mark for CMS garbage collection.
6602 // This cardmark does an optimization so that it must not always
6603 // do a releasing store. For this, it needs the constant address of
6604 // CMSCollectorCardTableModRefBSExt::_requires_release.
6605 // This constant address is split off here by expand so we can use
6606 // adlc / matcher functionality to load it from the constant section.
6607 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6608 match(Set mem (StoreCM mem zero));
6609 predicate(UseConcMarkSweepGC);
6610
6611 expand %{
6612 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6613 iRegLdst releaseFieldAddress;
6614 loadConL_Ex(releaseFieldAddress, baseImm);
6615 storeCM_CMS(mem, releaseFieldAddress);
6616 %}
6617 %}
6618
6619 instruct storeCM_G1(memory mem, immI_0 zero) %{
6620 match(Set mem (StoreCM mem zero));
6621 predicate(UseG1GC);
6622 ins_cost(MEMORY_REF_COST);
6623
6624 ins_cannot_rematerialize(true);
6625
6626 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6627 size(8);
6628 ins_encode %{
6629 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6630 __ li(R0, 0);
6631 //__ release(); // G1: oops are allowed to get visible after dirty marking
6632 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6633 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6634 %}
6635 ins_pipe(pipe_class_memory);
6636 %}
6637
6638 // Convert oop pointer into compressed form.
6639
6640 // Nodes for postalloc expand.
6641
6642 // Shift node for expand.
6643 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6644 // The match rule is needed to make it a 'MachTypeNode'!
6645 match(Set dst (EncodeP src));
6646 predicate(false);
6647
6648 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6649 size(4);
6650 ins_encode %{
6651 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6652 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6653 %}
6654 ins_pipe(pipe_class_default);
6655 %}
6656
6657 // Add node for expand.
6658 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6659 // The match rule is needed to make it a 'MachTypeNode'!
6660 match(Set dst (EncodeP src));
6661 predicate(false);
6662
6663 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6664 size(4);
6665 ins_encode %{
6666 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6667 __ subf($dst$$Register, R30, $src$$Register);
6668 %}
6669 ins_pipe(pipe_class_default);
6670 %}
6671
6672 // Conditional sub base.
6673 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6674 // The match rule is needed to make it a 'MachTypeNode'!
6675 match(Set dst (EncodeP (Binary crx src1)));
6676 predicate(false);
6677
6678 ins_variable_size_depending_on_alignment(true);
6679
6680 format %{ "BEQ $crx, done\n\t"
6681 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6682 "done:" %}
6683 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6684 ins_encode %{
6685 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6686 Label done;
6687 __ beq($crx$$CondRegister, done);
6688 __ subf($dst$$Register, R30, $src1$$Register);
6689 // TODO PPC port __ endgroup_if_needed(_size == 12);
6690 __ bind(done);
6691 %}
6692 ins_pipe(pipe_class_default);
6693 %}
6694
6695 // Power 7 can use isel instruction
6696 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6697 // The match rule is needed to make it a 'MachTypeNode'!
6698 match(Set dst (EncodeP (Binary crx src1)));
6699 predicate(false);
6700
6701 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6702 size(4);
6703 ins_encode %{
6704 // This is a Power7 instruction for which no machine description exists.
6705 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6706 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6707 %}
6708 ins_pipe(pipe_class_default);
6709 %}
6710
6711 // base != 0
6712 // 32G aligned narrow oop base.
6713 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6714 match(Set dst (EncodeP src));
6715 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6716
6717 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6718 size(4);
6719 ins_encode %{
6720 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6721 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6722 %}
6723 ins_pipe(pipe_class_default);
6724 %}
6725
6726 // shift != 0, base != 0
6727 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6728 match(Set dst (EncodeP src));
6729 effect(TEMP crx);
6730 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6731 Universe::narrow_oop_shift() != 0 &&
6732 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6733
6734 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6735 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6736 %}
6737
6738 // shift != 0, base != 0
6739 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6740 match(Set dst (EncodeP src));
6741 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6742 Universe::narrow_oop_shift() != 0 &&
6743 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6744
6745 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6746 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6747 %}
6748
6749 // shift != 0, base == 0
6750 // TODO: This is the same as encodeP_shift. Merge!
6751 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6752 match(Set dst (EncodeP src));
6753 predicate(Universe::narrow_oop_shift() != 0 &&
6754 Universe::narrow_oop_base() ==0);
6755
6756 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6757 size(4);
6758 ins_encode %{
6759 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6760 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6761 %}
6762 ins_pipe(pipe_class_default);
6763 %}
6764
6765 // Compressed OOPs with narrow_oop_shift == 0.
6766 // shift == 0, base == 0
6767 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6768 match(Set dst (EncodeP src));
6769 predicate(Universe::narrow_oop_shift() == 0);
6770
6771 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6772 // variable size, 0 or 4.
6773 ins_encode %{
6774 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6775 __ mr_if_needed($dst$$Register, $src$$Register);
6776 %}
6777 ins_pipe(pipe_class_default);
6778 %}
6779
6780 // Decode nodes.
6781
6782 // Shift node for expand.
6783 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6784 // The match rule is needed to make it a 'MachTypeNode'!
6785 match(Set dst (DecodeN src));
6786 predicate(false);
6787
6788 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6789 size(4);
6790 ins_encode %{
6791 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6792 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6793 %}
6794 ins_pipe(pipe_class_default);
6795 %}
6796
6797 // Add node for expand.
6798 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6799 // The match rule is needed to make it a 'MachTypeNode'!
6800 match(Set dst (DecodeN src));
6801 predicate(false);
6802
6803 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6804 size(4);
6805 ins_encode %{
6806 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6807 __ add($dst$$Register, $src$$Register, R30);
6808 %}
6809 ins_pipe(pipe_class_default);
6810 %}
6811
6812 // conditianal add base for expand
6813 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6814 // The match rule is needed to make it a 'MachTypeNode'!
6815 // NOTICE that the rule is nonsense - we just have to make sure that:
6816 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6817 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6818 match(Set dst (DecodeN (Binary crx src1)));
6819 predicate(false);
6820
6821 ins_variable_size_depending_on_alignment(true);
6822
6823 format %{ "BEQ $crx, done\n\t"
6824 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6825 "done:" %}
6826 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6827 ins_encode %{
6828 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6829 Label done;
6830 __ beq($crx$$CondRegister, done);
6831 __ add($dst$$Register, $src1$$Register, R30);
6832 // TODO PPC port __ endgroup_if_needed(_size == 12);
6833 __ bind(done);
6834 %}
6835 ins_pipe(pipe_class_default);
6836 %}
6837
6838 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6839 // The match rule is needed to make it a 'MachTypeNode'!
6840 // NOTICE that the rule is nonsense - we just have to make sure that:
6841 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6842 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6843 match(Set dst (DecodeN (Binary crx src1)));
6844 predicate(false);
6845
6846 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6847 size(4);
6848 ins_encode %{
6849 // This is a Power7 instruction for which no machine description exists.
6850 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6851 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6852 %}
6853 ins_pipe(pipe_class_default);
6854 %}
6855
6856 // shift != 0, base != 0
6857 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6858 match(Set dst (DecodeN src));
6859 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6860 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6861 Universe::narrow_oop_shift() != 0 &&
6862 Universe::narrow_oop_base() != 0);
6863 effect(TEMP crx);
6864
6865 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6866 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6867 %}
6868
6869 // shift != 0, base == 0
6870 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6871 match(Set dst (DecodeN src));
6872 predicate(Universe::narrow_oop_shift() != 0 &&
6873 Universe::narrow_oop_base() == 0);
6874
6875 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6876 size(4);
6877 ins_encode %{
6878 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6879 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6880 %}
6881 ins_pipe(pipe_class_default);
6882 %}
6883
6884 // src != 0, shift != 0, base != 0
6885 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6886 match(Set dst (DecodeN src));
6887 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6888 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6889 Universe::narrow_oop_shift() != 0 &&
6890 Universe::narrow_oop_base() != 0);
6891
6892 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6893 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6894 %}
6895
6896 // Compressed OOPs with narrow_oop_shift == 0.
6897 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6898 match(Set dst (DecodeN src));
6899 predicate(Universe::narrow_oop_shift() == 0);
6900 ins_cost(DEFAULT_COST);
6901
6902 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6903 // variable size, 0 or 4.
6904 ins_encode %{
6905 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6906 __ mr_if_needed($dst$$Register, $src$$Register);
6907 %}
6908 ins_pipe(pipe_class_default);
6909 %}
6910
6911 // Convert compressed oop into int for vectors alignment masking.
6912 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6913 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6914 predicate(Universe::narrow_oop_shift() == 0);
6915 ins_cost(DEFAULT_COST);
6916
6917 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6918 // variable size, 0 or 4.
6919 ins_encode %{
6920 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6921 __ mr_if_needed($dst$$Register, $src$$Register);
6922 %}
6923 ins_pipe(pipe_class_default);
6924 %}
6925
6926 // Convert klass pointer into compressed form.
6927
6928 // Nodes for postalloc expand.
6929
6930 // Shift node for expand.
6931 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6932 // The match rule is needed to make it a 'MachTypeNode'!
6933 match(Set dst (EncodePKlass src));
6934 predicate(false);
6935
6936 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6937 size(4);
6938 ins_encode %{
6939 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6940 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6941 %}
6942 ins_pipe(pipe_class_default);
6943 %}
6944
6945 // Add node for expand.
6946 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6947 // The match rule is needed to make it a 'MachTypeNode'!
6948 match(Set dst (EncodePKlass (Binary base src)));
6949 predicate(false);
6950
6951 format %{ "SUB $dst, $base, $src \t// encode" %}
6952 size(4);
6953 ins_encode %{
6954 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6955 __ subf($dst$$Register, $base$$Register, $src$$Register);
6956 %}
6957 ins_pipe(pipe_class_default);
6958 %}
6959
6960 // base != 0
6961 // 32G aligned narrow oop base.
6962 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6963 match(Set dst (EncodePKlass src));
6964 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6965
6966 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6967 size(4);
6968 ins_encode %{
6969 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6970 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6971 %}
6972 ins_pipe(pipe_class_default);
6973 %}
6974
6975 // shift != 0, base != 0
6976 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6977 match(Set dst (EncodePKlass (Binary base src)));
6978 predicate(false);
6979
6980 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6981 postalloc_expand %{
6982 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
6983 n1->add_req(n_region, n_base, n_src);
6984 n1->_opnds[0] = op_dst;
6985 n1->_opnds[1] = op_base;
6986 n1->_opnds[2] = op_src;
6987 n1->_bottom_type = _bottom_type;
6988
6989 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
6990 n2->add_req(n_region, n1);
6991 n2->_opnds[0] = op_dst;
6992 n2->_opnds[1] = op_dst;
6993 n2->_bottom_type = _bottom_type;
6994 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6995 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6996
6997 nodes->push(n1);
6998 nodes->push(n2);
6999 %}
7000 %}
7001
7002 // shift != 0, base != 0
7003 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7004 match(Set dst (EncodePKlass src));
7005 //predicate(Universe::narrow_klass_shift() != 0 &&
7006 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7007
7008 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7009 ins_cost(DEFAULT_COST*2); // Don't count constant.
7010 expand %{
7011 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7012 iRegLdst base;
7013 loadConL_Ex(base, baseImm);
7014 encodePKlass_not_null_Ex(dst, base, src);
7015 %}
7016 %}
7017
7018 // Decode nodes.
7019
7020 // Shift node for expand.
7021 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7022 // The match rule is needed to make it a 'MachTypeNode'!
7023 match(Set dst (DecodeNKlass src));
7024 predicate(false);
7025
7026 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7027 size(4);
7028 ins_encode %{
7029 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7030 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7031 %}
7032 ins_pipe(pipe_class_default);
7033 %}
7034
7035 // Add node for expand.
7036
7037 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7038 // The match rule is needed to make it a 'MachTypeNode'!
7039 match(Set dst (DecodeNKlass (Binary base src)));
7040 predicate(false);
7041
7042 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7043 size(4);
7044 ins_encode %{
7045 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7046 __ add($dst$$Register, $base$$Register, $src$$Register);
7047 %}
7048 ins_pipe(pipe_class_default);
7049 %}
7050
7051 // src != 0, shift != 0, base != 0
7052 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7053 match(Set dst (DecodeNKlass (Binary base src)));
7054 //effect(kill src); // We need a register for the immediate result after shifting.
7055 predicate(false);
7056
7057 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7058 postalloc_expand %{
7059 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7060 n1->add_req(n_region, n_base, n_src);
7061 n1->_opnds[0] = op_dst;
7062 n1->_opnds[1] = op_base;
7063 n1->_opnds[2] = op_src;
7064 n1->_bottom_type = _bottom_type;
7065
7066 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7067 n2->add_req(n_region, n2);
7068 n2->_opnds[0] = op_dst;
7069 n2->_opnds[1] = op_dst;
7070 n2->_bottom_type = _bottom_type;
7071
7072 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7073 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7074
7075 nodes->push(n1);
7076 nodes->push(n2);
7077 %}
7078 %}
7079
7080 // src != 0, shift != 0, base != 0
7081 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7082 match(Set dst (DecodeNKlass src));
7083 // predicate(Universe::narrow_klass_shift() != 0 &&
7084 // Universe::narrow_klass_base() != 0);
7085
7086 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7087
7088 ins_cost(DEFAULT_COST*2); // Don't count constant.
7089 expand %{
7090 // We add first, then we shift. Like this, we can get along with one register less.
7091 // But we have to load the base pre-shifted.
7092 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7093 iRegLdst base;
7094 loadConL_Ex(base, baseImm);
7095 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7096 %}
7097 %}
7098
7099 //----------MemBar Instructions-----------------------------------------------
7100 // Memory barrier flavors
7101
7102 instruct membar_acquire() %{
7103 match(LoadFence);
7104 ins_cost(4*MEMORY_REF_COST);
7105
7106 format %{ "MEMBAR-acquire" %}
7107 size(4);
7108 ins_encode %{
7109 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7110 __ acquire();
7111 %}
7112 ins_pipe(pipe_class_default);
7113 %}
7114
7115 instruct unnecessary_membar_acquire() %{
7116 match(MemBarAcquire);
7117 ins_cost(0);
7118
7119 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7120 size(0);
7121 ins_encode( /*empty*/ );
7122 ins_pipe(pipe_class_default);
7123 %}
7124
7125 instruct membar_acquire_lock() %{
7126 match(MemBarAcquireLock);
7127 ins_cost(0);
7128
7129 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7130 size(0);
7131 ins_encode( /*empty*/ );
7132 ins_pipe(pipe_class_default);
7133 %}
7134
7135 instruct membar_release() %{
7136 match(MemBarRelease);
7137 match(StoreFence);
7138 ins_cost(4*MEMORY_REF_COST);
7139
7140 format %{ "MEMBAR-release" %}
7141 size(4);
7142 ins_encode %{
7143 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7144 __ release();
7145 %}
7146 ins_pipe(pipe_class_default);
7147 %}
7148
7149 instruct membar_storestore() %{
7150 match(MemBarStoreStore);
7151 ins_cost(4*MEMORY_REF_COST);
7152
7153 format %{ "MEMBAR-store-store" %}
7154 size(4);
7155 ins_encode %{
7156 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7157 __ membar(Assembler::StoreStore);
7158 %}
7159 ins_pipe(pipe_class_default);
7160 %}
7161
7162 instruct membar_release_lock() %{
7163 match(MemBarReleaseLock);
7164 ins_cost(0);
7165
7166 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7167 size(0);
7168 ins_encode( /*empty*/ );
7169 ins_pipe(pipe_class_default);
7170 %}
7171
7172 instruct membar_volatile() %{
7173 match(MemBarVolatile);
7174 ins_cost(4*MEMORY_REF_COST);
7175
7176 format %{ "MEMBAR-volatile" %}
7177 size(4);
7178 ins_encode %{
7179 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7180 __ fence();
7181 %}
7182 ins_pipe(pipe_class_default);
7183 %}
7184
7185 // This optimization is wrong on PPC. The following pattern is not supported:
7186 // MemBarVolatile
7187 // ^ ^
7188 // | |
7189 // CtrlProj MemProj
7190 // ^ ^
7191 // | |
7192 // | Load
7193 // |
7194 // MemBarVolatile
7195 //
7196 // The first MemBarVolatile could get optimized out! According to
7197 // Vladimir, this pattern can not occur on Oracle platforms.
7198 // However, it does occur on PPC64 (because of membars in
7199 // inline_unsafe_load_store).
7200 //
7201 // Add this node again if we found a good solution for inline_unsafe_load_store().
7202 // Don't forget to look at the implementation of post_store_load_barrier again,
7203 // we did other fixes in that method.
7204 //instruct unnecessary_membar_volatile() %{
7205 // match(MemBarVolatile);
7206 // predicate(Matcher::post_store_load_barrier(n));
7207 // ins_cost(0);
7208 //
7209 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7210 // size(0);
7211 // ins_encode( /*empty*/ );
7212 // ins_pipe(pipe_class_default);
7213 //%}
7214
7215 instruct membar_CPUOrder() %{
7216 match(MemBarCPUOrder);
7217 ins_cost(0);
7218
7219 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7220 size(0);
7221 ins_encode( /*empty*/ );
7222 ins_pipe(pipe_class_default);
7223 %}
7224
7225 //----------Conditional Move---------------------------------------------------
7226
7227 // Cmove using isel.
7228 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7229 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7230 predicate(VM_Version::has_isel());
7231 ins_cost(DEFAULT_COST);
7232
7233 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7234 size(4);
7235 ins_encode %{
7236 // This is a Power7 instruction for which no machine description
7237 // exists. Anyways, the scheduler should be off on Power7.
7238 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7239 int cc = $cmp$$cmpcode;
7240 __ isel($dst$$Register, $crx$$CondRegister,
7241 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7242 %}
7243 ins_pipe(pipe_class_default);
7244 %}
7245
7246 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7247 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7248 predicate(!VM_Version::has_isel());
7249 ins_cost(DEFAULT_COST+BRANCH_COST);
7250
7251 ins_variable_size_depending_on_alignment(true);
7252
7253 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7254 // Worst case is branch + move + stop, no stop without scheduler
7255 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7256 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7257 ins_pipe(pipe_class_default);
7258 %}
7259
7260 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7261 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7262 ins_cost(DEFAULT_COST+BRANCH_COST);
7263
7264 ins_variable_size_depending_on_alignment(true);
7265
7266 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7267 // Worst case is branch + move + stop, no stop without scheduler
7268 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7269 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7270 ins_pipe(pipe_class_default);
7271 %}
7272
7273 // Cmove using isel.
7274 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7275 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7276 predicate(VM_Version::has_isel());
7277 ins_cost(DEFAULT_COST);
7278
7279 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7280 size(4);
7281 ins_encode %{
7282 // This is a Power7 instruction for which no machine description
7283 // exists. Anyways, the scheduler should be off on Power7.
7284 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7285 int cc = $cmp$$cmpcode;
7286 __ isel($dst$$Register, $crx$$CondRegister,
7287 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7288 %}
7289 ins_pipe(pipe_class_default);
7290 %}
7291
7292 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7293 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7294 predicate(!VM_Version::has_isel());
7295 ins_cost(DEFAULT_COST+BRANCH_COST);
7296
7297 ins_variable_size_depending_on_alignment(true);
7298
7299 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7300 // Worst case is branch + move + stop, no stop without scheduler.
7301 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7302 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7303 ins_pipe(pipe_class_default);
7304 %}
7305
7306 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7307 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7308 ins_cost(DEFAULT_COST+BRANCH_COST);
7309
7310 ins_variable_size_depending_on_alignment(true);
7311
7312 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7313 // Worst case is branch + move + stop, no stop without scheduler.
7314 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7315 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7316 ins_pipe(pipe_class_default);
7317 %}
7318
7319 // Cmove using isel.
7320 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7321 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7322 predicate(VM_Version::has_isel());
7323 ins_cost(DEFAULT_COST);
7324
7325 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7326 size(4);
7327 ins_encode %{
7328 // This is a Power7 instruction for which no machine description
7329 // exists. Anyways, the scheduler should be off on Power7.
7330 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7331 int cc = $cmp$$cmpcode;
7332 __ isel($dst$$Register, $crx$$CondRegister,
7333 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7334 %}
7335 ins_pipe(pipe_class_default);
7336 %}
7337
7338 // Conditional move for RegN. Only cmov(reg, reg).
7339 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7340 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7341 predicate(!VM_Version::has_isel());
7342 ins_cost(DEFAULT_COST+BRANCH_COST);
7343
7344 ins_variable_size_depending_on_alignment(true);
7345
7346 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7347 // Worst case is branch + move + stop, no stop without scheduler.
7348 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7349 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7350 ins_pipe(pipe_class_default);
7351 %}
7352
7353 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7354 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7355 ins_cost(DEFAULT_COST+BRANCH_COST);
7356
7357 ins_variable_size_depending_on_alignment(true);
7358
7359 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7360 // Worst case is branch + move + stop, no stop without scheduler.
7361 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7362 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7363 ins_pipe(pipe_class_default);
7364 %}
7365
7366 // Cmove using isel.
7367 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7368 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7369 predicate(VM_Version::has_isel());
7370 ins_cost(DEFAULT_COST);
7371
7372 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7373 size(4);
7374 ins_encode %{
7375 // This is a Power7 instruction for which no machine description
7376 // exists. Anyways, the scheduler should be off on Power7.
7377 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7378 int cc = $cmp$$cmpcode;
7379 __ isel($dst$$Register, $crx$$CondRegister,
7380 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7381 %}
7382 ins_pipe(pipe_class_default);
7383 %}
7384
7385 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7386 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7387 predicate(!VM_Version::has_isel());
7388 ins_cost(DEFAULT_COST+BRANCH_COST);
7389
7390 ins_variable_size_depending_on_alignment(true);
7391
7392 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7393 // Worst case is branch + move + stop, no stop without scheduler.
7394 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7395 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7396 ins_pipe(pipe_class_default);
7397 %}
7398
7399 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7400 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7401 ins_cost(DEFAULT_COST+BRANCH_COST);
7402
7403 ins_variable_size_depending_on_alignment(true);
7404
7405 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7406 // Worst case is branch + move + stop, no stop without scheduler.
7407 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7408 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7409 ins_pipe(pipe_class_default);
7410 %}
7411
7412 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7413 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7414 ins_cost(DEFAULT_COST+BRANCH_COST);
7415
7416 ins_variable_size_depending_on_alignment(true);
7417
7418 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7419 // Worst case is branch + move + stop, no stop without scheduler.
7420 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7421 ins_encode %{
7422 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7423 Label done;
7424 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7425 // Branch if not (cmp crx).
7426 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7427 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7428 // TODO PPC port __ endgroup_if_needed(_size == 12);
7429 __ bind(done);
7430 %}
7431 ins_pipe(pipe_class_default);
7432 %}
7433
7434 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7435 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7436 ins_cost(DEFAULT_COST+BRANCH_COST);
7437
7438 ins_variable_size_depending_on_alignment(true);
7439
7440 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7441 // Worst case is branch + move + stop, no stop without scheduler.
7442 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7443 ins_encode %{
7444 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7445 Label done;
7446 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7447 // Branch if not (cmp crx).
7448 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7449 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7450 // TODO PPC port __ endgroup_if_needed(_size == 12);
7451 __ bind(done);
7452 %}
7453 ins_pipe(pipe_class_default);
7454 %}
7455
7456 //----------Conditional_store--------------------------------------------------
7457 // Conditional-store of the updated heap-top.
7458 // Used during allocation of the shared heap.
7459 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7460
7461 // As compareAndSwapL, but return flag register instead of boolean value in
7462 // int register.
7463 // Used by sun/misc/AtomicLongCSImpl.java.
7464 // Mem_ptr must be a memory operand, else this node does not get
7465 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7466 // can be rematerialized which leads to errors.
7467 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7468 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7469 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7470 ins_encode %{
7471 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7472 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7473 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7474 noreg, NULL, true);
7475 %}
7476 ins_pipe(pipe_class_default);
7477 %}
7478
7479 // As compareAndSwapP, but return flag register instead of boolean value in
7480 // int register.
7481 // This instruction is matched if UseTLAB is off.
7482 // Mem_ptr must be a memory operand, else this node does not get
7483 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7484 // can be rematerialized which leads to errors.
7485 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7486 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7487 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7488 ins_encode %{
7489 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7490 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7491 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7492 noreg, NULL, true);
7493 %}
7494 ins_pipe(pipe_class_default);
7495 %}
7496
7497 // Implement LoadPLocked. Must be ordered against changes of the memory location
7498 // by storePConditional.
7499 // Don't know whether this is ever used.
7500 instruct loadPLocked(iRegPdst dst, memory mem) %{
7501 match(Set dst (LoadPLocked mem));
7502 ins_cost(MEMORY_REF_COST);
7503
7504 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7505 "TWI $dst\n\t"
7506 "ISYNC" %}
7507 size(12);
7508 ins_encode( enc_ld_ac(dst, mem) );
7509 ins_pipe(pipe_class_memory);
7510 %}
7511
7512 //----------Compare-And-Swap---------------------------------------------------
7513
7514 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7515 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7516 // matched.
7517
7518 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7519 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7520 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7521 // Variable size: instruction count smaller if regs are disjoint.
7522 ins_encode %{
7523 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7524 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7525 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7526 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7527 $res$$Register, true);
7528 %}
7529 ins_pipe(pipe_class_default);
7530 %}
7531
7532 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7533 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7534 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7535 // Variable size: instruction count smaller if regs are disjoint.
7536 ins_encode %{
7537 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7538 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7539 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7540 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7541 $res$$Register, true);
7542 %}
7543 ins_pipe(pipe_class_default);
7544 %}
7545
7546 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7547 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7548 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7549 // Variable size: instruction count smaller if regs are disjoint.
7550 ins_encode %{
7551 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7552 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7553 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7554 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7555 $res$$Register, NULL, true);
7556 %}
7557 ins_pipe(pipe_class_default);
7558 %}
7559
7560 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7561 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7562 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7563 // Variable size: instruction count smaller if regs are disjoint.
7564 ins_encode %{
7565 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7566 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7567 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7568 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7569 $res$$Register, NULL, true);
7570 %}
7571 ins_pipe(pipe_class_default);
7572 %}
7573
7574 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7575 match(Set res (GetAndAddI mem_ptr src));
7576 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7577 // Variable size: instruction count smaller if regs are disjoint.
7578 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7579 ins_pipe(pipe_class_default);
7580 %}
7581
7582 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7583 match(Set res (GetAndAddL mem_ptr src));
7584 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7585 // Variable size: instruction count smaller if regs are disjoint.
7586 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7587 ins_pipe(pipe_class_default);
7588 %}
7589
7590 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7591 match(Set res (GetAndSetI mem_ptr src));
7592 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7593 // Variable size: instruction count smaller if regs are disjoint.
7594 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7595 ins_pipe(pipe_class_default);
7596 %}
7597
7598 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7599 match(Set res (GetAndSetL mem_ptr src));
7600 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7601 // Variable size: instruction count smaller if regs are disjoint.
7602 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7603 ins_pipe(pipe_class_default);
7604 %}
7605
7606 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7607 match(Set res (GetAndSetP mem_ptr src));
7608 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7609 // Variable size: instruction count smaller if regs are disjoint.
7610 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7611 ins_pipe(pipe_class_default);
7612 %}
7613
7614 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7615 match(Set res (GetAndSetN mem_ptr src));
7616 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7617 // Variable size: instruction count smaller if regs are disjoint.
7618 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7619 ins_pipe(pipe_class_default);
7620 %}
7621
7622 //----------Arithmetic Instructions--------------------------------------------
7623 // Addition Instructions
7624
7625 // Register Addition
7626 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7627 match(Set dst (AddI src1 src2));
7628 format %{ "ADD $dst, $src1, $src2" %}
7629 size(4);
7630 ins_encode %{
7631 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7632 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7633 %}
7634 ins_pipe(pipe_class_default);
7635 %}
7636
7637 // Expand does not work with above instruct. (??)
7638 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7639 // no match-rule
7640 effect(DEF dst, USE src1, USE src2);
7641 format %{ "ADD $dst, $src1, $src2" %}
7642 size(4);
7643 ins_encode %{
7644 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7645 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7646 %}
7647 ins_pipe(pipe_class_default);
7648 %}
7649
7650 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7651 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7652 ins_cost(DEFAULT_COST*3);
7653
7654 expand %{
7655 // FIXME: we should do this in the ideal world.
7656 iRegIdst tmp1;
7657 iRegIdst tmp2;
7658 addI_reg_reg(tmp1, src1, src2);
7659 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7660 addI_reg_reg(dst, tmp1, tmp2);
7661 %}
7662 %}
7663
7664 // Immediate Addition
7665 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7666 match(Set dst (AddI src1 src2));
7667 format %{ "ADDI $dst, $src1, $src2" %}
7668 size(4);
7669 ins_encode %{
7670 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7671 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7672 %}
7673 ins_pipe(pipe_class_default);
7674 %}
7675
7676 // Immediate Addition with 16-bit shifted operand
7677 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7678 match(Set dst (AddI src1 src2));
7679 format %{ "ADDIS $dst, $src1, $src2" %}
7680 size(4);
7681 ins_encode %{
7682 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7683 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7684 %}
7685 ins_pipe(pipe_class_default);
7686 %}
7687
7688 // Long Addition
7689 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7690 match(Set dst (AddL src1 src2));
7691 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7692 size(4);
7693 ins_encode %{
7694 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7695 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7696 %}
7697 ins_pipe(pipe_class_default);
7698 %}
7699
7700 // Expand does not work with above instruct. (??)
7701 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7702 // no match-rule
7703 effect(DEF dst, USE src1, USE src2);
7704 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7705 size(4);
7706 ins_encode %{
7707 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7708 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7709 %}
7710 ins_pipe(pipe_class_default);
7711 %}
7712
7713 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7714 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7715 ins_cost(DEFAULT_COST*3);
7716
7717 expand %{
7718 // FIXME: we should do this in the ideal world.
7719 iRegLdst tmp1;
7720 iRegLdst tmp2;
7721 addL_reg_reg(tmp1, src1, src2);
7722 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7723 addL_reg_reg(dst, tmp1, tmp2);
7724 %}
7725 %}
7726
7727 // AddL + ConvL2I.
7728 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7729 match(Set dst (ConvL2I (AddL src1 src2)));
7730
7731 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7732 size(4);
7733 ins_encode %{
7734 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7735 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7736 %}
7737 ins_pipe(pipe_class_default);
7738 %}
7739
7740 // No constant pool entries required.
7741 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7742 match(Set dst (AddL src1 src2));
7743
7744 format %{ "ADDI $dst, $src1, $src2" %}
7745 size(4);
7746 ins_encode %{
7747 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7748 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7749 %}
7750 ins_pipe(pipe_class_default);
7751 %}
7752
7753 // Long Immediate Addition with 16-bit shifted operand.
7754 // No constant pool entries required.
7755 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7756 match(Set dst (AddL src1 src2));
7757
7758 format %{ "ADDIS $dst, $src1, $src2" %}
7759 size(4);
7760 ins_encode %{
7761 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7762 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7763 %}
7764 ins_pipe(pipe_class_default);
7765 %}
7766
7767 // Pointer Register Addition
7768 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7769 match(Set dst (AddP src1 src2));
7770 format %{ "ADD $dst, $src1, $src2" %}
7771 size(4);
7772 ins_encode %{
7773 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7774 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7775 %}
7776 ins_pipe(pipe_class_default);
7777 %}
7778
7779 // Pointer Immediate Addition
7780 // No constant pool entries required.
7781 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7782 match(Set dst (AddP src1 src2));
7783
7784 format %{ "ADDI $dst, $src1, $src2" %}
7785 size(4);
7786 ins_encode %{
7787 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7788 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7789 %}
7790 ins_pipe(pipe_class_default);
7791 %}
7792
7793 // Pointer Immediate Addition with 16-bit shifted operand.
7794 // No constant pool entries required.
7795 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7796 match(Set dst (AddP src1 src2));
7797
7798 format %{ "ADDIS $dst, $src1, $src2" %}
7799 size(4);
7800 ins_encode %{
7801 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7802 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7803 %}
7804 ins_pipe(pipe_class_default);
7805 %}
7806
7807 //---------------------
7808 // Subtraction Instructions
7809
7810 // Register Subtraction
7811 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7812 match(Set dst (SubI src1 src2));
7813 format %{ "SUBF $dst, $src2, $src1" %}
7814 size(4);
7815 ins_encode %{
7816 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7817 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7818 %}
7819 ins_pipe(pipe_class_default);
7820 %}
7821
7822 // Immediate Subtraction
7823 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7824 // so this rule seems to be unused.
7825 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7826 match(Set dst (SubI src1 src2));
7827 format %{ "SUBI $dst, $src1, $src2" %}
7828 size(4);
7829 ins_encode %{
7830 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7831 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7832 %}
7833 ins_pipe(pipe_class_default);
7834 %}
7835
7836 // SubI from constant (using subfic).
7837 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7838 match(Set dst (SubI src1 src2));
7839 format %{ "SUBI $dst, $src1, $src2" %}
7840
7841 size(4);
7842 ins_encode %{
7843 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7844 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7845 %}
7846 ins_pipe(pipe_class_default);
7847 %}
7848
7849 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7850 // positive integers and 0xF...F for negative ones.
7851 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7852 // no match-rule, false predicate
7853 effect(DEF dst, USE src);
7854 predicate(false);
7855
7856 format %{ "SRAWI $dst, $src, #31" %}
7857 size(4);
7858 ins_encode %{
7859 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7860 __ srawi($dst$$Register, $src$$Register, 0x1f);
7861 %}
7862 ins_pipe(pipe_class_default);
7863 %}
7864
7865 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7866 match(Set dst (AbsI src));
7867 ins_cost(DEFAULT_COST*3);
7868
7869 expand %{
7870 iRegIdst tmp1;
7871 iRegIdst tmp2;
7872 signmask32I_regI(tmp1, src);
7873 xorI_reg_reg(tmp2, tmp1, src);
7874 subI_reg_reg(dst, tmp2, tmp1);
7875 %}
7876 %}
7877
7878 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7879 match(Set dst (SubI zero src2));
7880 format %{ "NEG $dst, $src2" %}
7881 size(4);
7882 ins_encode %{
7883 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7884 __ neg($dst$$Register, $src2$$Register);
7885 %}
7886 ins_pipe(pipe_class_default);
7887 %}
7888
7889 // Long subtraction
7890 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7891 match(Set dst (SubL src1 src2));
7892 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7893 size(4);
7894 ins_encode %{
7895 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7896 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7897 %}
7898 ins_pipe(pipe_class_default);
7899 %}
7900
7901 // SubL + convL2I.
7902 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7903 match(Set dst (ConvL2I (SubL src1 src2)));
7904
7905 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7906 size(4);
7907 ins_encode %{
7908 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7909 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7910 %}
7911 ins_pipe(pipe_class_default);
7912 %}
7913
7914 // Immediate Subtraction
7915 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7916 // so this rule seems to be unused.
7917 // No constant pool entries required.
7918 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7919 match(Set dst (SubL src1 src2));
7920
7921 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7922 size(4);
7923 ins_encode %{
7924 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7925 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7926 %}
7927 ins_pipe(pipe_class_default);
7928 %}
7929
7930 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7931 // positive longs and 0xF...F for negative ones.
7932 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
7933 // no match-rule, false predicate
7934 effect(DEF dst, USE src);
7935 predicate(false);
7936
7937 format %{ "SRADI $dst, $src, #63" %}
7938 size(4);
7939 ins_encode %{
7940 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7941 __ sradi($dst$$Register, $src$$Register, 0x3f);
7942 %}
7943 ins_pipe(pipe_class_default);
7944 %}
7945
7946 // Long negation
7947 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7948 match(Set dst (SubL zero src2));
7949 format %{ "NEG $dst, $src2 \t// long" %}
7950 size(4);
7951 ins_encode %{
7952 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7953 __ neg($dst$$Register, $src2$$Register);
7954 %}
7955 ins_pipe(pipe_class_default);
7956 %}
7957
7958 // NegL + ConvL2I.
7959 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7960 match(Set dst (ConvL2I (SubL zero src2)));
7961
7962 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7963 size(4);
7964 ins_encode %{
7965 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7966 __ neg($dst$$Register, $src2$$Register);
7967 %}
7968 ins_pipe(pipe_class_default);
7969 %}
7970
7971 // Multiplication Instructions
7972 // Integer Multiplication
7973
7974 // Register Multiplication
7975 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7976 match(Set dst (MulI src1 src2));
7977 ins_cost(DEFAULT_COST);
7978
7979 format %{ "MULLW $dst, $src1, $src2" %}
7980 size(4);
7981 ins_encode %{
7982 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
7983 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
7984 %}
7985 ins_pipe(pipe_class_default);
7986 %}
7987
7988 // Immediate Multiplication
7989 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7990 match(Set dst (MulI src1 src2));
7991 ins_cost(DEFAULT_COST);
7992
7993 format %{ "MULLI $dst, $src1, $src2" %}
7994 size(4);
7995 ins_encode %{
7996 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7997 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7998 %}
7999 ins_pipe(pipe_class_default);
8000 %}
8001
8002 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8003 match(Set dst (MulL src1 src2));
8004 ins_cost(DEFAULT_COST);
8005
8006 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8007 size(4);
8008 ins_encode %{
8009 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8010 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8011 %}
8012 ins_pipe(pipe_class_default);
8013 %}
8014
8015 // Multiply high for optimized long division by constant.
8016 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8017 match(Set dst (MulHiL src1 src2));
8018 ins_cost(DEFAULT_COST);
8019
8020 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8021 size(4);
8022 ins_encode %{
8023 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8024 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8025 %}
8026 ins_pipe(pipe_class_default);
8027 %}
8028
8029 // Immediate Multiplication
8030 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8031 match(Set dst (MulL src1 src2));
8032 ins_cost(DEFAULT_COST);
8033
8034 format %{ "MULLI $dst, $src1, $src2" %}
8035 size(4);
8036 ins_encode %{
8037 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8038 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8039 %}
8040 ins_pipe(pipe_class_default);
8041 %}
8042
8043 // Integer Division with Immediate -1: Negate.
8044 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8045 match(Set dst (DivI src1 src2));
8046 ins_cost(DEFAULT_COST);
8047
8048 format %{ "NEG $dst, $src1 \t// /-1" %}
8049 size(4);
8050 ins_encode %{
8051 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8052 __ neg($dst$$Register, $src1$$Register);
8053 %}
8054 ins_pipe(pipe_class_default);
8055 %}
8056
8057 // Integer Division with constant, but not -1.
8058 // We should be able to improve this by checking the type of src2.
8059 // It might well be that src2 is known to be positive.
8060 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8061 match(Set dst (DivI src1 src2));
8062 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8063 ins_cost(2*DEFAULT_COST);
8064
8065 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8066 size(4);
8067 ins_encode %{
8068 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8069 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8070 %}
8071 ins_pipe(pipe_class_default);
8072 %}
8073
8074 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8075 effect(USE_DEF dst, USE src1, USE crx);
8076 predicate(false);
8077
8078 ins_variable_size_depending_on_alignment(true);
8079
8080 format %{ "CMOVE $dst, neg($src1), $crx" %}
8081 // Worst case is branch + move + stop, no stop without scheduler.
8082 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8083 ins_encode %{
8084 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8085 Label done;
8086 __ bne($crx$$CondRegister, done);
8087 __ neg($dst$$Register, $src1$$Register);
8088 // TODO PPC port __ endgroup_if_needed(_size == 12);
8089 __ bind(done);
8090 %}
8091 ins_pipe(pipe_class_default);
8092 %}
8093
8094 // Integer Division with Registers not containing constants.
8095 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8096 match(Set dst (DivI src1 src2));
8097 ins_cost(10*DEFAULT_COST);
8098
8099 expand %{
8100 immI16 imm %{ (int)-1 %}
8101 flagsReg tmp1;
8102 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8103 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8104 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8105 %}
8106 %}
8107
8108 // Long Division with Immediate -1: Negate.
8109 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8110 match(Set dst (DivL src1 src2));
8111 ins_cost(DEFAULT_COST);
8112
8113 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8114 size(4);
8115 ins_encode %{
8116 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8117 __ neg($dst$$Register, $src1$$Register);
8118 %}
8119 ins_pipe(pipe_class_default);
8120 %}
8121
8122 // Long Division with constant, but not -1.
8123 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8124 match(Set dst (DivL src1 src2));
8125 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8126 ins_cost(2*DEFAULT_COST);
8127
8128 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8129 size(4);
8130 ins_encode %{
8131 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8132 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8133 %}
8134 ins_pipe(pipe_class_default);
8135 %}
8136
8137 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8138 effect(USE_DEF dst, USE src1, USE crx);
8139 predicate(false);
8140
8141 ins_variable_size_depending_on_alignment(true);
8142
8143 format %{ "CMOVE $dst, neg($src1), $crx" %}
8144 // Worst case is branch + move + stop, no stop without scheduler.
8145 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8146 ins_encode %{
8147 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8148 Label done;
8149 __ bne($crx$$CondRegister, done);
8150 __ neg($dst$$Register, $src1$$Register);
8151 // TODO PPC port __ endgroup_if_needed(_size == 12);
8152 __ bind(done);
8153 %}
8154 ins_pipe(pipe_class_default);
8155 %}
8156
8157 // Long Division with Registers not containing constants.
8158 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8159 match(Set dst (DivL src1 src2));
8160 ins_cost(10*DEFAULT_COST);
8161
8162 expand %{
8163 immL16 imm %{ (int)-1 %}
8164 flagsReg tmp1;
8165 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8166 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8167 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8168 %}
8169 %}
8170
8171 // Integer Remainder with registers.
8172 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8173 match(Set dst (ModI src1 src2));
8174 ins_cost(10*DEFAULT_COST);
8175
8176 expand %{
8177 immI16 imm %{ (int)-1 %}
8178 flagsReg tmp1;
8179 iRegIdst tmp2;
8180 iRegIdst tmp3;
8181 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8182 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8183 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8184 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8185 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8186 %}
8187 %}
8188
8189 // Long Remainder with registers
8190 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8191 match(Set dst (ModL src1 src2));
8192 ins_cost(10*DEFAULT_COST);
8193
8194 expand %{
8195 immL16 imm %{ (int)-1 %}
8196 flagsReg tmp1;
8197 iRegLdst tmp2;
8198 iRegLdst tmp3;
8199 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8200 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8201 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8202 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8203 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8204 %}
8205 %}
8206
8207 // Integer Shift Instructions
8208
8209 // Register Shift Left
8210
8211 // Clear all but the lowest #mask bits.
8212 // Used to normalize shift amounts in registers.
8213 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8214 // no match-rule, false predicate
8215 effect(DEF dst, USE src, USE mask);
8216 predicate(false);
8217
8218 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8219 size(4);
8220 ins_encode %{
8221 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8222 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8223 %}
8224 ins_pipe(pipe_class_default);
8225 %}
8226
8227 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8228 // no match-rule, false predicate
8229 effect(DEF dst, USE src1, USE src2);
8230 predicate(false);
8231
8232 format %{ "SLW $dst, $src1, $src2" %}
8233 size(4);
8234 ins_encode %{
8235 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8236 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8237 %}
8238 ins_pipe(pipe_class_default);
8239 %}
8240
8241 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8242 match(Set dst (LShiftI src1 src2));
8243 ins_cost(DEFAULT_COST*2);
8244 expand %{
8245 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8246 iRegIdst tmpI;
8247 maskI_reg_imm(tmpI, src2, mask);
8248 lShiftI_reg_reg(dst, src1, tmpI);
8249 %}
8250 %}
8251
8252 // Register Shift Left Immediate
8253 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8254 match(Set dst (LShiftI src1 src2));
8255
8256 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8257 size(4);
8258 ins_encode %{
8259 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8260 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8261 %}
8262 ins_pipe(pipe_class_default);
8263 %}
8264
8265 // AndI with negpow2-constant + LShiftI
8266 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8267 match(Set dst (LShiftI (AndI src1 src2) src3));
8268 predicate(UseRotateAndMaskInstructionsPPC64);
8269
8270 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8271 size(4);
8272 ins_encode %{
8273 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8274 long src2 = $src2$$constant;
8275 long src3 = $src3$$constant;
8276 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8277 if (maskbits >= 32) {
8278 __ li($dst$$Register, 0); // addi
8279 } else {
8280 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8281 }
8282 %}
8283 ins_pipe(pipe_class_default);
8284 %}
8285
8286 // RShiftI + AndI with negpow2-constant + LShiftI
8287 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8288 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8289 predicate(UseRotateAndMaskInstructionsPPC64);
8290
8291 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8292 size(4);
8293 ins_encode %{
8294 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8295 long src2 = $src2$$constant;
8296 long src3 = $src3$$constant;
8297 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8298 if (maskbits >= 32) {
8299 __ li($dst$$Register, 0); // addi
8300 } else {
8301 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8302 }
8303 %}
8304 ins_pipe(pipe_class_default);
8305 %}
8306
8307 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8308 // no match-rule, false predicate
8309 effect(DEF dst, USE src1, USE src2);
8310 predicate(false);
8311
8312 format %{ "SLD $dst, $src1, $src2" %}
8313 size(4);
8314 ins_encode %{
8315 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8316 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8317 %}
8318 ins_pipe(pipe_class_default);
8319 %}
8320
8321 // Register Shift Left
8322 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8323 match(Set dst (LShiftL src1 src2));
8324 ins_cost(DEFAULT_COST*2);
8325 expand %{
8326 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8327 iRegIdst tmpI;
8328 maskI_reg_imm(tmpI, src2, mask);
8329 lShiftL_regL_regI(dst, src1, tmpI);
8330 %}
8331 %}
8332
8333 // Register Shift Left Immediate
8334 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8335 match(Set dst (LShiftL src1 src2));
8336 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8337 size(4);
8338 ins_encode %{
8339 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8340 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8341 %}
8342 ins_pipe(pipe_class_default);
8343 %}
8344
8345 // If we shift more than 32 bits, we need not convert I2L.
8346 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8347 match(Set dst (LShiftL (ConvI2L src1) src2));
8348 ins_cost(DEFAULT_COST);
8349
8350 size(4);
8351 format %{ "SLDI $dst, i2l($src1), $src2" %}
8352 ins_encode %{
8353 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8354 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8355 %}
8356 ins_pipe(pipe_class_default);
8357 %}
8358
8359 // Shift a postivie int to the left.
8360 // Clrlsldi clears the upper 32 bits and shifts.
8361 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8362 match(Set dst (LShiftL (ConvI2L src1) src2));
8363 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8364
8365 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8366 size(4);
8367 ins_encode %{
8368 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8369 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8370 %}
8371 ins_pipe(pipe_class_default);
8372 %}
8373
8374 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8375 // no match-rule, false predicate
8376 effect(DEF dst, USE src1, USE src2);
8377 predicate(false);
8378
8379 format %{ "SRAW $dst, $src1, $src2" %}
8380 size(4);
8381 ins_encode %{
8382 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8383 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8384 %}
8385 ins_pipe(pipe_class_default);
8386 %}
8387
8388 // Register Arithmetic Shift Right
8389 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8390 match(Set dst (RShiftI src1 src2));
8391 ins_cost(DEFAULT_COST*2);
8392 expand %{
8393 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8394 iRegIdst tmpI;
8395 maskI_reg_imm(tmpI, src2, mask);
8396 arShiftI_reg_reg(dst, src1, tmpI);
8397 %}
8398 %}
8399
8400 // Register Arithmetic Shift Right Immediate
8401 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8402 match(Set dst (RShiftI src1 src2));
8403
8404 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8405 size(4);
8406 ins_encode %{
8407 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8408 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8409 %}
8410 ins_pipe(pipe_class_default);
8411 %}
8412
8413 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8414 // no match-rule, false predicate
8415 effect(DEF dst, USE src1, USE src2);
8416 predicate(false);
8417
8418 format %{ "SRAD $dst, $src1, $src2" %}
8419 size(4);
8420 ins_encode %{
8421 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8422 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8423 %}
8424 ins_pipe(pipe_class_default);
8425 %}
8426
8427 // Register Shift Right Arithmetic Long
8428 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8429 match(Set dst (RShiftL src1 src2));
8430 ins_cost(DEFAULT_COST*2);
8431
8432 expand %{
8433 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8434 iRegIdst tmpI;
8435 maskI_reg_imm(tmpI, src2, mask);
8436 arShiftL_regL_regI(dst, src1, tmpI);
8437 %}
8438 %}
8439
8440 // Register Shift Right Immediate
8441 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8442 match(Set dst (RShiftL src1 src2));
8443
8444 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8445 size(4);
8446 ins_encode %{
8447 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8448 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8449 %}
8450 ins_pipe(pipe_class_default);
8451 %}
8452
8453 // RShiftL + ConvL2I
8454 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8455 match(Set dst (ConvL2I (RShiftL src1 src2)));
8456
8457 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8458 size(4);
8459 ins_encode %{
8460 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8461 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8462 %}
8463 ins_pipe(pipe_class_default);
8464 %}
8465
8466 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8467 // no match-rule, false predicate
8468 effect(DEF dst, USE src1, USE src2);
8469 predicate(false);
8470
8471 format %{ "SRW $dst, $src1, $src2" %}
8472 size(4);
8473 ins_encode %{
8474 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8475 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8476 %}
8477 ins_pipe(pipe_class_default);
8478 %}
8479
8480 // Register Shift Right
8481 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8482 match(Set dst (URShiftI src1 src2));
8483 ins_cost(DEFAULT_COST*2);
8484
8485 expand %{
8486 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8487 iRegIdst tmpI;
8488 maskI_reg_imm(tmpI, src2, mask);
8489 urShiftI_reg_reg(dst, src1, tmpI);
8490 %}
8491 %}
8492
8493 // Register Shift Right Immediate
8494 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8495 match(Set dst (URShiftI src1 src2));
8496
8497 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8498 size(4);
8499 ins_encode %{
8500 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8501 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8502 %}
8503 ins_pipe(pipe_class_default);
8504 %}
8505
8506 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8507 // no match-rule, false predicate
8508 effect(DEF dst, USE src1, USE src2);
8509 predicate(false);
8510
8511 format %{ "SRD $dst, $src1, $src2" %}
8512 size(4);
8513 ins_encode %{
8514 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8515 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8516 %}
8517 ins_pipe(pipe_class_default);
8518 %}
8519
8520 // Register Shift Right
8521 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8522 match(Set dst (URShiftL src1 src2));
8523 ins_cost(DEFAULT_COST*2);
8524
8525 expand %{
8526 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8527 iRegIdst tmpI;
8528 maskI_reg_imm(tmpI, src2, mask);
8529 urShiftL_regL_regI(dst, src1, tmpI);
8530 %}
8531 %}
8532
8533 // Register Shift Right Immediate
8534 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8535 match(Set dst (URShiftL src1 src2));
8536
8537 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8538 size(4);
8539 ins_encode %{
8540 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8541 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8542 %}
8543 ins_pipe(pipe_class_default);
8544 %}
8545
8546 // URShiftL + ConvL2I.
8547 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8548 match(Set dst (ConvL2I (URShiftL src1 src2)));
8549
8550 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8551 size(4);
8552 ins_encode %{
8553 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8554 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8555 %}
8556 ins_pipe(pipe_class_default);
8557 %}
8558
8559 // Register Shift Right Immediate with a CastP2X
8560 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8561 match(Set dst (URShiftL (CastP2X src1) src2));
8562
8563 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8564 size(4);
8565 ins_encode %{
8566 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8567 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8568 %}
8569 ins_pipe(pipe_class_default);
8570 %}
8571
8572 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8573 match(Set dst (ConvL2I (ConvI2L src)));
8574
8575 format %{ "EXTSW $dst, $src \t// int->int" %}
8576 size(4);
8577 ins_encode %{
8578 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8579 __ extsw($dst$$Register, $src$$Register);
8580 %}
8581 ins_pipe(pipe_class_default);
8582 %}
8583
8584 //----------Rotate Instructions------------------------------------------------
8585
8586 // Rotate Left by 8-bit immediate
8587 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8588 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8589 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8590
8591 format %{ "ROTLWI $dst, $src, $lshift" %}
8592 size(4);
8593 ins_encode %{
8594 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8595 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8596 %}
8597 ins_pipe(pipe_class_default);
8598 %}
8599
8600 // Rotate Right by 8-bit immediate
8601 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8602 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8603 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8604
8605 format %{ "ROTRWI $dst, $rshift" %}
8606 size(4);
8607 ins_encode %{
8608 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8609 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8610 %}
8611 ins_pipe(pipe_class_default);
8612 %}
8613
8614 //----------Floating Point Arithmetic Instructions-----------------------------
8615
8616 // Add float single precision
8617 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8618 match(Set dst (AddF src1 src2));
8619
8620 format %{ "FADDS $dst, $src1, $src2" %}
8621 size(4);
8622 ins_encode %{
8623 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8624 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8625 %}
8626 ins_pipe(pipe_class_default);
8627 %}
8628
8629 // Add float double precision
8630 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8631 match(Set dst (AddD src1 src2));
8632
8633 format %{ "FADD $dst, $src1, $src2" %}
8634 size(4);
8635 ins_encode %{
8636 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8637 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8638 %}
8639 ins_pipe(pipe_class_default);
8640 %}
8641
8642 // Sub float single precision
8643 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8644 match(Set dst (SubF src1 src2));
8645
8646 format %{ "FSUBS $dst, $src1, $src2" %}
8647 size(4);
8648 ins_encode %{
8649 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8650 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8651 %}
8652 ins_pipe(pipe_class_default);
8653 %}
8654
8655 // Sub float double precision
8656 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8657 match(Set dst (SubD src1 src2));
8658 format %{ "FSUB $dst, $src1, $src2" %}
8659 size(4);
8660 ins_encode %{
8661 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8662 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8663 %}
8664 ins_pipe(pipe_class_default);
8665 %}
8666
8667 // Mul float single precision
8668 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8669 match(Set dst (MulF src1 src2));
8670 format %{ "FMULS $dst, $src1, $src2" %}
8671 size(4);
8672 ins_encode %{
8673 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8674 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8675 %}
8676 ins_pipe(pipe_class_default);
8677 %}
8678
8679 // Mul float double precision
8680 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8681 match(Set dst (MulD src1 src2));
8682 format %{ "FMUL $dst, $src1, $src2" %}
8683 size(4);
8684 ins_encode %{
8685 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8686 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8687 %}
8688 ins_pipe(pipe_class_default);
8689 %}
8690
8691 // Div float single precision
8692 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8693 match(Set dst (DivF src1 src2));
8694 format %{ "FDIVS $dst, $src1, $src2" %}
8695 size(4);
8696 ins_encode %{
8697 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8698 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8699 %}
8700 ins_pipe(pipe_class_default);
8701 %}
8702
8703 // Div float double precision
8704 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8705 match(Set dst (DivD src1 src2));
8706 format %{ "FDIV $dst, $src1, $src2" %}
8707 size(4);
8708 ins_encode %{
8709 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8710 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8711 %}
8712 ins_pipe(pipe_class_default);
8713 %}
8714
8715 // Absolute float single precision
8716 instruct absF_reg(regF dst, regF src) %{
8717 match(Set dst (AbsF src));
8718 format %{ "FABS $dst, $src \t// float" %}
8719 size(4);
8720 ins_encode %{
8721 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8722 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8723 %}
8724 ins_pipe(pipe_class_default);
8725 %}
8726
8727 // Absolute float double precision
8728 instruct absD_reg(regD dst, regD src) %{
8729 match(Set dst (AbsD src));
8730 format %{ "FABS $dst, $src \t// double" %}
8731 size(4);
8732 ins_encode %{
8733 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8734 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8735 %}
8736 ins_pipe(pipe_class_default);
8737 %}
8738
8739 instruct negF_reg(regF dst, regF src) %{
8740 match(Set dst (NegF src));
8741 format %{ "FNEG $dst, $src \t// float" %}
8742 size(4);
8743 ins_encode %{
8744 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8745 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8746 %}
8747 ins_pipe(pipe_class_default);
8748 %}
8749
8750 instruct negD_reg(regD dst, regD src) %{
8751 match(Set dst (NegD src));
8752 format %{ "FNEG $dst, $src \t// double" %}
8753 size(4);
8754 ins_encode %{
8755 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8756 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8757 %}
8758 ins_pipe(pipe_class_default);
8759 %}
8760
8761 // AbsF + NegF.
8762 instruct negF_absF_reg(regF dst, regF src) %{
8763 match(Set dst (NegF (AbsF src)));
8764 format %{ "FNABS $dst, $src \t// float" %}
8765 size(4);
8766 ins_encode %{
8767 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8768 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8769 %}
8770 ins_pipe(pipe_class_default);
8771 %}
8772
8773 // AbsD + NegD.
8774 instruct negD_absD_reg(regD dst, regD src) %{
8775 match(Set dst (NegD (AbsD src)));
8776 format %{ "FNABS $dst, $src \t// double" %}
8777 size(4);
8778 ins_encode %{
8779 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8780 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8781 %}
8782 ins_pipe(pipe_class_default);
8783 %}
8784
8785 // VM_Version::has_fsqrt() decides if this node will be used.
8786 // Sqrt float double precision
8787 instruct sqrtD_reg(regD dst, regD src) %{
8788 match(Set dst (SqrtD src));
8789 format %{ "FSQRT $dst, $src" %}
8790 size(4);
8791 ins_encode %{
8792 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8793 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8794 %}
8795 ins_pipe(pipe_class_default);
8796 %}
8797
8798 // Single-precision sqrt.
8799 instruct sqrtF_reg(regF dst, regF src) %{
8800 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8801 ins_cost(DEFAULT_COST);
8802
8803 format %{ "FSQRTS $dst, $src" %}
8804 size(4);
8805 ins_encode %{
8806 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8807 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8808 %}
8809 ins_pipe(pipe_class_default);
8810 %}
8811
8812 instruct roundDouble_nop(regD dst) %{
8813 match(Set dst (RoundDouble dst));
8814 ins_cost(0);
8815
8816 format %{ " -- \t// RoundDouble not needed - empty" %}
8817 size(0);
8818 // PPC results are already "rounded" (i.e., normal-format IEEE).
8819 ins_encode( /*empty*/ );
8820 ins_pipe(pipe_class_default);
8821 %}
8822
8823 instruct roundFloat_nop(regF dst) %{
8824 match(Set dst (RoundFloat dst));
8825 ins_cost(0);
8826
8827 format %{ " -- \t// RoundFloat not needed - empty" %}
8828 size(0);
8829 // PPC results are already "rounded" (i.e., normal-format IEEE).
8830 ins_encode( /*empty*/ );
8831 ins_pipe(pipe_class_default);
8832 %}
8833
8834 //----------Logical Instructions-----------------------------------------------
8835
8836 // And Instructions
8837
8838 // Register And
8839 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8840 match(Set dst (AndI src1 src2));
8841 format %{ "AND $dst, $src1, $src2" %}
8842 size(4);
8843 ins_encode %{
8844 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8845 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8846 %}
8847 ins_pipe(pipe_class_default);
8848 %}
8849
8850 // Immediate And
8851 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8852 match(Set dst (AndI src1 src2));
8853 effect(KILL cr0);
8854
8855 format %{ "ANDI $dst, $src1, $src2" %}
8856 size(4);
8857 ins_encode %{
8858 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8859 // FIXME: avoid andi_ ?
8860 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8861 %}
8862 ins_pipe(pipe_class_default);
8863 %}
8864
8865 // Immediate And where the immediate is a negative power of 2.
8866 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8867 match(Set dst (AndI src1 src2));
8868 format %{ "ANDWI $dst, $src1, $src2" %}
8869 size(4);
8870 ins_encode %{
8871 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8872 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8873 %}
8874 ins_pipe(pipe_class_default);
8875 %}
8876
8877 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8878 match(Set dst (AndI src1 src2));
8879 format %{ "ANDWI $dst, $src1, $src2" %}
8880 size(4);
8881 ins_encode %{
8882 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8883 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8884 %}
8885 ins_pipe(pipe_class_default);
8886 %}
8887
8888 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8889 match(Set dst (AndI src1 src2));
8890 predicate(UseRotateAndMaskInstructionsPPC64);
8891 format %{ "ANDWI $dst, $src1, $src2" %}
8892 size(4);
8893 ins_encode %{
8894 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8895 __ rlwinm($dst$$Register, $src1$$Register, 0,
8896 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8897 %}
8898 ins_pipe(pipe_class_default);
8899 %}
8900
8901 // Register And Long
8902 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8903 match(Set dst (AndL src1 src2));
8904 ins_cost(DEFAULT_COST);
8905
8906 format %{ "AND $dst, $src1, $src2 \t// long" %}
8907 size(4);
8908 ins_encode %{
8909 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8910 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8911 %}
8912 ins_pipe(pipe_class_default);
8913 %}
8914
8915 // Immediate And long
8916 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8917 match(Set dst (AndL src1 src2));
8918 effect(KILL cr0);
8919 ins_cost(DEFAULT_COST);
8920
8921 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8922 size(4);
8923 ins_encode %{
8924 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8925 // FIXME: avoid andi_ ?
8926 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8927 %}
8928 ins_pipe(pipe_class_default);
8929 %}
8930
8931 // Immediate And Long where the immediate is a negative power of 2.
8932 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8933 match(Set dst (AndL src1 src2));
8934 format %{ "ANDDI $dst, $src1, $src2" %}
8935 size(4);
8936 ins_encode %{
8937 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8938 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8939 %}
8940 ins_pipe(pipe_class_default);
8941 %}
8942
8943 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8944 match(Set dst (AndL src1 src2));
8945 format %{ "ANDDI $dst, $src1, $src2" %}
8946 size(4);
8947 ins_encode %{
8948 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8949 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8950 %}
8951 ins_pipe(pipe_class_default);
8952 %}
8953
8954 // AndL + ConvL2I.
8955 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8956 match(Set dst (ConvL2I (AndL src1 src2)));
8957 ins_cost(DEFAULT_COST);
8958
8959 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8960 size(4);
8961 ins_encode %{
8962 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8963 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8964 %}
8965 ins_pipe(pipe_class_default);
8966 %}
8967
8968 // Or Instructions
8969
8970 // Register Or
8971 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8972 match(Set dst (OrI src1 src2));
8973 format %{ "OR $dst, $src1, $src2" %}
8974 size(4);
8975 ins_encode %{
8976 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8977 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8978 %}
8979 ins_pipe(pipe_class_default);
8980 %}
8981
8982 // Expand does not work with above instruct. (??)
8983 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8984 // no match-rule
8985 effect(DEF dst, USE src1, USE src2);
8986 format %{ "OR $dst, $src1, $src2" %}
8987 size(4);
8988 ins_encode %{
8989 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8990 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8991 %}
8992 ins_pipe(pipe_class_default);
8993 %}
8994
8995 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8996 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
8997 ins_cost(DEFAULT_COST*3);
8998
8999 expand %{
9000 // FIXME: we should do this in the ideal world.
9001 iRegIdst tmp1;
9002 iRegIdst tmp2;
9003 orI_reg_reg(tmp1, src1, src2);
9004 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9005 orI_reg_reg(dst, tmp1, tmp2);
9006 %}
9007 %}
9008
9009 // Immediate Or
9010 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9011 match(Set dst (OrI src1 src2));
9012 format %{ "ORI $dst, $src1, $src2" %}
9013 size(4);
9014 ins_encode %{
9015 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9016 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9017 %}
9018 ins_pipe(pipe_class_default);
9019 %}
9020
9021 // Register Or Long
9022 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9023 match(Set dst (OrL src1 src2));
9024 ins_cost(DEFAULT_COST);
9025
9026 size(4);
9027 format %{ "OR $dst, $src1, $src2 \t// long" %}
9028 ins_encode %{
9029 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9030 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9031 %}
9032 ins_pipe(pipe_class_default);
9033 %}
9034
9035 // OrL + ConvL2I.
9036 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9037 match(Set dst (ConvL2I (OrL src1 src2)));
9038 ins_cost(DEFAULT_COST);
9039
9040 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9041 size(4);
9042 ins_encode %{
9043 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9044 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9045 %}
9046 ins_pipe(pipe_class_default);
9047 %}
9048
9049 // Immediate Or long
9050 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9051 match(Set dst (OrL src1 con));
9052 ins_cost(DEFAULT_COST);
9053
9054 format %{ "ORI $dst, $src1, $con \t// long" %}
9055 size(4);
9056 ins_encode %{
9057 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9058 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9059 %}
9060 ins_pipe(pipe_class_default);
9061 %}
9062
9063 // Xor Instructions
9064
9065 // Register Xor
9066 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9067 match(Set dst (XorI src1 src2));
9068 format %{ "XOR $dst, $src1, $src2" %}
9069 size(4);
9070 ins_encode %{
9071 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9072 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9073 %}
9074 ins_pipe(pipe_class_default);
9075 %}
9076
9077 // Expand does not work with above instruct. (??)
9078 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9079 // no match-rule
9080 effect(DEF dst, USE src1, USE src2);
9081 format %{ "XOR $dst, $src1, $src2" %}
9082 size(4);
9083 ins_encode %{
9084 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9085 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9086 %}
9087 ins_pipe(pipe_class_default);
9088 %}
9089
9090 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9091 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9092 ins_cost(DEFAULT_COST*3);
9093
9094 expand %{
9095 // FIXME: we should do this in the ideal world.
9096 iRegIdst tmp1;
9097 iRegIdst tmp2;
9098 xorI_reg_reg(tmp1, src1, src2);
9099 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9100 xorI_reg_reg(dst, tmp1, tmp2);
9101 %}
9102 %}
9103
9104 // Immediate Xor
9105 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9106 match(Set dst (XorI src1 src2));
9107 format %{ "XORI $dst, $src1, $src2" %}
9108 size(4);
9109 ins_encode %{
9110 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9111 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9112 %}
9113 ins_pipe(pipe_class_default);
9114 %}
9115
9116 // Register Xor Long
9117 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9118 match(Set dst (XorL src1 src2));
9119 ins_cost(DEFAULT_COST);
9120
9121 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9122 size(4);
9123 ins_encode %{
9124 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9125 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9126 %}
9127 ins_pipe(pipe_class_default);
9128 %}
9129
9130 // XorL + ConvL2I.
9131 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9132 match(Set dst (ConvL2I (XorL src1 src2)));
9133 ins_cost(DEFAULT_COST);
9134
9135 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9136 size(4);
9137 ins_encode %{
9138 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9139 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9140 %}
9141 ins_pipe(pipe_class_default);
9142 %}
9143
9144 // Immediate Xor Long
9145 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9146 match(Set dst (XorL src1 src2));
9147 ins_cost(DEFAULT_COST);
9148
9149 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9150 size(4);
9151 ins_encode %{
9152 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9153 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9154 %}
9155 ins_pipe(pipe_class_default);
9156 %}
9157
9158 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9159 match(Set dst (XorI src1 src2));
9160 ins_cost(DEFAULT_COST);
9161
9162 format %{ "NOT $dst, $src1 ($src2)" %}
9163 size(4);
9164 ins_encode %{
9165 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9166 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9167 %}
9168 ins_pipe(pipe_class_default);
9169 %}
9170
9171 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9172 match(Set dst (XorL src1 src2));
9173 ins_cost(DEFAULT_COST);
9174
9175 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9176 size(4);
9177 ins_encode %{
9178 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9179 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9180 %}
9181 ins_pipe(pipe_class_default);
9182 %}
9183
9184 // And-complement
9185 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9186 match(Set dst (AndI (XorI src1 src2) src3));
9187 ins_cost(DEFAULT_COST);
9188
9189 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9190 size(4);
9191 ins_encode( enc_andc(dst, src3, src1) );
9192 ins_pipe(pipe_class_default);
9193 %}
9194
9195 // And-complement
9196 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9197 // no match-rule, false predicate
9198 effect(DEF dst, USE src1, USE src2);
9199 predicate(false);
9200
9201 format %{ "ANDC $dst, $src1, $src2" %}
9202 size(4);
9203 ins_encode %{
9204 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9205 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9206 %}
9207 ins_pipe(pipe_class_default);
9208 %}
9209
9210 //----------Moves between int/long and float/double----------------------------
9211 //
9212 // The following rules move values from int/long registers/stack-locations
9213 // to float/double registers/stack-locations and vice versa, without doing any
9214 // conversions. These rules are used to implement the bit-conversion methods
9215 // of java.lang.Float etc., e.g.
9216 // int floatToIntBits(float value)
9217 // float intBitsToFloat(int bits)
9218 //
9219 // Notes on the implementation on ppc64:
9220 // We only provide rules which move between a register and a stack-location,
9221 // because we always have to go through memory when moving between a float
9222 // register and an integer register.
9223
9224 //---------- Chain stack slots between similar types --------
9225
9226 // These are needed so that the rules below can match.
9227
9228 // Load integer from stack slot
9229 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9230 match(Set dst src);
9231 ins_cost(MEMORY_REF_COST);
9232
9233 format %{ "LWZ $dst, $src" %}
9234 size(4);
9235 ins_encode( enc_lwz(dst, src) );
9236 ins_pipe(pipe_class_memory);
9237 %}
9238
9239 // Store integer to stack slot
9240 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9241 match(Set dst src);
9242 ins_cost(MEMORY_REF_COST);
9243
9244 format %{ "STW $src, $dst \t// stk" %}
9245 size(4);
9246 ins_encode( enc_stw(src, dst) ); // rs=rt
9247 ins_pipe(pipe_class_memory);
9248 %}
9249
9250 // Load long from stack slot
9251 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9252 match(Set dst src);
9253 ins_cost(MEMORY_REF_COST);
9254
9255 format %{ "LD $dst, $src \t// long" %}
9256 size(4);
9257 ins_encode( enc_ld(dst, src) );
9258 ins_pipe(pipe_class_memory);
9259 %}
9260
9261 // Store long to stack slot
9262 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9263 match(Set dst src);
9264 ins_cost(MEMORY_REF_COST);
9265
9266 format %{ "STD $src, $dst \t// long" %}
9267 size(4);
9268 ins_encode( enc_std(src, dst) ); // rs=rt
9269 ins_pipe(pipe_class_memory);
9270 %}
9271
9272 //----------Moves between int and float
9273
9274 // Move float value from float stack-location to integer register.
9275 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9276 match(Set dst (MoveF2I src));
9277 ins_cost(MEMORY_REF_COST);
9278
9279 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9280 size(4);
9281 ins_encode( enc_lwz(dst, src) );
9282 ins_pipe(pipe_class_memory);
9283 %}
9284
9285 // Move float value from float register to integer stack-location.
9286 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9287 match(Set dst (MoveF2I src));
9288 ins_cost(MEMORY_REF_COST);
9289
9290 format %{ "STFS $src, $dst \t// MoveF2I" %}
9291 size(4);
9292 ins_encode( enc_stfs(src, dst) );
9293 ins_pipe(pipe_class_memory);
9294 %}
9295
9296 // Move integer value from integer stack-location to float register.
9297 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9298 match(Set dst (MoveI2F src));
9299 ins_cost(MEMORY_REF_COST);
9300
9301 format %{ "LFS $dst, $src \t// MoveI2F" %}
9302 size(4);
9303 ins_encode %{
9304 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9305 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9306 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9307 %}
9308 ins_pipe(pipe_class_memory);
9309 %}
9310
9311 // Move integer value from integer register to float stack-location.
9312 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9313 match(Set dst (MoveI2F src));
9314 ins_cost(MEMORY_REF_COST);
9315
9316 format %{ "STW $src, $dst \t// MoveI2F" %}
9317 size(4);
9318 ins_encode( enc_stw(src, dst) );
9319 ins_pipe(pipe_class_memory);
9320 %}
9321
9322 //----------Moves between long and float
9323
9324 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9325 // no match-rule, false predicate
9326 effect(DEF dst, USE src);
9327 predicate(false);
9328
9329 format %{ "storeD $src, $dst \t// STACK" %}
9330 size(4);
9331 ins_encode( enc_stfd(src, dst) );
9332 ins_pipe(pipe_class_default);
9333 %}
9334
9335 //----------Moves between long and double
9336
9337 // Move double value from double stack-location to long register.
9338 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9339 match(Set dst (MoveD2L src));
9340 ins_cost(MEMORY_REF_COST);
9341 size(4);
9342 format %{ "LD $dst, $src \t// MoveD2L" %}
9343 ins_encode( enc_ld(dst, src) );
9344 ins_pipe(pipe_class_memory);
9345 %}
9346
9347 // Move double value from double register to long stack-location.
9348 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9349 match(Set dst (MoveD2L src));
9350 effect(DEF dst, USE src);
9351 ins_cost(MEMORY_REF_COST);
9352
9353 format %{ "STFD $src, $dst \t// MoveD2L" %}
9354 size(4);
9355 ins_encode( enc_stfd(src, dst) );
9356 ins_pipe(pipe_class_memory);
9357 %}
9358
9359 // Move long value from long stack-location to double register.
9360 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9361 match(Set dst (MoveL2D src));
9362 ins_cost(MEMORY_REF_COST);
9363
9364 format %{ "LFD $dst, $src \t// MoveL2D" %}
9365 size(4);
9366 ins_encode( enc_lfd(dst, src) );
9367 ins_pipe(pipe_class_memory);
9368 %}
9369
9370 // Move long value from long register to double stack-location.
9371 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9372 match(Set dst (MoveL2D src));
9373 ins_cost(MEMORY_REF_COST);
9374
9375 format %{ "STD $src, $dst \t// MoveL2D" %}
9376 size(4);
9377 ins_encode( enc_std(src, dst) );
9378 ins_pipe(pipe_class_memory);
9379 %}
9380
9381 //----------Register Move Instructions-----------------------------------------
9382
9383 // Replicate for Superword
9384
9385 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9386 predicate(false);
9387 effect(DEF dst, USE src);
9388
9389 format %{ "MR $dst, $src \t// replicate " %}
9390 // variable size, 0 or 4.
9391 ins_encode %{
9392 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9393 __ mr_if_needed($dst$$Register, $src$$Register);
9394 %}
9395 ins_pipe(pipe_class_default);
9396 %}
9397
9398 //----------Cast instructions (Java-level type cast)---------------------------
9399
9400 // Cast Long to Pointer for unsafe natives.
9401 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9402 match(Set dst (CastX2P src));
9403
9404 format %{ "MR $dst, $src \t// Long->Ptr" %}
9405 // variable size, 0 or 4.
9406 ins_encode %{
9407 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9408 __ mr_if_needed($dst$$Register, $src$$Register);
9409 %}
9410 ins_pipe(pipe_class_default);
9411 %}
9412
9413 // Cast Pointer to Long for unsafe natives.
9414 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9415 match(Set dst (CastP2X src));
9416
9417 format %{ "MR $dst, $src \t// Ptr->Long" %}
9418 // variable size, 0 or 4.
9419 ins_encode %{
9420 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9421 __ mr_if_needed($dst$$Register, $src$$Register);
9422 %}
9423 ins_pipe(pipe_class_default);
9424 %}
9425
9426 instruct castPP(iRegPdst dst) %{
9427 match(Set dst (CastPP dst));
9428 format %{ " -- \t// castPP of $dst" %}
9429 size(0);
9430 ins_encode( /*empty*/ );
9431 ins_pipe(pipe_class_default);
9432 %}
9433
9434 instruct castII(iRegIdst dst) %{
9435 match(Set dst (CastII dst));
9436 format %{ " -- \t// castII of $dst" %}
9437 size(0);
9438 ins_encode( /*empty*/ );
9439 ins_pipe(pipe_class_default);
9440 %}
9441
9442 instruct checkCastPP(iRegPdst dst) %{
9443 match(Set dst (CheckCastPP dst));
9444 format %{ " -- \t// checkcastPP of $dst" %}
9445 size(0);
9446 ins_encode( /*empty*/ );
9447 ins_pipe(pipe_class_default);
9448 %}
9449
9450 //----------Convert instructions-----------------------------------------------
9451
9452 // Convert to boolean.
9453
9454 // int_to_bool(src) : { 1 if src != 0
9455 // { 0 else
9456 //
9457 // strategy:
9458 // 1) Count leading zeros of 32 bit-value src,
9459 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9460 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9461 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9462
9463 // convI2Bool
9464 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9465 match(Set dst (Conv2B src));
9466 predicate(UseCountLeadingZerosInstructionsPPC64);
9467 ins_cost(DEFAULT_COST);
9468
9469 expand %{
9470 immI shiftAmount %{ 0x5 %}
9471 uimmI16 mask %{ 0x1 %}
9472 iRegIdst tmp1;
9473 iRegIdst tmp2;
9474 countLeadingZerosI(tmp1, src);
9475 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9476 xorI_reg_uimm16(dst, tmp2, mask);
9477 %}
9478 %}
9479
9480 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9481 match(Set dst (Conv2B src));
9482 effect(TEMP crx);
9483 predicate(!UseCountLeadingZerosInstructionsPPC64);
9484 ins_cost(DEFAULT_COST);
9485
9486 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9487 "LI $dst, #0\n\t"
9488 "BEQ $crx, done\n\t"
9489 "LI $dst, #1\n"
9490 "done:" %}
9491 size(16);
9492 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9493 ins_pipe(pipe_class_compare);
9494 %}
9495
9496 // ConvI2B + XorI
9497 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9498 match(Set dst (XorI (Conv2B src) mask));
9499 predicate(UseCountLeadingZerosInstructionsPPC64);
9500 ins_cost(DEFAULT_COST);
9501
9502 expand %{
9503 immI shiftAmount %{ 0x5 %}
9504 iRegIdst tmp1;
9505 countLeadingZerosI(tmp1, src);
9506 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9507 %}
9508 %}
9509
9510 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9511 match(Set dst (XorI (Conv2B src) mask));
9512 effect(TEMP crx);
9513 predicate(!UseCountLeadingZerosInstructionsPPC64);
9514 ins_cost(DEFAULT_COST);
9515
9516 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9517 "LI $dst, #1\n\t"
9518 "BEQ $crx, done\n\t"
9519 "LI $dst, #0\n"
9520 "done:" %}
9521 size(16);
9522 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9523 ins_pipe(pipe_class_compare);
9524 %}
9525
9526 // AndI 0b0..010..0 + ConvI2B
9527 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9528 match(Set dst (Conv2B (AndI src mask)));
9529 predicate(UseRotateAndMaskInstructionsPPC64);
9530 ins_cost(DEFAULT_COST);
9531
9532 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9533 size(4);
9534 ins_encode %{
9535 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9536 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9537 %}
9538 ins_pipe(pipe_class_default);
9539 %}
9540
9541 // Convert pointer to boolean.
9542 //
9543 // ptr_to_bool(src) : { 1 if src != 0
9544 // { 0 else
9545 //
9546 // strategy:
9547 // 1) Count leading zeros of 64 bit-value src,
9548 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9549 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9550 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9551
9552 // ConvP2B
9553 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9554 match(Set dst (Conv2B src));
9555 predicate(UseCountLeadingZerosInstructionsPPC64);
9556 ins_cost(DEFAULT_COST);
9557
9558 expand %{
9559 immI shiftAmount %{ 0x6 %}
9560 uimmI16 mask %{ 0x1 %}
9561 iRegIdst tmp1;
9562 iRegIdst tmp2;
9563 countLeadingZerosP(tmp1, src);
9564 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9565 xorI_reg_uimm16(dst, tmp2, mask);
9566 %}
9567 %}
9568
9569 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9570 match(Set dst (Conv2B src));
9571 effect(TEMP crx);
9572 predicate(!UseCountLeadingZerosInstructionsPPC64);
9573 ins_cost(DEFAULT_COST);
9574
9575 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9576 "LI $dst, #0\n\t"
9577 "BEQ $crx, done\n\t"
9578 "LI $dst, #1\n"
9579 "done:" %}
9580 size(16);
9581 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9582 ins_pipe(pipe_class_compare);
9583 %}
9584
9585 // ConvP2B + XorI
9586 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9587 match(Set dst (XorI (Conv2B src) mask));
9588 predicate(UseCountLeadingZerosInstructionsPPC64);
9589 ins_cost(DEFAULT_COST);
9590
9591 expand %{
9592 immI shiftAmount %{ 0x6 %}
9593 iRegIdst tmp1;
9594 countLeadingZerosP(tmp1, src);
9595 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9596 %}
9597 %}
9598
9599 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9600 match(Set dst (XorI (Conv2B src) mask));
9601 effect(TEMP crx);
9602 predicate(!UseCountLeadingZerosInstructionsPPC64);
9603 ins_cost(DEFAULT_COST);
9604
9605 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9606 "LI $dst, #1\n\t"
9607 "BEQ $crx, done\n\t"
9608 "LI $dst, #0\n"
9609 "done:" %}
9610 size(16);
9611 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9612 ins_pipe(pipe_class_compare);
9613 %}
9614
9615 // if src1 < src2, return -1 else return 0
9616 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9617 match(Set dst (CmpLTMask src1 src2));
9618 ins_cost(DEFAULT_COST*4);
9619
9620 expand %{
9621 iRegIdst src1s;
9622 iRegIdst src2s;
9623 iRegIdst diff;
9624 sxtI_reg(src1s, src1); // ensure proper sign extention
9625 sxtI_reg(src2s, src2); // ensure proper sign extention
9626 subI_reg_reg(diff, src1s, src2s);
9627 // Need to consider >=33 bit result, therefore we need signmaskL.
9628 signmask64I_regI(dst, diff);
9629 %}
9630 %}
9631
9632 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9633 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9634 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9635 size(4);
9636 ins_encode %{
9637 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9638 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9639 %}
9640 ins_pipe(pipe_class_default);
9641 %}
9642
9643 //----------Arithmetic Conversion Instructions---------------------------------
9644
9645 // Convert to Byte -- nop
9646 // Convert to Short -- nop
9647
9648 // Convert to Int
9649
9650 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9651 match(Set dst (RShiftI (LShiftI src amount) amount));
9652 format %{ "EXTSB $dst, $src \t// byte->int" %}
9653 size(4);
9654 ins_encode %{
9655 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9656 __ extsb($dst$$Register, $src$$Register);
9657 %}
9658 ins_pipe(pipe_class_default);
9659 %}
9660
9661 // LShiftI 16 + RShiftI 16 converts short to int.
9662 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9663 match(Set dst (RShiftI (LShiftI src amount) amount));
9664 format %{ "EXTSH $dst, $src \t// short->int" %}
9665 size(4);
9666 ins_encode %{
9667 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9668 __ extsh($dst$$Register, $src$$Register);
9669 %}
9670 ins_pipe(pipe_class_default);
9671 %}
9672
9673 // ConvL2I + ConvI2L: Sign extend int in long register.
9674 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9675 match(Set dst (ConvI2L (ConvL2I src)));
9676
9677 format %{ "EXTSW $dst, $src \t// long->long" %}
9678 size(4);
9679 ins_encode %{
9680 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9681 __ extsw($dst$$Register, $src$$Register);
9682 %}
9683 ins_pipe(pipe_class_default);
9684 %}
9685
9686 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9687 match(Set dst (ConvL2I src));
9688 format %{ "MR $dst, $src \t// long->int" %}
9689 // variable size, 0 or 4
9690 ins_encode %{
9691 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9692 __ mr_if_needed($dst$$Register, $src$$Register);
9693 %}
9694 ins_pipe(pipe_class_default);
9695 %}
9696
9697 instruct convD2IRaw_regD(regD dst, regD src) %{
9698 // no match-rule, false predicate
9699 effect(DEF dst, USE src);
9700 predicate(false);
9701
9702 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9703 size(4);
9704 ins_encode %{
9705 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9706 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9707 %}
9708 ins_pipe(pipe_class_default);
9709 %}
9710
9711 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9712 // no match-rule, false predicate
9713 effect(DEF dst, USE crx, USE src);
9714 predicate(false);
9715
9716 ins_variable_size_depending_on_alignment(true);
9717
9718 format %{ "cmovI $crx, $dst, $src" %}
9719 // Worst case is branch + move + stop, no stop without scheduler.
9720 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9721 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9722 ins_pipe(pipe_class_default);
9723 %}
9724
9725 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9726 // no match-rule, false predicate
9727 effect(DEF dst, USE crx, USE mem);
9728 predicate(false);
9729
9730 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9731 postalloc_expand %{
9732 //
9733 // replaces
9734 //
9735 // region dst crx mem
9736 // \ | | /
9737 // dst=cmovI_bso_stackSlotL_conLvalue0
9738 //
9739 // with
9740 //
9741 // region dst
9742 // \ /
9743 // dst=loadConI16(0)
9744 // |
9745 // ^ region dst crx mem
9746 // | \ | | /
9747 // dst=cmovI_bso_stackSlotL
9748 //
9749
9750 // Create new nodes.
9751 MachNode *m1 = new (C) loadConI16Node();
9752 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9753
9754 // inputs for new nodes
9755 m1->add_req(n_region);
9756 m2->add_req(n_region, n_crx, n_mem);
9757
9758 // precedences for new nodes
9759 m2->add_prec(m1);
9760
9761 // operands for new nodes
9762 m1->_opnds[0] = op_dst;
9763 m1->_opnds[1] = new (C) immI16Oper(0);
9764
9765 m2->_opnds[0] = op_dst;
9766 m2->_opnds[1] = op_crx;
9767 m2->_opnds[2] = op_mem;
9768
9769 // registers for new nodes
9770 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9771 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9772
9773 // Insert new nodes.
9774 nodes->push(m1);
9775 nodes->push(m2);
9776 %}
9777 %}
9778
9779 // Double to Int conversion, NaN is mapped to 0.
9780 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9781 match(Set dst (ConvD2I src));
9782 ins_cost(DEFAULT_COST);
9783
9784 expand %{
9785 regD tmpD;
9786 stackSlotL tmpS;
9787 flagsReg crx;
9788 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9789 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9790 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9791 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9792 %}
9793 %}
9794
9795 instruct convF2IRaw_regF(regF dst, regF src) %{
9796 // no match-rule, false predicate
9797 effect(DEF dst, USE src);
9798 predicate(false);
9799
9800 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9801 size(4);
9802 ins_encode %{
9803 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9804 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9805 %}
9806 ins_pipe(pipe_class_default);
9807 %}
9808
9809 // Float to Int conversion, NaN is mapped to 0.
9810 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9811 match(Set dst (ConvF2I src));
9812 ins_cost(DEFAULT_COST);
9813
9814 expand %{
9815 regF tmpF;
9816 stackSlotL tmpS;
9817 flagsReg crx;
9818 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9819 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9820 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9821 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9822 %}
9823 %}
9824
9825 // Convert to Long
9826
9827 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9828 match(Set dst (ConvI2L src));
9829 format %{ "EXTSW $dst, $src \t// int->long" %}
9830 size(4);
9831 ins_encode %{
9832 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9833 __ extsw($dst$$Register, $src$$Register);
9834 %}
9835 ins_pipe(pipe_class_default);
9836 %}
9837
9838 // Zero-extend: convert unsigned int to long (convUI2L).
9839 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9840 match(Set dst (AndL (ConvI2L src) mask));
9841 ins_cost(DEFAULT_COST);
9842
9843 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9844 size(4);
9845 ins_encode %{
9846 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9847 __ clrldi($dst$$Register, $src$$Register, 32);
9848 %}
9849 ins_pipe(pipe_class_default);
9850 %}
9851
9852 // Zero-extend: convert unsigned int to long in long register.
9853 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9854 match(Set dst (AndL src mask));
9855 ins_cost(DEFAULT_COST);
9856
9857 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9858 size(4);
9859 ins_encode %{
9860 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9861 __ clrldi($dst$$Register, $src$$Register, 32);
9862 %}
9863 ins_pipe(pipe_class_default);
9864 %}
9865
9866 instruct convF2LRaw_regF(regF dst, regF src) %{
9867 // no match-rule, false predicate
9868 effect(DEF dst, USE src);
9869 predicate(false);
9870
9871 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9872 size(4);
9873 ins_encode %{
9874 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9875 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9876 %}
9877 ins_pipe(pipe_class_default);
9878 %}
9879
9880 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9881 // no match-rule, false predicate
9882 effect(DEF dst, USE crx, USE src);
9883 predicate(false);
9884
9885 ins_variable_size_depending_on_alignment(true);
9886
9887 format %{ "cmovL $crx, $dst, $src" %}
9888 // Worst case is branch + move + stop, no stop without scheduler.
9889 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9890 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9891 ins_pipe(pipe_class_default);
9892 %}
9893
9894 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9895 // no match-rule, false predicate
9896 effect(DEF dst, USE crx, USE mem);
9897 predicate(false);
9898
9899 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9900 postalloc_expand %{
9901 //
9902 // replaces
9903 //
9904 // region dst crx mem
9905 // \ | | /
9906 // dst=cmovL_bso_stackSlotL_conLvalue0
9907 //
9908 // with
9909 //
9910 // region dst
9911 // \ /
9912 // dst=loadConL16(0)
9913 // |
9914 // ^ region dst crx mem
9915 // | \ | | /
9916 // dst=cmovL_bso_stackSlotL
9917 //
9918
9919 // Create new nodes.
9920 MachNode *m1 = new (C) loadConL16Node();
9921 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9922
9923 // inputs for new nodes
9924 m1->add_req(n_region);
9925 m2->add_req(n_region, n_crx, n_mem);
9926 m2->add_prec(m1);
9927
9928 // operands for new nodes
9929 m1->_opnds[0] = op_dst;
9930 m1->_opnds[1] = new (C) immL16Oper(0);
9931 m2->_opnds[0] = op_dst;
9932 m2->_opnds[1] = op_crx;
9933 m2->_opnds[2] = op_mem;
9934
9935 // registers for new nodes
9936 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9937 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9938
9939 // Insert new nodes.
9940 nodes->push(m1);
9941 nodes->push(m2);
9942 %}
9943 %}
9944
9945 // Float to Long conversion, NaN is mapped to 0.
9946 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9947 match(Set dst (ConvF2L src));
9948 ins_cost(DEFAULT_COST);
9949
9950 expand %{
9951 regF tmpF;
9952 stackSlotL tmpS;
9953 flagsReg crx;
9954 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9955 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9956 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9957 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9958 %}
9959 %}
9960
9961 instruct convD2LRaw_regD(regD dst, regD src) %{
9962 // no match-rule, false predicate
9963 effect(DEF dst, USE src);
9964 predicate(false);
9965
9966 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9967 size(4);
9968 ins_encode %{
9969 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9970 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9971 %}
9972 ins_pipe(pipe_class_default);
9973 %}
9974
9975 // Double to Long conversion, NaN is mapped to 0.
9976 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
9977 match(Set dst (ConvD2L src));
9978 ins_cost(DEFAULT_COST);
9979
9980 expand %{
9981 regD tmpD;
9982 stackSlotL tmpS;
9983 flagsReg crx;
9984 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9985 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
9986 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9987 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9988 %}
9989 %}
9990
9991 // Convert to Float
9992
9993 // Placed here as needed in expand.
9994 instruct convL2DRaw_regD(regD dst, regD src) %{
9995 // no match-rule, false predicate
9996 effect(DEF dst, USE src);
9997 predicate(false);
9998
9999 format %{ "FCFID $dst, $src \t// convL2D" %}
10000 size(4);
10001 ins_encode %{
10002 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10003 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10004 %}
10005 ins_pipe(pipe_class_default);
10006 %}
10007
10008 // Placed here as needed in expand.
10009 instruct convD2F_reg(regF dst, regD src) %{
10010 match(Set dst (ConvD2F src));
10011 format %{ "FRSP $dst, $src \t// convD2F" %}
10012 size(4);
10013 ins_encode %{
10014 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10015 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10016 %}
10017 ins_pipe(pipe_class_default);
10018 %}
10019
10020 // Integer to Float conversion.
10021 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10022 match(Set dst (ConvI2F src));
10023 predicate(!VM_Version::has_fcfids());
10024 ins_cost(DEFAULT_COST);
10025
10026 expand %{
10027 iRegLdst tmpL;
10028 stackSlotL tmpS;
10029 regD tmpD;
10030 regD tmpD2;
10031 convI2L_reg(tmpL, src); // Sign-extension int to long.
10032 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10033 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10034 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10035 convD2F_reg(dst, tmpD2); // Convert double to float.
10036 %}
10037 %}
10038
10039 instruct convL2FRaw_regF(regF dst, regD src) %{
10040 // no match-rule, false predicate
10041 effect(DEF dst, USE src);
10042 predicate(false);
10043
10044 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10045 size(4);
10046 ins_encode %{
10047 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10048 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10049 %}
10050 ins_pipe(pipe_class_default);
10051 %}
10052
10053 // Integer to Float conversion. Special version for Power7.
10054 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10055 match(Set dst (ConvI2F src));
10056 predicate(VM_Version::has_fcfids());
10057 ins_cost(DEFAULT_COST);
10058
10059 expand %{
10060 iRegLdst tmpL;
10061 stackSlotL tmpS;
10062 regD tmpD;
10063 convI2L_reg(tmpL, src); // Sign-extension int to long.
10064 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10065 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10066 convL2FRaw_regF(dst, tmpD); // Convert to float.
10067 %}
10068 %}
10069
10070 // L2F to avoid runtime call.
10071 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10072 match(Set dst (ConvL2F src));
10073 predicate(VM_Version::has_fcfids());
10074 ins_cost(DEFAULT_COST);
10075
10076 expand %{
10077 stackSlotL tmpS;
10078 regD tmpD;
10079 regL_to_stkL(tmpS, src); // Store long to stack.
10080 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10081 convL2FRaw_regF(dst, tmpD); // Convert to float.
10082 %}
10083 %}
10084
10085 // Moved up as used in expand.
10086 //instruct convD2F_reg(regF dst, regD src) %{%}
10087
10088 // Convert to Double
10089
10090 // Integer to Double conversion.
10091 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10092 match(Set dst (ConvI2D src));
10093 ins_cost(DEFAULT_COST);
10094
10095 expand %{
10096 iRegLdst tmpL;
10097 stackSlotL tmpS;
10098 regD tmpD;
10099 convI2L_reg(tmpL, src); // Sign-extension int to long.
10100 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10101 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10102 convL2DRaw_regD(dst, tmpD); // Convert to double.
10103 %}
10104 %}
10105
10106 // Long to Double conversion
10107 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10108 match(Set dst (ConvL2D src));
10109 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10110
10111 expand %{
10112 regD tmpD;
10113 moveL2D_stack_reg(tmpD, src);
10114 convL2DRaw_regD(dst, tmpD);
10115 %}
10116 %}
10117
10118 instruct convF2D_reg(regD dst, regF src) %{
10119 match(Set dst (ConvF2D src));
10120 format %{ "FMR $dst, $src \t// float->double" %}
10121 // variable size, 0 or 4
10122 ins_encode %{
10123 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10124 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10125 %}
10126 ins_pipe(pipe_class_default);
10127 %}
10128
10129 //----------Control Flow Instructions------------------------------------------
10130 // Compare Instructions
10131
10132 // Compare Integers
10133 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10134 match(Set crx (CmpI src1 src2));
10135 size(4);
10136 format %{ "CMPW $crx, $src1, $src2" %}
10137 ins_encode %{
10138 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10139 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10140 %}
10141 ins_pipe(pipe_class_compare);
10142 %}
10143
10144 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10145 match(Set crx (CmpI src1 src2));
10146 format %{ "CMPWI $crx, $src1, $src2" %}
10147 size(4);
10148 ins_encode %{
10149 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10150 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10151 %}
10152 ins_pipe(pipe_class_compare);
10153 %}
10154
10155 // (src1 & src2) == 0?
10156 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10157 match(Set cr0 (CmpI (AndI src1 src2) zero));
10158 // r0 is killed
10159 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10160 size(4);
10161 ins_encode %{
10162 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10163 // FIXME: avoid andi_ ?
10164 __ andi_(R0, $src1$$Register, $src2$$constant);
10165 %}
10166 ins_pipe(pipe_class_compare);
10167 %}
10168
10169 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10170 match(Set crx (CmpL src1 src2));
10171 format %{ "CMPD $crx, $src1, $src2" %}
10172 size(4);
10173 ins_encode %{
10174 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10175 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10176 %}
10177 ins_pipe(pipe_class_compare);
10178 %}
10179
10180 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10181 match(Set crx (CmpL src1 src2));
10182 format %{ "CMPDI $crx, $src1, $src2" %}
10183 size(4);
10184 ins_encode %{
10185 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10186 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10187 %}
10188 ins_pipe(pipe_class_compare);
10189 %}
10190
10191 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10192 match(Set cr0 (CmpL (AndL src1 src2) zero));
10193 // r0 is killed
10194 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10195 size(4);
10196 ins_encode %{
10197 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10198 __ and_(R0, $src1$$Register, $src2$$Register);
10199 %}
10200 ins_pipe(pipe_class_compare);
10201 %}
10202
10203 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10204 match(Set cr0 (CmpL (AndL src1 src2) zero));
10205 // r0 is killed
10206 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10207 size(4);
10208 ins_encode %{
10209 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10210 // FIXME: avoid andi_ ?
10211 __ andi_(R0, $src1$$Register, $src2$$constant);
10212 %}
10213 ins_pipe(pipe_class_compare);
10214 %}
10215
10216 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10217 // no match-rule, false predicate
10218 effect(DEF dst, USE crx);
10219 predicate(false);
10220
10221 ins_variable_size_depending_on_alignment(true);
10222
10223 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10224 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10225 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10226 ins_encode %{
10227 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10228 Label done;
10229 // li(Rdst, 0); // equal -> 0
10230 __ beq($crx$$CondRegister, done);
10231 __ li($dst$$Register, 1); // greater -> +1
10232 __ bgt($crx$$CondRegister, done);
10233 __ li($dst$$Register, -1); // unordered or less -> -1
10234 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10235 __ bind(done);
10236 %}
10237 ins_pipe(pipe_class_compare);
10238 %}
10239
10240 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10241 // no match-rule, false predicate
10242 effect(DEF dst, USE crx);
10243 predicate(false);
10244
10245 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10246 postalloc_expand %{
10247 //
10248 // replaces
10249 //
10250 // region crx
10251 // \ |
10252 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10253 //
10254 // with
10255 //
10256 // region
10257 // \
10258 // dst=loadConI16(0)
10259 // |
10260 // ^ region crx
10261 // | \ |
10262 // dst=cmovI_conIvalueMinus1_conIvalue1
10263 //
10264
10265 // Create new nodes.
10266 MachNode *m1 = new (C) loadConI16Node();
10267 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10268
10269 // inputs for new nodes
10270 m1->add_req(n_region);
10271 m2->add_req(n_region, n_crx);
10272 m2->add_prec(m1);
10273
10274 // operands for new nodes
10275 m1->_opnds[0] = op_dst;
10276 m1->_opnds[1] = new (C) immI16Oper(0);
10277 m2->_opnds[0] = op_dst;
10278 m2->_opnds[1] = op_crx;
10279
10280 // registers for new nodes
10281 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10282 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10283
10284 // Insert new nodes.
10285 nodes->push(m1);
10286 nodes->push(m2);
10287 %}
10288 %}
10289
10290 // Manifest a CmpL3 result in an integer register. Very painful.
10291 // This is the test to avoid.
10292 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10293 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10294 match(Set dst (CmpL3 src1 src2));
10295 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10296
10297 expand %{
10298 flagsReg tmp1;
10299 cmpL_reg_reg(tmp1, src1, src2);
10300 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10301 %}
10302 %}
10303
10304 // Implicit range checks.
10305 // A range check in the ideal world has one of the following shapes:
10306 // - (If le (CmpU length index)), (IfTrue throw exception)
10307 // - (If lt (CmpU index length)), (IfFalse throw exception)
10308 //
10309 // Match range check 'If le (CmpU length index)'.
10310 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10311 match(If cmp (CmpU src_length index));
10312 effect(USE labl);
10313 predicate(TrapBasedRangeChecks &&
10314 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10315 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10316 (Matcher::branches_to_uncommon_trap(_leaf)));
10317
10318 ins_is_TrapBasedCheckNode(true);
10319
10320 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10321 size(4);
10322 ins_encode %{
10323 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10324 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10325 __ trap_range_check_le($src_length$$Register, $index$$constant);
10326 } else {
10327 // Both successors are uncommon traps, probability is 0.
10328 // Node got flipped during fixup flow.
10329 assert($cmp$$cmpcode == 0x9, "must be greater");
10330 __ trap_range_check_g($src_length$$Register, $index$$constant);
10331 }
10332 %}
10333 ins_pipe(pipe_class_trap);
10334 %}
10335
10336 // Match range check 'If lt (CmpU index length)'.
10337 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10338 match(If cmp (CmpU src_index src_length));
10339 effect(USE labl);
10340 predicate(TrapBasedRangeChecks &&
10341 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10342 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10343 (Matcher::branches_to_uncommon_trap(_leaf)));
10344
10345 ins_is_TrapBasedCheckNode(true);
10346
10347 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10348 size(4);
10349 ins_encode %{
10350 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10351 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10352 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10353 } else {
10354 // Both successors are uncommon traps, probability is 0.
10355 // Node got flipped during fixup flow.
10356 assert($cmp$$cmpcode == 0x8, "must be less");
10357 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10358 }
10359 %}
10360 ins_pipe(pipe_class_trap);
10361 %}
10362
10363 // Match range check 'If lt (CmpU index length)'.
10364 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10365 match(If cmp (CmpU src_index length));
10366 effect(USE labl);
10367 predicate(TrapBasedRangeChecks &&
10368 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10369 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10370 (Matcher::branches_to_uncommon_trap(_leaf)));
10371
10372 ins_is_TrapBasedCheckNode(true);
10373
10374 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10375 size(4);
10376 ins_encode %{
10377 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10378 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10379 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10380 } else {
10381 // Both successors are uncommon traps, probability is 0.
10382 // Node got flipped during fixup flow.
10383 assert($cmp$$cmpcode == 0x8, "must be less");
10384 __ trap_range_check_l($src_index$$Register, $length$$constant);
10385 }
10386 %}
10387 ins_pipe(pipe_class_trap);
10388 %}
10389
10390 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10391 match(Set crx (CmpU src1 src2));
10392 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10393 size(4);
10394 ins_encode %{
10395 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10396 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10397 %}
10398 ins_pipe(pipe_class_compare);
10399 %}
10400
10401 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10402 match(Set crx (CmpU src1 src2));
10403 size(4);
10404 format %{ "CMPLWI $crx, $src1, $src2" %}
10405 ins_encode %{
10406 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10407 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10408 %}
10409 ins_pipe(pipe_class_compare);
10410 %}
10411
10412 // Implicit zero checks (more implicit null checks).
10413 // No constant pool entries required.
10414 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10415 match(If cmp (CmpN value zero));
10416 effect(USE labl);
10417 predicate(TrapBasedNullChecks &&
10418 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10419 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10420 Matcher::branches_to_uncommon_trap(_leaf));
10421 ins_cost(1);
10422
10423 ins_is_TrapBasedCheckNode(true);
10424
10425 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10426 size(4);
10427 ins_encode %{
10428 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10429 if ($cmp$$cmpcode == 0xA) {
10430 __ trap_null_check($value$$Register);
10431 } else {
10432 // Both successors are uncommon traps, probability is 0.
10433 // Node got flipped during fixup flow.
10434 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10435 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10436 }
10437 %}
10438 ins_pipe(pipe_class_trap);
10439 %}
10440
10441 // Compare narrow oops.
10442 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10443 match(Set crx (CmpN src1 src2));
10444
10445 size(4);
10446 ins_cost(DEFAULT_COST);
10447 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10448 ins_encode %{
10449 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10450 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10451 %}
10452 ins_pipe(pipe_class_compare);
10453 %}
10454
10455 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10456 match(Set crx (CmpN src1 src2));
10457 // Make this more expensive than zeroCheckN_iReg_imm0.
10458 ins_cost(DEFAULT_COST);
10459
10460 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10461 size(4);
10462 ins_encode %{
10463 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10464 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10465 %}
10466 ins_pipe(pipe_class_compare);
10467 %}
10468
10469 // Implicit zero checks (more implicit null checks).
10470 // No constant pool entries required.
10471 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10472 match(If cmp (CmpP value zero));
10473 effect(USE labl);
10474 predicate(TrapBasedNullChecks &&
10475 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10476 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10477 Matcher::branches_to_uncommon_trap(_leaf));
10478
10479 ins_is_TrapBasedCheckNode(true);
10480
10481 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10482 size(4);
10483 ins_encode %{
10484 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10485 if ($cmp$$cmpcode == 0xA) {
10486 __ trap_null_check($value$$Register);
10487 } else {
10488 // Both successors are uncommon traps, probability is 0.
10489 // Node got flipped during fixup flow.
10490 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10491 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10492 }
10493 %}
10494 ins_pipe(pipe_class_trap);
10495 %}
10496
10497 // Compare Pointers
10498 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10499 match(Set crx (CmpP src1 src2));
10500 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10501 size(4);
10502 ins_encode %{
10503 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10504 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10505 %}
10506 ins_pipe(pipe_class_compare);
10507 %}
10508
10509 // Used in postalloc expand.
10510 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10511 // This match rule prevents reordering of node before a safepoint.
10512 // This only makes sense if this instructions is used exclusively
10513 // for the expansion of EncodeP!
10514 match(Set crx (CmpP src1 src2));
10515 predicate(false);
10516
10517 format %{ "CMPDI $crx, $src1, $src2" %}
10518 size(4);
10519 ins_encode %{
10520 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10521 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10522 %}
10523 ins_pipe(pipe_class_compare);
10524 %}
10525
10526 //----------Float Compares----------------------------------------------------
10527
10528 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10529 // no match-rule, false predicate
10530 effect(DEF crx, USE src1, USE src2);
10531 predicate(false);
10532
10533 format %{ "cmpFUrd $crx, $src1, $src2" %}
10534 size(4);
10535 ins_encode %{
10536 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10537 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10538 %}
10539 ins_pipe(pipe_class_default);
10540 %}
10541
10542 instruct cmov_bns_less(flagsReg crx) %{
10543 // no match-rule, false predicate
10544 effect(DEF crx);
10545 predicate(false);
10546
10547 ins_variable_size_depending_on_alignment(true);
10548
10549 format %{ "cmov $crx" %}
10550 // Worst case is branch + move + stop, no stop without scheduler.
10551 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10552 ins_encode %{
10553 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10554 Label done;
10555 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10556 __ li(R0, 0);
10557 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10558 // TODO PPC port __ endgroup_if_needed(_size == 16);
10559 __ bind(done);
10560 %}
10561 ins_pipe(pipe_class_default);
10562 %}
10563
10564 // Compare floating, generate condition code.
10565 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10566 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10567 //
10568 // The following code sequence occurs a lot in mpegaudio:
10569 //
10570 // block BXX:
10571 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10572 // cmpFUrd CCR6, F11, F9
10573 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10574 // cmov CCR6
10575 // 8: instruct branchConSched:
10576 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10577 match(Set crx (CmpF src1 src2));
10578 ins_cost(DEFAULT_COST+BRANCH_COST);
10579
10580 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10581 postalloc_expand %{
10582 //
10583 // replaces
10584 //
10585 // region src1 src2
10586 // \ | |
10587 // crx=cmpF_reg_reg
10588 //
10589 // with
10590 //
10591 // region src1 src2
10592 // \ | |
10593 // crx=cmpFUnordered_reg_reg
10594 // |
10595 // ^ region
10596 // | \
10597 // crx=cmov_bns_less
10598 //
10599
10600 // Create new nodes.
10601 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10602 MachNode *m2 = new (C) cmov_bns_lessNode();
10603
10604 // inputs for new nodes
10605 m1->add_req(n_region, n_src1, n_src2);
10606 m2->add_req(n_region);
10607 m2->add_prec(m1);
10608
10609 // operands for new nodes
10610 m1->_opnds[0] = op_crx;
10611 m1->_opnds[1] = op_src1;
10612 m1->_opnds[2] = op_src2;
10613 m2->_opnds[0] = op_crx;
10614
10615 // registers for new nodes
10616 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10617 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10618
10619 // Insert new nodes.
10620 nodes->push(m1);
10621 nodes->push(m2);
10622 %}
10623 %}
10624
10625 // Compare float, generate -1,0,1
10626 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10627 match(Set dst (CmpF3 src1 src2));
10628 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10629
10630 expand %{
10631 flagsReg tmp1;
10632 cmpFUnordered_reg_reg(tmp1, src1, src2);
10633 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10634 %}
10635 %}
10636
10637 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10638 // no match-rule, false predicate
10639 effect(DEF crx, USE src1, USE src2);
10640 predicate(false);
10641
10642 format %{ "cmpFUrd $crx, $src1, $src2" %}
10643 size(4);
10644 ins_encode %{
10645 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10646 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10647 %}
10648 ins_pipe(pipe_class_default);
10649 %}
10650
10651 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10652 match(Set crx (CmpD src1 src2));
10653 ins_cost(DEFAULT_COST+BRANCH_COST);
10654
10655 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10656 postalloc_expand %{
10657 //
10658 // replaces
10659 //
10660 // region src1 src2
10661 // \ | |
10662 // crx=cmpD_reg_reg
10663 //
10664 // with
10665 //
10666 // region src1 src2
10667 // \ | |
10668 // crx=cmpDUnordered_reg_reg
10669 // |
10670 // ^ region
10671 // | \
10672 // crx=cmov_bns_less
10673 //
10674
10675 // create new nodes
10676 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10677 MachNode *m2 = new (C) cmov_bns_lessNode();
10678
10679 // inputs for new nodes
10680 m1->add_req(n_region, n_src1, n_src2);
10681 m2->add_req(n_region);
10682 m2->add_prec(m1);
10683
10684 // operands for new nodes
10685 m1->_opnds[0] = op_crx;
10686 m1->_opnds[1] = op_src1;
10687 m1->_opnds[2] = op_src2;
10688 m2->_opnds[0] = op_crx;
10689
10690 // registers for new nodes
10691 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10692 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10693
10694 // Insert new nodes.
10695 nodes->push(m1);
10696 nodes->push(m2);
10697 %}
10698 %}
10699
10700 // Compare double, generate -1,0,1
10701 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10702 match(Set dst (CmpD3 src1 src2));
10703 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10704
10705 expand %{
10706 flagsReg tmp1;
10707 cmpDUnordered_reg_reg(tmp1, src1, src2);
10708 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10709 %}
10710 %}
10711
10712 //----------Branches---------------------------------------------------------
10713 // Jump
10714
10715 // Direct Branch.
10716 instruct branch(label labl) %{
10717 match(Goto);
10718 effect(USE labl);
10719 ins_cost(BRANCH_COST);
10720
10721 format %{ "B $labl" %}
10722 size(4);
10723 ins_encode %{
10724 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10725 Label d; // dummy
10726 __ bind(d);
10727 Label* p = $labl$$label;
10728 // `p' is `NULL' when this encoding class is used only to
10729 // determine the size of the encoded instruction.
10730 Label& l = (NULL == p)? d : *(p);
10731 __ b(l);
10732 %}
10733 ins_pipe(pipe_class_default);
10734 %}
10735
10736 // Conditional Near Branch
10737 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10738 // Same match rule as `branchConFar'.
10739 match(If cmp crx);
10740 effect(USE lbl);
10741 ins_cost(BRANCH_COST);
10742
10743 // If set to 1 this indicates that the current instruction is a
10744 // short variant of a long branch. This avoids using this
10745 // instruction in first-pass matching. It will then only be used in
10746 // the `Shorten_branches' pass.
10747 ins_short_branch(1);
10748
10749 format %{ "B$cmp $crx, $lbl" %}
10750 size(4);
10751 ins_encode( enc_bc(crx, cmp, lbl) );
10752 ins_pipe(pipe_class_default);
10753 %}
10754
10755 // This is for cases when the ppc64 `bc' instruction does not
10756 // reach far enough. So we emit a far branch here, which is more
10757 // expensive.
10758 //
10759 // Conditional Far Branch
10760 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10761 // Same match rule as `branchCon'.
10762 match(If cmp crx);
10763 effect(USE crx, USE lbl);
10764 predicate(!false /* TODO: PPC port HB_Schedule*/);
10765 // Higher cost than `branchCon'.
10766 ins_cost(5*BRANCH_COST);
10767
10768 // This is not a short variant of a branch, but the long variant.
10769 ins_short_branch(0);
10770
10771 format %{ "B_FAR$cmp $crx, $lbl" %}
10772 size(8);
10773 ins_encode( enc_bc_far(crx, cmp, lbl) );
10774 ins_pipe(pipe_class_default);
10775 %}
10776
10777 // Conditional Branch used with Power6 scheduler (can be far or short).
10778 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10779 // Same match rule as `branchCon'.
10780 match(If cmp crx);
10781 effect(USE crx, USE lbl);
10782 predicate(false /* TODO: PPC port HB_Schedule*/);
10783 // Higher cost than `branchCon'.
10784 ins_cost(5*BRANCH_COST);
10785
10786 // Actually size doesn't depend on alignment but on shortening.
10787 ins_variable_size_depending_on_alignment(true);
10788 // long variant.
10789 ins_short_branch(0);
10790
10791 format %{ "B_FAR$cmp $crx, $lbl" %}
10792 size(8); // worst case
10793 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10794 ins_pipe(pipe_class_default);
10795 %}
10796
10797 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10798 match(CountedLoopEnd cmp crx);
10799 effect(USE labl);
10800 ins_cost(BRANCH_COST);
10801
10802 // short variant.
10803 ins_short_branch(1);
10804
10805 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10806 size(4);
10807 ins_encode( enc_bc(crx, cmp, labl) );
10808 ins_pipe(pipe_class_default);
10809 %}
10810
10811 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10812 match(CountedLoopEnd cmp crx);
10813 effect(USE labl);
10814 predicate(!false /* TODO: PPC port HB_Schedule */);
10815 ins_cost(BRANCH_COST);
10816
10817 // Long variant.
10818 ins_short_branch(0);
10819
10820 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10821 size(8);
10822 ins_encode( enc_bc_far(crx, cmp, labl) );
10823 ins_pipe(pipe_class_default);
10824 %}
10825
10826 // Conditional Branch used with Power6 scheduler (can be far or short).
10827 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10828 match(CountedLoopEnd cmp crx);
10829 effect(USE labl);
10830 predicate(false /* TODO: PPC port HB_Schedule */);
10831 // Higher cost than `branchCon'.
10832 ins_cost(5*BRANCH_COST);
10833
10834 // Actually size doesn't depend on alignment but on shortening.
10835 ins_variable_size_depending_on_alignment(true);
10836 // Long variant.
10837 ins_short_branch(0);
10838
10839 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10840 size(8); // worst case
10841 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10842 ins_pipe(pipe_class_default);
10843 %}
10844
10845 // ============================================================================
10846 // Java runtime operations, intrinsics and other complex operations.
10847
10848 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10849 // array for an instance of the superklass. Set a hidden internal cache on a
10850 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10851 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10852 //
10853 // GL TODO: Improve this.
10854 // - result should not be a TEMP
10855 // - Add match rule as on sparc avoiding additional Cmp.
10856 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10857 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10858 match(Set result (PartialSubtypeCheck subklass superklass));
10859 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10860 ins_cost(DEFAULT_COST*10);
10861
10862 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10863 ins_encode %{
10864 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10865 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10866 $tmp_klass$$Register, NULL, $result$$Register);
10867 %}
10868 ins_pipe(pipe_class_default);
10869 %}
10870
10871 // inlined locking and unlocking
10872
10873 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10874 match(Set crx (FastLock oop box));
10875 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10876 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10877
10878 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10879 ins_encode %{
10880 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10881 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10882 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10883 // If locking was successfull, crx should indicate 'EQ'.
10884 // The compiler generates a branch to the runtime call to
10885 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10886 %}
10887 ins_pipe(pipe_class_compare);
10888 %}
10889
10890 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10891 match(Set crx (FastUnlock oop box));
10892 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10893
10894 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10895 ins_encode %{
10896 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10897 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10898 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10899 // If unlocking was successfull, crx should indicate 'EQ'.
10900 // The compiler generates a branch to the runtime call to
10901 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10902 %}
10903 ins_pipe(pipe_class_compare);
10904 %}
10905
10906 // Align address.
10907 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10908 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10909
10910 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10911 size(4);
10912 ins_encode %{
10913 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10914 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10915 %}
10916 ins_pipe(pipe_class_default);
10917 %}
10918
10919 // Array size computation.
10920 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10921 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10922
10923 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10924 size(4);
10925 ins_encode %{
10926 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10927 __ subf($dst$$Register, $start$$Register, $end$$Register);
10928 %}
10929 ins_pipe(pipe_class_default);
10930 %}
10931
10932 // Clear-array with dynamic array-size.
10933 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10934 match(Set dummy (ClearArray cnt base));
10935 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10936 ins_cost(MEMORY_REF_COST);
10937
10938 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10939
10940 format %{ "ClearArray $cnt, $base" %}
10941 ins_encode %{
10942 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10943 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10944 %}
10945 ins_pipe(pipe_class_default);
10946 %}
10947
10948 // String_IndexOf for needle of length 1.
10949 //
10950 // Match needle into immediate operands: no loadConP node needed. Saves one
10951 // register and two instructions over string_indexOf_imm1Node.
10952 //
10953 // Assumes register result differs from all input registers.
10954 //
10955 // Preserves registers haystack, haycnt
10956 // Kills registers tmp1, tmp2
10957 // Defines registers result
10958 //
10959 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10960 //
10961 // Unfortunately this does not match too often. In many situations the AddP is used
10962 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10963 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10964 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10965 iRegIdst tmp1, iRegIdst tmp2,
10966 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10967 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10968 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10969
10970 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10971
10972 ins_cost(150);
10973 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10974 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10975
10976 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
10977 ins_encode %{
10978 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10979 immPOper *needleOper = (immPOper *)$needleImm;
10980 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10981 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10982
10983 __ string_indexof_1($result$$Register,
10984 $haystack$$Register, $haycnt$$Register,
10985 R0, needle_values->char_at(0),
10986 $tmp1$$Register, $tmp2$$Register);
10987 %}
10988 ins_pipe(pipe_class_compare);
10989 %}
10990
10991 // String_IndexOf for needle of length 1.
10992 //
10993 // Special case requires less registers and emits less instructions.
10994 //
10995 // Assumes register result differs from all input registers.
10996 //
10997 // Preserves registers haystack, haycnt
10998 // Kills registers tmp1, tmp2, needle
10999 // Defines registers result
11000 //
11001 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11002 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11003 rscratch2RegP needle, immI_1 needlecntImm,
11004 iRegIdst tmp1, iRegIdst tmp2,
11005 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11006 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11007 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
11008 TEMP tmp1, TEMP tmp2);
11009 // Required for EA: check if it is still a type_array.
11010 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11011 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11012 ins_cost(180);
11013
11014 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11015
11016 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11017 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11018 ins_encode %{
11019 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11020 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11021 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11022 guarantee(needle_values, "sanity");
11023 if (needle_values != NULL) {
11024 __ string_indexof_1($result$$Register,
11025 $haystack$$Register, $haycnt$$Register,
11026 R0, needle_values->char_at(0),
11027 $tmp1$$Register, $tmp2$$Register);
11028 } else {
11029 __ string_indexof_1($result$$Register,
11030 $haystack$$Register, $haycnt$$Register,
11031 $needle$$Register, 0,
11032 $tmp1$$Register, $tmp2$$Register);
11033 }
11034 %}
11035 ins_pipe(pipe_class_compare);
11036 %}
11037
11038 // String_IndexOf.
11039 //
11040 // Length of needle as immediate. This saves instruction loading constant needle
11041 // length.
11042 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11043 // completely or do it in vector instruction. This should save registers for
11044 // needlecnt and needle.
11045 //
11046 // Assumes register result differs from all input registers.
11047 // Overwrites haycnt, needlecnt.
11048 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11049 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11050 iRegPsrc needle, uimmI15 needlecntImm,
11051 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11052 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11053 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11054 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11055 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11056 // Required for EA: check if it is still a type_array.
11057 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11058 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11059 ins_cost(250);
11060
11061 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11062
11063 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11064 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11065 ins_encode %{
11066 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11067 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11068 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11069
11070 __ string_indexof($result$$Register,
11071 $haystack$$Register, $haycnt$$Register,
11072 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11073 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11074 %}
11075 ins_pipe(pipe_class_compare);
11076 %}
11077
11078 // StrIndexOf node.
11079 //
11080 // Assumes register result differs from all input registers.
11081 // Overwrites haycnt, needlecnt.
11082 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11083 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11084 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11085 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11086 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11087 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11088 TEMP result,
11089 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11090 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11091 ins_cost(300);
11092
11093 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11094
11095 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11096 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11097 ins_encode %{
11098 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11099 __ string_indexof($result$$Register,
11100 $haystack$$Register, $haycnt$$Register,
11101 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11102 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11103 %}
11104 ins_pipe(pipe_class_compare);
11105 %}
11106
11107 // String equals with immediate.
11108 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11109 iRegPdst tmp1, iRegPdst tmp2,
11110 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11111 match(Set result (StrEquals (Binary str1 str2) cntImm));
11112 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11113 KILL cr0, KILL cr6, KILL ctr);
11114 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11115 ins_cost(250);
11116
11117 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11118
11119 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11120 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11121 ins_encode %{
11122 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11123 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11124 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11125 %}
11126 ins_pipe(pipe_class_compare);
11127 %}
11128
11129 // String equals.
11130 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11131 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11132 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11133 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11134 match(Set result (StrEquals (Binary str1 str2) cnt));
11135 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11136 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11137 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11138 ins_cost(300);
11139
11140 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11141
11142 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11143 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11144 ins_encode %{
11145 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11146 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11147 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11148 %}
11149 ins_pipe(pipe_class_compare);
11150 %}
11151
11152 // String compare.
11153 // Char[] pointers are passed in.
11154 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11155 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11156 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11157 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11158 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11159 ins_cost(300);
11160
11161 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11162
11163 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11164 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11165 ins_encode %{
11166 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11167 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11168 $result$$Register, $tmp$$Register);
11169 %}
11170 ins_pipe(pipe_class_compare);
11171 %}
11172
11173 //---------- Min/Max Instructions ---------------------------------------------
11174
11175 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11176 match(Set dst (MinI src1 src2));
11177 ins_cost(DEFAULT_COST*6);
11178
11179 expand %{
11180 iRegIdst src1s;
11181 iRegIdst src2s;
11182 iRegIdst diff;
11183 iRegIdst sm;
11184 iRegIdst doz; // difference or zero
11185 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11186 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11187 subI_reg_reg(diff, src2s, src1s);
11188 // Need to consider >=33 bit result, therefore we need signmaskL.
11189 signmask64I_regI(sm, diff);
11190 andI_reg_reg(doz, diff, sm); // <=0
11191 addI_reg_reg(dst, doz, src1s);
11192 %}
11193 %}
11194
11195 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11196 match(Set dst (MaxI src1 src2));
11197 ins_cost(DEFAULT_COST*6);
11198
11199 expand %{
11200 immI_minus1 m1 %{ -1 %}
11201 iRegIdst src1s;
11202 iRegIdst src2s;
11203 iRegIdst diff;
11204 iRegIdst sm;
11205 iRegIdst doz; // difference or zero
11206 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11207 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11208 subI_reg_reg(diff, src2s, src1s);
11209 // Need to consider >=33 bit result, therefore we need signmaskL.
11210 signmask64I_regI(sm, diff);
11211 andcI_reg_reg(doz, sm, m1, diff); // >=0
11212 addI_reg_reg(dst, doz, src1s);
11213 %}
11214 %}
11215
11216 //---------- Population Count Instructions ------------------------------------
11217
11218 // Popcnt for Power7.
11219 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11220 match(Set dst (PopCountI src));
11221 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11222 ins_cost(DEFAULT_COST);
11223
11224 format %{ "POPCNTW $dst, $src" %}
11225 size(4);
11226 ins_encode %{
11227 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11228 __ popcntw($dst$$Register, $src$$Register);
11229 %}
11230 ins_pipe(pipe_class_default);
11231 %}
11232
11233 // Popcnt for Power7.
11234 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11235 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11236 match(Set dst (PopCountL src));
11237 ins_cost(DEFAULT_COST);
11238
11239 format %{ "POPCNTD $dst, $src" %}
11240 size(4);
11241 ins_encode %{
11242 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11243 __ popcntd($dst$$Register, $src$$Register);
11244 %}
11245 ins_pipe(pipe_class_default);
11246 %}
11247
11248 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11249 match(Set dst (CountLeadingZerosI src));
11250 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11251 ins_cost(DEFAULT_COST);
11252
11253 format %{ "CNTLZW $dst, $src" %}
11254 size(4);
11255 ins_encode %{
11256 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11257 __ cntlzw($dst$$Register, $src$$Register);
11258 %}
11259 ins_pipe(pipe_class_default);
11260 %}
11261
11262 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11263 match(Set dst (CountLeadingZerosL src));
11264 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11265 ins_cost(DEFAULT_COST);
11266
11267 format %{ "CNTLZD $dst, $src" %}
11268 size(4);
11269 ins_encode %{
11270 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11271 __ cntlzd($dst$$Register, $src$$Register);
11272 %}
11273 ins_pipe(pipe_class_default);
11274 %}
11275
11276 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11277 // no match-rule, false predicate
11278 effect(DEF dst, USE src);
11279 predicate(false);
11280
11281 format %{ "CNTLZD $dst, $src" %}
11282 size(4);
11283 ins_encode %{
11284 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11285 __ cntlzd($dst$$Register, $src$$Register);
11286 %}
11287 ins_pipe(pipe_class_default);
11288 %}
11289
11290 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11291 match(Set dst (CountTrailingZerosI src));
11292 predicate(UseCountLeadingZerosInstructionsPPC64);
11293 ins_cost(DEFAULT_COST);
11294
11295 expand %{
11296 immI16 imm1 %{ (int)-1 %}
11297 immI16 imm2 %{ (int)32 %}
11298 immI_minus1 m1 %{ -1 %}
11299 iRegIdst tmpI1;
11300 iRegIdst tmpI2;
11301 iRegIdst tmpI3;
11302 addI_reg_imm16(tmpI1, src, imm1);
11303 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11304 countLeadingZerosI(tmpI3, tmpI2);
11305 subI_imm16_reg(dst, imm2, tmpI3);
11306 %}
11307 %}
11308
11309 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11310 match(Set dst (CountTrailingZerosL src));
11311 predicate(UseCountLeadingZerosInstructionsPPC64);
11312 ins_cost(DEFAULT_COST);
11313
11314 expand %{
11315 immL16 imm1 %{ (long)-1 %}
11316 immI16 imm2 %{ (int)64 %}
11317 iRegLdst tmpL1;
11318 iRegLdst tmpL2;
11319 iRegIdst tmpL3;
11320 addL_reg_imm16(tmpL1, src, imm1);
11321 andcL_reg_reg(tmpL2, tmpL1, src);
11322 countLeadingZerosL(tmpL3, tmpL2);
11323 subI_imm16_reg(dst, imm2, tmpL3);
11324 %}
11325 %}
11326
11327 // Expand nodes for byte_reverse_int.
11328 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11329 effect(DEF dst, USE src, USE pos, USE shift);
11330 predicate(false);
11331
11332 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11333 size(4);
11334 ins_encode %{
11335 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11336 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11337 %}
11338 ins_pipe(pipe_class_default);
11339 %}
11340
11341 // As insrwi_a, but with USE_DEF.
11342 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11343 effect(USE_DEF dst, USE src, USE pos, USE shift);
11344 predicate(false);
11345
11346 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11347 size(4);
11348 ins_encode %{
11349 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11350 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11351 %}
11352 ins_pipe(pipe_class_default);
11353 %}
11354
11355 // Just slightly faster than java implementation.
11356 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11357 match(Set dst (ReverseBytesI src));
11358 predicate(UseCountLeadingZerosInstructionsPPC64);
11359 ins_cost(DEFAULT_COST);
11360
11361 expand %{
11362 immI16 imm24 %{ (int) 24 %}
11363 immI16 imm16 %{ (int) 16 %}
11364 immI16 imm8 %{ (int) 8 %}
11365 immI16 imm4 %{ (int) 4 %}
11366 immI16 imm0 %{ (int) 0 %}
11367 iRegLdst tmpI1;
11368 iRegLdst tmpI2;
11369 iRegLdst tmpI3;
11370
11371 urShiftI_reg_imm(tmpI1, src, imm24);
11372 insrwi_a(dst, tmpI1, imm24, imm8);
11373 urShiftI_reg_imm(tmpI2, src, imm16);
11374 insrwi(dst, tmpI2, imm8, imm16);
11375 urShiftI_reg_imm(tmpI3, src, imm8);
11376 insrwi(dst, tmpI3, imm8, imm8);
11377 insrwi(dst, src, imm0, imm8);
11378 %}
11379 %}
11380
11381 //---------- Replicate Vector Instructions ------------------------------------
11382
11383 // Insrdi does replicate if src == dst.
11384 instruct repl32(iRegLdst dst) %{
11385 predicate(false);
11386 effect(USE_DEF dst);
11387
11388 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11389 size(4);
11390 ins_encode %{
11391 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11392 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11393 %}
11394 ins_pipe(pipe_class_default);
11395 %}
11396
11397 // Insrdi does replicate if src == dst.
11398 instruct repl48(iRegLdst dst) %{
11399 predicate(false);
11400 effect(USE_DEF dst);
11401
11402 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11403 size(4);
11404 ins_encode %{
11405 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11406 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11407 %}
11408 ins_pipe(pipe_class_default);
11409 %}
11410
11411 // Insrdi does replicate if src == dst.
11412 instruct repl56(iRegLdst dst) %{
11413 predicate(false);
11414 effect(USE_DEF dst);
11415
11416 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11417 size(4);
11418 ins_encode %{
11419 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11420 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11421 %}
11422 ins_pipe(pipe_class_default);
11423 %}
11424
11425 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11426 match(Set dst (ReplicateB src));
11427 predicate(n->as_Vector()->length() == 8);
11428 expand %{
11429 moveReg(dst, src);
11430 repl56(dst);
11431 repl48(dst);
11432 repl32(dst);
11433 %}
11434 %}
11435
11436 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11437 match(Set dst (ReplicateB zero));
11438 predicate(n->as_Vector()->length() == 8);
11439 format %{ "LI $dst, #0 \t// replicate8B" %}
11440 size(4);
11441 ins_encode %{
11442 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11443 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11444 %}
11445 ins_pipe(pipe_class_default);
11446 %}
11447
11448 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11449 match(Set dst (ReplicateB src));
11450 predicate(n->as_Vector()->length() == 8);
11451 format %{ "LI $dst, #-1 \t// replicate8B" %}
11452 size(4);
11453 ins_encode %{
11454 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11455 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11456 %}
11457 ins_pipe(pipe_class_default);
11458 %}
11459
11460 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11461 match(Set dst (ReplicateS src));
11462 predicate(n->as_Vector()->length() == 4);
11463 expand %{
11464 moveReg(dst, src);
11465 repl48(dst);
11466 repl32(dst);
11467 %}
11468 %}
11469
11470 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11471 match(Set dst (ReplicateS zero));
11472 predicate(n->as_Vector()->length() == 4);
11473 format %{ "LI $dst, #0 \t// replicate4C" %}
11474 size(4);
11475 ins_encode %{
11476 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11477 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11478 %}
11479 ins_pipe(pipe_class_default);
11480 %}
11481
11482 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11483 match(Set dst (ReplicateS src));
11484 predicate(n->as_Vector()->length() == 4);
11485 format %{ "LI $dst, -1 \t// replicate4C" %}
11486 size(4);
11487 ins_encode %{
11488 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11489 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11490 %}
11491 ins_pipe(pipe_class_default);
11492 %}
11493
11494 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11495 match(Set dst (ReplicateI src));
11496 predicate(n->as_Vector()->length() == 2);
11497 ins_cost(2 * DEFAULT_COST);
11498 expand %{
11499 moveReg(dst, src);
11500 repl32(dst);
11501 %}
11502 %}
11503
11504 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11505 match(Set dst (ReplicateI zero));
11506 predicate(n->as_Vector()->length() == 2);
11507 format %{ "LI $dst, #0 \t// replicate4C" %}
11508 size(4);
11509 ins_encode %{
11510 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11511 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11512 %}
11513 ins_pipe(pipe_class_default);
11514 %}
11515
11516 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11517 match(Set dst (ReplicateI src));
11518 predicate(n->as_Vector()->length() == 2);
11519 format %{ "LI $dst, -1 \t// replicate4C" %}
11520 size(4);
11521 ins_encode %{
11522 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11523 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11524 %}
11525 ins_pipe(pipe_class_default);
11526 %}
11527
11528 // Move float to int register via stack, replicate.
11529 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11530 match(Set dst (ReplicateF src));
11531 predicate(n->as_Vector()->length() == 2);
11532 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11533 expand %{
11534 stackSlotL tmpS;
11535 iRegIdst tmpI;
11536 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11537 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11538 moveReg(dst, tmpI); // Move int to long reg.
11539 repl32(dst); // Replicate bitpattern.
11540 %}
11541 %}
11542
11543 // Replicate scalar constant to packed float values in Double register
11544 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11545 match(Set dst (ReplicateF src));
11546 predicate(n->as_Vector()->length() == 2);
11547 ins_cost(5 * DEFAULT_COST);
11548
11549 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11550 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11551 %}
11552
11553 // Replicate scalar zero constant to packed float values in Double register
11554 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11555 match(Set dst (ReplicateF zero));
11556 predicate(n->as_Vector()->length() == 2);
11557
11558 format %{ "LI $dst, #0 \t// replicate2F" %}
11559 ins_encode %{
11560 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11561 __ li($dst$$Register, 0x0);
11562 %}
11563 ins_pipe(pipe_class_default);
11564 %}
11565
11566 // ============================================================================
11567 // Safepoint Instruction
11568
11569 instruct safePoint_poll(iRegPdst poll) %{
11570 match(SafePoint poll);
11571 predicate(LoadPollAddressFromThread);
11572
11573 // It caused problems to add the effect that r0 is killed, but this
11574 // effect no longer needs to be mentioned, since r0 is not contained
11575 // in a reg_class.
11576
11577 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11578 size(4);
11579 ins_encode( enc_poll(0x0, poll) );
11580 ins_pipe(pipe_class_default);
11581 %}
11582
11583 // Safepoint without per-thread support. Load address of page to poll
11584 // as constant.
11585 // Rscratch2RegP is R12.
11586 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11587 // a seperate node so that the oop map is at the right location.
11588 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11589 match(SafePoint poll);
11590 predicate(!LoadPollAddressFromThread);
11591
11592 // It caused problems to add the effect that r0 is killed, but this
11593 // effect no longer needs to be mentioned, since r0 is not contained
11594 // in a reg_class.
11595
11596 format %{ "LD R12, addr of polling page\n\t"
11597 "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11598 ins_encode( enc_poll(0x0, poll) );
11599 ins_pipe(pipe_class_default);
11600 %}
11601
11602 // ============================================================================
11603 // Call Instructions
11604
11605 // Call Java Static Instruction
11606
11607 // Schedulable version of call static node.
11608 instruct CallStaticJavaDirect(method meth) %{
11609 match(CallStaticJava);
11610 effect(USE meth);
11611 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11612 ins_cost(CALL_COST);
11613
11614 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11615
11616 format %{ "CALL,static $meth \t// ==> " %}
11617 size(4);
11618 ins_encode( enc_java_static_call(meth) );
11619 ins_pipe(pipe_class_call);
11620 %}
11621
11622 // Schedulable version of call static node.
11623 instruct CallStaticJavaDirectHandle(method meth) %{
11624 match(CallStaticJava);
11625 effect(USE meth);
11626 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11627 ins_cost(CALL_COST);
11628
11629 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11630
11631 format %{ "CALL,static $meth \t// ==> " %}
11632 ins_encode( enc_java_handle_call(meth) );
11633 ins_pipe(pipe_class_call);
11634 %}
11635
11636 // Call Java Dynamic Instruction
11637
11638 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11639 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11640 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11641 // The call destination must still be placed in the constant pool.
11642 instruct CallDynamicJavaDirectSched(method meth) %{
11643 match(CallDynamicJava); // To get all the data fields we need ...
11644 effect(USE meth);
11645 predicate(false); // ... but never match.
11646
11647 ins_field_load_ic_hi_node(loadConL_hiNode*);
11648 ins_field_load_ic_node(loadConLNode*);
11649 ins_num_consts(1 /* 1 patchable constant: call destination */);
11650
11651 format %{ "BL \t// dynamic $meth ==> " %}
11652 size(4);
11653 ins_encode( enc_java_dynamic_call_sched(meth) );
11654 ins_pipe(pipe_class_call);
11655 %}
11656
11657 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11658 // We use postalloc expanded calls if we use inline caches
11659 // and do not update method data.
11660 //
11661 // This instruction has two constants: inline cache (IC) and call destination.
11662 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11663 // one constant.
11664 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11665 match(CallDynamicJava);
11666 effect(USE meth);
11667 predicate(UseInlineCaches);
11668 ins_cost(CALL_COST);
11669
11670 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11671
11672 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11673 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11674 %}
11675
11676 // Compound version of call dynamic java
11677 // We use postalloc expanded calls if we use inline caches
11678 // and do not update method data.
11679 instruct CallDynamicJavaDirect(method meth) %{
11680 match(CallDynamicJava);
11681 effect(USE meth);
11682 predicate(!UseInlineCaches);
11683 ins_cost(CALL_COST);
11684
11685 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11686 ins_num_consts(4);
11687
11688 format %{ "CALL,dynamic $meth \t// ==> " %}
11689 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11690 ins_pipe(pipe_class_call);
11691 %}
11692
11693 // Call Runtime Instruction
11694
11695 instruct CallRuntimeDirect(method meth) %{
11696 match(CallRuntime);
11697 effect(USE meth);
11698 ins_cost(CALL_COST);
11699
11700 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11701 // env for callee, C-toc.
11702 ins_num_consts(3);
11703
11704 format %{ "CALL,runtime" %}
11705 ins_encode( enc_java_to_runtime_call(meth) );
11706 ins_pipe(pipe_class_call);
11707 %}
11708
11709 // Call Leaf
11710
11711 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11712 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11713 effect(DEF dst, USE src);
11714
11715 ins_num_consts(1);
11716
11717 format %{ "MTCTR $src" %}
11718 size(4);
11719 ins_encode( enc_leaf_call_mtctr(src) );
11720 ins_pipe(pipe_class_default);
11721 %}
11722
11723 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11724 instruct CallLeafDirect(method meth) %{
11725 match(CallLeaf); // To get the data all the data fields we need ...
11726 effect(USE meth);
11727 predicate(false); // but never match.
11728
11729 format %{ "BCTRL \t// leaf call $meth ==> " %}
11730 size(4);
11731 ins_encode %{
11732 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11733 __ bctrl();
11734 %}
11735 ins_pipe(pipe_class_call);
11736 %}
11737
11738 // postalloc expand of CallLeafDirect.
11739 // Load adress to call from TOC, then bl to it.
11740 instruct CallLeafDirect_Ex(method meth) %{
11741 match(CallLeaf);
11742 effect(USE meth);
11743 ins_cost(CALL_COST);
11744
11745 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11746 // env for callee, C-toc.
11747 ins_num_consts(3);
11748
11749 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11750 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11751 %}
11752
11753 // Call runtime without safepoint - same as CallLeaf.
11754 // postalloc expand of CallLeafNoFPDirect.
11755 // Load adress to call from TOC, then bl to it.
11756 instruct CallLeafNoFPDirect_Ex(method meth) %{
11757 match(CallLeafNoFP);
11758 effect(USE meth);
11759 ins_cost(CALL_COST);
11760
11761 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11762 // env for callee, C-toc.
11763 ins_num_consts(3);
11764
11765 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11766 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11767 %}
11768
11769 // Tail Call; Jump from runtime stub to Java code.
11770 // Also known as an 'interprocedural jump'.
11771 // Target of jump will eventually return to caller.
11772 // TailJump below removes the return address.
11773 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11774 match(TailCall jump_target method_oop);
11775 ins_cost(CALL_COST);
11776
11777 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11778 "BCTR \t// tail call" %}
11779 size(8);
11780 ins_encode %{
11781 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11782 __ mtctr($jump_target$$Register);
11783 __ bctr();
11784 %}
11785 ins_pipe(pipe_class_call);
11786 %}
11787
11788 // Return Instruction
11789 instruct Ret() %{
11790 match(Return);
11791 format %{ "BLR \t// branch to link register" %}
11792 size(4);
11793 ins_encode %{
11794 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11795 // LR is restored in MachEpilogNode. Just do the RET here.
11796 __ blr();
11797 %}
11798 ins_pipe(pipe_class_default);
11799 %}
11800
11801 // Tail Jump; remove the return address; jump to target.
11802 // TailCall above leaves the return address around.
11803 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11804 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11805 // "restore" before this instruction (in Epilogue), we need to materialize it
11806 // in %i0.
11807 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11808 match(TailJump jump_target ex_oop);
11809 ins_cost(CALL_COST);
11810
11811 format %{ "LD R4_ARG2 = LR\n\t"
11812 "MTCTR $jump_target\n\t"
11813 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11814 size(12);
11815 ins_encode %{
11816 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11817 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11818 __ mtctr($jump_target$$Register);
11819 __ bctr();
11820 %}
11821 ins_pipe(pipe_class_call);
11822 %}
11823
11824 // Create exception oop: created by stack-crawling runtime code.
11825 // Created exception is now available to this handler, and is setup
11826 // just prior to jumping to this handler. No code emitted.
11827 instruct CreateException(rarg1RegP ex_oop) %{
11828 match(Set ex_oop (CreateEx));
11829 ins_cost(0);
11830
11831 format %{ " -- \t// exception oop; no code emitted" %}
11832 size(0);
11833 ins_encode( /*empty*/ );
11834 ins_pipe(pipe_class_default);
11835 %}
11836
11837 // Rethrow exception: The exception oop will come in the first
11838 // argument position. Then JUMP (not call) to the rethrow stub code.
11839 instruct RethrowException() %{
11840 match(Rethrow);
11841 ins_cost(CALL_COST);
11842
11843 format %{ "Jmp rethrow_stub" %}
11844 ins_encode %{
11845 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11846 cbuf.set_insts_mark();
11847 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11848 %}
11849 ins_pipe(pipe_class_call);
11850 %}
11851
11852 // Die now.
11853 instruct ShouldNotReachHere() %{
11854 match(Halt);
11855 ins_cost(CALL_COST);
11856
11857 format %{ "ShouldNotReachHere" %}
11858 size(4);
11859 ins_encode %{
11860 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11861 __ trap_should_not_reach_here();
11862 %}
11863 ins_pipe(pipe_class_default);
11864 %}
11865
11866 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11867 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11868 // Get a DEF on threadRegP, no costs, no encoding, use
11869 // 'ins_should_rematerialize(true)' to avoid spilling.
11870 instruct tlsLoadP(threadRegP dst) %{
11871 match(Set dst (ThreadLocal));
11872 ins_cost(0);
11873
11874 ins_should_rematerialize(true);
11875
11876 format %{ " -- \t// $dst=Thread::current(), empty" %}
11877 size(0);
11878 ins_encode( /*empty*/ );
11879 ins_pipe(pipe_class_empty);
11880 %}
11881
11882 //---Some PPC specific nodes---------------------------------------------------
11883
11884 // Stop a group.
11885 instruct endGroup() %{
11886 ins_cost(0);
11887
11888 ins_is_nop(true);
11889
11890 format %{ "End Bundle (ori r1, r1, 0)" %}
11891 size(4);
11892 ins_encode %{
11893 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11894 __ endgroup();
11895 %}
11896 ins_pipe(pipe_class_default);
11897 %}
11898
11899 // Nop instructions
11900
11901 instruct fxNop() %{
11902 ins_cost(0);
11903
11904 ins_is_nop(true);
11905
11906 format %{ "fxNop" %}
11907 size(4);
11908 ins_encode %{
11909 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11910 __ nop();
11911 %}
11912 ins_pipe(pipe_class_default);
11913 %}
11914
11915 instruct fpNop0() %{
11916 ins_cost(0);
11917
11918 ins_is_nop(true);
11919
11920 format %{ "fpNop0" %}
11921 size(4);
11922 ins_encode %{
11923 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11924 __ fpnop0();
11925 %}
11926 ins_pipe(pipe_class_default);
11927 %}
11928
11929 instruct fpNop1() %{
11930 ins_cost(0);
11931
11932 ins_is_nop(true);
11933
11934 format %{ "fpNop1" %}
11935 size(4);
11936 ins_encode %{
11937 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11938 __ fpnop1();
11939 %}
11940 ins_pipe(pipe_class_default);
11941 %}
11942
11943 instruct brNop0() %{
11944 ins_cost(0);
11945 size(4);
11946 format %{ "brNop0" %}
11947 ins_encode %{
11948 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11949 __ brnop0();
11950 %}
11951 ins_is_nop(true);
11952 ins_pipe(pipe_class_default);
11953 %}
11954
11955 instruct brNop1() %{
11956 ins_cost(0);
11957
11958 ins_is_nop(true);
11959
11960 format %{ "brNop1" %}
11961 size(4);
11962 ins_encode %{
11963 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11964 __ brnop1();
11965 %}
11966 ins_pipe(pipe_class_default);
11967 %}
11968
11969 instruct brNop2() %{
11970 ins_cost(0);
11971
11972 ins_is_nop(true);
11973
11974 format %{ "brNop2" %}
11975 size(4);
11976 ins_encode %{
11977 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11978 __ brnop2();
11979 %}
11980 ins_pipe(pipe_class_default);
11981 %}
11982
11983 //----------PEEPHOLE RULES-----------------------------------------------------
11984 // These must follow all instruction definitions as they use the names
11985 // defined in the instructions definitions.
11986 //
11987 // peepmatch ( root_instr_name [preceeding_instruction]* );
11988 //
11989 // peepconstraint %{
11990 // (instruction_number.operand_name relational_op instruction_number.operand_name
11991 // [, ...] );
11992 // // instruction numbers are zero-based using left to right order in peepmatch
11993 //
11994 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11995 // // provide an instruction_number.operand_name for each operand that appears
11996 // // in the replacement instruction's match rule
11997 //
11998 // ---------VM FLAGS---------------------------------------------------------
11999 //
12000 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12001 //
12002 // Each peephole rule is given an identifying number starting with zero and
12003 // increasing by one in the order seen by the parser. An individual peephole
12004 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12005 // on the command-line.
12006 //
12007 // ---------CURRENT LIMITATIONS----------------------------------------------
12008 //
12009 // Only match adjacent instructions in same basic block
12010 // Only equality constraints
12011 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12012 // Only one replacement instruction
12013 //
12014 // ---------EXAMPLE----------------------------------------------------------
12015 //
12016 // // pertinent parts of existing instructions in architecture description
12017 // instruct movI(eRegI dst, eRegI src) %{
12018 // match(Set dst (CopyI src));
12019 // %}
12020 //
12021 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12022 // match(Set dst (AddI dst src));
12023 // effect(KILL cr);
12024 // %}
12025 //
12026 // // Change (inc mov) to lea
12027 // peephole %{
12028 // // increment preceeded by register-register move
12029 // peepmatch ( incI_eReg movI );
12030 // // require that the destination register of the increment
12031 // // match the destination register of the move
12032 // peepconstraint ( 0.dst == 1.dst );
12033 // // construct a replacement instruction that sets
12034 // // the destination to ( move's source register + one )
12035 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12036 // %}
12037 //
12038 // Implementation no longer uses movX instructions since
12039 // machine-independent system no longer uses CopyX nodes.
12040 //
12041 // peephole %{
12042 // peepmatch ( incI_eReg movI );
12043 // peepconstraint ( 0.dst == 1.dst );
12044 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12045 // %}
12046 //
12047 // peephole %{
12048 // peepmatch ( decI_eReg movI );
12049 // peepconstraint ( 0.dst == 1.dst );
12050 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12051 // %}
12052 //
12053 // peephole %{
12054 // peepmatch ( addI_eReg_imm movI );
12055 // peepconstraint ( 0.dst == 1.dst );
12056 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12057 // %}
12058 //
12059 // peephole %{
12060 // peepmatch ( addP_eReg_imm movP );
12061 // peepconstraint ( 0.dst == 1.dst );
12062 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12063 // %}
12064
12065 // // Change load of spilled value to only a spill
12066 // instruct storeI(memory mem, eRegI src) %{
12067 // match(Set mem (StoreI mem src));
12068 // %}
12069 //
12070 // instruct loadI(eRegI dst, memory mem) %{
12071 // match(Set dst (LoadI mem));
12072 // %}
12073 //
12074 peephole %{
12075 peepmatch ( loadI storeI );
12076 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12077 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12078 %}
12079
12080 peephole %{
12081 peepmatch ( loadL storeL );
12082 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12083 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12084 %}
12085
12086 peephole %{
12087 peepmatch ( loadP storeP );
12088 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12089 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12090 %}
12091
12092 //----------SMARTSPILL RULES---------------------------------------------------
12093 // These must follow all instruction definitions as they use the names
12094 // defined in the instructions definitions.