1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_slots() << LogBytesPerInt;
516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
517 // Remove wordSize for return addr which is already pushed.
518 framesize -= wordSize;
519
520 if (C->need_stack_bang(framesize)) {
521 framesize -= wordSize;
522 st->print("# stack bang");
523 st->print("\n\t");
524 st->print("PUSH EBP\t# Save EBP");
525 if (framesize) {
526 st->print("\n\t");
527 st->print("SUB ESP, #%d\t# Create frame",framesize);
528 }
529 } else {
530 st->print("SUB ESP, #%d\t# Create frame",framesize);
531 st->print("\n\t");
532 framesize -= wordSize;
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
534 }
535
536 if (VerifyStackAtCalls) {
537 st->print("\n\t");
538 framesize -= wordSize;
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
540 }
541
542 if( C->in_24_bit_fp_mode() ) {
543 st->print("\n\t");
544 st->print("FLDCW \t# load 24 bit fpu control word");
545 }
546 if (UseSSE >= 2 && VerifyFPU) {
547 st->print("\n\t");
548 st->print("# verify FPU stack (must be clean on entry)");
549 }
550
551 #ifdef ASSERT
552 if (VerifyStackAtCalls) {
553 st->print("\n\t");
554 st->print("# stack alignment check");
555 }
556 #endif
557 st->cr();
558 }
559 #endif
560
561
562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
563 Compile* C = ra_->C;
564 MacroAssembler _masm(&cbuf);
565
566 int framesize = C->frame_slots() << LogBytesPerInt;
567
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
569
570 C->set_frame_complete(cbuf.insts_size());
571
572 if (C->has_mach_constant_base_node()) {
573 // NOTE: We set the table base offset here because users might be
574 // emitted before MachConstantBaseNode.
575 Compile::ConstantTable& constant_table = C->constant_table();
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
577 }
578 }
579
580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
581 return MachNode::size(ra_); // too many variables; just compute it the hard way
582 }
583
584 int MachPrologNode::reloc() const {
585 return 0; // a large enough number
586 }
587
588 //=============================================================================
589 #ifndef PRODUCT
590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
591 Compile *C = ra_->C;
592 int framesize = C->frame_slots() << LogBytesPerInt;
593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
594 // Remove two words for return addr and rbp,
595 framesize -= 2*wordSize;
596
597 if (C->max_vector_size() > 16) {
598 st->print("VZEROUPPER");
599 st->cr(); st->print("\t");
600 }
601 if (C->in_24_bit_fp_mode()) {
602 st->print("FLDCW standard control word");
603 st->cr(); st->print("\t");
604 }
605 if (framesize) {
606 st->print("ADD ESP,%d\t# Destroy frame",framesize);
607 st->cr(); st->print("\t");
608 }
609 st->print_cr("POPL EBP"); st->print("\t");
610 if (do_polling() && C->is_method_compilation()) {
611 st->print("TEST PollPage,EAX\t! Poll Safepoint");
612 st->cr(); st->print("\t");
613 }
614 }
615 #endif
616
617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
618 Compile *C = ra_->C;
619
620 if (C->max_vector_size() > 16) {
621 // Clear upper bits of YMM registers when current compiled code uses
622 // wide vectors to avoid AVX <-> SSE transition penalty during call.
623 MacroAssembler masm(&cbuf);
624 masm.vzeroupper();
625 }
626 // If method set FPU control word, restore to standard control word
627 if (C->in_24_bit_fp_mode()) {
628 MacroAssembler masm(&cbuf);
629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
630 }
631
632 int framesize = C->frame_slots() << LogBytesPerInt;
633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
634 // Remove two words for return addr and rbp,
635 framesize -= 2*wordSize;
636
637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
638
639 if (framesize >= 128) {
640 emit_opcode(cbuf, 0x81); // add SP, #framesize
641 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
642 emit_d32(cbuf, framesize);
643 } else if (framesize) {
644 emit_opcode(cbuf, 0x83); // add SP, #framesize
645 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
646 emit_d8(cbuf, framesize);
647 }
648
649 emit_opcode(cbuf, 0x58 | EBP_enc);
650
651 if (do_polling() && C->is_method_compilation()) {
652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
653 emit_opcode(cbuf,0x85);
654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
655 emit_d32(cbuf, (intptr_t)os::get_polling_page());
656 }
657 }
658
659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661 // If method set FPU control word, restore to standard control word
662 int size = C->in_24_bit_fp_mode() ? 6 : 0;
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper
664 if (do_polling() && C->is_method_compilation()) size += 6;
665
666 int framesize = C->frame_slots() << LogBytesPerInt;
667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
668 // Remove two words for return addr and rbp,
669 framesize -= 2*wordSize;
670
671 size++; // popl rbp,
672
673 if (framesize >= 128) {
674 size += 6;
675 } else {
676 size += framesize ? 3 : 0;
677 }
678 return size;
679 }
680
681 int MachEpilogNode::reloc() const {
682 return 0; // a large enough number
683 }
684
685 const Pipeline * MachEpilogNode::pipeline() const {
686 return MachNode::pipeline_class();
687 }
688
689 int MachEpilogNode::safepoint_offset() const { return 0; }
690
691 //=============================================================================
692
693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
694 static enum RC rc_class( OptoReg::Name reg ) {
695
696 if( !OptoReg::is_valid(reg) ) return rc_bad;
697 if (OptoReg::is_stack(reg)) return rc_stack;
698
699 VMReg r = OptoReg::as_VMReg(reg);
700 if (r->is_Register()) return rc_int;
701 if (r->is_FloatRegister()) {
702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
703 return rc_float;
704 }
705 assert(r->is_XMMRegister(), "must be");
706 return rc_xmm;
707 }
708
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
710 int opcode, const char *op_str, int size, outputStream* st ) {
711 if( cbuf ) {
712 emit_opcode (*cbuf, opcode );
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
714 #ifndef PRODUCT
715 } else if( !do_size ) {
716 if( size != 0 ) st->print("\n\t");
717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
720 } else { // FLD, FST, PUSH, POP
721 st->print("%s [ESP + #%d]",op_str,offset);
722 }
723 #endif
724 }
725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
726 return size+3+offset_size;
727 }
728
729 // Helper for XMM registers. Extra opcode bits, limited syntax.
730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
732 if (cbuf) {
733 MacroAssembler _masm(cbuf);
734 if (reg_lo+1 == reg_hi) { // double move?
735 if (is_load) {
736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
737 } else {
738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
739 }
740 } else {
741 if (is_load) {
742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
743 } else {
744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
745 }
746 }
747 #ifndef PRODUCT
748 } else if (!do_size) {
749 if (size != 0) st->print("\n\t");
750 if (reg_lo+1 == reg_hi) { // double move?
751 if (is_load) st->print("%s %s,[ESP + #%d]",
752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSD [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 } else {
757 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
758 Matcher::regName[reg_lo], offset);
759 else st->print("MOVSS [ESP + #%d],%s",
760 offset, Matcher::regName[reg_lo]);
761 }
762 #endif
763 }
764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
766 return size+5+offset_size;
767 }
768
769
770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
771 int src_hi, int dst_hi, int size, outputStream* st ) {
772 if (cbuf) {
773 MacroAssembler _masm(cbuf);
774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
776 as_XMMRegister(Matcher::_regEncode[src_lo]));
777 } else {
778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
779 as_XMMRegister(Matcher::_regEncode[src_lo]));
780 }
781 #ifndef PRODUCT
782 } else if (!do_size) {
783 if (size != 0) st->print("\n\t");
784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
787 } else {
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 }
790 } else {
791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
793 } else {
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 }
796 }
797 #endif
798 }
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
800 // Only MOVAPS SSE prefix uses 1 byte.
801 int sz = 4;
802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
804 return size + sz;
805 }
806
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
808 int src_hi, int dst_hi, int size, outputStream* st ) {
809 // 32-bit
810 if (cbuf) {
811 MacroAssembler _masm(cbuf);
812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
813 as_Register(Matcher::_regEncode[src_lo]));
814 #ifndef PRODUCT
815 } else if (!do_size) {
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
817 #endif
818 }
819 return 4;
820 }
821
822
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 // 32-bit
826 if (cbuf) {
827 MacroAssembler _masm(cbuf);
828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
829 as_XMMRegister(Matcher::_regEncode[src_lo]));
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
833 #endif
834 }
835 return 4;
836 }
837
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
839 if( cbuf ) {
840 emit_opcode(*cbuf, 0x8B );
841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
842 #ifndef PRODUCT
843 } else if( !do_size ) {
844 if( size != 0 ) st->print("\n\t");
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
846 #endif
847 }
848 return size+2;
849 }
850
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
852 int offset, int size, outputStream* st ) {
853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
854 if( cbuf ) {
855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
857 #ifndef PRODUCT
858 } else if( !do_size ) {
859 if( size != 0 ) st->print("\n\t");
860 st->print("FLD %s",Matcher::regName[src_lo]);
861 #endif
862 }
863 size += 2;
864 }
865
866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
867 const char *op_str;
868 int op;
869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
871 op = 0xDD;
872 } else { // 32-bit store
873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
874 op = 0xD9;
875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
876 }
877
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
879 }
880
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
883 int src_hi, int dst_hi, uint ireg, outputStream* st);
884
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
886 int stack_offset, int reg, uint ireg, outputStream* st);
887
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
889 int dst_offset, uint ireg, outputStream* st) {
890 int calc_size = 0;
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
893 switch (ireg) {
894 case Op_VecS:
895 calc_size = 3+src_offset_size + 3+dst_offset_size;
896 break;
897 case Op_VecD:
898 calc_size = 3+src_offset_size + 3+dst_offset_size;
899 src_offset += 4;
900 dst_offset += 4;
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
903 calc_size += 3+src_offset_size + 3+dst_offset_size;
904 break;
905 case Op_VecX:
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
907 break;
908 case Op_VecY:
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
910 break;
911 default:
912 ShouldNotReachHere();
913 }
914 if (cbuf) {
915 MacroAssembler _masm(cbuf);
916 int offset = __ offset();
917 switch (ireg) {
918 case Op_VecS:
919 __ pushl(Address(rsp, src_offset));
920 __ popl (Address(rsp, dst_offset));
921 break;
922 case Op_VecD:
923 __ pushl(Address(rsp, src_offset));
924 __ popl (Address(rsp, dst_offset));
925 __ pushl(Address(rsp, src_offset+4));
926 __ popl (Address(rsp, dst_offset+4));
927 break;
928 case Op_VecX:
929 __ movdqu(Address(rsp, -16), xmm0);
930 __ movdqu(xmm0, Address(rsp, src_offset));
931 __ movdqu(Address(rsp, dst_offset), xmm0);
932 __ movdqu(xmm0, Address(rsp, -16));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 int size = __ offset() - offset;
944 assert(size == calc_size, "incorrect size calculattion");
945 return size;
946 #ifndef PRODUCT
947 } else if (!do_size) {
948 switch (ireg) {
949 case Op_VecS:
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
951 "popl [rsp + #%d]",
952 src_offset, dst_offset);
953 break;
954 case Op_VecD:
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
956 "popq [rsp + #%d]\n\t"
957 "pushl [rsp + #%d]\n\t"
958 "popq [rsp + #%d]",
959 src_offset, dst_offset, src_offset+4, dst_offset+4);
960 break;
961 case Op_VecX:
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
963 "movdqu xmm0, [rsp + #%d]\n\t"
964 "movdqu [rsp + #%d], xmm0\n\t"
965 "movdqu xmm0, [rsp - #16]",
966 src_offset, dst_offset);
967 break;
968 case Op_VecY:
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
970 "vmovdqu xmm0, [rsp + #%d]\n\t"
971 "vmovdqu [rsp + #%d], xmm0\n\t"
972 "vmovdqu xmm0, [rsp - #32]",
973 src_offset, dst_offset);
974 break;
975 default:
976 ShouldNotReachHere();
977 }
978 #endif
979 }
980 return calc_size;
981 }
982
983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this );
988 OptoReg::Name dst_first = ra_->get_reg_first(this );
989
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
994
995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
996
997 // Generate spill code!
998 int size = 0;
999
1000 if( src_first == dst_first && src_second == dst_second )
1001 return size; // Self copy, no move
1002
1003 if (bottom_type()->isa_vect() != NULL) {
1004 uint ireg = ideal_reg();
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1025
1026 // --------------------------------------
1027 // Check for mem-mem move. push/pop to move.
1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029 if( src_second == dst_first ) { // overlapping stack copy ranges
1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1034 }
1035 // move low bits
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1041 }
1042 return size;
1043 }
1044
1045 // --------------------------------------
1046 // Check for integer reg-reg copy
1047 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1049
1050 // Check for integer store
1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1053
1054 // Check for integer load
1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1057
1058 // Check for integer reg-xmm reg copy
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061 "no 64 bit integer-float reg moves" );
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063 }
1064 // --------------------------------------
1065 // Check for float reg-reg copy
1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069 if( cbuf ) {
1070
1071 // Note the mucking with the register encode to compensate for the 0/1
1072 // indexing issue mentioned in a comment in the reg_def sections
1073 // for FPR registers many lines above here.
1074
1075 if( src_first != FPR1L_num ) {
1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080 } else {
1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083 }
1084 #ifndef PRODUCT
1085 } else if( !do_size ) {
1086 if( size != 0 ) st->print("\n\t");
1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088 else st->print( "FST %s", Matcher::regName[dst_first]);
1089 #endif
1090 }
1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092 }
1093
1094 // Check for float store
1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097 }
1098
1099 // Check for float load
1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101 int offset = ra_->reg2offset(src_first);
1102 const char *op_str;
1103 int op;
1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105 op_str = "FLD_D";
1106 op = 0xDD;
1107 } else { // 32-bit load
1108 op_str = "FLD_S";
1109 op = 0xD9;
1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111 }
1112 if( cbuf ) {
1113 emit_opcode (*cbuf, op );
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118 } else if( !do_size ) {
1119 if( size != 0 ) st->print("\n\t");
1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122 }
1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124 return size + 3+offset_size+2;
1125 }
1126
1127 // Check for xmm reg-reg copy
1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130 (src_first+1 == src_second && dst_first+1 == dst_second),
1131 "no non-adjacent float-moves" );
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133 }
1134
1135 // Check for xmm reg-integer reg copy
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138 "no 64 bit float-integer reg moves" );
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140 }
1141
1142 // Check for xmm store
1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145 }
1146
1147 // Check for float xmm load
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150 }
1151
1152 // Copy from float reg to xmm reg
1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154 // copy to the top of stack from floating point reg
1155 // and use LEA to preserve flags
1156 if( cbuf ) {
1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160 emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162 } else if( !do_size ) {
1163 if( size != 0 ) st->print("\n\t");
1164 st->print("LEA ESP,[ESP-8]");
1165 #endif
1166 }
1167 size += 4;
1168
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1170
1171 // Copy from the temp memory to the xmm reg.
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1173
1174 if( cbuf ) {
1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178 emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180 } else if( !do_size ) {
1181 if( size != 0 ) st->print("\n\t");
1182 st->print("LEA ESP,[ESP+8]");
1183 #endif
1184 }
1185 size += 4;
1186 return size;
1187 }
1188
1189 assert( size > 0, "missed a case" );
1190
1191 // --------------------------------------------------------------------
1192 // Check for second bits still needing moving.
1193 if( src_second == dst_second )
1194 return size; // Self copy; no move
1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1196
1197 // Check for second word int-int move
1198 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1200
1201 // Check for second word integer store
1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1204
1205 // Check for second word integer load
1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1208
1209
1210 Unimplemented();
1211 }
1212
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215 implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1218
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 implementation( &cbuf, ra_, false, NULL );
1221 }
1222
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224 return implementation( NULL, ra_, true, NULL );
1225 }
1226
1227
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232 int reg = ra_->get_reg_first(this);
1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1236
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239 int reg = ra_->get_encode(this);
1240 if( offset >= 128 ) {
1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1242 emit_rm(cbuf, 0x2, reg, 0x04);
1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244 emit_d32(cbuf, offset);
1245 }
1246 else {
1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1248 emit_rm(cbuf, 0x1, reg, 0x04);
1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250 emit_d8(cbuf, offset);
1251 }
1252 }
1253
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256 if( offset >= 128 ) {
1257 return 7;
1258 }
1259 else {
1260 return 4;
1261 }
1262 }
1263
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1269 st->print_cr("\tNOP");
1270 st->print_cr("\tNOP");
1271 if( !OptoBreakpoint )
1272 st->print_cr("\tNOP");
1273 }
1274 #endif
1275
1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277 MacroAssembler masm(&cbuf);
1278 #ifdef ASSERT
1279 uint insts_size = cbuf.insts_size();
1280 #endif
1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1282 masm.jump_cc(Assembler::notEqual,
1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1284 /* WARNING these NOPs are critical so that verified entry point is properly
1285 aligned for patching by NativeJump::patch_verified_entry() */
1286 int nops_cnt = 2;
1287 if( !OptoBreakpoint ) // Leave space for int3
1288 nops_cnt += 1;
1289 masm.nop(nops_cnt);
1290
1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1292 }
1293
1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1295 return OptoBreakpoint ? 11 : 12;
1296 }
1297
1298
1299 //=============================================================================
1300
1301 int Matcher::regnum_to_fpu_offset(int regnum) {
1302 return regnum - 32; // The FP registers are in the second chunk
1303 }
1304
1305 // This is UltraSparc specific, true just means we have fast l2f conversion
1306 const bool Matcher::convL2FSupported(void) {
1307 return true;
1308 }
1309
1310 // Is this branch offset short enough that a short branch can be used?
1311 //
1312 // NOTE: If the platform does not provide any short branch variants, then
1313 // this method should return false for offset 0.
1314 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1315 // The passed offset is relative to address of the branch.
1316 // On 86 a branch displacement is calculated relative to address
1317 // of a next instruction.
1318 offset -= br_size;
1319
1320 // the short version of jmpConUCF2 contains multiple branches,
1321 // making the reach slightly less
1322 if (rule == jmpConUCF2_rule)
1323 return (-126 <= offset && offset <= 125);
1324 return (-128 <= offset && offset <= 127);
1325 }
1326
1327 const bool Matcher::isSimpleConstant64(jlong value) {
1328 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1329 return false;
1330 }
1331
1332 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1333 const bool Matcher::init_array_count_is_in_bytes = false;
1334
1335 // Threshold size for cleararray.
1336 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1337
1338 // Needs 2 CMOV's for longs.
1339 const int Matcher::long_cmove_cost() { return 1; }
1340
1341 // No CMOVF/CMOVD with SSE/SSE2
1342 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1343
1344 // Does the CPU require late expand (see block.cpp for description of late expand)?
1345 const bool Matcher::require_postalloc_expand = false;
1346
1347 // Should the Matcher clone shifts on addressing modes, expecting them to
1348 // be subsumed into complex addressing expressions or compute them into
1349 // registers? True for Intel but false for most RISCs
1350 const bool Matcher::clone_shift_expressions = true;
1351
1352 // Do we need to mask the count passed to shift instructions or does
1353 // the cpu only look at the lower 5/6 bits anyway?
1354 const bool Matcher::need_masked_shift_count = false;
1355
1356 bool Matcher::narrow_oop_use_complex_address() {
1357 ShouldNotCallThis();
1358 return true;
1359 }
1360
1361 bool Matcher::narrow_klass_use_complex_address() {
1362 ShouldNotCallThis();
1363 return true;
1364 }
1365
1366
1367 // Is it better to copy float constants, or load them directly from memory?
1368 // Intel can load a float constant from a direct address, requiring no
1369 // extra registers. Most RISCs will have to materialize an address into a
1370 // register first, so they would do better to copy the constant from stack.
1371 const bool Matcher::rematerialize_float_constants = true;
1372
1373 // If CPU can load and store mis-aligned doubles directly then no fixup is
1374 // needed. Else we split the double into 2 integer pieces and move it
1375 // piece-by-piece. Only happens when passing doubles into C code as the
1376 // Java calling convention forces doubles to be aligned.
1377 const bool Matcher::misaligned_doubles_ok = true;
1378
1379
1380 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1381 // Get the memory operand from the node
1382 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1383 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1384 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1385 uint opcnt = 1; // First operand
1386 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1387 while( idx >= skipped+num_edges ) {
1388 skipped += num_edges;
1389 opcnt++; // Bump operand count
1390 assert( opcnt < numopnds, "Accessing non-existent operand" );
1391 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1392 }
1393
1394 MachOper *memory = node->_opnds[opcnt];
1395 MachOper *new_memory = NULL;
1396 switch (memory->opcode()) {
1397 case DIRECT:
1398 case INDOFFSET32X:
1399 // No transformation necessary.
1400 return;
1401 case INDIRECT:
1402 new_memory = new (C) indirect_win95_safeOper( );
1403 break;
1404 case INDOFFSET8:
1405 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1406 break;
1407 case INDOFFSET32:
1408 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1409 break;
1410 case INDINDEXOFFSET:
1411 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1412 break;
1413 case INDINDEXSCALE:
1414 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1415 break;
1416 case INDINDEXSCALEOFFSET:
1417 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1418 break;
1419 case LOAD_LONG_INDIRECT:
1420 case LOAD_LONG_INDOFFSET32:
1421 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1422 return;
1423 default:
1424 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1425 return;
1426 }
1427 node->_opnds[opcnt] = new_memory;
1428 }
1429
1430 // Advertise here if the CPU requires explicit rounding operations
1431 // to implement the UseStrictFP mode.
1432 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1433
1434 // Are floats conerted to double when stored to stack during deoptimization?
1435 // On x32 it is stored with convertion only when FPU is used for floats.
1436 bool Matcher::float_in_double() { return (UseSSE == 0); }
1437
1438 // Do ints take an entire long register or just half?
1439 const bool Matcher::int_in_long = false;
1440
1441 // Return whether or not this register is ever used as an argument. This
1442 // function is used on startup to build the trampoline stubs in generateOptoStub.
1443 // Registers not mentioned will be killed by the VM call in the trampoline, and
1444 // arguments in those registers not be available to the callee.
1445 bool Matcher::can_be_java_arg( int reg ) {
1446 if( reg == ECX_num || reg == EDX_num ) return true;
1447 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1448 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1449 return false;
1450 }
1451
1452 bool Matcher::is_spillable_arg( int reg ) {
1453 return can_be_java_arg(reg);
1454 }
1455
1456 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1457 // Use hardware integer DIV instruction when
1458 // it is faster than a code which use multiply.
1459 // Only when constant divisor fits into 32 bit
1460 // (min_jint is excluded to get only correct
1461 // positive 32 bit values from negative).
1462 return VM_Version::has_fast_idiv() &&
1463 (divisor == (int)divisor && divisor != min_jint);
1464 }
1465
1466 // Register for DIVI projection of divmodI
1467 RegMask Matcher::divI_proj_mask() {
1468 return EAX_REG_mask();
1469 }
1470
1471 // Register for MODI projection of divmodI
1472 RegMask Matcher::modI_proj_mask() {
1473 return EDX_REG_mask();
1474 }
1475
1476 // Register for DIVL projection of divmodL
1477 RegMask Matcher::divL_proj_mask() {
1478 ShouldNotReachHere();
1479 return RegMask();
1480 }
1481
1482 // Register for MODL projection of divmodL
1483 RegMask Matcher::modL_proj_mask() {
1484 ShouldNotReachHere();
1485 return RegMask();
1486 }
1487
1488 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1489 return EBP_REG_mask();
1490 }
1491
1492 // Returns true if the high 32 bits of the value is known to be zero.
1493 bool is_operand_hi32_zero(Node* n) {
1494 int opc = n->Opcode();
1495 if (opc == Op_AndL) {
1496 Node* o2 = n->in(2);
1497 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1498 return true;
1499 }
1500 }
1501 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1502 return true;
1503 }
1504 return false;
1505 }
1506
1507 %}
1508
1509 //----------ENCODING BLOCK-----------------------------------------------------
1510 // This block specifies the encoding classes used by the compiler to output
1511 // byte streams. Encoding classes generate functions which are called by
1512 // Machine Instruction Nodes in order to generate the bit encoding of the
1513 // instruction. Operands specify their base encoding interface with the
1514 // interface keyword. There are currently supported four interfaces,
1515 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1516 // operand to generate a function which returns its register number when
1517 // queried. CONST_INTER causes an operand to generate a function which
1518 // returns the value of the constant when queried. MEMORY_INTER causes an
1519 // operand to generate four functions which return the Base Register, the
1520 // Index Register, the Scale Value, and the Offset Value of the operand when
1521 // queried. COND_INTER causes an operand to generate six functions which
1522 // return the encoding code (ie - encoding bits for the instruction)
1523 // associated with each basic boolean condition for a conditional instruction.
1524 // Instructions specify two basic values for encoding. They use the
1525 // ins_encode keyword to specify their encoding class (which must be one of
1526 // the class names specified in the encoding block), and they use the
1527 // opcode keyword to specify, in order, their primary, secondary, and
1528 // tertiary opcode. Only the opcode sections which a particular instruction
1529 // needs for encoding need to be specified.
1530 encode %{
1531 // Build emit functions for each basic byte or larger field in the intel
1532 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1533 // code in the enc_class source block. Emit functions will live in the
1534 // main source block for now. In future, we can generalize this by
1535 // adding a syntax that specifies the sizes of fields in an order,
1536 // so that the adlc can build the emit functions automagically
1537
1538 // Emit primary opcode
1539 enc_class OpcP %{
1540 emit_opcode(cbuf, $primary);
1541 %}
1542
1543 // Emit secondary opcode
1544 enc_class OpcS %{
1545 emit_opcode(cbuf, $secondary);
1546 %}
1547
1548 // Emit opcode directly
1549 enc_class Opcode(immI d8) %{
1550 emit_opcode(cbuf, $d8$$constant);
1551 %}
1552
1553 enc_class SizePrefix %{
1554 emit_opcode(cbuf,0x66);
1555 %}
1556
1557 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1558 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1559 %}
1560
1561 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1562 emit_opcode(cbuf,$opcode$$constant);
1563 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1564 %}
1565
1566 enc_class mov_r32_imm0( rRegI dst ) %{
1567 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1568 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1569 %}
1570
1571 enc_class cdq_enc %{
1572 // Full implementation of Java idiv and irem; checks for
1573 // special case as described in JVM spec., p.243 & p.271.
1574 //
1575 // normal case special case
1576 //
1577 // input : rax,: dividend min_int
1578 // reg: divisor -1
1579 //
1580 // output: rax,: quotient (= rax, idiv reg) min_int
1581 // rdx: remainder (= rax, irem reg) 0
1582 //
1583 // Code sequnce:
1584 //
1585 // 81 F8 00 00 00 80 cmp rax,80000000h
1586 // 0F 85 0B 00 00 00 jne normal_case
1587 // 33 D2 xor rdx,edx
1588 // 83 F9 FF cmp rcx,0FFh
1589 // 0F 84 03 00 00 00 je done
1590 // normal_case:
1591 // 99 cdq
1592 // F7 F9 idiv rax,ecx
1593 // done:
1594 //
1595 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1596 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1597 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1598 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1599 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1600 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1601 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1602 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1603 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1604 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1605 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1606 // normal_case:
1607 emit_opcode(cbuf,0x99); // cdq
1608 // idiv (note: must be emitted by the user of this rule)
1609 // normal:
1610 %}
1611
1612 // Dense encoding for older common ops
1613 enc_class Opc_plus(immI opcode, rRegI reg) %{
1614 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1615 %}
1616
1617
1618 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1619 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1620 // Check for 8-bit immediate, and set sign extend bit in opcode
1621 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1622 emit_opcode(cbuf, $primary | 0x02);
1623 }
1624 else { // If 32-bit immediate
1625 emit_opcode(cbuf, $primary);
1626 }
1627 %}
1628
1629 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1630 // Emit primary opcode and set sign-extend bit
1631 // Check for 8-bit immediate, and set sign extend bit in opcode
1632 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1633 emit_opcode(cbuf, $primary | 0x02); }
1634 else { // If 32-bit immediate
1635 emit_opcode(cbuf, $primary);
1636 }
1637 // Emit r/m byte with secondary opcode, after primary opcode.
1638 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1639 %}
1640
1641 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1642 // Check for 8-bit immediate, and set sign extend bit in opcode
1643 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1644 $$$emit8$imm$$constant;
1645 }
1646 else { // If 32-bit immediate
1647 // Output immediate
1648 $$$emit32$imm$$constant;
1649 }
1650 %}
1651
1652 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1653 // Emit primary opcode and set sign-extend bit
1654 // Check for 8-bit immediate, and set sign extend bit in opcode
1655 int con = (int)$imm$$constant; // Throw away top bits
1656 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1657 // Emit r/m byte with secondary opcode, after primary opcode.
1658 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1659 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1660 else emit_d32(cbuf,con);
1661 %}
1662
1663 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1664 // Emit primary opcode and set sign-extend bit
1665 // Check for 8-bit immediate, and set sign extend bit in opcode
1666 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1667 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1668 // Emit r/m byte with tertiary opcode, after primary opcode.
1669 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1670 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1671 else emit_d32(cbuf,con);
1672 %}
1673
1674 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1675 emit_cc(cbuf, $secondary, $dst$$reg );
1676 %}
1677
1678 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1679 int destlo = $dst$$reg;
1680 int desthi = HIGH_FROM_LOW(destlo);
1681 // bswap lo
1682 emit_opcode(cbuf, 0x0F);
1683 emit_cc(cbuf, 0xC8, destlo);
1684 // bswap hi
1685 emit_opcode(cbuf, 0x0F);
1686 emit_cc(cbuf, 0xC8, desthi);
1687 // xchg lo and hi
1688 emit_opcode(cbuf, 0x87);
1689 emit_rm(cbuf, 0x3, destlo, desthi);
1690 %}
1691
1692 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1693 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1694 %}
1695
1696 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1697 $$$emit8$primary;
1698 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1699 %}
1700
1701 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1702 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1703 emit_d8(cbuf, op >> 8 );
1704 emit_d8(cbuf, op & 255);
1705 %}
1706
1707 // emulate a CMOV with a conditional branch around a MOV
1708 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1709 // Invert sense of branch from sense of CMOV
1710 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1711 emit_d8( cbuf, $brOffs$$constant );
1712 %}
1713
1714 enc_class enc_PartialSubtypeCheck( ) %{
1715 Register Redi = as_Register(EDI_enc); // result register
1716 Register Reax = as_Register(EAX_enc); // super class
1717 Register Recx = as_Register(ECX_enc); // killed
1718 Register Resi = as_Register(ESI_enc); // sub class
1719 Label miss;
1720
1721 MacroAssembler _masm(&cbuf);
1722 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1723 NULL, &miss,
1724 /*set_cond_codes:*/ true);
1725 if ($primary) {
1726 __ xorptr(Redi, Redi);
1727 }
1728 __ bind(miss);
1729 %}
1730
1731 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1732 MacroAssembler masm(&cbuf);
1733 int start = masm.offset();
1734 if (UseSSE >= 2) {
1735 if (VerifyFPU) {
1736 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1737 }
1738 } else {
1739 // External c_calling_convention expects the FPU stack to be 'clean'.
1740 // Compiled code leaves it dirty. Do cleanup now.
1741 masm.empty_FPU_stack();
1742 }
1743 if (sizeof_FFree_Float_Stack_All == -1) {
1744 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1745 } else {
1746 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1747 }
1748 %}
1749
1750 enc_class Verify_FPU_For_Leaf %{
1751 if( VerifyFPU ) {
1752 MacroAssembler masm(&cbuf);
1753 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1754 }
1755 %}
1756
1757 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1758 // This is the instruction starting address for relocation info.
1759 cbuf.set_insts_mark();
1760 $$$emit8$primary;
1761 // CALL directly to the runtime
1762 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1763 runtime_call_Relocation::spec(), RELOC_IMM32 );
1764
1765 if (UseSSE >= 2) {
1766 MacroAssembler _masm(&cbuf);
1767 BasicType rt = tf()->return_type();
1768
1769 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1770 // A C runtime call where the return value is unused. In SSE2+
1771 // mode the result needs to be removed from the FPU stack. It's
1772 // likely that this function call could be removed by the
1773 // optimizer if the C function is a pure function.
1774 __ ffree(0);
1775 } else if (rt == T_FLOAT) {
1776 __ lea(rsp, Address(rsp, -4));
1777 __ fstp_s(Address(rsp, 0));
1778 __ movflt(xmm0, Address(rsp, 0));
1779 __ lea(rsp, Address(rsp, 4));
1780 } else if (rt == T_DOUBLE) {
1781 __ lea(rsp, Address(rsp, -8));
1782 __ fstp_d(Address(rsp, 0));
1783 __ movdbl(xmm0, Address(rsp, 0));
1784 __ lea(rsp, Address(rsp, 8));
1785 }
1786 }
1787 %}
1788
1789
1790 enc_class pre_call_resets %{
1791 // If method sets FPU control word restore it here
1792 debug_only(int off0 = cbuf.insts_size());
1793 if (ra_->C->in_24_bit_fp_mode()) {
1794 MacroAssembler _masm(&cbuf);
1795 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1796 }
1797 if (ra_->C->max_vector_size() > 16) {
1798 // Clear upper bits of YMM registers when current compiled code uses
1799 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1800 MacroAssembler _masm(&cbuf);
1801 __ vzeroupper();
1802 }
1803 debug_only(int off1 = cbuf.insts_size());
1804 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1805 %}
1806
1807 enc_class post_call_FPU %{
1808 // If method sets FPU control word do it here also
1809 if (Compile::current()->in_24_bit_fp_mode()) {
1810 MacroAssembler masm(&cbuf);
1811 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1812 }
1813 %}
1814
1815 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1816 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1817 // who we intended to call.
1818 cbuf.set_insts_mark();
1819 $$$emit8$primary;
1820 if (!_method) {
1821 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1822 runtime_call_Relocation::spec(), RELOC_IMM32 );
1823 } else if (_optimized_virtual) {
1824 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1825 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1826 } else {
1827 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1828 static_call_Relocation::spec(), RELOC_IMM32 );
1829 }
1830 if (_method) { // Emit stub for static call.
1831 CompiledStaticCall::emit_to_interp_stub(cbuf);
1832 }
1833 %}
1834
1835 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1836 MacroAssembler _masm(&cbuf);
1837 __ ic_call((address)$meth$$method);
1838 %}
1839
1840 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1841 int disp = in_bytes(Method::from_compiled_offset());
1842 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1843
1844 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1845 cbuf.set_insts_mark();
1846 $$$emit8$primary;
1847 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1848 emit_d8(cbuf, disp); // Displacement
1849
1850 %}
1851
1852 // Following encoding is no longer used, but may be restored if calling
1853 // convention changes significantly.
1854 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1855 //
1856 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1857 // // int ic_reg = Matcher::inline_cache_reg();
1858 // // int ic_encode = Matcher::_regEncode[ic_reg];
1859 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1860 // // int imo_encode = Matcher::_regEncode[imo_reg];
1861 //
1862 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1863 // // // so we load it immediately before the call
1864 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1865 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1866 //
1867 // // xor rbp,ebp
1868 // emit_opcode(cbuf, 0x33);
1869 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1870 //
1871 // // CALL to interpreter.
1872 // cbuf.set_insts_mark();
1873 // $$$emit8$primary;
1874 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1875 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1876 // %}
1877
1878 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1879 $$$emit8$primary;
1880 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1881 $$$emit8$shift$$constant;
1882 %}
1883
1884 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1885 // Load immediate does not have a zero or sign extended version
1886 // for 8-bit immediates
1887 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1888 $$$emit32$src$$constant;
1889 %}
1890
1891 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1892 // Load immediate does not have a zero or sign extended version
1893 // for 8-bit immediates
1894 emit_opcode(cbuf, $primary + $dst$$reg);
1895 $$$emit32$src$$constant;
1896 %}
1897
1898 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1899 // Load immediate does not have a zero or sign extended version
1900 // for 8-bit immediates
1901 int dst_enc = $dst$$reg;
1902 int src_con = $src$$constant & 0x0FFFFFFFFL;
1903 if (src_con == 0) {
1904 // xor dst, dst
1905 emit_opcode(cbuf, 0x33);
1906 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1907 } else {
1908 emit_opcode(cbuf, $primary + dst_enc);
1909 emit_d32(cbuf, src_con);
1910 }
1911 %}
1912
1913 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1914 // Load immediate does not have a zero or sign extended version
1915 // for 8-bit immediates
1916 int dst_enc = $dst$$reg + 2;
1917 int src_con = ((julong)($src$$constant)) >> 32;
1918 if (src_con == 0) {
1919 // xor dst, dst
1920 emit_opcode(cbuf, 0x33);
1921 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1922 } else {
1923 emit_opcode(cbuf, $primary + dst_enc);
1924 emit_d32(cbuf, src_con);
1925 }
1926 %}
1927
1928
1929 // Encode a reg-reg copy. If it is useless, then empty encoding.
1930 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1931 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1932 %}
1933
1934 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1935 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1936 %}
1937
1938 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1939 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1940 %}
1941
1942 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1943 $$$emit8$primary;
1944 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1945 %}
1946
1947 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1948 $$$emit8$secondary;
1949 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1950 %}
1951
1952 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1953 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1954 %}
1955
1956 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
1957 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1958 %}
1959
1960 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
1961 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1962 %}
1963
1964 enc_class Con32 (immI src) %{ // Con32(storeImmI)
1965 // Output immediate
1966 $$$emit32$src$$constant;
1967 %}
1968
1969 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
1970 // Output Float immediate bits
1971 jfloat jf = $src$$constant;
1972 int jf_as_bits = jint_cast( jf );
1973 emit_d32(cbuf, jf_as_bits);
1974 %}
1975
1976 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
1977 // Output Float immediate bits
1978 jfloat jf = $src$$constant;
1979 int jf_as_bits = jint_cast( jf );
1980 emit_d32(cbuf, jf_as_bits);
1981 %}
1982
1983 enc_class Con16 (immI src) %{ // Con16(storeImmI)
1984 // Output immediate
1985 $$$emit16$src$$constant;
1986 %}
1987
1988 enc_class Con_d32(immI src) %{
1989 emit_d32(cbuf,$src$$constant);
1990 %}
1991
1992 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
1993 // Output immediate memory reference
1994 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
1995 emit_d32(cbuf, 0x00);
1996 %}
1997
1998 enc_class lock_prefix( ) %{
1999 if( os::is_MP() )
2000 emit_opcode(cbuf,0xF0); // [Lock]
2001 %}
2002
2003 // Cmp-xchg long value.
2004 // Note: we need to swap rbx, and rcx before and after the
2005 // cmpxchg8 instruction because the instruction uses
2006 // rcx as the high order word of the new value to store but
2007 // our register encoding uses rbx,.
2008 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2009
2010 // XCHG rbx,ecx
2011 emit_opcode(cbuf,0x87);
2012 emit_opcode(cbuf,0xD9);
2013 // [Lock]
2014 if( os::is_MP() )
2015 emit_opcode(cbuf,0xF0);
2016 // CMPXCHG8 [Eptr]
2017 emit_opcode(cbuf,0x0F);
2018 emit_opcode(cbuf,0xC7);
2019 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2020 // XCHG rbx,ecx
2021 emit_opcode(cbuf,0x87);
2022 emit_opcode(cbuf,0xD9);
2023 %}
2024
2025 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2026 // [Lock]
2027 if( os::is_MP() )
2028 emit_opcode(cbuf,0xF0);
2029
2030 // CMPXCHG [Eptr]
2031 emit_opcode(cbuf,0x0F);
2032 emit_opcode(cbuf,0xB1);
2033 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2034 %}
2035
2036 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2037 int res_encoding = $res$$reg;
2038
2039 // MOV res,0
2040 emit_opcode( cbuf, 0xB8 + res_encoding);
2041 emit_d32( cbuf, 0 );
2042 // JNE,s fail
2043 emit_opcode(cbuf,0x75);
2044 emit_d8(cbuf, 5 );
2045 // MOV res,1
2046 emit_opcode( cbuf, 0xB8 + res_encoding);
2047 emit_d32( cbuf, 1 );
2048 // fail:
2049 %}
2050
2051 enc_class set_instruction_start( ) %{
2052 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2053 %}
2054
2055 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2056 int reg_encoding = $ereg$$reg;
2057 int base = $mem$$base;
2058 int index = $mem$$index;
2059 int scale = $mem$$scale;
2060 int displace = $mem$$disp;
2061 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2062 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2063 %}
2064
2065 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2066 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2067 int base = $mem$$base;
2068 int index = $mem$$index;
2069 int scale = $mem$$scale;
2070 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2071 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2072 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2073 %}
2074
2075 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2076 int r1, r2;
2077 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2078 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2079 emit_opcode(cbuf,0x0F);
2080 emit_opcode(cbuf,$tertiary);
2081 emit_rm(cbuf, 0x3, r1, r2);
2082 emit_d8(cbuf,$cnt$$constant);
2083 emit_d8(cbuf,$primary);
2084 emit_rm(cbuf, 0x3, $secondary, r1);
2085 emit_d8(cbuf,$cnt$$constant);
2086 %}
2087
2088 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2089 emit_opcode( cbuf, 0x8B ); // Move
2090 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2091 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2092 emit_d8(cbuf,$primary);
2093 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2094 emit_d8(cbuf,$cnt$$constant-32);
2095 }
2096 emit_d8(cbuf,$primary);
2097 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2098 emit_d8(cbuf,31);
2099 %}
2100
2101 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2102 int r1, r2;
2103 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2104 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2105
2106 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2107 emit_rm(cbuf, 0x3, r1, r2);
2108 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2109 emit_opcode(cbuf,$primary);
2110 emit_rm(cbuf, 0x3, $secondary, r1);
2111 emit_d8(cbuf,$cnt$$constant-32);
2112 }
2113 emit_opcode(cbuf,0x33); // XOR r2,r2
2114 emit_rm(cbuf, 0x3, r2, r2);
2115 %}
2116
2117 // Clone of RegMem but accepts an extra parameter to access each
2118 // half of a double in memory; it never needs relocation info.
2119 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2120 emit_opcode(cbuf,$opcode$$constant);
2121 int reg_encoding = $rm_reg$$reg;
2122 int base = $mem$$base;
2123 int index = $mem$$index;
2124 int scale = $mem$$scale;
2125 int displace = $mem$$disp + $disp_for_half$$constant;
2126 relocInfo::relocType disp_reloc = relocInfo::none;
2127 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2128 %}
2129
2130 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2131 //
2132 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2133 // and it never needs relocation information.
2134 // Frequently used to move data between FPU's Stack Top and memory.
2135 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2136 int rm_byte_opcode = $rm_opcode$$constant;
2137 int base = $mem$$base;
2138 int index = $mem$$index;
2139 int scale = $mem$$scale;
2140 int displace = $mem$$disp;
2141 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2142 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2143 %}
2144
2145 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2146 int rm_byte_opcode = $rm_opcode$$constant;
2147 int base = $mem$$base;
2148 int index = $mem$$index;
2149 int scale = $mem$$scale;
2150 int displace = $mem$$disp;
2151 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2152 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2153 %}
2154
2155 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2156 int reg_encoding = $dst$$reg;
2157 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2158 int index = 0x04; // 0x04 indicates no index
2159 int scale = 0x00; // 0x00 indicates no scale
2160 int displace = $src1$$constant; // 0x00 indicates no displacement
2161 relocInfo::relocType disp_reloc = relocInfo::none;
2162 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2163 %}
2164
2165 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2166 // Compare dst,src
2167 emit_opcode(cbuf,0x3B);
2168 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2169 // jmp dst < src around move
2170 emit_opcode(cbuf,0x7C);
2171 emit_d8(cbuf,2);
2172 // move dst,src
2173 emit_opcode(cbuf,0x8B);
2174 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2175 %}
2176
2177 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2178 // Compare dst,src
2179 emit_opcode(cbuf,0x3B);
2180 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2181 // jmp dst > src around move
2182 emit_opcode(cbuf,0x7F);
2183 emit_d8(cbuf,2);
2184 // move dst,src
2185 emit_opcode(cbuf,0x8B);
2186 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2187 %}
2188
2189 enc_class enc_FPR_store(memory mem, regDPR src) %{
2190 // If src is FPR1, we can just FST to store it.
2191 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2192 int reg_encoding = 0x2; // Just store
2193 int base = $mem$$base;
2194 int index = $mem$$index;
2195 int scale = $mem$$scale;
2196 int displace = $mem$$disp;
2197 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2198 if( $src$$reg != FPR1L_enc ) {
2199 reg_encoding = 0x3; // Store & pop
2200 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2201 emit_d8( cbuf, 0xC0-1+$src$$reg );
2202 }
2203 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2204 emit_opcode(cbuf,$primary);
2205 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2206 %}
2207
2208 enc_class neg_reg(rRegI dst) %{
2209 // NEG $dst
2210 emit_opcode(cbuf,0xF7);
2211 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2212 %}
2213
2214 enc_class setLT_reg(eCXRegI dst) %{
2215 // SETLT $dst
2216 emit_opcode(cbuf,0x0F);
2217 emit_opcode(cbuf,0x9C);
2218 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2219 %}
2220
2221 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2222 int tmpReg = $tmp$$reg;
2223
2224 // SUB $p,$q
2225 emit_opcode(cbuf,0x2B);
2226 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2227 // SBB $tmp,$tmp
2228 emit_opcode(cbuf,0x1B);
2229 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2230 // AND $tmp,$y
2231 emit_opcode(cbuf,0x23);
2232 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2233 // ADD $p,$tmp
2234 emit_opcode(cbuf,0x03);
2235 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2236 %}
2237
2238 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2239 // TEST shift,32
2240 emit_opcode(cbuf,0xF7);
2241 emit_rm(cbuf, 0x3, 0, ECX_enc);
2242 emit_d32(cbuf,0x20);
2243 // JEQ,s small
2244 emit_opcode(cbuf, 0x74);
2245 emit_d8(cbuf, 0x04);
2246 // MOV $dst.hi,$dst.lo
2247 emit_opcode( cbuf, 0x8B );
2248 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2249 // CLR $dst.lo
2250 emit_opcode(cbuf, 0x33);
2251 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2252 // small:
2253 // SHLD $dst.hi,$dst.lo,$shift
2254 emit_opcode(cbuf,0x0F);
2255 emit_opcode(cbuf,0xA5);
2256 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2257 // SHL $dst.lo,$shift"
2258 emit_opcode(cbuf,0xD3);
2259 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2260 %}
2261
2262 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2263 // TEST shift,32
2264 emit_opcode(cbuf,0xF7);
2265 emit_rm(cbuf, 0x3, 0, ECX_enc);
2266 emit_d32(cbuf,0x20);
2267 // JEQ,s small
2268 emit_opcode(cbuf, 0x74);
2269 emit_d8(cbuf, 0x04);
2270 // MOV $dst.lo,$dst.hi
2271 emit_opcode( cbuf, 0x8B );
2272 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2273 // CLR $dst.hi
2274 emit_opcode(cbuf, 0x33);
2275 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2276 // small:
2277 // SHRD $dst.lo,$dst.hi,$shift
2278 emit_opcode(cbuf,0x0F);
2279 emit_opcode(cbuf,0xAD);
2280 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2281 // SHR $dst.hi,$shift"
2282 emit_opcode(cbuf,0xD3);
2283 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2284 %}
2285
2286 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2287 // TEST shift,32
2288 emit_opcode(cbuf,0xF7);
2289 emit_rm(cbuf, 0x3, 0, ECX_enc);
2290 emit_d32(cbuf,0x20);
2291 // JEQ,s small
2292 emit_opcode(cbuf, 0x74);
2293 emit_d8(cbuf, 0x05);
2294 // MOV $dst.lo,$dst.hi
2295 emit_opcode( cbuf, 0x8B );
2296 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2297 // SAR $dst.hi,31
2298 emit_opcode(cbuf, 0xC1);
2299 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2300 emit_d8(cbuf, 0x1F );
2301 // small:
2302 // SHRD $dst.lo,$dst.hi,$shift
2303 emit_opcode(cbuf,0x0F);
2304 emit_opcode(cbuf,0xAD);
2305 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2306 // SAR $dst.hi,$shift"
2307 emit_opcode(cbuf,0xD3);
2308 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2309 %}
2310
2311
2312 // ----------------- Encodings for floating point unit -----------------
2313 // May leave result in FPU-TOS or FPU reg depending on opcodes
2314 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2315 $$$emit8$primary;
2316 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2317 %}
2318
2319 // Pop argument in FPR0 with FSTP ST(0)
2320 enc_class PopFPU() %{
2321 emit_opcode( cbuf, 0xDD );
2322 emit_d8( cbuf, 0xD8 );
2323 %}
2324
2325 // !!!!! equivalent to Pop_Reg_F
2326 enc_class Pop_Reg_DPR( regDPR dst ) %{
2327 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2328 emit_d8( cbuf, 0xD8+$dst$$reg );
2329 %}
2330
2331 enc_class Push_Reg_DPR( regDPR dst ) %{
2332 emit_opcode( cbuf, 0xD9 );
2333 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2334 %}
2335
2336 enc_class strictfp_bias1( regDPR dst ) %{
2337 emit_opcode( cbuf, 0xDB ); // FLD m80real
2338 emit_opcode( cbuf, 0x2D );
2339 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2340 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2341 emit_opcode( cbuf, 0xC8+$dst$$reg );
2342 %}
2343
2344 enc_class strictfp_bias2( regDPR dst ) %{
2345 emit_opcode( cbuf, 0xDB ); // FLD m80real
2346 emit_opcode( cbuf, 0x2D );
2347 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2348 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2349 emit_opcode( cbuf, 0xC8+$dst$$reg );
2350 %}
2351
2352 // Special case for moving an integer register to a stack slot.
2353 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2354 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2355 %}
2356
2357 // Special case for moving a register to a stack slot.
2358 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2359 // Opcode already emitted
2360 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2361 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2362 emit_d32(cbuf, $dst$$disp); // Displacement
2363 %}
2364
2365 // Push the integer in stackSlot 'src' onto FP-stack
2366 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2367 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2368 %}
2369
2370 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2371 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2372 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2373 %}
2374
2375 // Same as Pop_Mem_F except for opcode
2376 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2377 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2378 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2379 %}
2380
2381 enc_class Pop_Reg_FPR( regFPR dst ) %{
2382 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2383 emit_d8( cbuf, 0xD8+$dst$$reg );
2384 %}
2385
2386 enc_class Push_Reg_FPR( regFPR dst ) %{
2387 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2388 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2389 %}
2390
2391 // Push FPU's float to a stack-slot, and pop FPU-stack
2392 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2393 int pop = 0x02;
2394 if ($src$$reg != FPR1L_enc) {
2395 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2396 emit_d8( cbuf, 0xC0-1+$src$$reg );
2397 pop = 0x03;
2398 }
2399 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2400 %}
2401
2402 // Push FPU's double to a stack-slot, and pop FPU-stack
2403 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2404 int pop = 0x02;
2405 if ($src$$reg != FPR1L_enc) {
2406 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2407 emit_d8( cbuf, 0xC0-1+$src$$reg );
2408 pop = 0x03;
2409 }
2410 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2411 %}
2412
2413 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2414 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2415 int pop = 0xD0 - 1; // -1 since we skip FLD
2416 if ($src$$reg != FPR1L_enc) {
2417 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2418 emit_d8( cbuf, 0xC0-1+$src$$reg );
2419 pop = 0xD8;
2420 }
2421 emit_opcode( cbuf, 0xDD );
2422 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2423 %}
2424
2425
2426 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2427 // load dst in FPR0
2428 emit_opcode( cbuf, 0xD9 );
2429 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2430 if ($src$$reg != FPR1L_enc) {
2431 // fincstp
2432 emit_opcode (cbuf, 0xD9);
2433 emit_opcode (cbuf, 0xF7);
2434 // swap src with FPR1:
2435 // FXCH FPR1 with src
2436 emit_opcode(cbuf, 0xD9);
2437 emit_d8(cbuf, 0xC8-1+$src$$reg );
2438 // fdecstp
2439 emit_opcode (cbuf, 0xD9);
2440 emit_opcode (cbuf, 0xF6);
2441 }
2442 %}
2443
2444 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2445 MacroAssembler _masm(&cbuf);
2446 __ subptr(rsp, 8);
2447 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2448 __ fld_d(Address(rsp, 0));
2449 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2450 __ fld_d(Address(rsp, 0));
2451 %}
2452
2453 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2454 MacroAssembler _masm(&cbuf);
2455 __ subptr(rsp, 4);
2456 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2457 __ fld_s(Address(rsp, 0));
2458 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2459 __ fld_s(Address(rsp, 0));
2460 %}
2461
2462 enc_class Push_ResultD(regD dst) %{
2463 MacroAssembler _masm(&cbuf);
2464 __ fstp_d(Address(rsp, 0));
2465 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2466 __ addptr(rsp, 8);
2467 %}
2468
2469 enc_class Push_ResultF(regF dst, immI d8) %{
2470 MacroAssembler _masm(&cbuf);
2471 __ fstp_s(Address(rsp, 0));
2472 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2473 __ addptr(rsp, $d8$$constant);
2474 %}
2475
2476 enc_class Push_SrcD(regD src) %{
2477 MacroAssembler _masm(&cbuf);
2478 __ subptr(rsp, 8);
2479 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2480 __ fld_d(Address(rsp, 0));
2481 %}
2482
2483 enc_class push_stack_temp_qword() %{
2484 MacroAssembler _masm(&cbuf);
2485 __ subptr(rsp, 8);
2486 %}
2487
2488 enc_class pop_stack_temp_qword() %{
2489 MacroAssembler _masm(&cbuf);
2490 __ addptr(rsp, 8);
2491 %}
2492
2493 enc_class push_xmm_to_fpr1(regD src) %{
2494 MacroAssembler _masm(&cbuf);
2495 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2496 __ fld_d(Address(rsp, 0));
2497 %}
2498
2499 enc_class Push_Result_Mod_DPR( regDPR src) %{
2500 if ($src$$reg != FPR1L_enc) {
2501 // fincstp
2502 emit_opcode (cbuf, 0xD9);
2503 emit_opcode (cbuf, 0xF7);
2504 // FXCH FPR1 with src
2505 emit_opcode(cbuf, 0xD9);
2506 emit_d8(cbuf, 0xC8-1+$src$$reg );
2507 // fdecstp
2508 emit_opcode (cbuf, 0xD9);
2509 emit_opcode (cbuf, 0xF6);
2510 }
2511 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2512 // // FSTP FPR$dst$$reg
2513 // emit_opcode( cbuf, 0xDD );
2514 // emit_d8( cbuf, 0xD8+$dst$$reg );
2515 %}
2516
2517 enc_class fnstsw_sahf_skip_parity() %{
2518 // fnstsw ax
2519 emit_opcode( cbuf, 0xDF );
2520 emit_opcode( cbuf, 0xE0 );
2521 // sahf
2522 emit_opcode( cbuf, 0x9E );
2523 // jnp ::skip
2524 emit_opcode( cbuf, 0x7B );
2525 emit_opcode( cbuf, 0x05 );
2526 %}
2527
2528 enc_class emitModDPR() %{
2529 // fprem must be iterative
2530 // :: loop
2531 // fprem
2532 emit_opcode( cbuf, 0xD9 );
2533 emit_opcode( cbuf, 0xF8 );
2534 // wait
2535 emit_opcode( cbuf, 0x9b );
2536 // fnstsw ax
2537 emit_opcode( cbuf, 0xDF );
2538 emit_opcode( cbuf, 0xE0 );
2539 // sahf
2540 emit_opcode( cbuf, 0x9E );
2541 // jp ::loop
2542 emit_opcode( cbuf, 0x0F );
2543 emit_opcode( cbuf, 0x8A );
2544 emit_opcode( cbuf, 0xF4 );
2545 emit_opcode( cbuf, 0xFF );
2546 emit_opcode( cbuf, 0xFF );
2547 emit_opcode( cbuf, 0xFF );
2548 %}
2549
2550 enc_class fpu_flags() %{
2551 // fnstsw_ax
2552 emit_opcode( cbuf, 0xDF);
2553 emit_opcode( cbuf, 0xE0);
2554 // test ax,0x0400
2555 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2556 emit_opcode( cbuf, 0xA9 );
2557 emit_d16 ( cbuf, 0x0400 );
2558 // // // This sequence works, but stalls for 12-16 cycles on PPro
2559 // // test rax,0x0400
2560 // emit_opcode( cbuf, 0xA9 );
2561 // emit_d32 ( cbuf, 0x00000400 );
2562 //
2563 // jz exit (no unordered comparison)
2564 emit_opcode( cbuf, 0x74 );
2565 emit_d8 ( cbuf, 0x02 );
2566 // mov ah,1 - treat as LT case (set carry flag)
2567 emit_opcode( cbuf, 0xB4 );
2568 emit_d8 ( cbuf, 0x01 );
2569 // sahf
2570 emit_opcode( cbuf, 0x9E);
2571 %}
2572
2573 enc_class cmpF_P6_fixup() %{
2574 // Fixup the integer flags in case comparison involved a NaN
2575 //
2576 // JNP exit (no unordered comparison, P-flag is set by NaN)
2577 emit_opcode( cbuf, 0x7B );
2578 emit_d8 ( cbuf, 0x03 );
2579 // MOV AH,1 - treat as LT case (set carry flag)
2580 emit_opcode( cbuf, 0xB4 );
2581 emit_d8 ( cbuf, 0x01 );
2582 // SAHF
2583 emit_opcode( cbuf, 0x9E);
2584 // NOP // target for branch to avoid branch to branch
2585 emit_opcode( cbuf, 0x90);
2586 %}
2587
2588 // fnstsw_ax();
2589 // sahf();
2590 // movl(dst, nan_result);
2591 // jcc(Assembler::parity, exit);
2592 // movl(dst, less_result);
2593 // jcc(Assembler::below, exit);
2594 // movl(dst, equal_result);
2595 // jcc(Assembler::equal, exit);
2596 // movl(dst, greater_result);
2597
2598 // less_result = 1;
2599 // greater_result = -1;
2600 // equal_result = 0;
2601 // nan_result = -1;
2602
2603 enc_class CmpF_Result(rRegI dst) %{
2604 // fnstsw_ax();
2605 emit_opcode( cbuf, 0xDF);
2606 emit_opcode( cbuf, 0xE0);
2607 // sahf
2608 emit_opcode( cbuf, 0x9E);
2609 // movl(dst, nan_result);
2610 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2611 emit_d32( cbuf, -1 );
2612 // jcc(Assembler::parity, exit);
2613 emit_opcode( cbuf, 0x7A );
2614 emit_d8 ( cbuf, 0x13 );
2615 // movl(dst, less_result);
2616 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2617 emit_d32( cbuf, -1 );
2618 // jcc(Assembler::below, exit);
2619 emit_opcode( cbuf, 0x72 );
2620 emit_d8 ( cbuf, 0x0C );
2621 // movl(dst, equal_result);
2622 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2623 emit_d32( cbuf, 0 );
2624 // jcc(Assembler::equal, exit);
2625 emit_opcode( cbuf, 0x74 );
2626 emit_d8 ( cbuf, 0x05 );
2627 // movl(dst, greater_result);
2628 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2629 emit_d32( cbuf, 1 );
2630 %}
2631
2632
2633 // Compare the longs and set flags
2634 // BROKEN! Do Not use as-is
2635 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2636 // CMP $src1.hi,$src2.hi
2637 emit_opcode( cbuf, 0x3B );
2638 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2639 // JNE,s done
2640 emit_opcode(cbuf,0x75);
2641 emit_d8(cbuf, 2 );
2642 // CMP $src1.lo,$src2.lo
2643 emit_opcode( cbuf, 0x3B );
2644 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2645 // done:
2646 %}
2647
2648 enc_class convert_int_long( regL dst, rRegI src ) %{
2649 // mov $dst.lo,$src
2650 int dst_encoding = $dst$$reg;
2651 int src_encoding = $src$$reg;
2652 encode_Copy( cbuf, dst_encoding , src_encoding );
2653 // mov $dst.hi,$src
2654 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2655 // sar $dst.hi,31
2656 emit_opcode( cbuf, 0xC1 );
2657 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2658 emit_d8(cbuf, 0x1F );
2659 %}
2660
2661 enc_class convert_long_double( eRegL src ) %{
2662 // push $src.hi
2663 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2664 // push $src.lo
2665 emit_opcode(cbuf, 0x50+$src$$reg );
2666 // fild 64-bits at [SP]
2667 emit_opcode(cbuf,0xdf);
2668 emit_d8(cbuf, 0x6C);
2669 emit_d8(cbuf, 0x24);
2670 emit_d8(cbuf, 0x00);
2671 // pop stack
2672 emit_opcode(cbuf, 0x83); // add SP, #8
2673 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2674 emit_d8(cbuf, 0x8);
2675 %}
2676
2677 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2678 // IMUL EDX:EAX,$src1
2679 emit_opcode( cbuf, 0xF7 );
2680 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2681 // SAR EDX,$cnt-32
2682 int shift_count = ((int)$cnt$$constant) - 32;
2683 if (shift_count > 0) {
2684 emit_opcode(cbuf, 0xC1);
2685 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2686 emit_d8(cbuf, shift_count);
2687 }
2688 %}
2689
2690 // this version doesn't have add sp, 8
2691 enc_class convert_long_double2( eRegL src ) %{
2692 // push $src.hi
2693 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2694 // push $src.lo
2695 emit_opcode(cbuf, 0x50+$src$$reg );
2696 // fild 64-bits at [SP]
2697 emit_opcode(cbuf,0xdf);
2698 emit_d8(cbuf, 0x6C);
2699 emit_d8(cbuf, 0x24);
2700 emit_d8(cbuf, 0x00);
2701 %}
2702
2703 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2704 // Basic idea: long = (long)int * (long)int
2705 // IMUL EDX:EAX, src
2706 emit_opcode( cbuf, 0xF7 );
2707 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2708 %}
2709
2710 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2711 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2712 // MUL EDX:EAX, src
2713 emit_opcode( cbuf, 0xF7 );
2714 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2715 %}
2716
2717 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2718 // Basic idea: lo(result) = lo(x_lo * y_lo)
2719 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2720 // MOV $tmp,$src.lo
2721 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2722 // IMUL $tmp,EDX
2723 emit_opcode( cbuf, 0x0F );
2724 emit_opcode( cbuf, 0xAF );
2725 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2726 // MOV EDX,$src.hi
2727 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2728 // IMUL EDX,EAX
2729 emit_opcode( cbuf, 0x0F );
2730 emit_opcode( cbuf, 0xAF );
2731 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2732 // ADD $tmp,EDX
2733 emit_opcode( cbuf, 0x03 );
2734 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2735 // MUL EDX:EAX,$src.lo
2736 emit_opcode( cbuf, 0xF7 );
2737 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2738 // ADD EDX,ESI
2739 emit_opcode( cbuf, 0x03 );
2740 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2741 %}
2742
2743 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2744 // Basic idea: lo(result) = lo(src * y_lo)
2745 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2746 // IMUL $tmp,EDX,$src
2747 emit_opcode( cbuf, 0x6B );
2748 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2749 emit_d8( cbuf, (int)$src$$constant );
2750 // MOV EDX,$src
2751 emit_opcode(cbuf, 0xB8 + EDX_enc);
2752 emit_d32( cbuf, (int)$src$$constant );
2753 // MUL EDX:EAX,EDX
2754 emit_opcode( cbuf, 0xF7 );
2755 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2756 // ADD EDX,ESI
2757 emit_opcode( cbuf, 0x03 );
2758 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2759 %}
2760
2761 enc_class long_div( eRegL src1, eRegL src2 ) %{
2762 // PUSH src1.hi
2763 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2764 // PUSH src1.lo
2765 emit_opcode(cbuf, 0x50+$src1$$reg );
2766 // PUSH src2.hi
2767 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2768 // PUSH src2.lo
2769 emit_opcode(cbuf, 0x50+$src2$$reg );
2770 // CALL directly to the runtime
2771 cbuf.set_insts_mark();
2772 emit_opcode(cbuf,0xE8); // Call into runtime
2773 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2774 // Restore stack
2775 emit_opcode(cbuf, 0x83); // add SP, #framesize
2776 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2777 emit_d8(cbuf, 4*4);
2778 %}
2779
2780 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2781 // PUSH src1.hi
2782 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2783 // PUSH src1.lo
2784 emit_opcode(cbuf, 0x50+$src1$$reg );
2785 // PUSH src2.hi
2786 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2787 // PUSH src2.lo
2788 emit_opcode(cbuf, 0x50+$src2$$reg );
2789 // CALL directly to the runtime
2790 cbuf.set_insts_mark();
2791 emit_opcode(cbuf,0xE8); // Call into runtime
2792 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2793 // Restore stack
2794 emit_opcode(cbuf, 0x83); // add SP, #framesize
2795 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2796 emit_d8(cbuf, 4*4);
2797 %}
2798
2799 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2800 // MOV $tmp,$src.lo
2801 emit_opcode(cbuf, 0x8B);
2802 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2803 // OR $tmp,$src.hi
2804 emit_opcode(cbuf, 0x0B);
2805 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2806 %}
2807
2808 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2809 // CMP $src1.lo,$src2.lo
2810 emit_opcode( cbuf, 0x3B );
2811 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2812 // JNE,s skip
2813 emit_cc(cbuf, 0x70, 0x5);
2814 emit_d8(cbuf,2);
2815 // CMP $src1.hi,$src2.hi
2816 emit_opcode( cbuf, 0x3B );
2817 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2818 %}
2819
2820 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2821 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2822 emit_opcode( cbuf, 0x3B );
2823 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2824 // MOV $tmp,$src1.hi
2825 emit_opcode( cbuf, 0x8B );
2826 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2827 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2828 emit_opcode( cbuf, 0x1B );
2829 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2830 %}
2831
2832 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2833 // XOR $tmp,$tmp
2834 emit_opcode(cbuf,0x33); // XOR
2835 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2836 // CMP $tmp,$src.lo
2837 emit_opcode( cbuf, 0x3B );
2838 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2839 // SBB $tmp,$src.hi
2840 emit_opcode( cbuf, 0x1B );
2841 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2842 %}
2843
2844 // Sniff, sniff... smells like Gnu Superoptimizer
2845 enc_class neg_long( eRegL dst ) %{
2846 emit_opcode(cbuf,0xF7); // NEG hi
2847 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2848 emit_opcode(cbuf,0xF7); // NEG lo
2849 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2850 emit_opcode(cbuf,0x83); // SBB hi,0
2851 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2852 emit_d8 (cbuf,0 );
2853 %}
2854
2855 enc_class enc_pop_rdx() %{
2856 emit_opcode(cbuf,0x5A);
2857 %}
2858
2859 enc_class enc_rethrow() %{
2860 cbuf.set_insts_mark();
2861 emit_opcode(cbuf, 0xE9); // jmp entry
2862 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
2863 runtime_call_Relocation::spec(), RELOC_IMM32 );
2864 %}
2865
2866
2867 // Convert a double to an int. Java semantics require we do complex
2868 // manglelations in the corner cases. So we set the rounding mode to
2869 // 'zero', store the darned double down as an int, and reset the
2870 // rounding mode to 'nearest'. The hardware throws an exception which
2871 // patches up the correct value directly to the stack.
2872 enc_class DPR2I_encoding( regDPR src ) %{
2873 // Flip to round-to-zero mode. We attempted to allow invalid-op
2874 // exceptions here, so that a NAN or other corner-case value will
2875 // thrown an exception (but normal values get converted at full speed).
2876 // However, I2C adapters and other float-stack manglers leave pending
2877 // invalid-op exceptions hanging. We would have to clear them before
2878 // enabling them and that is more expensive than just testing for the
2879 // invalid value Intel stores down in the corner cases.
2880 emit_opcode(cbuf,0xD9); // FLDCW trunc
2881 emit_opcode(cbuf,0x2D);
2882 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2883 // Allocate a word
2884 emit_opcode(cbuf,0x83); // SUB ESP,4
2885 emit_opcode(cbuf,0xEC);
2886 emit_d8(cbuf,0x04);
2887 // Encoding assumes a double has been pushed into FPR0.
2888 // Store down the double as an int, popping the FPU stack
2889 emit_opcode(cbuf,0xDB); // FISTP [ESP]
2890 emit_opcode(cbuf,0x1C);
2891 emit_d8(cbuf,0x24);
2892 // Restore the rounding mode; mask the exception
2893 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2894 emit_opcode(cbuf,0x2D);
2895 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2896 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2897 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2898
2899 // Load the converted int; adjust CPU stack
2900 emit_opcode(cbuf,0x58); // POP EAX
2901 emit_opcode(cbuf,0x3D); // CMP EAX,imm
2902 emit_d32 (cbuf,0x80000000); // 0x80000000
2903 emit_opcode(cbuf,0x75); // JNE around_slow_call
2904 emit_d8 (cbuf,0x07); // Size of slow_call
2905 // Push src onto stack slow-path
2906 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2907 emit_d8 (cbuf,0xC0-1+$src$$reg );
2908 // CALL directly to the runtime
2909 cbuf.set_insts_mark();
2910 emit_opcode(cbuf,0xE8); // Call into runtime
2911 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2912 // Carry on here...
2913 %}
2914
2915 enc_class DPR2L_encoding( regDPR src ) %{
2916 emit_opcode(cbuf,0xD9); // FLDCW trunc
2917 emit_opcode(cbuf,0x2D);
2918 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2919 // Allocate a word
2920 emit_opcode(cbuf,0x83); // SUB ESP,8
2921 emit_opcode(cbuf,0xEC);
2922 emit_d8(cbuf,0x08);
2923 // Encoding assumes a double has been pushed into FPR0.
2924 // Store down the double as a long, popping the FPU stack
2925 emit_opcode(cbuf,0xDF); // FISTP [ESP]
2926 emit_opcode(cbuf,0x3C);
2927 emit_d8(cbuf,0x24);
2928 // Restore the rounding mode; mask the exception
2929 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2930 emit_opcode(cbuf,0x2D);
2931 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2932 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2933 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2934
2935 // Load the converted int; adjust CPU stack
2936 emit_opcode(cbuf,0x58); // POP EAX
2937 emit_opcode(cbuf,0x5A); // POP EDX
2938 emit_opcode(cbuf,0x81); // CMP EDX,imm
2939 emit_d8 (cbuf,0xFA); // rdx
2940 emit_d32 (cbuf,0x80000000); // 0x80000000
2941 emit_opcode(cbuf,0x75); // JNE around_slow_call
2942 emit_d8 (cbuf,0x07+4); // Size of slow_call
2943 emit_opcode(cbuf,0x85); // TEST EAX,EAX
2944 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
2945 emit_opcode(cbuf,0x75); // JNE around_slow_call
2946 emit_d8 (cbuf,0x07); // Size of slow_call
2947 // Push src onto stack slow-path
2948 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2949 emit_d8 (cbuf,0xC0-1+$src$$reg );
2950 // CALL directly to the runtime
2951 cbuf.set_insts_mark();
2952 emit_opcode(cbuf,0xE8); // Call into runtime
2953 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2954 // Carry on here...
2955 %}
2956
2957 enc_class FMul_ST_reg( eRegFPR src1 ) %{
2958 // Operand was loaded from memory into fp ST (stack top)
2959 // FMUL ST,$src /* D8 C8+i */
2960 emit_opcode(cbuf, 0xD8);
2961 emit_opcode(cbuf, 0xC8 + $src1$$reg);
2962 %}
2963
2964 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
2965 // FADDP ST,src2 /* D8 C0+i */
2966 emit_opcode(cbuf, 0xD8);
2967 emit_opcode(cbuf, 0xC0 + $src2$$reg);
2968 //could use FADDP src2,fpST /* DE C0+i */
2969 %}
2970
2971 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
2972 // FADDP src2,ST /* DE C0+i */
2973 emit_opcode(cbuf, 0xDE);
2974 emit_opcode(cbuf, 0xC0 + $src2$$reg);
2975 %}
2976
2977 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
2978 // Operand has been loaded into fp ST (stack top)
2979 // FSUB ST,$src1
2980 emit_opcode(cbuf, 0xD8);
2981 emit_opcode(cbuf, 0xE0 + $src1$$reg);
2982
2983 // FDIV
2984 emit_opcode(cbuf, 0xD8);
2985 emit_opcode(cbuf, 0xF0 + $src2$$reg);
2986 %}
2987
2988 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
2989 // Operand was loaded from memory into fp ST (stack top)
2990 // FADD ST,$src /* D8 C0+i */
2991 emit_opcode(cbuf, 0xD8);
2992 emit_opcode(cbuf, 0xC0 + $src1$$reg);
2993
2994 // FMUL ST,src2 /* D8 C*+i */
2995 emit_opcode(cbuf, 0xD8);
2996 emit_opcode(cbuf, 0xC8 + $src2$$reg);
2997 %}
2998
2999
3000 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3001 // Operand was loaded from memory into fp ST (stack top)
3002 // FADD ST,$src /* D8 C0+i */
3003 emit_opcode(cbuf, 0xD8);
3004 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3005
3006 // FMULP src2,ST /* DE C8+i */
3007 emit_opcode(cbuf, 0xDE);
3008 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3009 %}
3010
3011 // Atomically load the volatile long
3012 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3013 emit_opcode(cbuf,0xDF);
3014 int rm_byte_opcode = 0x05;
3015 int base = $mem$$base;
3016 int index = $mem$$index;
3017 int scale = $mem$$scale;
3018 int displace = $mem$$disp;
3019 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3020 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3021 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3022 %}
3023
3024 // Volatile Store Long. Must be atomic, so move it into
3025 // the FP TOS and then do a 64-bit FIST. Has to probe the
3026 // target address before the store (for null-ptr checks)
3027 // so the memory operand is used twice in the encoding.
3028 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3029 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3030 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3031 emit_opcode(cbuf,0xDF);
3032 int rm_byte_opcode = 0x07;
3033 int base = $mem$$base;
3034 int index = $mem$$index;
3035 int scale = $mem$$scale;
3036 int displace = $mem$$disp;
3037 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3038 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3039 %}
3040
3041 // Safepoint Poll. This polls the safepoint page, and causes an
3042 // exception if it is not readable. Unfortunately, it kills the condition code
3043 // in the process
3044 // We current use TESTL [spp],EDI
3045 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3046
3047 enc_class Safepoint_Poll() %{
3048 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3049 emit_opcode(cbuf,0x85);
3050 emit_rm (cbuf, 0x0, 0x7, 0x5);
3051 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3052 %}
3053 %}
3054
3055
3056 //----------FRAME--------------------------------------------------------------
3057 // Definition of frame structure and management information.
3058 //
3059 // S T A C K L A Y O U T Allocators stack-slot number
3060 // | (to get allocators register number
3061 // G Owned by | | v add OptoReg::stack0())
3062 // r CALLER | |
3063 // o | +--------+ pad to even-align allocators stack-slot
3064 // w V | pad0 | numbers; owned by CALLER
3065 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3066 // h ^ | in | 5
3067 // | | args | 4 Holes in incoming args owned by SELF
3068 // | | | | 3
3069 // | | +--------+
3070 // V | | old out| Empty on Intel, window on Sparc
3071 // | old |preserve| Must be even aligned.
3072 // | SP-+--------+----> Matcher::_old_SP, even aligned
3073 // | | in | 3 area for Intel ret address
3074 // Owned by |preserve| Empty on Sparc.
3075 // SELF +--------+
3076 // | | pad2 | 2 pad to align old SP
3077 // | +--------+ 1
3078 // | | locks | 0
3079 // | +--------+----> OptoReg::stack0(), even aligned
3080 // | | pad1 | 11 pad to align new SP
3081 // | +--------+
3082 // | | | 10
3083 // | | spills | 9 spills
3084 // V | | 8 (pad0 slot for callee)
3085 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3086 // ^ | out | 7
3087 // | | args | 6 Holes in outgoing args owned by CALLEE
3088 // Owned by +--------+
3089 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3090 // | new |preserve| Must be even-aligned.
3091 // | SP-+--------+----> Matcher::_new_SP, even aligned
3092 // | | |
3093 //
3094 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3095 // known from SELF's arguments and the Java calling convention.
3096 // Region 6-7 is determined per call site.
3097 // Note 2: If the calling convention leaves holes in the incoming argument
3098 // area, those holes are owned by SELF. Holes in the outgoing area
3099 // are owned by the CALLEE. Holes should not be nessecary in the
3100 // incoming area, as the Java calling convention is completely under
3101 // the control of the AD file. Doubles can be sorted and packed to
3102 // avoid holes. Holes in the outgoing arguments may be nessecary for
3103 // varargs C calling conventions.
3104 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3105 // even aligned with pad0 as needed.
3106 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3107 // region 6-11 is even aligned; it may be padded out more so that
3108 // the region from SP to FP meets the minimum stack alignment.
3109
3110 frame %{
3111 // What direction does stack grow in (assumed to be same for C & Java)
3112 stack_direction(TOWARDS_LOW);
3113
3114 // These three registers define part of the calling convention
3115 // between compiled code and the interpreter.
3116 inline_cache_reg(EAX); // Inline Cache Register
3117 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3118
3119 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3120 cisc_spilling_operand_name(indOffset32);
3121
3122 // Number of stack slots consumed by locking an object
3123 sync_stack_slots(1);
3124
3125 // Compiled code's Frame Pointer
3126 frame_pointer(ESP);
3127 // Interpreter stores its frame pointer in a register which is
3128 // stored to the stack by I2CAdaptors.
3129 // I2CAdaptors convert from interpreted java to compiled java.
3130 interpreter_frame_pointer(EBP);
3131
3132 // Stack alignment requirement
3133 // Alignment size in bytes (128-bit -> 16 bytes)
3134 stack_alignment(StackAlignmentInBytes);
3135
3136 // Number of stack slots between incoming argument block and the start of
3137 // a new frame. The PROLOG must add this many slots to the stack. The
3138 // EPILOG must remove this many slots. Intel needs one slot for
3139 // return address and one for rbp, (must save rbp)
3140 in_preserve_stack_slots(2+VerifyStackAtCalls);
3141
3142 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3143 // for calls to C. Supports the var-args backing area for register parms.
3144 varargs_C_out_slots_killed(0);
3145
3146 // The after-PROLOG location of the return address. Location of
3147 // return address specifies a type (REG or STACK) and a number
3148 // representing the register number (i.e. - use a register name) or
3149 // stack slot.
3150 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3151 // Otherwise, it is above the locks and verification slot and alignment word
3152 return_addr(STACK - 1 +
3153 round_to((Compile::current()->in_preserve_stack_slots() +
3154 Compile::current()->fixed_slots()),
3155 stack_alignment_in_slots()));
3156
3157 // Body of function which returns an integer array locating
3158 // arguments either in registers or in stack slots. Passed an array
3159 // of ideal registers called "sig" and a "length" count. Stack-slot
3160 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3161 // arguments for a CALLEE. Incoming stack arguments are
3162 // automatically biased by the preserve_stack_slots field above.
3163 calling_convention %{
3164 // No difference between ingoing/outgoing just pass false
3165 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3166 %}
3167
3168
3169 // Body of function which returns an integer array locating
3170 // arguments either in registers or in stack slots. Passed an array
3171 // of ideal registers called "sig" and a "length" count. Stack-slot
3172 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3173 // arguments for a CALLEE. Incoming stack arguments are
3174 // automatically biased by the preserve_stack_slots field above.
3175 c_calling_convention %{
3176 // This is obviously always outgoing
3177 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3178 %}
3179
3180 // Location of C & interpreter return values
3181 c_return_value %{
3182 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3183 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3184 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3185
3186 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3187 // that C functions return float and double results in XMM0.
3188 if( ideal_reg == Op_RegD && UseSSE>=2 )
3189 return OptoRegPair(XMM0b_num,XMM0_num);
3190 if( ideal_reg == Op_RegF && UseSSE>=2 )
3191 return OptoRegPair(OptoReg::Bad,XMM0_num);
3192
3193 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3194 %}
3195
3196 // Location of return values
3197 return_value %{
3198 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3199 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3200 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3201 if( ideal_reg == Op_RegD && UseSSE>=2 )
3202 return OptoRegPair(XMM0b_num,XMM0_num);
3203 if( ideal_reg == Op_RegF && UseSSE>=1 )
3204 return OptoRegPair(OptoReg::Bad,XMM0_num);
3205 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3206 %}
3207
3208 %}
3209
3210 //----------ATTRIBUTES---------------------------------------------------------
3211 //----------Operand Attributes-------------------------------------------------
3212 op_attrib op_cost(0); // Required cost attribute
3213
3214 //----------Instruction Attributes---------------------------------------------
3215 ins_attrib ins_cost(100); // Required cost attribute
3216 ins_attrib ins_size(8); // Required size attribute (in bits)
3217 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3218 // non-matching short branch variant of some
3219 // long branch?
3220 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3221 // specifies the alignment that some part of the instruction (not
3222 // necessarily the start) requires. If > 1, a compute_padding()
3223 // function must be provided for the instruction
3224
3225 //----------OPERANDS-----------------------------------------------------------
3226 // Operand definitions must precede instruction definitions for correct parsing
3227 // in the ADLC because operands constitute user defined types which are used in
3228 // instruction definitions.
3229
3230 //----------Simple Operands----------------------------------------------------
3231 // Immediate Operands
3232 // Integer Immediate
3233 operand immI() %{
3234 match(ConI);
3235
3236 op_cost(10);
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Constant for test vs zero
3242 operand immI0() %{
3243 predicate(n->get_int() == 0);
3244 match(ConI);
3245
3246 op_cost(0);
3247 format %{ %}
3248 interface(CONST_INTER);
3249 %}
3250
3251 // Constant for increment
3252 operand immI1() %{
3253 predicate(n->get_int() == 1);
3254 match(ConI);
3255
3256 op_cost(0);
3257 format %{ %}
3258 interface(CONST_INTER);
3259 %}
3260
3261 // Constant for decrement
3262 operand immI_M1() %{
3263 predicate(n->get_int() == -1);
3264 match(ConI);
3265
3266 op_cost(0);
3267 format %{ %}
3268 interface(CONST_INTER);
3269 %}
3270
3271 // Valid scale values for addressing modes
3272 operand immI2() %{
3273 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3274 match(ConI);
3275
3276 format %{ %}
3277 interface(CONST_INTER);
3278 %}
3279
3280 operand immI8() %{
3281 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3282 match(ConI);
3283
3284 op_cost(5);
3285 format %{ %}
3286 interface(CONST_INTER);
3287 %}
3288
3289 operand immI16() %{
3290 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3291 match(ConI);
3292
3293 op_cost(10);
3294 format %{ %}
3295 interface(CONST_INTER);
3296 %}
3297
3298 // Int Immediate non-negative
3299 operand immU31()
3300 %{
3301 predicate(n->get_int() >= 0);
3302 match(ConI);
3303
3304 op_cost(0);
3305 format %{ %}
3306 interface(CONST_INTER);
3307 %}
3308
3309 // Constant for long shifts
3310 operand immI_32() %{
3311 predicate( n->get_int() == 32 );
3312 match(ConI);
3313
3314 op_cost(0);
3315 format %{ %}
3316 interface(CONST_INTER);
3317 %}
3318
3319 operand immI_1_31() %{
3320 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3321 match(ConI);
3322
3323 op_cost(0);
3324 format %{ %}
3325 interface(CONST_INTER);
3326 %}
3327
3328 operand immI_32_63() %{
3329 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3330 match(ConI);
3331 op_cost(0);
3332
3333 format %{ %}
3334 interface(CONST_INTER);
3335 %}
3336
3337 operand immI_1() %{
3338 predicate( n->get_int() == 1 );
3339 match(ConI);
3340
3341 op_cost(0);
3342 format %{ %}
3343 interface(CONST_INTER);
3344 %}
3345
3346 operand immI_2() %{
3347 predicate( n->get_int() == 2 );
3348 match(ConI);
3349
3350 op_cost(0);
3351 format %{ %}
3352 interface(CONST_INTER);
3353 %}
3354
3355 operand immI_3() %{
3356 predicate( n->get_int() == 3 );
3357 match(ConI);
3358
3359 op_cost(0);
3360 format %{ %}
3361 interface(CONST_INTER);
3362 %}
3363
3364 // Pointer Immediate
3365 operand immP() %{
3366 match(ConP);
3367
3368 op_cost(10);
3369 format %{ %}
3370 interface(CONST_INTER);
3371 %}
3372
3373 // NULL Pointer Immediate
3374 operand immP0() %{
3375 predicate( n->get_ptr() == 0 );
3376 match(ConP);
3377 op_cost(0);
3378
3379 format %{ %}
3380 interface(CONST_INTER);
3381 %}
3382
3383 // Long Immediate
3384 operand immL() %{
3385 match(ConL);
3386
3387 op_cost(20);
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 // Long Immediate zero
3393 operand immL0() %{
3394 predicate( n->get_long() == 0L );
3395 match(ConL);
3396 op_cost(0);
3397
3398 format %{ %}
3399 interface(CONST_INTER);
3400 %}
3401
3402 // Long Immediate zero
3403 operand immL_M1() %{
3404 predicate( n->get_long() == -1L );
3405 match(ConL);
3406 op_cost(0);
3407
3408 format %{ %}
3409 interface(CONST_INTER);
3410 %}
3411
3412 // Long immediate from 0 to 127.
3413 // Used for a shorter form of long mul by 10.
3414 operand immL_127() %{
3415 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3416 match(ConL);
3417 op_cost(0);
3418
3419 format %{ %}
3420 interface(CONST_INTER);
3421 %}
3422
3423 // Long Immediate: low 32-bit mask
3424 operand immL_32bits() %{
3425 predicate(n->get_long() == 0xFFFFFFFFL);
3426 match(ConL);
3427 op_cost(0);
3428
3429 format %{ %}
3430 interface(CONST_INTER);
3431 %}
3432
3433 // Long Immediate: low 32-bit mask
3434 operand immL32() %{
3435 predicate(n->get_long() == (int)(n->get_long()));
3436 match(ConL);
3437 op_cost(20);
3438
3439 format %{ %}
3440 interface(CONST_INTER);
3441 %}
3442
3443 //Double Immediate zero
3444 operand immDPR0() %{
3445 // Do additional (and counter-intuitive) test against NaN to work around VC++
3446 // bug that generates code such that NaNs compare equal to 0.0
3447 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
3448 match(ConD);
3449
3450 op_cost(5);
3451 format %{ %}
3452 interface(CONST_INTER);
3453 %}
3454
3455 // Double Immediate one
3456 operand immDPR1() %{
3457 predicate( UseSSE<=1 && n->getd() == 1.0 );
3458 match(ConD);
3459
3460 op_cost(5);
3461 format %{ %}
3462 interface(CONST_INTER);
3463 %}
3464
3465 // Double Immediate
3466 operand immDPR() %{
3467 predicate(UseSSE<=1);
3468 match(ConD);
3469
3470 op_cost(5);
3471 format %{ %}
3472 interface(CONST_INTER);
3473 %}
3474
3475 operand immD() %{
3476 predicate(UseSSE>=2);
3477 match(ConD);
3478
3479 op_cost(5);
3480 format %{ %}
3481 interface(CONST_INTER);
3482 %}
3483
3484 // Double Immediate zero
3485 operand immD0() %{
3486 // Do additional (and counter-intuitive) test against NaN to work around VC++
3487 // bug that generates code such that NaNs compare equal to 0.0 AND do not
3488 // compare equal to -0.0.
3489 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
3490 match(ConD);
3491
3492 format %{ %}
3493 interface(CONST_INTER);
3494 %}
3495
3496 // Float Immediate zero
3497 operand immFPR0() %{
3498 predicate(UseSSE == 0 && n->getf() == 0.0F);
3499 match(ConF);
3500
3501 op_cost(5);
3502 format %{ %}
3503 interface(CONST_INTER);
3504 %}
3505
3506 // Float Immediate one
3507 operand immFPR1() %{
3508 predicate(UseSSE == 0 && n->getf() == 1.0F);
3509 match(ConF);
3510
3511 op_cost(5);
3512 format %{ %}
3513 interface(CONST_INTER);
3514 %}
3515
3516 // Float Immediate
3517 operand immFPR() %{
3518 predicate( UseSSE == 0 );
3519 match(ConF);
3520
3521 op_cost(5);
3522 format %{ %}
3523 interface(CONST_INTER);
3524 %}
3525
3526 // Float Immediate
3527 operand immF() %{
3528 predicate(UseSSE >= 1);
3529 match(ConF);
3530
3531 op_cost(5);
3532 format %{ %}
3533 interface(CONST_INTER);
3534 %}
3535
3536 // Float Immediate zero. Zero and not -0.0
3537 operand immF0() %{
3538 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
3539 match(ConF);
3540
3541 op_cost(5);
3542 format %{ %}
3543 interface(CONST_INTER);
3544 %}
3545
3546 // Immediates for special shifts (sign extend)
3547
3548 // Constants for increment
3549 operand immI_16() %{
3550 predicate( n->get_int() == 16 );
3551 match(ConI);
3552
3553 format %{ %}
3554 interface(CONST_INTER);
3555 %}
3556
3557 operand immI_24() %{
3558 predicate( n->get_int() == 24 );
3559 match(ConI);
3560
3561 format %{ %}
3562 interface(CONST_INTER);
3563 %}
3564
3565 // Constant for byte-wide masking
3566 operand immI_255() %{
3567 predicate( n->get_int() == 255 );
3568 match(ConI);
3569
3570 format %{ %}
3571 interface(CONST_INTER);
3572 %}
3573
3574 // Constant for short-wide masking
3575 operand immI_65535() %{
3576 predicate(n->get_int() == 65535);
3577 match(ConI);
3578
3579 format %{ %}
3580 interface(CONST_INTER);
3581 %}
3582
3583 // Register Operands
3584 // Integer Register
3585 operand rRegI() %{
3586 constraint(ALLOC_IN_RC(int_reg));
3587 match(RegI);
3588 match(xRegI);
3589 match(eAXRegI);
3590 match(eBXRegI);
3591 match(eCXRegI);
3592 match(eDXRegI);
3593 match(eDIRegI);
3594 match(eSIRegI);
3595
3596 format %{ %}
3597 interface(REG_INTER);
3598 %}
3599
3600 // Subset of Integer Register
3601 operand xRegI(rRegI reg) %{
3602 constraint(ALLOC_IN_RC(int_x_reg));
3603 match(reg);
3604 match(eAXRegI);
3605 match(eBXRegI);
3606 match(eCXRegI);
3607 match(eDXRegI);
3608
3609 format %{ %}
3610 interface(REG_INTER);
3611 %}
3612
3613 // Special Registers
3614 operand eAXRegI(xRegI reg) %{
3615 constraint(ALLOC_IN_RC(eax_reg));
3616 match(reg);
3617 match(rRegI);
3618
3619 format %{ "EAX" %}
3620 interface(REG_INTER);
3621 %}
3622
3623 // Special Registers
3624 operand eBXRegI(xRegI reg) %{
3625 constraint(ALLOC_IN_RC(ebx_reg));
3626 match(reg);
3627 match(rRegI);
3628
3629 format %{ "EBX" %}
3630 interface(REG_INTER);
3631 %}
3632
3633 operand eCXRegI(xRegI reg) %{
3634 constraint(ALLOC_IN_RC(ecx_reg));
3635 match(reg);
3636 match(rRegI);
3637
3638 format %{ "ECX" %}
3639 interface(REG_INTER);
3640 %}
3641
3642 operand eDXRegI(xRegI reg) %{
3643 constraint(ALLOC_IN_RC(edx_reg));
3644 match(reg);
3645 match(rRegI);
3646
3647 format %{ "EDX" %}
3648 interface(REG_INTER);
3649 %}
3650
3651 operand eDIRegI(xRegI reg) %{
3652 constraint(ALLOC_IN_RC(edi_reg));
3653 match(reg);
3654 match(rRegI);
3655
3656 format %{ "EDI" %}
3657 interface(REG_INTER);
3658 %}
3659
3660 operand naxRegI() %{
3661 constraint(ALLOC_IN_RC(nax_reg));
3662 match(RegI);
3663 match(eCXRegI);
3664 match(eDXRegI);
3665 match(eSIRegI);
3666 match(eDIRegI);
3667
3668 format %{ %}
3669 interface(REG_INTER);
3670 %}
3671
3672 operand nadxRegI() %{
3673 constraint(ALLOC_IN_RC(nadx_reg));
3674 match(RegI);
3675 match(eBXRegI);
3676 match(eCXRegI);
3677 match(eSIRegI);
3678 match(eDIRegI);
3679
3680 format %{ %}
3681 interface(REG_INTER);
3682 %}
3683
3684 operand ncxRegI() %{
3685 constraint(ALLOC_IN_RC(ncx_reg));
3686 match(RegI);
3687 match(eAXRegI);
3688 match(eDXRegI);
3689 match(eSIRegI);
3690 match(eDIRegI);
3691
3692 format %{ %}
3693 interface(REG_INTER);
3694 %}
3695
3696 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
3697 // //
3698 operand eSIRegI(xRegI reg) %{
3699 constraint(ALLOC_IN_RC(esi_reg));
3700 match(reg);
3701 match(rRegI);
3702
3703 format %{ "ESI" %}
3704 interface(REG_INTER);
3705 %}
3706
3707 // Pointer Register
3708 operand anyRegP() %{
3709 constraint(ALLOC_IN_RC(any_reg));
3710 match(RegP);
3711 match(eAXRegP);
3712 match(eBXRegP);
3713 match(eCXRegP);
3714 match(eDIRegP);
3715 match(eRegP);
3716
3717 format %{ %}
3718 interface(REG_INTER);
3719 %}
3720
3721 operand eRegP() %{
3722 constraint(ALLOC_IN_RC(int_reg));
3723 match(RegP);
3724 match(eAXRegP);
3725 match(eBXRegP);
3726 match(eCXRegP);
3727 match(eDIRegP);
3728
3729 format %{ %}
3730 interface(REG_INTER);
3731 %}
3732
3733 // On windows95, EBP is not safe to use for implicit null tests.
3734 operand eRegP_no_EBP() %{
3735 constraint(ALLOC_IN_RC(int_reg_no_rbp));
3736 match(RegP);
3737 match(eAXRegP);
3738 match(eBXRegP);
3739 match(eCXRegP);
3740 match(eDIRegP);
3741
3742 op_cost(100);
3743 format %{ %}
3744 interface(REG_INTER);
3745 %}
3746
3747 operand naxRegP() %{
3748 constraint(ALLOC_IN_RC(nax_reg));
3749 match(RegP);
3750 match(eBXRegP);
3751 match(eDXRegP);
3752 match(eCXRegP);
3753 match(eSIRegP);
3754 match(eDIRegP);
3755
3756 format %{ %}
3757 interface(REG_INTER);
3758 %}
3759
3760 operand nabxRegP() %{
3761 constraint(ALLOC_IN_RC(nabx_reg));
3762 match(RegP);
3763 match(eCXRegP);
3764 match(eDXRegP);
3765 match(eSIRegP);
3766 match(eDIRegP);
3767
3768 format %{ %}
3769 interface(REG_INTER);
3770 %}
3771
3772 operand pRegP() %{
3773 constraint(ALLOC_IN_RC(p_reg));
3774 match(RegP);
3775 match(eBXRegP);
3776 match(eDXRegP);
3777 match(eSIRegP);
3778 match(eDIRegP);
3779
3780 format %{ %}
3781 interface(REG_INTER);
3782 %}
3783
3784 // Special Registers
3785 // Return a pointer value
3786 operand eAXRegP(eRegP reg) %{
3787 constraint(ALLOC_IN_RC(eax_reg));
3788 match(reg);
3789 format %{ "EAX" %}
3790 interface(REG_INTER);
3791 %}
3792
3793 // Used in AtomicAdd
3794 operand eBXRegP(eRegP reg) %{
3795 constraint(ALLOC_IN_RC(ebx_reg));
3796 match(reg);
3797 format %{ "EBX" %}
3798 interface(REG_INTER);
3799 %}
3800
3801 // Tail-call (interprocedural jump) to interpreter
3802 operand eCXRegP(eRegP reg) %{
3803 constraint(ALLOC_IN_RC(ecx_reg));
3804 match(reg);
3805 format %{ "ECX" %}
3806 interface(REG_INTER);
3807 %}
3808
3809 operand eSIRegP(eRegP reg) %{
3810 constraint(ALLOC_IN_RC(esi_reg));
3811 match(reg);
3812 format %{ "ESI" %}
3813 interface(REG_INTER);
3814 %}
3815
3816 // Used in rep stosw
3817 operand eDIRegP(eRegP reg) %{
3818 constraint(ALLOC_IN_RC(edi_reg));
3819 match(reg);
3820 format %{ "EDI" %}
3821 interface(REG_INTER);
3822 %}
3823
3824 operand eBPRegP() %{
3825 constraint(ALLOC_IN_RC(ebp_reg));
3826 match(RegP);
3827 format %{ "EBP" %}
3828 interface(REG_INTER);
3829 %}
3830
3831 operand eRegL() %{
3832 constraint(ALLOC_IN_RC(long_reg));
3833 match(RegL);
3834 match(eADXRegL);
3835
3836 format %{ %}
3837 interface(REG_INTER);
3838 %}
3839
3840 operand eADXRegL( eRegL reg ) %{
3841 constraint(ALLOC_IN_RC(eadx_reg));
3842 match(reg);
3843
3844 format %{ "EDX:EAX" %}
3845 interface(REG_INTER);
3846 %}
3847
3848 operand eBCXRegL( eRegL reg ) %{
3849 constraint(ALLOC_IN_RC(ebcx_reg));
3850 match(reg);
3851
3852 format %{ "EBX:ECX" %}
3853 interface(REG_INTER);
3854 %}
3855
3856 // Special case for integer high multiply
3857 operand eADXRegL_low_only() %{
3858 constraint(ALLOC_IN_RC(eadx_reg));
3859 match(RegL);
3860
3861 format %{ "EAX" %}
3862 interface(REG_INTER);
3863 %}
3864
3865 // Flags register, used as output of compare instructions
3866 operand eFlagsReg() %{
3867 constraint(ALLOC_IN_RC(int_flags));
3868 match(RegFlags);
3869
3870 format %{ "EFLAGS" %}
3871 interface(REG_INTER);
3872 %}
3873
3874 // Flags register, used as output of FLOATING POINT compare instructions
3875 operand eFlagsRegU() %{
3876 constraint(ALLOC_IN_RC(int_flags));
3877 match(RegFlags);
3878
3879 format %{ "EFLAGS_U" %}
3880 interface(REG_INTER);
3881 %}
3882
3883 operand eFlagsRegUCF() %{
3884 constraint(ALLOC_IN_RC(int_flags));
3885 match(RegFlags);
3886 predicate(false);
3887
3888 format %{ "EFLAGS_U_CF" %}
3889 interface(REG_INTER);
3890 %}
3891
3892 // Condition Code Register used by long compare
3893 operand flagsReg_long_LTGE() %{
3894 constraint(ALLOC_IN_RC(int_flags));
3895 match(RegFlags);
3896 format %{ "FLAGS_LTGE" %}
3897 interface(REG_INTER);
3898 %}
3899 operand flagsReg_long_EQNE() %{
3900 constraint(ALLOC_IN_RC(int_flags));
3901 match(RegFlags);
3902 format %{ "FLAGS_EQNE" %}
3903 interface(REG_INTER);
3904 %}
3905 operand flagsReg_long_LEGT() %{
3906 constraint(ALLOC_IN_RC(int_flags));
3907 match(RegFlags);
3908 format %{ "FLAGS_LEGT" %}
3909 interface(REG_INTER);
3910 %}
3911
3912 // Float register operands
3913 operand regDPR() %{
3914 predicate( UseSSE < 2 );
3915 constraint(ALLOC_IN_RC(fp_dbl_reg));
3916 match(RegD);
3917 match(regDPR1);
3918 match(regDPR2);
3919 format %{ %}
3920 interface(REG_INTER);
3921 %}
3922
3923 operand regDPR1(regDPR reg) %{
3924 predicate( UseSSE < 2 );
3925 constraint(ALLOC_IN_RC(fp_dbl_reg0));
3926 match(reg);
3927 format %{ "FPR1" %}
3928 interface(REG_INTER);
3929 %}
3930
3931 operand regDPR2(regDPR reg) %{
3932 predicate( UseSSE < 2 );
3933 constraint(ALLOC_IN_RC(fp_dbl_reg1));
3934 match(reg);
3935 format %{ "FPR2" %}
3936 interface(REG_INTER);
3937 %}
3938
3939 operand regnotDPR1(regDPR reg) %{
3940 predicate( UseSSE < 2 );
3941 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
3942 match(reg);
3943 format %{ %}
3944 interface(REG_INTER);
3945 %}
3946
3947 // Float register operands
3948 operand regFPR() %{
3949 predicate( UseSSE < 2 );
3950 constraint(ALLOC_IN_RC(fp_flt_reg));
3951 match(RegF);
3952 match(regFPR1);
3953 format %{ %}
3954 interface(REG_INTER);
3955 %}
3956
3957 // Float register operands
3958 operand regFPR1(regFPR reg) %{
3959 predicate( UseSSE < 2 );
3960 constraint(ALLOC_IN_RC(fp_flt_reg0));
3961 match(reg);
3962 format %{ "FPR1" %}
3963 interface(REG_INTER);
3964 %}
3965
3966 // XMM Float register operands
3967 operand regF() %{
3968 predicate( UseSSE>=1 );
3969 constraint(ALLOC_IN_RC(float_reg));
3970 match(RegF);
3971 format %{ %}
3972 interface(REG_INTER);
3973 %}
3974
3975 // XMM Double register operands
3976 operand regD() %{
3977 predicate( UseSSE>=2 );
3978 constraint(ALLOC_IN_RC(double_reg));
3979 match(RegD);
3980 format %{ %}
3981 interface(REG_INTER);
3982 %}
3983
3984
3985 //----------Memory Operands----------------------------------------------------
3986 // Direct Memory Operand
3987 operand direct(immP addr) %{
3988 match(addr);
3989
3990 format %{ "[$addr]" %}
3991 interface(MEMORY_INTER) %{
3992 base(0xFFFFFFFF);
3993 index(0x4);
3994 scale(0x0);
3995 disp($addr);
3996 %}
3997 %}
3998
3999 // Indirect Memory Operand
4000 operand indirect(eRegP reg) %{
4001 constraint(ALLOC_IN_RC(int_reg));
4002 match(reg);
4003
4004 format %{ "[$reg]" %}
4005 interface(MEMORY_INTER) %{
4006 base($reg);
4007 index(0x4);
4008 scale(0x0);
4009 disp(0x0);
4010 %}
4011 %}
4012
4013 // Indirect Memory Plus Short Offset Operand
4014 operand indOffset8(eRegP reg, immI8 off) %{
4015 match(AddP reg off);
4016
4017 format %{ "[$reg + $off]" %}
4018 interface(MEMORY_INTER) %{
4019 base($reg);
4020 index(0x4);
4021 scale(0x0);
4022 disp($off);
4023 %}
4024 %}
4025
4026 // Indirect Memory Plus Long Offset Operand
4027 operand indOffset32(eRegP reg, immI off) %{
4028 match(AddP reg off);
4029
4030 format %{ "[$reg + $off]" %}
4031 interface(MEMORY_INTER) %{
4032 base($reg);
4033 index(0x4);
4034 scale(0x0);
4035 disp($off);
4036 %}
4037 %}
4038
4039 // Indirect Memory Plus Long Offset Operand
4040 operand indOffset32X(rRegI reg, immP off) %{
4041 match(AddP off reg);
4042
4043 format %{ "[$reg + $off]" %}
4044 interface(MEMORY_INTER) %{
4045 base($reg);
4046 index(0x4);
4047 scale(0x0);
4048 disp($off);
4049 %}
4050 %}
4051
4052 // Indirect Memory Plus Index Register Plus Offset Operand
4053 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4054 match(AddP (AddP reg ireg) off);
4055
4056 op_cost(10);
4057 format %{"[$reg + $off + $ireg]" %}
4058 interface(MEMORY_INTER) %{
4059 base($reg);
4060 index($ireg);
4061 scale(0x0);
4062 disp($off);
4063 %}
4064 %}
4065
4066 // Indirect Memory Plus Index Register Plus Offset Operand
4067 operand indIndex(eRegP reg, rRegI ireg) %{
4068 match(AddP reg ireg);
4069
4070 op_cost(10);
4071 format %{"[$reg + $ireg]" %}
4072 interface(MEMORY_INTER) %{
4073 base($reg);
4074 index($ireg);
4075 scale(0x0);
4076 disp(0x0);
4077 %}
4078 %}
4079
4080 // // -------------------------------------------------------------------------
4081 // // 486 architecture doesn't support "scale * index + offset" with out a base
4082 // // -------------------------------------------------------------------------
4083 // // Scaled Memory Operands
4084 // // Indirect Memory Times Scale Plus Offset Operand
4085 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4086 // match(AddP off (LShiftI ireg scale));
4087 //
4088 // op_cost(10);
4089 // format %{"[$off + $ireg << $scale]" %}
4090 // interface(MEMORY_INTER) %{
4091 // base(0x4);
4092 // index($ireg);
4093 // scale($scale);
4094 // disp($off);
4095 // %}
4096 // %}
4097
4098 // Indirect Memory Times Scale Plus Index Register
4099 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4100 match(AddP reg (LShiftI ireg scale));
4101
4102 op_cost(10);
4103 format %{"[$reg + $ireg << $scale]" %}
4104 interface(MEMORY_INTER) %{
4105 base($reg);
4106 index($ireg);
4107 scale($scale);
4108 disp(0x0);
4109 %}
4110 %}
4111
4112 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4113 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4114 match(AddP (AddP reg (LShiftI ireg scale)) off);
4115
4116 op_cost(10);
4117 format %{"[$reg + $off + $ireg << $scale]" %}
4118 interface(MEMORY_INTER) %{
4119 base($reg);
4120 index($ireg);
4121 scale($scale);
4122 disp($off);
4123 %}
4124 %}
4125
4126 //----------Load Long Memory Operands------------------------------------------
4127 // The load-long idiom will use it's address expression again after loading
4128 // the first word of the long. If the load-long destination overlaps with
4129 // registers used in the addressing expression, the 2nd half will be loaded
4130 // from a clobbered address. Fix this by requiring that load-long use
4131 // address registers that do not overlap with the load-long target.
4132
4133 // load-long support
4134 operand load_long_RegP() %{
4135 constraint(ALLOC_IN_RC(esi_reg));
4136 match(RegP);
4137 match(eSIRegP);
4138 op_cost(100);
4139 format %{ %}
4140 interface(REG_INTER);
4141 %}
4142
4143 // Indirect Memory Operand Long
4144 operand load_long_indirect(load_long_RegP reg) %{
4145 constraint(ALLOC_IN_RC(esi_reg));
4146 match(reg);
4147
4148 format %{ "[$reg]" %}
4149 interface(MEMORY_INTER) %{
4150 base($reg);
4151 index(0x4);
4152 scale(0x0);
4153 disp(0x0);
4154 %}
4155 %}
4156
4157 // Indirect Memory Plus Long Offset Operand
4158 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4159 match(AddP reg off);
4160
4161 format %{ "[$reg + $off]" %}
4162 interface(MEMORY_INTER) %{
4163 base($reg);
4164 index(0x4);
4165 scale(0x0);
4166 disp($off);
4167 %}
4168 %}
4169
4170 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4171
4172
4173 //----------Special Memory Operands--------------------------------------------
4174 // Stack Slot Operand - This operand is used for loading and storing temporary
4175 // values on the stack where a match requires a value to
4176 // flow through memory.
4177 operand stackSlotP(sRegP reg) %{
4178 constraint(ALLOC_IN_RC(stack_slots));
4179 // No match rule because this operand is only generated in matching
4180 format %{ "[$reg]" %}
4181 interface(MEMORY_INTER) %{
4182 base(0x4); // ESP
4183 index(0x4); // No Index
4184 scale(0x0); // No Scale
4185 disp($reg); // Stack Offset
4186 %}
4187 %}
4188
4189 operand stackSlotI(sRegI reg) %{
4190 constraint(ALLOC_IN_RC(stack_slots));
4191 // No match rule because this operand is only generated in matching
4192 format %{ "[$reg]" %}
4193 interface(MEMORY_INTER) %{
4194 base(0x4); // ESP
4195 index(0x4); // No Index
4196 scale(0x0); // No Scale
4197 disp($reg); // Stack Offset
4198 %}
4199 %}
4200
4201 operand stackSlotF(sRegF reg) %{
4202 constraint(ALLOC_IN_RC(stack_slots));
4203 // No match rule because this operand is only generated in matching
4204 format %{ "[$reg]" %}
4205 interface(MEMORY_INTER) %{
4206 base(0x4); // ESP
4207 index(0x4); // No Index
4208 scale(0x0); // No Scale
4209 disp($reg); // Stack Offset
4210 %}
4211 %}
4212
4213 operand stackSlotD(sRegD reg) %{
4214 constraint(ALLOC_IN_RC(stack_slots));
4215 // No match rule because this operand is only generated in matching
4216 format %{ "[$reg]" %}
4217 interface(MEMORY_INTER) %{
4218 base(0x4); // ESP
4219 index(0x4); // No Index
4220 scale(0x0); // No Scale
4221 disp($reg); // Stack Offset
4222 %}
4223 %}
4224
4225 operand stackSlotL(sRegL reg) %{
4226 constraint(ALLOC_IN_RC(stack_slots));
4227 // No match rule because this operand is only generated in matching
4228 format %{ "[$reg]" %}
4229 interface(MEMORY_INTER) %{
4230 base(0x4); // ESP
4231 index(0x4); // No Index
4232 scale(0x0); // No Scale
4233 disp($reg); // Stack Offset
4234 %}
4235 %}
4236
4237 //----------Memory Operands - Win95 Implicit Null Variants----------------
4238 // Indirect Memory Operand
4239 operand indirect_win95_safe(eRegP_no_EBP reg)
4240 %{
4241 constraint(ALLOC_IN_RC(int_reg));
4242 match(reg);
4243
4244 op_cost(100);
4245 format %{ "[$reg]" %}
4246 interface(MEMORY_INTER) %{
4247 base($reg);
4248 index(0x4);
4249 scale(0x0);
4250 disp(0x0);
4251 %}
4252 %}
4253
4254 // Indirect Memory Plus Short Offset Operand
4255 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4256 %{
4257 match(AddP reg off);
4258
4259 op_cost(100);
4260 format %{ "[$reg + $off]" %}
4261 interface(MEMORY_INTER) %{
4262 base($reg);
4263 index(0x4);
4264 scale(0x0);
4265 disp($off);
4266 %}
4267 %}
4268
4269 // Indirect Memory Plus Long Offset Operand
4270 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4271 %{
4272 match(AddP reg off);
4273
4274 op_cost(100);
4275 format %{ "[$reg + $off]" %}
4276 interface(MEMORY_INTER) %{
4277 base($reg);
4278 index(0x4);
4279 scale(0x0);
4280 disp($off);
4281 %}
4282 %}
4283
4284 // Indirect Memory Plus Index Register Plus Offset Operand
4285 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4286 %{
4287 match(AddP (AddP reg ireg) off);
4288
4289 op_cost(100);
4290 format %{"[$reg + $off + $ireg]" %}
4291 interface(MEMORY_INTER) %{
4292 base($reg);
4293 index($ireg);
4294 scale(0x0);
4295 disp($off);
4296 %}
4297 %}
4298
4299 // Indirect Memory Times Scale Plus Index Register
4300 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4301 %{
4302 match(AddP reg (LShiftI ireg scale));
4303
4304 op_cost(100);
4305 format %{"[$reg + $ireg << $scale]" %}
4306 interface(MEMORY_INTER) %{
4307 base($reg);
4308 index($ireg);
4309 scale($scale);
4310 disp(0x0);
4311 %}
4312 %}
4313
4314 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4315 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4316 %{
4317 match(AddP (AddP reg (LShiftI ireg scale)) off);
4318
4319 op_cost(100);
4320 format %{"[$reg + $off + $ireg << $scale]" %}
4321 interface(MEMORY_INTER) %{
4322 base($reg);
4323 index($ireg);
4324 scale($scale);
4325 disp($off);
4326 %}
4327 %}
4328
4329 //----------Conditional Branch Operands----------------------------------------
4330 // Comparison Op - This is the operation of the comparison, and is limited to
4331 // the following set of codes:
4332 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4333 //
4334 // Other attributes of the comparison, such as unsignedness, are specified
4335 // by the comparison instruction that sets a condition code flags register.
4336 // That result is represented by a flags operand whose subtype is appropriate
4337 // to the unsignedness (etc.) of the comparison.
4338 //
4339 // Later, the instruction which matches both the Comparison Op (a Bool) and
4340 // the flags (produced by the Cmp) specifies the coding of the comparison op
4341 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4342
4343 // Comparision Code
4344 operand cmpOp() %{
4345 match(Bool);
4346
4347 format %{ "" %}
4348 interface(COND_INTER) %{
4349 equal(0x4, "e");
4350 not_equal(0x5, "ne");
4351 less(0xC, "l");
4352 greater_equal(0xD, "ge");
4353 less_equal(0xE, "le");
4354 greater(0xF, "g");
4355 overflow(0x0, "o");
4356 no_overflow(0x1, "no");
4357 %}
4358 %}
4359
4360 // Comparison Code, unsigned compare. Used by FP also, with
4361 // C2 (unordered) turned into GT or LT already. The other bits
4362 // C0 and C3 are turned into Carry & Zero flags.
4363 operand cmpOpU() %{
4364 match(Bool);
4365
4366 format %{ "" %}
4367 interface(COND_INTER) %{
4368 equal(0x4, "e");
4369 not_equal(0x5, "ne");
4370 less(0x2, "b");
4371 greater_equal(0x3, "nb");
4372 less_equal(0x6, "be");
4373 greater(0x7, "nbe");
4374 overflow(0x0, "o");
4375 no_overflow(0x1, "no");
4376 %}
4377 %}
4378
4379 // Floating comparisons that don't require any fixup for the unordered case
4380 operand cmpOpUCF() %{
4381 match(Bool);
4382 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4383 n->as_Bool()->_test._test == BoolTest::ge ||
4384 n->as_Bool()->_test._test == BoolTest::le ||
4385 n->as_Bool()->_test._test == BoolTest::gt);
4386 format %{ "" %}
4387 interface(COND_INTER) %{
4388 equal(0x4, "e");
4389 not_equal(0x5, "ne");
4390 less(0x2, "b");
4391 greater_equal(0x3, "nb");
4392 less_equal(0x6, "be");
4393 greater(0x7, "nbe");
4394 overflow(0x0, "o");
4395 no_overflow(0x1, "no");
4396 %}
4397 %}
4398
4399
4400 // Floating comparisons that can be fixed up with extra conditional jumps
4401 operand cmpOpUCF2() %{
4402 match(Bool);
4403 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4404 n->as_Bool()->_test._test == BoolTest::eq);
4405 format %{ "" %}
4406 interface(COND_INTER) %{
4407 equal(0x4, "e");
4408 not_equal(0x5, "ne");
4409 less(0x2, "b");
4410 greater_equal(0x3, "nb");
4411 less_equal(0x6, "be");
4412 greater(0x7, "nbe");
4413 overflow(0x0, "o");
4414 no_overflow(0x1, "no");
4415 %}
4416 %}
4417
4418 // Comparison Code for FP conditional move
4419 operand cmpOp_fcmov() %{
4420 match(Bool);
4421
4422 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4423 n->as_Bool()->_test._test != BoolTest::no_overflow);
4424 format %{ "" %}
4425 interface(COND_INTER) %{
4426 equal (0x0C8);
4427 not_equal (0x1C8);
4428 less (0x0C0);
4429 greater_equal(0x1C0);
4430 less_equal (0x0D0);
4431 greater (0x1D0);
4432 overflow(0x0, "o"); // not really supported by the instruction
4433 no_overflow(0x1, "no"); // not really supported by the instruction
4434 %}
4435 %}
4436
4437 // Comparision Code used in long compares
4438 operand cmpOp_commute() %{
4439 match(Bool);
4440
4441 format %{ "" %}
4442 interface(COND_INTER) %{
4443 equal(0x4, "e");
4444 not_equal(0x5, "ne");
4445 less(0xF, "g");
4446 greater_equal(0xE, "le");
4447 less_equal(0xD, "ge");
4448 greater(0xC, "l");
4449 overflow(0x0, "o");
4450 no_overflow(0x1, "no");
4451 %}
4452 %}
4453
4454 //----------OPERAND CLASSES----------------------------------------------------
4455 // Operand Classes are groups of operands that are used as to simplify
4456 // instruction definitions by not requiring the AD writer to specify separate
4457 // instructions for every form of operand when the instruction accepts
4458 // multiple operand types with the same basic encoding and format. The classic
4459 // case of this is memory operands.
4460
4461 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
4462 indIndex, indIndexScale, indIndexScaleOffset);
4463
4464 // Long memory operations are encoded in 2 instructions and a +4 offset.
4465 // This means some kind of offset is always required and you cannot use
4466 // an oop as the offset (done when working on static globals).
4467 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
4468 indIndex, indIndexScale, indIndexScaleOffset);
4469
4470
4471 //----------PIPELINE-----------------------------------------------------------
4472 // Rules which define the behavior of the target architectures pipeline.
4473 pipeline %{
4474
4475 //----------ATTRIBUTES---------------------------------------------------------
4476 attributes %{
4477 variable_size_instructions; // Fixed size instructions
4478 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4479 instruction_unit_size = 1; // An instruction is 1 bytes long
4480 instruction_fetch_unit_size = 16; // The processor fetches one line
4481 instruction_fetch_units = 1; // of 16 bytes
4482
4483 // List of nop instructions
4484 nops( MachNop );
4485 %}
4486
4487 //----------RESOURCES----------------------------------------------------------
4488 // Resources are the functional units available to the machine
4489
4490 // Generic P2/P3 pipeline
4491 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4492 // 3 instructions decoded per cycle.
4493 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4494 // 2 ALU op, only ALU0 handles mul/div instructions.
4495 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4496 MS0, MS1, MEM = MS0 | MS1,
4497 BR, FPU,
4498 ALU0, ALU1, ALU = ALU0 | ALU1 );
4499
4500 //----------PIPELINE DESCRIPTION-----------------------------------------------
4501 // Pipeline Description specifies the stages in the machine's pipeline
4502
4503 // Generic P2/P3 pipeline
4504 pipe_desc(S0, S1, S2, S3, S4, S5);
4505
4506 //----------PIPELINE CLASSES---------------------------------------------------
4507 // Pipeline Classes describe the stages in which input and output are
4508 // referenced by the hardware pipeline.
4509
4510 // Naming convention: ialu or fpu
4511 // Then: _reg
4512 // Then: _reg if there is a 2nd register
4513 // Then: _long if it's a pair of instructions implementing a long
4514 // Then: _fat if it requires the big decoder
4515 // Or: _mem if it requires the big decoder and a memory unit.
4516
4517 // Integer ALU reg operation
4518 pipe_class ialu_reg(rRegI dst) %{
4519 single_instruction;
4520 dst : S4(write);
4521 dst : S3(read);
4522 DECODE : S0; // any decoder
4523 ALU : S3; // any alu
4524 %}
4525
4526 // Long ALU reg operation
4527 pipe_class ialu_reg_long(eRegL dst) %{
4528 instruction_count(2);
4529 dst : S4(write);
4530 dst : S3(read);
4531 DECODE : S0(2); // any 2 decoders
4532 ALU : S3(2); // both alus
4533 %}
4534
4535 // Integer ALU reg operation using big decoder
4536 pipe_class ialu_reg_fat(rRegI dst) %{
4537 single_instruction;
4538 dst : S4(write);
4539 dst : S3(read);
4540 D0 : S0; // big decoder only
4541 ALU : S3; // any alu
4542 %}
4543
4544 // Long ALU reg operation using big decoder
4545 pipe_class ialu_reg_long_fat(eRegL dst) %{
4546 instruction_count(2);
4547 dst : S4(write);
4548 dst : S3(read);
4549 D0 : S0(2); // big decoder only; twice
4550 ALU : S3(2); // any 2 alus
4551 %}
4552
4553 // Integer ALU reg-reg operation
4554 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
4555 single_instruction;
4556 dst : S4(write);
4557 src : S3(read);
4558 DECODE : S0; // any decoder
4559 ALU : S3; // any alu
4560 %}
4561
4562 // Long ALU reg-reg operation
4563 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
4564 instruction_count(2);
4565 dst : S4(write);
4566 src : S3(read);
4567 DECODE : S0(2); // any 2 decoders
4568 ALU : S3(2); // both alus
4569 %}
4570
4571 // Integer ALU reg-reg operation
4572 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
4573 single_instruction;
4574 dst : S4(write);
4575 src : S3(read);
4576 D0 : S0; // big decoder only
4577 ALU : S3; // any alu
4578 %}
4579
4580 // Long ALU reg-reg operation
4581 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
4582 instruction_count(2);
4583 dst : S4(write);
4584 src : S3(read);
4585 D0 : S0(2); // big decoder only; twice
4586 ALU : S3(2); // both alus
4587 %}
4588
4589 // Integer ALU reg-mem operation
4590 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
4591 single_instruction;
4592 dst : S5(write);
4593 mem : S3(read);
4594 D0 : S0; // big decoder only
4595 ALU : S4; // any alu
4596 MEM : S3; // any mem
4597 %}
4598
4599 // Long ALU reg-mem operation
4600 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
4601 instruction_count(2);
4602 dst : S5(write);
4603 mem : S3(read);
4604 D0 : S0(2); // big decoder only; twice
4605 ALU : S4(2); // any 2 alus
4606 MEM : S3(2); // both mems
4607 %}
4608
4609 // Integer mem operation (prefetch)
4610 pipe_class ialu_mem(memory mem)
4611 %{
4612 single_instruction;
4613 mem : S3(read);
4614 D0 : S0; // big decoder only
4615 MEM : S3; // any mem
4616 %}
4617
4618 // Integer Store to Memory
4619 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
4620 single_instruction;
4621 mem : S3(read);
4622 src : S5(read);
4623 D0 : S0; // big decoder only
4624 ALU : S4; // any alu
4625 MEM : S3;
4626 %}
4627
4628 // Long Store to Memory
4629 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
4630 instruction_count(2);
4631 mem : S3(read);
4632 src : S5(read);
4633 D0 : S0(2); // big decoder only; twice
4634 ALU : S4(2); // any 2 alus
4635 MEM : S3(2); // Both mems
4636 %}
4637
4638 // Integer Store to Memory
4639 pipe_class ialu_mem_imm(memory mem) %{
4640 single_instruction;
4641 mem : S3(read);
4642 D0 : S0; // big decoder only
4643 ALU : S4; // any alu
4644 MEM : S3;
4645 %}
4646
4647 // Integer ALU0 reg-reg operation
4648 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
4649 single_instruction;
4650 dst : S4(write);
4651 src : S3(read);
4652 D0 : S0; // Big decoder only
4653 ALU0 : S3; // only alu0
4654 %}
4655
4656 // Integer ALU0 reg-mem operation
4657 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
4658 single_instruction;
4659 dst : S5(write);
4660 mem : S3(read);
4661 D0 : S0; // big decoder only
4662 ALU0 : S4; // ALU0 only
4663 MEM : S3; // any mem
4664 %}
4665
4666 // Integer ALU reg-reg operation
4667 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
4668 single_instruction;
4669 cr : S4(write);
4670 src1 : S3(read);
4671 src2 : S3(read);
4672 DECODE : S0; // any decoder
4673 ALU : S3; // any alu
4674 %}
4675
4676 // Integer ALU reg-imm operation
4677 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
4678 single_instruction;
4679 cr : S4(write);
4680 src1 : S3(read);
4681 DECODE : S0; // any decoder
4682 ALU : S3; // any alu
4683 %}
4684
4685 // Integer ALU reg-mem operation
4686 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
4687 single_instruction;
4688 cr : S4(write);
4689 src1 : S3(read);
4690 src2 : S3(read);
4691 D0 : S0; // big decoder only
4692 ALU : S4; // any alu
4693 MEM : S3;
4694 %}
4695
4696 // Conditional move reg-reg
4697 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
4698 instruction_count(4);
4699 y : S4(read);
4700 q : S3(read);
4701 p : S3(read);
4702 DECODE : S0(4); // any decoder
4703 %}
4704
4705 // Conditional move reg-reg
4706 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
4707 single_instruction;
4708 dst : S4(write);
4709 src : S3(read);
4710 cr : S3(read);
4711 DECODE : S0; // any decoder
4712 %}
4713
4714 // Conditional move reg-mem
4715 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
4716 single_instruction;
4717 dst : S4(write);
4718 src : S3(read);
4719 cr : S3(read);
4720 DECODE : S0; // any decoder
4721 MEM : S3;
4722 %}
4723
4724 // Conditional move reg-reg long
4725 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
4726 single_instruction;
4727 dst : S4(write);
4728 src : S3(read);
4729 cr : S3(read);
4730 DECODE : S0(2); // any 2 decoders
4731 %}
4732
4733 // Conditional move double reg-reg
4734 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
4735 single_instruction;
4736 dst : S4(write);
4737 src : S3(read);
4738 cr : S3(read);
4739 DECODE : S0; // any decoder
4740 %}
4741
4742 // Float reg-reg operation
4743 pipe_class fpu_reg(regDPR dst) %{
4744 instruction_count(2);
4745 dst : S3(read);
4746 DECODE : S0(2); // any 2 decoders
4747 FPU : S3;
4748 %}
4749
4750 // Float reg-reg operation
4751 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
4752 instruction_count(2);
4753 dst : S4(write);
4754 src : S3(read);
4755 DECODE : S0(2); // any 2 decoders
4756 FPU : S3;
4757 %}
4758
4759 // Float reg-reg operation
4760 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
4761 instruction_count(3);
4762 dst : S4(write);
4763 src1 : S3(read);
4764 src2 : S3(read);
4765 DECODE : S0(3); // any 3 decoders
4766 FPU : S3(2);
4767 %}
4768
4769 // Float reg-reg operation
4770 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
4771 instruction_count(4);
4772 dst : S4(write);
4773 src1 : S3(read);
4774 src2 : S3(read);
4775 src3 : S3(read);
4776 DECODE : S0(4); // any 3 decoders
4777 FPU : S3(2);
4778 %}
4779
4780 // Float reg-reg operation
4781 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
4782 instruction_count(4);
4783 dst : S4(write);
4784 src1 : S3(read);
4785 src2 : S3(read);
4786 src3 : S3(read);
4787 DECODE : S1(3); // any 3 decoders
4788 D0 : S0; // Big decoder only
4789 FPU : S3(2);
4790 MEM : S3;
4791 %}
4792
4793 // Float reg-mem operation
4794 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
4795 instruction_count(2);
4796 dst : S5(write);
4797 mem : S3(read);
4798 D0 : S0; // big decoder only
4799 DECODE : S1; // any decoder for FPU POP
4800 FPU : S4;
4801 MEM : S3; // any mem
4802 %}
4803
4804 // Float reg-mem operation
4805 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
4806 instruction_count(3);
4807 dst : S5(write);
4808 src1 : S3(read);
4809 mem : S3(read);
4810 D0 : S0; // big decoder only
4811 DECODE : S1(2); // any decoder for FPU POP
4812 FPU : S4;
4813 MEM : S3; // any mem
4814 %}
4815
4816 // Float mem-reg operation
4817 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
4818 instruction_count(2);
4819 src : S5(read);
4820 mem : S3(read);
4821 DECODE : S0; // any decoder for FPU PUSH
4822 D0 : S1; // big decoder only
4823 FPU : S4;
4824 MEM : S3; // any mem
4825 %}
4826
4827 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
4828 instruction_count(3);
4829 src1 : S3(read);
4830 src2 : S3(read);
4831 mem : S3(read);
4832 DECODE : S0(2); // any decoder for FPU PUSH
4833 D0 : S1; // big decoder only
4834 FPU : S4;
4835 MEM : S3; // any mem
4836 %}
4837
4838 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
4839 instruction_count(3);
4840 src1 : S3(read);
4841 src2 : S3(read);
4842 mem : S4(read);
4843 DECODE : S0; // any decoder for FPU PUSH
4844 D0 : S0(2); // big decoder only
4845 FPU : S4;
4846 MEM : S3(2); // any mem
4847 %}
4848
4849 pipe_class fpu_mem_mem(memory dst, memory src1) %{
4850 instruction_count(2);
4851 src1 : S3(read);
4852 dst : S4(read);
4853 D0 : S0(2); // big decoder only
4854 MEM : S3(2); // any mem
4855 %}
4856
4857 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
4858 instruction_count(3);
4859 src1 : S3(read);
4860 src2 : S3(read);
4861 dst : S4(read);
4862 D0 : S0(3); // big decoder only
4863 FPU : S4;
4864 MEM : S3(3); // any mem
4865 %}
4866
4867 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
4868 instruction_count(3);
4869 src1 : S4(read);
4870 mem : S4(read);
4871 DECODE : S0; // any decoder for FPU PUSH
4872 D0 : S0(2); // big decoder only
4873 FPU : S4;
4874 MEM : S3(2); // any mem
4875 %}
4876
4877 // Float load constant
4878 pipe_class fpu_reg_con(regDPR dst) %{
4879 instruction_count(2);
4880 dst : S5(write);
4881 D0 : S0; // big decoder only for the load
4882 DECODE : S1; // any decoder for FPU POP
4883 FPU : S4;
4884 MEM : S3; // any mem
4885 %}
4886
4887 // Float load constant
4888 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
4889 instruction_count(3);
4890 dst : S5(write);
4891 src : S3(read);
4892 D0 : S0; // big decoder only for the load
4893 DECODE : S1(2); // any decoder for FPU POP
4894 FPU : S4;
4895 MEM : S3; // any mem
4896 %}
4897
4898 // UnConditional branch
4899 pipe_class pipe_jmp( label labl ) %{
4900 single_instruction;
4901 BR : S3;
4902 %}
4903
4904 // Conditional branch
4905 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
4906 single_instruction;
4907 cr : S1(read);
4908 BR : S3;
4909 %}
4910
4911 // Allocation idiom
4912 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
4913 instruction_count(1); force_serialization;
4914 fixed_latency(6);
4915 heap_ptr : S3(read);
4916 DECODE : S0(3);
4917 D0 : S2;
4918 MEM : S3;
4919 ALU : S3(2);
4920 dst : S5(write);
4921 BR : S5;
4922 %}
4923
4924 // Generic big/slow expanded idiom
4925 pipe_class pipe_slow( ) %{
4926 instruction_count(10); multiple_bundles; force_serialization;
4927 fixed_latency(100);
4928 D0 : S0(2);
4929 MEM : S3(2);
4930 %}
4931
4932 // The real do-nothing guy
4933 pipe_class empty( ) %{
4934 instruction_count(0);
4935 %}
4936
4937 // Define the class for the Nop node
4938 define %{
4939 MachNop = empty;
4940 %}
4941
4942 %}
4943
4944 //----------INSTRUCTIONS-------------------------------------------------------
4945 //
4946 // match -- States which machine-independent subtree may be replaced
4947 // by this instruction.
4948 // ins_cost -- The estimated cost of this instruction is used by instruction
4949 // selection to identify a minimum cost tree of machine
4950 // instructions that matches a tree of machine-independent
4951 // instructions.
4952 // format -- A string providing the disassembly for this instruction.
4953 // The value of an instruction's operand may be inserted
4954 // by referring to it with a '$' prefix.
4955 // opcode -- Three instruction opcodes may be provided. These are referred
4956 // to within an encode class as $primary, $secondary, and $tertiary
4957 // respectively. The primary opcode is commonly used to
4958 // indicate the type of machine instruction, while secondary
4959 // and tertiary are often used for prefix options or addressing
4960 // modes.
4961 // ins_encode -- A list of encode classes with parameters. The encode class
4962 // name must have been defined in an 'enc_class' specification
4963 // in the encode section of the architecture description.
4964
4965 //----------BSWAP-Instruction--------------------------------------------------
4966 instruct bytes_reverse_int(rRegI dst) %{
4967 match(Set dst (ReverseBytesI dst));
4968
4969 format %{ "BSWAP $dst" %}
4970 opcode(0x0F, 0xC8);
4971 ins_encode( OpcP, OpcSReg(dst) );
4972 ins_pipe( ialu_reg );
4973 %}
4974
4975 instruct bytes_reverse_long(eRegL dst) %{
4976 match(Set dst (ReverseBytesL dst));
4977
4978 format %{ "BSWAP $dst.lo\n\t"
4979 "BSWAP $dst.hi\n\t"
4980 "XCHG $dst.lo $dst.hi" %}
4981
4982 ins_cost(125);
4983 ins_encode( bswap_long_bytes(dst) );
4984 ins_pipe( ialu_reg_reg);
4985 %}
4986
4987 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
4988 match(Set dst (ReverseBytesUS dst));
4989 effect(KILL cr);
4990
4991 format %{ "BSWAP $dst\n\t"
4992 "SHR $dst,16\n\t" %}
4993 ins_encode %{
4994 __ bswapl($dst$$Register);
4995 __ shrl($dst$$Register, 16);
4996 %}
4997 ins_pipe( ialu_reg );
4998 %}
4999
5000 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5001 match(Set dst (ReverseBytesS dst));
5002 effect(KILL cr);
5003
5004 format %{ "BSWAP $dst\n\t"
5005 "SAR $dst,16\n\t" %}
5006 ins_encode %{
5007 __ bswapl($dst$$Register);
5008 __ sarl($dst$$Register, 16);
5009 %}
5010 ins_pipe( ialu_reg );
5011 %}
5012
5013
5014 //---------- Zeros Count Instructions ------------------------------------------
5015
5016 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5017 predicate(UseCountLeadingZerosInstruction);
5018 match(Set dst (CountLeadingZerosI src));
5019 effect(KILL cr);
5020
5021 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5022 ins_encode %{
5023 __ lzcntl($dst$$Register, $src$$Register);
5024 %}
5025 ins_pipe(ialu_reg);
5026 %}
5027
5028 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5029 predicate(!UseCountLeadingZerosInstruction);
5030 match(Set dst (CountLeadingZerosI src));
5031 effect(KILL cr);
5032
5033 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5034 "JNZ skip\n\t"
5035 "MOV $dst, -1\n"
5036 "skip:\n\t"
5037 "NEG $dst\n\t"
5038 "ADD $dst, 31" %}
5039 ins_encode %{
5040 Register Rdst = $dst$$Register;
5041 Register Rsrc = $src$$Register;
5042 Label skip;
5043 __ bsrl(Rdst, Rsrc);
5044 __ jccb(Assembler::notZero, skip);
5045 __ movl(Rdst, -1);
5046 __ bind(skip);
5047 __ negl(Rdst);
5048 __ addl(Rdst, BitsPerInt - 1);
5049 %}
5050 ins_pipe(ialu_reg);
5051 %}
5052
5053 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5054 predicate(UseCountLeadingZerosInstruction);
5055 match(Set dst (CountLeadingZerosL src));
5056 effect(TEMP dst, KILL cr);
5057
5058 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5059 "JNC done\n\t"
5060 "LZCNT $dst, $src.lo\n\t"
5061 "ADD $dst, 32\n"
5062 "done:" %}
5063 ins_encode %{
5064 Register Rdst = $dst$$Register;
5065 Register Rsrc = $src$$Register;
5066 Label done;
5067 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5068 __ jccb(Assembler::carryClear, done);
5069 __ lzcntl(Rdst, Rsrc);
5070 __ addl(Rdst, BitsPerInt);
5071 __ bind(done);
5072 %}
5073 ins_pipe(ialu_reg);
5074 %}
5075
5076 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5077 predicate(!UseCountLeadingZerosInstruction);
5078 match(Set dst (CountLeadingZerosL src));
5079 effect(TEMP dst, KILL cr);
5080
5081 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5082 "JZ msw_is_zero\n\t"
5083 "ADD $dst, 32\n\t"
5084 "JMP not_zero\n"
5085 "msw_is_zero:\n\t"
5086 "BSR $dst, $src.lo\n\t"
5087 "JNZ not_zero\n\t"
5088 "MOV $dst, -1\n"
5089 "not_zero:\n\t"
5090 "NEG $dst\n\t"
5091 "ADD $dst, 63\n" %}
5092 ins_encode %{
5093 Register Rdst = $dst$$Register;
5094 Register Rsrc = $src$$Register;
5095 Label msw_is_zero;
5096 Label not_zero;
5097 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5098 __ jccb(Assembler::zero, msw_is_zero);
5099 __ addl(Rdst, BitsPerInt);
5100 __ jmpb(not_zero);
5101 __ bind(msw_is_zero);
5102 __ bsrl(Rdst, Rsrc);
5103 __ jccb(Assembler::notZero, not_zero);
5104 __ movl(Rdst, -1);
5105 __ bind(not_zero);
5106 __ negl(Rdst);
5107 __ addl(Rdst, BitsPerLong - 1);
5108 %}
5109 ins_pipe(ialu_reg);
5110 %}
5111
5112 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5113 predicate(UseCountTrailingZerosInstruction);
5114 match(Set dst (CountTrailingZerosI src));
5115 effect(KILL cr);
5116
5117 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %}
5118 ins_encode %{
5119 __ tzcntl($dst$$Register, $src$$Register);
5120 %}
5121 ins_pipe(ialu_reg);
5122 %}
5123
5124 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5125 predicate(!UseCountTrailingZerosInstruction);
5126 match(Set dst (CountTrailingZerosI src));
5127 effect(KILL cr);
5128
5129 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5130 "JNZ done\n\t"
5131 "MOV $dst, 32\n"
5132 "done:" %}
5133 ins_encode %{
5134 Register Rdst = $dst$$Register;
5135 Label done;
5136 __ bsfl(Rdst, $src$$Register);
5137 __ jccb(Assembler::notZero, done);
5138 __ movl(Rdst, BitsPerInt);
5139 __ bind(done);
5140 %}
5141 ins_pipe(ialu_reg);
5142 %}
5143
5144 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5145 predicate(UseCountTrailingZerosInstruction);
5146 match(Set dst (CountTrailingZerosL src));
5147 effect(TEMP dst, KILL cr);
5148
5149 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t"
5150 "JNC done\n\t"
5151 "TZCNT $dst, $src.hi\n\t"
5152 "ADD $dst, 32\n"
5153 "done:" %}
5154 ins_encode %{
5155 Register Rdst = $dst$$Register;
5156 Register Rsrc = $src$$Register;
5157 Label done;
5158 __ tzcntl(Rdst, Rsrc);
5159 __ jccb(Assembler::carryClear, done);
5160 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5161 __ addl(Rdst, BitsPerInt);
5162 __ bind(done);
5163 %}
5164 ins_pipe(ialu_reg);
5165 %}
5166
5167 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5168 predicate(!UseCountTrailingZerosInstruction);
5169 match(Set dst (CountTrailingZerosL src));
5170 effect(TEMP dst, KILL cr);
5171
5172 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5173 "JNZ done\n\t"
5174 "BSF $dst, $src.hi\n\t"
5175 "JNZ msw_not_zero\n\t"
5176 "MOV $dst, 32\n"
5177 "msw_not_zero:\n\t"
5178 "ADD $dst, 32\n"
5179 "done:" %}
5180 ins_encode %{
5181 Register Rdst = $dst$$Register;
5182 Register Rsrc = $src$$Register;
5183 Label msw_not_zero;
5184 Label done;
5185 __ bsfl(Rdst, Rsrc);
5186 __ jccb(Assembler::notZero, done);
5187 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5188 __ jccb(Assembler::notZero, msw_not_zero);
5189 __ movl(Rdst, BitsPerInt);
5190 __ bind(msw_not_zero);
5191 __ addl(Rdst, BitsPerInt);
5192 __ bind(done);
5193 %}
5194 ins_pipe(ialu_reg);
5195 %}
5196
5197
5198 //---------- Population Count Instructions -------------------------------------
5199
5200 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5201 predicate(UsePopCountInstruction);
5202 match(Set dst (PopCountI src));
5203 effect(KILL cr);
5204
5205 format %{ "POPCNT $dst, $src" %}
5206 ins_encode %{
5207 __ popcntl($dst$$Register, $src$$Register);
5208 %}
5209 ins_pipe(ialu_reg);
5210 %}
5211
5212 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5213 predicate(UsePopCountInstruction);
5214 match(Set dst (PopCountI (LoadI mem)));
5215 effect(KILL cr);
5216
5217 format %{ "POPCNT $dst, $mem" %}
5218 ins_encode %{
5219 __ popcntl($dst$$Register, $mem$$Address);
5220 %}
5221 ins_pipe(ialu_reg);
5222 %}
5223
5224 // Note: Long.bitCount(long) returns an int.
5225 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5226 predicate(UsePopCountInstruction);
5227 match(Set dst (PopCountL src));
5228 effect(KILL cr, TEMP tmp, TEMP dst);
5229
5230 format %{ "POPCNT $dst, $src.lo\n\t"
5231 "POPCNT $tmp, $src.hi\n\t"
5232 "ADD $dst, $tmp" %}
5233 ins_encode %{
5234 __ popcntl($dst$$Register, $src$$Register);
5235 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5236 __ addl($dst$$Register, $tmp$$Register);
5237 %}
5238 ins_pipe(ialu_reg);
5239 %}
5240
5241 // Note: Long.bitCount(long) returns an int.
5242 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5243 predicate(UsePopCountInstruction);
5244 match(Set dst (PopCountL (LoadL mem)));
5245 effect(KILL cr, TEMP tmp, TEMP dst);
5246
5247 format %{ "POPCNT $dst, $mem\n\t"
5248 "POPCNT $tmp, $mem+4\n\t"
5249 "ADD $dst, $tmp" %}
5250 ins_encode %{
5251 //__ popcntl($dst$$Register, $mem$$Address$$first);
5252 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5253 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5254 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5255 __ addl($dst$$Register, $tmp$$Register);
5256 %}
5257 ins_pipe(ialu_reg);
5258 %}
5259
5260
5261 //----------Load/Store/Move Instructions---------------------------------------
5262 //----------Load Instructions--------------------------------------------------
5263 // Load Byte (8bit signed)
5264 instruct loadB(xRegI dst, memory mem) %{
5265 match(Set dst (LoadB mem));
5266
5267 ins_cost(125);
5268 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5269
5270 ins_encode %{
5271 __ movsbl($dst$$Register, $mem$$Address);
5272 %}
5273
5274 ins_pipe(ialu_reg_mem);
5275 %}
5276
5277 // Load Byte (8bit signed) into Long Register
5278 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5279 match(Set dst (ConvI2L (LoadB mem)));
5280 effect(KILL cr);
5281
5282 ins_cost(375);
5283 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5284 "MOV $dst.hi,$dst.lo\n\t"
5285 "SAR $dst.hi,7" %}
5286
5287 ins_encode %{
5288 __ movsbl($dst$$Register, $mem$$Address);
5289 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5290 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5291 %}
5292
5293 ins_pipe(ialu_reg_mem);
5294 %}
5295
5296 // Load Unsigned Byte (8bit UNsigned)
5297 instruct loadUB(xRegI dst, memory mem) %{
5298 match(Set dst (LoadUB mem));
5299
5300 ins_cost(125);
5301 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5302
5303 ins_encode %{
5304 __ movzbl($dst$$Register, $mem$$Address);
5305 %}
5306
5307 ins_pipe(ialu_reg_mem);
5308 %}
5309
5310 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5311 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5312 match(Set dst (ConvI2L (LoadUB mem)));
5313 effect(KILL cr);
5314
5315 ins_cost(250);
5316 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5317 "XOR $dst.hi,$dst.hi" %}
5318
5319 ins_encode %{
5320 Register Rdst = $dst$$Register;
5321 __ movzbl(Rdst, $mem$$Address);
5322 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5323 %}
5324
5325 ins_pipe(ialu_reg_mem);
5326 %}
5327
5328 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5329 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5330 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5331 effect(KILL cr);
5332
5333 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5334 "XOR $dst.hi,$dst.hi\n\t"
5335 "AND $dst.lo,$mask" %}
5336 ins_encode %{
5337 Register Rdst = $dst$$Register;
5338 __ movzbl(Rdst, $mem$$Address);
5339 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5340 __ andl(Rdst, $mask$$constant);
5341 %}
5342 ins_pipe(ialu_reg_mem);
5343 %}
5344
5345 // Load Short (16bit signed)
5346 instruct loadS(rRegI dst, memory mem) %{
5347 match(Set dst (LoadS mem));
5348
5349 ins_cost(125);
5350 format %{ "MOVSX $dst,$mem\t# short" %}
5351
5352 ins_encode %{
5353 __ movswl($dst$$Register, $mem$$Address);
5354 %}
5355
5356 ins_pipe(ialu_reg_mem);
5357 %}
5358
5359 // Load Short (16 bit signed) to Byte (8 bit signed)
5360 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5361 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5362
5363 ins_cost(125);
5364 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5365 ins_encode %{
5366 __ movsbl($dst$$Register, $mem$$Address);
5367 %}
5368 ins_pipe(ialu_reg_mem);
5369 %}
5370
5371 // Load Short (16bit signed) into Long Register
5372 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5373 match(Set dst (ConvI2L (LoadS mem)));
5374 effect(KILL cr);
5375
5376 ins_cost(375);
5377 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5378 "MOV $dst.hi,$dst.lo\n\t"
5379 "SAR $dst.hi,15" %}
5380
5381 ins_encode %{
5382 __ movswl($dst$$Register, $mem$$Address);
5383 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5384 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5385 %}
5386
5387 ins_pipe(ialu_reg_mem);
5388 %}
5389
5390 // Load Unsigned Short/Char (16bit unsigned)
5391 instruct loadUS(rRegI dst, memory mem) %{
5392 match(Set dst (LoadUS mem));
5393
5394 ins_cost(125);
5395 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5396
5397 ins_encode %{
5398 __ movzwl($dst$$Register, $mem$$Address);
5399 %}
5400
5401 ins_pipe(ialu_reg_mem);
5402 %}
5403
5404 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5405 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5406 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5407
5408 ins_cost(125);
5409 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5410 ins_encode %{
5411 __ movsbl($dst$$Register, $mem$$Address);
5412 %}
5413 ins_pipe(ialu_reg_mem);
5414 %}
5415
5416 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5417 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5418 match(Set dst (ConvI2L (LoadUS mem)));
5419 effect(KILL cr);
5420
5421 ins_cost(250);
5422 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5423 "XOR $dst.hi,$dst.hi" %}
5424
5425 ins_encode %{
5426 __ movzwl($dst$$Register, $mem$$Address);
5427 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5428 %}
5429
5430 ins_pipe(ialu_reg_mem);
5431 %}
5432
5433 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5434 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5435 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5436 effect(KILL cr);
5437
5438 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5439 "XOR $dst.hi,$dst.hi" %}
5440 ins_encode %{
5441 Register Rdst = $dst$$Register;
5442 __ movzbl(Rdst, $mem$$Address);
5443 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5444 %}
5445 ins_pipe(ialu_reg_mem);
5446 %}
5447
5448 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5449 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5450 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5451 effect(KILL cr);
5452
5453 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5454 "XOR $dst.hi,$dst.hi\n\t"
5455 "AND $dst.lo,$mask" %}
5456 ins_encode %{
5457 Register Rdst = $dst$$Register;
5458 __ movzwl(Rdst, $mem$$Address);
5459 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5460 __ andl(Rdst, $mask$$constant);
5461 %}
5462 ins_pipe(ialu_reg_mem);
5463 %}
5464
5465 // Load Integer
5466 instruct loadI(rRegI dst, memory mem) %{
5467 match(Set dst (LoadI mem));
5468
5469 ins_cost(125);
5470 format %{ "MOV $dst,$mem\t# int" %}
5471
5472 ins_encode %{
5473 __ movl($dst$$Register, $mem$$Address);
5474 %}
5475
5476 ins_pipe(ialu_reg_mem);
5477 %}
5478
5479 // Load Integer (32 bit signed) to Byte (8 bit signed)
5480 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5481 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5482
5483 ins_cost(125);
5484 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
5485 ins_encode %{
5486 __ movsbl($dst$$Register, $mem$$Address);
5487 %}
5488 ins_pipe(ialu_reg_mem);
5489 %}
5490
5491 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5492 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5493 match(Set dst (AndI (LoadI mem) mask));
5494
5495 ins_cost(125);
5496 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
5497 ins_encode %{
5498 __ movzbl($dst$$Register, $mem$$Address);
5499 %}
5500 ins_pipe(ialu_reg_mem);
5501 %}
5502
5503 // Load Integer (32 bit signed) to Short (16 bit signed)
5504 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5505 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5506
5507 ins_cost(125);
5508 format %{ "MOVSX $dst, $mem\t# int -> short" %}
5509 ins_encode %{
5510 __ movswl($dst$$Register, $mem$$Address);
5511 %}
5512 ins_pipe(ialu_reg_mem);
5513 %}
5514
5515 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5516 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5517 match(Set dst (AndI (LoadI mem) mask));
5518
5519 ins_cost(125);
5520 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
5521 ins_encode %{
5522 __ movzwl($dst$$Register, $mem$$Address);
5523 %}
5524 ins_pipe(ialu_reg_mem);
5525 %}
5526
5527 // Load Integer into Long Register
5528 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
5529 match(Set dst (ConvI2L (LoadI mem)));
5530 effect(KILL cr);
5531
5532 ins_cost(375);
5533 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
5534 "MOV $dst.hi,$dst.lo\n\t"
5535 "SAR $dst.hi,31" %}
5536
5537 ins_encode %{
5538 __ movl($dst$$Register, $mem$$Address);
5539 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5540 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
5541 %}
5542
5543 ins_pipe(ialu_reg_mem);
5544 %}
5545
5546 // Load Integer with mask 0xFF into Long Register
5547 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5548 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5549 effect(KILL cr);
5550
5551 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
5552 "XOR $dst.hi,$dst.hi" %}
5553 ins_encode %{
5554 Register Rdst = $dst$$Register;
5555 __ movzbl(Rdst, $mem$$Address);
5556 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5557 %}
5558 ins_pipe(ialu_reg_mem);
5559 %}
5560
5561 // Load Integer with mask 0xFFFF into Long Register
5562 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
5563 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5564 effect(KILL cr);
5565
5566 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
5567 "XOR $dst.hi,$dst.hi" %}
5568 ins_encode %{
5569 Register Rdst = $dst$$Register;
5570 __ movzwl(Rdst, $mem$$Address);
5571 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5572 %}
5573 ins_pipe(ialu_reg_mem);
5574 %}
5575
5576 // Load Integer with 31-bit mask into Long Register
5577 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
5578 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5579 effect(KILL cr);
5580
5581 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
5582 "XOR $dst.hi,$dst.hi\n\t"
5583 "AND $dst.lo,$mask" %}
5584 ins_encode %{
5585 Register Rdst = $dst$$Register;
5586 __ movl(Rdst, $mem$$Address);
5587 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5588 __ andl(Rdst, $mask$$constant);
5589 %}
5590 ins_pipe(ialu_reg_mem);
5591 %}
5592
5593 // Load Unsigned Integer into Long Register
5594 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
5595 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5596 effect(KILL cr);
5597
5598 ins_cost(250);
5599 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
5600 "XOR $dst.hi,$dst.hi" %}
5601
5602 ins_encode %{
5603 __ movl($dst$$Register, $mem$$Address);
5604 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5605 %}
5606
5607 ins_pipe(ialu_reg_mem);
5608 %}
5609
5610 // Load Long. Cannot clobber address while loading, so restrict address
5611 // register to ESI
5612 instruct loadL(eRegL dst, load_long_memory mem) %{
5613 predicate(!((LoadLNode*)n)->require_atomic_access());
5614 match(Set dst (LoadL mem));
5615
5616 ins_cost(250);
5617 format %{ "MOV $dst.lo,$mem\t# long\n\t"
5618 "MOV $dst.hi,$mem+4" %}
5619
5620 ins_encode %{
5621 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
5622 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
5623 __ movl($dst$$Register, Amemlo);
5624 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
5625 %}
5626
5627 ins_pipe(ialu_reg_long_mem);
5628 %}
5629
5630 // Volatile Load Long. Must be atomic, so do 64-bit FILD
5631 // then store it down to the stack and reload on the int
5632 // side.
5633 instruct loadL_volatile(stackSlotL dst, memory mem) %{
5634 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
5635 match(Set dst (LoadL mem));
5636
5637 ins_cost(200);
5638 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
5639 "FISTp $dst" %}
5640 ins_encode(enc_loadL_volatile(mem,dst));
5641 ins_pipe( fpu_reg_mem );
5642 %}
5643
5644 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
5645 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5646 match(Set dst (LoadL mem));
5647 effect(TEMP tmp);
5648 ins_cost(180);
5649 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5650 "MOVSD $dst,$tmp" %}
5651 ins_encode %{
5652 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5653 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
5654 %}
5655 ins_pipe( pipe_slow );
5656 %}
5657
5658 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
5659 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5660 match(Set dst (LoadL mem));
5661 effect(TEMP tmp);
5662 ins_cost(160);
5663 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5664 "MOVD $dst.lo,$tmp\n\t"
5665 "PSRLQ $tmp,32\n\t"
5666 "MOVD $dst.hi,$tmp" %}
5667 ins_encode %{
5668 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5669 __ movdl($dst$$Register, $tmp$$XMMRegister);
5670 __ psrlq($tmp$$XMMRegister, 32);
5671 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
5672 %}
5673 ins_pipe( pipe_slow );
5674 %}
5675
5676 // Load Range
5677 instruct loadRange(rRegI dst, memory mem) %{
5678 match(Set dst (LoadRange mem));
5679
5680 ins_cost(125);
5681 format %{ "MOV $dst,$mem" %}
5682 opcode(0x8B);
5683 ins_encode( OpcP, RegMem(dst,mem));
5684 ins_pipe( ialu_reg_mem );
5685 %}
5686
5687
5688 // Load Pointer
5689 instruct loadP(eRegP dst, memory mem) %{
5690 match(Set dst (LoadP mem));
5691
5692 ins_cost(125);
5693 format %{ "MOV $dst,$mem" %}
5694 opcode(0x8B);
5695 ins_encode( OpcP, RegMem(dst,mem));
5696 ins_pipe( ialu_reg_mem );
5697 %}
5698
5699 // Load Klass Pointer
5700 instruct loadKlass(eRegP dst, memory mem) %{
5701 match(Set dst (LoadKlass mem));
5702
5703 ins_cost(125);
5704 format %{ "MOV $dst,$mem" %}
5705 opcode(0x8B);
5706 ins_encode( OpcP, RegMem(dst,mem));
5707 ins_pipe( ialu_reg_mem );
5708 %}
5709
5710 // Load Double
5711 instruct loadDPR(regDPR dst, memory mem) %{
5712 predicate(UseSSE<=1);
5713 match(Set dst (LoadD mem));
5714
5715 ins_cost(150);
5716 format %{ "FLD_D ST,$mem\n\t"
5717 "FSTP $dst" %}
5718 opcode(0xDD); /* DD /0 */
5719 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5720 Pop_Reg_DPR(dst) );
5721 ins_pipe( fpu_reg_mem );
5722 %}
5723
5724 // Load Double to XMM
5725 instruct loadD(regD dst, memory mem) %{
5726 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5727 match(Set dst (LoadD mem));
5728 ins_cost(145);
5729 format %{ "MOVSD $dst,$mem" %}
5730 ins_encode %{
5731 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5732 %}
5733 ins_pipe( pipe_slow );
5734 %}
5735
5736 instruct loadD_partial(regD dst, memory mem) %{
5737 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
5738 match(Set dst (LoadD mem));
5739 ins_cost(145);
5740 format %{ "MOVLPD $dst,$mem" %}
5741 ins_encode %{
5742 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5743 %}
5744 ins_pipe( pipe_slow );
5745 %}
5746
5747 // Load to XMM register (single-precision floating point)
5748 // MOVSS instruction
5749 instruct loadF(regF dst, memory mem) %{
5750 predicate(UseSSE>=1);
5751 match(Set dst (LoadF mem));
5752 ins_cost(145);
5753 format %{ "MOVSS $dst,$mem" %}
5754 ins_encode %{
5755 __ movflt ($dst$$XMMRegister, $mem$$Address);
5756 %}
5757 ins_pipe( pipe_slow );
5758 %}
5759
5760 // Load Float
5761 instruct loadFPR(regFPR dst, memory mem) %{
5762 predicate(UseSSE==0);
5763 match(Set dst (LoadF mem));
5764
5765 ins_cost(150);
5766 format %{ "FLD_S ST,$mem\n\t"
5767 "FSTP $dst" %}
5768 opcode(0xD9); /* D9 /0 */
5769 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5770 Pop_Reg_FPR(dst) );
5771 ins_pipe( fpu_reg_mem );
5772 %}
5773
5774 // Load Effective Address
5775 instruct leaP8(eRegP dst, indOffset8 mem) %{
5776 match(Set dst mem);
5777
5778 ins_cost(110);
5779 format %{ "LEA $dst,$mem" %}
5780 opcode(0x8D);
5781 ins_encode( OpcP, RegMem(dst,mem));
5782 ins_pipe( ialu_reg_reg_fat );
5783 %}
5784
5785 instruct leaP32(eRegP dst, indOffset32 mem) %{
5786 match(Set dst mem);
5787
5788 ins_cost(110);
5789 format %{ "LEA $dst,$mem" %}
5790 opcode(0x8D);
5791 ins_encode( OpcP, RegMem(dst,mem));
5792 ins_pipe( ialu_reg_reg_fat );
5793 %}
5794
5795 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
5796 match(Set dst mem);
5797
5798 ins_cost(110);
5799 format %{ "LEA $dst,$mem" %}
5800 opcode(0x8D);
5801 ins_encode( OpcP, RegMem(dst,mem));
5802 ins_pipe( ialu_reg_reg_fat );
5803 %}
5804
5805 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
5806 match(Set dst mem);
5807
5808 ins_cost(110);
5809 format %{ "LEA $dst,$mem" %}
5810 opcode(0x8D);
5811 ins_encode( OpcP, RegMem(dst,mem));
5812 ins_pipe( ialu_reg_reg_fat );
5813 %}
5814
5815 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5816 match(Set dst mem);
5817
5818 ins_cost(110);
5819 format %{ "LEA $dst,$mem" %}
5820 opcode(0x8D);
5821 ins_encode( OpcP, RegMem(dst,mem));
5822 ins_pipe( ialu_reg_reg_fat );
5823 %}
5824
5825 // Load Constant
5826 instruct loadConI(rRegI dst, immI src) %{
5827 match(Set dst src);
5828
5829 format %{ "MOV $dst,$src" %}
5830 ins_encode( LdImmI(dst, src) );
5831 ins_pipe( ialu_reg_fat );
5832 %}
5833
5834 // Load Constant zero
5835 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5836 match(Set dst src);
5837 effect(KILL cr);
5838
5839 ins_cost(50);
5840 format %{ "XOR $dst,$dst" %}
5841 opcode(0x33); /* + rd */
5842 ins_encode( OpcP, RegReg( dst, dst ) );
5843 ins_pipe( ialu_reg );
5844 %}
5845
5846 instruct loadConP(eRegP dst, immP src) %{
5847 match(Set dst src);
5848
5849 format %{ "MOV $dst,$src" %}
5850 opcode(0xB8); /* + rd */
5851 ins_encode( LdImmP(dst, src) );
5852 ins_pipe( ialu_reg_fat );
5853 %}
5854
5855 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
5856 match(Set dst src);
5857 effect(KILL cr);
5858 ins_cost(200);
5859 format %{ "MOV $dst.lo,$src.lo\n\t"
5860 "MOV $dst.hi,$src.hi" %}
5861 opcode(0xB8);
5862 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
5863 ins_pipe( ialu_reg_long_fat );
5864 %}
5865
5866 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
5867 match(Set dst src);
5868 effect(KILL cr);
5869 ins_cost(150);
5870 format %{ "XOR $dst.lo,$dst.lo\n\t"
5871 "XOR $dst.hi,$dst.hi" %}
5872 opcode(0x33,0x33);
5873 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
5874 ins_pipe( ialu_reg_long );
5875 %}
5876
5877 // The instruction usage is guarded by predicate in operand immFPR().
5878 instruct loadConFPR(regFPR dst, immFPR con) %{
5879 match(Set dst con);
5880 ins_cost(125);
5881 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
5882 "FSTP $dst" %}
5883 ins_encode %{
5884 __ fld_s($constantaddress($con));
5885 __ fstp_d($dst$$reg);
5886 %}
5887 ins_pipe(fpu_reg_con);
5888 %}
5889
5890 // The instruction usage is guarded by predicate in operand immFPR0().
5891 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
5892 match(Set dst con);
5893 ins_cost(125);
5894 format %{ "FLDZ ST\n\t"
5895 "FSTP $dst" %}
5896 ins_encode %{
5897 __ fldz();
5898 __ fstp_d($dst$$reg);
5899 %}
5900 ins_pipe(fpu_reg_con);
5901 %}
5902
5903 // The instruction usage is guarded by predicate in operand immFPR1().
5904 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
5905 match(Set dst con);
5906 ins_cost(125);
5907 format %{ "FLD1 ST\n\t"
5908 "FSTP $dst" %}
5909 ins_encode %{
5910 __ fld1();
5911 __ fstp_d($dst$$reg);
5912 %}
5913 ins_pipe(fpu_reg_con);
5914 %}
5915
5916 // The instruction usage is guarded by predicate in operand immF().
5917 instruct loadConF(regF dst, immF con) %{
5918 match(Set dst con);
5919 ins_cost(125);
5920 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
5921 ins_encode %{
5922 __ movflt($dst$$XMMRegister, $constantaddress($con));
5923 %}
5924 ins_pipe(pipe_slow);
5925 %}
5926
5927 // The instruction usage is guarded by predicate in operand immF0().
5928 instruct loadConF0(regF dst, immF0 src) %{
5929 match(Set dst src);
5930 ins_cost(100);
5931 format %{ "XORPS $dst,$dst\t# float 0.0" %}
5932 ins_encode %{
5933 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5934 %}
5935 ins_pipe(pipe_slow);
5936 %}
5937
5938 // The instruction usage is guarded by predicate in operand immDPR().
5939 instruct loadConDPR(regDPR dst, immDPR con) %{
5940 match(Set dst con);
5941 ins_cost(125);
5942
5943 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
5944 "FSTP $dst" %}
5945 ins_encode %{
5946 __ fld_d($constantaddress($con));
5947 __ fstp_d($dst$$reg);
5948 %}
5949 ins_pipe(fpu_reg_con);
5950 %}
5951
5952 // The instruction usage is guarded by predicate in operand immDPR0().
5953 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
5954 match(Set dst con);
5955 ins_cost(125);
5956
5957 format %{ "FLDZ ST\n\t"
5958 "FSTP $dst" %}
5959 ins_encode %{
5960 __ fldz();
5961 __ fstp_d($dst$$reg);
5962 %}
5963 ins_pipe(fpu_reg_con);
5964 %}
5965
5966 // The instruction usage is guarded by predicate in operand immDPR1().
5967 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
5968 match(Set dst con);
5969 ins_cost(125);
5970
5971 format %{ "FLD1 ST\n\t"
5972 "FSTP $dst" %}
5973 ins_encode %{
5974 __ fld1();
5975 __ fstp_d($dst$$reg);
5976 %}
5977 ins_pipe(fpu_reg_con);
5978 %}
5979
5980 // The instruction usage is guarded by predicate in operand immD().
5981 instruct loadConD(regD dst, immD con) %{
5982 match(Set dst con);
5983 ins_cost(125);
5984 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
5985 ins_encode %{
5986 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5987 %}
5988 ins_pipe(pipe_slow);
5989 %}
5990
5991 // The instruction usage is guarded by predicate in operand immD0().
5992 instruct loadConD0(regD dst, immD0 src) %{
5993 match(Set dst src);
5994 ins_cost(100);
5995 format %{ "XORPD $dst,$dst\t# double 0.0" %}
5996 ins_encode %{
5997 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5998 %}
5999 ins_pipe( pipe_slow );
6000 %}
6001
6002 // Load Stack Slot
6003 instruct loadSSI(rRegI dst, stackSlotI src) %{
6004 match(Set dst src);
6005 ins_cost(125);
6006
6007 format %{ "MOV $dst,$src" %}
6008 opcode(0x8B);
6009 ins_encode( OpcP, RegMem(dst,src));
6010 ins_pipe( ialu_reg_mem );
6011 %}
6012
6013 instruct loadSSL(eRegL dst, stackSlotL src) %{
6014 match(Set dst src);
6015
6016 ins_cost(200);
6017 format %{ "MOV $dst,$src.lo\n\t"
6018 "MOV $dst+4,$src.hi" %}
6019 opcode(0x8B, 0x8B);
6020 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6021 ins_pipe( ialu_mem_long_reg );
6022 %}
6023
6024 // Load Stack Slot
6025 instruct loadSSP(eRegP dst, stackSlotP src) %{
6026 match(Set dst src);
6027 ins_cost(125);
6028
6029 format %{ "MOV $dst,$src" %}
6030 opcode(0x8B);
6031 ins_encode( OpcP, RegMem(dst,src));
6032 ins_pipe( ialu_reg_mem );
6033 %}
6034
6035 // Load Stack Slot
6036 instruct loadSSF(regFPR dst, stackSlotF src) %{
6037 match(Set dst src);
6038 ins_cost(125);
6039
6040 format %{ "FLD_S $src\n\t"
6041 "FSTP $dst" %}
6042 opcode(0xD9); /* D9 /0, FLD m32real */
6043 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6044 Pop_Reg_FPR(dst) );
6045 ins_pipe( fpu_reg_mem );
6046 %}
6047
6048 // Load Stack Slot
6049 instruct loadSSD(regDPR dst, stackSlotD src) %{
6050 match(Set dst src);
6051 ins_cost(125);
6052
6053 format %{ "FLD_D $src\n\t"
6054 "FSTP $dst" %}
6055 opcode(0xDD); /* DD /0, FLD m64real */
6056 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6057 Pop_Reg_DPR(dst) );
6058 ins_pipe( fpu_reg_mem );
6059 %}
6060
6061 // Prefetch instructions.
6062 // Must be safe to execute with invalid address (cannot fault).
6063
6064 instruct prefetchr0( memory mem ) %{
6065 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6066 match(PrefetchRead mem);
6067 ins_cost(0);
6068 size(0);
6069 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6070 ins_encode();
6071 ins_pipe(empty);
6072 %}
6073
6074 instruct prefetchr( memory mem ) %{
6075 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6076 match(PrefetchRead mem);
6077 ins_cost(100);
6078
6079 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6080 ins_encode %{
6081 __ prefetchr($mem$$Address);
6082 %}
6083 ins_pipe(ialu_mem);
6084 %}
6085
6086 instruct prefetchrNTA( memory mem ) %{
6087 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6088 match(PrefetchRead mem);
6089 ins_cost(100);
6090
6091 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6092 ins_encode %{
6093 __ prefetchnta($mem$$Address);
6094 %}
6095 ins_pipe(ialu_mem);
6096 %}
6097
6098 instruct prefetchrT0( memory mem ) %{
6099 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6100 match(PrefetchRead mem);
6101 ins_cost(100);
6102
6103 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6104 ins_encode %{
6105 __ prefetcht0($mem$$Address);
6106 %}
6107 ins_pipe(ialu_mem);
6108 %}
6109
6110 instruct prefetchrT2( memory mem ) %{
6111 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6112 match(PrefetchRead mem);
6113 ins_cost(100);
6114
6115 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6116 ins_encode %{
6117 __ prefetcht2($mem$$Address);
6118 %}
6119 ins_pipe(ialu_mem);
6120 %}
6121
6122 instruct prefetchw0( memory mem ) %{
6123 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6124 match(PrefetchWrite mem);
6125 ins_cost(0);
6126 size(0);
6127 format %{ "Prefetch (non-SSE is empty encoding)" %}
6128 ins_encode();
6129 ins_pipe(empty);
6130 %}
6131
6132 instruct prefetchw( memory mem ) %{
6133 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6134 match( PrefetchWrite mem );
6135 ins_cost(100);
6136
6137 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6138 ins_encode %{
6139 __ prefetchw($mem$$Address);
6140 %}
6141 ins_pipe(ialu_mem);
6142 %}
6143
6144 instruct prefetchwNTA( memory mem ) %{
6145 predicate(UseSSE>=1);
6146 match(PrefetchWrite mem);
6147 ins_cost(100);
6148
6149 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6150 ins_encode %{
6151 __ prefetchnta($mem$$Address);
6152 %}
6153 ins_pipe(ialu_mem);
6154 %}
6155
6156 // Prefetch instructions for allocation.
6157
6158 instruct prefetchAlloc0( memory mem ) %{
6159 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6160 match(PrefetchAllocation mem);
6161 ins_cost(0);
6162 size(0);
6163 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6164 ins_encode();
6165 ins_pipe(empty);
6166 %}
6167
6168 instruct prefetchAlloc( memory mem ) %{
6169 predicate(AllocatePrefetchInstr==3);
6170 match( PrefetchAllocation mem );
6171 ins_cost(100);
6172
6173 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6174 ins_encode %{
6175 __ prefetchw($mem$$Address);
6176 %}
6177 ins_pipe(ialu_mem);
6178 %}
6179
6180 instruct prefetchAllocNTA( memory mem ) %{
6181 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6182 match(PrefetchAllocation mem);
6183 ins_cost(100);
6184
6185 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6186 ins_encode %{
6187 __ prefetchnta($mem$$Address);
6188 %}
6189 ins_pipe(ialu_mem);
6190 %}
6191
6192 instruct prefetchAllocT0( memory mem ) %{
6193 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6194 match(PrefetchAllocation mem);
6195 ins_cost(100);
6196
6197 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6198 ins_encode %{
6199 __ prefetcht0($mem$$Address);
6200 %}
6201 ins_pipe(ialu_mem);
6202 %}
6203
6204 instruct prefetchAllocT2( memory mem ) %{
6205 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6206 match(PrefetchAllocation mem);
6207 ins_cost(100);
6208
6209 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6210 ins_encode %{
6211 __ prefetcht2($mem$$Address);
6212 %}
6213 ins_pipe(ialu_mem);
6214 %}
6215
6216 //----------Store Instructions-------------------------------------------------
6217
6218 // Store Byte
6219 instruct storeB(memory mem, xRegI src) %{
6220 match(Set mem (StoreB mem src));
6221
6222 ins_cost(125);
6223 format %{ "MOV8 $mem,$src" %}
6224 opcode(0x88);
6225 ins_encode( OpcP, RegMem( src, mem ) );
6226 ins_pipe( ialu_mem_reg );
6227 %}
6228
6229 // Store Char/Short
6230 instruct storeC(memory mem, rRegI src) %{
6231 match(Set mem (StoreC mem src));
6232
6233 ins_cost(125);
6234 format %{ "MOV16 $mem,$src" %}
6235 opcode(0x89, 0x66);
6236 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6237 ins_pipe( ialu_mem_reg );
6238 %}
6239
6240 // Store Integer
6241 instruct storeI(memory mem, rRegI src) %{
6242 match(Set mem (StoreI mem src));
6243
6244 ins_cost(125);
6245 format %{ "MOV $mem,$src" %}
6246 opcode(0x89);
6247 ins_encode( OpcP, RegMem( src, mem ) );
6248 ins_pipe( ialu_mem_reg );
6249 %}
6250
6251 // Store Long
6252 instruct storeL(long_memory mem, eRegL src) %{
6253 predicate(!((StoreLNode*)n)->require_atomic_access());
6254 match(Set mem (StoreL mem src));
6255
6256 ins_cost(200);
6257 format %{ "MOV $mem,$src.lo\n\t"
6258 "MOV $mem+4,$src.hi" %}
6259 opcode(0x89, 0x89);
6260 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6261 ins_pipe( ialu_mem_long_reg );
6262 %}
6263
6264 // Store Long to Integer
6265 instruct storeL2I(memory mem, eRegL src) %{
6266 match(Set mem (StoreI mem (ConvL2I src)));
6267
6268 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6269 ins_encode %{
6270 __ movl($mem$$Address, $src$$Register);
6271 %}
6272 ins_pipe(ialu_mem_reg);
6273 %}
6274
6275 // Volatile Store Long. Must be atomic, so move it into
6276 // the FP TOS and then do a 64-bit FIST. Has to probe the
6277 // target address before the store (for null-ptr checks)
6278 // so the memory operand is used twice in the encoding.
6279 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6280 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6281 match(Set mem (StoreL mem src));
6282 effect( KILL cr );
6283 ins_cost(400);
6284 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6285 "FILD $src\n\t"
6286 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6287 opcode(0x3B);
6288 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6289 ins_pipe( fpu_reg_mem );
6290 %}
6291
6292 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6293 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6294 match(Set mem (StoreL mem src));
6295 effect( TEMP tmp, KILL cr );
6296 ins_cost(380);
6297 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6298 "MOVSD $tmp,$src\n\t"
6299 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6300 ins_encode %{
6301 __ cmpl(rax, $mem$$Address);
6302 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6303 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6304 %}
6305 ins_pipe( pipe_slow );
6306 %}
6307
6308 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6309 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6310 match(Set mem (StoreL mem src));
6311 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6312 ins_cost(360);
6313 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6314 "MOVD $tmp,$src.lo\n\t"
6315 "MOVD $tmp2,$src.hi\n\t"
6316 "PUNPCKLDQ $tmp,$tmp2\n\t"
6317 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6318 ins_encode %{
6319 __ cmpl(rax, $mem$$Address);
6320 __ movdl($tmp$$XMMRegister, $src$$Register);
6321 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6322 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6323 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6324 %}
6325 ins_pipe( pipe_slow );
6326 %}
6327
6328 // Store Pointer; for storing unknown oops and raw pointers
6329 instruct storeP(memory mem, anyRegP src) %{
6330 match(Set mem (StoreP mem src));
6331
6332 ins_cost(125);
6333 format %{ "MOV $mem,$src" %}
6334 opcode(0x89);
6335 ins_encode( OpcP, RegMem( src, mem ) );
6336 ins_pipe( ialu_mem_reg );
6337 %}
6338
6339 // Store Integer Immediate
6340 instruct storeImmI(memory mem, immI src) %{
6341 match(Set mem (StoreI mem src));
6342
6343 ins_cost(150);
6344 format %{ "MOV $mem,$src" %}
6345 opcode(0xC7); /* C7 /0 */
6346 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6347 ins_pipe( ialu_mem_imm );
6348 %}
6349
6350 // Store Short/Char Immediate
6351 instruct storeImmI16(memory mem, immI16 src) %{
6352 predicate(UseStoreImmI16);
6353 match(Set mem (StoreC mem src));
6354
6355 ins_cost(150);
6356 format %{ "MOV16 $mem,$src" %}
6357 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6358 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6359 ins_pipe( ialu_mem_imm );
6360 %}
6361
6362 // Store Pointer Immediate; null pointers or constant oops that do not
6363 // need card-mark barriers.
6364 instruct storeImmP(memory mem, immP src) %{
6365 match(Set mem (StoreP mem src));
6366
6367 ins_cost(150);
6368 format %{ "MOV $mem,$src" %}
6369 opcode(0xC7); /* C7 /0 */
6370 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6371 ins_pipe( ialu_mem_imm );
6372 %}
6373
6374 // Store Byte Immediate
6375 instruct storeImmB(memory mem, immI8 src) %{
6376 match(Set mem (StoreB mem src));
6377
6378 ins_cost(150);
6379 format %{ "MOV8 $mem,$src" %}
6380 opcode(0xC6); /* C6 /0 */
6381 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6382 ins_pipe( ialu_mem_imm );
6383 %}
6384
6385 // Store CMS card-mark Immediate
6386 instruct storeImmCM(memory mem, immI8 src) %{
6387 match(Set mem (StoreCM mem src));
6388
6389 ins_cost(150);
6390 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6391 opcode(0xC6); /* C6 /0 */
6392 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6393 ins_pipe( ialu_mem_imm );
6394 %}
6395
6396 // Store Double
6397 instruct storeDPR( memory mem, regDPR1 src) %{
6398 predicate(UseSSE<=1);
6399 match(Set mem (StoreD mem src));
6400
6401 ins_cost(100);
6402 format %{ "FST_D $mem,$src" %}
6403 opcode(0xDD); /* DD /2 */
6404 ins_encode( enc_FPR_store(mem,src) );
6405 ins_pipe( fpu_mem_reg );
6406 %}
6407
6408 // Store double does rounding on x86
6409 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6410 predicate(UseSSE<=1);
6411 match(Set mem (StoreD mem (RoundDouble src)));
6412
6413 ins_cost(100);
6414 format %{ "FST_D $mem,$src\t# round" %}
6415 opcode(0xDD); /* DD /2 */
6416 ins_encode( enc_FPR_store(mem,src) );
6417 ins_pipe( fpu_mem_reg );
6418 %}
6419
6420 // Store XMM register to memory (double-precision floating points)
6421 // MOVSD instruction
6422 instruct storeD(memory mem, regD src) %{
6423 predicate(UseSSE>=2);
6424 match(Set mem (StoreD mem src));
6425 ins_cost(95);
6426 format %{ "MOVSD $mem,$src" %}
6427 ins_encode %{
6428 __ movdbl($mem$$Address, $src$$XMMRegister);
6429 %}
6430 ins_pipe( pipe_slow );
6431 %}
6432
6433 // Store XMM register to memory (single-precision floating point)
6434 // MOVSS instruction
6435 instruct storeF(memory mem, regF src) %{
6436 predicate(UseSSE>=1);
6437 match(Set mem (StoreF mem src));
6438 ins_cost(95);
6439 format %{ "MOVSS $mem,$src" %}
6440 ins_encode %{
6441 __ movflt($mem$$Address, $src$$XMMRegister);
6442 %}
6443 ins_pipe( pipe_slow );
6444 %}
6445
6446 // Store Float
6447 instruct storeFPR( memory mem, regFPR1 src) %{
6448 predicate(UseSSE==0);
6449 match(Set mem (StoreF mem src));
6450
6451 ins_cost(100);
6452 format %{ "FST_S $mem,$src" %}
6453 opcode(0xD9); /* D9 /2 */
6454 ins_encode( enc_FPR_store(mem,src) );
6455 ins_pipe( fpu_mem_reg );
6456 %}
6457
6458 // Store Float does rounding on x86
6459 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6460 predicate(UseSSE==0);
6461 match(Set mem (StoreF mem (RoundFloat src)));
6462
6463 ins_cost(100);
6464 format %{ "FST_S $mem,$src\t# round" %}
6465 opcode(0xD9); /* D9 /2 */
6466 ins_encode( enc_FPR_store(mem,src) );
6467 ins_pipe( fpu_mem_reg );
6468 %}
6469
6470 // Store Float does rounding on x86
6471 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6472 predicate(UseSSE<=1);
6473 match(Set mem (StoreF mem (ConvD2F src)));
6474
6475 ins_cost(100);
6476 format %{ "FST_S $mem,$src\t# D-round" %}
6477 opcode(0xD9); /* D9 /2 */
6478 ins_encode( enc_FPR_store(mem,src) );
6479 ins_pipe( fpu_mem_reg );
6480 %}
6481
6482 // Store immediate Float value (it is faster than store from FPU register)
6483 // The instruction usage is guarded by predicate in operand immFPR().
6484 instruct storeFPR_imm( memory mem, immFPR src) %{
6485 match(Set mem (StoreF mem src));
6486
6487 ins_cost(50);
6488 format %{ "MOV $mem,$src\t# store float" %}
6489 opcode(0xC7); /* C7 /0 */
6490 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
6491 ins_pipe( ialu_mem_imm );
6492 %}
6493
6494 // Store immediate Float value (it is faster than store from XMM register)
6495 // The instruction usage is guarded by predicate in operand immF().
6496 instruct storeF_imm( memory mem, immF src) %{
6497 match(Set mem (StoreF mem src));
6498
6499 ins_cost(50);
6500 format %{ "MOV $mem,$src\t# store float" %}
6501 opcode(0xC7); /* C7 /0 */
6502 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
6503 ins_pipe( ialu_mem_imm );
6504 %}
6505
6506 // Store Integer to stack slot
6507 instruct storeSSI(stackSlotI dst, rRegI src) %{
6508 match(Set dst src);
6509
6510 ins_cost(100);
6511 format %{ "MOV $dst,$src" %}
6512 opcode(0x89);
6513 ins_encode( OpcPRegSS( dst, src ) );
6514 ins_pipe( ialu_mem_reg );
6515 %}
6516
6517 // Store Integer to stack slot
6518 instruct storeSSP(stackSlotP dst, eRegP src) %{
6519 match(Set dst src);
6520
6521 ins_cost(100);
6522 format %{ "MOV $dst,$src" %}
6523 opcode(0x89);
6524 ins_encode( OpcPRegSS( dst, src ) );
6525 ins_pipe( ialu_mem_reg );
6526 %}
6527
6528 // Store Long to stack slot
6529 instruct storeSSL(stackSlotL dst, eRegL src) %{
6530 match(Set dst src);
6531
6532 ins_cost(200);
6533 format %{ "MOV $dst,$src.lo\n\t"
6534 "MOV $dst+4,$src.hi" %}
6535 opcode(0x89, 0x89);
6536 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
6537 ins_pipe( ialu_mem_long_reg );
6538 %}
6539
6540 //----------MemBar Instructions-----------------------------------------------
6541 // Memory barrier flavors
6542
6543 instruct membar_acquire() %{
6544 match(MemBarAcquire);
6545 match(LoadFence);
6546 ins_cost(400);
6547
6548 size(0);
6549 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6550 ins_encode();
6551 ins_pipe(empty);
6552 %}
6553
6554 instruct membar_acquire_lock() %{
6555 match(MemBarAcquireLock);
6556 ins_cost(0);
6557
6558 size(0);
6559 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6560 ins_encode( );
6561 ins_pipe(empty);
6562 %}
6563
6564 instruct membar_release() %{
6565 match(MemBarRelease);
6566 match(StoreFence);
6567 ins_cost(400);
6568
6569 size(0);
6570 format %{ "MEMBAR-release ! (empty encoding)" %}
6571 ins_encode( );
6572 ins_pipe(empty);
6573 %}
6574
6575 instruct membar_release_lock() %{
6576 match(MemBarReleaseLock);
6577 ins_cost(0);
6578
6579 size(0);
6580 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6581 ins_encode( );
6582 ins_pipe(empty);
6583 %}
6584
6585 instruct membar_volatile(eFlagsReg cr) %{
6586 match(MemBarVolatile);
6587 effect(KILL cr);
6588 ins_cost(400);
6589
6590 format %{
6591 $$template
6592 if (os::is_MP()) {
6593 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
6594 } else {
6595 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6596 }
6597 %}
6598 ins_encode %{
6599 __ membar(Assembler::StoreLoad);
6600 %}
6601 ins_pipe(pipe_slow);
6602 %}
6603
6604 instruct unnecessary_membar_volatile() %{
6605 match(MemBarVolatile);
6606 predicate(Matcher::post_store_load_barrier(n));
6607 ins_cost(0);
6608
6609 size(0);
6610 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6611 ins_encode( );
6612 ins_pipe(empty);
6613 %}
6614
6615 instruct membar_storestore() %{
6616 match(MemBarStoreStore);
6617 ins_cost(0);
6618
6619 size(0);
6620 format %{ "MEMBAR-storestore (empty encoding)" %}
6621 ins_encode( );
6622 ins_pipe(empty);
6623 %}
6624
6625 //----------Move Instructions--------------------------------------------------
6626 instruct castX2P(eAXRegP dst, eAXRegI src) %{
6627 match(Set dst (CastX2P src));
6628 format %{ "# X2P $dst, $src" %}
6629 ins_encode( /*empty encoding*/ );
6630 ins_cost(0);
6631 ins_pipe(empty);
6632 %}
6633
6634 instruct castP2X(rRegI dst, eRegP src ) %{
6635 match(Set dst (CastP2X src));
6636 ins_cost(50);
6637 format %{ "MOV $dst, $src\t# CastP2X" %}
6638 ins_encode( enc_Copy( dst, src) );
6639 ins_pipe( ialu_reg_reg );
6640 %}
6641
6642 //----------Conditional Move---------------------------------------------------
6643 // Conditional move
6644 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
6645 predicate(!VM_Version::supports_cmov() );
6646 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6647 ins_cost(200);
6648 format %{ "J$cop,us skip\t# signed cmove\n\t"
6649 "MOV $dst,$src\n"
6650 "skip:" %}
6651 ins_encode %{
6652 Label Lskip;
6653 // Invert sense of branch from sense of CMOV
6654 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6655 __ movl($dst$$Register, $src$$Register);
6656 __ bind(Lskip);
6657 %}
6658 ins_pipe( pipe_cmov_reg );
6659 %}
6660
6661 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
6662 predicate(!VM_Version::supports_cmov() );
6663 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6664 ins_cost(200);
6665 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
6666 "MOV $dst,$src\n"
6667 "skip:" %}
6668 ins_encode %{
6669 Label Lskip;
6670 // Invert sense of branch from sense of CMOV
6671 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6672 __ movl($dst$$Register, $src$$Register);
6673 __ bind(Lskip);
6674 %}
6675 ins_pipe( pipe_cmov_reg );
6676 %}
6677
6678 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
6679 predicate(VM_Version::supports_cmov() );
6680 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6681 ins_cost(200);
6682 format %{ "CMOV$cop $dst,$src" %}
6683 opcode(0x0F,0x40);
6684 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6685 ins_pipe( pipe_cmov_reg );
6686 %}
6687
6688 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
6689 predicate(VM_Version::supports_cmov() );
6690 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6691 ins_cost(200);
6692 format %{ "CMOV$cop $dst,$src" %}
6693 opcode(0x0F,0x40);
6694 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6695 ins_pipe( pipe_cmov_reg );
6696 %}
6697
6698 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
6699 predicate(VM_Version::supports_cmov() );
6700 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6701 ins_cost(200);
6702 expand %{
6703 cmovI_regU(cop, cr, dst, src);
6704 %}
6705 %}
6706
6707 // Conditional move
6708 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
6709 predicate(VM_Version::supports_cmov() );
6710 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6711 ins_cost(250);
6712 format %{ "CMOV$cop $dst,$src" %}
6713 opcode(0x0F,0x40);
6714 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6715 ins_pipe( pipe_cmov_mem );
6716 %}
6717
6718 // Conditional move
6719 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
6720 predicate(VM_Version::supports_cmov() );
6721 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6722 ins_cost(250);
6723 format %{ "CMOV$cop $dst,$src" %}
6724 opcode(0x0F,0x40);
6725 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6726 ins_pipe( pipe_cmov_mem );
6727 %}
6728
6729 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
6730 predicate(VM_Version::supports_cmov() );
6731 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6732 ins_cost(250);
6733 expand %{
6734 cmovI_memU(cop, cr, dst, src);
6735 %}
6736 %}
6737
6738 // Conditional move
6739 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6740 predicate(VM_Version::supports_cmov() );
6741 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6742 ins_cost(200);
6743 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6744 opcode(0x0F,0x40);
6745 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6746 ins_pipe( pipe_cmov_reg );
6747 %}
6748
6749 // Conditional move (non-P6 version)
6750 // Note: a CMoveP is generated for stubs and native wrappers
6751 // regardless of whether we are on a P6, so we
6752 // emulate a cmov here
6753 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6754 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6755 ins_cost(300);
6756 format %{ "Jn$cop skip\n\t"
6757 "MOV $dst,$src\t# pointer\n"
6758 "skip:" %}
6759 opcode(0x8b);
6760 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
6761 ins_pipe( pipe_cmov_reg );
6762 %}
6763
6764 // Conditional move
6765 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
6766 predicate(VM_Version::supports_cmov() );
6767 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6768 ins_cost(200);
6769 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6770 opcode(0x0F,0x40);
6771 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6772 ins_pipe( pipe_cmov_reg );
6773 %}
6774
6775 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
6776 predicate(VM_Version::supports_cmov() );
6777 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6778 ins_cost(200);
6779 expand %{
6780 cmovP_regU(cop, cr, dst, src);
6781 %}
6782 %}
6783
6784 // DISABLED: Requires the ADLC to emit a bottom_type call that
6785 // correctly meets the two pointer arguments; one is an incoming
6786 // register but the other is a memory operand. ALSO appears to
6787 // be buggy with implicit null checks.
6788 //
6789 //// Conditional move
6790 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
6791 // predicate(VM_Version::supports_cmov() );
6792 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6793 // ins_cost(250);
6794 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6795 // opcode(0x0F,0x40);
6796 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6797 // ins_pipe( pipe_cmov_mem );
6798 //%}
6799 //
6800 //// Conditional move
6801 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
6802 // predicate(VM_Version::supports_cmov() );
6803 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6804 // ins_cost(250);
6805 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6806 // opcode(0x0F,0x40);
6807 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6808 // ins_pipe( pipe_cmov_mem );
6809 //%}
6810
6811 // Conditional move
6812 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
6813 predicate(UseSSE<=1);
6814 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6815 ins_cost(200);
6816 format %{ "FCMOV$cop $dst,$src\t# double" %}
6817 opcode(0xDA);
6818 ins_encode( enc_cmov_dpr(cop,src) );
6819 ins_pipe( pipe_cmovDPR_reg );
6820 %}
6821
6822 // Conditional move
6823 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
6824 predicate(UseSSE==0);
6825 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6826 ins_cost(200);
6827 format %{ "FCMOV$cop $dst,$src\t# float" %}
6828 opcode(0xDA);
6829 ins_encode( enc_cmov_dpr(cop,src) );
6830 ins_pipe( pipe_cmovDPR_reg );
6831 %}
6832
6833 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6834 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
6835 predicate(UseSSE<=1);
6836 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6837 ins_cost(200);
6838 format %{ "Jn$cop skip\n\t"
6839 "MOV $dst,$src\t# double\n"
6840 "skip:" %}
6841 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6842 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
6843 ins_pipe( pipe_cmovDPR_reg );
6844 %}
6845
6846 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6847 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
6848 predicate(UseSSE==0);
6849 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6850 ins_cost(200);
6851 format %{ "Jn$cop skip\n\t"
6852 "MOV $dst,$src\t# float\n"
6853 "skip:" %}
6854 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6855 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
6856 ins_pipe( pipe_cmovDPR_reg );
6857 %}
6858
6859 // No CMOVE with SSE/SSE2
6860 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
6861 predicate (UseSSE>=1);
6862 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6863 ins_cost(200);
6864 format %{ "Jn$cop skip\n\t"
6865 "MOVSS $dst,$src\t# float\n"
6866 "skip:" %}
6867 ins_encode %{
6868 Label skip;
6869 // Invert sense of branch from sense of CMOV
6870 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6871 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6872 __ bind(skip);
6873 %}
6874 ins_pipe( pipe_slow );
6875 %}
6876
6877 // No CMOVE with SSE/SSE2
6878 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
6879 predicate (UseSSE>=2);
6880 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6881 ins_cost(200);
6882 format %{ "Jn$cop skip\n\t"
6883 "MOVSD $dst,$src\t# float\n"
6884 "skip:" %}
6885 ins_encode %{
6886 Label skip;
6887 // Invert sense of branch from sense of CMOV
6888 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6889 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6890 __ bind(skip);
6891 %}
6892 ins_pipe( pipe_slow );
6893 %}
6894
6895 // unsigned version
6896 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
6897 predicate (UseSSE>=1);
6898 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6899 ins_cost(200);
6900 format %{ "Jn$cop skip\n\t"
6901 "MOVSS $dst,$src\t# float\n"
6902 "skip:" %}
6903 ins_encode %{
6904 Label skip;
6905 // Invert sense of branch from sense of CMOV
6906 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6907 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6908 __ bind(skip);
6909 %}
6910 ins_pipe( pipe_slow );
6911 %}
6912
6913 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
6914 predicate (UseSSE>=1);
6915 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6916 ins_cost(200);
6917 expand %{
6918 fcmovF_regU(cop, cr, dst, src);
6919 %}
6920 %}
6921
6922 // unsigned version
6923 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
6924 predicate (UseSSE>=2);
6925 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6926 ins_cost(200);
6927 format %{ "Jn$cop skip\n\t"
6928 "MOVSD $dst,$src\t# float\n"
6929 "skip:" %}
6930 ins_encode %{
6931 Label skip;
6932 // Invert sense of branch from sense of CMOV
6933 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6934 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6935 __ bind(skip);
6936 %}
6937 ins_pipe( pipe_slow );
6938 %}
6939
6940 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
6941 predicate (UseSSE>=2);
6942 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6943 ins_cost(200);
6944 expand %{
6945 fcmovD_regU(cop, cr, dst, src);
6946 %}
6947 %}
6948
6949 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
6950 predicate(VM_Version::supports_cmov() );
6951 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6952 ins_cost(200);
6953 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6954 "CMOV$cop $dst.hi,$src.hi" %}
6955 opcode(0x0F,0x40);
6956 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6957 ins_pipe( pipe_cmov_reg_long );
6958 %}
6959
6960 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
6961 predicate(VM_Version::supports_cmov() );
6962 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6963 ins_cost(200);
6964 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6965 "CMOV$cop $dst.hi,$src.hi" %}
6966 opcode(0x0F,0x40);
6967 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6968 ins_pipe( pipe_cmov_reg_long );
6969 %}
6970
6971 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
6972 predicate(VM_Version::supports_cmov() );
6973 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6974 ins_cost(200);
6975 expand %{
6976 cmovL_regU(cop, cr, dst, src);
6977 %}
6978 %}
6979
6980 //----------Arithmetic Instructions--------------------------------------------
6981 //----------Addition Instructions----------------------------------------------
6982
6983 // Integer Addition Instructions
6984 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
6985 match(Set dst (AddI dst src));
6986 effect(KILL cr);
6987
6988 size(2);
6989 format %{ "ADD $dst,$src" %}
6990 opcode(0x03);
6991 ins_encode( OpcP, RegReg( dst, src) );
6992 ins_pipe( ialu_reg_reg );
6993 %}
6994
6995 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
6996 match(Set dst (AddI dst src));
6997 effect(KILL cr);
6998
6999 format %{ "ADD $dst,$src" %}
7000 opcode(0x81, 0x00); /* /0 id */
7001 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7002 ins_pipe( ialu_reg );
7003 %}
7004
7005 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7006 predicate(UseIncDec);
7007 match(Set dst (AddI dst src));
7008 effect(KILL cr);
7009
7010 size(1);
7011 format %{ "INC $dst" %}
7012 opcode(0x40); /* */
7013 ins_encode( Opc_plus( primary, dst ) );
7014 ins_pipe( ialu_reg );
7015 %}
7016
7017 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7018 match(Set dst (AddI src0 src1));
7019 ins_cost(110);
7020
7021 format %{ "LEA $dst,[$src0 + $src1]" %}
7022 opcode(0x8D); /* 0x8D /r */
7023 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7024 ins_pipe( ialu_reg_reg );
7025 %}
7026
7027 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7028 match(Set dst (AddP src0 src1));
7029 ins_cost(110);
7030
7031 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7032 opcode(0x8D); /* 0x8D /r */
7033 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7034 ins_pipe( ialu_reg_reg );
7035 %}
7036
7037 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7038 predicate(UseIncDec);
7039 match(Set dst (AddI dst src));
7040 effect(KILL cr);
7041
7042 size(1);
7043 format %{ "DEC $dst" %}
7044 opcode(0x48); /* */
7045 ins_encode( Opc_plus( primary, dst ) );
7046 ins_pipe( ialu_reg );
7047 %}
7048
7049 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7050 match(Set dst (AddP dst src));
7051 effect(KILL cr);
7052
7053 size(2);
7054 format %{ "ADD $dst,$src" %}
7055 opcode(0x03);
7056 ins_encode( OpcP, RegReg( dst, src) );
7057 ins_pipe( ialu_reg_reg );
7058 %}
7059
7060 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7061 match(Set dst (AddP dst src));
7062 effect(KILL cr);
7063
7064 format %{ "ADD $dst,$src" %}
7065 opcode(0x81,0x00); /* Opcode 81 /0 id */
7066 // ins_encode( RegImm( dst, src) );
7067 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7068 ins_pipe( ialu_reg );
7069 %}
7070
7071 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7072 match(Set dst (AddI dst (LoadI src)));
7073 effect(KILL cr);
7074
7075 ins_cost(125);
7076 format %{ "ADD $dst,$src" %}
7077 opcode(0x03);
7078 ins_encode( OpcP, RegMem( dst, src) );
7079 ins_pipe( ialu_reg_mem );
7080 %}
7081
7082 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7083 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7084 effect(KILL cr);
7085
7086 ins_cost(150);
7087 format %{ "ADD $dst,$src" %}
7088 opcode(0x01); /* Opcode 01 /r */
7089 ins_encode( OpcP, RegMem( src, dst ) );
7090 ins_pipe( ialu_mem_reg );
7091 %}
7092
7093 // Add Memory with Immediate
7094 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7095 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7096 effect(KILL cr);
7097
7098 ins_cost(125);
7099 format %{ "ADD $dst,$src" %}
7100 opcode(0x81); /* Opcode 81 /0 id */
7101 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7102 ins_pipe( ialu_mem_imm );
7103 %}
7104
7105 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7106 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7107 effect(KILL cr);
7108
7109 ins_cost(125);
7110 format %{ "INC $dst" %}
7111 opcode(0xFF); /* Opcode FF /0 */
7112 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7113 ins_pipe( ialu_mem_imm );
7114 %}
7115
7116 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7117 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7118 effect(KILL cr);
7119
7120 ins_cost(125);
7121 format %{ "DEC $dst" %}
7122 opcode(0xFF); /* Opcode FF /1 */
7123 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7124 ins_pipe( ialu_mem_imm );
7125 %}
7126
7127
7128 instruct checkCastPP( eRegP dst ) %{
7129 match(Set dst (CheckCastPP dst));
7130
7131 size(0);
7132 format %{ "#checkcastPP of $dst" %}
7133 ins_encode( /*empty encoding*/ );
7134 ins_pipe( empty );
7135 %}
7136
7137 instruct castPP( eRegP dst ) %{
7138 match(Set dst (CastPP dst));
7139 format %{ "#castPP of $dst" %}
7140 ins_encode( /*empty encoding*/ );
7141 ins_pipe( empty );
7142 %}
7143
7144 instruct castII( rRegI dst ) %{
7145 match(Set dst (CastII dst));
7146 format %{ "#castII of $dst" %}
7147 ins_encode( /*empty encoding*/ );
7148 ins_cost(0);
7149 ins_pipe( empty );
7150 %}
7151
7152
7153 // Load-locked - same as a regular pointer load when used with compare-swap
7154 instruct loadPLocked(eRegP dst, memory mem) %{
7155 match(Set dst (LoadPLocked mem));
7156
7157 ins_cost(125);
7158 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7159 opcode(0x8B);
7160 ins_encode( OpcP, RegMem(dst,mem));
7161 ins_pipe( ialu_reg_mem );
7162 %}
7163
7164 // Conditional-store of the updated heap-top.
7165 // Used during allocation of the shared heap.
7166 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7167 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7168 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7169 // EAX is killed if there is contention, but then it's also unused.
7170 // In the common case of no contention, EAX holds the new oop address.
7171 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7172 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7173 ins_pipe( pipe_cmpxchg );
7174 %}
7175
7176 // Conditional-store of an int value.
7177 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7178 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7179 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7180 effect(KILL oldval);
7181 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7182 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7183 ins_pipe( pipe_cmpxchg );
7184 %}
7185
7186 // Conditional-store of a long value.
7187 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7188 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7189 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7190 effect(KILL oldval);
7191 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7192 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7193 "XCHG EBX,ECX"
7194 %}
7195 ins_encode %{
7196 // Note: we need to swap rbx, and rcx before and after the
7197 // cmpxchg8 instruction because the instruction uses
7198 // rcx as the high order word of the new value to store but
7199 // our register encoding uses rbx.
7200 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7201 if( os::is_MP() )
7202 __ lock();
7203 __ cmpxchg8($mem$$Address);
7204 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7205 %}
7206 ins_pipe( pipe_cmpxchg );
7207 %}
7208
7209 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7210
7211 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7212 predicate(VM_Version::supports_cx8());
7213 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7214 effect(KILL cr, KILL oldval);
7215 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7216 "MOV $res,0\n\t"
7217 "JNE,s fail\n\t"
7218 "MOV $res,1\n"
7219 "fail:" %}
7220 ins_encode( enc_cmpxchg8(mem_ptr),
7221 enc_flags_ne_to_boolean(res) );
7222 ins_pipe( pipe_cmpxchg );
7223 %}
7224
7225 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7226 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7227 effect(KILL cr, KILL oldval);
7228 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7229 "MOV $res,0\n\t"
7230 "JNE,s fail\n\t"
7231 "MOV $res,1\n"
7232 "fail:" %}
7233 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7234 ins_pipe( pipe_cmpxchg );
7235 %}
7236
7237 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7238 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7239 effect(KILL cr, KILL oldval);
7240 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7241 "MOV $res,0\n\t"
7242 "JNE,s fail\n\t"
7243 "MOV $res,1\n"
7244 "fail:" %}
7245 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7246 ins_pipe( pipe_cmpxchg );
7247 %}
7248
7249 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7250 predicate(n->as_LoadStore()->result_not_used());
7251 match(Set dummy (GetAndAddI mem add));
7252 effect(KILL cr);
7253 format %{ "ADDL [$mem],$add" %}
7254 ins_encode %{
7255 if (os::is_MP()) { __ lock(); }
7256 __ addl($mem$$Address, $add$$constant);
7257 %}
7258 ins_pipe( pipe_cmpxchg );
7259 %}
7260
7261 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7262 match(Set newval (GetAndAddI mem newval));
7263 effect(KILL cr);
7264 format %{ "XADDL [$mem],$newval" %}
7265 ins_encode %{
7266 if (os::is_MP()) { __ lock(); }
7267 __ xaddl($mem$$Address, $newval$$Register);
7268 %}
7269 ins_pipe( pipe_cmpxchg );
7270 %}
7271
7272 instruct xchgI( memory mem, rRegI newval) %{
7273 match(Set newval (GetAndSetI mem newval));
7274 format %{ "XCHGL $newval,[$mem]" %}
7275 ins_encode %{
7276 __ xchgl($newval$$Register, $mem$$Address);
7277 %}
7278 ins_pipe( pipe_cmpxchg );
7279 %}
7280
7281 instruct xchgP( memory mem, pRegP newval) %{
7282 match(Set newval (GetAndSetP mem newval));
7283 format %{ "XCHGL $newval,[$mem]" %}
7284 ins_encode %{
7285 __ xchgl($newval$$Register, $mem$$Address);
7286 %}
7287 ins_pipe( pipe_cmpxchg );
7288 %}
7289
7290 //----------Subtraction Instructions-------------------------------------------
7291
7292 // Integer Subtraction Instructions
7293 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7294 match(Set dst (SubI dst src));
7295 effect(KILL cr);
7296
7297 size(2);
7298 format %{ "SUB $dst,$src" %}
7299 opcode(0x2B);
7300 ins_encode( OpcP, RegReg( dst, src) );
7301 ins_pipe( ialu_reg_reg );
7302 %}
7303
7304 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7305 match(Set dst (SubI dst src));
7306 effect(KILL cr);
7307
7308 format %{ "SUB $dst,$src" %}
7309 opcode(0x81,0x05); /* Opcode 81 /5 */
7310 // ins_encode( RegImm( dst, src) );
7311 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7312 ins_pipe( ialu_reg );
7313 %}
7314
7315 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7316 match(Set dst (SubI dst (LoadI src)));
7317 effect(KILL cr);
7318
7319 ins_cost(125);
7320 format %{ "SUB $dst,$src" %}
7321 opcode(0x2B);
7322 ins_encode( OpcP, RegMem( dst, src) );
7323 ins_pipe( ialu_reg_mem );
7324 %}
7325
7326 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7327 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7328 effect(KILL cr);
7329
7330 ins_cost(150);
7331 format %{ "SUB $dst,$src" %}
7332 opcode(0x29); /* Opcode 29 /r */
7333 ins_encode( OpcP, RegMem( src, dst ) );
7334 ins_pipe( ialu_mem_reg );
7335 %}
7336
7337 // Subtract from a pointer
7338 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7339 match(Set dst (AddP dst (SubI zero src)));
7340 effect(KILL cr);
7341
7342 size(2);
7343 format %{ "SUB $dst,$src" %}
7344 opcode(0x2B);
7345 ins_encode( OpcP, RegReg( dst, src) );
7346 ins_pipe( ialu_reg_reg );
7347 %}
7348
7349 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7350 match(Set dst (SubI zero dst));
7351 effect(KILL cr);
7352
7353 size(2);
7354 format %{ "NEG $dst" %}
7355 opcode(0xF7,0x03); // Opcode F7 /3
7356 ins_encode( OpcP, RegOpc( dst ) );
7357 ins_pipe( ialu_reg );
7358 %}
7359
7360 //----------Multiplication/Division Instructions-------------------------------
7361 // Integer Multiplication Instructions
7362 // Multiply Register
7363 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7364 match(Set dst (MulI dst src));
7365 effect(KILL cr);
7366
7367 size(3);
7368 ins_cost(300);
7369 format %{ "IMUL $dst,$src" %}
7370 opcode(0xAF, 0x0F);
7371 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7372 ins_pipe( ialu_reg_reg_alu0 );
7373 %}
7374
7375 // Multiply 32-bit Immediate
7376 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7377 match(Set dst (MulI src imm));
7378 effect(KILL cr);
7379
7380 ins_cost(300);
7381 format %{ "IMUL $dst,$src,$imm" %}
7382 opcode(0x69); /* 69 /r id */
7383 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7384 ins_pipe( ialu_reg_reg_alu0 );
7385 %}
7386
7387 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7388 match(Set dst src);
7389 effect(KILL cr);
7390
7391 // Note that this is artificially increased to make it more expensive than loadConL
7392 ins_cost(250);
7393 format %{ "MOV EAX,$src\t// low word only" %}
7394 opcode(0xB8);
7395 ins_encode( LdImmL_Lo(dst, src) );
7396 ins_pipe( ialu_reg_fat );
7397 %}
7398
7399 // Multiply by 32-bit Immediate, taking the shifted high order results
7400 // (special case for shift by 32)
7401 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7402 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7403 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7404 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7405 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7406 effect(USE src1, KILL cr);
7407
7408 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7409 ins_cost(0*100 + 1*400 - 150);
7410 format %{ "IMUL EDX:EAX,$src1" %}
7411 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7412 ins_pipe( pipe_slow );
7413 %}
7414
7415 // Multiply by 32-bit Immediate, taking the shifted high order results
7416 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7417 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7418 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7419 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7420 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7421 effect(USE src1, KILL cr);
7422
7423 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7424 ins_cost(1*100 + 1*400 - 150);
7425 format %{ "IMUL EDX:EAX,$src1\n\t"
7426 "SAR EDX,$cnt-32" %}
7427 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7428 ins_pipe( pipe_slow );
7429 %}
7430
7431 // Multiply Memory 32-bit Immediate
7432 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7433 match(Set dst (MulI (LoadI src) imm));
7434 effect(KILL cr);
7435
7436 ins_cost(300);
7437 format %{ "IMUL $dst,$src,$imm" %}
7438 opcode(0x69); /* 69 /r id */
7439 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7440 ins_pipe( ialu_reg_mem_alu0 );
7441 %}
7442
7443 // Multiply Memory
7444 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7445 match(Set dst (MulI dst (LoadI src)));
7446 effect(KILL cr);
7447
7448 ins_cost(350);
7449 format %{ "IMUL $dst,$src" %}
7450 opcode(0xAF, 0x0F);
7451 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7452 ins_pipe( ialu_reg_mem_alu0 );
7453 %}
7454
7455 // Multiply Register Int to Long
7456 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7457 // Basic Idea: long = (long)int * (long)int
7458 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7459 effect(DEF dst, USE src, USE src1, KILL flags);
7460
7461 ins_cost(300);
7462 format %{ "IMUL $dst,$src1" %}
7463
7464 ins_encode( long_int_multiply( dst, src1 ) );
7465 ins_pipe( ialu_reg_reg_alu0 );
7466 %}
7467
7468 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7469 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
7470 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7471 effect(KILL flags);
7472
7473 ins_cost(300);
7474 format %{ "MUL $dst,$src1" %}
7475
7476 ins_encode( long_uint_multiply(dst, src1) );
7477 ins_pipe( ialu_reg_reg_alu0 );
7478 %}
7479
7480 // Multiply Register Long
7481 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7482 match(Set dst (MulL dst src));
7483 effect(KILL cr, TEMP tmp);
7484 ins_cost(4*100+3*400);
7485 // Basic idea: lo(result) = lo(x_lo * y_lo)
7486 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
7487 format %{ "MOV $tmp,$src.lo\n\t"
7488 "IMUL $tmp,EDX\n\t"
7489 "MOV EDX,$src.hi\n\t"
7490 "IMUL EDX,EAX\n\t"
7491 "ADD $tmp,EDX\n\t"
7492 "MUL EDX:EAX,$src.lo\n\t"
7493 "ADD EDX,$tmp" %}
7494 ins_encode( long_multiply( dst, src, tmp ) );
7495 ins_pipe( pipe_slow );
7496 %}
7497
7498 // Multiply Register Long where the left operand's high 32 bits are zero
7499 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7500 predicate(is_operand_hi32_zero(n->in(1)));
7501 match(Set dst (MulL dst src));
7502 effect(KILL cr, TEMP tmp);
7503 ins_cost(2*100+2*400);
7504 // Basic idea: lo(result) = lo(x_lo * y_lo)
7505 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
7506 format %{ "MOV $tmp,$src.hi\n\t"
7507 "IMUL $tmp,EAX\n\t"
7508 "MUL EDX:EAX,$src.lo\n\t"
7509 "ADD EDX,$tmp" %}
7510 ins_encode %{
7511 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
7512 __ imull($tmp$$Register, rax);
7513 __ mull($src$$Register);
7514 __ addl(rdx, $tmp$$Register);
7515 %}
7516 ins_pipe( pipe_slow );
7517 %}
7518
7519 // Multiply Register Long where the right operand's high 32 bits are zero
7520 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7521 predicate(is_operand_hi32_zero(n->in(2)));
7522 match(Set dst (MulL dst src));
7523 effect(KILL cr, TEMP tmp);
7524 ins_cost(2*100+2*400);
7525 // Basic idea: lo(result) = lo(x_lo * y_lo)
7526 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
7527 format %{ "MOV $tmp,$src.lo\n\t"
7528 "IMUL $tmp,EDX\n\t"
7529 "MUL EDX:EAX,$src.lo\n\t"
7530 "ADD EDX,$tmp" %}
7531 ins_encode %{
7532 __ movl($tmp$$Register, $src$$Register);
7533 __ imull($tmp$$Register, rdx);
7534 __ mull($src$$Register);
7535 __ addl(rdx, $tmp$$Register);
7536 %}
7537 ins_pipe( pipe_slow );
7538 %}
7539
7540 // Multiply Register Long where the left and the right operands' high 32 bits are zero
7541 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
7542 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
7543 match(Set dst (MulL dst src));
7544 effect(KILL cr);
7545 ins_cost(1*400);
7546 // Basic idea: lo(result) = lo(x_lo * y_lo)
7547 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
7548 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
7549 ins_encode %{
7550 __ mull($src$$Register);
7551 %}
7552 ins_pipe( pipe_slow );
7553 %}
7554
7555 // Multiply Register Long by small constant
7556 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
7557 match(Set dst (MulL dst src));
7558 effect(KILL cr, TEMP tmp);
7559 ins_cost(2*100+2*400);
7560 size(12);
7561 // Basic idea: lo(result) = lo(src * EAX)
7562 // hi(result) = hi(src * EAX) + lo(src * EDX)
7563 format %{ "IMUL $tmp,EDX,$src\n\t"
7564 "MOV EDX,$src\n\t"
7565 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
7566 "ADD EDX,$tmp" %}
7567 ins_encode( long_multiply_con( dst, src, tmp ) );
7568 ins_pipe( pipe_slow );
7569 %}
7570
7571 // Integer DIV with Register
7572 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7573 match(Set rax (DivI rax div));
7574 effect(KILL rdx, KILL cr);
7575 size(26);
7576 ins_cost(30*100+10*100);
7577 format %{ "CMP EAX,0x80000000\n\t"
7578 "JNE,s normal\n\t"
7579 "XOR EDX,EDX\n\t"
7580 "CMP ECX,-1\n\t"
7581 "JE,s done\n"
7582 "normal: CDQ\n\t"
7583 "IDIV $div\n\t"
7584 "done:" %}
7585 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7586 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7587 ins_pipe( ialu_reg_reg_alu0 );
7588 %}
7589
7590 // Divide Register Long
7591 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7592 match(Set dst (DivL src1 src2));
7593 effect( KILL cr, KILL cx, KILL bx );
7594 ins_cost(10000);
7595 format %{ "PUSH $src1.hi\n\t"
7596 "PUSH $src1.lo\n\t"
7597 "PUSH $src2.hi\n\t"
7598 "PUSH $src2.lo\n\t"
7599 "CALL SharedRuntime::ldiv\n\t"
7600 "ADD ESP,16" %}
7601 ins_encode( long_div(src1,src2) );
7602 ins_pipe( pipe_slow );
7603 %}
7604
7605 // Integer DIVMOD with Register, both quotient and mod results
7606 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7607 match(DivModI rax div);
7608 effect(KILL cr);
7609 size(26);
7610 ins_cost(30*100+10*100);
7611 format %{ "CMP EAX,0x80000000\n\t"
7612 "JNE,s normal\n\t"
7613 "XOR EDX,EDX\n\t"
7614 "CMP ECX,-1\n\t"
7615 "JE,s done\n"
7616 "normal: CDQ\n\t"
7617 "IDIV $div\n\t"
7618 "done:" %}
7619 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7620 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7621 ins_pipe( pipe_slow );
7622 %}
7623
7624 // Integer MOD with Register
7625 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
7626 match(Set rdx (ModI rax div));
7627 effect(KILL rax, KILL cr);
7628
7629 size(26);
7630 ins_cost(300);
7631 format %{ "CDQ\n\t"
7632 "IDIV $div" %}
7633 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7634 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7635 ins_pipe( ialu_reg_reg_alu0 );
7636 %}
7637
7638 // Remainder Register Long
7639 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7640 match(Set dst (ModL src1 src2));
7641 effect( KILL cr, KILL cx, KILL bx );
7642 ins_cost(10000);
7643 format %{ "PUSH $src1.hi\n\t"
7644 "PUSH $src1.lo\n\t"
7645 "PUSH $src2.hi\n\t"
7646 "PUSH $src2.lo\n\t"
7647 "CALL SharedRuntime::lrem\n\t"
7648 "ADD ESP,16" %}
7649 ins_encode( long_mod(src1,src2) );
7650 ins_pipe( pipe_slow );
7651 %}
7652
7653 // Divide Register Long (no special case since divisor != -1)
7654 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7655 match(Set dst (DivL dst imm));
7656 effect( TEMP tmp, TEMP tmp2, KILL cr );
7657 ins_cost(1000);
7658 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
7659 "XOR $tmp2,$tmp2\n\t"
7660 "CMP $tmp,EDX\n\t"
7661 "JA,s fast\n\t"
7662 "MOV $tmp2,EAX\n\t"
7663 "MOV EAX,EDX\n\t"
7664 "MOV EDX,0\n\t"
7665 "JLE,s pos\n\t"
7666 "LNEG EAX : $tmp2\n\t"
7667 "DIV $tmp # unsigned division\n\t"
7668 "XCHG EAX,$tmp2\n\t"
7669 "DIV $tmp\n\t"
7670 "LNEG $tmp2 : EAX\n\t"
7671 "JMP,s done\n"
7672 "pos:\n\t"
7673 "DIV $tmp\n\t"
7674 "XCHG EAX,$tmp2\n"
7675 "fast:\n\t"
7676 "DIV $tmp\n"
7677 "done:\n\t"
7678 "MOV EDX,$tmp2\n\t"
7679 "NEG EDX:EAX # if $imm < 0" %}
7680 ins_encode %{
7681 int con = (int)$imm$$constant;
7682 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7683 int pcon = (con > 0) ? con : -con;
7684 Label Lfast, Lpos, Ldone;
7685
7686 __ movl($tmp$$Register, pcon);
7687 __ xorl($tmp2$$Register,$tmp2$$Register);
7688 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7689 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
7690
7691 __ movl($tmp2$$Register, $dst$$Register); // save
7692 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7693 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7694 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7695
7696 // Negative dividend.
7697 // convert value to positive to use unsigned division
7698 __ lneg($dst$$Register, $tmp2$$Register);
7699 __ divl($tmp$$Register);
7700 __ xchgl($dst$$Register, $tmp2$$Register);
7701 __ divl($tmp$$Register);
7702 // revert result back to negative
7703 __ lneg($tmp2$$Register, $dst$$Register);
7704 __ jmpb(Ldone);
7705
7706 __ bind(Lpos);
7707 __ divl($tmp$$Register); // Use unsigned division
7708 __ xchgl($dst$$Register, $tmp2$$Register);
7709 // Fallthrow for final divide, tmp2 has 32 bit hi result
7710
7711 __ bind(Lfast);
7712 // fast path: src is positive
7713 __ divl($tmp$$Register); // Use unsigned division
7714
7715 __ bind(Ldone);
7716 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
7717 if (con < 0) {
7718 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
7719 }
7720 %}
7721 ins_pipe( pipe_slow );
7722 %}
7723
7724 // Remainder Register Long (remainder fit into 32 bits)
7725 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7726 match(Set dst (ModL dst imm));
7727 effect( TEMP tmp, TEMP tmp2, KILL cr );
7728 ins_cost(1000);
7729 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
7730 "CMP $tmp,EDX\n\t"
7731 "JA,s fast\n\t"
7732 "MOV $tmp2,EAX\n\t"
7733 "MOV EAX,EDX\n\t"
7734 "MOV EDX,0\n\t"
7735 "JLE,s pos\n\t"
7736 "LNEG EAX : $tmp2\n\t"
7737 "DIV $tmp # unsigned division\n\t"
7738 "MOV EAX,$tmp2\n\t"
7739 "DIV $tmp\n\t"
7740 "NEG EDX\n\t"
7741 "JMP,s done\n"
7742 "pos:\n\t"
7743 "DIV $tmp\n\t"
7744 "MOV EAX,$tmp2\n"
7745 "fast:\n\t"
7746 "DIV $tmp\n"
7747 "done:\n\t"
7748 "MOV EAX,EDX\n\t"
7749 "SAR EDX,31\n\t" %}
7750 ins_encode %{
7751 int con = (int)$imm$$constant;
7752 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7753 int pcon = (con > 0) ? con : -con;
7754 Label Lfast, Lpos, Ldone;
7755
7756 __ movl($tmp$$Register, pcon);
7757 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7758 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
7759
7760 __ movl($tmp2$$Register, $dst$$Register); // save
7761 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7762 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7763 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7764
7765 // Negative dividend.
7766 // convert value to positive to use unsigned division
7767 __ lneg($dst$$Register, $tmp2$$Register);
7768 __ divl($tmp$$Register);
7769 __ movl($dst$$Register, $tmp2$$Register);
7770 __ divl($tmp$$Register);
7771 // revert remainder back to negative
7772 __ negl(HIGH_FROM_LOW($dst$$Register));
7773 __ jmpb(Ldone);
7774
7775 __ bind(Lpos);
7776 __ divl($tmp$$Register);
7777 __ movl($dst$$Register, $tmp2$$Register);
7778
7779 __ bind(Lfast);
7780 // fast path: src is positive
7781 __ divl($tmp$$Register);
7782
7783 __ bind(Ldone);
7784 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7785 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
7786
7787 %}
7788 ins_pipe( pipe_slow );
7789 %}
7790
7791 // Integer Shift Instructions
7792 // Shift Left by one
7793 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7794 match(Set dst (LShiftI dst shift));
7795 effect(KILL cr);
7796
7797 size(2);
7798 format %{ "SHL $dst,$shift" %}
7799 opcode(0xD1, 0x4); /* D1 /4 */
7800 ins_encode( OpcP, RegOpc( dst ) );
7801 ins_pipe( ialu_reg );
7802 %}
7803
7804 // Shift Left by 8-bit immediate
7805 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7806 match(Set dst (LShiftI dst shift));
7807 effect(KILL cr);
7808
7809 size(3);
7810 format %{ "SHL $dst,$shift" %}
7811 opcode(0xC1, 0x4); /* C1 /4 ib */
7812 ins_encode( RegOpcImm( dst, shift) );
7813 ins_pipe( ialu_reg );
7814 %}
7815
7816 // Shift Left by variable
7817 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7818 match(Set dst (LShiftI dst shift));
7819 effect(KILL cr);
7820
7821 size(2);
7822 format %{ "SHL $dst,$shift" %}
7823 opcode(0xD3, 0x4); /* D3 /4 */
7824 ins_encode( OpcP, RegOpc( dst ) );
7825 ins_pipe( ialu_reg_reg );
7826 %}
7827
7828 // Arithmetic shift right by one
7829 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7830 match(Set dst (RShiftI dst shift));
7831 effect(KILL cr);
7832
7833 size(2);
7834 format %{ "SAR $dst,$shift" %}
7835 opcode(0xD1, 0x7); /* D1 /7 */
7836 ins_encode( OpcP, RegOpc( dst ) );
7837 ins_pipe( ialu_reg );
7838 %}
7839
7840 // Arithmetic shift right by one
7841 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
7842 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7843 effect(KILL cr);
7844 format %{ "SAR $dst,$shift" %}
7845 opcode(0xD1, 0x7); /* D1 /7 */
7846 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
7847 ins_pipe( ialu_mem_imm );
7848 %}
7849
7850 // Arithmetic Shift Right by 8-bit immediate
7851 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7852 match(Set dst (RShiftI dst shift));
7853 effect(KILL cr);
7854
7855 size(3);
7856 format %{ "SAR $dst,$shift" %}
7857 opcode(0xC1, 0x7); /* C1 /7 ib */
7858 ins_encode( RegOpcImm( dst, shift ) );
7859 ins_pipe( ialu_mem_imm );
7860 %}
7861
7862 // Arithmetic Shift Right by 8-bit immediate
7863 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
7864 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7865 effect(KILL cr);
7866
7867 format %{ "SAR $dst,$shift" %}
7868 opcode(0xC1, 0x7); /* C1 /7 ib */
7869 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
7870 ins_pipe( ialu_mem_imm );
7871 %}
7872
7873 // Arithmetic Shift Right by variable
7874 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7875 match(Set dst (RShiftI dst shift));
7876 effect(KILL cr);
7877
7878 size(2);
7879 format %{ "SAR $dst,$shift" %}
7880 opcode(0xD3, 0x7); /* D3 /7 */
7881 ins_encode( OpcP, RegOpc( dst ) );
7882 ins_pipe( ialu_reg_reg );
7883 %}
7884
7885 // Logical shift right by one
7886 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7887 match(Set dst (URShiftI dst shift));
7888 effect(KILL cr);
7889
7890 size(2);
7891 format %{ "SHR $dst,$shift" %}
7892 opcode(0xD1, 0x5); /* D1 /5 */
7893 ins_encode( OpcP, RegOpc( dst ) );
7894 ins_pipe( ialu_reg );
7895 %}
7896
7897 // Logical Shift Right by 8-bit immediate
7898 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7899 match(Set dst (URShiftI dst shift));
7900 effect(KILL cr);
7901
7902 size(3);
7903 format %{ "SHR $dst,$shift" %}
7904 opcode(0xC1, 0x5); /* C1 /5 ib */
7905 ins_encode( RegOpcImm( dst, shift) );
7906 ins_pipe( ialu_reg );
7907 %}
7908
7909
7910 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
7911 // This idiom is used by the compiler for the i2b bytecode.
7912 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
7913 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
7914
7915 size(3);
7916 format %{ "MOVSX $dst,$src :8" %}
7917 ins_encode %{
7918 __ movsbl($dst$$Register, $src$$Register);
7919 %}
7920 ins_pipe(ialu_reg_reg);
7921 %}
7922
7923 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
7924 // This idiom is used by the compiler the i2s bytecode.
7925 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
7926 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
7927
7928 size(3);
7929 format %{ "MOVSX $dst,$src :16" %}
7930 ins_encode %{
7931 __ movswl($dst$$Register, $src$$Register);
7932 %}
7933 ins_pipe(ialu_reg_reg);
7934 %}
7935
7936
7937 // Logical Shift Right by variable
7938 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7939 match(Set dst (URShiftI dst shift));
7940 effect(KILL cr);
7941
7942 size(2);
7943 format %{ "SHR $dst,$shift" %}
7944 opcode(0xD3, 0x5); /* D3 /5 */
7945 ins_encode( OpcP, RegOpc( dst ) );
7946 ins_pipe( ialu_reg_reg );
7947 %}
7948
7949
7950 //----------Logical Instructions-----------------------------------------------
7951 //----------Integer Logical Instructions---------------------------------------
7952 // And Instructions
7953 // And Register with Register
7954 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7955 match(Set dst (AndI dst src));
7956 effect(KILL cr);
7957
7958 size(2);
7959 format %{ "AND $dst,$src" %}
7960 opcode(0x23);
7961 ins_encode( OpcP, RegReg( dst, src) );
7962 ins_pipe( ialu_reg_reg );
7963 %}
7964
7965 // And Register with Immediate
7966 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7967 match(Set dst (AndI dst src));
7968 effect(KILL cr);
7969
7970 format %{ "AND $dst,$src" %}
7971 opcode(0x81,0x04); /* Opcode 81 /4 */
7972 // ins_encode( RegImm( dst, src) );
7973 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7974 ins_pipe( ialu_reg );
7975 %}
7976
7977 // And Register with Memory
7978 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7979 match(Set dst (AndI dst (LoadI src)));
7980 effect(KILL cr);
7981
7982 ins_cost(125);
7983 format %{ "AND $dst,$src" %}
7984 opcode(0x23);
7985 ins_encode( OpcP, RegMem( dst, src) );
7986 ins_pipe( ialu_reg_mem );
7987 %}
7988
7989 // And Memory with Register
7990 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7991 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
7992 effect(KILL cr);
7993
7994 ins_cost(150);
7995 format %{ "AND $dst,$src" %}
7996 opcode(0x21); /* Opcode 21 /r */
7997 ins_encode( OpcP, RegMem( src, dst ) );
7998 ins_pipe( ialu_mem_reg );
7999 %}
8000
8001 // And Memory with Immediate
8002 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8003 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8004 effect(KILL cr);
8005
8006 ins_cost(125);
8007 format %{ "AND $dst,$src" %}
8008 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8009 // ins_encode( MemImm( dst, src) );
8010 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8011 ins_pipe( ialu_mem_imm );
8012 %}
8013
8014 // BMI1 instructions
8015 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
8016 match(Set dst (AndI (XorI src1 minus_1) src2));
8017 predicate(UseBMI1Instructions);
8018 effect(KILL cr);
8019
8020 format %{ "ANDNL $dst, $src1, $src2" %}
8021
8022 ins_encode %{
8023 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8024 %}
8025 ins_pipe(ialu_reg);
8026 %}
8027
8028 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8029 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8030 predicate(UseBMI1Instructions);
8031 effect(KILL cr);
8032
8033 ins_cost(125);
8034 format %{ "ANDNL $dst, $src1, $src2" %}
8035
8036 ins_encode %{
8037 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8038 %}
8039 ins_pipe(ialu_reg_mem);
8040 %}
8041
8042 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
8043 match(Set dst (AndI (SubI imm_zero src) src));
8044 predicate(UseBMI1Instructions);
8045 effect(KILL cr);
8046
8047 format %{ "BLSIL $dst, $src" %}
8048
8049 ins_encode %{
8050 __ blsil($dst$$Register, $src$$Register);
8051 %}
8052 ins_pipe(ialu_reg);
8053 %}
8054
8055 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
8056 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8057 predicate(UseBMI1Instructions);
8058 effect(KILL cr);
8059
8060 ins_cost(125);
8061 format %{ "BLSIL $dst, $src" %}
8062
8063 ins_encode %{
8064 __ blsil($dst$$Register, $src$$Address);
8065 %}
8066 ins_pipe(ialu_reg_mem);
8067 %}
8068
8069 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8070 %{
8071 match(Set dst (XorI (AddI src minus_1) src));
8072 predicate(UseBMI1Instructions);
8073 effect(KILL cr);
8074
8075 format %{ "BLSMSKL $dst, $src" %}
8076
8077 ins_encode %{
8078 __ blsmskl($dst$$Register, $src$$Register);
8079 %}
8080
8081 ins_pipe(ialu_reg);
8082 %}
8083
8084 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8085 %{
8086 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
8087 predicate(UseBMI1Instructions);
8088 effect(KILL cr);
8089
8090 ins_cost(125);
8091 format %{ "BLSMSKL $dst, $src" %}
8092
8093 ins_encode %{
8094 __ blsmskl($dst$$Register, $src$$Address);
8095 %}
8096
8097 ins_pipe(ialu_reg_mem);
8098 %}
8099
8100 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8101 %{
8102 match(Set dst (AndI (AddI src minus_1) src) );
8103 predicate(UseBMI1Instructions);
8104 effect(KILL cr);
8105
8106 format %{ "BLSRL $dst, $src" %}
8107
8108 ins_encode %{
8109 __ blsrl($dst$$Register, $src$$Register);
8110 %}
8111
8112 ins_pipe(ialu_reg);
8113 %}
8114
8115 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8116 %{
8117 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8118 predicate(UseBMI1Instructions);
8119 effect(KILL cr);
8120
8121 ins_cost(125);
8122 format %{ "BLSRL $dst, $src" %}
8123
8124 ins_encode %{
8125 __ blsrl($dst$$Register, $src$$Address);
8126 %}
8127
8128 ins_pipe(ialu_reg_mem);
8129 %}
8130
8131 // Or Instructions
8132 // Or Register with Register
8133 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8134 match(Set dst (OrI dst src));
8135 effect(KILL cr);
8136
8137 size(2);
8138 format %{ "OR $dst,$src" %}
8139 opcode(0x0B);
8140 ins_encode( OpcP, RegReg( dst, src) );
8141 ins_pipe( ialu_reg_reg );
8142 %}
8143
8144 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8145 match(Set dst (OrI dst (CastP2X src)));
8146 effect(KILL cr);
8147
8148 size(2);
8149 format %{ "OR $dst,$src" %}
8150 opcode(0x0B);
8151 ins_encode( OpcP, RegReg( dst, src) );
8152 ins_pipe( ialu_reg_reg );
8153 %}
8154
8155
8156 // Or Register with Immediate
8157 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8158 match(Set dst (OrI dst src));
8159 effect(KILL cr);
8160
8161 format %{ "OR $dst,$src" %}
8162 opcode(0x81,0x01); /* Opcode 81 /1 id */
8163 // ins_encode( RegImm( dst, src) );
8164 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8165 ins_pipe( ialu_reg );
8166 %}
8167
8168 // Or Register with Memory
8169 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8170 match(Set dst (OrI dst (LoadI src)));
8171 effect(KILL cr);
8172
8173 ins_cost(125);
8174 format %{ "OR $dst,$src" %}
8175 opcode(0x0B);
8176 ins_encode( OpcP, RegMem( dst, src) );
8177 ins_pipe( ialu_reg_mem );
8178 %}
8179
8180 // Or Memory with Register
8181 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8182 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8183 effect(KILL cr);
8184
8185 ins_cost(150);
8186 format %{ "OR $dst,$src" %}
8187 opcode(0x09); /* Opcode 09 /r */
8188 ins_encode( OpcP, RegMem( src, dst ) );
8189 ins_pipe( ialu_mem_reg );
8190 %}
8191
8192 // Or Memory with Immediate
8193 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8194 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8195 effect(KILL cr);
8196
8197 ins_cost(125);
8198 format %{ "OR $dst,$src" %}
8199 opcode(0x81,0x1); /* Opcode 81 /1 id */
8200 // ins_encode( MemImm( dst, src) );
8201 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8202 ins_pipe( ialu_mem_imm );
8203 %}
8204
8205 // ROL/ROR
8206 // ROL expand
8207 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8208 effect(USE_DEF dst, USE shift, KILL cr);
8209
8210 format %{ "ROL $dst, $shift" %}
8211 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8212 ins_encode( OpcP, RegOpc( dst ));
8213 ins_pipe( ialu_reg );
8214 %}
8215
8216 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8217 effect(USE_DEF dst, USE shift, KILL cr);
8218
8219 format %{ "ROL $dst, $shift" %}
8220 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8221 ins_encode( RegOpcImm(dst, shift) );
8222 ins_pipe(ialu_reg);
8223 %}
8224
8225 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8226 effect(USE_DEF dst, USE shift, KILL cr);
8227
8228 format %{ "ROL $dst, $shift" %}
8229 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8230 ins_encode(OpcP, RegOpc(dst));
8231 ins_pipe( ialu_reg_reg );
8232 %}
8233 // end of ROL expand
8234
8235 // ROL 32bit by one once
8236 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8237 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8238
8239 expand %{
8240 rolI_eReg_imm1(dst, lshift, cr);
8241 %}
8242 %}
8243
8244 // ROL 32bit var by imm8 once
8245 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8246 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8247 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8248
8249 expand %{
8250 rolI_eReg_imm8(dst, lshift, cr);
8251 %}
8252 %}
8253
8254 // ROL 32bit var by var once
8255 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8256 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8257
8258 expand %{
8259 rolI_eReg_CL(dst, shift, cr);
8260 %}
8261 %}
8262
8263 // ROL 32bit var by var once
8264 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8265 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8266
8267 expand %{
8268 rolI_eReg_CL(dst, shift, cr);
8269 %}
8270 %}
8271
8272 // ROR expand
8273 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8274 effect(USE_DEF dst, USE shift, KILL cr);
8275
8276 format %{ "ROR $dst, $shift" %}
8277 opcode(0xD1,0x1); /* Opcode D1 /1 */
8278 ins_encode( OpcP, RegOpc( dst ) );
8279 ins_pipe( ialu_reg );
8280 %}
8281
8282 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8283 effect (USE_DEF dst, USE shift, KILL cr);
8284
8285 format %{ "ROR $dst, $shift" %}
8286 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8287 ins_encode( RegOpcImm(dst, shift) );
8288 ins_pipe( ialu_reg );
8289 %}
8290
8291 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8292 effect(USE_DEF dst, USE shift, KILL cr);
8293
8294 format %{ "ROR $dst, $shift" %}
8295 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8296 ins_encode(OpcP, RegOpc(dst));
8297 ins_pipe( ialu_reg_reg );
8298 %}
8299 // end of ROR expand
8300
8301 // ROR right once
8302 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8303 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8304
8305 expand %{
8306 rorI_eReg_imm1(dst, rshift, cr);
8307 %}
8308 %}
8309
8310 // ROR 32bit by immI8 once
8311 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8312 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8313 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8314
8315 expand %{
8316 rorI_eReg_imm8(dst, rshift, cr);
8317 %}
8318 %}
8319
8320 // ROR 32bit var by var once
8321 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8322 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8323
8324 expand %{
8325 rorI_eReg_CL(dst, shift, cr);
8326 %}
8327 %}
8328
8329 // ROR 32bit var by var once
8330 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8331 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8332
8333 expand %{
8334 rorI_eReg_CL(dst, shift, cr);
8335 %}
8336 %}
8337
8338 // Xor Instructions
8339 // Xor Register with Register
8340 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8341 match(Set dst (XorI dst src));
8342 effect(KILL cr);
8343
8344 size(2);
8345 format %{ "XOR $dst,$src" %}
8346 opcode(0x33);
8347 ins_encode( OpcP, RegReg( dst, src) );
8348 ins_pipe( ialu_reg_reg );
8349 %}
8350
8351 // Xor Register with Immediate -1
8352 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8353 match(Set dst (XorI dst imm));
8354
8355 size(2);
8356 format %{ "NOT $dst" %}
8357 ins_encode %{
8358 __ notl($dst$$Register);
8359 %}
8360 ins_pipe( ialu_reg );
8361 %}
8362
8363 // Xor Register with Immediate
8364 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8365 match(Set dst (XorI dst src));
8366 effect(KILL cr);
8367
8368 format %{ "XOR $dst,$src" %}
8369 opcode(0x81,0x06); /* Opcode 81 /6 id */
8370 // ins_encode( RegImm( dst, src) );
8371 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8372 ins_pipe( ialu_reg );
8373 %}
8374
8375 // Xor Register with Memory
8376 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8377 match(Set dst (XorI dst (LoadI src)));
8378 effect(KILL cr);
8379
8380 ins_cost(125);
8381 format %{ "XOR $dst,$src" %}
8382 opcode(0x33);
8383 ins_encode( OpcP, RegMem(dst, src) );
8384 ins_pipe( ialu_reg_mem );
8385 %}
8386
8387 // Xor Memory with Register
8388 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8389 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8390 effect(KILL cr);
8391
8392 ins_cost(150);
8393 format %{ "XOR $dst,$src" %}
8394 opcode(0x31); /* Opcode 31 /r */
8395 ins_encode( OpcP, RegMem( src, dst ) );
8396 ins_pipe( ialu_mem_reg );
8397 %}
8398
8399 // Xor Memory with Immediate
8400 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8401 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8402 effect(KILL cr);
8403
8404 ins_cost(125);
8405 format %{ "XOR $dst,$src" %}
8406 opcode(0x81,0x6); /* Opcode 81 /6 id */
8407 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8408 ins_pipe( ialu_mem_imm );
8409 %}
8410
8411 //----------Convert Int to Boolean---------------------------------------------
8412
8413 instruct movI_nocopy(rRegI dst, rRegI src) %{
8414 effect( DEF dst, USE src );
8415 format %{ "MOV $dst,$src" %}
8416 ins_encode( enc_Copy( dst, src) );
8417 ins_pipe( ialu_reg_reg );
8418 %}
8419
8420 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8421 effect( USE_DEF dst, USE src, KILL cr );
8422
8423 size(4);
8424 format %{ "NEG $dst\n\t"
8425 "ADC $dst,$src" %}
8426 ins_encode( neg_reg(dst),
8427 OpcRegReg(0x13,dst,src) );
8428 ins_pipe( ialu_reg_reg_long );
8429 %}
8430
8431 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8432 match(Set dst (Conv2B src));
8433
8434 expand %{
8435 movI_nocopy(dst,src);
8436 ci2b(dst,src,cr);
8437 %}
8438 %}
8439
8440 instruct movP_nocopy(rRegI dst, eRegP src) %{
8441 effect( DEF dst, USE src );
8442 format %{ "MOV $dst,$src" %}
8443 ins_encode( enc_Copy( dst, src) );
8444 ins_pipe( ialu_reg_reg );
8445 %}
8446
8447 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8448 effect( USE_DEF dst, USE src, KILL cr );
8449 format %{ "NEG $dst\n\t"
8450 "ADC $dst,$src" %}
8451 ins_encode( neg_reg(dst),
8452 OpcRegReg(0x13,dst,src) );
8453 ins_pipe( ialu_reg_reg_long );
8454 %}
8455
8456 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8457 match(Set dst (Conv2B src));
8458
8459 expand %{
8460 movP_nocopy(dst,src);
8461 cp2b(dst,src,cr);
8462 %}
8463 %}
8464
8465 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8466 match(Set dst (CmpLTMask p q));
8467 effect(KILL cr);
8468 ins_cost(400);
8469
8470 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8471 format %{ "XOR $dst,$dst\n\t"
8472 "CMP $p,$q\n\t"
8473 "SETlt $dst\n\t"
8474 "NEG $dst" %}
8475 ins_encode %{
8476 Register Rp = $p$$Register;
8477 Register Rq = $q$$Register;
8478 Register Rd = $dst$$Register;
8479 Label done;
8480 __ xorl(Rd, Rd);
8481 __ cmpl(Rp, Rq);
8482 __ setb(Assembler::less, Rd);
8483 __ negl(Rd);
8484 %}
8485
8486 ins_pipe(pipe_slow);
8487 %}
8488
8489 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8490 match(Set dst (CmpLTMask dst zero));
8491 effect(DEF dst, KILL cr);
8492 ins_cost(100);
8493
8494 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8495 ins_encode %{
8496 __ sarl($dst$$Register, 31);
8497 %}
8498 ins_pipe(ialu_reg);
8499 %}
8500
8501 /* better to save a register than avoid a branch */
8502 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8503 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8504 effect(KILL cr);
8505 ins_cost(400);
8506 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8507 "JGE done\n\t"
8508 "ADD $p,$y\n"
8509 "done: " %}
8510 ins_encode %{
8511 Register Rp = $p$$Register;
8512 Register Rq = $q$$Register;
8513 Register Ry = $y$$Register;
8514 Label done;
8515 __ subl(Rp, Rq);
8516 __ jccb(Assembler::greaterEqual, done);
8517 __ addl(Rp, Ry);
8518 __ bind(done);
8519 %}
8520
8521 ins_pipe(pipe_cmplt);
8522 %}
8523
8524 /* better to save a register than avoid a branch */
8525 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8526 match(Set y (AndI (CmpLTMask p q) y));
8527 effect(KILL cr);
8528
8529 ins_cost(300);
8530
8531 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8532 "JLT done\n\t"
8533 "XORL $y, $y\n"
8534 "done: " %}
8535 ins_encode %{
8536 Register Rp = $p$$Register;
8537 Register Rq = $q$$Register;
8538 Register Ry = $y$$Register;
8539 Label done;
8540 __ cmpl(Rp, Rq);
8541 __ jccb(Assembler::less, done);
8542 __ xorl(Ry, Ry);
8543 __ bind(done);
8544 %}
8545
8546 ins_pipe(pipe_cmplt);
8547 %}
8548
8549 /* If I enable this, I encourage spilling in the inner loop of compress.
8550 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8551 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8552 */
8553 //----------Overflow Math Instructions-----------------------------------------
8554
8555 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8556 %{
8557 match(Set cr (OverflowAddI op1 op2));
8558 effect(DEF cr, USE_KILL op1, USE op2);
8559
8560 format %{ "ADD $op1, $op2\t# overflow check int" %}
8561
8562 ins_encode %{
8563 __ addl($op1$$Register, $op2$$Register);
8564 %}
8565 ins_pipe(ialu_reg_reg);
8566 %}
8567
8568 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
8569 %{
8570 match(Set cr (OverflowAddI op1 op2));
8571 effect(DEF cr, USE_KILL op1, USE op2);
8572
8573 format %{ "ADD $op1, $op2\t# overflow check int" %}
8574
8575 ins_encode %{
8576 __ addl($op1$$Register, $op2$$constant);
8577 %}
8578 ins_pipe(ialu_reg_reg);
8579 %}
8580
8581 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2)
8582 %{
8583 match(Set cr (OverflowSubI op1 op2));
8584
8585 format %{ "CMP $op1, $op2\t# overflow check int" %}
8586 ins_encode %{
8587 __ cmpl($op1$$Register, $op2$$Register);
8588 %}
8589 ins_pipe(ialu_reg_reg);
8590 %}
8591
8592 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8593 %{
8594 match(Set cr (OverflowSubI op1 op2));
8595
8596 format %{ "CMP $op1, $op2\t# overflow check int" %}
8597 ins_encode %{
8598 __ cmpl($op1$$Register, $op2$$constant);
8599 %}
8600 ins_pipe(ialu_reg_reg);
8601 %}
8602
8603 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
8604 %{
8605 match(Set cr (OverflowSubI zero op2));
8606 effect(DEF cr, USE_KILL op2);
8607
8608 format %{ "NEG $op2\t# overflow check int" %}
8609 ins_encode %{
8610 __ negl($op2$$Register);
8611 %}
8612 ins_pipe(ialu_reg_reg);
8613 %}
8614
8615 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8616 %{
8617 match(Set cr (OverflowMulI op1 op2));
8618 effect(DEF cr, USE_KILL op1, USE op2);
8619
8620 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8621 ins_encode %{
8622 __ imull($op1$$Register, $op2$$Register);
8623 %}
8624 ins_pipe(ialu_reg_reg_alu0);
8625 %}
8626
8627 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8628 %{
8629 match(Set cr (OverflowMulI op1 op2));
8630 effect(DEF cr, TEMP tmp, USE op1, USE op2);
8631
8632 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %}
8633 ins_encode %{
8634 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8635 %}
8636 ins_pipe(ialu_reg_reg_alu0);
8637 %}
8638
8639 //----------Long Instructions------------------------------------------------
8640 // Add Long Register with Register
8641 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8642 match(Set dst (AddL dst src));
8643 effect(KILL cr);
8644 ins_cost(200);
8645 format %{ "ADD $dst.lo,$src.lo\n\t"
8646 "ADC $dst.hi,$src.hi" %}
8647 opcode(0x03, 0x13);
8648 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8649 ins_pipe( ialu_reg_reg_long );
8650 %}
8651
8652 // Add Long Register with Immediate
8653 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8654 match(Set dst (AddL dst src));
8655 effect(KILL cr);
8656 format %{ "ADD $dst.lo,$src.lo\n\t"
8657 "ADC $dst.hi,$src.hi" %}
8658 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8659 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8660 ins_pipe( ialu_reg_long );
8661 %}
8662
8663 // Add Long Register with Memory
8664 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8665 match(Set dst (AddL dst (LoadL mem)));
8666 effect(KILL cr);
8667 ins_cost(125);
8668 format %{ "ADD $dst.lo,$mem\n\t"
8669 "ADC $dst.hi,$mem+4" %}
8670 opcode(0x03, 0x13);
8671 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8672 ins_pipe( ialu_reg_long_mem );
8673 %}
8674
8675 // Subtract Long Register with Register.
8676 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8677 match(Set dst (SubL dst src));
8678 effect(KILL cr);
8679 ins_cost(200);
8680 format %{ "SUB $dst.lo,$src.lo\n\t"
8681 "SBB $dst.hi,$src.hi" %}
8682 opcode(0x2B, 0x1B);
8683 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8684 ins_pipe( ialu_reg_reg_long );
8685 %}
8686
8687 // Subtract Long Register with Immediate
8688 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8689 match(Set dst (SubL dst src));
8690 effect(KILL cr);
8691 format %{ "SUB $dst.lo,$src.lo\n\t"
8692 "SBB $dst.hi,$src.hi" %}
8693 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8694 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8695 ins_pipe( ialu_reg_long );
8696 %}
8697
8698 // Subtract Long Register with Memory
8699 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8700 match(Set dst (SubL dst (LoadL mem)));
8701 effect(KILL cr);
8702 ins_cost(125);
8703 format %{ "SUB $dst.lo,$mem\n\t"
8704 "SBB $dst.hi,$mem+4" %}
8705 opcode(0x2B, 0x1B);
8706 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8707 ins_pipe( ialu_reg_long_mem );
8708 %}
8709
8710 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8711 match(Set dst (SubL zero dst));
8712 effect(KILL cr);
8713 ins_cost(300);
8714 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8715 ins_encode( neg_long(dst) );
8716 ins_pipe( ialu_reg_reg_long );
8717 %}
8718
8719 // And Long Register with Register
8720 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8721 match(Set dst (AndL dst src));
8722 effect(KILL cr);
8723 format %{ "AND $dst.lo,$src.lo\n\t"
8724 "AND $dst.hi,$src.hi" %}
8725 opcode(0x23,0x23);
8726 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8727 ins_pipe( ialu_reg_reg_long );
8728 %}
8729
8730 // And Long Register with Immediate
8731 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8732 match(Set dst (AndL dst src));
8733 effect(KILL cr);
8734 format %{ "AND $dst.lo,$src.lo\n\t"
8735 "AND $dst.hi,$src.hi" %}
8736 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8737 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8738 ins_pipe( ialu_reg_long );
8739 %}
8740
8741 // And Long Register with Memory
8742 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8743 match(Set dst (AndL dst (LoadL mem)));
8744 effect(KILL cr);
8745 ins_cost(125);
8746 format %{ "AND $dst.lo,$mem\n\t"
8747 "AND $dst.hi,$mem+4" %}
8748 opcode(0x23, 0x23);
8749 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8750 ins_pipe( ialu_reg_long_mem );
8751 %}
8752
8753 // BMI1 instructions
8754 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
8755 match(Set dst (AndL (XorL src1 minus_1) src2));
8756 predicate(UseBMI1Instructions);
8757 effect(KILL cr, TEMP dst);
8758
8759 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t"
8760 "ANDNL $dst.hi, $src1.hi, $src2.hi"
8761 %}
8762
8763 ins_encode %{
8764 Register Rdst = $dst$$Register;
8765 Register Rsrc1 = $src1$$Register;
8766 Register Rsrc2 = $src2$$Register;
8767 __ andnl(Rdst, Rsrc1, Rsrc2);
8768 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
8769 %}
8770 ins_pipe(ialu_reg_reg_long);
8771 %}
8772
8773 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
8774 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
8775 predicate(UseBMI1Instructions);
8776 effect(KILL cr, TEMP dst);
8777
8778 ins_cost(125);
8779 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t"
8780 "ANDNL $dst.hi, $src1.hi, $src2+4"
8781 %}
8782
8783 ins_encode %{
8784 Register Rdst = $dst$$Register;
8785 Register Rsrc1 = $src1$$Register;
8786 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
8787
8788 __ andnl(Rdst, Rsrc1, $src2$$Address);
8789 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
8790 %}
8791 ins_pipe(ialu_reg_mem);
8792 %}
8793
8794 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
8795 match(Set dst (AndL (SubL imm_zero src) src));
8796 predicate(UseBMI1Instructions);
8797 effect(KILL cr, TEMP dst);
8798
8799 format %{ "MOVL $dst.hi, 0\n\t"
8800 "BLSIL $dst.lo, $src.lo\n\t"
8801 "JNZ done\n\t"
8802 "BLSIL $dst.hi, $src.hi\n"
8803 "done:"
8804 %}
8805
8806 ins_encode %{
8807 Label done;
8808 Register Rdst = $dst$$Register;
8809 Register Rsrc = $src$$Register;
8810 __ movl(HIGH_FROM_LOW(Rdst), 0);
8811 __ blsil(Rdst, Rsrc);
8812 __ jccb(Assembler::notZero, done);
8813 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8814 __ bind(done);
8815 %}
8816 ins_pipe(ialu_reg);
8817 %}
8818
8819 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
8820 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
8821 predicate(UseBMI1Instructions);
8822 effect(KILL cr, TEMP dst);
8823
8824 ins_cost(125);
8825 format %{ "MOVL $dst.hi, 0\n\t"
8826 "BLSIL $dst.lo, $src\n\t"
8827 "JNZ done\n\t"
8828 "BLSIL $dst.hi, $src+4\n"
8829 "done:"
8830 %}
8831
8832 ins_encode %{
8833 Label done;
8834 Register Rdst = $dst$$Register;
8835 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8836
8837 __ movl(HIGH_FROM_LOW(Rdst), 0);
8838 __ blsil(Rdst, $src$$Address);
8839 __ jccb(Assembler::notZero, done);
8840 __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
8841 __ bind(done);
8842 %}
8843 ins_pipe(ialu_reg_mem);
8844 %}
8845
8846 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8847 %{
8848 match(Set dst (XorL (AddL src minus_1) src));
8849 predicate(UseBMI1Instructions);
8850 effect(KILL cr, TEMP dst);
8851
8852 format %{ "MOVL $dst.hi, 0\n\t"
8853 "BLSMSKL $dst.lo, $src.lo\n\t"
8854 "JNC done\n\t"
8855 "BLSMSKL $dst.hi, $src.hi\n"
8856 "done:"
8857 %}
8858
8859 ins_encode %{
8860 Label done;
8861 Register Rdst = $dst$$Register;
8862 Register Rsrc = $src$$Register;
8863 __ movl(HIGH_FROM_LOW(Rdst), 0);
8864 __ blsmskl(Rdst, Rsrc);
8865 __ jccb(Assembler::carryClear, done);
8866 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8867 __ bind(done);
8868 %}
8869
8870 ins_pipe(ialu_reg);
8871 %}
8872
8873 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8874 %{
8875 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
8876 predicate(UseBMI1Instructions);
8877 effect(KILL cr, TEMP dst);
8878
8879 ins_cost(125);
8880 format %{ "MOVL $dst.hi, 0\n\t"
8881 "BLSMSKL $dst.lo, $src\n\t"
8882 "JNC done\n\t"
8883 "BLSMSKL $dst.hi, $src+4\n"
8884 "done:"
8885 %}
8886
8887 ins_encode %{
8888 Label done;
8889 Register Rdst = $dst$$Register;
8890 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8891
8892 __ movl(HIGH_FROM_LOW(Rdst), 0);
8893 __ blsmskl(Rdst, $src$$Address);
8894 __ jccb(Assembler::carryClear, done);
8895 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
8896 __ bind(done);
8897 %}
8898
8899 ins_pipe(ialu_reg_mem);
8900 %}
8901
8902 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8903 %{
8904 match(Set dst (AndL (AddL src minus_1) src) );
8905 predicate(UseBMI1Instructions);
8906 effect(KILL cr, TEMP dst);
8907
8908 format %{ "MOVL $dst.hi, $src.hi\n\t"
8909 "BLSRL $dst.lo, $src.lo\n\t"
8910 "JNC done\n\t"
8911 "BLSRL $dst.hi, $src.hi\n"
8912 "done:"
8913 %}
8914
8915 ins_encode %{
8916 Label done;
8917 Register Rdst = $dst$$Register;
8918 Register Rsrc = $src$$Register;
8919 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8920 __ blsrl(Rdst, Rsrc);
8921 __ jccb(Assembler::carryClear, done);
8922 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8923 __ bind(done);
8924 %}
8925
8926 ins_pipe(ialu_reg);
8927 %}
8928
8929 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8930 %{
8931 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
8932 predicate(UseBMI1Instructions);
8933 effect(KILL cr, TEMP dst);
8934
8935 ins_cost(125);
8936 format %{ "MOVL $dst.hi, $src+4\n\t"
8937 "BLSRL $dst.lo, $src\n\t"
8938 "JNC done\n\t"
8939 "BLSRL $dst.hi, $src+4\n"
8940 "done:"
8941 %}
8942
8943 ins_encode %{
8944 Label done;
8945 Register Rdst = $dst$$Register;
8946 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8947 __ movl(HIGH_FROM_LOW(Rdst), src_hi);
8948 __ blsrl(Rdst, $src$$Address);
8949 __ jccb(Assembler::carryClear, done);
8950 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
8951 __ bind(done);
8952 %}
8953
8954 ins_pipe(ialu_reg_mem);
8955 %}
8956
8957 // Or Long Register with Register
8958 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8959 match(Set dst (OrL dst src));
8960 effect(KILL cr);
8961 format %{ "OR $dst.lo,$src.lo\n\t"
8962 "OR $dst.hi,$src.hi" %}
8963 opcode(0x0B,0x0B);
8964 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8965 ins_pipe( ialu_reg_reg_long );
8966 %}
8967
8968 // Or Long Register with Immediate
8969 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8970 match(Set dst (OrL dst src));
8971 effect(KILL cr);
8972 format %{ "OR $dst.lo,$src.lo\n\t"
8973 "OR $dst.hi,$src.hi" %}
8974 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
8975 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8976 ins_pipe( ialu_reg_long );
8977 %}
8978
8979 // Or Long Register with Memory
8980 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8981 match(Set dst (OrL dst (LoadL mem)));
8982 effect(KILL cr);
8983 ins_cost(125);
8984 format %{ "OR $dst.lo,$mem\n\t"
8985 "OR $dst.hi,$mem+4" %}
8986 opcode(0x0B,0x0B);
8987 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8988 ins_pipe( ialu_reg_long_mem );
8989 %}
8990
8991 // Xor Long Register with Register
8992 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8993 match(Set dst (XorL dst src));
8994 effect(KILL cr);
8995 format %{ "XOR $dst.lo,$src.lo\n\t"
8996 "XOR $dst.hi,$src.hi" %}
8997 opcode(0x33,0x33);
8998 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8999 ins_pipe( ialu_reg_reg_long );
9000 %}
9001
9002 // Xor Long Register with Immediate -1
9003 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9004 match(Set dst (XorL dst imm));
9005 format %{ "NOT $dst.lo\n\t"
9006 "NOT $dst.hi" %}
9007 ins_encode %{
9008 __ notl($dst$$Register);
9009 __ notl(HIGH_FROM_LOW($dst$$Register));
9010 %}
9011 ins_pipe( ialu_reg_long );
9012 %}
9013
9014 // Xor Long Register with Immediate
9015 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9016 match(Set dst (XorL dst src));
9017 effect(KILL cr);
9018 format %{ "XOR $dst.lo,$src.lo\n\t"
9019 "XOR $dst.hi,$src.hi" %}
9020 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9021 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9022 ins_pipe( ialu_reg_long );
9023 %}
9024
9025 // Xor Long Register with Memory
9026 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9027 match(Set dst (XorL dst (LoadL mem)));
9028 effect(KILL cr);
9029 ins_cost(125);
9030 format %{ "XOR $dst.lo,$mem\n\t"
9031 "XOR $dst.hi,$mem+4" %}
9032 opcode(0x33,0x33);
9033 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9034 ins_pipe( ialu_reg_long_mem );
9035 %}
9036
9037 // Shift Left Long by 1
9038 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9039 predicate(UseNewLongLShift);
9040 match(Set dst (LShiftL dst cnt));
9041 effect(KILL cr);
9042 ins_cost(100);
9043 format %{ "ADD $dst.lo,$dst.lo\n\t"
9044 "ADC $dst.hi,$dst.hi" %}
9045 ins_encode %{
9046 __ addl($dst$$Register,$dst$$Register);
9047 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9048 %}
9049 ins_pipe( ialu_reg_long );
9050 %}
9051
9052 // Shift Left Long by 2
9053 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9054 predicate(UseNewLongLShift);
9055 match(Set dst (LShiftL dst cnt));
9056 effect(KILL cr);
9057 ins_cost(100);
9058 format %{ "ADD $dst.lo,$dst.lo\n\t"
9059 "ADC $dst.hi,$dst.hi\n\t"
9060 "ADD $dst.lo,$dst.lo\n\t"
9061 "ADC $dst.hi,$dst.hi" %}
9062 ins_encode %{
9063 __ addl($dst$$Register,$dst$$Register);
9064 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9065 __ addl($dst$$Register,$dst$$Register);
9066 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9067 %}
9068 ins_pipe( ialu_reg_long );
9069 %}
9070
9071 // Shift Left Long by 3
9072 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9073 predicate(UseNewLongLShift);
9074 match(Set dst (LShiftL dst cnt));
9075 effect(KILL cr);
9076 ins_cost(100);
9077 format %{ "ADD $dst.lo,$dst.lo\n\t"
9078 "ADC $dst.hi,$dst.hi\n\t"
9079 "ADD $dst.lo,$dst.lo\n\t"
9080 "ADC $dst.hi,$dst.hi\n\t"
9081 "ADD $dst.lo,$dst.lo\n\t"
9082 "ADC $dst.hi,$dst.hi" %}
9083 ins_encode %{
9084 __ addl($dst$$Register,$dst$$Register);
9085 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9086 __ addl($dst$$Register,$dst$$Register);
9087 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9088 __ addl($dst$$Register,$dst$$Register);
9089 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9090 %}
9091 ins_pipe( ialu_reg_long );
9092 %}
9093
9094 // Shift Left Long by 1-31
9095 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9096 match(Set dst (LShiftL dst cnt));
9097 effect(KILL cr);
9098 ins_cost(200);
9099 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9100 "SHL $dst.lo,$cnt" %}
9101 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9102 ins_encode( move_long_small_shift(dst,cnt) );
9103 ins_pipe( ialu_reg_long );
9104 %}
9105
9106 // Shift Left Long by 32-63
9107 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9108 match(Set dst (LShiftL dst cnt));
9109 effect(KILL cr);
9110 ins_cost(300);
9111 format %{ "MOV $dst.hi,$dst.lo\n"
9112 "\tSHL $dst.hi,$cnt-32\n"
9113 "\tXOR $dst.lo,$dst.lo" %}
9114 opcode(0xC1, 0x4); /* C1 /4 ib */
9115 ins_encode( move_long_big_shift_clr(dst,cnt) );
9116 ins_pipe( ialu_reg_long );
9117 %}
9118
9119 // Shift Left Long by variable
9120 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9121 match(Set dst (LShiftL dst shift));
9122 effect(KILL cr);
9123 ins_cost(500+200);
9124 size(17);
9125 format %{ "TEST $shift,32\n\t"
9126 "JEQ,s small\n\t"
9127 "MOV $dst.hi,$dst.lo\n\t"
9128 "XOR $dst.lo,$dst.lo\n"
9129 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9130 "SHL $dst.lo,$shift" %}
9131 ins_encode( shift_left_long( dst, shift ) );
9132 ins_pipe( pipe_slow );
9133 %}
9134
9135 // Shift Right Long by 1-31
9136 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9137 match(Set dst (URShiftL dst cnt));
9138 effect(KILL cr);
9139 ins_cost(200);
9140 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9141 "SHR $dst.hi,$cnt" %}
9142 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9143 ins_encode( move_long_small_shift(dst,cnt) );
9144 ins_pipe( ialu_reg_long );
9145 %}
9146
9147 // Shift Right Long by 32-63
9148 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9149 match(Set dst (URShiftL dst cnt));
9150 effect(KILL cr);
9151 ins_cost(300);
9152 format %{ "MOV $dst.lo,$dst.hi\n"
9153 "\tSHR $dst.lo,$cnt-32\n"
9154 "\tXOR $dst.hi,$dst.hi" %}
9155 opcode(0xC1, 0x5); /* C1 /5 ib */
9156 ins_encode( move_long_big_shift_clr(dst,cnt) );
9157 ins_pipe( ialu_reg_long );
9158 %}
9159
9160 // Shift Right Long by variable
9161 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9162 match(Set dst (URShiftL dst shift));
9163 effect(KILL cr);
9164 ins_cost(600);
9165 size(17);
9166 format %{ "TEST $shift,32\n\t"
9167 "JEQ,s small\n\t"
9168 "MOV $dst.lo,$dst.hi\n\t"
9169 "XOR $dst.hi,$dst.hi\n"
9170 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9171 "SHR $dst.hi,$shift" %}
9172 ins_encode( shift_right_long( dst, shift ) );
9173 ins_pipe( pipe_slow );
9174 %}
9175
9176 // Shift Right Long by 1-31
9177 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9178 match(Set dst (RShiftL dst cnt));
9179 effect(KILL cr);
9180 ins_cost(200);
9181 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9182 "SAR $dst.hi,$cnt" %}
9183 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9184 ins_encode( move_long_small_shift(dst,cnt) );
9185 ins_pipe( ialu_reg_long );
9186 %}
9187
9188 // Shift Right Long by 32-63
9189 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9190 match(Set dst (RShiftL dst cnt));
9191 effect(KILL cr);
9192 ins_cost(300);
9193 format %{ "MOV $dst.lo,$dst.hi\n"
9194 "\tSAR $dst.lo,$cnt-32\n"
9195 "\tSAR $dst.hi,31" %}
9196 opcode(0xC1, 0x7); /* C1 /7 ib */
9197 ins_encode( move_long_big_shift_sign(dst,cnt) );
9198 ins_pipe( ialu_reg_long );
9199 %}
9200
9201 // Shift Right arithmetic Long by variable
9202 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9203 match(Set dst (RShiftL dst shift));
9204 effect(KILL cr);
9205 ins_cost(600);
9206 size(18);
9207 format %{ "TEST $shift,32\n\t"
9208 "JEQ,s small\n\t"
9209 "MOV $dst.lo,$dst.hi\n\t"
9210 "SAR $dst.hi,31\n"
9211 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9212 "SAR $dst.hi,$shift" %}
9213 ins_encode( shift_right_arith_long( dst, shift ) );
9214 ins_pipe( pipe_slow );
9215 %}
9216
9217
9218 //----------Double Instructions------------------------------------------------
9219 // Double Math
9220
9221 // Compare & branch
9222
9223 // P6 version of float compare, sets condition codes in EFLAGS
9224 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9225 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9226 match(Set cr (CmpD src1 src2));
9227 effect(KILL rax);
9228 ins_cost(150);
9229 format %{ "FLD $src1\n\t"
9230 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9231 "JNP exit\n\t"
9232 "MOV ah,1 // saw a NaN, set CF\n\t"
9233 "SAHF\n"
9234 "exit:\tNOP // avoid branch to branch" %}
9235 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9236 ins_encode( Push_Reg_DPR(src1),
9237 OpcP, RegOpc(src2),
9238 cmpF_P6_fixup );
9239 ins_pipe( pipe_slow );
9240 %}
9241
9242 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9243 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9244 match(Set cr (CmpD src1 src2));
9245 ins_cost(150);
9246 format %{ "FLD $src1\n\t"
9247 "FUCOMIP ST,$src2 // P6 instruction" %}
9248 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9249 ins_encode( Push_Reg_DPR(src1),
9250 OpcP, RegOpc(src2));
9251 ins_pipe( pipe_slow );
9252 %}
9253
9254 // Compare & branch
9255 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9256 predicate(UseSSE<=1);
9257 match(Set cr (CmpD src1 src2));
9258 effect(KILL rax);
9259 ins_cost(200);
9260 format %{ "FLD $src1\n\t"
9261 "FCOMp $src2\n\t"
9262 "FNSTSW AX\n\t"
9263 "TEST AX,0x400\n\t"
9264 "JZ,s flags\n\t"
9265 "MOV AH,1\t# unordered treat as LT\n"
9266 "flags:\tSAHF" %}
9267 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9268 ins_encode( Push_Reg_DPR(src1),
9269 OpcP, RegOpc(src2),
9270 fpu_flags);
9271 ins_pipe( pipe_slow );
9272 %}
9273
9274 // Compare vs zero into -1,0,1
9275 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9276 predicate(UseSSE<=1);
9277 match(Set dst (CmpD3 src1 zero));
9278 effect(KILL cr, KILL rax);
9279 ins_cost(280);
9280 format %{ "FTSTD $dst,$src1" %}
9281 opcode(0xE4, 0xD9);
9282 ins_encode( Push_Reg_DPR(src1),
9283 OpcS, OpcP, PopFPU,
9284 CmpF_Result(dst));
9285 ins_pipe( pipe_slow );
9286 %}
9287
9288 // Compare into -1,0,1
9289 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9290 predicate(UseSSE<=1);
9291 match(Set dst (CmpD3 src1 src2));
9292 effect(KILL cr, KILL rax);
9293 ins_cost(300);
9294 format %{ "FCMPD $dst,$src1,$src2" %}
9295 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9296 ins_encode( Push_Reg_DPR(src1),
9297 OpcP, RegOpc(src2),
9298 CmpF_Result(dst));
9299 ins_pipe( pipe_slow );
9300 %}
9301
9302 // float compare and set condition codes in EFLAGS by XMM regs
9303 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9304 predicate(UseSSE>=2);
9305 match(Set cr (CmpD src1 src2));
9306 ins_cost(145);
9307 format %{ "UCOMISD $src1,$src2\n\t"
9308 "JNP,s exit\n\t"
9309 "PUSHF\t# saw NaN, set CF\n\t"
9310 "AND [rsp], #0xffffff2b\n\t"
9311 "POPF\n"
9312 "exit:" %}
9313 ins_encode %{
9314 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9315 emit_cmpfp_fixup(_masm);
9316 %}
9317 ins_pipe( pipe_slow );
9318 %}
9319
9320 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9321 predicate(UseSSE>=2);
9322 match(Set cr (CmpD src1 src2));
9323 ins_cost(100);
9324 format %{ "UCOMISD $src1,$src2" %}
9325 ins_encode %{
9326 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9327 %}
9328 ins_pipe( pipe_slow );
9329 %}
9330
9331 // float compare and set condition codes in EFLAGS by XMM regs
9332 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9333 predicate(UseSSE>=2);
9334 match(Set cr (CmpD src1 (LoadD src2)));
9335 ins_cost(145);
9336 format %{ "UCOMISD $src1,$src2\n\t"
9337 "JNP,s exit\n\t"
9338 "PUSHF\t# saw NaN, set CF\n\t"
9339 "AND [rsp], #0xffffff2b\n\t"
9340 "POPF\n"
9341 "exit:" %}
9342 ins_encode %{
9343 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9344 emit_cmpfp_fixup(_masm);
9345 %}
9346 ins_pipe( pipe_slow );
9347 %}
9348
9349 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9350 predicate(UseSSE>=2);
9351 match(Set cr (CmpD src1 (LoadD src2)));
9352 ins_cost(100);
9353 format %{ "UCOMISD $src1,$src2" %}
9354 ins_encode %{
9355 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9356 %}
9357 ins_pipe( pipe_slow );
9358 %}
9359
9360 // Compare into -1,0,1 in XMM
9361 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9362 predicate(UseSSE>=2);
9363 match(Set dst (CmpD3 src1 src2));
9364 effect(KILL cr);
9365 ins_cost(255);
9366 format %{ "UCOMISD $src1, $src2\n\t"
9367 "MOV $dst, #-1\n\t"
9368 "JP,s done\n\t"
9369 "JB,s done\n\t"
9370 "SETNE $dst\n\t"
9371 "MOVZB $dst, $dst\n"
9372 "done:" %}
9373 ins_encode %{
9374 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9375 emit_cmpfp3(_masm, $dst$$Register);
9376 %}
9377 ins_pipe( pipe_slow );
9378 %}
9379
9380 // Compare into -1,0,1 in XMM and memory
9381 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9382 predicate(UseSSE>=2);
9383 match(Set dst (CmpD3 src1 (LoadD src2)));
9384 effect(KILL cr);
9385 ins_cost(275);
9386 format %{ "UCOMISD $src1, $src2\n\t"
9387 "MOV $dst, #-1\n\t"
9388 "JP,s done\n\t"
9389 "JB,s done\n\t"
9390 "SETNE $dst\n\t"
9391 "MOVZB $dst, $dst\n"
9392 "done:" %}
9393 ins_encode %{
9394 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9395 emit_cmpfp3(_masm, $dst$$Register);
9396 %}
9397 ins_pipe( pipe_slow );
9398 %}
9399
9400
9401 instruct subDPR_reg(regDPR dst, regDPR src) %{
9402 predicate (UseSSE <=1);
9403 match(Set dst (SubD dst src));
9404
9405 format %{ "FLD $src\n\t"
9406 "DSUBp $dst,ST" %}
9407 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9408 ins_cost(150);
9409 ins_encode( Push_Reg_DPR(src),
9410 OpcP, RegOpc(dst) );
9411 ins_pipe( fpu_reg_reg );
9412 %}
9413
9414 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9415 predicate (UseSSE <=1);
9416 match(Set dst (RoundDouble (SubD src1 src2)));
9417 ins_cost(250);
9418
9419 format %{ "FLD $src2\n\t"
9420 "DSUB ST,$src1\n\t"
9421 "FSTP_D $dst\t# D-round" %}
9422 opcode(0xD8, 0x5);
9423 ins_encode( Push_Reg_DPR(src2),
9424 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9425 ins_pipe( fpu_mem_reg_reg );
9426 %}
9427
9428
9429 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9430 predicate (UseSSE <=1);
9431 match(Set dst (SubD dst (LoadD src)));
9432 ins_cost(150);
9433
9434 format %{ "FLD $src\n\t"
9435 "DSUBp $dst,ST" %}
9436 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9437 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9438 OpcP, RegOpc(dst) );
9439 ins_pipe( fpu_reg_mem );
9440 %}
9441
9442 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9443 predicate (UseSSE<=1);
9444 match(Set dst (AbsD src));
9445 ins_cost(100);
9446 format %{ "FABS" %}
9447 opcode(0xE1, 0xD9);
9448 ins_encode( OpcS, OpcP );
9449 ins_pipe( fpu_reg_reg );
9450 %}
9451
9452 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9453 predicate(UseSSE<=1);
9454 match(Set dst (NegD src));
9455 ins_cost(100);
9456 format %{ "FCHS" %}
9457 opcode(0xE0, 0xD9);
9458 ins_encode( OpcS, OpcP );
9459 ins_pipe( fpu_reg_reg );
9460 %}
9461
9462 instruct addDPR_reg(regDPR dst, regDPR src) %{
9463 predicate(UseSSE<=1);
9464 match(Set dst (AddD dst src));
9465 format %{ "FLD $src\n\t"
9466 "DADD $dst,ST" %}
9467 size(4);
9468 ins_cost(150);
9469 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9470 ins_encode( Push_Reg_DPR(src),
9471 OpcP, RegOpc(dst) );
9472 ins_pipe( fpu_reg_reg );
9473 %}
9474
9475
9476 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9477 predicate(UseSSE<=1);
9478 match(Set dst (RoundDouble (AddD src1 src2)));
9479 ins_cost(250);
9480
9481 format %{ "FLD $src2\n\t"
9482 "DADD ST,$src1\n\t"
9483 "FSTP_D $dst\t# D-round" %}
9484 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9485 ins_encode( Push_Reg_DPR(src2),
9486 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9487 ins_pipe( fpu_mem_reg_reg );
9488 %}
9489
9490
9491 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9492 predicate(UseSSE<=1);
9493 match(Set dst (AddD dst (LoadD src)));
9494 ins_cost(150);
9495
9496 format %{ "FLD $src\n\t"
9497 "DADDp $dst,ST" %}
9498 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9499 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9500 OpcP, RegOpc(dst) );
9501 ins_pipe( fpu_reg_mem );
9502 %}
9503
9504 // add-to-memory
9505 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9506 predicate(UseSSE<=1);
9507 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9508 ins_cost(150);
9509
9510 format %{ "FLD_D $dst\n\t"
9511 "DADD ST,$src\n\t"
9512 "FST_D $dst" %}
9513 opcode(0xDD, 0x0);
9514 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9515 Opcode(0xD8), RegOpc(src),
9516 set_instruction_start,
9517 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9518 ins_pipe( fpu_reg_mem );
9519 %}
9520
9521 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9522 predicate(UseSSE<=1);
9523 match(Set dst (AddD dst con));
9524 ins_cost(125);
9525 format %{ "FLD1\n\t"
9526 "DADDp $dst,ST" %}
9527 ins_encode %{
9528 __ fld1();
9529 __ faddp($dst$$reg);
9530 %}
9531 ins_pipe(fpu_reg);
9532 %}
9533
9534 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9535 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9536 match(Set dst (AddD dst con));
9537 ins_cost(200);
9538 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9539 "DADDp $dst,ST" %}
9540 ins_encode %{
9541 __ fld_d($constantaddress($con));
9542 __ faddp($dst$$reg);
9543 %}
9544 ins_pipe(fpu_reg_mem);
9545 %}
9546
9547 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9548 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9549 match(Set dst (RoundDouble (AddD src con)));
9550 ins_cost(200);
9551 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9552 "DADD ST,$src\n\t"
9553 "FSTP_D $dst\t# D-round" %}
9554 ins_encode %{
9555 __ fld_d($constantaddress($con));
9556 __ fadd($src$$reg);
9557 __ fstp_d(Address(rsp, $dst$$disp));
9558 %}
9559 ins_pipe(fpu_mem_reg_con);
9560 %}
9561
9562 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9563 predicate(UseSSE<=1);
9564 match(Set dst (MulD dst src));
9565 format %{ "FLD $src\n\t"
9566 "DMULp $dst,ST" %}
9567 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9568 ins_cost(150);
9569 ins_encode( Push_Reg_DPR(src),
9570 OpcP, RegOpc(dst) );
9571 ins_pipe( fpu_reg_reg );
9572 %}
9573
9574 // Strict FP instruction biases argument before multiply then
9575 // biases result to avoid double rounding of subnormals.
9576 //
9577 // scale arg1 by multiplying arg1 by 2^(-15360)
9578 // load arg2
9579 // multiply scaled arg1 by arg2
9580 // rescale product by 2^(15360)
9581 //
9582 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9583 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9584 match(Set dst (MulD dst src));
9585 ins_cost(1); // Select this instruction for all strict FP double multiplies
9586
9587 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9588 "DMULp $dst,ST\n\t"
9589 "FLD $src\n\t"
9590 "DMULp $dst,ST\n\t"
9591 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9592 "DMULp $dst,ST\n\t" %}
9593 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9594 ins_encode( strictfp_bias1(dst),
9595 Push_Reg_DPR(src),
9596 OpcP, RegOpc(dst),
9597 strictfp_bias2(dst) );
9598 ins_pipe( fpu_reg_reg );
9599 %}
9600
9601 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9602 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9603 match(Set dst (MulD dst con));
9604 ins_cost(200);
9605 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9606 "DMULp $dst,ST" %}
9607 ins_encode %{
9608 __ fld_d($constantaddress($con));
9609 __ fmulp($dst$$reg);
9610 %}
9611 ins_pipe(fpu_reg_mem);
9612 %}
9613
9614
9615 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9616 predicate( UseSSE<=1 );
9617 match(Set dst (MulD dst (LoadD src)));
9618 ins_cost(200);
9619 format %{ "FLD_D $src\n\t"
9620 "DMULp $dst,ST" %}
9621 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9622 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9623 OpcP, RegOpc(dst) );
9624 ins_pipe( fpu_reg_mem );
9625 %}
9626
9627 //
9628 // Cisc-alternate to reg-reg multiply
9629 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9630 predicate( UseSSE<=1 );
9631 match(Set dst (MulD src (LoadD mem)));
9632 ins_cost(250);
9633 format %{ "FLD_D $mem\n\t"
9634 "DMUL ST,$src\n\t"
9635 "FSTP_D $dst" %}
9636 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9637 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9638 OpcReg_FPR(src),
9639 Pop_Reg_DPR(dst) );
9640 ins_pipe( fpu_reg_reg_mem );
9641 %}
9642
9643
9644 // MACRO3 -- addDPR a mulDPR
9645 // This instruction is a '2-address' instruction in that the result goes
9646 // back to src2. This eliminates a move from the macro; possibly the
9647 // register allocator will have to add it back (and maybe not).
9648 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9649 predicate( UseSSE<=1 );
9650 match(Set src2 (AddD (MulD src0 src1) src2));
9651 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9652 "DMUL ST,$src1\n\t"
9653 "DADDp $src2,ST" %}
9654 ins_cost(250);
9655 opcode(0xDD); /* LoadD DD /0 */
9656 ins_encode( Push_Reg_FPR(src0),
9657 FMul_ST_reg(src1),
9658 FAddP_reg_ST(src2) );
9659 ins_pipe( fpu_reg_reg_reg );
9660 %}
9661
9662
9663 // MACRO3 -- subDPR a mulDPR
9664 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9665 predicate( UseSSE<=1 );
9666 match(Set src2 (SubD (MulD src0 src1) src2));
9667 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9668 "DMUL ST,$src1\n\t"
9669 "DSUBRp $src2,ST" %}
9670 ins_cost(250);
9671 ins_encode( Push_Reg_FPR(src0),
9672 FMul_ST_reg(src1),
9673 Opcode(0xDE), Opc_plus(0xE0,src2));
9674 ins_pipe( fpu_reg_reg_reg );
9675 %}
9676
9677
9678 instruct divDPR_reg(regDPR dst, regDPR src) %{
9679 predicate( UseSSE<=1 );
9680 match(Set dst (DivD dst src));
9681
9682 format %{ "FLD $src\n\t"
9683 "FDIVp $dst,ST" %}
9684 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9685 ins_cost(150);
9686 ins_encode( Push_Reg_DPR(src),
9687 OpcP, RegOpc(dst) );
9688 ins_pipe( fpu_reg_reg );
9689 %}
9690
9691 // Strict FP instruction biases argument before division then
9692 // biases result, to avoid double rounding of subnormals.
9693 //
9694 // scale dividend by multiplying dividend by 2^(-15360)
9695 // load divisor
9696 // divide scaled dividend by divisor
9697 // rescale quotient by 2^(15360)
9698 //
9699 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9700 predicate (UseSSE<=1);
9701 match(Set dst (DivD dst src));
9702 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9703 ins_cost(01);
9704
9705 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9706 "DMULp $dst,ST\n\t"
9707 "FLD $src\n\t"
9708 "FDIVp $dst,ST\n\t"
9709 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9710 "DMULp $dst,ST\n\t" %}
9711 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9712 ins_encode( strictfp_bias1(dst),
9713 Push_Reg_DPR(src),
9714 OpcP, RegOpc(dst),
9715 strictfp_bias2(dst) );
9716 ins_pipe( fpu_reg_reg );
9717 %}
9718
9719 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9720 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9721 match(Set dst (RoundDouble (DivD src1 src2)));
9722
9723 format %{ "FLD $src1\n\t"
9724 "FDIV ST,$src2\n\t"
9725 "FSTP_D $dst\t# D-round" %}
9726 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9727 ins_encode( Push_Reg_DPR(src1),
9728 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9729 ins_pipe( fpu_mem_reg_reg );
9730 %}
9731
9732
9733 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9734 predicate(UseSSE<=1);
9735 match(Set dst (ModD dst src));
9736 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9737
9738 format %{ "DMOD $dst,$src" %}
9739 ins_cost(250);
9740 ins_encode(Push_Reg_Mod_DPR(dst, src),
9741 emitModDPR(),
9742 Push_Result_Mod_DPR(src),
9743 Pop_Reg_DPR(dst));
9744 ins_pipe( pipe_slow );
9745 %}
9746
9747 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9748 predicate(UseSSE>=2);
9749 match(Set dst (ModD src0 src1));
9750 effect(KILL rax, KILL cr);
9751
9752 format %{ "SUB ESP,8\t # DMOD\n"
9753 "\tMOVSD [ESP+0],$src1\n"
9754 "\tFLD_D [ESP+0]\n"
9755 "\tMOVSD [ESP+0],$src0\n"
9756 "\tFLD_D [ESP+0]\n"
9757 "loop:\tFPREM\n"
9758 "\tFWAIT\n"
9759 "\tFNSTSW AX\n"
9760 "\tSAHF\n"
9761 "\tJP loop\n"
9762 "\tFSTP_D [ESP+0]\n"
9763 "\tMOVSD $dst,[ESP+0]\n"
9764 "\tADD ESP,8\n"
9765 "\tFSTP ST0\t # Restore FPU Stack"
9766 %}
9767 ins_cost(250);
9768 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9769 ins_pipe( pipe_slow );
9770 %}
9771
9772 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9773 predicate (UseSSE<=1);
9774 match(Set dst (SinD src));
9775 ins_cost(1800);
9776 format %{ "DSIN $dst" %}
9777 opcode(0xD9, 0xFE);
9778 ins_encode( OpcP, OpcS );
9779 ins_pipe( pipe_slow );
9780 %}
9781
9782 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9783 predicate (UseSSE>=2);
9784 match(Set dst (SinD dst));
9785 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9786 ins_cost(1800);
9787 format %{ "DSIN $dst" %}
9788 opcode(0xD9, 0xFE);
9789 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9790 ins_pipe( pipe_slow );
9791 %}
9792
9793 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9794 predicate (UseSSE<=1);
9795 match(Set dst (CosD src));
9796 ins_cost(1800);
9797 format %{ "DCOS $dst" %}
9798 opcode(0xD9, 0xFF);
9799 ins_encode( OpcP, OpcS );
9800 ins_pipe( pipe_slow );
9801 %}
9802
9803 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9804 predicate (UseSSE>=2);
9805 match(Set dst (CosD dst));
9806 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9807 ins_cost(1800);
9808 format %{ "DCOS $dst" %}
9809 opcode(0xD9, 0xFF);
9810 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9811 ins_pipe( pipe_slow );
9812 %}
9813
9814 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9815 predicate (UseSSE<=1);
9816 match(Set dst(TanD src));
9817 format %{ "DTAN $dst" %}
9818 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9819 Opcode(0xDD), Opcode(0xD8)); // fstp st
9820 ins_pipe( pipe_slow );
9821 %}
9822
9823 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9824 predicate (UseSSE>=2);
9825 match(Set dst(TanD dst));
9826 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9827 format %{ "DTAN $dst" %}
9828 ins_encode( Push_SrcD(dst),
9829 Opcode(0xD9), Opcode(0xF2), // fptan
9830 Opcode(0xDD), Opcode(0xD8), // fstp st
9831 Push_ResultD(dst) );
9832 ins_pipe( pipe_slow );
9833 %}
9834
9835 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9836 predicate (UseSSE<=1);
9837 match(Set dst(AtanD dst src));
9838 format %{ "DATA $dst,$src" %}
9839 opcode(0xD9, 0xF3);
9840 ins_encode( Push_Reg_DPR(src),
9841 OpcP, OpcS, RegOpc(dst) );
9842 ins_pipe( pipe_slow );
9843 %}
9844
9845 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9846 predicate (UseSSE>=2);
9847 match(Set dst(AtanD dst src));
9848 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9849 format %{ "DATA $dst,$src" %}
9850 opcode(0xD9, 0xF3);
9851 ins_encode( Push_SrcD(src),
9852 OpcP, OpcS, Push_ResultD(dst) );
9853 ins_pipe( pipe_slow );
9854 %}
9855
9856 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9857 predicate (UseSSE<=1);
9858 match(Set dst (SqrtD src));
9859 format %{ "DSQRT $dst,$src" %}
9860 opcode(0xFA, 0xD9);
9861 ins_encode( Push_Reg_DPR(src),
9862 OpcS, OpcP, Pop_Reg_DPR(dst) );
9863 ins_pipe( pipe_slow );
9864 %}
9865
9866 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9867 predicate (UseSSE<=1);
9868 match(Set Y (PowD X Y)); // Raise X to the Yth power
9869 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9870 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9871 ins_encode %{
9872 __ subptr(rsp, 8);
9873 __ fld_s($X$$reg - 1);
9874 __ fast_pow();
9875 __ addptr(rsp, 8);
9876 %}
9877 ins_pipe( pipe_slow );
9878 %}
9879
9880 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9881 predicate (UseSSE>=2);
9882 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9883 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9884 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9885 ins_encode %{
9886 __ subptr(rsp, 8);
9887 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9888 __ fld_d(Address(rsp, 0));
9889 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9890 __ fld_d(Address(rsp, 0));
9891 __ fast_pow();
9892 __ fstp_d(Address(rsp, 0));
9893 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9894 __ addptr(rsp, 8);
9895 %}
9896 ins_pipe( pipe_slow );
9897 %}
9898
9899
9900 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9901 predicate (UseSSE<=1);
9902 match(Set dpr1 (ExpD dpr1));
9903 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9904 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9905 ins_encode %{
9906 __ fast_exp();
9907 %}
9908 ins_pipe( pipe_slow );
9909 %}
9910
9911 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9912 predicate (UseSSE>=2);
9913 match(Set dst (ExpD src));
9914 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9915 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9916 ins_encode %{
9917 __ subptr(rsp, 8);
9918 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9919 __ fld_d(Address(rsp, 0));
9920 __ fast_exp();
9921 __ fstp_d(Address(rsp, 0));
9922 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9923 __ addptr(rsp, 8);
9924 %}
9925 ins_pipe( pipe_slow );
9926 %}
9927
9928 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9929 predicate (UseSSE<=1);
9930 // The source Double operand on FPU stack
9931 match(Set dst (Log10D src));
9932 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9933 // fxch ; swap ST(0) with ST(1)
9934 // fyl2x ; compute log_10(2) * log_2(x)
9935 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9936 "FXCH \n\t"
9937 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9938 %}
9939 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9940 Opcode(0xD9), Opcode(0xC9), // fxch
9941 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9942
9943 ins_pipe( pipe_slow );
9944 %}
9945
9946 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9947 predicate (UseSSE>=2);
9948 effect(KILL cr);
9949 match(Set dst (Log10D src));
9950 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9951 // fyl2x ; compute log_10(2) * log_2(x)
9952 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9953 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9954 %}
9955 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9956 Push_SrcD(src),
9957 Opcode(0xD9), Opcode(0xF1), // fyl2x
9958 Push_ResultD(dst));
9959
9960 ins_pipe( pipe_slow );
9961 %}
9962
9963 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
9964 predicate (UseSSE<=1);
9965 // The source Double operand on FPU stack
9966 match(Set dst (LogD src));
9967 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9968 // fxch ; swap ST(0) with ST(1)
9969 // fyl2x ; compute log_e(2) * log_2(x)
9970 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9971 "FXCH \n\t"
9972 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9973 %}
9974 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9975 Opcode(0xD9), Opcode(0xC9), // fxch
9976 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9977
9978 ins_pipe( pipe_slow );
9979 %}
9980
9981 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
9982 predicate (UseSSE>=2);
9983 effect(KILL cr);
9984 // The source and result Double operands in XMM registers
9985 match(Set dst (LogD src));
9986 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9987 // fyl2x ; compute log_e(2) * log_2(x)
9988 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9989 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9990 %}
9991 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9992 Push_SrcD(src),
9993 Opcode(0xD9), Opcode(0xF1), // fyl2x
9994 Push_ResultD(dst));
9995 ins_pipe( pipe_slow );
9996 %}
9997
9998 //-------------Float Instructions-------------------------------
9999 // Float Math
10000
10001 // Code for float compare:
10002 // fcompp();
10003 // fwait(); fnstsw_ax();
10004 // sahf();
10005 // movl(dst, unordered_result);
10006 // jcc(Assembler::parity, exit);
10007 // movl(dst, less_result);
10008 // jcc(Assembler::below, exit);
10009 // movl(dst, equal_result);
10010 // jcc(Assembler::equal, exit);
10011 // movl(dst, greater_result);
10012 // exit:
10013
10014 // P6 version of float compare, sets condition codes in EFLAGS
10015 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10016 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10017 match(Set cr (CmpF src1 src2));
10018 effect(KILL rax);
10019 ins_cost(150);
10020 format %{ "FLD $src1\n\t"
10021 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10022 "JNP exit\n\t"
10023 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10024 "SAHF\n"
10025 "exit:\tNOP // avoid branch to branch" %}
10026 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10027 ins_encode( Push_Reg_DPR(src1),
10028 OpcP, RegOpc(src2),
10029 cmpF_P6_fixup );
10030 ins_pipe( pipe_slow );
10031 %}
10032
10033 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10034 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10035 match(Set cr (CmpF src1 src2));
10036 ins_cost(100);
10037 format %{ "FLD $src1\n\t"
10038 "FUCOMIP ST,$src2 // P6 instruction" %}
10039 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10040 ins_encode( Push_Reg_DPR(src1),
10041 OpcP, RegOpc(src2));
10042 ins_pipe( pipe_slow );
10043 %}
10044
10045
10046 // Compare & branch
10047 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10048 predicate(UseSSE == 0);
10049 match(Set cr (CmpF src1 src2));
10050 effect(KILL rax);
10051 ins_cost(200);
10052 format %{ "FLD $src1\n\t"
10053 "FCOMp $src2\n\t"
10054 "FNSTSW AX\n\t"
10055 "TEST AX,0x400\n\t"
10056 "JZ,s flags\n\t"
10057 "MOV AH,1\t# unordered treat as LT\n"
10058 "flags:\tSAHF" %}
10059 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10060 ins_encode( Push_Reg_DPR(src1),
10061 OpcP, RegOpc(src2),
10062 fpu_flags);
10063 ins_pipe( pipe_slow );
10064 %}
10065
10066 // Compare vs zero into -1,0,1
10067 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10068 predicate(UseSSE == 0);
10069 match(Set dst (CmpF3 src1 zero));
10070 effect(KILL cr, KILL rax);
10071 ins_cost(280);
10072 format %{ "FTSTF $dst,$src1" %}
10073 opcode(0xE4, 0xD9);
10074 ins_encode( Push_Reg_DPR(src1),
10075 OpcS, OpcP, PopFPU,
10076 CmpF_Result(dst));
10077 ins_pipe( pipe_slow );
10078 %}
10079
10080 // Compare into -1,0,1
10081 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10082 predicate(UseSSE == 0);
10083 match(Set dst (CmpF3 src1 src2));
10084 effect(KILL cr, KILL rax);
10085 ins_cost(300);
10086 format %{ "FCMPF $dst,$src1,$src2" %}
10087 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10088 ins_encode( Push_Reg_DPR(src1),
10089 OpcP, RegOpc(src2),
10090 CmpF_Result(dst));
10091 ins_pipe( pipe_slow );
10092 %}
10093
10094 // float compare and set condition codes in EFLAGS by XMM regs
10095 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10096 predicate(UseSSE>=1);
10097 match(Set cr (CmpF src1 src2));
10098 ins_cost(145);
10099 format %{ "UCOMISS $src1,$src2\n\t"
10100 "JNP,s exit\n\t"
10101 "PUSHF\t# saw NaN, set CF\n\t"
10102 "AND [rsp], #0xffffff2b\n\t"
10103 "POPF\n"
10104 "exit:" %}
10105 ins_encode %{
10106 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10107 emit_cmpfp_fixup(_masm);
10108 %}
10109 ins_pipe( pipe_slow );
10110 %}
10111
10112 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10113 predicate(UseSSE>=1);
10114 match(Set cr (CmpF src1 src2));
10115 ins_cost(100);
10116 format %{ "UCOMISS $src1,$src2" %}
10117 ins_encode %{
10118 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10119 %}
10120 ins_pipe( pipe_slow );
10121 %}
10122
10123 // float compare and set condition codes in EFLAGS by XMM regs
10124 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10125 predicate(UseSSE>=1);
10126 match(Set cr (CmpF src1 (LoadF src2)));
10127 ins_cost(165);
10128 format %{ "UCOMISS $src1,$src2\n\t"
10129 "JNP,s exit\n\t"
10130 "PUSHF\t# saw NaN, set CF\n\t"
10131 "AND [rsp], #0xffffff2b\n\t"
10132 "POPF\n"
10133 "exit:" %}
10134 ins_encode %{
10135 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10136 emit_cmpfp_fixup(_masm);
10137 %}
10138 ins_pipe( pipe_slow );
10139 %}
10140
10141 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10142 predicate(UseSSE>=1);
10143 match(Set cr (CmpF src1 (LoadF src2)));
10144 ins_cost(100);
10145 format %{ "UCOMISS $src1,$src2" %}
10146 ins_encode %{
10147 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10148 %}
10149 ins_pipe( pipe_slow );
10150 %}
10151
10152 // Compare into -1,0,1 in XMM
10153 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10154 predicate(UseSSE>=1);
10155 match(Set dst (CmpF3 src1 src2));
10156 effect(KILL cr);
10157 ins_cost(255);
10158 format %{ "UCOMISS $src1, $src2\n\t"
10159 "MOV $dst, #-1\n\t"
10160 "JP,s done\n\t"
10161 "JB,s done\n\t"
10162 "SETNE $dst\n\t"
10163 "MOVZB $dst, $dst\n"
10164 "done:" %}
10165 ins_encode %{
10166 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10167 emit_cmpfp3(_masm, $dst$$Register);
10168 %}
10169 ins_pipe( pipe_slow );
10170 %}
10171
10172 // Compare into -1,0,1 in XMM and memory
10173 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10174 predicate(UseSSE>=1);
10175 match(Set dst (CmpF3 src1 (LoadF src2)));
10176 effect(KILL cr);
10177 ins_cost(275);
10178 format %{ "UCOMISS $src1, $src2\n\t"
10179 "MOV $dst, #-1\n\t"
10180 "JP,s done\n\t"
10181 "JB,s done\n\t"
10182 "SETNE $dst\n\t"
10183 "MOVZB $dst, $dst\n"
10184 "done:" %}
10185 ins_encode %{
10186 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10187 emit_cmpfp3(_masm, $dst$$Register);
10188 %}
10189 ins_pipe( pipe_slow );
10190 %}
10191
10192 // Spill to obtain 24-bit precision
10193 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10194 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10195 match(Set dst (SubF src1 src2));
10196
10197 format %{ "FSUB $dst,$src1 - $src2" %}
10198 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10199 ins_encode( Push_Reg_FPR(src1),
10200 OpcReg_FPR(src2),
10201 Pop_Mem_FPR(dst) );
10202 ins_pipe( fpu_mem_reg_reg );
10203 %}
10204 //
10205 // This instruction does not round to 24-bits
10206 instruct subFPR_reg(regFPR dst, regFPR src) %{
10207 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10208 match(Set dst (SubF dst src));
10209
10210 format %{ "FSUB $dst,$src" %}
10211 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10212 ins_encode( Push_Reg_FPR(src),
10213 OpcP, RegOpc(dst) );
10214 ins_pipe( fpu_reg_reg );
10215 %}
10216
10217 // Spill to obtain 24-bit precision
10218 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10219 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10220 match(Set dst (AddF src1 src2));
10221
10222 format %{ "FADD $dst,$src1,$src2" %}
10223 opcode(0xD8, 0x0); /* D8 C0+i */
10224 ins_encode( Push_Reg_FPR(src2),
10225 OpcReg_FPR(src1),
10226 Pop_Mem_FPR(dst) );
10227 ins_pipe( fpu_mem_reg_reg );
10228 %}
10229 //
10230 // This instruction does not round to 24-bits
10231 instruct addFPR_reg(regFPR dst, regFPR src) %{
10232 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10233 match(Set dst (AddF dst src));
10234
10235 format %{ "FLD $src\n\t"
10236 "FADDp $dst,ST" %}
10237 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10238 ins_encode( Push_Reg_FPR(src),
10239 OpcP, RegOpc(dst) );
10240 ins_pipe( fpu_reg_reg );
10241 %}
10242
10243 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10244 predicate(UseSSE==0);
10245 match(Set dst (AbsF src));
10246 ins_cost(100);
10247 format %{ "FABS" %}
10248 opcode(0xE1, 0xD9);
10249 ins_encode( OpcS, OpcP );
10250 ins_pipe( fpu_reg_reg );
10251 %}
10252
10253 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10254 predicate(UseSSE==0);
10255 match(Set dst (NegF src));
10256 ins_cost(100);
10257 format %{ "FCHS" %}
10258 opcode(0xE0, 0xD9);
10259 ins_encode( OpcS, OpcP );
10260 ins_pipe( fpu_reg_reg );
10261 %}
10262
10263 // Cisc-alternate to addFPR_reg
10264 // Spill to obtain 24-bit precision
10265 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10266 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10267 match(Set dst (AddF src1 (LoadF src2)));
10268
10269 format %{ "FLD $src2\n\t"
10270 "FADD ST,$src1\n\t"
10271 "FSTP_S $dst" %}
10272 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10273 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10274 OpcReg_FPR(src1),
10275 Pop_Mem_FPR(dst) );
10276 ins_pipe( fpu_mem_reg_mem );
10277 %}
10278 //
10279 // Cisc-alternate to addFPR_reg
10280 // This instruction does not round to 24-bits
10281 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10282 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10283 match(Set dst (AddF dst (LoadF src)));
10284
10285 format %{ "FADD $dst,$src" %}
10286 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10287 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10288 OpcP, RegOpc(dst) );
10289 ins_pipe( fpu_reg_mem );
10290 %}
10291
10292 // // Following two instructions for _222_mpegaudio
10293 // Spill to obtain 24-bit precision
10294 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10295 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10296 match(Set dst (AddF src1 src2));
10297
10298 format %{ "FADD $dst,$src1,$src2" %}
10299 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10300 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10301 OpcReg_FPR(src2),
10302 Pop_Mem_FPR(dst) );
10303 ins_pipe( fpu_mem_reg_mem );
10304 %}
10305
10306 // Cisc-spill variant
10307 // Spill to obtain 24-bit precision
10308 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10309 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10310 match(Set dst (AddF src1 (LoadF src2)));
10311
10312 format %{ "FADD $dst,$src1,$src2 cisc" %}
10313 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10314 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10315 set_instruction_start,
10316 OpcP, RMopc_Mem(secondary,src1),
10317 Pop_Mem_FPR(dst) );
10318 ins_pipe( fpu_mem_mem_mem );
10319 %}
10320
10321 // Spill to obtain 24-bit precision
10322 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10323 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10324 match(Set dst (AddF src1 src2));
10325
10326 format %{ "FADD $dst,$src1,$src2" %}
10327 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10328 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10329 set_instruction_start,
10330 OpcP, RMopc_Mem(secondary,src1),
10331 Pop_Mem_FPR(dst) );
10332 ins_pipe( fpu_mem_mem_mem );
10333 %}
10334
10335
10336 // Spill to obtain 24-bit precision
10337 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10338 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10339 match(Set dst (AddF src con));
10340 format %{ "FLD $src\n\t"
10341 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10342 "FSTP_S $dst" %}
10343 ins_encode %{
10344 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10345 __ fadd_s($constantaddress($con));
10346 __ fstp_s(Address(rsp, $dst$$disp));
10347 %}
10348 ins_pipe(fpu_mem_reg_con);
10349 %}
10350 //
10351 // This instruction does not round to 24-bits
10352 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10353 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10354 match(Set dst (AddF src con));
10355 format %{ "FLD $src\n\t"
10356 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10357 "FSTP $dst" %}
10358 ins_encode %{
10359 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10360 __ fadd_s($constantaddress($con));
10361 __ fstp_d($dst$$reg);
10362 %}
10363 ins_pipe(fpu_reg_reg_con);
10364 %}
10365
10366 // Spill to obtain 24-bit precision
10367 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10368 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10369 match(Set dst (MulF src1 src2));
10370
10371 format %{ "FLD $src1\n\t"
10372 "FMUL $src2\n\t"
10373 "FSTP_S $dst" %}
10374 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10375 ins_encode( Push_Reg_FPR(src1),
10376 OpcReg_FPR(src2),
10377 Pop_Mem_FPR(dst) );
10378 ins_pipe( fpu_mem_reg_reg );
10379 %}
10380 //
10381 // This instruction does not round to 24-bits
10382 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10383 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10384 match(Set dst (MulF src1 src2));
10385
10386 format %{ "FLD $src1\n\t"
10387 "FMUL $src2\n\t"
10388 "FSTP_S $dst" %}
10389 opcode(0xD8, 0x1); /* D8 C8+i */
10390 ins_encode( Push_Reg_FPR(src2),
10391 OpcReg_FPR(src1),
10392 Pop_Reg_FPR(dst) );
10393 ins_pipe( fpu_reg_reg_reg );
10394 %}
10395
10396
10397 // Spill to obtain 24-bit precision
10398 // Cisc-alternate to reg-reg multiply
10399 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10400 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10401 match(Set dst (MulF src1 (LoadF src2)));
10402
10403 format %{ "FLD_S $src2\n\t"
10404 "FMUL $src1\n\t"
10405 "FSTP_S $dst" %}
10406 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10407 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10408 OpcReg_FPR(src1),
10409 Pop_Mem_FPR(dst) );
10410 ins_pipe( fpu_mem_reg_mem );
10411 %}
10412 //
10413 // This instruction does not round to 24-bits
10414 // Cisc-alternate to reg-reg multiply
10415 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10416 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10417 match(Set dst (MulF src1 (LoadF src2)));
10418
10419 format %{ "FMUL $dst,$src1,$src2" %}
10420 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10421 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10422 OpcReg_FPR(src1),
10423 Pop_Reg_FPR(dst) );
10424 ins_pipe( fpu_reg_reg_mem );
10425 %}
10426
10427 // Spill to obtain 24-bit precision
10428 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10429 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10430 match(Set dst (MulF src1 src2));
10431
10432 format %{ "FMUL $dst,$src1,$src2" %}
10433 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10434 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10435 set_instruction_start,
10436 OpcP, RMopc_Mem(secondary,src1),
10437 Pop_Mem_FPR(dst) );
10438 ins_pipe( fpu_mem_mem_mem );
10439 %}
10440
10441 // Spill to obtain 24-bit precision
10442 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10443 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10444 match(Set dst (MulF src con));
10445
10446 format %{ "FLD $src\n\t"
10447 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10448 "FSTP_S $dst" %}
10449 ins_encode %{
10450 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10451 __ fmul_s($constantaddress($con));
10452 __ fstp_s(Address(rsp, $dst$$disp));
10453 %}
10454 ins_pipe(fpu_mem_reg_con);
10455 %}
10456 //
10457 // This instruction does not round to 24-bits
10458 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10459 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10460 match(Set dst (MulF src con));
10461
10462 format %{ "FLD $src\n\t"
10463 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10464 "FSTP $dst" %}
10465 ins_encode %{
10466 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10467 __ fmul_s($constantaddress($con));
10468 __ fstp_d($dst$$reg);
10469 %}
10470 ins_pipe(fpu_reg_reg_con);
10471 %}
10472
10473
10474 //
10475 // MACRO1 -- subsume unshared load into mulFPR
10476 // This instruction does not round to 24-bits
10477 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10478 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10479 match(Set dst (MulF (LoadF mem1) src));
10480
10481 format %{ "FLD $mem1 ===MACRO1===\n\t"
10482 "FMUL ST,$src\n\t"
10483 "FSTP $dst" %}
10484 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10485 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10486 OpcReg_FPR(src),
10487 Pop_Reg_FPR(dst) );
10488 ins_pipe( fpu_reg_reg_mem );
10489 %}
10490 //
10491 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10492 // This instruction does not round to 24-bits
10493 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10494 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10495 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10496 ins_cost(95);
10497
10498 format %{ "FLD $mem1 ===MACRO2===\n\t"
10499 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10500 "FADD ST,$src2\n\t"
10501 "FSTP $dst" %}
10502 opcode(0xD9); /* LoadF D9 /0 */
10503 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10504 FMul_ST_reg(src1),
10505 FAdd_ST_reg(src2),
10506 Pop_Reg_FPR(dst) );
10507 ins_pipe( fpu_reg_mem_reg_reg );
10508 %}
10509
10510 // MACRO3 -- addFPR a mulFPR
10511 // This instruction does not round to 24-bits. It is a '2-address'
10512 // instruction in that the result goes back to src2. This eliminates
10513 // a move from the macro; possibly the register allocator will have
10514 // to add it back (and maybe not).
10515 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10516 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10517 match(Set src2 (AddF (MulF src0 src1) src2));
10518
10519 format %{ "FLD $src0 ===MACRO3===\n\t"
10520 "FMUL ST,$src1\n\t"
10521 "FADDP $src2,ST" %}
10522 opcode(0xD9); /* LoadF D9 /0 */
10523 ins_encode( Push_Reg_FPR(src0),
10524 FMul_ST_reg(src1),
10525 FAddP_reg_ST(src2) );
10526 ins_pipe( fpu_reg_reg_reg );
10527 %}
10528
10529 // MACRO4 -- divFPR subFPR
10530 // This instruction does not round to 24-bits
10531 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10532 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10533 match(Set dst (DivF (SubF src2 src1) src3));
10534
10535 format %{ "FLD $src2 ===MACRO4===\n\t"
10536 "FSUB ST,$src1\n\t"
10537 "FDIV ST,$src3\n\t"
10538 "FSTP $dst" %}
10539 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10540 ins_encode( Push_Reg_FPR(src2),
10541 subFPR_divFPR_encode(src1,src3),
10542 Pop_Reg_FPR(dst) );
10543 ins_pipe( fpu_reg_reg_reg_reg );
10544 %}
10545
10546 // Spill to obtain 24-bit precision
10547 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10548 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10549 match(Set dst (DivF src1 src2));
10550
10551 format %{ "FDIV $dst,$src1,$src2" %}
10552 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10553 ins_encode( Push_Reg_FPR(src1),
10554 OpcReg_FPR(src2),
10555 Pop_Mem_FPR(dst) );
10556 ins_pipe( fpu_mem_reg_reg );
10557 %}
10558 //
10559 // This instruction does not round to 24-bits
10560 instruct divFPR_reg(regFPR dst, regFPR src) %{
10561 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10562 match(Set dst (DivF dst src));
10563
10564 format %{ "FDIV $dst,$src" %}
10565 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10566 ins_encode( Push_Reg_FPR(src),
10567 OpcP, RegOpc(dst) );
10568 ins_pipe( fpu_reg_reg );
10569 %}
10570
10571
10572 // Spill to obtain 24-bit precision
10573 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10574 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10575 match(Set dst (ModF src1 src2));
10576 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10577
10578 format %{ "FMOD $dst,$src1,$src2" %}
10579 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10580 emitModDPR(),
10581 Push_Result_Mod_DPR(src2),
10582 Pop_Mem_FPR(dst));
10583 ins_pipe( pipe_slow );
10584 %}
10585 //
10586 // This instruction does not round to 24-bits
10587 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10588 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10589 match(Set dst (ModF dst src));
10590 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10591
10592 format %{ "FMOD $dst,$src" %}
10593 ins_encode(Push_Reg_Mod_DPR(dst, src),
10594 emitModDPR(),
10595 Push_Result_Mod_DPR(src),
10596 Pop_Reg_FPR(dst));
10597 ins_pipe( pipe_slow );
10598 %}
10599
10600 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10601 predicate(UseSSE>=1);
10602 match(Set dst (ModF src0 src1));
10603 effect(KILL rax, KILL cr);
10604 format %{ "SUB ESP,4\t # FMOD\n"
10605 "\tMOVSS [ESP+0],$src1\n"
10606 "\tFLD_S [ESP+0]\n"
10607 "\tMOVSS [ESP+0],$src0\n"
10608 "\tFLD_S [ESP+0]\n"
10609 "loop:\tFPREM\n"
10610 "\tFWAIT\n"
10611 "\tFNSTSW AX\n"
10612 "\tSAHF\n"
10613 "\tJP loop\n"
10614 "\tFSTP_S [ESP+0]\n"
10615 "\tMOVSS $dst,[ESP+0]\n"
10616 "\tADD ESP,4\n"
10617 "\tFSTP ST0\t # Restore FPU Stack"
10618 %}
10619 ins_cost(250);
10620 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10621 ins_pipe( pipe_slow );
10622 %}
10623
10624
10625 //----------Arithmetic Conversion Instructions---------------------------------
10626 // The conversions operations are all Alpha sorted. Please keep it that way!
10627
10628 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10629 predicate(UseSSE==0);
10630 match(Set dst (RoundFloat src));
10631 ins_cost(125);
10632 format %{ "FST_S $dst,$src\t# F-round" %}
10633 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10634 ins_pipe( fpu_mem_reg );
10635 %}
10636
10637 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10638 predicate(UseSSE<=1);
10639 match(Set dst (RoundDouble src));
10640 ins_cost(125);
10641 format %{ "FST_D $dst,$src\t# D-round" %}
10642 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10643 ins_pipe( fpu_mem_reg );
10644 %}
10645
10646 // Force rounding to 24-bit precision and 6-bit exponent
10647 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10648 predicate(UseSSE==0);
10649 match(Set dst (ConvD2F src));
10650 format %{ "FST_S $dst,$src\t# F-round" %}
10651 expand %{
10652 roundFloat_mem_reg(dst,src);
10653 %}
10654 %}
10655
10656 // Force rounding to 24-bit precision and 6-bit exponent
10657 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10658 predicate(UseSSE==1);
10659 match(Set dst (ConvD2F src));
10660 effect( KILL cr );
10661 format %{ "SUB ESP,4\n\t"
10662 "FST_S [ESP],$src\t# F-round\n\t"
10663 "MOVSS $dst,[ESP]\n\t"
10664 "ADD ESP,4" %}
10665 ins_encode %{
10666 __ subptr(rsp, 4);
10667 if ($src$$reg != FPR1L_enc) {
10668 __ fld_s($src$$reg-1);
10669 __ fstp_s(Address(rsp, 0));
10670 } else {
10671 __ fst_s(Address(rsp, 0));
10672 }
10673 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10674 __ addptr(rsp, 4);
10675 %}
10676 ins_pipe( pipe_slow );
10677 %}
10678
10679 // Force rounding double precision to single precision
10680 instruct convD2F_reg(regF dst, regD src) %{
10681 predicate(UseSSE>=2);
10682 match(Set dst (ConvD2F src));
10683 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10684 ins_encode %{
10685 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10686 %}
10687 ins_pipe( pipe_slow );
10688 %}
10689
10690 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10691 predicate(UseSSE==0);
10692 match(Set dst (ConvF2D src));
10693 format %{ "FST_S $dst,$src\t# D-round" %}
10694 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10695 ins_pipe( fpu_reg_reg );
10696 %}
10697
10698 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10699 predicate(UseSSE==1);
10700 match(Set dst (ConvF2D src));
10701 format %{ "FST_D $dst,$src\t# D-round" %}
10702 expand %{
10703 roundDouble_mem_reg(dst,src);
10704 %}
10705 %}
10706
10707 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10708 predicate(UseSSE==1);
10709 match(Set dst (ConvF2D src));
10710 effect( KILL cr );
10711 format %{ "SUB ESP,4\n\t"
10712 "MOVSS [ESP] $src\n\t"
10713 "FLD_S [ESP]\n\t"
10714 "ADD ESP,4\n\t"
10715 "FSTP $dst\t# D-round" %}
10716 ins_encode %{
10717 __ subptr(rsp, 4);
10718 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10719 __ fld_s(Address(rsp, 0));
10720 __ addptr(rsp, 4);
10721 __ fstp_d($dst$$reg);
10722 %}
10723 ins_pipe( pipe_slow );
10724 %}
10725
10726 instruct convF2D_reg(regD dst, regF src) %{
10727 predicate(UseSSE>=2);
10728 match(Set dst (ConvF2D src));
10729 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10730 ins_encode %{
10731 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10732 %}
10733 ins_pipe( pipe_slow );
10734 %}
10735
10736 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10737 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10738 predicate(UseSSE<=1);
10739 match(Set dst (ConvD2I src));
10740 effect( KILL tmp, KILL cr );
10741 format %{ "FLD $src\t# Convert double to int \n\t"
10742 "FLDCW trunc mode\n\t"
10743 "SUB ESP,4\n\t"
10744 "FISTp [ESP + #0]\n\t"
10745 "FLDCW std/24-bit mode\n\t"
10746 "POP EAX\n\t"
10747 "CMP EAX,0x80000000\n\t"
10748 "JNE,s fast\n\t"
10749 "FLD_D $src\n\t"
10750 "CALL d2i_wrapper\n"
10751 "fast:" %}
10752 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10753 ins_pipe( pipe_slow );
10754 %}
10755
10756 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10757 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10758 predicate(UseSSE>=2);
10759 match(Set dst (ConvD2I src));
10760 effect( KILL tmp, KILL cr );
10761 format %{ "CVTTSD2SI $dst, $src\n\t"
10762 "CMP $dst,0x80000000\n\t"
10763 "JNE,s fast\n\t"
10764 "SUB ESP, 8\n\t"
10765 "MOVSD [ESP], $src\n\t"
10766 "FLD_D [ESP]\n\t"
10767 "ADD ESP, 8\n\t"
10768 "CALL d2i_wrapper\n"
10769 "fast:" %}
10770 ins_encode %{
10771 Label fast;
10772 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10773 __ cmpl($dst$$Register, 0x80000000);
10774 __ jccb(Assembler::notEqual, fast);
10775 __ subptr(rsp, 8);
10776 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10777 __ fld_d(Address(rsp, 0));
10778 __ addptr(rsp, 8);
10779 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10780 __ bind(fast);
10781 %}
10782 ins_pipe( pipe_slow );
10783 %}
10784
10785 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10786 predicate(UseSSE<=1);
10787 match(Set dst (ConvD2L src));
10788 effect( KILL cr );
10789 format %{ "FLD $src\t# Convert double to long\n\t"
10790 "FLDCW trunc mode\n\t"
10791 "SUB ESP,8\n\t"
10792 "FISTp [ESP + #0]\n\t"
10793 "FLDCW std/24-bit mode\n\t"
10794 "POP EAX\n\t"
10795 "POP EDX\n\t"
10796 "CMP EDX,0x80000000\n\t"
10797 "JNE,s fast\n\t"
10798 "TEST EAX,EAX\n\t"
10799 "JNE,s fast\n\t"
10800 "FLD $src\n\t"
10801 "CALL d2l_wrapper\n"
10802 "fast:" %}
10803 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10804 ins_pipe( pipe_slow );
10805 %}
10806
10807 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10808 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10809 predicate (UseSSE>=2);
10810 match(Set dst (ConvD2L src));
10811 effect( KILL cr );
10812 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10813 "MOVSD [ESP],$src\n\t"
10814 "FLD_D [ESP]\n\t"
10815 "FLDCW trunc mode\n\t"
10816 "FISTp [ESP + #0]\n\t"
10817 "FLDCW std/24-bit mode\n\t"
10818 "POP EAX\n\t"
10819 "POP EDX\n\t"
10820 "CMP EDX,0x80000000\n\t"
10821 "JNE,s fast\n\t"
10822 "TEST EAX,EAX\n\t"
10823 "JNE,s fast\n\t"
10824 "SUB ESP,8\n\t"
10825 "MOVSD [ESP],$src\n\t"
10826 "FLD_D [ESP]\n\t"
10827 "ADD ESP,8\n\t"
10828 "CALL d2l_wrapper\n"
10829 "fast:" %}
10830 ins_encode %{
10831 Label fast;
10832 __ subptr(rsp, 8);
10833 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10834 __ fld_d(Address(rsp, 0));
10835 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10836 __ fistp_d(Address(rsp, 0));
10837 // Restore the rounding mode, mask the exception
10838 if (Compile::current()->in_24_bit_fp_mode()) {
10839 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10840 } else {
10841 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10842 }
10843 // Load the converted long, adjust CPU stack
10844 __ pop(rax);
10845 __ pop(rdx);
10846 __ cmpl(rdx, 0x80000000);
10847 __ jccb(Assembler::notEqual, fast);
10848 __ testl(rax, rax);
10849 __ jccb(Assembler::notEqual, fast);
10850 __ subptr(rsp, 8);
10851 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10852 __ fld_d(Address(rsp, 0));
10853 __ addptr(rsp, 8);
10854 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10855 __ bind(fast);
10856 %}
10857 ins_pipe( pipe_slow );
10858 %}
10859
10860 // Convert a double to an int. Java semantics require we do complex
10861 // manglations in the corner cases. So we set the rounding mode to
10862 // 'zero', store the darned double down as an int, and reset the
10863 // rounding mode to 'nearest'. The hardware stores a flag value down
10864 // if we would overflow or converted a NAN; we check for this and
10865 // and go the slow path if needed.
10866 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10867 predicate(UseSSE==0);
10868 match(Set dst (ConvF2I src));
10869 effect( KILL tmp, KILL cr );
10870 format %{ "FLD $src\t# Convert float to int \n\t"
10871 "FLDCW trunc mode\n\t"
10872 "SUB ESP,4\n\t"
10873 "FISTp [ESP + #0]\n\t"
10874 "FLDCW std/24-bit mode\n\t"
10875 "POP EAX\n\t"
10876 "CMP EAX,0x80000000\n\t"
10877 "JNE,s fast\n\t"
10878 "FLD $src\n\t"
10879 "CALL d2i_wrapper\n"
10880 "fast:" %}
10881 // DPR2I_encoding works for FPR2I
10882 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10883 ins_pipe( pipe_slow );
10884 %}
10885
10886 // Convert a float in xmm to an int reg.
10887 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10888 predicate(UseSSE>=1);
10889 match(Set dst (ConvF2I src));
10890 effect( KILL tmp, KILL cr );
10891 format %{ "CVTTSS2SI $dst, $src\n\t"
10892 "CMP $dst,0x80000000\n\t"
10893 "JNE,s fast\n\t"
10894 "SUB ESP, 4\n\t"
10895 "MOVSS [ESP], $src\n\t"
10896 "FLD [ESP]\n\t"
10897 "ADD ESP, 4\n\t"
10898 "CALL d2i_wrapper\n"
10899 "fast:" %}
10900 ins_encode %{
10901 Label fast;
10902 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10903 __ cmpl($dst$$Register, 0x80000000);
10904 __ jccb(Assembler::notEqual, fast);
10905 __ subptr(rsp, 4);
10906 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10907 __ fld_s(Address(rsp, 0));
10908 __ addptr(rsp, 4);
10909 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10910 __ bind(fast);
10911 %}
10912 ins_pipe( pipe_slow );
10913 %}
10914
10915 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10916 predicate(UseSSE==0);
10917 match(Set dst (ConvF2L src));
10918 effect( KILL cr );
10919 format %{ "FLD $src\t# Convert float to long\n\t"
10920 "FLDCW trunc mode\n\t"
10921 "SUB ESP,8\n\t"
10922 "FISTp [ESP + #0]\n\t"
10923 "FLDCW std/24-bit mode\n\t"
10924 "POP EAX\n\t"
10925 "POP EDX\n\t"
10926 "CMP EDX,0x80000000\n\t"
10927 "JNE,s fast\n\t"
10928 "TEST EAX,EAX\n\t"
10929 "JNE,s fast\n\t"
10930 "FLD $src\n\t"
10931 "CALL d2l_wrapper\n"
10932 "fast:" %}
10933 // DPR2L_encoding works for FPR2L
10934 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
10935 ins_pipe( pipe_slow );
10936 %}
10937
10938 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10939 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10940 predicate (UseSSE>=1);
10941 match(Set dst (ConvF2L src));
10942 effect( KILL cr );
10943 format %{ "SUB ESP,8\t# Convert float to long\n\t"
10944 "MOVSS [ESP],$src\n\t"
10945 "FLD_S [ESP]\n\t"
10946 "FLDCW trunc mode\n\t"
10947 "FISTp [ESP + #0]\n\t"
10948 "FLDCW std/24-bit mode\n\t"
10949 "POP EAX\n\t"
10950 "POP EDX\n\t"
10951 "CMP EDX,0x80000000\n\t"
10952 "JNE,s fast\n\t"
10953 "TEST EAX,EAX\n\t"
10954 "JNE,s fast\n\t"
10955 "SUB ESP,4\t# Convert float to long\n\t"
10956 "MOVSS [ESP],$src\n\t"
10957 "FLD_S [ESP]\n\t"
10958 "ADD ESP,4\n\t"
10959 "CALL d2l_wrapper\n"
10960 "fast:" %}
10961 ins_encode %{
10962 Label fast;
10963 __ subptr(rsp, 8);
10964 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10965 __ fld_s(Address(rsp, 0));
10966 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10967 __ fistp_d(Address(rsp, 0));
10968 // Restore the rounding mode, mask the exception
10969 if (Compile::current()->in_24_bit_fp_mode()) {
10970 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10971 } else {
10972 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10973 }
10974 // Load the converted long, adjust CPU stack
10975 __ pop(rax);
10976 __ pop(rdx);
10977 __ cmpl(rdx, 0x80000000);
10978 __ jccb(Assembler::notEqual, fast);
10979 __ testl(rax, rax);
10980 __ jccb(Assembler::notEqual, fast);
10981 __ subptr(rsp, 4);
10982 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10983 __ fld_s(Address(rsp, 0));
10984 __ addptr(rsp, 4);
10985 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10986 __ bind(fast);
10987 %}
10988 ins_pipe( pipe_slow );
10989 %}
10990
10991 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
10992 predicate( UseSSE<=1 );
10993 match(Set dst (ConvI2D src));
10994 format %{ "FILD $src\n\t"
10995 "FSTP $dst" %}
10996 opcode(0xDB, 0x0); /* DB /0 */
10997 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
10998 ins_pipe( fpu_reg_mem );
10999 %}
11000
11001 instruct convI2D_reg(regD dst, rRegI src) %{
11002 predicate( UseSSE>=2 && !UseXmmI2D );
11003 match(Set dst (ConvI2D src));
11004 format %{ "CVTSI2SD $dst,$src" %}
11005 ins_encode %{
11006 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11007 %}
11008 ins_pipe( pipe_slow );
11009 %}
11010
11011 instruct convI2D_mem(regD dst, memory mem) %{
11012 predicate( UseSSE>=2 );
11013 match(Set dst (ConvI2D (LoadI mem)));
11014 format %{ "CVTSI2SD $dst,$mem" %}
11015 ins_encode %{
11016 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11017 %}
11018 ins_pipe( pipe_slow );
11019 %}
11020
11021 instruct convXI2D_reg(regD dst, rRegI src)
11022 %{
11023 predicate( UseSSE>=2 && UseXmmI2D );
11024 match(Set dst (ConvI2D src));
11025
11026 format %{ "MOVD $dst,$src\n\t"
11027 "CVTDQ2PD $dst,$dst\t# i2d" %}
11028 ins_encode %{
11029 __ movdl($dst$$XMMRegister, $src$$Register);
11030 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11031 %}
11032 ins_pipe(pipe_slow); // XXX
11033 %}
11034
11035 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11036 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11037 match(Set dst (ConvI2D (LoadI mem)));
11038 format %{ "FILD $mem\n\t"
11039 "FSTP $dst" %}
11040 opcode(0xDB); /* DB /0 */
11041 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11042 Pop_Reg_DPR(dst));
11043 ins_pipe( fpu_reg_mem );
11044 %}
11045
11046 // Convert a byte to a float; no rounding step needed.
11047 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11048 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11049 match(Set dst (ConvI2F src));
11050 format %{ "FILD $src\n\t"
11051 "FSTP $dst" %}
11052
11053 opcode(0xDB, 0x0); /* DB /0 */
11054 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11055 ins_pipe( fpu_reg_mem );
11056 %}
11057
11058 // In 24-bit mode, force exponent rounding by storing back out
11059 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11060 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11061 match(Set dst (ConvI2F src));
11062 ins_cost(200);
11063 format %{ "FILD $src\n\t"
11064 "FSTP_S $dst" %}
11065 opcode(0xDB, 0x0); /* DB /0 */
11066 ins_encode( Push_Mem_I(src),
11067 Pop_Mem_FPR(dst));
11068 ins_pipe( fpu_mem_mem );
11069 %}
11070
11071 // In 24-bit mode, force exponent rounding by storing back out
11072 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11073 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11074 match(Set dst (ConvI2F (LoadI mem)));
11075 ins_cost(200);
11076 format %{ "FILD $mem\n\t"
11077 "FSTP_S $dst" %}
11078 opcode(0xDB); /* DB /0 */
11079 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11080 Pop_Mem_FPR(dst));
11081 ins_pipe( fpu_mem_mem );
11082 %}
11083
11084 // This instruction does not round to 24-bits
11085 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11086 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11087 match(Set dst (ConvI2F src));
11088 format %{ "FILD $src\n\t"
11089 "FSTP $dst" %}
11090 opcode(0xDB, 0x0); /* DB /0 */
11091 ins_encode( Push_Mem_I(src),
11092 Pop_Reg_FPR(dst));
11093 ins_pipe( fpu_reg_mem );
11094 %}
11095
11096 // This instruction does not round to 24-bits
11097 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11098 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11099 match(Set dst (ConvI2F (LoadI mem)));
11100 format %{ "FILD $mem\n\t"
11101 "FSTP $dst" %}
11102 opcode(0xDB); /* DB /0 */
11103 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11104 Pop_Reg_FPR(dst));
11105 ins_pipe( fpu_reg_mem );
11106 %}
11107
11108 // Convert an int to a float in xmm; no rounding step needed.
11109 instruct convI2F_reg(regF dst, rRegI src) %{
11110 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11111 match(Set dst (ConvI2F src));
11112 format %{ "CVTSI2SS $dst, $src" %}
11113 ins_encode %{
11114 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11115 %}
11116 ins_pipe( pipe_slow );
11117 %}
11118
11119 instruct convXI2F_reg(regF dst, rRegI src)
11120 %{
11121 predicate( UseSSE>=2 && UseXmmI2F );
11122 match(Set dst (ConvI2F src));
11123
11124 format %{ "MOVD $dst,$src\n\t"
11125 "CVTDQ2PS $dst,$dst\t# i2f" %}
11126 ins_encode %{
11127 __ movdl($dst$$XMMRegister, $src$$Register);
11128 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11129 %}
11130 ins_pipe(pipe_slow); // XXX
11131 %}
11132
11133 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11134 match(Set dst (ConvI2L src));
11135 effect(KILL cr);
11136 ins_cost(375);
11137 format %{ "MOV $dst.lo,$src\n\t"
11138 "MOV $dst.hi,$src\n\t"
11139 "SAR $dst.hi,31" %}
11140 ins_encode(convert_int_long(dst,src));
11141 ins_pipe( ialu_reg_reg_long );
11142 %}
11143
11144 // Zero-extend convert int to long
11145 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11146 match(Set dst (AndL (ConvI2L src) mask) );
11147 effect( KILL flags );
11148 ins_cost(250);
11149 format %{ "MOV $dst.lo,$src\n\t"
11150 "XOR $dst.hi,$dst.hi" %}
11151 opcode(0x33); // XOR
11152 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11153 ins_pipe( ialu_reg_reg_long );
11154 %}
11155
11156 // Zero-extend long
11157 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11158 match(Set dst (AndL src mask) );
11159 effect( KILL flags );
11160 ins_cost(250);
11161 format %{ "MOV $dst.lo,$src.lo\n\t"
11162 "XOR $dst.hi,$dst.hi\n\t" %}
11163 opcode(0x33); // XOR
11164 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11165 ins_pipe( ialu_reg_reg_long );
11166 %}
11167
11168 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11169 predicate (UseSSE<=1);
11170 match(Set dst (ConvL2D src));
11171 effect( KILL cr );
11172 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11173 "PUSH $src.lo\n\t"
11174 "FILD ST,[ESP + #0]\n\t"
11175 "ADD ESP,8\n\t"
11176 "FSTP_D $dst\t# D-round" %}
11177 opcode(0xDF, 0x5); /* DF /5 */
11178 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11179 ins_pipe( pipe_slow );
11180 %}
11181
11182 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11183 predicate (UseSSE>=2);
11184 match(Set dst (ConvL2D src));
11185 effect( KILL cr );
11186 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11187 "PUSH $src.lo\n\t"
11188 "FILD_D [ESP]\n\t"
11189 "FSTP_D [ESP]\n\t"
11190 "MOVSD $dst,[ESP]\n\t"
11191 "ADD ESP,8" %}
11192 opcode(0xDF, 0x5); /* DF /5 */
11193 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11194 ins_pipe( pipe_slow );
11195 %}
11196
11197 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11198 predicate (UseSSE>=1);
11199 match(Set dst (ConvL2F src));
11200 effect( KILL cr );
11201 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11202 "PUSH $src.lo\n\t"
11203 "FILD_D [ESP]\n\t"
11204 "FSTP_S [ESP]\n\t"
11205 "MOVSS $dst,[ESP]\n\t"
11206 "ADD ESP,8" %}
11207 opcode(0xDF, 0x5); /* DF /5 */
11208 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11209 ins_pipe( pipe_slow );
11210 %}
11211
11212 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11213 match(Set dst (ConvL2F src));
11214 effect( KILL cr );
11215 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11216 "PUSH $src.lo\n\t"
11217 "FILD ST,[ESP + #0]\n\t"
11218 "ADD ESP,8\n\t"
11219 "FSTP_S $dst\t# F-round" %}
11220 opcode(0xDF, 0x5); /* DF /5 */
11221 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11222 ins_pipe( pipe_slow );
11223 %}
11224
11225 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11226 match(Set dst (ConvL2I src));
11227 effect( DEF dst, USE src );
11228 format %{ "MOV $dst,$src.lo" %}
11229 ins_encode(enc_CopyL_Lo(dst,src));
11230 ins_pipe( ialu_reg_reg );
11231 %}
11232
11233
11234 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11235 match(Set dst (MoveF2I src));
11236 effect( DEF dst, USE src );
11237 ins_cost(100);
11238 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11239 ins_encode %{
11240 __ movl($dst$$Register, Address(rsp, $src$$disp));
11241 %}
11242 ins_pipe( ialu_reg_mem );
11243 %}
11244
11245 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11246 predicate(UseSSE==0);
11247 match(Set dst (MoveF2I src));
11248 effect( DEF dst, USE src );
11249
11250 ins_cost(125);
11251 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11252 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11253 ins_pipe( fpu_mem_reg );
11254 %}
11255
11256 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11257 predicate(UseSSE>=1);
11258 match(Set dst (MoveF2I src));
11259 effect( DEF dst, USE src );
11260
11261 ins_cost(95);
11262 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11263 ins_encode %{
11264 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11265 %}
11266 ins_pipe( pipe_slow );
11267 %}
11268
11269 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11270 predicate(UseSSE>=2);
11271 match(Set dst (MoveF2I src));
11272 effect( DEF dst, USE src );
11273 ins_cost(85);
11274 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11275 ins_encode %{
11276 __ movdl($dst$$Register, $src$$XMMRegister);
11277 %}
11278 ins_pipe( pipe_slow );
11279 %}
11280
11281 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11282 match(Set dst (MoveI2F src));
11283 effect( DEF dst, USE src );
11284
11285 ins_cost(100);
11286 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11287 ins_encode %{
11288 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11289 %}
11290 ins_pipe( ialu_mem_reg );
11291 %}
11292
11293
11294 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11295 predicate(UseSSE==0);
11296 match(Set dst (MoveI2F src));
11297 effect(DEF dst, USE src);
11298
11299 ins_cost(125);
11300 format %{ "FLD_S $src\n\t"
11301 "FSTP $dst\t# MoveI2F_stack_reg" %}
11302 opcode(0xD9); /* D9 /0, FLD m32real */
11303 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11304 Pop_Reg_FPR(dst) );
11305 ins_pipe( fpu_reg_mem );
11306 %}
11307
11308 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11309 predicate(UseSSE>=1);
11310 match(Set dst (MoveI2F src));
11311 effect( DEF dst, USE src );
11312
11313 ins_cost(95);
11314 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11315 ins_encode %{
11316 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11317 %}
11318 ins_pipe( pipe_slow );
11319 %}
11320
11321 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11322 predicate(UseSSE>=2);
11323 match(Set dst (MoveI2F src));
11324 effect( DEF dst, USE src );
11325
11326 ins_cost(85);
11327 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11328 ins_encode %{
11329 __ movdl($dst$$XMMRegister, $src$$Register);
11330 %}
11331 ins_pipe( pipe_slow );
11332 %}
11333
11334 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11335 match(Set dst (MoveD2L src));
11336 effect(DEF dst, USE src);
11337
11338 ins_cost(250);
11339 format %{ "MOV $dst.lo,$src\n\t"
11340 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11341 opcode(0x8B, 0x8B);
11342 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11343 ins_pipe( ialu_mem_long_reg );
11344 %}
11345
11346 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11347 predicate(UseSSE<=1);
11348 match(Set dst (MoveD2L src));
11349 effect(DEF dst, USE src);
11350
11351 ins_cost(125);
11352 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11353 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11354 ins_pipe( fpu_mem_reg );
11355 %}
11356
11357 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11358 predicate(UseSSE>=2);
11359 match(Set dst (MoveD2L src));
11360 effect(DEF dst, USE src);
11361 ins_cost(95);
11362 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11363 ins_encode %{
11364 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11365 %}
11366 ins_pipe( pipe_slow );
11367 %}
11368
11369 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11370 predicate(UseSSE>=2);
11371 match(Set dst (MoveD2L src));
11372 effect(DEF dst, USE src, TEMP tmp);
11373 ins_cost(85);
11374 format %{ "MOVD $dst.lo,$src\n\t"
11375 "PSHUFLW $tmp,$src,0x4E\n\t"
11376 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11377 ins_encode %{
11378 __ movdl($dst$$Register, $src$$XMMRegister);
11379 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11380 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11381 %}
11382 ins_pipe( pipe_slow );
11383 %}
11384
11385 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11386 match(Set dst (MoveL2D src));
11387 effect(DEF dst, USE src);
11388
11389 ins_cost(200);
11390 format %{ "MOV $dst,$src.lo\n\t"
11391 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11392 opcode(0x89, 0x89);
11393 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11394 ins_pipe( ialu_mem_long_reg );
11395 %}
11396
11397
11398 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11399 predicate(UseSSE<=1);
11400 match(Set dst (MoveL2D src));
11401 effect(DEF dst, USE src);
11402 ins_cost(125);
11403
11404 format %{ "FLD_D $src\n\t"
11405 "FSTP $dst\t# MoveL2D_stack_reg" %}
11406 opcode(0xDD); /* DD /0, FLD m64real */
11407 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11408 Pop_Reg_DPR(dst) );
11409 ins_pipe( fpu_reg_mem );
11410 %}
11411
11412
11413 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11414 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11415 match(Set dst (MoveL2D src));
11416 effect(DEF dst, USE src);
11417
11418 ins_cost(95);
11419 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11420 ins_encode %{
11421 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11422 %}
11423 ins_pipe( pipe_slow );
11424 %}
11425
11426 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11427 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11428 match(Set dst (MoveL2D src));
11429 effect(DEF dst, USE src);
11430
11431 ins_cost(95);
11432 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11433 ins_encode %{
11434 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11435 %}
11436 ins_pipe( pipe_slow );
11437 %}
11438
11439 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11440 predicate(UseSSE>=2);
11441 match(Set dst (MoveL2D src));
11442 effect(TEMP dst, USE src, TEMP tmp);
11443 ins_cost(85);
11444 format %{ "MOVD $dst,$src.lo\n\t"
11445 "MOVD $tmp,$src.hi\n\t"
11446 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11447 ins_encode %{
11448 __ movdl($dst$$XMMRegister, $src$$Register);
11449 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11450 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11451 %}
11452 ins_pipe( pipe_slow );
11453 %}
11454
11455
11456 // =======================================================================
11457 // fast clearing of an array
11458 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11459 predicate(!UseFastStosb);
11460 match(Set dummy (ClearArray cnt base));
11461 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11462 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11463 "SHL ECX,1\t# Convert doublewords to words\n\t"
11464 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11465 ins_encode %{
11466 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11467 %}
11468 ins_pipe( pipe_slow );
11469 %}
11470
11471 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11472 predicate(UseFastStosb);
11473 match(Set dummy (ClearArray cnt base));
11474 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11475 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11476 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11477 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11478 ins_encode %{
11479 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11480 %}
11481 ins_pipe( pipe_slow );
11482 %}
11483
11484 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11485 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11486 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11487 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11488
11489 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11490 ins_encode %{
11491 __ string_compare($str1$$Register, $str2$$Register,
11492 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11493 $tmp1$$XMMRegister);
11494 %}
11495 ins_pipe( pipe_slow );
11496 %}
11497
11498 // fast string equals
11499 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11500 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11501 match(Set result (StrEquals (Binary str1 str2) cnt));
11502 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11503
11504 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11505 ins_encode %{
11506 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11507 $cnt$$Register, $result$$Register, $tmp3$$Register,
11508 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11509 %}
11510 ins_pipe( pipe_slow );
11511 %}
11512
11513 // fast search of substring with known size.
11514 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11515 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11516 predicate(UseSSE42Intrinsics);
11517 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11518 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11519
11520 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11521 ins_encode %{
11522 int icnt2 = (int)$int_cnt2$$constant;
11523 if (icnt2 >= 8) {
11524 // IndexOf for constant substrings with size >= 8 elements
11525 // which don't need to be loaded through stack.
11526 __ string_indexofC8($str1$$Register, $str2$$Register,
11527 $cnt1$$Register, $cnt2$$Register,
11528 icnt2, $result$$Register,
11529 $vec$$XMMRegister, $tmp$$Register);
11530 } else {
11531 // Small strings are loaded through stack if they cross page boundary.
11532 __ string_indexof($str1$$Register, $str2$$Register,
11533 $cnt1$$Register, $cnt2$$Register,
11534 icnt2, $result$$Register,
11535 $vec$$XMMRegister, $tmp$$Register);
11536 }
11537 %}
11538 ins_pipe( pipe_slow );
11539 %}
11540
11541 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11542 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11543 predicate(UseSSE42Intrinsics);
11544 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11545 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11546
11547 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11548 ins_encode %{
11549 __ string_indexof($str1$$Register, $str2$$Register,
11550 $cnt1$$Register, $cnt2$$Register,
11551 (-1), $result$$Register,
11552 $vec$$XMMRegister, $tmp$$Register);
11553 %}
11554 ins_pipe( pipe_slow );
11555 %}
11556
11557 // fast array equals
11558 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11559 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11560 %{
11561 match(Set result (AryEq ary1 ary2));
11562 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11563 //ins_cost(300);
11564
11565 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11566 ins_encode %{
11567 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11568 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11569 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11570 %}
11571 ins_pipe( pipe_slow );
11572 %}
11573
11574 // encode char[] to byte[] in ISO_8859_1
11575 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11576 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11577 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11578 match(Set result (EncodeISOArray src (Binary dst len)));
11579 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11580
11581 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11582 ins_encode %{
11583 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11584 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11585 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11586 %}
11587 ins_pipe( pipe_slow );
11588 %}
11589
11590
11591 //----------Control Flow Instructions------------------------------------------
11592 // Signed compare Instructions
11593 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11594 match(Set cr (CmpI op1 op2));
11595 effect( DEF cr, USE op1, USE op2 );
11596 format %{ "CMP $op1,$op2" %}
11597 opcode(0x3B); /* Opcode 3B /r */
11598 ins_encode( OpcP, RegReg( op1, op2) );
11599 ins_pipe( ialu_cr_reg_reg );
11600 %}
11601
11602 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11603 match(Set cr (CmpI op1 op2));
11604 effect( DEF cr, USE op1 );
11605 format %{ "CMP $op1,$op2" %}
11606 opcode(0x81,0x07); /* Opcode 81 /7 */
11607 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11608 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11609 ins_pipe( ialu_cr_reg_imm );
11610 %}
11611
11612 // Cisc-spilled version of cmpI_eReg
11613 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11614 match(Set cr (CmpI op1 (LoadI op2)));
11615
11616 format %{ "CMP $op1,$op2" %}
11617 ins_cost(500);
11618 opcode(0x3B); /* Opcode 3B /r */
11619 ins_encode( OpcP, RegMem( op1, op2) );
11620 ins_pipe( ialu_cr_reg_mem );
11621 %}
11622
11623 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11624 match(Set cr (CmpI src zero));
11625 effect( DEF cr, USE src );
11626
11627 format %{ "TEST $src,$src" %}
11628 opcode(0x85);
11629 ins_encode( OpcP, RegReg( src, src ) );
11630 ins_pipe( ialu_cr_reg_imm );
11631 %}
11632
11633 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11634 match(Set cr (CmpI (AndI src con) zero));
11635
11636 format %{ "TEST $src,$con" %}
11637 opcode(0xF7,0x00);
11638 ins_encode( OpcP, RegOpc(src), Con32(con) );
11639 ins_pipe( ialu_cr_reg_imm );
11640 %}
11641
11642 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11643 match(Set cr (CmpI (AndI src mem) zero));
11644
11645 format %{ "TEST $src,$mem" %}
11646 opcode(0x85);
11647 ins_encode( OpcP, RegMem( src, mem ) );
11648 ins_pipe( ialu_cr_reg_mem );
11649 %}
11650
11651 // Unsigned compare Instructions; really, same as signed except they
11652 // produce an eFlagsRegU instead of eFlagsReg.
11653 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11654 match(Set cr (CmpU op1 op2));
11655
11656 format %{ "CMPu $op1,$op2" %}
11657 opcode(0x3B); /* Opcode 3B /r */
11658 ins_encode( OpcP, RegReg( op1, op2) );
11659 ins_pipe( ialu_cr_reg_reg );
11660 %}
11661
11662 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11663 match(Set cr (CmpU op1 op2));
11664
11665 format %{ "CMPu $op1,$op2" %}
11666 opcode(0x81,0x07); /* Opcode 81 /7 */
11667 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11668 ins_pipe( ialu_cr_reg_imm );
11669 %}
11670
11671 // // Cisc-spilled version of cmpU_eReg
11672 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11673 match(Set cr (CmpU op1 (LoadI op2)));
11674
11675 format %{ "CMPu $op1,$op2" %}
11676 ins_cost(500);
11677 opcode(0x3B); /* Opcode 3B /r */
11678 ins_encode( OpcP, RegMem( op1, op2) );
11679 ins_pipe( ialu_cr_reg_mem );
11680 %}
11681
11682 // // Cisc-spilled version of cmpU_eReg
11683 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11684 // match(Set cr (CmpU (LoadI op1) op2));
11685 //
11686 // format %{ "CMPu $op1,$op2" %}
11687 // ins_cost(500);
11688 // opcode(0x39); /* Opcode 39 /r */
11689 // ins_encode( OpcP, RegMem( op1, op2) );
11690 //%}
11691
11692 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11693 match(Set cr (CmpU src zero));
11694
11695 format %{ "TESTu $src,$src" %}
11696 opcode(0x85);
11697 ins_encode( OpcP, RegReg( src, src ) );
11698 ins_pipe( ialu_cr_reg_imm );
11699 %}
11700
11701 // Unsigned pointer compare Instructions
11702 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11703 match(Set cr (CmpP op1 op2));
11704
11705 format %{ "CMPu $op1,$op2" %}
11706 opcode(0x3B); /* Opcode 3B /r */
11707 ins_encode( OpcP, RegReg( op1, op2) );
11708 ins_pipe( ialu_cr_reg_reg );
11709 %}
11710
11711 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11712 match(Set cr (CmpP op1 op2));
11713
11714 format %{ "CMPu $op1,$op2" %}
11715 opcode(0x81,0x07); /* Opcode 81 /7 */
11716 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11717 ins_pipe( ialu_cr_reg_imm );
11718 %}
11719
11720 // // Cisc-spilled version of cmpP_eReg
11721 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11722 match(Set cr (CmpP op1 (LoadP op2)));
11723
11724 format %{ "CMPu $op1,$op2" %}
11725 ins_cost(500);
11726 opcode(0x3B); /* Opcode 3B /r */
11727 ins_encode( OpcP, RegMem( op1, op2) );
11728 ins_pipe( ialu_cr_reg_mem );
11729 %}
11730
11731 // // Cisc-spilled version of cmpP_eReg
11732 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11733 // match(Set cr (CmpP (LoadP op1) op2));
11734 //
11735 // format %{ "CMPu $op1,$op2" %}
11736 // ins_cost(500);
11737 // opcode(0x39); /* Opcode 39 /r */
11738 // ins_encode( OpcP, RegMem( op1, op2) );
11739 //%}
11740
11741 // Compare raw pointer (used in out-of-heap check).
11742 // Only works because non-oop pointers must be raw pointers
11743 // and raw pointers have no anti-dependencies.
11744 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11745 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11746 match(Set cr (CmpP op1 (LoadP op2)));
11747
11748 format %{ "CMPu $op1,$op2" %}
11749 opcode(0x3B); /* Opcode 3B /r */
11750 ins_encode( OpcP, RegMem( op1, op2) );
11751 ins_pipe( ialu_cr_reg_mem );
11752 %}
11753
11754 //
11755 // This will generate a signed flags result. This should be ok
11756 // since any compare to a zero should be eq/neq.
11757 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11758 match(Set cr (CmpP src zero));
11759
11760 format %{ "TEST $src,$src" %}
11761 opcode(0x85);
11762 ins_encode( OpcP, RegReg( src, src ) );
11763 ins_pipe( ialu_cr_reg_imm );
11764 %}
11765
11766 // Cisc-spilled version of testP_reg
11767 // This will generate a signed flags result. This should be ok
11768 // since any compare to a zero should be eq/neq.
11769 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11770 match(Set cr (CmpP (LoadP op) zero));
11771
11772 format %{ "TEST $op,0xFFFFFFFF" %}
11773 ins_cost(500);
11774 opcode(0xF7); /* Opcode F7 /0 */
11775 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11776 ins_pipe( ialu_cr_reg_imm );
11777 %}
11778
11779 // Yanked all unsigned pointer compare operations.
11780 // Pointer compares are done with CmpP which is already unsigned.
11781
11782 //----------Max and Min--------------------------------------------------------
11783 // Min Instructions
11784 ////
11785 // *** Min and Max using the conditional move are slower than the
11786 // *** branch version on a Pentium III.
11787 // // Conditional move for min
11788 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11789 // effect( USE_DEF op2, USE op1, USE cr );
11790 // format %{ "CMOVlt $op2,$op1\t! min" %}
11791 // opcode(0x4C,0x0F);
11792 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11793 // ins_pipe( pipe_cmov_reg );
11794 //%}
11795 //
11796 //// Min Register with Register (P6 version)
11797 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11798 // predicate(VM_Version::supports_cmov() );
11799 // match(Set op2 (MinI op1 op2));
11800 // ins_cost(200);
11801 // expand %{
11802 // eFlagsReg cr;
11803 // compI_eReg(cr,op1,op2);
11804 // cmovI_reg_lt(op2,op1,cr);
11805 // %}
11806 //%}
11807
11808 // Min Register with Register (generic version)
11809 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11810 match(Set dst (MinI dst src));
11811 effect(KILL flags);
11812 ins_cost(300);
11813
11814 format %{ "MIN $dst,$src" %}
11815 opcode(0xCC);
11816 ins_encode( min_enc(dst,src) );
11817 ins_pipe( pipe_slow );
11818 %}
11819
11820 // Max Register with Register
11821 // *** Min and Max using the conditional move are slower than the
11822 // *** branch version on a Pentium III.
11823 // // Conditional move for max
11824 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11825 // effect( USE_DEF op2, USE op1, USE cr );
11826 // format %{ "CMOVgt $op2,$op1\t! max" %}
11827 // opcode(0x4F,0x0F);
11828 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11829 // ins_pipe( pipe_cmov_reg );
11830 //%}
11831 //
11832 // // Max Register with Register (P6 version)
11833 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11834 // predicate(VM_Version::supports_cmov() );
11835 // match(Set op2 (MaxI op1 op2));
11836 // ins_cost(200);
11837 // expand %{
11838 // eFlagsReg cr;
11839 // compI_eReg(cr,op1,op2);
11840 // cmovI_reg_gt(op2,op1,cr);
11841 // %}
11842 //%}
11843
11844 // Max Register with Register (generic version)
11845 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11846 match(Set dst (MaxI dst src));
11847 effect(KILL flags);
11848 ins_cost(300);
11849
11850 format %{ "MAX $dst,$src" %}
11851 opcode(0xCC);
11852 ins_encode( max_enc(dst,src) );
11853 ins_pipe( pipe_slow );
11854 %}
11855
11856 // ============================================================================
11857 // Counted Loop limit node which represents exact final iterator value.
11858 // Note: the resulting value should fit into integer range since
11859 // counted loops have limit check on overflow.
11860 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11861 match(Set limit (LoopLimit (Binary init limit) stride));
11862 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11863 ins_cost(300);
11864
11865 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11866 ins_encode %{
11867 int strd = (int)$stride$$constant;
11868 assert(strd != 1 && strd != -1, "sanity");
11869 int m1 = (strd > 0) ? 1 : -1;
11870 // Convert limit to long (EAX:EDX)
11871 __ cdql();
11872 // Convert init to long (init:tmp)
11873 __ movl($tmp$$Register, $init$$Register);
11874 __ sarl($tmp$$Register, 31);
11875 // $limit - $init
11876 __ subl($limit$$Register, $init$$Register);
11877 __ sbbl($limit_hi$$Register, $tmp$$Register);
11878 // + ($stride - 1)
11879 if (strd > 0) {
11880 __ addl($limit$$Register, (strd - 1));
11881 __ adcl($limit_hi$$Register, 0);
11882 __ movl($tmp$$Register, strd);
11883 } else {
11884 __ addl($limit$$Register, (strd + 1));
11885 __ adcl($limit_hi$$Register, -1);
11886 __ lneg($limit_hi$$Register, $limit$$Register);
11887 __ movl($tmp$$Register, -strd);
11888 }
11889 // signed devision: (EAX:EDX) / pos_stride
11890 __ idivl($tmp$$Register);
11891 if (strd < 0) {
11892 // restore sign
11893 __ negl($tmp$$Register);
11894 }
11895 // (EAX) * stride
11896 __ mull($tmp$$Register);
11897 // + init (ignore upper bits)
11898 __ addl($limit$$Register, $init$$Register);
11899 %}
11900 ins_pipe( pipe_slow );
11901 %}
11902
11903 // ============================================================================
11904 // Branch Instructions
11905 // Jump Table
11906 instruct jumpXtnd(rRegI switch_val) %{
11907 match(Jump switch_val);
11908 ins_cost(350);
11909 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11910 ins_encode %{
11911 // Jump to Address(table_base + switch_reg)
11912 Address index(noreg, $switch_val$$Register, Address::times_1);
11913 __ jump(ArrayAddress($constantaddress, index));
11914 %}
11915 ins_pipe(pipe_jmp);
11916 %}
11917
11918 // Jump Direct - Label defines a relative address from JMP+1
11919 instruct jmpDir(label labl) %{
11920 match(Goto);
11921 effect(USE labl);
11922
11923 ins_cost(300);
11924 format %{ "JMP $labl" %}
11925 size(5);
11926 ins_encode %{
11927 Label* L = $labl$$label;
11928 __ jmp(*L, false); // Always long jump
11929 %}
11930 ins_pipe( pipe_jmp );
11931 %}
11932
11933 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11934 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11935 match(If cop cr);
11936 effect(USE labl);
11937
11938 ins_cost(300);
11939 format %{ "J$cop $labl" %}
11940 size(6);
11941 ins_encode %{
11942 Label* L = $labl$$label;
11943 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11944 %}
11945 ins_pipe( pipe_jcc );
11946 %}
11947
11948 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11949 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
11950 match(CountedLoopEnd cop cr);
11951 effect(USE labl);
11952
11953 ins_cost(300);
11954 format %{ "J$cop $labl\t# Loop end" %}
11955 size(6);
11956 ins_encode %{
11957 Label* L = $labl$$label;
11958 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11959 %}
11960 ins_pipe( pipe_jcc );
11961 %}
11962
11963 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11964 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11965 match(CountedLoopEnd cop cmp);
11966 effect(USE labl);
11967
11968 ins_cost(300);
11969 format %{ "J$cop,u $labl\t# Loop end" %}
11970 size(6);
11971 ins_encode %{
11972 Label* L = $labl$$label;
11973 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11974 %}
11975 ins_pipe( pipe_jcc );
11976 %}
11977
11978 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11979 match(CountedLoopEnd cop cmp);
11980 effect(USE labl);
11981
11982 ins_cost(200);
11983 format %{ "J$cop,u $labl\t# Loop end" %}
11984 size(6);
11985 ins_encode %{
11986 Label* L = $labl$$label;
11987 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11988 %}
11989 ins_pipe( pipe_jcc );
11990 %}
11991
11992 // Jump Direct Conditional - using unsigned comparison
11993 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11994 match(If cop cmp);
11995 effect(USE labl);
11996
11997 ins_cost(300);
11998 format %{ "J$cop,u $labl" %}
11999 size(6);
12000 ins_encode %{
12001 Label* L = $labl$$label;
12002 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12003 %}
12004 ins_pipe(pipe_jcc);
12005 %}
12006
12007 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12008 match(If cop cmp);
12009 effect(USE labl);
12010
12011 ins_cost(200);
12012 format %{ "J$cop,u $labl" %}
12013 size(6);
12014 ins_encode %{
12015 Label* L = $labl$$label;
12016 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12017 %}
12018 ins_pipe(pipe_jcc);
12019 %}
12020
12021 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12022 match(If cop cmp);
12023 effect(USE labl);
12024
12025 ins_cost(200);
12026 format %{ $$template
12027 if ($cop$$cmpcode == Assembler::notEqual) {
12028 $$emit$$"JP,u $labl\n\t"
12029 $$emit$$"J$cop,u $labl"
12030 } else {
12031 $$emit$$"JP,u done\n\t"
12032 $$emit$$"J$cop,u $labl\n\t"
12033 $$emit$$"done:"
12034 }
12035 %}
12036 ins_encode %{
12037 Label* l = $labl$$label;
12038 if ($cop$$cmpcode == Assembler::notEqual) {
12039 __ jcc(Assembler::parity, *l, false);
12040 __ jcc(Assembler::notEqual, *l, false);
12041 } else if ($cop$$cmpcode == Assembler::equal) {
12042 Label done;
12043 __ jccb(Assembler::parity, done);
12044 __ jcc(Assembler::equal, *l, false);
12045 __ bind(done);
12046 } else {
12047 ShouldNotReachHere();
12048 }
12049 %}
12050 ins_pipe(pipe_jcc);
12051 %}
12052
12053 // ============================================================================
12054 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12055 // array for an instance of the superklass. Set a hidden internal cache on a
12056 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12057 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12058 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12059 match(Set result (PartialSubtypeCheck sub super));
12060 effect( KILL rcx, KILL cr );
12061
12062 ins_cost(1100); // slightly larger than the next version
12063 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12064 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12065 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12066 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12067 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12068 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12069 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12070 "miss:\t" %}
12071
12072 opcode(0x1); // Force a XOR of EDI
12073 ins_encode( enc_PartialSubtypeCheck() );
12074 ins_pipe( pipe_slow );
12075 %}
12076
12077 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12078 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12079 effect( KILL rcx, KILL result );
12080
12081 ins_cost(1000);
12082 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12083 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12084 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12085 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12086 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12087 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12088 "miss:\t" %}
12089
12090 opcode(0x0); // No need to XOR EDI
12091 ins_encode( enc_PartialSubtypeCheck() );
12092 ins_pipe( pipe_slow );
12093 %}
12094
12095 // ============================================================================
12096 // Branch Instructions -- short offset versions
12097 //
12098 // These instructions are used to replace jumps of a long offset (the default
12099 // match) with jumps of a shorter offset. These instructions are all tagged
12100 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12101 // match rules in general matching. Instead, the ADLC generates a conversion
12102 // method in the MachNode which can be used to do in-place replacement of the
12103 // long variant with the shorter variant. The compiler will determine if a
12104 // branch can be taken by the is_short_branch_offset() predicate in the machine
12105 // specific code section of the file.
12106
12107 // Jump Direct - Label defines a relative address from JMP+1
12108 instruct jmpDir_short(label labl) %{
12109 match(Goto);
12110 effect(USE labl);
12111
12112 ins_cost(300);
12113 format %{ "JMP,s $labl" %}
12114 size(2);
12115 ins_encode %{
12116 Label* L = $labl$$label;
12117 __ jmpb(*L);
12118 %}
12119 ins_pipe( pipe_jmp );
12120 ins_short_branch(1);
12121 %}
12122
12123 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12124 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12125 match(If cop cr);
12126 effect(USE labl);
12127
12128 ins_cost(300);
12129 format %{ "J$cop,s $labl" %}
12130 size(2);
12131 ins_encode %{
12132 Label* L = $labl$$label;
12133 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12134 %}
12135 ins_pipe( pipe_jcc );
12136 ins_short_branch(1);
12137 %}
12138
12139 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12140 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12141 match(CountedLoopEnd cop cr);
12142 effect(USE labl);
12143
12144 ins_cost(300);
12145 format %{ "J$cop,s $labl\t# Loop end" %}
12146 size(2);
12147 ins_encode %{
12148 Label* L = $labl$$label;
12149 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12150 %}
12151 ins_pipe( pipe_jcc );
12152 ins_short_branch(1);
12153 %}
12154
12155 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12156 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12157 match(CountedLoopEnd cop cmp);
12158 effect(USE labl);
12159
12160 ins_cost(300);
12161 format %{ "J$cop,us $labl\t# Loop end" %}
12162 size(2);
12163 ins_encode %{
12164 Label* L = $labl$$label;
12165 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12166 %}
12167 ins_pipe( pipe_jcc );
12168 ins_short_branch(1);
12169 %}
12170
12171 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12172 match(CountedLoopEnd cop cmp);
12173 effect(USE labl);
12174
12175 ins_cost(300);
12176 format %{ "J$cop,us $labl\t# Loop end" %}
12177 size(2);
12178 ins_encode %{
12179 Label* L = $labl$$label;
12180 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12181 %}
12182 ins_pipe( pipe_jcc );
12183 ins_short_branch(1);
12184 %}
12185
12186 // Jump Direct Conditional - using unsigned comparison
12187 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12188 match(If cop cmp);
12189 effect(USE labl);
12190
12191 ins_cost(300);
12192 format %{ "J$cop,us $labl" %}
12193 size(2);
12194 ins_encode %{
12195 Label* L = $labl$$label;
12196 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12197 %}
12198 ins_pipe( pipe_jcc );
12199 ins_short_branch(1);
12200 %}
12201
12202 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12203 match(If cop cmp);
12204 effect(USE labl);
12205
12206 ins_cost(300);
12207 format %{ "J$cop,us $labl" %}
12208 size(2);
12209 ins_encode %{
12210 Label* L = $labl$$label;
12211 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12212 %}
12213 ins_pipe( pipe_jcc );
12214 ins_short_branch(1);
12215 %}
12216
12217 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12218 match(If cop cmp);
12219 effect(USE labl);
12220
12221 ins_cost(300);
12222 format %{ $$template
12223 if ($cop$$cmpcode == Assembler::notEqual) {
12224 $$emit$$"JP,u,s $labl\n\t"
12225 $$emit$$"J$cop,u,s $labl"
12226 } else {
12227 $$emit$$"JP,u,s done\n\t"
12228 $$emit$$"J$cop,u,s $labl\n\t"
12229 $$emit$$"done:"
12230 }
12231 %}
12232 size(4);
12233 ins_encode %{
12234 Label* l = $labl$$label;
12235 if ($cop$$cmpcode == Assembler::notEqual) {
12236 __ jccb(Assembler::parity, *l);
12237 __ jccb(Assembler::notEqual, *l);
12238 } else if ($cop$$cmpcode == Assembler::equal) {
12239 Label done;
12240 __ jccb(Assembler::parity, done);
12241 __ jccb(Assembler::equal, *l);
12242 __ bind(done);
12243 } else {
12244 ShouldNotReachHere();
12245 }
12246 %}
12247 ins_pipe(pipe_jcc);
12248 ins_short_branch(1);
12249 %}
12250
12251 // ============================================================================
12252 // Long Compare
12253 //
12254 // Currently we hold longs in 2 registers. Comparing such values efficiently
12255 // is tricky. The flavor of compare used depends on whether we are testing
12256 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12257 // The GE test is the negated LT test. The LE test can be had by commuting
12258 // the operands (yielding a GE test) and then negating; negate again for the
12259 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12260 // NE test is negated from that.
12261
12262 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12263 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12264 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12265 // are collapsed internally in the ADLC's dfa-gen code. The match for
12266 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12267 // foo match ends up with the wrong leaf. One fix is to not match both
12268 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12269 // both forms beat the trinary form of long-compare and both are very useful
12270 // on Intel which has so few registers.
12271
12272 // Manifest a CmpL result in an integer register. Very painful.
12273 // This is the test to avoid.
12274 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12275 match(Set dst (CmpL3 src1 src2));
12276 effect( KILL flags );
12277 ins_cost(1000);
12278 format %{ "XOR $dst,$dst\n\t"
12279 "CMP $src1.hi,$src2.hi\n\t"
12280 "JLT,s m_one\n\t"
12281 "JGT,s p_one\n\t"
12282 "CMP $src1.lo,$src2.lo\n\t"
12283 "JB,s m_one\n\t"
12284 "JEQ,s done\n"
12285 "p_one:\tINC $dst\n\t"
12286 "JMP,s done\n"
12287 "m_one:\tDEC $dst\n"
12288 "done:" %}
12289 ins_encode %{
12290 Label p_one, m_one, done;
12291 __ xorptr($dst$$Register, $dst$$Register);
12292 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12293 __ jccb(Assembler::less, m_one);
12294 __ jccb(Assembler::greater, p_one);
12295 __ cmpl($src1$$Register, $src2$$Register);
12296 __ jccb(Assembler::below, m_one);
12297 __ jccb(Assembler::equal, done);
12298 __ bind(p_one);
12299 __ incrementl($dst$$Register);
12300 __ jmpb(done);
12301 __ bind(m_one);
12302 __ decrementl($dst$$Register);
12303 __ bind(done);
12304 %}
12305 ins_pipe( pipe_slow );
12306 %}
12307
12308 //======
12309 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12310 // compares. Can be used for LE or GT compares by reversing arguments.
12311 // NOT GOOD FOR EQ/NE tests.
12312 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12313 match( Set flags (CmpL src zero ));
12314 ins_cost(100);
12315 format %{ "TEST $src.hi,$src.hi" %}
12316 opcode(0x85);
12317 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12318 ins_pipe( ialu_cr_reg_reg );
12319 %}
12320
12321 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12322 // compares. Can be used for LE or GT compares by reversing arguments.
12323 // NOT GOOD FOR EQ/NE tests.
12324 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12325 match( Set flags (CmpL src1 src2 ));
12326 effect( TEMP tmp );
12327 ins_cost(300);
12328 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12329 "MOV $tmp,$src1.hi\n\t"
12330 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12331 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12332 ins_pipe( ialu_cr_reg_reg );
12333 %}
12334
12335 // Long compares reg < zero/req OR reg >= zero/req.
12336 // Just a wrapper for a normal branch, plus the predicate test.
12337 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12338 match(If cmp flags);
12339 effect(USE labl);
12340 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12341 expand %{
12342 jmpCon(cmp,flags,labl); // JLT or JGE...
12343 %}
12344 %}
12345
12346 // Compare 2 longs and CMOVE longs.
12347 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12348 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12349 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12350 ins_cost(400);
12351 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12352 "CMOV$cmp $dst.hi,$src.hi" %}
12353 opcode(0x0F,0x40);
12354 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12355 ins_pipe( pipe_cmov_reg_long );
12356 %}
12357
12358 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12359 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12360 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12361 ins_cost(500);
12362 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12363 "CMOV$cmp $dst.hi,$src.hi" %}
12364 opcode(0x0F,0x40);
12365 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12366 ins_pipe( pipe_cmov_reg_long );
12367 %}
12368
12369 // Compare 2 longs and CMOVE ints.
12370 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12371 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12372 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12373 ins_cost(200);
12374 format %{ "CMOV$cmp $dst,$src" %}
12375 opcode(0x0F,0x40);
12376 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12377 ins_pipe( pipe_cmov_reg );
12378 %}
12379
12380 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12381 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12382 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12383 ins_cost(250);
12384 format %{ "CMOV$cmp $dst,$src" %}
12385 opcode(0x0F,0x40);
12386 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12387 ins_pipe( pipe_cmov_mem );
12388 %}
12389
12390 // Compare 2 longs and CMOVE ints.
12391 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12392 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12393 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12394 ins_cost(200);
12395 format %{ "CMOV$cmp $dst,$src" %}
12396 opcode(0x0F,0x40);
12397 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12398 ins_pipe( pipe_cmov_reg );
12399 %}
12400
12401 // Compare 2 longs and CMOVE doubles
12402 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12403 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12404 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12405 ins_cost(200);
12406 expand %{
12407 fcmovDPR_regS(cmp,flags,dst,src);
12408 %}
12409 %}
12410
12411 // Compare 2 longs and CMOVE doubles
12412 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12413 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12414 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12415 ins_cost(200);
12416 expand %{
12417 fcmovD_regS(cmp,flags,dst,src);
12418 %}
12419 %}
12420
12421 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12422 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12423 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12424 ins_cost(200);
12425 expand %{
12426 fcmovFPR_regS(cmp,flags,dst,src);
12427 %}
12428 %}
12429
12430 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12431 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12432 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12433 ins_cost(200);
12434 expand %{
12435 fcmovF_regS(cmp,flags,dst,src);
12436 %}
12437 %}
12438
12439 //======
12440 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12441 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12442 match( Set flags (CmpL src zero ));
12443 effect(TEMP tmp);
12444 ins_cost(200);
12445 format %{ "MOV $tmp,$src.lo\n\t"
12446 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12447 ins_encode( long_cmp_flags0( src, tmp ) );
12448 ins_pipe( ialu_reg_reg_long );
12449 %}
12450
12451 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12452 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12453 match( Set flags (CmpL src1 src2 ));
12454 ins_cost(200+300);
12455 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12456 "JNE,s skip\n\t"
12457 "CMP $src1.hi,$src2.hi\n\t"
12458 "skip:\t" %}
12459 ins_encode( long_cmp_flags1( src1, src2 ) );
12460 ins_pipe( ialu_cr_reg_reg );
12461 %}
12462
12463 // Long compare reg == zero/reg OR reg != zero/reg
12464 // Just a wrapper for a normal branch, plus the predicate test.
12465 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12466 match(If cmp flags);
12467 effect(USE labl);
12468 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12469 expand %{
12470 jmpCon(cmp,flags,labl); // JEQ or JNE...
12471 %}
12472 %}
12473
12474 // Compare 2 longs and CMOVE longs.
12475 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12476 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12477 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12478 ins_cost(400);
12479 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12480 "CMOV$cmp $dst.hi,$src.hi" %}
12481 opcode(0x0F,0x40);
12482 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12483 ins_pipe( pipe_cmov_reg_long );
12484 %}
12485
12486 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12487 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12488 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12489 ins_cost(500);
12490 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12491 "CMOV$cmp $dst.hi,$src.hi" %}
12492 opcode(0x0F,0x40);
12493 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12494 ins_pipe( pipe_cmov_reg_long );
12495 %}
12496
12497 // Compare 2 longs and CMOVE ints.
12498 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12499 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12500 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12501 ins_cost(200);
12502 format %{ "CMOV$cmp $dst,$src" %}
12503 opcode(0x0F,0x40);
12504 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12505 ins_pipe( pipe_cmov_reg );
12506 %}
12507
12508 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12509 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12510 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12511 ins_cost(250);
12512 format %{ "CMOV$cmp $dst,$src" %}
12513 opcode(0x0F,0x40);
12514 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12515 ins_pipe( pipe_cmov_mem );
12516 %}
12517
12518 // Compare 2 longs and CMOVE ints.
12519 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12520 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12521 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12522 ins_cost(200);
12523 format %{ "CMOV$cmp $dst,$src" %}
12524 opcode(0x0F,0x40);
12525 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12526 ins_pipe( pipe_cmov_reg );
12527 %}
12528
12529 // Compare 2 longs and CMOVE doubles
12530 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12531 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12532 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12533 ins_cost(200);
12534 expand %{
12535 fcmovDPR_regS(cmp,flags,dst,src);
12536 %}
12537 %}
12538
12539 // Compare 2 longs and CMOVE doubles
12540 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12541 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12542 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12543 ins_cost(200);
12544 expand %{
12545 fcmovD_regS(cmp,flags,dst,src);
12546 %}
12547 %}
12548
12549 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12550 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12551 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12552 ins_cost(200);
12553 expand %{
12554 fcmovFPR_regS(cmp,flags,dst,src);
12555 %}
12556 %}
12557
12558 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12559 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12560 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12561 ins_cost(200);
12562 expand %{
12563 fcmovF_regS(cmp,flags,dst,src);
12564 %}
12565 %}
12566
12567 //======
12568 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12569 // Same as cmpL_reg_flags_LEGT except must negate src
12570 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12571 match( Set flags (CmpL src zero ));
12572 effect( TEMP tmp );
12573 ins_cost(300);
12574 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12575 "CMP $tmp,$src.lo\n\t"
12576 "SBB $tmp,$src.hi\n\t" %}
12577 ins_encode( long_cmp_flags3(src, tmp) );
12578 ins_pipe( ialu_reg_reg_long );
12579 %}
12580
12581 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12582 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12583 // requires a commuted test to get the same result.
12584 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12585 match( Set flags (CmpL src1 src2 ));
12586 effect( TEMP tmp );
12587 ins_cost(300);
12588 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12589 "MOV $tmp,$src2.hi\n\t"
12590 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12591 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12592 ins_pipe( ialu_cr_reg_reg );
12593 %}
12594
12595 // Long compares reg < zero/req OR reg >= zero/req.
12596 // Just a wrapper for a normal branch, plus the predicate test
12597 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12598 match(If cmp flags);
12599 effect(USE labl);
12600 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12601 ins_cost(300);
12602 expand %{
12603 jmpCon(cmp,flags,labl); // JGT or JLE...
12604 %}
12605 %}
12606
12607 // Compare 2 longs and CMOVE longs.
12608 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12609 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12610 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12611 ins_cost(400);
12612 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12613 "CMOV$cmp $dst.hi,$src.hi" %}
12614 opcode(0x0F,0x40);
12615 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12616 ins_pipe( pipe_cmov_reg_long );
12617 %}
12618
12619 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12620 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12621 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12622 ins_cost(500);
12623 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12624 "CMOV$cmp $dst.hi,$src.hi+4" %}
12625 opcode(0x0F,0x40);
12626 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12627 ins_pipe( pipe_cmov_reg_long );
12628 %}
12629
12630 // Compare 2 longs and CMOVE ints.
12631 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12632 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12633 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12634 ins_cost(200);
12635 format %{ "CMOV$cmp $dst,$src" %}
12636 opcode(0x0F,0x40);
12637 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12638 ins_pipe( pipe_cmov_reg );
12639 %}
12640
12641 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12642 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12643 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12644 ins_cost(250);
12645 format %{ "CMOV$cmp $dst,$src" %}
12646 opcode(0x0F,0x40);
12647 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12648 ins_pipe( pipe_cmov_mem );
12649 %}
12650
12651 // Compare 2 longs and CMOVE ptrs.
12652 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12653 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12654 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12655 ins_cost(200);
12656 format %{ "CMOV$cmp $dst,$src" %}
12657 opcode(0x0F,0x40);
12658 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12659 ins_pipe( pipe_cmov_reg );
12660 %}
12661
12662 // Compare 2 longs and CMOVE doubles
12663 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12664 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12665 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12666 ins_cost(200);
12667 expand %{
12668 fcmovDPR_regS(cmp,flags,dst,src);
12669 %}
12670 %}
12671
12672 // Compare 2 longs and CMOVE doubles
12673 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12674 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12675 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12676 ins_cost(200);
12677 expand %{
12678 fcmovD_regS(cmp,flags,dst,src);
12679 %}
12680 %}
12681
12682 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12683 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12684 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12685 ins_cost(200);
12686 expand %{
12687 fcmovFPR_regS(cmp,flags,dst,src);
12688 %}
12689 %}
12690
12691
12692 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12693 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12694 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12695 ins_cost(200);
12696 expand %{
12697 fcmovF_regS(cmp,flags,dst,src);
12698 %}
12699 %}
12700
12701
12702 // ============================================================================
12703 // Procedure Call/Return Instructions
12704 // Call Java Static Instruction
12705 // Note: If this code changes, the corresponding ret_addr_offset() and
12706 // compute_padding() functions will have to be adjusted.
12707 instruct CallStaticJavaDirect(method meth) %{
12708 match(CallStaticJava);
12709 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12710 effect(USE meth);
12711
12712 ins_cost(300);
12713 format %{ "CALL,static " %}
12714 opcode(0xE8); /* E8 cd */
12715 ins_encode( pre_call_resets,
12716 Java_Static_Call( meth ),
12717 call_epilog,
12718 post_call_FPU );
12719 ins_pipe( pipe_slow );
12720 ins_alignment(4);
12721 %}
12722
12723 // Call Java Static Instruction (method handle version)
12724 // Note: If this code changes, the corresponding ret_addr_offset() and
12725 // compute_padding() functions will have to be adjusted.
12726 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12727 match(CallStaticJava);
12728 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12729 effect(USE meth);
12730 // EBP is saved by all callees (for interpreter stack correction).
12731 // We use it here for a similar purpose, in {preserve,restore}_SP.
12732
12733 ins_cost(300);
12734 format %{ "CALL,static/MethodHandle " %}
12735 opcode(0xE8); /* E8 cd */
12736 ins_encode( pre_call_resets,
12737 preserve_SP,
12738 Java_Static_Call( meth ),
12739 restore_SP,
12740 call_epilog,
12741 post_call_FPU );
12742 ins_pipe( pipe_slow );
12743 ins_alignment(4);
12744 %}
12745
12746 // Call Java Dynamic Instruction
12747 // Note: If this code changes, the corresponding ret_addr_offset() and
12748 // compute_padding() functions will have to be adjusted.
12749 instruct CallDynamicJavaDirect(method meth) %{
12750 match(CallDynamicJava);
12751 effect(USE meth);
12752
12753 ins_cost(300);
12754 format %{ "MOV EAX,(oop)-1\n\t"
12755 "CALL,dynamic" %}
12756 opcode(0xE8); /* E8 cd */
12757 ins_encode( pre_call_resets,
12758 Java_Dynamic_Call( meth ),
12759 call_epilog,
12760 post_call_FPU );
12761 ins_pipe( pipe_slow );
12762 ins_alignment(4);
12763 %}
12764
12765 // Call Runtime Instruction
12766 instruct CallRuntimeDirect(method meth) %{
12767 match(CallRuntime );
12768 effect(USE meth);
12769
12770 ins_cost(300);
12771 format %{ "CALL,runtime " %}
12772 opcode(0xE8); /* E8 cd */
12773 // Use FFREEs to clear entries in float stack
12774 ins_encode( pre_call_resets,
12775 FFree_Float_Stack_All,
12776 Java_To_Runtime( meth ),
12777 post_call_FPU );
12778 ins_pipe( pipe_slow );
12779 %}
12780
12781 // Call runtime without safepoint
12782 instruct CallLeafDirect(method meth) %{
12783 match(CallLeaf);
12784 effect(USE meth);
12785
12786 ins_cost(300);
12787 format %{ "CALL_LEAF,runtime " %}
12788 opcode(0xE8); /* E8 cd */
12789 ins_encode( pre_call_resets,
12790 FFree_Float_Stack_All,
12791 Java_To_Runtime( meth ),
12792 Verify_FPU_For_Leaf, post_call_FPU );
12793 ins_pipe( pipe_slow );
12794 %}
12795
12796 instruct CallLeafNoFPDirect(method meth) %{
12797 match(CallLeafNoFP);
12798 effect(USE meth);
12799
12800 ins_cost(300);
12801 format %{ "CALL_LEAF_NOFP,runtime " %}
12802 opcode(0xE8); /* E8 cd */
12803 ins_encode(Java_To_Runtime(meth));
12804 ins_pipe( pipe_slow );
12805 %}
12806
12807
12808 // Return Instruction
12809 // Remove the return address & jump to it.
12810 instruct Ret() %{
12811 match(Return);
12812 format %{ "RET" %}
12813 opcode(0xC3);
12814 ins_encode(OpcP);
12815 ins_pipe( pipe_jmp );
12816 %}
12817
12818 // Tail Call; Jump from runtime stub to Java code.
12819 // Also known as an 'interprocedural jump'.
12820 // Target of jump will eventually return to caller.
12821 // TailJump below removes the return address.
12822 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12823 match(TailCall jump_target method_oop );
12824 ins_cost(300);
12825 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12826 opcode(0xFF, 0x4); /* Opcode FF /4 */
12827 ins_encode( OpcP, RegOpc(jump_target) );
12828 ins_pipe( pipe_jmp );
12829 %}
12830
12831
12832 // Tail Jump; remove the return address; jump to target.
12833 // TailCall above leaves the return address around.
12834 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12835 match( TailJump jump_target ex_oop );
12836 ins_cost(300);
12837 format %{ "POP EDX\t# pop return address into dummy\n\t"
12838 "JMP $jump_target " %}
12839 opcode(0xFF, 0x4); /* Opcode FF /4 */
12840 ins_encode( enc_pop_rdx,
12841 OpcP, RegOpc(jump_target) );
12842 ins_pipe( pipe_jmp );
12843 %}
12844
12845 // Create exception oop: created by stack-crawling runtime code.
12846 // Created exception is now available to this handler, and is setup
12847 // just prior to jumping to this handler. No code emitted.
12848 instruct CreateException( eAXRegP ex_oop )
12849 %{
12850 match(Set ex_oop (CreateEx));
12851
12852 size(0);
12853 // use the following format syntax
12854 format %{ "# exception oop is in EAX; no code emitted" %}
12855 ins_encode();
12856 ins_pipe( empty );
12857 %}
12858
12859
12860 // Rethrow exception:
12861 // The exception oop will come in the first argument position.
12862 // Then JUMP (not call) to the rethrow stub code.
12863 instruct RethrowException()
12864 %{
12865 match(Rethrow);
12866
12867 // use the following format syntax
12868 format %{ "JMP rethrow_stub" %}
12869 ins_encode(enc_rethrow);
12870 ins_pipe( pipe_jmp );
12871 %}
12872
12873 // inlined locking and unlocking
12874
12875 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12876 match(Set cr (FastLock object box));
12877 effect(TEMP tmp, TEMP scr, USE_KILL box);
12878 ins_cost(300);
12879 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12880 ins_encode %{
12881 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register, _counters);
12882 %}
12883 ins_pipe(pipe_slow);
12884 %}
12885
12886 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12887 match(Set cr (FastUnlock object box));
12888 effect(TEMP tmp, USE_KILL box);
12889 ins_cost(300);
12890 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12891 ins_encode %{
12892 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12893 %}
12894 ins_pipe(pipe_slow);
12895 %}
12896
12897
12898
12899 // ============================================================================
12900 // Safepoint Instruction
12901 instruct safePoint_poll(eFlagsReg cr) %{
12902 match(SafePoint);
12903 effect(KILL cr);
12904
12905 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12906 // On SPARC that might be acceptable as we can generate the address with
12907 // just a sethi, saving an or. By polling at offset 0 we can end up
12908 // putting additional pressure on the index-0 in the D$. Because of
12909 // alignment (just like the situation at hand) the lower indices tend
12910 // to see more traffic. It'd be better to change the polling address
12911 // to offset 0 of the last $line in the polling page.
12912
12913 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12914 ins_cost(125);
12915 size(6) ;
12916 ins_encode( Safepoint_Poll() );
12917 ins_pipe( ialu_reg_mem );
12918 %}
12919
12920
12921 // ============================================================================
12922 // This name is KNOWN by the ADLC and cannot be changed.
12923 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12924 // for this guy.
12925 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12926 match(Set dst (ThreadLocal));
12927 effect(DEF dst, KILL cr);
12928
12929 format %{ "MOV $dst, Thread::current()" %}
12930 ins_encode %{
12931 Register dstReg = as_Register($dst$$reg);
12932 __ get_thread(dstReg);
12933 %}
12934 ins_pipe( ialu_reg_fat );
12935 %}
12936
12937
12938
12939 //----------PEEPHOLE RULES-----------------------------------------------------
12940 // These must follow all instruction definitions as they use the names
12941 // defined in the instructions definitions.
12942 //
12943 // peepmatch ( root_instr_name [preceding_instruction]* );
12944 //
12945 // peepconstraint %{
12946 // (instruction_number.operand_name relational_op instruction_number.operand_name
12947 // [, ...] );
12948 // // instruction numbers are zero-based using left to right order in peepmatch
12949 //
12950 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12951 // // provide an instruction_number.operand_name for each operand that appears
12952 // // in the replacement instruction's match rule
12953 //
12954 // ---------VM FLAGS---------------------------------------------------------
12955 //
12956 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12957 //
12958 // Each peephole rule is given an identifying number starting with zero and
12959 // increasing by one in the order seen by the parser. An individual peephole
12960 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12961 // on the command-line.
12962 //
12963 // ---------CURRENT LIMITATIONS----------------------------------------------
12964 //
12965 // Only match adjacent instructions in same basic block
12966 // Only equality constraints
12967 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12968 // Only one replacement instruction
12969 //
12970 // ---------EXAMPLE----------------------------------------------------------
12971 //
12972 // // pertinent parts of existing instructions in architecture description
12973 // instruct movI(rRegI dst, rRegI src) %{
12974 // match(Set dst (CopyI src));
12975 // %}
12976 //
12977 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
12978 // match(Set dst (AddI dst src));
12979 // effect(KILL cr);
12980 // %}
12981 //
12982 // // Change (inc mov) to lea
12983 // peephole %{
12984 // // increment preceeded by register-register move
12985 // peepmatch ( incI_eReg movI );
12986 // // require that the destination register of the increment
12987 // // match the destination register of the move
12988 // peepconstraint ( 0.dst == 1.dst );
12989 // // construct a replacement instruction that sets
12990 // // the destination to ( move's source register + one )
12991 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12992 // %}
12993 //
12994 // Implementation no longer uses movX instructions since
12995 // machine-independent system no longer uses CopyX nodes.
12996 //
12997 // peephole %{
12998 // peepmatch ( incI_eReg movI );
12999 // peepconstraint ( 0.dst == 1.dst );
13000 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13001 // %}
13002 //
13003 // peephole %{
13004 // peepmatch ( decI_eReg movI );
13005 // peepconstraint ( 0.dst == 1.dst );
13006 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13007 // %}
13008 //
13009 // peephole %{
13010 // peepmatch ( addI_eReg_imm movI );
13011 // peepconstraint ( 0.dst == 1.dst );
13012 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13013 // %}
13014 //
13015 // peephole %{
13016 // peepmatch ( addP_eReg_imm movP );
13017 // peepconstraint ( 0.dst == 1.dst );
13018 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13019 // %}
13020
13021 // // Change load of spilled value to only a spill
13022 // instruct storeI(memory mem, rRegI src) %{
13023 // match(Set mem (StoreI mem src));
13024 // %}
13025 //
13026 // instruct loadI(rRegI dst, memory mem) %{
13027 // match(Set dst (LoadI mem));
13028 // %}
13029 //
13030 peephole %{
13031 peepmatch ( loadI storeI );
13032 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13033 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13034 %}
13035
13036 //----------SMARTSPILL RULES---------------------------------------------------
13037 // These must follow all instruction definitions as they use the names
13038 // defined in the instructions definitions.