1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2014 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "prims/methodHandles.hpp"
34 #include "runtime/biasedLocking.hpp"
35 #include "runtime/icache.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc_implementation/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
47
48 #ifdef PRODUCT
49 #define BLOCK_COMMENT(str) // nothing
50 #else
51 #define BLOCK_COMMENT(str) block_comment(str)
52 #endif
53
54 #ifdef ASSERT
55 // On RISC, there's no benefit to verifying instruction boundaries.
56 bool AbstractAssembler::pd_check_instruction_mark() { return false; }
57 #endif
58
59 void MacroAssembler::ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop) {
60 assert(Assembler::is_simm(si31, 31) && si31 >= 0, "si31 out of range");
61 if (Assembler::is_simm(si31, 16)) {
62 ld(d, si31, a);
63 if (emit_filler_nop) nop();
64 } else {
65 const int hi = MacroAssembler::largeoffset_si16_si16_hi(si31);
66 const int lo = MacroAssembler::largeoffset_si16_si16_lo(si31);
67 addis(d, a, hi);
68 ld(d, lo, d);
69 }
70 }
71
72 void MacroAssembler::ld_largeoffset(Register d, int si31, Register a, int emit_filler_nop) {
73 assert_different_registers(d, a);
74 ld_largeoffset_unchecked(d, si31, a, emit_filler_nop);
75 }
76
77 void MacroAssembler::load_sized_value(Register dst, RegisterOrConstant offs, Register base,
78 size_t size_in_bytes, bool is_signed) {
79 switch (size_in_bytes) {
80 case 8: ld(dst, offs, base); break;
81 case 4: is_signed ? lwa(dst, offs, base) : lwz(dst, offs, base); break;
82 case 2: is_signed ? lha(dst, offs, base) : lhz(dst, offs, base); break;
83 case 1: lbz(dst, offs, base); if (is_signed) extsb(dst, dst); break; // lba doesn't exist :(
84 default: ShouldNotReachHere();
85 }
86 }
87
88 void MacroAssembler::store_sized_value(Register dst, RegisterOrConstant offs, Register base,
89 size_t size_in_bytes) {
90 switch (size_in_bytes) {
91 case 8: std(dst, offs, base); break;
92 case 4: stw(dst, offs, base); break;
93 case 2: sth(dst, offs, base); break;
94 case 1: stb(dst, offs, base); break;
95 default: ShouldNotReachHere();
96 }
97 }
98
99 void MacroAssembler::align(int modulus, int max, int rem) {
100 int padding = (rem + modulus - (offset() % modulus)) % modulus;
101 if (padding > max) return;
102 for (int c = (padding >> 2); c > 0; --c) { nop(); }
103 }
104
105 // Issue instructions that calculate given TOC from global TOC.
106 void MacroAssembler::calculate_address_from_global_toc(Register dst, address addr, bool hi16, bool lo16,
107 bool add_relocation, bool emit_dummy_addr) {
108 int offset = -1;
109 if (emit_dummy_addr) {
110 offset = -128; // dummy address
111 } else if (addr != (address)(intptr_t)-1) {
112 offset = MacroAssembler::offset_to_global_toc(addr);
113 }
114
115 if (hi16) {
116 addis(dst, R29, MacroAssembler::largeoffset_si16_si16_hi(offset));
117 }
118 if (lo16) {
119 if (add_relocation) {
120 // Relocate at the addi to avoid confusion with a load from the method's TOC.
121 relocate(internal_word_Relocation::spec(addr));
122 }
123 addi(dst, dst, MacroAssembler::largeoffset_si16_si16_lo(offset));
124 }
125 }
126
127 int MacroAssembler::patch_calculate_address_from_global_toc_at(address a, address bound, address addr) {
128 const int offset = MacroAssembler::offset_to_global_toc(addr);
129
130 const address inst2_addr = a;
131 const int inst2 = *(int *)inst2_addr;
132
133 // The relocation points to the second instruction, the addi,
134 // and the addi reads and writes the same register dst.
135 const int dst = inv_rt_field(inst2);
136 assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");
137
138 // Now, find the preceding addis which writes to dst.
139 int inst1 = 0;
140 address inst1_addr = inst2_addr - BytesPerInstWord;
141 while (inst1_addr >= bound) {
142 inst1 = *(int *) inst1_addr;
143 if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
144 // Stop, found the addis which writes dst.
145 break;
146 }
147 inst1_addr -= BytesPerInstWord;
148 }
149
150 assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");
151 set_imm((int *)inst1_addr, MacroAssembler::largeoffset_si16_si16_hi(offset));
152 set_imm((int *)inst2_addr, MacroAssembler::largeoffset_si16_si16_lo(offset));
153 return (int)((intptr_t)addr - (intptr_t)inst1_addr);
154 }
155
156 address MacroAssembler::get_address_of_calculate_address_from_global_toc_at(address a, address bound) {
157 const address inst2_addr = a;
158 const int inst2 = *(int *)inst2_addr;
159
160 // The relocation points to the second instruction, the addi,
161 // and the addi reads and writes the same register dst.
162 const int dst = inv_rt_field(inst2);
163 assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");
164
165 // Now, find the preceding addis which writes to dst.
166 int inst1 = 0;
167 address inst1_addr = inst2_addr - BytesPerInstWord;
168 while (inst1_addr >= bound) {
169 inst1 = *(int *) inst1_addr;
170 if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
171 // stop, found the addis which writes dst
172 break;
173 }
174 inst1_addr -= BytesPerInstWord;
175 }
176
177 assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");
178
179 int offset = (get_imm(inst1_addr, 0) << 16) + get_imm(inst2_addr, 0);
180 // -1 is a special case
181 if (offset == -1) {
182 return (address)(intptr_t)-1;
183 } else {
184 return global_toc() + offset;
185 }
186 }
187
188 #ifdef _LP64
189 // Patch compressed oops or klass constants.
190 // Assembler sequence is
191 // 1) compressed oops:
192 // lis rx = const.hi
193 // ori rx = rx | const.lo
194 // 2) compressed klass:
195 // lis rx = const.hi
196 // clrldi rx = rx & 0xFFFFffff // clearMS32b, optional
197 // ori rx = rx | const.lo
198 // Clrldi will be passed by.
199 int MacroAssembler::patch_set_narrow_oop(address a, address bound, narrowOop data) {
200 assert(UseCompressedOops, "Should only patch compressed oops");
201
202 const address inst2_addr = a;
203 const int inst2 = *(int *)inst2_addr;
204
205 // The relocation points to the second instruction, the ori,
206 // and the ori reads and writes the same register dst.
207 const int dst = inv_rta_field(inst2);
208 assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");
209 // Now, find the preceding addis which writes to dst.
210 int inst1 = 0;
211 address inst1_addr = inst2_addr - BytesPerInstWord;
212 bool inst1_found = false;
213 while (inst1_addr >= bound) {
214 inst1 = *(int *)inst1_addr;
215 if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break; }
216 inst1_addr -= BytesPerInstWord;
217 }
218 assert(inst1_found, "inst is not lis");
219
220 int xc = (data >> 16) & 0xffff;
221 int xd = (data >> 0) & 0xffff;
222
223 set_imm((int *)inst1_addr, (short)(xc)); // see enc_load_con_narrow_hi/_lo
224 set_imm((int *)inst2_addr, (xd)); // unsigned int
225 return (int)((intptr_t)inst2_addr - (intptr_t)inst1_addr);
226 }
227
228 // Get compressed oop or klass constant.
229 narrowOop MacroAssembler::get_narrow_oop(address a, address bound) {
230 assert(UseCompressedOops, "Should only patch compressed oops");
231
232 const address inst2_addr = a;
233 const int inst2 = *(int *)inst2_addr;
234
235 // The relocation points to the second instruction, the ori,
236 // and the ori reads and writes the same register dst.
237 const int dst = inv_rta_field(inst2);
238 assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");
239 // Now, find the preceding lis which writes to dst.
240 int inst1 = 0;
241 address inst1_addr = inst2_addr - BytesPerInstWord;
242 bool inst1_found = false;
243
244 while (inst1_addr >= bound) {
245 inst1 = *(int *) inst1_addr;
246 if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break;}
247 inst1_addr -= BytesPerInstWord;
248 }
249 assert(inst1_found, "inst is not lis");
250
251 uint xl = ((unsigned int) (get_imm(inst2_addr, 0) & 0xffff));
252 uint xh = (((get_imm(inst1_addr, 0)) & 0xffff) << 16);
253
254 return (int) (xl | xh);
255 }
256 #endif // _LP64
257
258 void MacroAssembler::load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc) {
259 int toc_offset = 0;
260 // Use RelocationHolder::none for the constant pool entry, otherwise
261 // we will end up with a failing NativeCall::verify(x) where x is
262 // the address of the constant pool entry.
263 // FIXME: We should insert relocation information for oops at the constant
264 // pool entries instead of inserting it at the loads; patching of a constant
265 // pool entry should be less expensive.
266 address oop_address = address_constant((address)a.value(), RelocationHolder::none);
267 // Relocate at the pc of the load.
268 relocate(a.rspec());
269 toc_offset = (int)(oop_address - code()->consts()->start());
270 ld_largeoffset_unchecked(dst, toc_offset, toc, true);
271 }
272
273 bool MacroAssembler::is_load_const_from_method_toc_at(address a) {
274 const address inst1_addr = a;
275 const int inst1 = *(int *)inst1_addr;
276
277 // The relocation points to the ld or the addis.
278 return (is_ld(inst1)) ||
279 (is_addis(inst1) && inv_ra_field(inst1) != 0);
280 }
281
282 int MacroAssembler::get_offset_of_load_const_from_method_toc_at(address a) {
283 assert(is_load_const_from_method_toc_at(a), "must be load_const_from_method_toc");
284
285 const address inst1_addr = a;
286 const int inst1 = *(int *)inst1_addr;
287
288 if (is_ld(inst1)) {
289 return inv_d1_field(inst1);
290 } else if (is_addis(inst1)) {
291 const int dst = inv_rt_field(inst1);
292
293 // Now, find the succeeding ld which reads and writes to dst.
294 address inst2_addr = inst1_addr + BytesPerInstWord;
295 int inst2 = 0;
296 while (true) {
297 inst2 = *(int *) inst2_addr;
298 if (is_ld(inst2) && inv_ra_field(inst2) == dst && inv_rt_field(inst2) == dst) {
299 // Stop, found the ld which reads and writes dst.
300 break;
301 }
302 inst2_addr += BytesPerInstWord;
303 }
304 return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2);
305 }
306 ShouldNotReachHere();
307 return 0;
308 }
309
310 // Get the constant from a `load_const' sequence.
311 long MacroAssembler::get_const(address a) {
312 assert(is_load_const_at(a), "not a load of a constant");
313 const int *p = (const int*) a;
314 unsigned long x = (((unsigned long) (get_imm(a,0) & 0xffff)) << 48);
315 if (is_ori(*(p+1))) {
316 x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 32);
317 x |= (((unsigned long) (get_imm(a,3) & 0xffff)) << 16);
318 x |= (((unsigned long) (get_imm(a,4) & 0xffff)));
319 } else if (is_lis(*(p+1))) {
320 x |= (((unsigned long) (get_imm(a,2) & 0xffff)) << 32);
321 x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 16);
322 x |= (((unsigned long) (get_imm(a,3) & 0xffff)));
323 } else {
324 ShouldNotReachHere();
325 return (long) 0;
326 }
327 return (long) x;
328 }
329
330 // Patch the 64 bit constant of a `load_const' sequence. This is a low
331 // level procedure. It neither flushes the instruction cache nor is it
332 // mt safe.
333 void MacroAssembler::patch_const(address a, long x) {
334 assert(is_load_const_at(a), "not a load of a constant");
335 int *p = (int*) a;
336 if (is_ori(*(p+1))) {
337 set_imm(0 + p, (x >> 48) & 0xffff);
338 set_imm(1 + p, (x >> 32) & 0xffff);
339 set_imm(3 + p, (x >> 16) & 0xffff);
340 set_imm(4 + p, x & 0xffff);
341 } else if (is_lis(*(p+1))) {
342 set_imm(0 + p, (x >> 48) & 0xffff);
343 set_imm(2 + p, (x >> 32) & 0xffff);
344 set_imm(1 + p, (x >> 16) & 0xffff);
345 set_imm(3 + p, x & 0xffff);
346 } else {
347 ShouldNotReachHere();
348 }
349 }
350
351 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
352 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
353 int index = oop_recorder()->allocate_metadata_index(obj);
354 RelocationHolder rspec = metadata_Relocation::spec(index);
355 return AddressLiteral((address)obj, rspec);
356 }
357
358 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
359 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
360 int index = oop_recorder()->find_index(obj);
361 RelocationHolder rspec = metadata_Relocation::spec(index);
362 return AddressLiteral((address)obj, rspec);
363 }
364
365 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
366 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
367 int oop_index = oop_recorder()->allocate_oop_index(obj);
368 return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
369 }
370
371 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
372 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
373 int oop_index = oop_recorder()->find_index(obj);
374 return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
375 }
376
377 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
378 Register tmp, int offset) {
379 intptr_t value = *delayed_value_addr;
380 if (value != 0) {
381 return RegisterOrConstant(value + offset);
382 }
383
384 // Load indirectly to solve generation ordering problem.
385 // static address, no relocation
386 int simm16_offset = load_const_optimized(tmp, delayed_value_addr, noreg, true);
387 ld(tmp, simm16_offset, tmp); // must be aligned ((xa & 3) == 0)
388
389 if (offset != 0) {
390 addi(tmp, tmp, offset);
391 }
392
393 return RegisterOrConstant(tmp);
394 }
395
396 #ifndef PRODUCT
397 void MacroAssembler::pd_print_patched_instruction(address branch) {
398 Unimplemented(); // TODO: PPC port
399 }
400 #endif // ndef PRODUCT
401
402 // Conditional far branch for destinations encodable in 24+2 bits.
403 void MacroAssembler::bc_far(int boint, int biint, Label& dest, int optimize) {
404
405 // If requested by flag optimize, relocate the bc_far as a
406 // runtime_call and prepare for optimizing it when the code gets
407 // relocated.
408 if (optimize == bc_far_optimize_on_relocate) {
409 relocate(relocInfo::runtime_call_type);
410 }
411
412 // variant 2:
413 //
414 // b!cxx SKIP
415 // bxx DEST
416 // SKIP:
417 //
418
419 const int opposite_boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(boint)),
420 opposite_bcond(inv_boint_bcond(boint)));
421
422 // We emit two branches.
423 // First, a conditional branch which jumps around the far branch.
424 const address not_taken_pc = pc() + 2 * BytesPerInstWord;
425 const address bc_pc = pc();
426 bc(opposite_boint, biint, not_taken_pc);
427
428 const int bc_instr = *(int*)bc_pc;
429 assert(not_taken_pc == (address)inv_bd_field(bc_instr, (intptr_t)bc_pc), "postcondition");
430 assert(opposite_boint == inv_bo_field(bc_instr), "postcondition");
431 assert(boint == add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(bc_instr))),
432 opposite_bcond(inv_boint_bcond(inv_bo_field(bc_instr)))),
433 "postcondition");
434 assert(biint == inv_bi_field(bc_instr), "postcondition");
435
436 // Second, an unconditional far branch which jumps to dest.
437 // Note: target(dest) remembers the current pc (see CodeSection::target)
438 // and returns the current pc if the label is not bound yet; when
439 // the label gets bound, the unconditional far branch will be patched.
440 const address target_pc = target(dest);
441 const address b_pc = pc();
442 b(target_pc);
443
444 assert(not_taken_pc == pc(), "postcondition");
445 assert(dest.is_bound() || target_pc == b_pc, "postcondition");
446 }
447
448 bool MacroAssembler::is_bc_far_at(address instruction_addr) {
449 return is_bc_far_variant1_at(instruction_addr) ||
450 is_bc_far_variant2_at(instruction_addr) ||
451 is_bc_far_variant3_at(instruction_addr);
452 }
453
454 address MacroAssembler::get_dest_of_bc_far_at(address instruction_addr) {
455 if (is_bc_far_variant1_at(instruction_addr)) {
456 const address instruction_1_addr = instruction_addr;
457 const int instruction_1 = *(int*)instruction_1_addr;
458 return (address)inv_bd_field(instruction_1, (intptr_t)instruction_1_addr);
459 } else if (is_bc_far_variant2_at(instruction_addr)) {
460 const address instruction_2_addr = instruction_addr + 4;
461 return bxx_destination(instruction_2_addr);
462 } else if (is_bc_far_variant3_at(instruction_addr)) {
463 return instruction_addr + 8;
464 }
465 // variant 4 ???
466 ShouldNotReachHere();
467 return NULL;
468 }
469 void MacroAssembler::set_dest_of_bc_far_at(address instruction_addr, address dest) {
470
471 if (is_bc_far_variant3_at(instruction_addr)) {
472 // variant 3, far cond branch to the next instruction, already patched to nops:
473 //
474 // nop
475 // endgroup
476 // SKIP/DEST:
477 //
478 return;
479 }
480
481 // first, extract boint and biint from the current branch
482 int boint = 0;
483 int biint = 0;
484
485 ResourceMark rm;
486 const int code_size = 2 * BytesPerInstWord;
487 CodeBuffer buf(instruction_addr, code_size);
488 MacroAssembler masm(&buf);
489 if (is_bc_far_variant2_at(instruction_addr) && dest == instruction_addr + 8) {
490 // Far branch to next instruction: Optimize it by patching nops (produce variant 3).
491 masm.nop();
492 masm.endgroup();
493 } else {
494 if (is_bc_far_variant1_at(instruction_addr)) {
495 // variant 1, the 1st instruction contains the destination address:
496 //
497 // bcxx DEST
498 // endgroup
499 //
500 const int instruction_1 = *(int*)(instruction_addr);
501 boint = inv_bo_field(instruction_1);
502 biint = inv_bi_field(instruction_1);
503 } else if (is_bc_far_variant2_at(instruction_addr)) {
504 // variant 2, the 2nd instruction contains the destination address:
505 //
506 // b!cxx SKIP
507 // bxx DEST
508 // SKIP:
509 //
510 const int instruction_1 = *(int*)(instruction_addr);
511 boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(instruction_1))),
512 opposite_bcond(inv_boint_bcond(inv_bo_field(instruction_1))));
513 biint = inv_bi_field(instruction_1);
514 } else {
515 // variant 4???
516 ShouldNotReachHere();
517 }
518
519 // second, set the new branch destination and optimize the code
520 if (dest != instruction_addr + 4 && // the bc_far is still unbound!
521 masm.is_within_range_of_bcxx(dest, instruction_addr)) {
522 // variant 1:
523 //
524 // bcxx DEST
525 // endgroup
526 //
527 masm.bc(boint, biint, dest);
528 masm.endgroup();
529 } else {
530 // variant 2:
531 //
532 // b!cxx SKIP
533 // bxx DEST
534 // SKIP:
535 //
536 const int opposite_boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(boint)),
537 opposite_bcond(inv_boint_bcond(boint)));
538 const address not_taken_pc = masm.pc() + 2 * BytesPerInstWord;
539 masm.bc(opposite_boint, biint, not_taken_pc);
540 masm.b(dest);
541 }
542 }
543 ICache::ppc64_flush_icache_bytes(instruction_addr, code_size);
544 }
545
546 // Emit a NOT mt-safe patchable 64 bit absolute call/jump.
547 void MacroAssembler::bxx64_patchable(address dest, relocInfo::relocType rt, bool link) {
548 // get current pc
549 uint64_t start_pc = (uint64_t) pc();
550
551 const address pc_of_bl = (address) (start_pc + (6*BytesPerInstWord)); // bl is last
552 const address pc_of_b = (address) (start_pc + (0*BytesPerInstWord)); // b is first
553
554 // relocate here
555 if (rt != relocInfo::none) {
556 relocate(rt);
557 }
558
559 if ( ReoptimizeCallSequences &&
560 (( link && is_within_range_of_b(dest, pc_of_bl)) ||
561 (!link && is_within_range_of_b(dest, pc_of_b)))) {
562 // variant 2:
563 // Emit an optimized, pc-relative call/jump.
564
565 if (link) {
566 // some padding
567 nop();
568 nop();
569 nop();
570 nop();
571 nop();
572 nop();
573
574 // do the call
575 assert(pc() == pc_of_bl, "just checking");
576 bl(dest, relocInfo::none);
577 } else {
578 // do the jump
579 assert(pc() == pc_of_b, "just checking");
580 b(dest, relocInfo::none);
581
582 // some padding
583 nop();
584 nop();
585 nop();
586 nop();
587 nop();
588 nop();
589 }
590
591 // Assert that we can identify the emitted call/jump.
592 assert(is_bxx64_patchable_variant2_at((address)start_pc, link),
593 "can't identify emitted call");
594 } else {
595 // variant 1:
596 #if defined(ABI_ELFv2)
597 nop();
598 calculate_address_from_global_toc(R12, dest, true, true, false);
599 mtctr(R12);
600 nop();
601 nop();
602 #else
603 mr(R0, R11); // spill R11 -> R0.
604
605 // Load the destination address into CTR,
606 // calculate destination relative to global toc.
607 calculate_address_from_global_toc(R11, dest, true, true, false);
608
609 mtctr(R11);
610 mr(R11, R0); // spill R11 <- R0.
611 nop();
612 #endif
613
614 // do the call/jump
615 if (link) {
616 bctrl();
617 } else{
618 bctr();
619 }
620 // Assert that we can identify the emitted call/jump.
621 assert(is_bxx64_patchable_variant1b_at((address)start_pc, link),
622 "can't identify emitted call");
623 }
624
625 // Assert that we can identify the emitted call/jump.
626 assert(is_bxx64_patchable_at((address)start_pc, link),
627 "can't identify emitted call");
628 assert(get_dest_of_bxx64_patchable_at((address)start_pc, link) == dest,
629 "wrong encoding of dest address");
630 }
631
632 // Identify a bxx64_patchable instruction.
633 bool MacroAssembler::is_bxx64_patchable_at(address instruction_addr, bool link) {
634 return is_bxx64_patchable_variant1b_at(instruction_addr, link)
635 //|| is_bxx64_patchable_variant1_at(instruction_addr, link)
636 || is_bxx64_patchable_variant2_at(instruction_addr, link);
637 }
638
639 // Does the call64_patchable instruction use a pc-relative encoding of
640 // the call destination?
641 bool MacroAssembler::is_bxx64_patchable_pcrelative_at(address instruction_addr, bool link) {
642 // variant 2 is pc-relative
643 return is_bxx64_patchable_variant2_at(instruction_addr, link);
644 }
645
646 // Identify variant 1.
647 bool MacroAssembler::is_bxx64_patchable_variant1_at(address instruction_addr, bool link) {
648 unsigned int* instr = (unsigned int*) instruction_addr;
649 return (link ? is_bctrl(instr[6]) : is_bctr(instr[6])) // bctr[l]
650 && is_mtctr(instr[5]) // mtctr
651 && is_load_const_at(instruction_addr);
652 }
653
654 // Identify variant 1b: load destination relative to global toc.
655 bool MacroAssembler::is_bxx64_patchable_variant1b_at(address instruction_addr, bool link) {
656 unsigned int* instr = (unsigned int*) instruction_addr;
657 return (link ? is_bctrl(instr[6]) : is_bctr(instr[6])) // bctr[l]
658 && is_mtctr(instr[3]) // mtctr
659 && is_calculate_address_from_global_toc_at(instruction_addr + 2*BytesPerInstWord, instruction_addr);
660 }
661
662 // Identify variant 2.
663 bool MacroAssembler::is_bxx64_patchable_variant2_at(address instruction_addr, bool link) {
664 unsigned int* instr = (unsigned int*) instruction_addr;
665 if (link) {
666 return is_bl (instr[6]) // bl dest is last
667 && is_nop(instr[0]) // nop
668 && is_nop(instr[1]) // nop
669 && is_nop(instr[2]) // nop
670 && is_nop(instr[3]) // nop
671 && is_nop(instr[4]) // nop
672 && is_nop(instr[5]); // nop
673 } else {
674 return is_b (instr[0]) // b dest is first
675 && is_nop(instr[1]) // nop
676 && is_nop(instr[2]) // nop
677 && is_nop(instr[3]) // nop
678 && is_nop(instr[4]) // nop
679 && is_nop(instr[5]) // nop
680 && is_nop(instr[6]); // nop
681 }
682 }
683
684 // Set dest address of a bxx64_patchable instruction.
685 void MacroAssembler::set_dest_of_bxx64_patchable_at(address instruction_addr, address dest, bool link) {
686 ResourceMark rm;
687 int code_size = MacroAssembler::bxx64_patchable_size;
688 CodeBuffer buf(instruction_addr, code_size);
689 MacroAssembler masm(&buf);
690 masm.bxx64_patchable(dest, relocInfo::none, link);
691 ICache::ppc64_flush_icache_bytes(instruction_addr, code_size);
692 }
693
694 // Get dest address of a bxx64_patchable instruction.
695 address MacroAssembler::get_dest_of_bxx64_patchable_at(address instruction_addr, bool link) {
696 if (is_bxx64_patchable_variant1_at(instruction_addr, link)) {
697 return (address) (unsigned long) get_const(instruction_addr);
698 } else if (is_bxx64_patchable_variant2_at(instruction_addr, link)) {
699 unsigned int* instr = (unsigned int*) instruction_addr;
700 if (link) {
701 const int instr_idx = 6; // bl is last
702 int branchoffset = branch_destination(instr[instr_idx], 0);
703 return instruction_addr + branchoffset + instr_idx*BytesPerInstWord;
704 } else {
705 const int instr_idx = 0; // b is first
706 int branchoffset = branch_destination(instr[instr_idx], 0);
707 return instruction_addr + branchoffset + instr_idx*BytesPerInstWord;
708 }
709 // Load dest relative to global toc.
710 } else if (is_bxx64_patchable_variant1b_at(instruction_addr, link)) {
711 return get_address_of_calculate_address_from_global_toc_at(instruction_addr + 2*BytesPerInstWord,
712 instruction_addr);
713 } else {
714 ShouldNotReachHere();
715 return NULL;
716 }
717 }
718
719 // Uses ordering which corresponds to ABI:
720 // _savegpr0_14: std r14,-144(r1)
721 // _savegpr0_15: std r15,-136(r1)
722 // _savegpr0_16: std r16,-128(r1)
723 void MacroAssembler::save_nonvolatile_gprs(Register dst, int offset) {
724 std(R14, offset, dst); offset += 8;
725 std(R15, offset, dst); offset += 8;
726 std(R16, offset, dst); offset += 8;
727 std(R17, offset, dst); offset += 8;
728 std(R18, offset, dst); offset += 8;
729 std(R19, offset, dst); offset += 8;
730 std(R20, offset, dst); offset += 8;
731 std(R21, offset, dst); offset += 8;
732 std(R22, offset, dst); offset += 8;
733 std(R23, offset, dst); offset += 8;
734 std(R24, offset, dst); offset += 8;
735 std(R25, offset, dst); offset += 8;
736 std(R26, offset, dst); offset += 8;
737 std(R27, offset, dst); offset += 8;
738 std(R28, offset, dst); offset += 8;
739 std(R29, offset, dst); offset += 8;
740 std(R30, offset, dst); offset += 8;
741 std(R31, offset, dst); offset += 8;
742
743 stfd(F14, offset, dst); offset += 8;
744 stfd(F15, offset, dst); offset += 8;
745 stfd(F16, offset, dst); offset += 8;
746 stfd(F17, offset, dst); offset += 8;
747 stfd(F18, offset, dst); offset += 8;
748 stfd(F19, offset, dst); offset += 8;
749 stfd(F20, offset, dst); offset += 8;
750 stfd(F21, offset, dst); offset += 8;
751 stfd(F22, offset, dst); offset += 8;
752 stfd(F23, offset, dst); offset += 8;
753 stfd(F24, offset, dst); offset += 8;
754 stfd(F25, offset, dst); offset += 8;
755 stfd(F26, offset, dst); offset += 8;
756 stfd(F27, offset, dst); offset += 8;
757 stfd(F28, offset, dst); offset += 8;
758 stfd(F29, offset, dst); offset += 8;
759 stfd(F30, offset, dst); offset += 8;
760 stfd(F31, offset, dst);
761 }
762
763 // Uses ordering which corresponds to ABI:
764 // _restgpr0_14: ld r14,-144(r1)
765 // _restgpr0_15: ld r15,-136(r1)
766 // _restgpr0_16: ld r16,-128(r1)
767 void MacroAssembler::restore_nonvolatile_gprs(Register src, int offset) {
768 ld(R14, offset, src); offset += 8;
769 ld(R15, offset, src); offset += 8;
770 ld(R16, offset, src); offset += 8;
771 ld(R17, offset, src); offset += 8;
772 ld(R18, offset, src); offset += 8;
773 ld(R19, offset, src); offset += 8;
774 ld(R20, offset, src); offset += 8;
775 ld(R21, offset, src); offset += 8;
776 ld(R22, offset, src); offset += 8;
777 ld(R23, offset, src); offset += 8;
778 ld(R24, offset, src); offset += 8;
779 ld(R25, offset, src); offset += 8;
780 ld(R26, offset, src); offset += 8;
781 ld(R27, offset, src); offset += 8;
782 ld(R28, offset, src); offset += 8;
783 ld(R29, offset, src); offset += 8;
784 ld(R30, offset, src); offset += 8;
785 ld(R31, offset, src); offset += 8;
786
787 // FP registers
788 lfd(F14, offset, src); offset += 8;
789 lfd(F15, offset, src); offset += 8;
790 lfd(F16, offset, src); offset += 8;
791 lfd(F17, offset, src); offset += 8;
792 lfd(F18, offset, src); offset += 8;
793 lfd(F19, offset, src); offset += 8;
794 lfd(F20, offset, src); offset += 8;
795 lfd(F21, offset, src); offset += 8;
796 lfd(F22, offset, src); offset += 8;
797 lfd(F23, offset, src); offset += 8;
798 lfd(F24, offset, src); offset += 8;
799 lfd(F25, offset, src); offset += 8;
800 lfd(F26, offset, src); offset += 8;
801 lfd(F27, offset, src); offset += 8;
802 lfd(F28, offset, src); offset += 8;
803 lfd(F29, offset, src); offset += 8;
804 lfd(F30, offset, src); offset += 8;
805 lfd(F31, offset, src);
806 }
807
808 // For verify_oops.
809 void MacroAssembler::save_volatile_gprs(Register dst, int offset) {
810 std(R3, offset, dst); offset += 8;
811 std(R4, offset, dst); offset += 8;
812 std(R5, offset, dst); offset += 8;
813 std(R6, offset, dst); offset += 8;
814 std(R7, offset, dst); offset += 8;
815 std(R8, offset, dst); offset += 8;
816 std(R9, offset, dst); offset += 8;
817 std(R10, offset, dst); offset += 8;
818 std(R11, offset, dst); offset += 8;
819 std(R12, offset, dst);
820 }
821
822 // For verify_oops.
823 void MacroAssembler::restore_volatile_gprs(Register src, int offset) {
824 ld(R3, offset, src); offset += 8;
825 ld(R4, offset, src); offset += 8;
826 ld(R5, offset, src); offset += 8;
827 ld(R6, offset, src); offset += 8;
828 ld(R7, offset, src); offset += 8;
829 ld(R8, offset, src); offset += 8;
830 ld(R9, offset, src); offset += 8;
831 ld(R10, offset, src); offset += 8;
832 ld(R11, offset, src); offset += 8;
833 ld(R12, offset, src);
834 }
835
836 void MacroAssembler::save_LR_CR(Register tmp) {
837 mfcr(tmp);
838 std(tmp, _abi(cr), R1_SP);
839 mflr(tmp);
840 std(tmp, _abi(lr), R1_SP);
841 // Tmp must contain lr on exit! (see return_addr and prolog in ppc64.ad)
842 }
843
844 void MacroAssembler::restore_LR_CR(Register tmp) {
845 assert(tmp != R1_SP, "must be distinct");
846 ld(tmp, _abi(lr), R1_SP);
847 mtlr(tmp);
848 ld(tmp, _abi(cr), R1_SP);
849 mtcr(tmp);
850 }
851
852 address MacroAssembler::get_PC_trash_LR(Register result) {
853 Label L;
854 bl(L);
855 bind(L);
856 address lr_pc = pc();
857 mflr(result);
858 return lr_pc;
859 }
860
861 void MacroAssembler::resize_frame(Register offset, Register tmp) {
862 #ifdef ASSERT
863 assert_different_registers(offset, tmp, R1_SP);
864 andi_(tmp, offset, frame::alignment_in_bytes-1);
865 asm_assert_eq("resize_frame: unaligned", 0x204);
866 #endif
867
868 // tmp <- *(SP)
869 ld(tmp, _abi(callers_sp), R1_SP);
870 // addr <- SP + offset;
871 // *(addr) <- tmp;
872 // SP <- addr
873 stdux(tmp, R1_SP, offset);
874 }
875
876 void MacroAssembler::resize_frame(int offset, Register tmp) {
877 assert(is_simm(offset, 16), "too big an offset");
878 assert_different_registers(tmp, R1_SP);
879 assert((offset & (frame::alignment_in_bytes-1))==0, "resize_frame: unaligned");
880 // tmp <- *(SP)
881 ld(tmp, _abi(callers_sp), R1_SP);
882 // addr <- SP + offset;
883 // *(addr) <- tmp;
884 // SP <- addr
885 stdu(tmp, offset, R1_SP);
886 }
887
888 void MacroAssembler::resize_frame_absolute(Register addr, Register tmp1, Register tmp2) {
889 // (addr == tmp1) || (addr == tmp2) is allowed here!
890 assert(tmp1 != tmp2, "must be distinct");
891
892 // compute offset w.r.t. current stack pointer
893 // tmp_1 <- addr - SP (!)
894 subf(tmp1, R1_SP, addr);
895
896 // atomically update SP keeping back link.
897 resize_frame(tmp1/* offset */, tmp2/* tmp */);
898 }
899
900 void MacroAssembler::push_frame(Register bytes, Register tmp) {
901 #ifdef ASSERT
902 assert(bytes != R0, "r0 not allowed here");
903 andi_(R0, bytes, frame::alignment_in_bytes-1);
904 asm_assert_eq("push_frame(Reg, Reg): unaligned", 0x203);
905 #endif
906 neg(tmp, bytes);
907 stdux(R1_SP, R1_SP, tmp);
908 }
909
910 // Push a frame of size `bytes'.
911 void MacroAssembler::push_frame(unsigned int bytes, Register tmp) {
912 long offset = align_addr(bytes, frame::alignment_in_bytes);
913 if (is_simm(-offset, 16)) {
914 stdu(R1_SP, -offset, R1_SP);
915 } else {
916 load_const(tmp, -offset);
917 stdux(R1_SP, R1_SP, tmp);
918 }
919 }
920
921 // Push a frame of size `bytes' plus abi_reg_args on top.
922 void MacroAssembler::push_frame_reg_args(unsigned int bytes, Register tmp) {
923 push_frame(bytes + frame::abi_reg_args_size, tmp);
924 }
925
926 // Setup up a new C frame with a spill area for non-volatile GPRs and
927 // additional space for local variables.
928 void MacroAssembler::push_frame_reg_args_nonvolatiles(unsigned int bytes,
929 Register tmp) {
930 push_frame(bytes + frame::abi_reg_args_size + frame::spill_nonvolatiles_size, tmp);
931 }
932
933 // Pop current C frame.
934 void MacroAssembler::pop_frame() {
935 ld(R1_SP, _abi(callers_sp), R1_SP);
936 }
937
938 #if defined(ABI_ELFv2)
939 address MacroAssembler::branch_to(Register r_function_entry, bool and_link) {
940 // TODO(asmundak): make sure the caller uses R12 as function descriptor
941 // most of the times.
942 if (R12 != r_function_entry) {
943 mr(R12, r_function_entry);
944 }
945 mtctr(R12);
946 // Do a call or a branch.
947 if (and_link) {
948 bctrl();
949 } else {
950 bctr();
951 }
952 _last_calls_return_pc = pc();
953
954 return _last_calls_return_pc;
955 }
956
957 // Call a C function via a function descriptor and use full C
958 // calling conventions. Updates and returns _last_calls_return_pc.
959 address MacroAssembler::call_c(Register r_function_entry) {
960 return branch_to(r_function_entry, /*and_link=*/true);
961 }
962
963 // For tail calls: only branch, don't link, so callee returns to caller of this function.
964 address MacroAssembler::call_c_and_return_to_caller(Register r_function_entry) {
965 return branch_to(r_function_entry, /*and_link=*/false);
966 }
967
968 address MacroAssembler::call_c(address function_entry, relocInfo::relocType rt) {
969 load_const(R12, function_entry, R0);
970 return branch_to(R12, /*and_link=*/true);
971 }
972
973 #else
974 // Generic version of a call to C function via a function descriptor
975 // with variable support for C calling conventions (TOC, ENV, etc.).
976 // Updates and returns _last_calls_return_pc.
977 address MacroAssembler::branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
978 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee) {
979 // we emit standard ptrgl glue code here
980 assert((function_descriptor != R0), "function_descriptor cannot be R0");
981
982 // retrieve necessary entries from the function descriptor
983 ld(R0, in_bytes(FunctionDescriptor::entry_offset()), function_descriptor);
984 mtctr(R0);
985
986 if (load_toc_of_callee) {
987 ld(R2_TOC, in_bytes(FunctionDescriptor::toc_offset()), function_descriptor);
988 }
989 if (load_env_of_callee) {
990 ld(R11, in_bytes(FunctionDescriptor::env_offset()), function_descriptor);
991 } else if (load_toc_of_callee) {
992 li(R11, 0);
993 }
994
995 // do a call or a branch
996 if (and_link) {
997 bctrl();
998 } else {
999 bctr();
1000 }
1001 _last_calls_return_pc = pc();
1002
1003 return _last_calls_return_pc;
1004 }
1005
1006 // Call a C function via a function descriptor and use full C calling
1007 // conventions.
1008 // We don't use the TOC in generated code, so there is no need to save
1009 // and restore its value.
1010 address MacroAssembler::call_c(Register fd) {
1011 return branch_to(fd, /*and_link=*/true,
1012 /*save toc=*/false,
1013 /*restore toc=*/false,
1014 /*load toc=*/true,
1015 /*load env=*/true);
1016 }
1017
1018 address MacroAssembler::call_c_and_return_to_caller(Register fd) {
1019 return branch_to(fd, /*and_link=*/false,
1020 /*save toc=*/false,
1021 /*restore toc=*/false,
1022 /*load toc=*/true,
1023 /*load env=*/true);
1024 }
1025
1026 address MacroAssembler::call_c(const FunctionDescriptor* fd, relocInfo::relocType rt) {
1027 if (rt != relocInfo::none) {
1028 // this call needs to be relocatable
1029 if (!ReoptimizeCallSequences
1030 || (rt != relocInfo::runtime_call_type && rt != relocInfo::none)
1031 || fd == NULL // support code-size estimation
1032 || !fd->is_friend_function()
1033 || fd->entry() == NULL) {
1034 // it's not a friend function as defined by class FunctionDescriptor,
1035 // so do a full call-c here.
1036 load_const(R11, (address)fd, R0);
1037
1038 bool has_env = (fd != NULL && fd->env() != NULL);
1039 return branch_to(R11, /*and_link=*/true,
1040 /*save toc=*/false,
1041 /*restore toc=*/false,
1042 /*load toc=*/true,
1043 /*load env=*/has_env);
1044 } else {
1045 // It's a friend function. Load the entry point and don't care about
1046 // toc and env. Use an optimizable call instruction, but ensure the
1047 // same code-size as in the case of a non-friend function.
1048 nop();
1049 nop();
1050 nop();
1051 bl64_patchable(fd->entry(), rt);
1052 _last_calls_return_pc = pc();
1053 return _last_calls_return_pc;
1054 }
1055 } else {
1056 // This call does not need to be relocatable, do more aggressive
1057 // optimizations.
1058 if (!ReoptimizeCallSequences
1059 || !fd->is_friend_function()) {
1060 // It's not a friend function as defined by class FunctionDescriptor,
1061 // so do a full call-c here.
1062 load_const(R11, (address)fd, R0);
1063 return branch_to(R11, /*and_link=*/true,
1064 /*save toc=*/false,
1065 /*restore toc=*/false,
1066 /*load toc=*/true,
1067 /*load env=*/true);
1068 } else {
1069 // it's a friend function, load the entry point and don't care about
1070 // toc and env.
1071 address dest = fd->entry();
1072 if (is_within_range_of_b(dest, pc())) {
1073 bl(dest);
1074 } else {
1075 bl64_patchable(dest, rt);
1076 }
1077 _last_calls_return_pc = pc();
1078 return _last_calls_return_pc;
1079 }
1080 }
1081 }
1082
1083 // Call a C function. All constants needed reside in TOC.
1084 //
1085 // Read the address to call from the TOC.
1086 // Read env from TOC, if fd specifies an env.
1087 // Read new TOC from TOC.
1088 address MacroAssembler::call_c_using_toc(const FunctionDescriptor* fd,
1089 relocInfo::relocType rt, Register toc) {
1090 if (!ReoptimizeCallSequences
1091 || (rt != relocInfo::runtime_call_type && rt != relocInfo::none)
1092 || !fd->is_friend_function()) {
1093 // It's not a friend function as defined by class FunctionDescriptor,
1094 // so do a full call-c here.
1095 assert(fd->entry() != NULL, "function must be linked");
1096
1097 AddressLiteral fd_entry(fd->entry());
1098 load_const_from_method_toc(R11, fd_entry, toc);
1099 mtctr(R11);
1100 if (fd->env() == NULL) {
1101 li(R11, 0);
1102 nop();
1103 } else {
1104 AddressLiteral fd_env(fd->env());
1105 load_const_from_method_toc(R11, fd_env, toc);
1106 }
1107 AddressLiteral fd_toc(fd->toc());
1108 load_toc_from_toc(R2_TOC, fd_toc, toc);
1109 // R2_TOC is killed.
1110 bctrl();
1111 _last_calls_return_pc = pc();
1112 } else {
1113 // It's a friend function, load the entry point and don't care about
1114 // toc and env. Use an optimizable call instruction, but ensure the
1115 // same code-size as in the case of a non-friend function.
1116 nop();
1117 bl64_patchable(fd->entry(), rt);
1118 _last_calls_return_pc = pc();
1119 }
1120 return _last_calls_return_pc;
1121 }
1122 #endif // ABI_ELFv2
1123
1124 void MacroAssembler::call_VM_base(Register oop_result,
1125 Register last_java_sp,
1126 address entry_point,
1127 bool check_exceptions) {
1128 BLOCK_COMMENT("call_VM {");
1129 // Determine last_java_sp register.
1130 if (!last_java_sp->is_valid()) {
1131 last_java_sp = R1_SP;
1132 }
1133 set_top_ijava_frame_at_SP_as_last_Java_frame(last_java_sp, R11_scratch1);
1134
1135 // ARG1 must hold thread address.
1136 mr(R3_ARG1, R16_thread);
1137 #if defined(ABI_ELFv2)
1138 address return_pc = call_c(entry_point, relocInfo::none);
1139 #else
1140 address return_pc = call_c((FunctionDescriptor*)entry_point, relocInfo::none);
1141 #endif
1142
1143 reset_last_Java_frame();
1144
1145 // Check for pending exceptions.
1146 if (check_exceptions) {
1147 // We don't check for exceptions here.
1148 ShouldNotReachHere();
1149 }
1150
1151 // Get oop result if there is one and reset the value in the thread.
1152 if (oop_result->is_valid()) {
1153 get_vm_result(oop_result);
1154 }
1155
1156 _last_calls_return_pc = return_pc;
1157 BLOCK_COMMENT("} call_VM");
1158 }
1159
1160 void MacroAssembler::call_VM_leaf_base(address entry_point) {
1161 BLOCK_COMMENT("call_VM_leaf {");
1162 #if defined(ABI_ELFv2)
1163 call_c(entry_point, relocInfo::none);
1164 #else
1165 call_c(CAST_FROM_FN_PTR(FunctionDescriptor*, entry_point), relocInfo::none);
1166 #endif
1167 BLOCK_COMMENT("} call_VM_leaf");
1168 }
1169
1170 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
1171 call_VM_base(oop_result, noreg, entry_point, check_exceptions);
1172 }
1173
1174 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1,
1175 bool check_exceptions) {
1176 // R3_ARG1 is reserved for the thread.
1177 mr_if_needed(R4_ARG2, arg_1);
1178 call_VM(oop_result, entry_point, check_exceptions);
1179 }
1180
1181 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
1182 bool check_exceptions) {
1183 // R3_ARG1 is reserved for the thread
1184 mr_if_needed(R4_ARG2, arg_1);
1185 assert(arg_2 != R4_ARG2, "smashed argument");
1186 mr_if_needed(R5_ARG3, arg_2);
1187 call_VM(oop_result, entry_point, check_exceptions);
1188 }
1189
1190 void MacroAssembler::call_VM_leaf(address entry_point) {
1191 call_VM_leaf_base(entry_point);
1192 }
1193
1194 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
1195 mr_if_needed(R3_ARG1, arg_1);
1196 call_VM_leaf(entry_point);
1197 }
1198
1199 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
1200 mr_if_needed(R3_ARG1, arg_1);
1201 assert(arg_2 != R3_ARG1, "smashed argument");
1202 mr_if_needed(R4_ARG2, arg_2);
1203 call_VM_leaf(entry_point);
1204 }
1205
1206 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
1207 mr_if_needed(R3_ARG1, arg_1);
1208 assert(arg_2 != R3_ARG1, "smashed argument");
1209 mr_if_needed(R4_ARG2, arg_2);
1210 assert(arg_3 != R3_ARG1 && arg_3 != R4_ARG2, "smashed argument");
1211 mr_if_needed(R5_ARG3, arg_3);
1212 call_VM_leaf(entry_point);
1213 }
1214
1215 // Check whether instruction is a read access to the polling page
1216 // which was emitted by load_from_polling_page(..).
1217 bool MacroAssembler::is_load_from_polling_page(int instruction, void* ucontext,
1218 address* polling_address_ptr) {
1219 if (!is_ld(instruction))
1220 return false; // It's not a ld. Fail.
1221
1222 int rt = inv_rt_field(instruction);
1223 int ra = inv_ra_field(instruction);
1224 int ds = inv_ds_field(instruction);
1225 if (!(ds == 0 && ra != 0 && rt == 0)) {
1226 return false; // It's not a ld(r0, X, ra). Fail.
1227 }
1228
1229 if (!ucontext) {
1230 // Set polling address.
1231 if (polling_address_ptr != NULL) {
1232 *polling_address_ptr = NULL;
1233 }
1234 return true; // No ucontext given. Can't check value of ra. Assume true.
1235 }
1236
1237 #ifdef LINUX
1238 // Ucontext given. Check that register ra contains the address of
1239 // the safepoing polling page.
1240 ucontext_t* uc = (ucontext_t*) ucontext;
1241 // Set polling address.
1242 address addr = (address)uc->uc_mcontext.regs->gpr[ra] + (ssize_t)ds;
1243 if (polling_address_ptr != NULL) {
1244 *polling_address_ptr = addr;
1245 }
1246 return os::is_poll_address(addr);
1247 #else
1248 // Not on Linux, ucontext must be NULL.
1249 ShouldNotReachHere();
1250 return false;
1251 #endif
1252 }
1253
1254 bool MacroAssembler::is_memory_serialization(int instruction, JavaThread* thread, void* ucontext) {
1255 #ifdef LINUX
1256 ucontext_t* uc = (ucontext_t*) ucontext;
1257
1258 if (is_stwx(instruction) || is_stwux(instruction)) {
1259 int ra = inv_ra_field(instruction);
1260 int rb = inv_rb_field(instruction);
1261
1262 // look up content of ra and rb in ucontext
1263 address ra_val=(address)uc->uc_mcontext.regs->gpr[ra];
1264 long rb_val=(long)uc->uc_mcontext.regs->gpr[rb];
1265 return os::is_memory_serialize_page(thread, ra_val+rb_val);
1266 } else if (is_stw(instruction) || is_stwu(instruction)) {
1267 int ra = inv_ra_field(instruction);
1268 int d1 = inv_d1_field(instruction);
1269
1270 // look up content of ra in ucontext
1271 address ra_val=(address)uc->uc_mcontext.regs->gpr[ra];
1272 return os::is_memory_serialize_page(thread, ra_val+d1);
1273 } else {
1274 return false;
1275 }
1276 #else
1277 // workaround not needed on !LINUX :-)
1278 ShouldNotCallThis();
1279 return false;
1280 #endif
1281 }
1282
1283 void MacroAssembler::bang_stack_with_offset(int offset) {
1284 // When increasing the stack, the old stack pointer will be written
1285 // to the new top of stack according to the PPC64 abi.
1286 // Therefore, stack banging is not necessary when increasing
1287 // the stack by <= os::vm_page_size() bytes.
1288 // When increasing the stack by a larger amount, this method is
1289 // called repeatedly to bang the intermediate pages.
1290
1291 // Stack grows down, caller passes positive offset.
1292 assert(offset > 0, "must bang with positive offset");
1293
1294 long stdoffset = -offset;
1295
1296 if (is_simm(stdoffset, 16)) {
1297 // Signed 16 bit offset, a simple std is ok.
1298 if (UseLoadInstructionsForStackBangingPPC64) {
1299 ld(R0, (int)(signed short)stdoffset, R1_SP);
1300 } else {
1301 std(R0,(int)(signed short)stdoffset, R1_SP);
1302 }
1303 } else if (is_simm(stdoffset, 31)) {
1304 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1305 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1306
1307 Register tmp = R11;
1308 addis(tmp, R1_SP, hi);
1309 if (UseLoadInstructionsForStackBangingPPC64) {
1310 ld(R0, lo, tmp);
1311 } else {
1312 std(R0, lo, tmp);
1313 }
1314 } else {
1315 ShouldNotReachHere();
1316 }
1317 }
1318
1319 // If instruction is a stack bang of the form
1320 // std R0, x(Ry), (see bang_stack_with_offset())
1321 // stdu R1_SP, x(R1_SP), (see push_frame(), resize_frame())
1322 // or stdux R1_SP, Rx, R1_SP (see push_frame(), resize_frame())
1323 // return the banged address. Otherwise, return 0.
1324 address MacroAssembler::get_stack_bang_address(int instruction, void *ucontext) {
1325 #ifdef LINUX
1326 ucontext_t* uc = (ucontext_t*) ucontext;
1327 int rs = inv_rs_field(instruction);
1328 int ra = inv_ra_field(instruction);
1329 if ( (is_ld(instruction) && rs == 0 && UseLoadInstructionsForStackBangingPPC64)
1330 || (is_std(instruction) && rs == 0 && !UseLoadInstructionsForStackBangingPPC64)
1331 || (is_stdu(instruction) && rs == 1)) {
1332 int ds = inv_ds_field(instruction);
1333 // return banged address
1334 return ds+(address)uc->uc_mcontext.regs->gpr[ra];
1335 } else if (is_stdux(instruction) && rs == 1) {
1336 int rb = inv_rb_field(instruction);
1337 address sp = (address)uc->uc_mcontext.regs->gpr[1];
1338 long rb_val = (long)uc->uc_mcontext.regs->gpr[rb];
1339 return ra != 1 || rb_val >= 0 ? NULL // not a stack bang
1340 : sp + rb_val; // banged address
1341 }
1342 return NULL; // not a stack bang
1343 #else
1344 // workaround not needed on !LINUX :-)
1345 ShouldNotCallThis();
1346 return NULL;
1347 #endif
1348 }
1349
1350 // CmpxchgX sets condition register to cmpX(current, compare).
1351 void MacroAssembler::cmpxchgw(ConditionRegister flag, Register dest_current_value,
1352 Register compare_value, Register exchange_value,
1353 Register addr_base, int semantics, bool cmpxchgx_hint,
1354 Register int_flag_success, bool contention_hint) {
1355 Label retry;
1356 Label failed;
1357 Label done;
1358
1359 // Save one branch if result is returned via register and
1360 // result register is different from the other ones.
1361 bool use_result_reg = (int_flag_success != noreg);
1362 bool preset_result_reg = (int_flag_success != dest_current_value && int_flag_success != compare_value &&
1363 int_flag_success != exchange_value && int_flag_success != addr_base);
1364
1365 // release/fence semantics
1366 if (semantics & MemBarRel) {
1367 release();
1368 }
1369
1370 if (use_result_reg && preset_result_reg) {
1371 li(int_flag_success, 0); // preset (assume cas failed)
1372 }
1373
1374 // Add simple guard in order to reduce risk of starving under high contention (recommended by IBM).
1375 if (contention_hint) { // Don't try to reserve if cmp fails.
1376 lwz(dest_current_value, 0, addr_base);
1377 cmpw(flag, dest_current_value, compare_value);
1378 bne(flag, failed);
1379 }
1380
1381 // atomic emulation loop
1382 bind(retry);
1383
1384 lwarx(dest_current_value, addr_base, cmpxchgx_hint);
1385 cmpw(flag, dest_current_value, compare_value);
1386 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1387 bne_predict_not_taken(flag, failed);
1388 } else {
1389 bne( flag, failed);
1390 }
1391 // branch to done => (flag == ne), (dest_current_value != compare_value)
1392 // fall through => (flag == eq), (dest_current_value == compare_value)
1393
1394 stwcx_(exchange_value, addr_base);
1395 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1396 bne_predict_not_taken(CCR0, retry); // StXcx_ sets CCR0.
1397 } else {
1398 bne( CCR0, retry); // StXcx_ sets CCR0.
1399 }
1400 // fall through => (flag == eq), (dest_current_value == compare_value), (swapped)
1401
1402 // Result in register (must do this at the end because int_flag_success can be the
1403 // same register as one above).
1404 if (use_result_reg) {
1405 li(int_flag_success, 1);
1406 }
1407
1408 if (semantics & MemBarFenceAfter) {
1409 fence();
1410 } else if (semantics & MemBarAcq) {
1411 isync();
1412 }
1413
1414 if (use_result_reg && !preset_result_reg) {
1415 b(done);
1416 }
1417
1418 bind(failed);
1419 if (use_result_reg && !preset_result_reg) {
1420 li(int_flag_success, 0);
1421 }
1422
1423 bind(done);
1424 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
1425 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
1426 }
1427
1428 // Preforms atomic compare exchange:
1429 // if (compare_value == *addr_base)
1430 // *addr_base = exchange_value
1431 // int_flag_success = 1;
1432 // else
1433 // int_flag_success = 0;
1434 //
1435 // ConditionRegister flag = cmp(compare_value, *addr_base)
1436 // Register dest_current_value = *addr_base
1437 // Register compare_value Used to compare with value in memory
1438 // Register exchange_value Written to memory if compare_value == *addr_base
1439 // Register addr_base The memory location to compareXChange
1440 // Register int_flag_success Set to 1 if exchange_value was written to *addr_base
1441 //
1442 // To avoid the costly compare exchange the value is tested beforehand.
1443 // Several special cases exist to avoid that unnecessary information is generated.
1444 //
1445 void MacroAssembler::cmpxchgd(ConditionRegister flag,
1446 Register dest_current_value, Register compare_value, Register exchange_value,
1447 Register addr_base, int semantics, bool cmpxchgx_hint,
1448 Register int_flag_success, Label* failed_ext, bool contention_hint) {
1449 Label retry;
1450 Label failed_int;
1451 Label& failed = (failed_ext != NULL) ? *failed_ext : failed_int;
1452 Label done;
1453
1454 // Save one branch if result is returned via register and result register is different from the other ones.
1455 bool use_result_reg = (int_flag_success!=noreg);
1456 bool preset_result_reg = (int_flag_success!=dest_current_value && int_flag_success!=compare_value &&
1457 int_flag_success!=exchange_value && int_flag_success!=addr_base);
1458 assert(int_flag_success == noreg || failed_ext == NULL, "cannot have both");
1459
1460 // release/fence semantics
1461 if (semantics & MemBarRel) {
1462 release();
1463 }
1464
1465 if (use_result_reg && preset_result_reg) {
1466 li(int_flag_success, 0); // preset (assume cas failed)
1467 }
1468
1469 // Add simple guard in order to reduce risk of starving under high contention (recommended by IBM).
1470 if (contention_hint) { // Don't try to reserve if cmp fails.
1471 ld(dest_current_value, 0, addr_base);
1472 cmpd(flag, dest_current_value, compare_value);
1473 bne(flag, failed);
1474 }
1475
1476 // atomic emulation loop
1477 bind(retry);
1478
1479 ldarx(dest_current_value, addr_base, cmpxchgx_hint);
1480 cmpd(flag, dest_current_value, compare_value);
1481 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1482 bne_predict_not_taken(flag, failed);
1483 } else {
1484 bne( flag, failed);
1485 }
1486
1487 stdcx_(exchange_value, addr_base);
1488 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1489 bne_predict_not_taken(CCR0, retry); // stXcx_ sets CCR0
1490 } else {
1491 bne( CCR0, retry); // stXcx_ sets CCR0
1492 }
1493
1494 // result in register (must do this at the end because int_flag_success can be the same register as one above)
1495 if (use_result_reg) {
1496 li(int_flag_success, 1);
1497 }
1498
1499 // POWER6 doesn't need isync in CAS.
1500 // Always emit isync to be on the safe side.
1501 if (semantics & MemBarFenceAfter) {
1502 fence();
1503 } else if (semantics & MemBarAcq) {
1504 isync();
1505 }
1506
1507 if (use_result_reg && !preset_result_reg) {
1508 b(done);
1509 }
1510
1511 bind(failed_int);
1512 if (use_result_reg && !preset_result_reg) {
1513 li(int_flag_success, 0);
1514 }
1515
1516 bind(done);
1517 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
1518 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
1519 }
1520
1521 // Look up the method for a megamorphic invokeinterface call.
1522 // The target method is determined by <intf_klass, itable_index>.
1523 // The receiver klass is in recv_klass.
1524 // On success, the result will be in method_result, and execution falls through.
1525 // On failure, execution transfers to the given label.
1526 void MacroAssembler::lookup_interface_method(Register recv_klass,
1527 Register intf_klass,
1528 RegisterOrConstant itable_index,
1529 Register method_result,
1530 Register scan_temp,
1531 Register sethi_temp,
1532 Label& L_no_such_interface) {
1533 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
1534 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1535 "caller must use same register for non-constant itable index as for method");
1536
1537 // Compute start of first itableOffsetEntry (which is at the end of the vtable).
1538 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
1539 int itentry_off = itableMethodEntry::method_offset_in_bytes();
1540 int logMEsize = exact_log2(itableMethodEntry::size() * wordSize);
1541 int scan_step = itableOffsetEntry::size() * wordSize;
1542 int log_vte_size= exact_log2(vtableEntry::size() * wordSize);
1543
1544 lwz(scan_temp, InstanceKlass::vtable_length_offset() * wordSize, recv_klass);
1545 // %%% We should store the aligned, prescaled offset in the klassoop.
1546 // Then the next several instructions would fold away.
1547
1548 sldi(scan_temp, scan_temp, log_vte_size);
1549 addi(scan_temp, scan_temp, vtable_base);
1550 add(scan_temp, recv_klass, scan_temp);
1551
1552 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1553 if (itable_index.is_register()) {
1554 Register itable_offset = itable_index.as_register();
1555 sldi(itable_offset, itable_offset, logMEsize);
1556 if (itentry_off) addi(itable_offset, itable_offset, itentry_off);
1557 add(recv_klass, itable_offset, recv_klass);
1558 } else {
1559 long itable_offset = (long)itable_index.as_constant();
1560 load_const_optimized(sethi_temp, (itable_offset<<logMEsize)+itentry_off); // static address, no relocation
1561 add(recv_klass, sethi_temp, recv_klass);
1562 }
1563
1564 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
1565 // if (scan->interface() == intf) {
1566 // result = (klass + scan->offset() + itable_index);
1567 // }
1568 // }
1569 Label search, found_method;
1570
1571 for (int peel = 1; peel >= 0; peel--) {
1572 // %%%% Could load both offset and interface in one ldx, if they were
1573 // in the opposite order. This would save a load.
1574 ld(method_result, itableOffsetEntry::interface_offset_in_bytes(), scan_temp);
1575
1576 // Check that this entry is non-null. A null entry means that
1577 // the receiver class doesn't implement the interface, and wasn't the
1578 // same as when the caller was compiled.
1579 cmpd(CCR0, method_result, intf_klass);
1580
1581 if (peel) {
1582 beq(CCR0, found_method);
1583 } else {
1584 bne(CCR0, search);
1585 // (invert the test to fall through to found_method...)
1586 }
1587
1588 if (!peel) break;
1589
1590 bind(search);
1591
1592 cmpdi(CCR0, method_result, 0);
1593 beq(CCR0, L_no_such_interface);
1594 addi(scan_temp, scan_temp, scan_step);
1595 }
1596
1597 bind(found_method);
1598
1599 // Got a hit.
1600 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
1601 lwz(scan_temp, ito_offset, scan_temp);
1602 ldx(method_result, scan_temp, recv_klass);
1603 }
1604
1605 // virtual method calling
1606 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1607 RegisterOrConstant vtable_index,
1608 Register method_result) {
1609
1610 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg());
1611
1612 const int base = InstanceKlass::vtable_start_offset() * wordSize;
1613 assert(vtableEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1614
1615 if (vtable_index.is_register()) {
1616 sldi(vtable_index.as_register(), vtable_index.as_register(), LogBytesPerWord);
1617 add(recv_klass, vtable_index.as_register(), recv_klass);
1618 } else {
1619 addi(recv_klass, recv_klass, vtable_index.as_constant() << LogBytesPerWord);
1620 }
1621 ld(R19_method, base + vtableEntry::method_offset_in_bytes(), recv_klass);
1622 }
1623
1624 /////////////////////////////////////////// subtype checking ////////////////////////////////////////////
1625
1626 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1627 Register super_klass,
1628 Register temp1_reg,
1629 Register temp2_reg,
1630 Label& L_success,
1631 Label& L_failure) {
1632
1633 const Register check_cache_offset = temp1_reg;
1634 const Register cached_super = temp2_reg;
1635
1636 assert_different_registers(sub_klass, super_klass, check_cache_offset, cached_super);
1637
1638 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1639 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1640
1641 // If the pointers are equal, we are done (e.g., String[] elements).
1642 // This self-check enables sharing of secondary supertype arrays among
1643 // non-primary types such as array-of-interface. Otherwise, each such
1644 // type would need its own customized SSA.
1645 // We move this check to the front of the fast path because many
1646 // type checks are in fact trivially successful in this manner,
1647 // so we get a nicely predicted branch right at the start of the check.
1648 cmpd(CCR0, sub_klass, super_klass);
1649 beq(CCR0, L_success);
1650
1651 // Check the supertype display:
1652 lwz(check_cache_offset, sco_offset, super_klass);
1653 // The loaded value is the offset from KlassOopDesc.
1654
1655 ldx(cached_super, check_cache_offset, sub_klass);
1656 cmpd(CCR0, cached_super, super_klass);
1657 beq(CCR0, L_success);
1658
1659 // This check has worked decisively for primary supers.
1660 // Secondary supers are sought in the super_cache ('super_cache_addr').
1661 // (Secondary supers are interfaces and very deeply nested subtypes.)
1662 // This works in the same check above because of a tricky aliasing
1663 // between the super_cache and the primary super display elements.
1664 // (The 'super_check_addr' can address either, as the case requires.)
1665 // Note that the cache is updated below if it does not help us find
1666 // what we need immediately.
1667 // So if it was a primary super, we can just fail immediately.
1668 // Otherwise, it's the slow path for us (no success at this point).
1669
1670 cmpwi(CCR0, check_cache_offset, sc_offset);
1671 bne(CCR0, L_failure);
1672 // bind(slow_path); // fallthru
1673 }
1674
1675 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1676 Register super_klass,
1677 Register temp1_reg,
1678 Register temp2_reg,
1679 Label* L_success,
1680 Register result_reg) {
1681 const Register array_ptr = temp1_reg; // current value from cache array
1682 const Register temp = temp2_reg;
1683
1684 assert_different_registers(sub_klass, super_klass, array_ptr, temp);
1685
1686 int source_offset = in_bytes(Klass::secondary_supers_offset());
1687 int target_offset = in_bytes(Klass::secondary_super_cache_offset());
1688
1689 int length_offset = Array<Klass*>::length_offset_in_bytes();
1690 int base_offset = Array<Klass*>::base_offset_in_bytes();
1691
1692 Label hit, loop, failure, fallthru;
1693
1694 ld(array_ptr, source_offset, sub_klass);
1695
1696 //assert(4 == arrayOopDesc::length_length_in_bytes(), "precondition violated.");
1697 lwz(temp, length_offset, array_ptr);
1698 cmpwi(CCR0, temp, 0);
1699 beq(CCR0, result_reg!=noreg ? failure : fallthru); // length 0
1700
1701 mtctr(temp); // load ctr
1702
1703 bind(loop);
1704 // Oops in table are NO MORE compressed.
1705 ld(temp, base_offset, array_ptr);
1706 cmpd(CCR0, temp, super_klass);
1707 beq(CCR0, hit);
1708 addi(array_ptr, array_ptr, BytesPerWord);
1709 bdnz(loop);
1710
1711 bind(failure);
1712 if (result_reg!=noreg) li(result_reg, 1); // load non-zero result (indicates a miss)
1713 b(fallthru);
1714
1715 bind(hit);
1716 std(super_klass, target_offset, sub_klass); // save result to cache
1717 if (result_reg != noreg) li(result_reg, 0); // load zero result (indicates a hit)
1718 if (L_success != NULL) b(*L_success);
1719
1720 bind(fallthru);
1721 }
1722
1723 // Try fast path, then go to slow one if not successful
1724 void MacroAssembler::check_klass_subtype(Register sub_klass,
1725 Register super_klass,
1726 Register temp1_reg,
1727 Register temp2_reg,
1728 Label& L_success) {
1729 Label L_failure;
1730 check_klass_subtype_fast_path(sub_klass, super_klass, temp1_reg, temp2_reg, L_success, L_failure);
1731 check_klass_subtype_slow_path(sub_klass, super_klass, temp1_reg, temp2_reg, &L_success);
1732 bind(L_failure); // Fallthru if not successful.
1733 }
1734
1735 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
1736 Register temp_reg,
1737 Label& wrong_method_type) {
1738 assert_different_registers(mtype_reg, mh_reg, temp_reg);
1739 // Compare method type against that of the receiver.
1740 load_heap_oop_not_null(temp_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg), mh_reg);
1741 cmpd(CCR0, temp_reg, mtype_reg);
1742 bne(CCR0, wrong_method_type);
1743 }
1744
1745 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
1746 Register temp_reg,
1747 int extra_slot_offset) {
1748 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1749 int stackElementSize = Interpreter::stackElementSize;
1750 int offset = extra_slot_offset * stackElementSize;
1751 if (arg_slot.is_constant()) {
1752 offset += arg_slot.as_constant() * stackElementSize;
1753 return offset;
1754 } else {
1755 assert(temp_reg != noreg, "must specify");
1756 sldi(temp_reg, arg_slot.as_register(), exact_log2(stackElementSize));
1757 if (offset != 0)
1758 addi(temp_reg, temp_reg, offset);
1759 return temp_reg;
1760 }
1761 }
1762
1763 void MacroAssembler::biased_locking_enter(ConditionRegister cr_reg, Register obj_reg,
1764 Register mark_reg, Register temp_reg,
1765 Register temp2_reg, Label& done, Label* slow_case) {
1766 assert(UseBiasedLocking, "why call this otherwise?");
1767
1768 #ifdef ASSERT
1769 assert_different_registers(obj_reg, mark_reg, temp_reg, temp2_reg);
1770 #endif
1771
1772 Label cas_label;
1773
1774 // Branch to done if fast path fails and no slow_case provided.
1775 Label *slow_case_int = (slow_case != NULL) ? slow_case : &done;
1776
1777 // Biased locking
1778 // See whether the lock is currently biased toward our thread and
1779 // whether the epoch is still valid
1780 // Note that the runtime guarantees sufficient alignment of JavaThread
1781 // pointers to allow age to be placed into low bits
1782 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits,
1783 "biased locking makes assumptions about bit layout");
1784
1785 if (PrintBiasedLockingStatistics) {
1786 load_const(temp_reg, (address) BiasedLocking::total_entry_count_addr(), temp2_reg);
1787 lwz(temp2_reg, 0, temp_reg);
1788 addi(temp2_reg, temp2_reg, 1);
1789 stw(temp2_reg, 0, temp_reg);
1790 }
1791
1792 andi(temp_reg, mark_reg, markOopDesc::biased_lock_mask_in_place);
1793 cmpwi(cr_reg, temp_reg, markOopDesc::biased_lock_pattern);
1794 bne(cr_reg, cas_label);
1795
1796 load_klass(temp_reg, obj_reg);
1797
1798 load_const_optimized(temp2_reg, ~((int) markOopDesc::age_mask_in_place));
1799 ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
1800 orr(temp_reg, R16_thread, temp_reg);
1801 xorr(temp_reg, mark_reg, temp_reg);
1802 andr(temp_reg, temp_reg, temp2_reg);
1803 cmpdi(cr_reg, temp_reg, 0);
1804 if (PrintBiasedLockingStatistics) {
1805 Label l;
1806 bne(cr_reg, l);
1807 load_const(mark_reg, (address) BiasedLocking::biased_lock_entry_count_addr());
1808 lwz(temp2_reg, 0, mark_reg);
1809 addi(temp2_reg, temp2_reg, 1);
1810 stw(temp2_reg, 0, mark_reg);
1811 // restore mark_reg
1812 ld(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
1813 bind(l);
1814 }
1815 beq(cr_reg, done);
1816
1817 Label try_revoke_bias;
1818 Label try_rebias;
1819
1820 // At this point we know that the header has the bias pattern and
1821 // that we are not the bias owner in the current epoch. We need to
1822 // figure out more details about the state of the header in order to
1823 // know what operations can be legally performed on the object's
1824 // header.
1825
1826 // If the low three bits in the xor result aren't clear, that means
1827 // the prototype header is no longer biased and we have to revoke
1828 // the bias on this object.
1829 andi(temp2_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
1830 cmpwi(cr_reg, temp2_reg, 0);
1831 bne(cr_reg, try_revoke_bias);
1832
1833 // Biasing is still enabled for this data type. See whether the
1834 // epoch of the current bias is still valid, meaning that the epoch
1835 // bits of the mark word are equal to the epoch bits of the
1836 // prototype header. (Note that the prototype header's epoch bits
1837 // only change at a safepoint.) If not, attempt to rebias the object
1838 // toward the current thread. Note that we must be absolutely sure
1839 // that the current epoch is invalid in order to do this because
1840 // otherwise the manipulations it performs on the mark word are
1841 // illegal.
1842
1843 int shift_amount = 64 - markOopDesc::epoch_shift;
1844 // rotate epoch bits to right (little) end and set other bits to 0
1845 // [ big part | epoch | little part ] -> [ 0..0 | epoch ]
1846 rldicl_(temp2_reg, temp_reg, shift_amount, 64 - markOopDesc::epoch_bits);
1847 // branch if epoch bits are != 0, i.e. they differ, because the epoch has been incremented
1848 bne(CCR0, try_rebias);
1849
1850 // The epoch of the current bias is still valid but we know nothing
1851 // about the owner; it might be set or it might be clear. Try to
1852 // acquire the bias of the object using an atomic operation. If this
1853 // fails we will go in to the runtime to revoke the object's bias.
1854 // Note that we first construct the presumed unbiased header so we
1855 // don't accidentally blow away another thread's valid bias.
1856 andi(mark_reg, mark_reg, (markOopDesc::biased_lock_mask_in_place |
1857 markOopDesc::age_mask_in_place |
1858 markOopDesc::epoch_mask_in_place));
1859 orr(temp_reg, R16_thread, mark_reg);
1860
1861 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
1862
1863 // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
1864 fence(); // TODO: replace by MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq ?
1865 cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
1866 /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
1867 /*where=*/obj_reg,
1868 MacroAssembler::MemBarAcq,
1869 MacroAssembler::cmpxchgx_hint_acquire_lock(),
1870 noreg, slow_case_int); // bail out if failed
1871
1872 // If the biasing toward our thread failed, this means that
1873 // another thread succeeded in biasing it toward itself and we
1874 // need to revoke that bias. The revocation will occur in the
1875 // interpreter runtime in the slow case.
1876 if (PrintBiasedLockingStatistics) {
1877 load_const(temp_reg, (address) BiasedLocking::anonymously_biased_lock_entry_count_addr(), temp2_reg);
1878 lwz(temp2_reg, 0, temp_reg);
1879 addi(temp2_reg, temp2_reg, 1);
1880 stw(temp2_reg, 0, temp_reg);
1881 }
1882 b(done);
1883
1884 bind(try_rebias);
1885 // At this point we know the epoch has expired, meaning that the
1886 // current "bias owner", if any, is actually invalid. Under these
1887 // circumstances _only_, we are allowed to use the current header's
1888 // value as the comparison value when doing the cas to acquire the
1889 // bias in the current epoch. In other words, we allow transfer of
1890 // the bias from one thread to another directly in this situation.
1891 andi(temp_reg, mark_reg, markOopDesc::age_mask_in_place);
1892 orr(temp_reg, R16_thread, temp_reg);
1893 load_klass(temp2_reg, obj_reg);
1894 ld(temp2_reg, in_bytes(Klass::prototype_header_offset()), temp2_reg);
1895 orr(temp_reg, temp_reg, temp2_reg);
1896
1897 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
1898
1899 // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
1900 fence(); // TODO: replace by MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq ?
1901 cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
1902 /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
1903 /*where=*/obj_reg,
1904 MacroAssembler::MemBarAcq,
1905 MacroAssembler::cmpxchgx_hint_acquire_lock(),
1906 noreg, slow_case_int); // bail out if failed
1907
1908 // If the biasing toward our thread failed, this means that
1909 // another thread succeeded in biasing it toward itself and we
1910 // need to revoke that bias. The revocation will occur in the
1911 // interpreter runtime in the slow case.
1912 if (PrintBiasedLockingStatistics) {
1913 load_const(temp_reg, (address) BiasedLocking::rebiased_lock_entry_count_addr(), temp2_reg);
1914 lwz(temp2_reg, 0, temp_reg);
1915 addi(temp2_reg, temp2_reg, 1);
1916 stw(temp2_reg, 0, temp_reg);
1917 }
1918 b(done);
1919
1920 bind(try_revoke_bias);
1921 // The prototype mark in the klass doesn't have the bias bit set any
1922 // more, indicating that objects of this data type are not supposed
1923 // to be biased any more. We are going to try to reset the mark of
1924 // this object to the prototype value and fall through to the
1925 // CAS-based locking scheme. Note that if our CAS fails, it means
1926 // that another thread raced us for the privilege of revoking the
1927 // bias of this particular object, so it's okay to continue in the
1928 // normal locking code.
1929 load_klass(temp_reg, obj_reg);
1930 ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
1931 andi(temp2_reg, mark_reg, markOopDesc::age_mask_in_place);
1932 orr(temp_reg, temp_reg, temp2_reg);
1933
1934 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
1935
1936 // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
1937 fence(); // TODO: replace by MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq ?
1938 cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
1939 /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
1940 /*where=*/obj_reg,
1941 MacroAssembler::MemBarAcq,
1942 MacroAssembler::cmpxchgx_hint_acquire_lock());
1943
1944 // reload markOop in mark_reg before continuing with lightweight locking
1945 ld(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
1946
1947 // Fall through to the normal CAS-based lock, because no matter what
1948 // the result of the above CAS, some thread must have succeeded in
1949 // removing the bias bit from the object's header.
1950 if (PrintBiasedLockingStatistics) {
1951 Label l;
1952 bne(cr_reg, l);
1953 load_const(temp_reg, (address) BiasedLocking::revoked_lock_entry_count_addr(), temp2_reg);
1954 lwz(temp2_reg, 0, temp_reg);
1955 addi(temp2_reg, temp2_reg, 1);
1956 stw(temp2_reg, 0, temp_reg);
1957 bind(l);
1958 }
1959
1960 bind(cas_label);
1961 }
1962
1963 void MacroAssembler::biased_locking_exit (ConditionRegister cr_reg, Register mark_addr, Register temp_reg, Label& done) {
1964 // Check for biased locking unlock case, which is a no-op
1965 // Note: we do not have to check the thread ID for two reasons.
1966 // First, the interpreter checks for IllegalMonitorStateException at
1967 // a higher level. Second, if the bias was revoked while we held the
1968 // lock, the object could not be rebiased toward another thread, so
1969 // the bias bit would be clear.
1970
1971 ld(temp_reg, 0, mark_addr);
1972 andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
1973
1974 cmpwi(cr_reg, temp_reg, markOopDesc::biased_lock_pattern);
1975 beq(cr_reg, done);
1976 }
1977
1978 // "The box" is the space on the stack where we copy the object mark.
1979 void MacroAssembler::compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
1980 Register temp, Register displaced_header, Register current_header) {
1981 assert_different_registers(oop, box, temp, displaced_header, current_header);
1982 assert(flag != CCR0, "bad condition register");
1983 Label cont;
1984 Label object_has_monitor;
1985 Label cas_failed;
1986
1987 // Load markOop from object into displaced_header.
1988 ld(displaced_header, oopDesc::mark_offset_in_bytes(), oop);
1989
1990
1991 // Always do locking in runtime.
1992 if (EmitSync & 0x01) {
1993 cmpdi(flag, oop, 0); // Oop can't be 0 here => always false.
1994 return;
1995 }
1996
1997 if (UseBiasedLocking) {
1998 biased_locking_enter(flag, oop, displaced_header, temp, current_header, cont);
1999 }
2000
2001 // Handle existing monitor.
2002 if ((EmitSync & 0x02) == 0) {
2003 // The object has an existing monitor iff (mark & monitor_value) != 0.
2004 andi_(temp, displaced_header, markOopDesc::monitor_value);
2005 bne(CCR0, object_has_monitor);
2006 }
2007
2008 // Set displaced_header to be (markOop of object | UNLOCK_VALUE).
2009 ori(displaced_header, displaced_header, markOopDesc::unlocked_value);
2010
2011 // Load Compare Value application register.
2012
2013 // Initialize the box. (Must happen before we update the object mark!)
2014 std(displaced_header, BasicLock::displaced_header_offset_in_bytes(), box);
2015
2016 // Must fence, otherwise, preceding store(s) may float below cmpxchg.
2017 // Compare object markOop with mark and if equal exchange scratch1 with object markOop.
2018 // CmpxchgX sets cr_reg to cmpX(current, displaced).
2019 membar(Assembler::StoreStore);
2020 cmpxchgd(/*flag=*/flag,
2021 /*current_value=*/current_header,
2022 /*compare_value=*/displaced_header,
2023 /*exchange_value=*/box,
2024 /*where=*/oop,
2025 MacroAssembler::MemBarAcq,
2026 MacroAssembler::cmpxchgx_hint_acquire_lock(),
2027 noreg,
2028 &cas_failed);
2029 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2030
2031 // If the compare-and-exchange succeeded, then we found an unlocked
2032 // object and we have now locked it.
2033 b(cont);
2034
2035 bind(cas_failed);
2036 // We did not see an unlocked object so try the fast recursive case.
2037
2038 // Check if the owner is self by comparing the value in the markOop of object
2039 // (current_header) with the stack pointer.
2040 sub(current_header, current_header, R1_SP);
2041 load_const_optimized(temp, (address) (~(os::vm_page_size()-1) |
2042 markOopDesc::lock_mask_in_place));
2043
2044 and_(R0/*==0?*/, current_header, temp);
2045 // If condition is true we are cont and hence we can store 0 as the
2046 // displaced header in the box, which indicates that it is a recursive lock.
2047 mcrf(flag,CCR0);
2048 std(R0/*==0, perhaps*/, BasicLock::displaced_header_offset_in_bytes(), box);
2049
2050 // Handle existing monitor.
2051 if ((EmitSync & 0x02) == 0) {
2052 b(cont);
2053
2054 bind(object_has_monitor);
2055 // The object's monitor m is unlocked iff m->owner == NULL,
2056 // otherwise m->owner may contain a thread or a stack address.
2057 //
2058 // Try to CAS m->owner from NULL to current thread.
2059 addi(temp, displaced_header, ObjectMonitor::owner_offset_in_bytes()-markOopDesc::monitor_value);
2060 li(displaced_header, 0);
2061 // CmpxchgX sets flag to cmpX(current, displaced).
2062 cmpxchgd(/*flag=*/flag,
2063 /*current_value=*/current_header,
2064 /*compare_value=*/displaced_header,
2065 /*exchange_value=*/R16_thread,
2066 /*where=*/temp,
2067 MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq,
2068 MacroAssembler::cmpxchgx_hint_acquire_lock());
2069
2070 // Store a non-null value into the box.
2071 std(box, BasicLock::displaced_header_offset_in_bytes(), box);
2072
2073 # ifdef ASSERT
2074 bne(flag, cont);
2075 // We have acquired the monitor, check some invariants.
2076 addi(/*monitor=*/temp, temp, -ObjectMonitor::owner_offset_in_bytes());
2077 // Invariant 1: _recursions should be 0.
2078 //assert(ObjectMonitor::recursions_size_in_bytes() == 8, "unexpected size");
2079 asm_assert_mem8_is_zero(ObjectMonitor::recursions_offset_in_bytes(), temp,
2080 "monitor->_recursions should be 0", -1);
2081 // Invariant 2: OwnerIsThread shouldn't be 0.
2082 //assert(ObjectMonitor::OwnerIsThread_size_in_bytes() == 4, "unexpected size");
2083 //asm_assert_mem4_isnot_zero(ObjectMonitor::OwnerIsThread_offset_in_bytes(), temp,
2084 // "monitor->OwnerIsThread shouldn't be 0", -1);
2085 # endif
2086 }
2087
2088 bind(cont);
2089 // flag == EQ indicates success
2090 // flag == NE indicates failure
2091 }
2092
2093 void MacroAssembler::compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
2094 Register temp, Register displaced_header, Register current_header) {
2095 assert_different_registers(oop, box, temp, displaced_header, current_header);
2096 assert(flag != CCR0, "bad condition register");
2097 Label cont;
2098 Label object_has_monitor;
2099
2100 // Always do locking in runtime.
2101 if (EmitSync & 0x01) {
2102 cmpdi(flag, oop, 0); // Oop can't be 0 here => always false.
2103 return;
2104 }
2105
2106 if (UseBiasedLocking) {
2107 biased_locking_exit(flag, oop, current_header, cont);
2108 }
2109
2110 // Find the lock address and load the displaced header from the stack.
2111 ld(displaced_header, BasicLock::displaced_header_offset_in_bytes(), box);
2112
2113 // If the displaced header is 0, we have a recursive unlock.
2114 cmpdi(flag, displaced_header, 0);
2115 beq(flag, cont);
2116
2117 // Handle existing monitor.
2118 if ((EmitSync & 0x02) == 0) {
2119 // The object has an existing monitor iff (mark & monitor_value) != 0.
2120 ld(current_header, oopDesc::mark_offset_in_bytes(), oop);
2121 andi(temp, current_header, markOopDesc::monitor_value);
2122 cmpdi(flag, temp, 0);
2123 bne(flag, object_has_monitor);
2124 }
2125
2126
2127 // Check if it is still a light weight lock, this is is true if we see
2128 // the stack address of the basicLock in the markOop of the object.
2129 // Cmpxchg sets flag to cmpd(current_header, box).
2130 cmpxchgd(/*flag=*/flag,
2131 /*current_value=*/current_header,
2132 /*compare_value=*/box,
2133 /*exchange_value=*/displaced_header,
2134 /*where=*/oop,
2135 MacroAssembler::MemBarRel,
2136 MacroAssembler::cmpxchgx_hint_release_lock(),
2137 noreg,
2138 &cont);
2139
2140 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2141
2142 // Handle existing monitor.
2143 if ((EmitSync & 0x02) == 0) {
2144 b(cont);
2145
2146 bind(object_has_monitor);
2147 addi(current_header, current_header, -markOopDesc::monitor_value); // monitor
2148 ld(temp, ObjectMonitor::owner_offset_in_bytes(), current_header);
2149 ld(displaced_header, ObjectMonitor::recursions_offset_in_bytes(), current_header);
2150 xorr(temp, R16_thread, temp); // Will be 0 if we are the owner.
2151 orr(temp, temp, displaced_header); // Will be 0 if there are 0 recursions.
2152 cmpdi(flag, temp, 0);
2153 bne(flag, cont);
2154
2155 ld(temp, ObjectMonitor::EntryList_offset_in_bytes(), current_header);
2156 ld(displaced_header, ObjectMonitor::cxq_offset_in_bytes(), current_header);
2157 orr(temp, temp, displaced_header); // Will be 0 if both are 0.
2158 cmpdi(flag, temp, 0);
2159 bne(flag, cont);
2160 release();
2161 std(temp, ObjectMonitor::owner_offset_in_bytes(), current_header);
2162 }
2163
2164 bind(cont);
2165 // flag == EQ indicates success
2166 // flag == NE indicates failure
2167 }
2168
2169 // Write serialization page so VM thread can do a pseudo remote membar.
2170 // We use the current thread pointer to calculate a thread specific
2171 // offset to write to within the page. This minimizes bus traffic
2172 // due to cache line collision.
2173 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
2174 srdi(tmp2, thread, os::get_serialize_page_shift_count());
2175
2176 int mask = os::vm_page_size() - sizeof(int);
2177 if (Assembler::is_simm(mask, 16)) {
2178 andi(tmp2, tmp2, mask);
2179 } else {
2180 lis(tmp1, (int)((signed short) (mask >> 16)));
2181 ori(tmp1, tmp1, mask & 0x0000ffff);
2182 andr(tmp2, tmp2, tmp1);
2183 }
2184
2185 load_const(tmp1, (long) os::get_memory_serialize_page());
2186 release();
2187 stwx(R0, tmp1, tmp2);
2188 }
2189
2190
2191 // GC barrier helper macros
2192
2193 // Write the card table byte if needed.
2194 void MacroAssembler::card_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp) {
2195 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
2196 assert(bs->kind() == BarrierSet::CardTableModRef ||
2197 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
2198 #ifdef ASSERT
2199 cmpdi(CCR0, Rnew_val, 0);
2200 asm_assert_ne("null oop not allowed", 0x321);
2201 #endif
2202 card_table_write(bs->byte_map_base, Rtmp, Rstore_addr);
2203 }
2204
2205 // Write the card table byte.
2206 void MacroAssembler::card_table_write(jbyte* byte_map_base, Register Rtmp, Register Robj) {
2207 assert_different_registers(Robj, Rtmp, R0);
2208 load_const_optimized(Rtmp, (address)byte_map_base, R0);
2209 srdi(Robj, Robj, CardTableModRefBS::card_shift);
2210 li(R0, 0); // dirty
2211 if (UseConcMarkSweepGC) membar(Assembler::StoreStore);
2212 stbx(R0, Rtmp, Robj);
2213 }
2214
2215 #if INCLUDE_ALL_GCS
2216 // General G1 pre-barrier generator.
2217 // Goal: record the previous value if it is not null.
2218 void MacroAssembler::g1_write_barrier_pre(Register Robj, RegisterOrConstant offset, Register Rpre_val,
2219 Register Rtmp1, Register Rtmp2, bool needs_frame) {
2220 Label runtime, filtered;
2221
2222 // Is marking active?
2223 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
2224 lwz(Rtmp1, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_active()), R16_thread);
2225 } else {
2226 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
2227 lbz(Rtmp1, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_active()), R16_thread);
2228 }
2229 cmpdi(CCR0, Rtmp1, 0);
2230 beq(CCR0, filtered);
2231
2232 // Do we need to load the previous value?
2233 if (Robj != noreg) {
2234 // Load the previous value...
2235 if (UseCompressedOops) {
2236 lwz(Rpre_val, offset, Robj);
2237 } else {
2238 ld(Rpre_val, offset, Robj);
2239 }
2240 // Previous value has been loaded into Rpre_val.
2241 }
2242 assert(Rpre_val != noreg, "must have a real register");
2243
2244 // Is the previous value null?
2245 cmpdi(CCR0, Rpre_val, 0);
2246 beq(CCR0, filtered);
2247
2248 if (Robj != noreg && UseCompressedOops) {
2249 decode_heap_oop_not_null(Rpre_val);
2250 }
2251
2252 // OK, it's not filtered, so we'll need to call enqueue. In the normal
2253 // case, pre_val will be a scratch G-reg, but there are some cases in
2254 // which it's an O-reg. In the first case, do a normal call. In the
2255 // latter, do a save here and call the frameless version.
2256
2257 // Can we store original value in the thread's buffer?
2258 // Is index == 0?
2259 // (The index field is typed as size_t.)
2260 const Register Rbuffer = Rtmp1, Rindex = Rtmp2;
2261
2262 ld(Rindex, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2263 cmpdi(CCR0, Rindex, 0);
2264 beq(CCR0, runtime); // If index == 0, goto runtime.
2265 ld(Rbuffer, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_buf()), R16_thread);
2266
2267 addi(Rindex, Rindex, -wordSize); // Decrement index.
2268 std(Rindex, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2269
2270 // Record the previous value.
2271 stdx(Rpre_val, Rbuffer, Rindex);
2272 b(filtered);
2273
2274 bind(runtime);
2275
2276 // VM call need frame to access(write) O register.
2277 if (needs_frame) {
2278 save_LR_CR(Rtmp1);
2279 push_frame_reg_args(0, Rtmp2);
2280 }
2281
2282 if (Rpre_val->is_volatile() && Robj == noreg) mr(R31, Rpre_val); // Save pre_val across C call if it was preloaded.
2283 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), Rpre_val, R16_thread);
2284 if (Rpre_val->is_volatile() && Robj == noreg) mr(Rpre_val, R31); // restore
2285
2286 if (needs_frame) {
2287 pop_frame();
2288 restore_LR_CR(Rtmp1);
2289 }
2290
2291 bind(filtered);
2292 }
2293
2294 // General G1 post-barrier generator
2295 // Store cross-region card.
2296 void MacroAssembler::g1_write_barrier_post(Register Rstore_addr, Register Rnew_val, Register Rtmp1, Register Rtmp2, Register Rtmp3, Label *filtered_ext) {
2297 Label runtime, filtered_int;
2298 Label& filtered = (filtered_ext != NULL) ? *filtered_ext : filtered_int;
2299 assert_different_registers(Rstore_addr, Rnew_val, Rtmp1, Rtmp2);
2300
2301 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
2302 assert(bs->kind() == BarrierSet::G1SATBCT ||
2303 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
2304
2305 // Does store cross heap regions?
2306 if (G1RSBarrierRegionFilter) {
2307 xorr(Rtmp1, Rstore_addr, Rnew_val);
2308 srdi_(Rtmp1, Rtmp1, HeapRegion::LogOfHRGrainBytes);
2309 beq(CCR0, filtered);
2310 }
2311
2312 // Crosses regions, storing NULL?
2313 #ifdef ASSERT
2314 cmpdi(CCR0, Rnew_val, 0);
2315 asm_assert_ne("null oop not allowed (G1)", 0x322); // Checked by caller on PPC64, so following branch is obsolete:
2316 //beq(CCR0, filtered);
2317 #endif
2318
2319 // Storing region crossing non-NULL, is card already dirty?
2320 assert(sizeof(*bs->byte_map_base) == sizeof(jbyte), "adjust this code");
2321 const Register Rcard_addr = Rtmp1;
2322 Register Rbase = Rtmp2;
2323 load_const_optimized(Rbase, (address)bs->byte_map_base, /*temp*/ Rtmp3);
2324
2325 srdi(Rcard_addr, Rstore_addr, CardTableModRefBS::card_shift);
2326
2327 // Get the address of the card.
2328 lbzx(/*card value*/ Rtmp3, Rbase, Rcard_addr);
2329 cmpwi(CCR0, Rtmp3, (int)G1SATBCardTableModRefBS::g1_young_card_val());
2330 beq(CCR0, filtered);
2331
2332 membar(Assembler::StoreLoad);
2333 lbzx(/*card value*/ Rtmp3, Rbase, Rcard_addr); // Reload after membar.
2334 cmpwi(CCR0, Rtmp3 /* card value */, CardTableModRefBS::dirty_card_val());
2335 beq(CCR0, filtered);
2336
2337 // Storing a region crossing, non-NULL oop, card is clean.
2338 // Dirty card and log.
2339 li(Rtmp3, CardTableModRefBS::dirty_card_val());
2340 //release(); // G1: oops are allowed to get visible after dirty marking.
2341 stbx(Rtmp3, Rbase, Rcard_addr);
2342
2343 add(Rcard_addr, Rbase, Rcard_addr); // This is the address which needs to get enqueued.
2344 Rbase = noreg; // end of lifetime
2345
2346 const Register Rqueue_index = Rtmp2,
2347 Rqueue_buf = Rtmp3;
2348 ld(Rqueue_index, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2349 cmpdi(CCR0, Rqueue_index, 0);
2350 beq(CCR0, runtime); // index == 0 then jump to runtime
2351 ld(Rqueue_buf, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_buf()), R16_thread);
2352
2353 addi(Rqueue_index, Rqueue_index, -wordSize); // decrement index
2354 std(Rqueue_index, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_index()), R16_thread);
2355
2356 stdx(Rcard_addr, Rqueue_buf, Rqueue_index); // store card
2357 b(filtered);
2358
2359 bind(runtime);
2360
2361 // Save the live input values.
2362 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), Rcard_addr, R16_thread);
2363
2364 bind(filtered_int);
2365 }
2366 #endif // INCLUDE_ALL_GCS
2367
2368 // Values for last_Java_pc, and last_Java_sp must comply to the rules
2369 // in frame_ppc64.hpp.
2370 void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc) {
2371 // Always set last_Java_pc and flags first because once last_Java_sp
2372 // is visible has_last_Java_frame is true and users will look at the
2373 // rest of the fields. (Note: flags should always be zero before we
2374 // get here so doesn't need to be set.)
2375
2376 // Verify that last_Java_pc was zeroed on return to Java
2377 asm_assert_mem8_is_zero(in_bytes(JavaThread::last_Java_pc_offset()), R16_thread,
2378 "last_Java_pc not zeroed before leaving Java", 0x200);
2379
2380 // When returning from calling out from Java mode the frame anchor's
2381 // last_Java_pc will always be set to NULL. It is set here so that
2382 // if we are doing a call to native (not VM) that we capture the
2383 // known pc and don't have to rely on the native call having a
2384 // standard frame linkage where we can find the pc.
2385 if (last_Java_pc != noreg)
2386 std(last_Java_pc, in_bytes(JavaThread::last_Java_pc_offset()), R16_thread);
2387
2388 // Set last_Java_sp last.
2389 std(last_Java_sp, in_bytes(JavaThread::last_Java_sp_offset()), R16_thread);
2390 }
2391
2392 void MacroAssembler::reset_last_Java_frame(void) {
2393 asm_assert_mem8_isnot_zero(in_bytes(JavaThread::last_Java_sp_offset()),
2394 R16_thread, "SP was not set, still zero", 0x202);
2395
2396 BLOCK_COMMENT("reset_last_Java_frame {");
2397 li(R0, 0);
2398
2399 // _last_Java_sp = 0
2400 std(R0, in_bytes(JavaThread::last_Java_sp_offset()), R16_thread);
2401
2402 // _last_Java_pc = 0
2403 std(R0, in_bytes(JavaThread::last_Java_pc_offset()), R16_thread);
2404 BLOCK_COMMENT("} reset_last_Java_frame");
2405 }
2406
2407 void MacroAssembler::set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1) {
2408 assert_different_registers(sp, tmp1);
2409
2410 // sp points to a TOP_IJAVA_FRAME, retrieve frame's PC via
2411 // TOP_IJAVA_FRAME_ABI.
2412 // FIXME: assert that we really have a TOP_IJAVA_FRAME here!
2413 #ifdef CC_INTERP
2414 ld(tmp1/*pc*/, _top_ijava_frame_abi(frame_manager_lr), sp);
2415 #else
2416 address entry = pc();
2417 load_const_optimized(tmp1, entry);
2418 #endif
2419
2420 set_last_Java_frame(/*sp=*/sp, /*pc=*/tmp1);
2421 }
2422
2423 void MacroAssembler::get_vm_result(Register oop_result) {
2424 // Read:
2425 // R16_thread
2426 // R16_thread->in_bytes(JavaThread::vm_result_offset())
2427 //
2428 // Updated:
2429 // oop_result
2430 // R16_thread->in_bytes(JavaThread::vm_result_offset())
2431
2432 ld(oop_result, in_bytes(JavaThread::vm_result_offset()), R16_thread);
2433 li(R0, 0);
2434 std(R0, in_bytes(JavaThread::vm_result_offset()), R16_thread);
2435
2436 verify_oop(oop_result);
2437 }
2438
2439 void MacroAssembler::get_vm_result_2(Register metadata_result) {
2440 // Read:
2441 // R16_thread
2442 // R16_thread->in_bytes(JavaThread::vm_result_2_offset())
2443 //
2444 // Updated:
2445 // metadata_result
2446 // R16_thread->in_bytes(JavaThread::vm_result_2_offset())
2447
2448 ld(metadata_result, in_bytes(JavaThread::vm_result_2_offset()), R16_thread);
2449 li(R0, 0);
2450 std(R0, in_bytes(JavaThread::vm_result_2_offset()), R16_thread);
2451 }
2452
2453
2454 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
2455 Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided.
2456 if (Universe::narrow_klass_base() != 0) {
2457 // Use dst as temp if it is free.
2458 load_const(R0, Universe::narrow_klass_base(), (dst != current && dst != R0) ? dst : noreg);
2459 sub(dst, current, R0);
2460 current = dst;
2461 }
2462 if (Universe::narrow_klass_shift() != 0) {
2463 srdi(dst, current, Universe::narrow_klass_shift());
2464 current = dst;
2465 }
2466 mr_if_needed(dst, current); // Move may be required.
2467 }
2468
2469 void MacroAssembler::store_klass(Register dst_oop, Register klass, Register ck) {
2470 if (UseCompressedClassPointers) {
2471 encode_klass_not_null(ck, klass);
2472 stw(ck, oopDesc::klass_offset_in_bytes(), dst_oop);
2473 } else {
2474 std(klass, oopDesc::klass_offset_in_bytes(), dst_oop);
2475 }
2476 }
2477
2478 void MacroAssembler::store_klass_gap(Register dst_oop, Register val) {
2479 if (UseCompressedClassPointers) {
2480 if (val == noreg) {
2481 val = R0;
2482 li(val, 0);
2483 }
2484 stw(val, oopDesc::klass_gap_offset_in_bytes(), dst_oop); // klass gap if compressed
2485 }
2486 }
2487
2488 int MacroAssembler::instr_size_for_decode_klass_not_null() {
2489 if (!UseCompressedClassPointers) return 0;
2490 int num_instrs = 1; // shift or move
2491 if (Universe::narrow_klass_base() != 0) num_instrs = 7; // shift + load const + add
2492 return num_instrs * BytesPerInstWord;
2493 }
2494
2495 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
2496 if (src == noreg) src = dst;
2497 Register shifted_src = src;
2498 if (Universe::narrow_klass_shift() != 0 ||
2499 Universe::narrow_klass_base() == 0 && src != dst) { // Move required.
2500 shifted_src = dst;
2501 sldi(shifted_src, src, Universe::narrow_klass_shift());
2502 }
2503 if (Universe::narrow_klass_base() != 0) {
2504 load_const(R0, Universe::narrow_klass_base());
2505 add(dst, shifted_src, R0);
2506 }
2507 }
2508
2509 void MacroAssembler::load_klass(Register dst, Register src) {
2510 if (UseCompressedClassPointers) {
2511 lwz(dst, oopDesc::klass_offset_in_bytes(), src);
2512 // Attention: no null check here!
2513 decode_klass_not_null(dst, dst);
2514 } else {
2515 ld(dst, oopDesc::klass_offset_in_bytes(), src);
2516 }
2517 }
2518
2519 void MacroAssembler::load_klass_with_trap_null_check(Register dst, Register src) {
2520 if (!os::zero_page_read_protected()) {
2521 if (TrapBasedNullChecks) {
2522 trap_null_check(src);
2523 }
2524 }
2525 load_klass(dst, src);
2526 }
2527
2528 void MacroAssembler::reinit_heapbase(Register d, Register tmp) {
2529 if (Universe::heap() != NULL) {
2530 if (Universe::narrow_oop_base() == NULL) {
2531 Assembler::xorr(R30, R30, R30);
2532 } else {
2533 load_const(R30, Universe::narrow_ptrs_base(), tmp);
2534 }
2535 } else {
2536 load_const(R30, Universe::narrow_ptrs_base_addr(), tmp);
2537 ld(R30, 0, R30);
2538 }
2539 }
2540
2541 // Clear Array
2542 // Kills both input registers. tmp == R0 is allowed.
2543 void MacroAssembler::clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp) {
2544 // Procedure for large arrays (uses data cache block zero instruction).
2545 Label startloop, fast, fastloop, small_rest, restloop, done;
2546 const int cl_size = VM_Version::get_cache_line_size(),
2547 cl_dwords = cl_size>>3,
2548 cl_dw_addr_bits = exact_log2(cl_dwords),
2549 dcbz_min = 1; // Min count of dcbz executions, needs to be >0.
2550
2551 //2:
2552 cmpdi(CCR1, cnt_dwords, ((dcbz_min+1)<<cl_dw_addr_bits)-1); // Big enough? (ensure >=dcbz_min lines included).
2553 blt(CCR1, small_rest); // Too small.
2554 rldicl_(tmp, base_ptr, 64-3, 64-cl_dw_addr_bits); // Extract dword offset within first cache line.
2555 beq(CCR0, fast); // Already 128byte aligned.
2556
2557 subfic(tmp, tmp, cl_dwords);
2558 mtctr(tmp); // Set ctr to hit 128byte boundary (0<ctr<cl_dwords).
2559 subf(cnt_dwords, tmp, cnt_dwords); // rest.
2560 li(tmp, 0);
2561 //10:
2562 bind(startloop); // Clear at the beginning to reach 128byte boundary.
2563 std(tmp, 0, base_ptr); // Clear 8byte aligned block.
2564 addi(base_ptr, base_ptr, 8);
2565 bdnz(startloop);
2566 //13:
2567 bind(fast); // Clear 128byte blocks.
2568 srdi(tmp, cnt_dwords, cl_dw_addr_bits); // Loop count for 128byte loop (>0).
2569 andi(cnt_dwords, cnt_dwords, cl_dwords-1); // Rest in dwords.
2570 mtctr(tmp); // Load counter.
2571 //16:
2572 bind(fastloop);
2573 dcbz(base_ptr); // Clear 128byte aligned block.
2574 addi(base_ptr, base_ptr, cl_size);
2575 bdnz(fastloop);
2576 if (InsertEndGroupPPC64) { endgroup(); } else { nop(); }
2577 //20:
2578 bind(small_rest);
2579 cmpdi(CCR0, cnt_dwords, 0); // size 0?
2580 beq(CCR0, done); // rest == 0
2581 li(tmp, 0);
2582 mtctr(cnt_dwords); // Load counter.
2583 //24:
2584 bind(restloop); // Clear rest.
2585 std(tmp, 0, base_ptr); // Clear 8byte aligned block.
2586 addi(base_ptr, base_ptr, 8);
2587 bdnz(restloop);
2588 //27:
2589 bind(done);
2590 }
2591
2592 /////////////////////////////////////////// String intrinsics ////////////////////////////////////////////
2593
2594 // Search for a single jchar in an jchar[].
2595 //
2596 // Assumes that result differs from all other registers.
2597 //
2598 // Haystack, needle are the addresses of jchar-arrays.
2599 // NeedleChar is needle[0] if it is known at compile time.
2600 // Haycnt is the length of the haystack. We assume haycnt >=1.
2601 //
2602 // Preserves haystack, haycnt, kills all other registers.
2603 //
2604 // If needle == R0, we search for the constant needleChar.
2605 void MacroAssembler::string_indexof_1(Register result, Register haystack, Register haycnt,
2606 Register needle, jchar needleChar,
2607 Register tmp1, Register tmp2) {
2608
2609 assert_different_registers(result, haystack, haycnt, needle, tmp1, tmp2);
2610
2611 Label L_InnerLoop, L_FinalCheck, L_Found1, L_Found2, L_Found3, L_NotFound, L_End;
2612 Register needle0 = needle, // Contains needle[0].
2613 addr = tmp1,
2614 ch1 = tmp2,
2615 ch2 = R0;
2616
2617 //2 (variable) or 3 (const):
2618 if (needle != R0) lhz(needle0, 0, needle); // Preload needle character, needle has len==1.
2619 dcbtct(haystack, 0x00); // Indicate R/O access to haystack.
2620
2621 srwi_(tmp2, haycnt, 1); // Shift right by exact_log2(UNROLL_FACTOR).
2622 mr(addr, haystack);
2623 beq(CCR0, L_FinalCheck);
2624 mtctr(tmp2); // Move to count register.
2625 //8:
2626 bind(L_InnerLoop); // Main work horse (2x unrolled search loop).
2627 lhz(ch1, 0, addr); // Load characters from haystack.
2628 lhz(ch2, 2, addr);
2629 (needle != R0) ? cmpw(CCR0, ch1, needle0) : cmplwi(CCR0, ch1, needleChar);
2630 (needle != R0) ? cmpw(CCR1, ch2, needle0) : cmplwi(CCR1, ch2, needleChar);
2631 beq(CCR0, L_Found1); // Did we find the needle?
2632 beq(CCR1, L_Found2);
2633 addi(addr, addr, 4);
2634 bdnz(L_InnerLoop);
2635 //16:
2636 bind(L_FinalCheck);
2637 andi_(R0, haycnt, 1);
2638 beq(CCR0, L_NotFound);
2639 lhz(ch1, 0, addr); // One position left at which we have to compare.
2640 (needle != R0) ? cmpw(CCR1, ch1, needle0) : cmplwi(CCR1, ch1, needleChar);
2641 beq(CCR1, L_Found3);
2642 //21:
2643 bind(L_NotFound);
2644 li(result, -1); // Not found.
2645 b(L_End);
2646
2647 bind(L_Found2);
2648 addi(addr, addr, 2);
2649 //24:
2650 bind(L_Found1);
2651 bind(L_Found3); // Return index ...
2652 subf(addr, haystack, addr); // relative to haystack,
2653 srdi(result, addr, 1); // in characters.
2654 bind(L_End);
2655 }
2656
2657
2658 // Implementation of IndexOf for jchar arrays.
2659 //
2660 // The length of haystack and needle are not constant, i.e. passed in a register.
2661 //
2662 // Preserves registers haystack, needle.
2663 // Kills registers haycnt, needlecnt.
2664 // Assumes that result differs from all other registers.
2665 // Haystack, needle are the addresses of jchar-arrays.
2666 // Haycnt, needlecnt are the lengths of them, respectively.
2667 //
2668 // Needlecntval must be zero or 15-bit unsigned immediate and > 1.
2669 void MacroAssembler::string_indexof(Register result, Register haystack, Register haycnt,
2670 Register needle, ciTypeArray* needle_values, Register needlecnt, int needlecntval,
2671 Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
2672
2673 // Ensure 0<needlecnt<=haycnt in ideal graph as prerequisite!
2674 Label L_TooShort, L_Found, L_NotFound, L_End;
2675 Register last_addr = haycnt, // Kill haycnt at the beginning.
2676 addr = tmp1,
2677 n_start = tmp2,
2678 ch1 = tmp3,
2679 ch2 = R0;
2680
2681 // **************************************************************************************************
2682 // Prepare for main loop: optimized for needle count >=2, bail out otherwise.
2683 // **************************************************************************************************
2684
2685 //1 (variable) or 3 (const):
2686 dcbtct(needle, 0x00); // Indicate R/O access to str1.
2687 dcbtct(haystack, 0x00); // Indicate R/O access to str2.
2688
2689 // Compute last haystack addr to use if no match gets found.
2690 if (needlecntval == 0) { // variable needlecnt
2691 //3:
2692 subf(ch1, needlecnt, haycnt); // Last character index to compare is haycnt-needlecnt.
2693 addi(addr, haystack, -2); // Accesses use pre-increment.
2694 cmpwi(CCR6, needlecnt, 2);
2695 blt(CCR6, L_TooShort); // Variable needlecnt: handle short needle separately.
2696 slwi(ch1, ch1, 1); // Scale to number of bytes.
2697 lwz(n_start, 0, needle); // Load first 2 characters of needle.
2698 add(last_addr, haystack, ch1); // Point to last address to compare (haystack+2*(haycnt-needlecnt)).
2699 addi(needlecnt, needlecnt, -2); // Rest of needle.
2700 } else { // constant needlecnt
2701 guarantee(needlecntval != 1, "IndexOf with single-character needle must be handled separately");
2702 assert((needlecntval & 0x7fff) == needlecntval, "wrong immediate");
2703 //5:
2704 addi(ch1, haycnt, -needlecntval); // Last character index to compare is haycnt-needlecnt.
2705 lwz(n_start, 0, needle); // Load first 2 characters of needle.
2706 addi(addr, haystack, -2); // Accesses use pre-increment.
2707 slwi(ch1, ch1, 1); // Scale to number of bytes.
2708 add(last_addr, haystack, ch1); // Point to last address to compare (haystack+2*(haycnt-needlecnt)).
2709 li(needlecnt, needlecntval-2); // Rest of needle.
2710 }
2711
2712 // Main Loop (now we have at least 3 characters).
2713 //11:
2714 Label L_OuterLoop, L_InnerLoop, L_FinalCheck, L_Comp1, L_Comp2, L_Comp3;
2715 bind(L_OuterLoop); // Search for 1st 2 characters.
2716 Register addr_diff = tmp4;
2717 subf(addr_diff, addr, last_addr); // Difference between already checked address and last address to check.
2718 addi(addr, addr, 2); // This is the new address we want to use for comparing.
2719 srdi_(ch2, addr_diff, 2);
2720 beq(CCR0, L_FinalCheck); // 2 characters left?
2721 mtctr(ch2); // addr_diff/4
2722 //16:
2723 bind(L_InnerLoop); // Main work horse (2x unrolled search loop)
2724 lwz(ch1, 0, addr); // Load 2 characters of haystack (ignore alignment).
2725 lwz(ch2, 2, addr);
2726 cmpw(CCR0, ch1, n_start); // Compare 2 characters (1 would be sufficient but try to reduce branches to CompLoop).
2727 cmpw(CCR1, ch2, n_start);
2728 beq(CCR0, L_Comp1); // Did we find the needle start?
2729 beq(CCR1, L_Comp2);
2730 addi(addr, addr, 4);
2731 bdnz(L_InnerLoop);
2732 //24:
2733 bind(L_FinalCheck);
2734 rldicl_(addr_diff, addr_diff, 64-1, 63); // Remaining characters not covered by InnerLoop: (addr_diff>>1)&1.
2735 beq(CCR0, L_NotFound);
2736 lwz(ch1, 0, addr); // One position left at which we have to compare.
2737 cmpw(CCR1, ch1, n_start);
2738 beq(CCR1, L_Comp3);
2739 //29:
2740 bind(L_NotFound);
2741 li(result, -1); // not found
2742 b(L_End);
2743
2744
2745 // **************************************************************************************************
2746 // Special Case: unfortunately, the variable needle case can be called with needlecnt<2
2747 // **************************************************************************************************
2748 //31:
2749 if ((needlecntval>>1) !=1 ) { // Const needlecnt is 2 or 3? Reduce code size.
2750 int nopcnt = 5;
2751 if (needlecntval !=0 ) ++nopcnt; // Balance alignment (other case: see below).
2752 if (needlecntval == 0) { // We have to handle these cases separately.
2753 Label L_OneCharLoop;
2754 bind(L_TooShort);
2755 mtctr(haycnt);
2756 lhz(n_start, 0, needle); // First character of needle
2757 bind(L_OneCharLoop);
2758 lhzu(ch1, 2, addr);
2759 cmpw(CCR1, ch1, n_start);
2760 beq(CCR1, L_Found); // Did we find the one character needle?
2761 bdnz(L_OneCharLoop);
2762 li(result, -1); // Not found.
2763 b(L_End);
2764 } // 8 instructions, so no impact on alignment.
2765 for (int x = 0; x < nopcnt; ++x) nop();
2766 }
2767
2768 // **************************************************************************************************
2769 // Regular Case Part II: compare rest of needle (first 2 characters have been compared already)
2770 // **************************************************************************************************
2771
2772 // Compare the rest
2773 //36 if needlecntval==0, else 37:
2774 bind(L_Comp2);
2775 addi(addr, addr, 2); // First comparison has failed, 2nd one hit.
2776 bind(L_Comp1); // Addr points to possible needle start.
2777 bind(L_Comp3); // Could have created a copy and use a different return address but saving code size here.
2778 if (needlecntval != 2) { // Const needlecnt==2?
2779 if (needlecntval != 3) {
2780 if (needlecntval == 0) beq(CCR6, L_Found); // Variable needlecnt==2?
2781 Register ind_reg = tmp4;
2782 li(ind_reg, 2*2); // First 2 characters are already compared, use index 2.
2783 mtctr(needlecnt); // Decremented by 2, still > 0.
2784 //40:
2785 Label L_CompLoop;
2786 bind(L_CompLoop);
2787 lhzx(ch2, needle, ind_reg);
2788 lhzx(ch1, addr, ind_reg);
2789 cmpw(CCR1, ch1, ch2);
2790 bne(CCR1, L_OuterLoop);
2791 addi(ind_reg, ind_reg, 2);
2792 bdnz(L_CompLoop);
2793 } else { // No loop required if there's only one needle character left.
2794 lhz(ch2, 2*2, needle);
2795 lhz(ch1, 2*2, addr);
2796 cmpw(CCR1, ch1, ch2);
2797 bne(CCR1, L_OuterLoop);
2798 }
2799 }
2800 // Return index ...
2801 //46:
2802 bind(L_Found);
2803 subf(addr, haystack, addr); // relative to haystack, ...
2804 srdi(result, addr, 1); // in characters.
2805 //48:
2806 bind(L_End);
2807 }
2808
2809 // Implementation of Compare for jchar arrays.
2810 //
2811 // Kills the registers str1, str2, cnt1, cnt2.
2812 // Kills cr0, ctr.
2813 // Assumes that result differes from the input registers.
2814 void MacroAssembler::string_compare(Register str1_reg, Register str2_reg, Register cnt1_reg, Register cnt2_reg,
2815 Register result_reg, Register tmp_reg) {
2816 assert_different_registers(result_reg, str1_reg, str2_reg, cnt1_reg, cnt2_reg, tmp_reg);
2817
2818 Label Ldone, Lslow_case, Lslow_loop, Lfast_loop;
2819 Register cnt_diff = R0,
2820 limit_reg = cnt1_reg,
2821 chr1_reg = result_reg,
2822 chr2_reg = cnt2_reg,
2823 addr_diff = str2_reg;
2824
2825 // Offset 0 should be 32 byte aligned.
2826 //-4:
2827 dcbtct(str1_reg, 0x00); // Indicate R/O access to str1.
2828 dcbtct(str2_reg, 0x00); // Indicate R/O access to str2.
2829 //-2:
2830 // Compute min(cnt1, cnt2) and check if 0 (bail out if we don't need to compare characters).
2831 subf(result_reg, cnt2_reg, cnt1_reg); // difference between cnt1/2
2832 subf_(addr_diff, str1_reg, str2_reg); // alias?
2833 beq(CCR0, Ldone); // return cnt difference if both ones are identical
2834 srawi(limit_reg, result_reg, 31); // generate signmask (cnt1/2 must be non-negative so cnt_diff can't overflow)
2835 mr(cnt_diff, result_reg);
2836 andr(limit_reg, result_reg, limit_reg); // difference or zero (negative): cnt1<cnt2 ? cnt1-cnt2 : 0
2837 add_(limit_reg, cnt2_reg, limit_reg); // min(cnt1, cnt2)==0?
2838 beq(CCR0, Ldone); // return cnt difference if one has 0 length
2839
2840 lhz(chr1_reg, 0, str1_reg); // optional: early out if first characters mismatch
2841 lhzx(chr2_reg, str1_reg, addr_diff); // optional: early out if first characters mismatch
2842 addi(tmp_reg, limit_reg, -1); // min(cnt1, cnt2)-1
2843 subf_(result_reg, chr2_reg, chr1_reg); // optional: early out if first characters mismatch
2844 bne(CCR0, Ldone); // optional: early out if first characters mismatch
2845
2846 // Set loop counter by scaling down tmp_reg
2847 srawi_(chr2_reg, tmp_reg, exact_log2(4)); // (min(cnt1, cnt2)-1)/4
2848 ble(CCR0, Lslow_case); // need >4 characters for fast loop
2849 andi(limit_reg, tmp_reg, 4-1); // remaining characters
2850
2851 // Adapt str1_reg str2_reg for the first loop iteration
2852 mtctr(chr2_reg); // (min(cnt1, cnt2)-1)/4
2853 addi(limit_reg, limit_reg, 4+1); // compare last 5-8 characters in slow_case if mismatch found in fast_loop
2854 //16:
2855 // Compare the rest of the characters
2856 bind(Lfast_loop);
2857 ld(chr1_reg, 0, str1_reg);
2858 ldx(chr2_reg, str1_reg, addr_diff);
2859 cmpd(CCR0, chr2_reg, chr1_reg);
2860 bne(CCR0, Lslow_case); // return chr1_reg
2861 addi(str1_reg, str1_reg, 4*2);
2862 bdnz(Lfast_loop);
2863 addi(limit_reg, limit_reg, -4); // no mismatch found in fast_loop, only 1-4 characters missing
2864 //23:
2865 bind(Lslow_case);
2866 mtctr(limit_reg);
2867 //24:
2868 bind(Lslow_loop);
2869 lhz(chr1_reg, 0, str1_reg);
2870 lhzx(chr2_reg, str1_reg, addr_diff);
2871 subf_(result_reg, chr2_reg, chr1_reg);
2872 bne(CCR0, Ldone); // return chr1_reg
2873 addi(str1_reg, str1_reg, 1*2);
2874 bdnz(Lslow_loop);
2875 //30:
2876 // If strings are equal up to min length, return the length difference.
2877 mr(result_reg, cnt_diff);
2878 nop(); // alignment
2879 //32:
2880 // Otherwise, return the difference between the first mismatched chars.
2881 bind(Ldone);
2882 }
2883
2884
2885 // Compare char[] arrays.
2886 //
2887 // str1_reg USE only
2888 // str2_reg USE only
2889 // cnt_reg USE_DEF, due to tmp reg shortage
2890 // result_reg DEF only, might compromise USE only registers
2891 void MacroAssembler::char_arrays_equals(Register str1_reg, Register str2_reg, Register cnt_reg, Register result_reg,
2892 Register tmp1_reg, Register tmp2_reg, Register tmp3_reg, Register tmp4_reg,
2893 Register tmp5_reg) {
2894
2895 // Str1 may be the same register as str2 which can occur e.g. after scalar replacement.
2896 assert_different_registers(result_reg, str1_reg, cnt_reg, tmp1_reg, tmp2_reg, tmp3_reg, tmp4_reg, tmp5_reg);
2897 assert_different_registers(result_reg, str2_reg, cnt_reg, tmp1_reg, tmp2_reg, tmp3_reg, tmp4_reg, tmp5_reg);
2898
2899 // Offset 0 should be 32 byte aligned.
2900 Label Linit_cbc, Lcbc, Lloop, Ldone_true, Ldone_false;
2901 Register index_reg = tmp5_reg;
2902 Register cbc_iter = tmp4_reg;
2903
2904 //-1:
2905 dcbtct(str1_reg, 0x00); // Indicate R/O access to str1.
2906 dcbtct(str2_reg, 0x00); // Indicate R/O access to str2.
2907 //1:
2908 andi(cbc_iter, cnt_reg, 4-1); // Remaining iterations after 4 java characters per iteration loop.
2909 li(index_reg, 0); // init
2910 li(result_reg, 0); // assume false
2911 srwi_(tmp2_reg, cnt_reg, exact_log2(4)); // Div: 4 java characters per iteration (main loop).
2912
2913 cmpwi(CCR1, cbc_iter, 0); // CCR1 = (cbc_iter==0)
2914 beq(CCR0, Linit_cbc); // too short
2915 mtctr(tmp2_reg);
2916 //8:
2917 bind(Lloop);
2918 ldx(tmp1_reg, str1_reg, index_reg);
2919 ldx(tmp2_reg, str2_reg, index_reg);
2920 cmpd(CCR0, tmp1_reg, tmp2_reg);
2921 bne(CCR0, Ldone_false); // Unequal char pair found -> done.
2922 addi(index_reg, index_reg, 4*sizeof(jchar));
2923 bdnz(Lloop);
2924 //14:
2925 bind(Linit_cbc);
2926 beq(CCR1, Ldone_true);
2927 mtctr(cbc_iter);
2928 //16:
2929 bind(Lcbc);
2930 lhzx(tmp1_reg, str1_reg, index_reg);
2931 lhzx(tmp2_reg, str2_reg, index_reg);
2932 cmpw(CCR0, tmp1_reg, tmp2_reg);
2933 bne(CCR0, Ldone_false); // Unequal char pair found -> done.
2934 addi(index_reg, index_reg, 1*sizeof(jchar));
2935 bdnz(Lcbc);
2936 nop();
2937 bind(Ldone_true);
2938 li(result_reg, 1);
2939 //24:
2940 bind(Ldone_false);
2941 }
2942
2943
2944 void MacroAssembler::char_arrays_equalsImm(Register str1_reg, Register str2_reg, int cntval, Register result_reg,
2945 Register tmp1_reg, Register tmp2_reg) {
2946 // Str1 may be the same register as str2 which can occur e.g. after scalar replacement.
2947 assert_different_registers(result_reg, str1_reg, tmp1_reg, tmp2_reg);
2948 assert_different_registers(result_reg, str2_reg, tmp1_reg, tmp2_reg);
2949 assert(sizeof(jchar) == 2, "must be");
2950 assert(cntval >= 0 && ((cntval & 0x7fff) == cntval), "wrong immediate");
2951
2952 Label Ldone_false;
2953
2954 if (cntval < 16) { // short case
2955 if (cntval != 0) li(result_reg, 0); // assume false
2956
2957 const int num_bytes = cntval*sizeof(jchar);
2958 int index = 0;
2959 for (int next_index; (next_index = index + 8) <= num_bytes; index = next_index) {
2960 ld(tmp1_reg, index, str1_reg);
2961 ld(tmp2_reg, index, str2_reg);
2962 cmpd(CCR0, tmp1_reg, tmp2_reg);
2963 bne(CCR0, Ldone_false);
2964 }
2965 if (cntval & 2) {
2966 lwz(tmp1_reg, index, str1_reg);
2967 lwz(tmp2_reg, index, str2_reg);
2968 cmpw(CCR0, tmp1_reg, tmp2_reg);
2969 bne(CCR0, Ldone_false);
2970 index += 4;
2971 }
2972 if (cntval & 1) {
2973 lhz(tmp1_reg, index, str1_reg);
2974 lhz(tmp2_reg, index, str2_reg);
2975 cmpw(CCR0, tmp1_reg, tmp2_reg);
2976 bne(CCR0, Ldone_false);
2977 }
2978 // fallthrough: true
2979 } else {
2980 Label Lloop;
2981 Register index_reg = tmp1_reg;
2982 const int loopcnt = cntval/4;
2983 assert(loopcnt > 0, "must be");
2984 // Offset 0 should be 32 byte aligned.
2985 //2:
2986 dcbtct(str1_reg, 0x00); // Indicate R/O access to str1.
2987 dcbtct(str2_reg, 0x00); // Indicate R/O access to str2.
2988 li(tmp2_reg, loopcnt);
2989 li(index_reg, 0); // init
2990 li(result_reg, 0); // assume false
2991 mtctr(tmp2_reg);
2992 //8:
2993 bind(Lloop);
2994 ldx(R0, str1_reg, index_reg);
2995 ldx(tmp2_reg, str2_reg, index_reg);
2996 cmpd(CCR0, R0, tmp2_reg);
2997 bne(CCR0, Ldone_false); // Unequal char pair found -> done.
2998 addi(index_reg, index_reg, 4*sizeof(jchar));
2999 bdnz(Lloop);
3000 //14:
3001 if (cntval & 2) {
3002 lwzx(R0, str1_reg, index_reg);
3003 lwzx(tmp2_reg, str2_reg, index_reg);
3004 cmpw(CCR0, R0, tmp2_reg);
3005 bne(CCR0, Ldone_false);
3006 if (cntval & 1) addi(index_reg, index_reg, 2*sizeof(jchar));
3007 }
3008 if (cntval & 1) {
3009 lhzx(R0, str1_reg, index_reg);
3010 lhzx(tmp2_reg, str2_reg, index_reg);
3011 cmpw(CCR0, R0, tmp2_reg);
3012 bne(CCR0, Ldone_false);
3013 }
3014 // fallthru: true
3015 }
3016 li(result_reg, 1);
3017 bind(Ldone_false);
3018 }
3019
3020
3021 void MacroAssembler::asm_assert(bool check_equal, const char *msg, int id) {
3022 #ifdef ASSERT
3023 Label ok;
3024 if (check_equal) {
3025 beq(CCR0, ok);
3026 } else {
3027 bne(CCR0, ok);
3028 }
3029 stop(msg, id);
3030 bind(ok);
3031 #endif
3032 }
3033
3034 void MacroAssembler::asm_assert_mems_zero(bool check_equal, int size, int mem_offset,
3035 Register mem_base, const char* msg, int id) {
3036 #ifdef ASSERT
3037 switch (size) {
3038 case 4:
3039 lwz(R0, mem_offset, mem_base);
3040 cmpwi(CCR0, R0, 0);
3041 break;
3042 case 8:
3043 ld(R0, mem_offset, mem_base);
3044 cmpdi(CCR0, R0, 0);
3045 break;
3046 default:
3047 ShouldNotReachHere();
3048 }
3049 asm_assert(check_equal, msg, id);
3050 #endif // ASSERT
3051 }
3052
3053 void MacroAssembler::verify_thread() {
3054 if (VerifyThread) {
3055 unimplemented("'VerifyThread' currently not implemented on PPC");
3056 }
3057 }
3058
3059 // READ: oop. KILL: R0. Volatile floats perhaps.
3060 void MacroAssembler::verify_oop(Register oop, const char* msg) {
3061 if (!VerifyOops) {
3062 return;
3063 }
3064 // Will be preserved.
3065 Register tmp = R11;
3066 assert(oop != tmp, "precondition");
3067 unsigned int nbytes_save = 10*8; // 10 volatile gprs
3068 address/* FunctionDescriptor** */fd = StubRoutines::verify_oop_subroutine_entry_address();
3069 // save tmp
3070 mr(R0, tmp);
3071 // kill tmp
3072 save_LR_CR(tmp);
3073 push_frame_reg_args(nbytes_save, tmp);
3074 // restore tmp
3075 mr(tmp, R0);
3076 save_volatile_gprs(R1_SP, 112); // except R0
3077 // load FunctionDescriptor** / entry_address *
3078 load_const(tmp, fd);
3079 // load FunctionDescriptor* / entry_address
3080 ld(tmp, 0, tmp);
3081 mr(R4_ARG2, oop);
3082 load_const(R3_ARG1, (address)msg);
3083 // call destination for its side effect
3084 call_c(tmp);
3085 restore_volatile_gprs(R1_SP, 112); // except R0
3086 pop_frame();
3087 // save tmp
3088 mr(R0, tmp);
3089 // kill tmp
3090 restore_LR_CR(tmp);
3091 // restore tmp
3092 mr(tmp, R0);
3093 }
3094
3095 const char* stop_types[] = {
3096 "stop",
3097 "untested",
3098 "unimplemented",
3099 "shouldnotreachhere"
3100 };
3101
3102 static void stop_on_request(int tp, const char* msg) {
3103 tty->print("PPC assembly code requires stop: (%s) %s\n", stop_types[tp%/*stop_end*/4], msg);
3104 guarantee(false, err_msg("PPC assembly code requires stop: %s", msg));
3105 }
3106
3107 // Call a C-function that prints output.
3108 void MacroAssembler::stop(int type, const char* msg, int id) {
3109 #ifndef PRODUCT
3110 block_comment(err_msg("stop: %s %s {", stop_types[type%stop_end], msg));
3111 #else
3112 block_comment("stop {");
3113 #endif
3114
3115 // setup arguments
3116 load_const_optimized(R3_ARG1, type);
3117 load_const_optimized(R4_ARG2, (void *)msg, /*tmp=*/R0);
3118 call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), R3_ARG1, R4_ARG2);
3119 illtrap();
3120 emit_int32(id);
3121 block_comment("} stop;");
3122 }
3123
3124 #ifndef PRODUCT
3125 // Write pattern 0x0101010101010101 in memory region [low-before, high+after].
3126 // Val, addr are temp registers.
3127 // If low == addr, addr is killed.
3128 // High is preserved.
3129 void MacroAssembler::zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) {
3130 if (!ZapMemory) return;
3131
3132 assert_different_registers(low, val);
3133
3134 BLOCK_COMMENT("zap memory region {");
3135 load_const_optimized(val, 0x0101010101010101);
3136 int size = before + after;
3137 if (low == high && size < 5 && size > 0) {
3138 int offset = -before*BytesPerWord;
3139 for (int i = 0; i < size; ++i) {
3140 std(val, offset, low);
3141 offset += (1*BytesPerWord);
3142 }
3143 } else {
3144 addi(addr, low, -before*BytesPerWord);
3145 assert_different_registers(high, val);
3146 if (after) addi(high, high, after * BytesPerWord);
3147 Label loop;
3148 bind(loop);
3149 std(val, 0, addr);
3150 addi(addr, addr, 8);
3151 cmpd(CCR6, addr, high);
3152 ble(CCR6, loop);
3153 if (after) addi(high, high, -after * BytesPerWord); // Correct back to old value.
3154 }
3155 BLOCK_COMMENT("} zap memory region");
3156 }
3157
3158 #endif // !PRODUCT
3159
3160 SkipIfEqualZero::SkipIfEqualZero(MacroAssembler* masm, Register temp, const bool* flag_addr) : _masm(masm), _label() {
3161 int simm16_offset = masm->load_const_optimized(temp, (address)flag_addr, R0, true);
3162 assert(sizeof(bool) == 1, "PowerPC ABI");
3163 masm->lbz(temp, simm16_offset, temp);
3164 masm->cmpwi(CCR0, temp, 0);
3165 masm->beq(CCR0, _label);
3166 }
3167
3168 SkipIfEqualZero::~SkipIfEqualZero() {
3169 _masm->bind(_label);
3170 }