1 //
2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2014 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
900
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
906
907 source %{
908
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
925
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
937
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
954
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
961
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
976
977 return false;
978 }
979
980 #define __ _masm.
981
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
984
985 // ****************************************************************************
986
987 // REQUIRED FUNCTIONALITY
988
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
992
993 // PPC port: Removed use of lazy constant construct.
994
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
999
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1005
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1016
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1024
1025 //=============================================================================
1026
1027 // condition code conversions
1028
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1032
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1036
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1040
1041 //=============================================================================
1042
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1046
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1050
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1054
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1058
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1062
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1066
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1071
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1075
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1079
1080 //=============================================================================
1081
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1087
1088 //=============================================================================
1089
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1095
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1101
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1105
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1109
1110 //=============================================================================
1111
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1116
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1121
1122 //=============================================================================
1123
1124 %} // interrupt source
1125
1126 source_hpp %{ // Header information of the source block.
1127
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1131
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1133
1134 class CallStubImpl {
1135
1136 public:
1137
1138 // Emit call stub, compiled java to interpreter.
1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1140
1141 // Size of call trampoline stub.
1142 // This doesn't need to be accurate to the byte, but it
1143 // must be larger than or equal to the real size of the stub.
1144 static uint size_call_trampoline() {
1145 return trampoline_stub_size;
1146 }
1147
1148 // number of relocations needed by a call trampoline stub
1149 static uint reloc_call_trampoline() {
1150 return 5;
1151 }
1152
1153 };
1154
1155 %} // end source_hpp
1156
1157 source %{
1158
1159 // Emit a trampoline stub for a call to a target which is too far away.
1160 //
1161 // code sequences:
1162 //
1163 // call-site:
1164 // branch-and-link to <destination> or <trampoline stub>
1165 //
1166 // Related trampoline stub for this call-site in the stub section:
1167 // load the call target from the constant pool
1168 // branch via CTR (LR/link still points to the call-site above)
1169
1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1171 // Start the stub.
1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1173 if (stub == NULL) {
1174 Compile::current()->env()->record_out_of_memory_failure();
1175 return;
1176 }
1177
1178 // For java_to_interp stubs we use R11_scratch1 as scratch register
1179 // and in call trampoline stubs we use R12_scratch2. This way we
1180 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1181 Register reg_scratch = R12_scratch2;
1182
1183 // Create a trampoline stub relocation which relates this trampoline stub
1184 // with the call instruction at insts_call_instruction_offset in the
1185 // instructions code-section.
1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1187 const int stub_start_offset = __ offset();
1188
1189 // Now, create the trampoline stub's code:
1190 // - load the TOC
1191 // - load the call target from the constant pool
1192 // - call
1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1195 __ mtctr(reg_scratch);
1196 __ bctr();
1197
1198 const address stub_start_addr = __ addr_at(stub_start_offset);
1199
1200 // FIXME: Assert that the trampoline stub can be identified and patched.
1201
1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1204 "encoded offset into the constant pool must match");
1205 // Trampoline_stub_size should be good.
1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1208
1209 // End the stub.
1210 __ end_a_stub();
1211 }
1212
1213 //=============================================================================
1214
1215 // Emit an inline branch-and-link call and a related trampoline stub.
1216 //
1217 // code sequences:
1218 //
1219 // call-site:
1220 // branch-and-link to <destination> or <trampoline stub>
1221 //
1222 // Related trampoline stub for this call-site in the stub section:
1223 // load the call target from the constant pool
1224 // branch via CTR (LR/link still points to the call-site above)
1225 //
1226
1227 typedef struct {
1228 int insts_call_instruction_offset;
1229 int ret_addr_offset;
1230 } EmitCallOffsets;
1231
1232 // Emit a branch-and-link instruction that branches to a trampoline.
1233 // - Remember the offset of the branch-and-link instruction.
1234 // - Add a relocation at the branch-and-link instruction.
1235 // - Emit a branch-and-link.
1236 // - Remember the return pc offset.
1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1238 EmitCallOffsets offsets = { -1, -1 };
1239 const int start_offset = __ offset();
1240 offsets.insts_call_instruction_offset = __ offset();
1241
1242 // No entry point given, use the current pc.
1243 if (entry_point == NULL) entry_point = __ pc();
1244
1245 if (!Compile::current()->in_scratch_emit_size()) {
1246 // Put the entry point as a constant into the constant pool.
1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1249
1250 // Emit the trampoline stub which will be related to the branch-and-link below.
1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1252 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full.
1253 __ relocate(rtype);
1254 }
1255
1256 // Note: At this point we do not have the address of the trampoline
1257 // stub, and the entry point might be too far away for bl, so __ pc()
1258 // serves as dummy and the bl will be patched later.
1259 __ bl((address) __ pc());
1260
1261 offsets.ret_addr_offset = __ offset() - start_offset;
1262
1263 return offsets;
1264 }
1265
1266 //=============================================================================
1267
1268 // Factory for creating loadConL* nodes for large/small constant pool.
1269
1270 static inline jlong replicate_immF(float con) {
1271 // Replicate float con 2 times and pack into vector.
1272 int val = *((int*)&con);
1273 jlong lval = val;
1274 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1275 return lval;
1276 }
1277
1278 //=============================================================================
1279
1280 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1281 int Compile::ConstantTable::calculate_table_base_offset() const {
1282 return 0; // absolute addressing, no offset
1283 }
1284
1285 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1286 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1287 iRegPdstOper *op_dst = new iRegPdstOper();
1288 MachNode *m1 = new loadToc_hiNode();
1289 MachNode *m2 = new loadToc_loNode();
1290
1291 m1->add_req(NULL);
1292 m2->add_req(NULL, m1);
1293 m1->_opnds[0] = op_dst;
1294 m2->_opnds[0] = op_dst;
1295 m2->_opnds[1] = op_dst;
1296 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1297 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1298 nodes->push(m1);
1299 nodes->push(m2);
1300 }
1301
1302 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1303 // Is postalloc expanded.
1304 ShouldNotReachHere();
1305 }
1306
1307 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1308 return 0;
1309 }
1310
1311 #ifndef PRODUCT
1312 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1313 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1314 }
1315 #endif
1316
1317 //=============================================================================
1318
1319 #ifndef PRODUCT
1320 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1321 Compile* C = ra_->C;
1322 const long framesize = C->frame_slots() << LogBytesPerInt;
1323
1324 st->print("PROLOG\n\t");
1325 if (C->need_stack_bang(framesize)) {
1326 st->print("stack_overflow_check\n\t");
1327 }
1328
1329 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1330 st->print("save return pc\n\t");
1331 st->print("push frame %ld\n\t", -framesize);
1332 }
1333 }
1334 #endif
1335
1336 // Macro used instead of the common __ to emulate the pipes of PPC.
1337 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1338 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1339 // still no scheduling of this code is possible, the micro scheduler is aware of the
1340 // code and can update its internal data. The following mechanism is used to achieve this:
1341 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1342 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1343 #if 0 // TODO: PPC port
1344 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1345 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1346 _masm.
1347 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1348 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1349 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1350 C->hb_scheduling()->_pdScheduling->advance_offset
1351 #else
1352 #define ___(op) if (UsePower6SchedulerPPC64) \
1353 Unimplemented(); \
1354 _masm.
1355 #define ___stop if (UsePower6SchedulerPPC64) \
1356 Unimplemented()
1357 #define ___advance if (UsePower6SchedulerPPC64) \
1358 Unimplemented()
1359 #endif
1360
1361 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1362 Compile* C = ra_->C;
1363 MacroAssembler _masm(&cbuf);
1364
1365 const long framesize = C->frame_size_in_bytes();
1366 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1367
1368 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1369
1370 const Register return_pc = R20; // Must match return_addr() in frame section.
1371 const Register callers_sp = R21;
1372 const Register push_frame_temp = R22;
1373 const Register toc_temp = R23;
1374 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1375
1376 if (method_is_frameless) {
1377 // Add nop at beginning of all frameless methods to prevent any
1378 // oop instructions from getting overwritten by make_not_entrant
1379 // (patching attempt would fail).
1380 ___(nop) nop();
1381 } else {
1382 // Get return pc.
1383 ___(mflr) mflr(return_pc);
1384 }
1385
1386 // Calls to C2R adapters often do not accept exceptional returns.
1387 // We require that their callers must bang for them. But be
1388 // careful, because some VM calls (such as call site linkage) can
1389 // use several kilobytes of stack. But the stack safety zone should
1390 // account for that. See bugs 4446381, 4468289, 4497237.
1391
1392 int bangsize = C->bang_size_in_bytes();
1393 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1394 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1395 // Unfortunately we cannot use the function provided in
1396 // assembler.cpp as we have to emulate the pipes. So I had to
1397 // insert the code of generate_stack_overflow_check(), see
1398 // assembler.cpp for some illuminative comments.
1399 const int page_size = os::vm_page_size();
1400 int bang_end = StackShadowPages * page_size;
1401
1402 // This is how far the previous frame's stack banging extended.
1403 const int bang_end_safe = bang_end;
1404
1405 if (bangsize > page_size) {
1406 bang_end += bangsize;
1407 }
1408
1409 int bang_offset = bang_end_safe;
1410
1411 while (bang_offset <= bang_end) {
1412 // Need at least one stack bang at end of shadow zone.
1413
1414 // Again I had to copy code, this time from assembler_ppc.cpp,
1415 // bang_stack_with_offset - see there for comments.
1416
1417 // Stack grows down, caller passes positive offset.
1418 assert(bang_offset > 0, "must bang with positive offset");
1419
1420 long stdoffset = -bang_offset;
1421
1422 if (Assembler::is_simm(stdoffset, 16)) {
1423 // Signed 16 bit offset, a simple std is ok.
1424 if (UseLoadInstructionsForStackBangingPPC64) {
1425 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1426 } else {
1427 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1428 }
1429 } else if (Assembler::is_simm(stdoffset, 31)) {
1430 // Use largeoffset calculations for addis & ld/std.
1431 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1432 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1433
1434 Register tmp = R11;
1435 ___(addis) addis(tmp, R1_SP, hi);
1436 if (UseLoadInstructionsForStackBangingPPC64) {
1437 ___(ld) ld(R0, lo, tmp);
1438 } else {
1439 ___(std) std(R0, lo, tmp);
1440 }
1441 } else {
1442 ShouldNotReachHere();
1443 }
1444
1445 bang_offset += page_size;
1446 }
1447 // R11 trashed
1448 } // C->need_stack_bang(framesize) && UseStackBanging
1449
1450 unsigned int bytes = (unsigned int)framesize;
1451 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1452 ciMethod *currMethod = C->method();
1453
1454 // Optimized version for most common case.
1455 if (UsePower6SchedulerPPC64 &&
1456 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1457 !(false /* ConstantsALot TODO: PPC port*/)) {
1458 ___(or) mr(callers_sp, R1_SP);
1459 ___(std) std(return_pc, _abi(lr), R1_SP);
1460 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1461 return;
1462 }
1463
1464 if (!method_is_frameless) {
1465 // Get callers sp.
1466 ___(or) mr(callers_sp, R1_SP);
1467
1468 // Push method's frame, modifies SP.
1469 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1470 // The ABI is already accounted for in 'framesize' via the
1471 // 'out_preserve' area.
1472 Register tmp = push_frame_temp;
1473 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1474 if (Assembler::is_simm(-offset, 16)) {
1475 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1476 } else {
1477 long x = -offset;
1478 // Had to insert load_const(tmp, -offset).
1479 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1480 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1481 ___(rldicr) sldi(tmp, tmp, 32);
1482 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1483 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1484
1485 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1486 }
1487 }
1488 #if 0 // TODO: PPC port
1489 // For testing large constant pools, emit a lot of constants to constant pool.
1490 // "Randomize" const_size.
1491 if (ConstantsALot) {
1492 const int num_consts = const_size();
1493 for (int i = 0; i < num_consts; i++) {
1494 __ long_constant(0xB0B5B00BBABE);
1495 }
1496 }
1497 #endif
1498 if (!method_is_frameless) {
1499 // Save return pc.
1500 ___(std) std(return_pc, _abi(lr), callers_sp);
1501 }
1502 }
1503 #undef ___
1504 #undef ___stop
1505 #undef ___advance
1506
1507 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1508 // Variable size. determine dynamically.
1509 return MachNode::size(ra_);
1510 }
1511
1512 int MachPrologNode::reloc() const {
1513 // Return number of relocatable values contained in this instruction.
1514 return 1; // 1 reloc entry for load_const(toc).
1515 }
1516
1517 //=============================================================================
1518
1519 #ifndef PRODUCT
1520 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1521 Compile* C = ra_->C;
1522
1523 st->print("EPILOG\n\t");
1524 st->print("restore return pc\n\t");
1525 st->print("pop frame\n\t");
1526
1527 if (do_polling() && C->is_method_compilation()) {
1528 st->print("touch polling page\n\t");
1529 }
1530 }
1531 #endif
1532
1533 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1534 Compile* C = ra_->C;
1535 MacroAssembler _masm(&cbuf);
1536
1537 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1538 assert(framesize >= 0, "negative frame-size?");
1539
1540 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1541 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1542 const Register return_pc = R11;
1543 const Register polling_page = R12;
1544
1545 if (!method_is_frameless) {
1546 // Restore return pc relative to callers' sp.
1547 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1548 }
1549
1550 if (method_needs_polling) {
1551 if (LoadPollAddressFromThread) {
1552 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1553 Unimplemented();
1554 } else {
1555 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1556 }
1557 }
1558
1559 if (!method_is_frameless) {
1560 // Move return pc to LR.
1561 __ mtlr(return_pc);
1562 // Pop frame (fixed frame-size).
1563 __ addi(R1_SP, R1_SP, (int)framesize);
1564 }
1565
1566 if (method_needs_polling) {
1567 // We need to mark the code position where the load from the safepoint
1568 // polling page was emitted as relocInfo::poll_return_type here.
1569 __ relocate(relocInfo::poll_return_type);
1570 __ load_from_polling_page(polling_page);
1571 }
1572 }
1573
1574 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1575 // Variable size. Determine dynamically.
1576 return MachNode::size(ra_);
1577 }
1578
1579 int MachEpilogNode::reloc() const {
1580 // Return number of relocatable values contained in this instruction.
1581 return 1; // 1 for load_from_polling_page.
1582 }
1583
1584 const Pipeline * MachEpilogNode::pipeline() const {
1585 return MachNode::pipeline_class();
1586 }
1587
1588 // This method seems to be obsolete. It is declared in machnode.hpp
1589 // and defined in all *.ad files, but it is never called. Should we
1590 // get rid of it?
1591 int MachEpilogNode::safepoint_offset() const {
1592 assert(do_polling(), "no return for this epilog node");
1593 return 0;
1594 }
1595
1596 #if 0 // TODO: PPC port
1597 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1598 MacroAssembler _masm(&cbuf);
1599 if (LoadPollAddressFromThread) {
1600 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1601 } else {
1602 _masm.nop();
1603 }
1604 }
1605
1606 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1607 if (LoadPollAddressFromThread) {
1608 return 4;
1609 } else {
1610 return 4;
1611 }
1612 }
1613
1614 #ifndef PRODUCT
1615 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1616 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1617 }
1618 #endif
1619
1620 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1621 return RSCRATCH1_BITS64_REG_mask();
1622 }
1623 #endif // PPC port
1624
1625 // =============================================================================
1626
1627 // Figure out which register class each belongs in: rc_int, rc_float or
1628 // rc_stack.
1629 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1630
1631 static enum RC rc_class(OptoReg::Name reg) {
1632 // Return the register class for the given register. The given register
1633 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1634 // enumeration in adGlobals_ppc.hpp.
1635
1636 if (reg == OptoReg::Bad) return rc_bad;
1637
1638 // We have 64 integer register halves, starting at index 0.
1639 if (reg < 64) return rc_int;
1640
1641 // We have 64 floating-point register halves, starting at index 64.
1642 if (reg < 64+64) return rc_float;
1643
1644 // Between float regs & stack are the flags regs.
1645 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1646
1647 return rc_stack;
1648 }
1649
1650 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1651 bool do_print, Compile* C, outputStream *st) {
1652
1653 assert(opcode == Assembler::LD_OPCODE ||
1654 opcode == Assembler::STD_OPCODE ||
1655 opcode == Assembler::LWZ_OPCODE ||
1656 opcode == Assembler::STW_OPCODE ||
1657 opcode == Assembler::LFD_OPCODE ||
1658 opcode == Assembler::STFD_OPCODE ||
1659 opcode == Assembler::LFS_OPCODE ||
1660 opcode == Assembler::STFS_OPCODE,
1661 "opcode not supported");
1662
1663 if (cbuf) {
1664 int d =
1665 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1666 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1667 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1668 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1669 }
1670 #ifndef PRODUCT
1671 else if (do_print) {
1672 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1673 op_str,
1674 Matcher::regName[reg],
1675 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1676 }
1677 #endif
1678 return 4; // size
1679 }
1680
1681 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1682 Compile* C = ra_->C;
1683
1684 // Get registers to move.
1685 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1686 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1687 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1688 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1689
1690 enum RC src_hi_rc = rc_class(src_hi);
1691 enum RC src_lo_rc = rc_class(src_lo);
1692 enum RC dst_hi_rc = rc_class(dst_hi);
1693 enum RC dst_lo_rc = rc_class(dst_lo);
1694
1695 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1696 if (src_hi != OptoReg::Bad)
1697 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1698 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1699 "expected aligned-adjacent pairs");
1700 // Generate spill code!
1701 int size = 0;
1702
1703 if (src_lo == dst_lo && src_hi == dst_hi)
1704 return size; // Self copy, no move.
1705
1706 // --------------------------------------
1707 // Memory->Memory Spill. Use R0 to hold the value.
1708 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1709 int src_offset = ra_->reg2offset(src_lo);
1710 int dst_offset = ra_->reg2offset(dst_lo);
1711 if (src_hi != OptoReg::Bad) {
1712 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1713 "expected same type of move for high parts");
1714 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1715 if (!cbuf && !do_size) st->print("\n\t");
1716 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1717 } else {
1718 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1719 if (!cbuf && !do_size) st->print("\n\t");
1720 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1721 }
1722 return size;
1723 }
1724
1725 // --------------------------------------
1726 // Check for float->int copy; requires a trip through memory.
1727 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1728 Unimplemented();
1729 }
1730
1731 // --------------------------------------
1732 // Check for integer reg-reg copy.
1733 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1734 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1735 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1736 size = (Rsrc != Rdst) ? 4 : 0;
1737
1738 if (cbuf) {
1739 MacroAssembler _masm(cbuf);
1740 if (size) {
1741 __ mr(Rdst, Rsrc);
1742 }
1743 }
1744 #ifndef PRODUCT
1745 else if (!do_size) {
1746 if (size) {
1747 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1748 } else {
1749 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1750 }
1751 }
1752 #endif
1753 return size;
1754 }
1755
1756 // Check for integer store.
1757 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1758 int dst_offset = ra_->reg2offset(dst_lo);
1759 if (src_hi != OptoReg::Bad) {
1760 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1761 "expected same type of move for high parts");
1762 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1763 } else {
1764 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1765 }
1766 return size;
1767 }
1768
1769 // Check for integer load.
1770 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1771 int src_offset = ra_->reg2offset(src_lo);
1772 if (src_hi != OptoReg::Bad) {
1773 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1774 "expected same type of move for high parts");
1775 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1776 } else {
1777 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1778 }
1779 return size;
1780 }
1781
1782 // Check for float reg-reg copy.
1783 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1784 if (cbuf) {
1785 MacroAssembler _masm(cbuf);
1786 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1787 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1788 __ fmr(Rdst, Rsrc);
1789 }
1790 #ifndef PRODUCT
1791 else if (!do_size) {
1792 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1793 }
1794 #endif
1795 return 4;
1796 }
1797
1798 // Check for float store.
1799 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1800 int dst_offset = ra_->reg2offset(dst_lo);
1801 if (src_hi != OptoReg::Bad) {
1802 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1803 "expected same type of move for high parts");
1804 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1805 } else {
1806 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1807 }
1808 return size;
1809 }
1810
1811 // Check for float load.
1812 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1813 int src_offset = ra_->reg2offset(src_lo);
1814 if (src_hi != OptoReg::Bad) {
1815 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1816 "expected same type of move for high parts");
1817 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1818 } else {
1819 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1820 }
1821 return size;
1822 }
1823
1824 // --------------------------------------------------------------------
1825 // Check for hi bits still needing moving. Only happens for misaligned
1826 // arguments to native calls.
1827 if (src_hi == dst_hi)
1828 return size; // Self copy; no move.
1829
1830 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1831 ShouldNotReachHere(); // Unimplemented
1832 return 0;
1833 }
1834
1835 #ifndef PRODUCT
1836 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1837 if (!ra_)
1838 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1839 else
1840 implementation(NULL, ra_, false, st);
1841 }
1842 #endif
1843
1844 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1845 implementation(&cbuf, ra_, false, NULL);
1846 }
1847
1848 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1849 return implementation(NULL, ra_, true, NULL);
1850 }
1851
1852 #if 0 // TODO: PPC port
1853 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1854 #ifndef PRODUCT
1855 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1856 #endif
1857 assert(ra_->node_regs_max_index() != 0, "");
1858
1859 // Get registers to move.
1860 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1861 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1862 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1863 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1864
1865 enum RC src_lo_rc = rc_class(src_lo);
1866 enum RC dst_lo_rc = rc_class(dst_lo);
1867
1868 if (src_lo == dst_lo && src_hi == dst_hi)
1869 return ppc64Opcode_none; // Self copy, no move.
1870
1871 // --------------------------------------
1872 // Memory->Memory Spill. Use R0 to hold the value.
1873 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1874 return ppc64Opcode_compound;
1875 }
1876
1877 // --------------------------------------
1878 // Check for float->int copy; requires a trip through memory.
1879 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1880 Unimplemented();
1881 }
1882
1883 // --------------------------------------
1884 // Check for integer reg-reg copy.
1885 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1886 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1887 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1888 if (Rsrc == Rdst) {
1889 return ppc64Opcode_none;
1890 } else {
1891 return ppc64Opcode_or;
1892 }
1893 }
1894
1895 // Check for integer store.
1896 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1897 if (src_hi != OptoReg::Bad) {
1898 return ppc64Opcode_std;
1899 } else {
1900 return ppc64Opcode_stw;
1901 }
1902 }
1903
1904 // Check for integer load.
1905 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1906 if (src_hi != OptoReg::Bad) {
1907 return ppc64Opcode_ld;
1908 } else {
1909 return ppc64Opcode_lwz;
1910 }
1911 }
1912
1913 // Check for float reg-reg copy.
1914 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1915 return ppc64Opcode_fmr;
1916 }
1917
1918 // Check for float store.
1919 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1920 if (src_hi != OptoReg::Bad) {
1921 return ppc64Opcode_stfd;
1922 } else {
1923 return ppc64Opcode_stfs;
1924 }
1925 }
1926
1927 // Check for float load.
1928 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1929 if (src_hi != OptoReg::Bad) {
1930 return ppc64Opcode_lfd;
1931 } else {
1932 return ppc64Opcode_lfs;
1933 }
1934 }
1935
1936 // --------------------------------------------------------------------
1937 // Check for hi bits still needing moving. Only happens for misaligned
1938 // arguments to native calls.
1939 if (src_hi == dst_hi)
1940 return ppc64Opcode_none; // Self copy; no move.
1941
1942 ShouldNotReachHere();
1943 return ppc64Opcode_undefined;
1944 }
1945 #endif // PPC port
1946
1947 #ifndef PRODUCT
1948 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1949 st->print("NOP \t// %d nops to pad for loops.", _count);
1950 }
1951 #endif
1952
1953 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1954 MacroAssembler _masm(&cbuf);
1955 // _count contains the number of nops needed for padding.
1956 for (int i = 0; i < _count; i++) {
1957 __ nop();
1958 }
1959 }
1960
1961 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1962 return _count * 4;
1963 }
1964
1965 #ifndef PRODUCT
1966 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1967 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1968 int reg = ra_->get_reg_first(this);
1969 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1970 }
1971 #endif
1972
1973 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1974 MacroAssembler _masm(&cbuf);
1975
1976 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1977 int reg = ra_->get_encode(this);
1978
1979 if (Assembler::is_simm(offset, 16)) {
1980 __ addi(as_Register(reg), R1, offset);
1981 } else {
1982 ShouldNotReachHere();
1983 }
1984 }
1985
1986 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1987 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1988 return 4;
1989 }
1990
1991 #ifndef PRODUCT
1992 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1993 st->print_cr("---- MachUEPNode ----");
1994 st->print_cr("...");
1995 }
1996 #endif
1997
1998 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1999 // This is the unverified entry point.
2000 MacroAssembler _masm(&cbuf);
2001
2002 // Inline_cache contains a klass.
2003 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2004 Register receiver_klass = R12_scratch2; // tmp
2005
2006 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2007 assert(R11_scratch1 == R11, "need prologue scratch register");
2008
2009 // Check for NULL argument if we don't have implicit null checks.
2010 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2011 if (TrapBasedNullChecks) {
2012 __ trap_null_check(R3_ARG1);
2013 } else {
2014 Label valid;
2015 __ cmpdi(CCR0, R3_ARG1, 0);
2016 __ bne_predict_taken(CCR0, valid);
2017 // We have a null argument, branch to ic_miss_stub.
2018 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2019 relocInfo::runtime_call_type);
2020 __ bind(valid);
2021 }
2022 }
2023 // Assume argument is not NULL, load klass from receiver.
2024 __ load_klass(receiver_klass, R3_ARG1);
2025
2026 if (TrapBasedICMissChecks) {
2027 __ trap_ic_miss_check(receiver_klass, ic_klass);
2028 } else {
2029 Label valid;
2030 __ cmpd(CCR0, receiver_klass, ic_klass);
2031 __ beq_predict_taken(CCR0, valid);
2032 // We have an unexpected klass, branch to ic_miss_stub.
2033 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2034 relocInfo::runtime_call_type);
2035 __ bind(valid);
2036 }
2037
2038 // Argument is valid and klass is as expected, continue.
2039 }
2040
2041 #if 0 // TODO: PPC port
2042 // Optimize UEP code on z (save a load_const() call in main path).
2043 int MachUEPNode::ep_offset() {
2044 return 0;
2045 }
2046 #endif
2047
2048 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2049 // Variable size. Determine dynamically.
2050 return MachNode::size(ra_);
2051 }
2052
2053 //=============================================================================
2054
2055 %} // interrupt source
2056
2057 source_hpp %{ // Header information of the source block.
2058
2059 class HandlerImpl {
2060
2061 public:
2062
2063 static int emit_exception_handler(CodeBuffer &cbuf);
2064 static int emit_deopt_handler(CodeBuffer& cbuf);
2065
2066 static uint size_exception_handler() {
2067 // The exception_handler is a b64_patchable.
2068 return MacroAssembler::b64_patchable_size;
2069 }
2070
2071 static uint size_deopt_handler() {
2072 // The deopt_handler is a bl64_patchable.
2073 return MacroAssembler::bl64_patchable_size;
2074 }
2075
2076 };
2077
2078 %} // end source_hpp
2079
2080 source %{
2081
2082 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2083 MacroAssembler _masm(&cbuf);
2084
2085 address base = __ start_a_stub(size_exception_handler());
2086 if (base == NULL) return 0; // CodeBuffer::expand failed
2087
2088 int offset = __ offset();
2089 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2090 relocInfo::runtime_call_type);
2091 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2092 __ end_a_stub();
2093
2094 return offset;
2095 }
2096
2097 // The deopt_handler is like the exception handler, but it calls to
2098 // the deoptimization blob instead of jumping to the exception blob.
2099 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2100 MacroAssembler _masm(&cbuf);
2101
2102 address base = __ start_a_stub(size_deopt_handler());
2103 if (base == NULL) return 0; // CodeBuffer::expand failed
2104
2105 int offset = __ offset();
2106 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2107 relocInfo::runtime_call_type);
2108 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2109 __ end_a_stub();
2110
2111 return offset;
2112 }
2113
2114 //=============================================================================
2115
2116 // Use a frame slots bias for frameless methods if accessing the stack.
2117 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2118 if (as_Register(reg_enc) == R1_SP) {
2119 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2120 }
2121 return 0;
2122 }
2123
2124 const bool Matcher::match_rule_supported(int opcode) {
2125 if (!has_match_rule(opcode))
2126 return false;
2127
2128 switch (opcode) {
2129 case Op_SqrtD:
2130 return VM_Version::has_fsqrt();
2131 case Op_CountLeadingZerosI:
2132 case Op_CountLeadingZerosL:
2133 case Op_CountTrailingZerosI:
2134 case Op_CountTrailingZerosL:
2135 if (!UseCountLeadingZerosInstructionsPPC64)
2136 return false;
2137 break;
2138
2139 case Op_PopCountI:
2140 case Op_PopCountL:
2141 return (UsePopCountInstruction && VM_Version::has_popcntw());
2142
2143 case Op_StrComp:
2144 return SpecialStringCompareTo;
2145 case Op_StrEquals:
2146 return SpecialStringEquals;
2147 case Op_StrIndexOf:
2148 return SpecialStringIndexOf;
2149 }
2150
2151 return true; // Per default match rules are supported.
2152 }
2153
2154 int Matcher::regnum_to_fpu_offset(int regnum) {
2155 // No user for this method?
2156 Unimplemented();
2157 return 999;
2158 }
2159
2160 const bool Matcher::convL2FSupported(void) {
2161 // fcfids can do the conversion (>= Power7).
2162 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2163 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2164 }
2165
2166 // Vector width in bytes.
2167 const int Matcher::vector_width_in_bytes(BasicType bt) {
2168 assert(MaxVectorSize == 8, "");
2169 return 8;
2170 }
2171
2172 // Vector ideal reg.
2173 const int Matcher::vector_ideal_reg(int size) {
2174 assert(MaxVectorSize == 8 && size == 8, "");
2175 return Op_RegL;
2176 }
2177
2178 const int Matcher::vector_shift_count_ideal_reg(int size) {
2179 fatal("vector shift is not supported");
2180 return Node::NotAMachineReg;
2181 }
2182
2183 // Limits on vector size (number of elements) loaded into vector.
2184 const int Matcher::max_vector_size(const BasicType bt) {
2185 assert(is_java_primitive(bt), "only primitive type vectors");
2186 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2187 }
2188
2189 const int Matcher::min_vector_size(const BasicType bt) {
2190 return max_vector_size(bt); // Same as max.
2191 }
2192
2193 // PPC doesn't support misaligned vectors store/load.
2194 const bool Matcher::misaligned_vectors_ok() {
2195 return false;
2196 }
2197
2198 // PPC AES support not yet implemented
2199 const bool Matcher::pass_original_key_for_aes() {
2200 return false;
2201 }
2202
2203 // RETURNS: whether this branch offset is short enough that a short
2204 // branch can be used.
2205 //
2206 // If the platform does not provide any short branch variants, then
2207 // this method should return `false' for offset 0.
2208 //
2209 // `Compile::Fill_buffer' will decide on basis of this information
2210 // whether to do the pass `Compile::Shorten_branches' at all.
2211 //
2212 // And `Compile::Shorten_branches' will decide on basis of this
2213 // information whether to replace particular branch sites by short
2214 // ones.
2215 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2216 // Is the offset within the range of a ppc64 pc relative branch?
2217 bool b;
2218
2219 const int safety_zone = 3 * BytesPerInstWord;
2220 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2221 29 - 16 + 1 + 2);
2222 return b;
2223 }
2224
2225 const bool Matcher::isSimpleConstant64(jlong value) {
2226 // Probably always true, even if a temp register is required.
2227 return true;
2228 }
2229 /* TODO: PPC port
2230 // Make a new machine dependent decode node (with its operands).
2231 MachTypeNode *Matcher::make_decode_node() {
2232 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2233 "This method is only implemented for unscaled cOops mode so far");
2234 MachTypeNode *decode = new decodeN_unscaledNode();
2235 decode->set_opnd_array(0, new iRegPdstOper());
2236 decode->set_opnd_array(1, new iRegNsrcOper());
2237 return decode;
2238 }
2239 */
2240 // Threshold size for cleararray.
2241 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2242
2243 // false => size gets scaled to BytesPerLong, ok.
2244 const bool Matcher::init_array_count_is_in_bytes = false;
2245
2246 // Use conditional move (CMOVL) on Power7.
2247 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2248
2249 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2250 // fsel doesn't accept a condition register as input, so this would be slightly different.
2251 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2252
2253 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2254 const bool Matcher::require_postalloc_expand = true;
2255
2256 // Should the Matcher clone shifts on addressing modes, expecting them to
2257 // be subsumed into complex addressing expressions or compute them into
2258 // registers? True for Intel but false for most RISCs.
2259 const bool Matcher::clone_shift_expressions = false;
2260
2261 // Do we need to mask the count passed to shift instructions or does
2262 // the cpu only look at the lower 5/6 bits anyway?
2263 // Off, as masks are generated in expand rules where required.
2264 // Constant shift counts are handled in Ideal phase.
2265 const bool Matcher::need_masked_shift_count = false;
2266
2267 // This affects two different things:
2268 // - how Decode nodes are matched
2269 // - how ImplicitNullCheck opportunities are recognized
2270 // If true, the matcher will try to remove all Decodes and match them
2271 // (as operands) into nodes. NullChecks are not prepared to deal with
2272 // Decodes by final_graph_reshaping().
2273 // If false, final_graph_reshaping() forces the decode behind the Cmp
2274 // for a NullCheck. The matcher matches the Decode node into a register.
2275 // Implicit_null_check optimization moves the Decode along with the
2276 // memory operation back up before the NullCheck.
2277 bool Matcher::narrow_oop_use_complex_address() {
2278 // TODO: PPC port if (MatchDecodeNodes) return true;
2279 return false;
2280 }
2281
2282 bool Matcher::narrow_klass_use_complex_address() {
2283 NOT_LP64(ShouldNotCallThis());
2284 assert(UseCompressedClassPointers, "only for compressed klass code");
2285 // TODO: PPC port if (MatchDecodeNodes) return true;
2286 return false;
2287 }
2288
2289 // Is it better to copy float constants, or load them directly from memory?
2290 // Intel can load a float constant from a direct address, requiring no
2291 // extra registers. Most RISCs will have to materialize an address into a
2292 // register first, so they would do better to copy the constant from stack.
2293 const bool Matcher::rematerialize_float_constants = false;
2294
2295 // If CPU can load and store mis-aligned doubles directly then no fixup is
2296 // needed. Else we split the double into 2 integer pieces and move it
2297 // piece-by-piece. Only happens when passing doubles into C code as the
2298 // Java calling convention forces doubles to be aligned.
2299 const bool Matcher::misaligned_doubles_ok = true;
2300
2301 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2302 Unimplemented();
2303 }
2304
2305 // Advertise here if the CPU requires explicit rounding operations
2306 // to implement the UseStrictFP mode.
2307 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2308
2309 // Do floats take an entire double register or just half?
2310 //
2311 // A float occupies a ppc64 double register. For the allocator, a
2312 // ppc64 double register appears as a pair of float registers.
2313 bool Matcher::float_in_double() { return true; }
2314
2315 // Do ints take an entire long register or just half?
2316 // The relevant question is how the int is callee-saved:
2317 // the whole long is written but de-opt'ing will have to extract
2318 // the relevant 32 bits.
2319 const bool Matcher::int_in_long = true;
2320
2321 // Constants for c2c and c calling conventions.
2322
2323 const MachRegisterNumbers iarg_reg[8] = {
2324 R3_num, R4_num, R5_num, R6_num,
2325 R7_num, R8_num, R9_num, R10_num
2326 };
2327
2328 const MachRegisterNumbers farg_reg[13] = {
2329 F1_num, F2_num, F3_num, F4_num,
2330 F5_num, F6_num, F7_num, F8_num,
2331 F9_num, F10_num, F11_num, F12_num,
2332 F13_num
2333 };
2334
2335 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2336
2337 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2338
2339 // Return whether or not this register is ever used as an argument. This
2340 // function is used on startup to build the trampoline stubs in generateOptoStub.
2341 // Registers not mentioned will be killed by the VM call in the trampoline, and
2342 // arguments in those registers not be available to the callee.
2343 bool Matcher::can_be_java_arg(int reg) {
2344 // We return true for all registers contained in iarg_reg[] and
2345 // farg_reg[] and their virtual halves.
2346 // We must include the virtual halves in order to get STDs and LDs
2347 // instead of STWs and LWs in the trampoline stubs.
2348
2349 if ( reg == R3_num || reg == R3_H_num
2350 || reg == R4_num || reg == R4_H_num
2351 || reg == R5_num || reg == R5_H_num
2352 || reg == R6_num || reg == R6_H_num
2353 || reg == R7_num || reg == R7_H_num
2354 || reg == R8_num || reg == R8_H_num
2355 || reg == R9_num || reg == R9_H_num
2356 || reg == R10_num || reg == R10_H_num)
2357 return true;
2358
2359 if ( reg == F1_num || reg == F1_H_num
2360 || reg == F2_num || reg == F2_H_num
2361 || reg == F3_num || reg == F3_H_num
2362 || reg == F4_num || reg == F4_H_num
2363 || reg == F5_num || reg == F5_H_num
2364 || reg == F6_num || reg == F6_H_num
2365 || reg == F7_num || reg == F7_H_num
2366 || reg == F8_num || reg == F8_H_num
2367 || reg == F9_num || reg == F9_H_num
2368 || reg == F10_num || reg == F10_H_num
2369 || reg == F11_num || reg == F11_H_num
2370 || reg == F12_num || reg == F12_H_num
2371 || reg == F13_num || reg == F13_H_num)
2372 return true;
2373
2374 return false;
2375 }
2376
2377 bool Matcher::is_spillable_arg(int reg) {
2378 return can_be_java_arg(reg);
2379 }
2380
2381 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2382 return false;
2383 }
2384
2385 // Register for DIVI projection of divmodI.
2386 RegMask Matcher::divI_proj_mask() {
2387 ShouldNotReachHere();
2388 return RegMask();
2389 }
2390
2391 // Register for MODI projection of divmodI.
2392 RegMask Matcher::modI_proj_mask() {
2393 ShouldNotReachHere();
2394 return RegMask();
2395 }
2396
2397 // Register for DIVL projection of divmodL.
2398 RegMask Matcher::divL_proj_mask() {
2399 ShouldNotReachHere();
2400 return RegMask();
2401 }
2402
2403 // Register for MODL projection of divmodL.
2404 RegMask Matcher::modL_proj_mask() {
2405 ShouldNotReachHere();
2406 return RegMask();
2407 }
2408
2409 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2410 return RegMask();
2411 }
2412
2413 %}
2414
2415 //----------ENCODING BLOCK-----------------------------------------------------
2416 // This block specifies the encoding classes used by the compiler to output
2417 // byte streams. Encoding classes are parameterized macros used by
2418 // Machine Instruction Nodes in order to generate the bit encoding of the
2419 // instruction. Operands specify their base encoding interface with the
2420 // interface keyword. There are currently supported four interfaces,
2421 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2422 // operand to generate a function which returns its register number when
2423 // queried. CONST_INTER causes an operand to generate a function which
2424 // returns the value of the constant when queried. MEMORY_INTER causes an
2425 // operand to generate four functions which return the Base Register, the
2426 // Index Register, the Scale Value, and the Offset Value of the operand when
2427 // queried. COND_INTER causes an operand to generate six functions which
2428 // return the encoding code (ie - encoding bits for the instruction)
2429 // associated with each basic boolean condition for a conditional instruction.
2430 //
2431 // Instructions specify two basic values for encoding. Again, a function
2432 // is available to check if the constant displacement is an oop. They use the
2433 // ins_encode keyword to specify their encoding classes (which must be
2434 // a sequence of enc_class names, and their parameters, specified in
2435 // the encoding block), and they use the
2436 // opcode keyword to specify, in order, their primary, secondary, and
2437 // tertiary opcode. Only the opcode sections which a particular instruction
2438 // needs for encoding need to be specified.
2439 encode %{
2440 enc_class enc_unimplemented %{
2441 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2442 MacroAssembler _masm(&cbuf);
2443 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2444 %}
2445
2446 enc_class enc_untested %{
2447 #ifdef ASSERT
2448 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2449 MacroAssembler _masm(&cbuf);
2450 __ untested("Untested mach node encoding in AD file.");
2451 #else
2452 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2453 #endif
2454 %}
2455
2456 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2457 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2458 MacroAssembler _masm(&cbuf);
2459 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2460 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2461 %}
2462
2463 // Load acquire.
2464 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2465 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2466 MacroAssembler _masm(&cbuf);
2467 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2468 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2469 __ twi_0($dst$$Register);
2470 __ isync();
2471 %}
2472
2473 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2474 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2475
2476 MacroAssembler _masm(&cbuf);
2477 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2478 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2479 %}
2480
2481 // Load acquire.
2482 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2483 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2484
2485 MacroAssembler _masm(&cbuf);
2486 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2487 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2488 __ twi_0($dst$$Register);
2489 __ isync();
2490 %}
2491
2492 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2493 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2494
2495 MacroAssembler _masm(&cbuf);
2496 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2497 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2498 %}
2499
2500 // Load acquire.
2501 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2502 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2503
2504 MacroAssembler _masm(&cbuf);
2505 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2506 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2507 __ twi_0($dst$$Register);
2508 __ isync();
2509 %}
2510
2511 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2512 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2513 MacroAssembler _masm(&cbuf);
2514 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2515 // Operand 'ds' requires 4-alignment.
2516 assert((Idisp & 0x3) == 0, "unaligned offset");
2517 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2518 %}
2519
2520 // Load acquire.
2521 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2522 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2523 MacroAssembler _masm(&cbuf);
2524 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2525 // Operand 'ds' requires 4-alignment.
2526 assert((Idisp & 0x3) == 0, "unaligned offset");
2527 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2528 __ twi_0($dst$$Register);
2529 __ isync();
2530 %}
2531
2532 enc_class enc_lfd(RegF dst, memory mem) %{
2533 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2534 MacroAssembler _masm(&cbuf);
2535 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2536 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2537 %}
2538
2539 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2540 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2541
2542 MacroAssembler _masm(&cbuf);
2543 int toc_offset = 0;
2544
2545 if (!ra_->C->in_scratch_emit_size()) {
2546 address const_toc_addr;
2547 // Create a non-oop constant, no relocation needed.
2548 // If it is an IC, it has a virtual_call_Relocation.
2549 const_toc_addr = __ long_constant((jlong)$src$$constant);
2550
2551 // Get the constant's TOC offset.
2552 toc_offset = __ offset_to_method_toc(const_toc_addr);
2553
2554 // Keep the current instruction offset in mind.
2555 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2556 }
2557
2558 __ ld($dst$$Register, toc_offset, $toc$$Register);
2559 %}
2560
2561 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2562 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2563
2564 MacroAssembler _masm(&cbuf);
2565
2566 if (!ra_->C->in_scratch_emit_size()) {
2567 address const_toc_addr;
2568 // Create a non-oop constant, no relocation needed.
2569 // If it is an IC, it has a virtual_call_Relocation.
2570 const_toc_addr = __ long_constant((jlong)$src$$constant);
2571
2572 // Get the constant's TOC offset.
2573 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2574 // Store the toc offset of the constant.
2575 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2576
2577 // Also keep the current instruction offset in mind.
2578 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2579 }
2580
2581 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2582 %}
2583
2584 %} // encode
2585
2586 source %{
2587
2588 typedef struct {
2589 loadConL_hiNode *_large_hi;
2590 loadConL_loNode *_large_lo;
2591 loadConLNode *_small;
2592 MachNode *_last;
2593 } loadConLNodesTuple;
2594
2595 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2596 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2597 loadConLNodesTuple nodes;
2598
2599 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2600 if (large_constant_pool) {
2601 // Create new nodes.
2602 loadConL_hiNode *m1 = new loadConL_hiNode();
2603 loadConL_loNode *m2 = new loadConL_loNode();
2604
2605 // inputs for new nodes
2606 m1->add_req(NULL, toc);
2607 m2->add_req(NULL, m1);
2608
2609 // operands for new nodes
2610 m1->_opnds[0] = new iRegLdstOper(); // dst
2611 m1->_opnds[1] = immSrc; // src
2612 m1->_opnds[2] = new iRegPdstOper(); // toc
2613 m2->_opnds[0] = new iRegLdstOper(); // dst
2614 m2->_opnds[1] = immSrc; // src
2615 m2->_opnds[2] = new iRegLdstOper(); // base
2616
2617 // Initialize ins_attrib TOC fields.
2618 m1->_const_toc_offset = -1;
2619 m2->_const_toc_offset_hi_node = m1;
2620
2621 // Initialize ins_attrib instruction offset.
2622 m1->_cbuf_insts_offset = -1;
2623
2624 // register allocation for new nodes
2625 ra_->set_pair(m1->_idx, reg_second, reg_first);
2626 ra_->set_pair(m2->_idx, reg_second, reg_first);
2627
2628 // Create result.
2629 nodes._large_hi = m1;
2630 nodes._large_lo = m2;
2631 nodes._small = NULL;
2632 nodes._last = nodes._large_lo;
2633 assert(m2->bottom_type()->isa_long(), "must be long");
2634 } else {
2635 loadConLNode *m2 = new loadConLNode();
2636
2637 // inputs for new nodes
2638 m2->add_req(NULL, toc);
2639
2640 // operands for new nodes
2641 m2->_opnds[0] = new iRegLdstOper(); // dst
2642 m2->_opnds[1] = immSrc; // src
2643 m2->_opnds[2] = new iRegPdstOper(); // toc
2644
2645 // Initialize ins_attrib instruction offset.
2646 m2->_cbuf_insts_offset = -1;
2647
2648 // register allocation for new nodes
2649 ra_->set_pair(m2->_idx, reg_second, reg_first);
2650
2651 // Create result.
2652 nodes._large_hi = NULL;
2653 nodes._large_lo = NULL;
2654 nodes._small = m2;
2655 nodes._last = nodes._small;
2656 assert(m2->bottom_type()->isa_long(), "must be long");
2657 }
2658
2659 return nodes;
2660 }
2661
2662 %} // source
2663
2664 encode %{
2665 // Postalloc expand emitter for loading a long constant from the method's TOC.
2666 // Enc_class needed as consttanttablebase is not supported by postalloc
2667 // expand.
2668 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2669 // Create new nodes.
2670 loadConLNodesTuple loadConLNodes =
2671 loadConLNodesTuple_create(ra_, n_toc, op_src,
2672 ra_->get_reg_second(this), ra_->get_reg_first(this));
2673
2674 // Push new nodes.
2675 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2676 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2677
2678 // some asserts
2679 assert(nodes->length() >= 1, "must have created at least 1 node");
2680 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2681 %}
2682
2683 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2684 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2685
2686 MacroAssembler _masm(&cbuf);
2687 int toc_offset = 0;
2688
2689 if (!ra_->C->in_scratch_emit_size()) {
2690 intptr_t val = $src$$constant;
2691 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2692 address const_toc_addr;
2693 if (constant_reloc == relocInfo::oop_type) {
2694 // Create an oop constant and a corresponding relocation.
2695 AddressLiteral a = __ allocate_oop_address((jobject)val);
2696 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2697 __ relocate(a.rspec());
2698 } else if (constant_reloc == relocInfo::metadata_type) {
2699 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2700 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2701 __ relocate(a.rspec());
2702 } else {
2703 // Create a non-oop constant, no relocation needed.
2704 const_toc_addr = __ long_constant((jlong)$src$$constant);
2705 }
2706
2707 // Get the constant's TOC offset.
2708 toc_offset = __ offset_to_method_toc(const_toc_addr);
2709 }
2710
2711 __ ld($dst$$Register, toc_offset, $toc$$Register);
2712 %}
2713
2714 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2715 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2716
2717 MacroAssembler _masm(&cbuf);
2718 if (!ra_->C->in_scratch_emit_size()) {
2719 intptr_t val = $src$$constant;
2720 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2721 address const_toc_addr;
2722 if (constant_reloc == relocInfo::oop_type) {
2723 // Create an oop constant and a corresponding relocation.
2724 AddressLiteral a = __ allocate_oop_address((jobject)val);
2725 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2726 __ relocate(a.rspec());
2727 } else if (constant_reloc == relocInfo::metadata_type) {
2728 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2729 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2730 __ relocate(a.rspec());
2731 } else { // non-oop pointers, e.g. card mark base, heap top
2732 // Create a non-oop constant, no relocation needed.
2733 const_toc_addr = __ long_constant((jlong)$src$$constant);
2734 }
2735
2736 // Get the constant's TOC offset.
2737 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2738 // Store the toc offset of the constant.
2739 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2740 }
2741
2742 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2743 %}
2744
2745 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2746 // Enc_class needed as consttanttablebase is not supported by postalloc
2747 // expand.
2748 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2749 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2750 if (large_constant_pool) {
2751 // Create new nodes.
2752 loadConP_hiNode *m1 = new loadConP_hiNode();
2753 loadConP_loNode *m2 = new loadConP_loNode();
2754
2755 // inputs for new nodes
2756 m1->add_req(NULL, n_toc);
2757 m2->add_req(NULL, m1);
2758
2759 // operands for new nodes
2760 m1->_opnds[0] = new iRegPdstOper(); // dst
2761 m1->_opnds[1] = op_src; // src
2762 m1->_opnds[2] = new iRegPdstOper(); // toc
2763 m2->_opnds[0] = new iRegPdstOper(); // dst
2764 m2->_opnds[1] = op_src; // src
2765 m2->_opnds[2] = new iRegLdstOper(); // base
2766
2767 // Initialize ins_attrib TOC fields.
2768 m1->_const_toc_offset = -1;
2769 m2->_const_toc_offset_hi_node = m1;
2770
2771 // Register allocation for new nodes.
2772 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2773 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2774
2775 nodes->push(m1);
2776 nodes->push(m2);
2777 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2778 } else {
2779 loadConPNode *m2 = new loadConPNode();
2780
2781 // inputs for new nodes
2782 m2->add_req(NULL, n_toc);
2783
2784 // operands for new nodes
2785 m2->_opnds[0] = new iRegPdstOper(); // dst
2786 m2->_opnds[1] = op_src; // src
2787 m2->_opnds[2] = new iRegPdstOper(); // toc
2788
2789 // Register allocation for new nodes.
2790 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2791
2792 nodes->push(m2);
2793 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2794 }
2795 %}
2796
2797 // Enc_class needed as consttanttablebase is not supported by postalloc
2798 // expand.
2799 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2800 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2801
2802 MachNode *m2;
2803 if (large_constant_pool) {
2804 m2 = new loadConFCompNode();
2805 } else {
2806 m2 = new loadConFNode();
2807 }
2808 // inputs for new nodes
2809 m2->add_req(NULL, n_toc);
2810
2811 // operands for new nodes
2812 m2->_opnds[0] = op_dst;
2813 m2->_opnds[1] = op_src;
2814 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2815
2816 // register allocation for new nodes
2817 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2818 nodes->push(m2);
2819 %}
2820
2821 // Enc_class needed as consttanttablebase is not supported by postalloc
2822 // expand.
2823 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2824 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2825
2826 MachNode *m2;
2827 if (large_constant_pool) {
2828 m2 = new loadConDCompNode();
2829 } else {
2830 m2 = new loadConDNode();
2831 }
2832 // inputs for new nodes
2833 m2->add_req(NULL, n_toc);
2834
2835 // operands for new nodes
2836 m2->_opnds[0] = op_dst;
2837 m2->_opnds[1] = op_src;
2838 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2839
2840 // register allocation for new nodes
2841 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2842 nodes->push(m2);
2843 %}
2844
2845 enc_class enc_stw(iRegIsrc src, memory mem) %{
2846 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2847 MacroAssembler _masm(&cbuf);
2848 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2849 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2850 %}
2851
2852 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2853 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2854 MacroAssembler _masm(&cbuf);
2855 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2856 // Operand 'ds' requires 4-alignment.
2857 assert((Idisp & 0x3) == 0, "unaligned offset");
2858 __ std($src$$Register, Idisp, $mem$$base$$Register);
2859 %}
2860
2861 enc_class enc_stfs(RegF src, memory mem) %{
2862 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2863 MacroAssembler _masm(&cbuf);
2864 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2865 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2866 %}
2867
2868 enc_class enc_stfd(RegF src, memory mem) %{
2869 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2870 MacroAssembler _masm(&cbuf);
2871 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2872 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2873 %}
2874
2875 // Use release_store for card-marking to ensure that previous
2876 // oop-stores are visible before the card-mark change.
2877 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2878 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2879 // FIXME: Implement this as a cmove and use a fixed condition code
2880 // register which is written on every transition to compiled code,
2881 // e.g. in call-stub and when returning from runtime stubs.
2882 //
2883 // Proposed code sequence for the cmove implementation:
2884 //
2885 // Label skip_release;
2886 // __ beq(CCRfixed, skip_release);
2887 // __ release();
2888 // __ bind(skip_release);
2889 // __ stb(card mark);
2890
2891 MacroAssembler _masm(&cbuf);
2892 Label skip_storestore;
2893
2894 #if 0 // TODO: PPC port
2895 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2896 // StoreStore barrier conditionally.
2897 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2898 __ cmpwi(CCR0, R0, 0);
2899 __ beq_predict_taken(CCR0, skip_storestore);
2900 #endif
2901 __ li(R0, 0);
2902 __ membar(Assembler::StoreStore);
2903 #if 0 // TODO: PPC port
2904 __ bind(skip_storestore);
2905 #endif
2906
2907 // Do the store.
2908 if ($mem$$index == 0) {
2909 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2910 } else {
2911 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2912 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2913 }
2914 %}
2915
2916 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2917
2918 if (VM_Version::has_isel()) {
2919 // use isel instruction with Power 7
2920 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2921 encodeP_subNode *n_sub_base = new encodeP_subNode();
2922 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2923 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2924
2925 n_compare->add_req(n_region, n_src);
2926 n_compare->_opnds[0] = op_crx;
2927 n_compare->_opnds[1] = op_src;
2928 n_compare->_opnds[2] = new immL16Oper(0);
2929
2930 n_sub_base->add_req(n_region, n_src);
2931 n_sub_base->_opnds[0] = op_dst;
2932 n_sub_base->_opnds[1] = op_src;
2933 n_sub_base->_bottom_type = _bottom_type;
2934
2935 n_shift->add_req(n_region, n_sub_base);
2936 n_shift->_opnds[0] = op_dst;
2937 n_shift->_opnds[1] = op_dst;
2938 n_shift->_bottom_type = _bottom_type;
2939
2940 n_cond_set->add_req(n_region, n_compare, n_shift);
2941 n_cond_set->_opnds[0] = op_dst;
2942 n_cond_set->_opnds[1] = op_crx;
2943 n_cond_set->_opnds[2] = op_dst;
2944 n_cond_set->_bottom_type = _bottom_type;
2945
2946 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2947 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2948 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2949 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2950
2951 nodes->push(n_compare);
2952 nodes->push(n_sub_base);
2953 nodes->push(n_shift);
2954 nodes->push(n_cond_set);
2955
2956 } else {
2957 // before Power 7
2958 moveRegNode *n_move = new moveRegNode();
2959 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2960 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2961 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2962
2963 n_move->add_req(n_region, n_src);
2964 n_move->_opnds[0] = op_dst;
2965 n_move->_opnds[1] = op_src;
2966 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2967
2968 n_compare->add_req(n_region, n_src);
2969 n_compare->add_prec(n_move);
2970
2971 n_compare->_opnds[0] = op_crx;
2972 n_compare->_opnds[1] = op_src;
2973 n_compare->_opnds[2] = new immL16Oper(0);
2974
2975 n_sub_base->add_req(n_region, n_compare, n_src);
2976 n_sub_base->_opnds[0] = op_dst;
2977 n_sub_base->_opnds[1] = op_crx;
2978 n_sub_base->_opnds[2] = op_src;
2979 n_sub_base->_bottom_type = _bottom_type;
2980
2981 n_shift->add_req(n_region, n_sub_base);
2982 n_shift->_opnds[0] = op_dst;
2983 n_shift->_opnds[1] = op_dst;
2984 n_shift->_bottom_type = _bottom_type;
2985
2986 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2987 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2988 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2989 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2990
2991 nodes->push(n_move);
2992 nodes->push(n_compare);
2993 nodes->push(n_sub_base);
2994 nodes->push(n_shift);
2995 }
2996
2997 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2998 %}
2999
3000 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3001
3002 encodeP_subNode *n1 = new encodeP_subNode();
3003 n1->add_req(n_region, n_src);
3004 n1->_opnds[0] = op_dst;
3005 n1->_opnds[1] = op_src;
3006 n1->_bottom_type = _bottom_type;
3007
3008 encodeP_shiftNode *n2 = new encodeP_shiftNode();
3009 n2->add_req(n_region, n1);
3010 n2->_opnds[0] = op_dst;
3011 n2->_opnds[1] = op_dst;
3012 n2->_bottom_type = _bottom_type;
3013 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3014 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3015
3016 nodes->push(n1);
3017 nodes->push(n2);
3018 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3019 %}
3020
3021 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3022 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
3023 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
3024
3025 n_compare->add_req(n_region, n_src);
3026 n_compare->_opnds[0] = op_crx;
3027 n_compare->_opnds[1] = op_src;
3028 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
3029
3030 n_shift->add_req(n_region, n_src);
3031 n_shift->_opnds[0] = op_dst;
3032 n_shift->_opnds[1] = op_src;
3033 n_shift->_bottom_type = _bottom_type;
3034
3035 if (VM_Version::has_isel()) {
3036 // use isel instruction with Power 7
3037
3038 decodeN_addNode *n_add_base = new decodeN_addNode();
3039 n_add_base->add_req(n_region, n_shift);
3040 n_add_base->_opnds[0] = op_dst;
3041 n_add_base->_opnds[1] = op_dst;
3042 n_add_base->_bottom_type = _bottom_type;
3043
3044 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
3045 n_cond_set->add_req(n_region, n_compare, n_add_base);
3046 n_cond_set->_opnds[0] = op_dst;
3047 n_cond_set->_opnds[1] = op_crx;
3048 n_cond_set->_opnds[2] = op_dst;
3049 n_cond_set->_bottom_type = _bottom_type;
3050
3051 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3052 ra_->set_oop(n_cond_set, true);
3053
3054 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3055 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3056 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3057 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3058
3059 nodes->push(n_compare);
3060 nodes->push(n_shift);
3061 nodes->push(n_add_base);
3062 nodes->push(n_cond_set);
3063
3064 } else {
3065 // before Power 7
3066 cond_add_baseNode *n_add_base = new cond_add_baseNode();
3067
3068 n_add_base->add_req(n_region, n_compare, n_shift);
3069 n_add_base->_opnds[0] = op_dst;
3070 n_add_base->_opnds[1] = op_crx;
3071 n_add_base->_opnds[2] = op_dst;
3072 n_add_base->_bottom_type = _bottom_type;
3073
3074 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3075 ra_->set_oop(n_add_base, true);
3076
3077 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3078 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3079 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3080
3081 nodes->push(n_compare);
3082 nodes->push(n_shift);
3083 nodes->push(n_add_base);
3084 }
3085 %}
3086
3087 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3088 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3089 n1->add_req(n_region, n_src);
3090 n1->_opnds[0] = op_dst;
3091 n1->_opnds[1] = op_src;
3092 n1->_bottom_type = _bottom_type;
3093
3094 decodeN_addNode *n2 = new decodeN_addNode();
3095 n2->add_req(n_region, n1);
3096 n2->_opnds[0] = op_dst;
3097 n2->_opnds[1] = op_dst;
3098 n2->_bottom_type = _bottom_type;
3099 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3100 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3101
3102 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3103 ra_->set_oop(n2, true);
3104
3105 nodes->push(n1);
3106 nodes->push(n2);
3107 %}
3108
3109 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3110 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3111
3112 MacroAssembler _masm(&cbuf);
3113 int cc = $cmp$$cmpcode;
3114 int flags_reg = $crx$$reg;
3115 Label done;
3116 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3117 // Branch if not (cmp crx).
3118 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3119 __ mr($dst$$Register, $src$$Register);
3120 // TODO PPC port __ endgroup_if_needed(_size == 12);
3121 __ bind(done);
3122 %}
3123
3124 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3125 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3126
3127 MacroAssembler _masm(&cbuf);
3128 Label done;
3129 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3130 // Branch if not (cmp crx).
3131 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3132 __ li($dst$$Register, $src$$constant);
3133 // TODO PPC port __ endgroup_if_needed(_size == 12);
3134 __ bind(done);
3135 %}
3136
3137 // New atomics.
3138 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3139 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3140
3141 MacroAssembler _masm(&cbuf);
3142 Register Rtmp = R0;
3143 Register Rres = $res$$Register;
3144 Register Rsrc = $src$$Register;
3145 Register Rptr = $mem_ptr$$Register;
3146 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3147 Register Rold = RegCollision ? Rtmp : Rres;
3148
3149 Label Lretry;
3150 __ bind(Lretry);
3151 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3152 __ add(Rtmp, Rsrc, Rold);
3153 __ stwcx_(Rtmp, Rptr);
3154 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3155 __ bne_predict_not_taken(CCR0, Lretry);
3156 } else {
3157 __ bne( CCR0, Lretry);
3158 }
3159 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3160 __ fence();
3161 %}
3162
3163 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3164 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3165
3166 MacroAssembler _masm(&cbuf);
3167 Register Rtmp = R0;
3168 Register Rres = $res$$Register;
3169 Register Rsrc = $src$$Register;
3170 Register Rptr = $mem_ptr$$Register;
3171 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3172 Register Rold = RegCollision ? Rtmp : Rres;
3173
3174 Label Lretry;
3175 __ bind(Lretry);
3176 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3177 __ add(Rtmp, Rsrc, Rold);
3178 __ stdcx_(Rtmp, Rptr);
3179 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3180 __ bne_predict_not_taken(CCR0, Lretry);
3181 } else {
3182 __ bne( CCR0, Lretry);
3183 }
3184 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3185 __ fence();
3186 %}
3187
3188 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3189 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3190
3191 MacroAssembler _masm(&cbuf);
3192 Register Rtmp = R0;
3193 Register Rres = $res$$Register;
3194 Register Rsrc = $src$$Register;
3195 Register Rptr = $mem_ptr$$Register;
3196 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3197 Register Rold = RegCollision ? Rtmp : Rres;
3198
3199 Label Lretry;
3200 __ bind(Lretry);
3201 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3202 __ stwcx_(Rsrc, Rptr);
3203 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3204 __ bne_predict_not_taken(CCR0, Lretry);
3205 } else {
3206 __ bne( CCR0, Lretry);
3207 }
3208 if (RegCollision) __ mr(Rres, Rtmp);
3209 __ fence();
3210 %}
3211
3212 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3213 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3214
3215 MacroAssembler _masm(&cbuf);
3216 Register Rtmp = R0;
3217 Register Rres = $res$$Register;
3218 Register Rsrc = $src$$Register;
3219 Register Rptr = $mem_ptr$$Register;
3220 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3221 Register Rold = RegCollision ? Rtmp : Rres;
3222
3223 Label Lretry;
3224 __ bind(Lretry);
3225 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3226 __ stdcx_(Rsrc, Rptr);
3227 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3228 __ bne_predict_not_taken(CCR0, Lretry);
3229 } else {
3230 __ bne( CCR0, Lretry);
3231 }
3232 if (RegCollision) __ mr(Rres, Rtmp);
3233 __ fence();
3234 %}
3235
3236 // This enc_class is needed so that scheduler gets proper
3237 // input mapping for latency computation.
3238 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3239 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3240 MacroAssembler _masm(&cbuf);
3241 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3242 %}
3243
3244 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3245 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3246
3247 MacroAssembler _masm(&cbuf);
3248
3249 Label done;
3250 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3251 __ li($dst$$Register, $zero$$constant);
3252 __ beq($crx$$CondRegister, done);
3253 __ li($dst$$Register, $notzero$$constant);
3254 __ bind(done);
3255 %}
3256
3257 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3258 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3259
3260 MacroAssembler _masm(&cbuf);
3261
3262 Label done;
3263 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3264 __ li($dst$$Register, $zero$$constant);
3265 __ beq($crx$$CondRegister, done);
3266 __ li($dst$$Register, $notzero$$constant);
3267 __ bind(done);
3268 %}
3269
3270 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3271 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3272
3273 MacroAssembler _masm(&cbuf);
3274 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3275 Label done;
3276 __ bso($crx$$CondRegister, done);
3277 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3278 // TODO PPC port __ endgroup_if_needed(_size == 12);
3279 __ bind(done);
3280 %}
3281
3282 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3283 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3284
3285 MacroAssembler _masm(&cbuf);
3286 Label d; // dummy
3287 __ bind(d);
3288 Label* p = ($lbl$$label);
3289 // `p' is `NULL' when this encoding class is used only to
3290 // determine the size of the encoded instruction.
3291 Label& l = (NULL == p)? d : *(p);
3292 int cc = $cmp$$cmpcode;
3293 int flags_reg = $crx$$reg;
3294 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3295 int bhint = Assembler::bhintNoHint;
3296
3297 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3298 if (_prob <= PROB_NEVER) {
3299 bhint = Assembler::bhintIsNotTaken;
3300 } else if (_prob >= PROB_ALWAYS) {
3301 bhint = Assembler::bhintIsTaken;
3302 }
3303 }
3304
3305 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3306 cc_to_biint(cc, flags_reg),
3307 l);
3308 %}
3309
3310 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3311 // The scheduler doesn't know about branch shortening, so we set the opcode
3312 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3313 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3314
3315 MacroAssembler _masm(&cbuf);
3316 Label d; // dummy
3317 __ bind(d);
3318 Label* p = ($lbl$$label);
3319 // `p' is `NULL' when this encoding class is used only to
3320 // determine the size of the encoded instruction.
3321 Label& l = (NULL == p)? d : *(p);
3322 int cc = $cmp$$cmpcode;
3323 int flags_reg = $crx$$reg;
3324 int bhint = Assembler::bhintNoHint;
3325
3326 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3327 if (_prob <= PROB_NEVER) {
3328 bhint = Assembler::bhintIsNotTaken;
3329 } else if (_prob >= PROB_ALWAYS) {
3330 bhint = Assembler::bhintIsTaken;
3331 }
3332 }
3333
3334 // Tell the conditional far branch to optimize itself when being relocated.
3335 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3336 cc_to_biint(cc, flags_reg),
3337 l,
3338 MacroAssembler::bc_far_optimize_on_relocate);
3339 %}
3340
3341 // Branch used with Power6 scheduling (can be shortened without changing the node).
3342 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3343 // The scheduler doesn't know about branch shortening, so we set the opcode
3344 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3345 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3346
3347 MacroAssembler _masm(&cbuf);
3348 Label d; // dummy
3349 __ bind(d);
3350 Label* p = ($lbl$$label);
3351 // `p' is `NULL' when this encoding class is used only to
3352 // determine the size of the encoded instruction.
3353 Label& l = (NULL == p)? d : *(p);
3354 int cc = $cmp$$cmpcode;
3355 int flags_reg = $crx$$reg;
3356 int bhint = Assembler::bhintNoHint;
3357
3358 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3359 if (_prob <= PROB_NEVER) {
3360 bhint = Assembler::bhintIsNotTaken;
3361 } else if (_prob >= PROB_ALWAYS) {
3362 bhint = Assembler::bhintIsTaken;
3363 }
3364 }
3365
3366 #if 0 // TODO: PPC port
3367 if (_size == 8) {
3368 // Tell the conditional far branch to optimize itself when being relocated.
3369 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3370 cc_to_biint(cc, flags_reg),
3371 l,
3372 MacroAssembler::bc_far_optimize_on_relocate);
3373 } else {
3374 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3375 cc_to_biint(cc, flags_reg),
3376 l);
3377 }
3378 #endif
3379 Unimplemented();
3380 %}
3381
3382 // Postalloc expand emitter for loading a replicatef float constant from
3383 // the method's TOC.
3384 // Enc_class needed as consttanttablebase is not supported by postalloc
3385 // expand.
3386 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3387 // Create new nodes.
3388
3389 // Make an operand with the bit pattern to load as float.
3390 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3391
3392 loadConLNodesTuple loadConLNodes =
3393 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3394 ra_->get_reg_second(this), ra_->get_reg_first(this));
3395
3396 // Push new nodes.
3397 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3398 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3399
3400 assert(nodes->length() >= 1, "must have created at least 1 node");
3401 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3402 %}
3403
3404 // This enc_class is needed so that scheduler gets proper
3405 // input mapping for latency computation.
3406 enc_class enc_poll(immI dst, iRegLdst poll) %{
3407 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3408 // Fake operand dst needed for PPC scheduler.
3409 assert($dst$$constant == 0x0, "dst must be 0x0");
3410
3411 MacroAssembler _masm(&cbuf);
3412 // Mark the code position where the load from the safepoint
3413 // polling page was emitted as relocInfo::poll_type.
3414 __ relocate(relocInfo::poll_type);
3415 __ load_from_polling_page($poll$$Register);
3416 %}
3417
3418 // A Java static call or a runtime call.
3419 //
3420 // Branch-and-link relative to a trampoline.
3421 // The trampoline loads the target address and does a long branch to there.
3422 // In case we call java, the trampoline branches to a interpreter_stub
3423 // which loads the inline cache and the real call target from the constant pool.
3424 //
3425 // This basically looks like this:
3426 //
3427 // >>>> consts -+ -+
3428 // | |- offset1
3429 // [call target1] | <-+
3430 // [IC cache] |- offset2
3431 // [call target2] <--+
3432 //
3433 // <<<< consts
3434 // >>>> insts
3435 //
3436 // bl offset16 -+ -+ ??? // How many bits available?
3437 // | |
3438 // <<<< insts | |
3439 // >>>> stubs | |
3440 // | |- trampoline_stub_Reloc
3441 // trampoline stub: | <-+
3442 // r2 = toc |
3443 // r2 = [r2 + offset1] | // Load call target1 from const section
3444 // mtctr r2 |
3445 // bctr |- static_stub_Reloc
3446 // comp_to_interp_stub: <---+
3447 // r1 = toc
3448 // ICreg = [r1 + IC_offset] // Load IC from const section
3449 // r1 = [r1 + offset2] // Load call target2 from const section
3450 // mtctr r1
3451 // bctr
3452 //
3453 // <<<< stubs
3454 //
3455 // The call instruction in the code either
3456 // - Branches directly to a compiled method if the offset is encodable in instruction.
3457 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3458 // - Branches to the compiled_to_interp stub if the target is interpreted.
3459 //
3460 // Further there are three relocations from the loads to the constants in
3461 // the constant section.
3462 //
3463 // Usage of r1 and r2 in the stubs allows to distinguish them.
3464 enc_class enc_java_static_call(method meth) %{
3465 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3466
3467 MacroAssembler _masm(&cbuf);
3468 address entry_point = (address)$meth$$method;
3469
3470 if (!_method) {
3471 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3472 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3473 } else {
3474 // Remember the offset not the address.
3475 const int start_offset = __ offset();
3476 // The trampoline stub.
3477 if (!Compile::current()->in_scratch_emit_size()) {
3478 // No entry point given, use the current pc.
3479 // Make sure branch fits into
3480 if (entry_point == 0) entry_point = __ pc();
3481
3482 // Put the entry point as a constant into the constant pool.
3483 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3484 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3485
3486 // Emit the trampoline stub which will be related to the branch-and-link below.
3487 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3488 if (Compile::current()->env()->failing()) { return; } // Code cache may be full.
3489 __ relocate(_optimized_virtual ?
3490 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3491 }
3492
3493 // The real call.
3494 // Note: At this point we do not have the address of the trampoline
3495 // stub, and the entry point might be too far away for bl, so __ pc()
3496 // serves as dummy and the bl will be patched later.
3497 cbuf.set_insts_mark();
3498 __ bl(__ pc()); // Emits a relocation.
3499
3500 // The stub for call to interpreter.
3501 CompiledStaticCall::emit_to_interp_stub(cbuf);
3502 }
3503 %}
3504
3505 // Emit a method handle call.
3506 //
3507 // Method handle calls from compiled to compiled are going thru a
3508 // c2i -> i2c adapter, extending the frame for their arguments. The
3509 // caller however, returns directly to the compiled callee, that has
3510 // to cope with the extended frame. We restore the original frame by
3511 // loading the callers sp and adding the calculated framesize.
3512 enc_class enc_java_handle_call(method meth) %{
3513 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3514
3515 MacroAssembler _masm(&cbuf);
3516 address entry_point = (address)$meth$$method;
3517
3518 // Remember the offset not the address.
3519 const int start_offset = __ offset();
3520 // The trampoline stub.
3521 if (!ra_->C->in_scratch_emit_size()) {
3522 // No entry point given, use the current pc.
3523 // Make sure branch fits into
3524 if (entry_point == 0) entry_point = __ pc();
3525
3526 // Put the entry point as a constant into the constant pool.
3527 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3528 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3529
3530 // Emit the trampoline stub which will be related to the branch-and-link below.
3531 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3532 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3533 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3534 __ relocate(relocInfo::opt_virtual_call_type);
3535 }
3536
3537 // The real call.
3538 // Note: At this point we do not have the address of the trampoline
3539 // stub, and the entry point might be too far away for bl, so __ pc()
3540 // serves as dummy and the bl will be patched later.
3541 cbuf.set_insts_mark();
3542 __ bl(__ pc()); // Emits a relocation.
3543
3544 assert(_method, "execute next statement conditionally");
3545 // The stub for call to interpreter.
3546 CompiledStaticCall::emit_to_interp_stub(cbuf);
3547
3548 // Restore original sp.
3549 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3550 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3551 unsigned int bytes = (unsigned int)framesize;
3552 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3553 if (Assembler::is_simm(-offset, 16)) {
3554 __ addi(R1_SP, R11_scratch1, -offset);
3555 } else {
3556 __ load_const_optimized(R12_scratch2, -offset);
3557 __ add(R1_SP, R11_scratch1, R12_scratch2);
3558 }
3559 #ifdef ASSERT
3560 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3561 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3562 __ asm_assert_eq("backlink changed", 0x8000);
3563 #endif
3564 // If fails should store backlink before unextending.
3565
3566 if (ra_->C->env()->failing()) {
3567 return;
3568 }
3569 %}
3570
3571 // Second node of expanded dynamic call - the call.
3572 enc_class enc_java_dynamic_call_sched(method meth) %{
3573 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3574
3575 MacroAssembler _masm(&cbuf);
3576
3577 if (!ra_->C->in_scratch_emit_size()) {
3578 // Create a call trampoline stub for the given method.
3579 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3580 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3581 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3582 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3583 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3584
3585 // Build relocation at call site with ic position as data.
3586 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3587 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3588 "must have one, but can't have both");
3589 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3590 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3591 "must contain instruction offset");
3592 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3593 ? _load_ic_hi_node->_cbuf_insts_offset
3594 : _load_ic_node->_cbuf_insts_offset;
3595 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3596 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3597 "should be load from TOC");
3598
3599 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3600 }
3601
3602 // At this point I do not have the address of the trampoline stub,
3603 // and the entry point might be too far away for bl. Pc() serves
3604 // as dummy and bl will be patched later.
3605 __ bl((address) __ pc());
3606 %}
3607
3608 // postalloc expand emitter for virtual calls.
3609 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3610
3611 // Create the nodes for loading the IC from the TOC.
3612 loadConLNodesTuple loadConLNodes_IC =
3613 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3614 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3615
3616 // Create the call node.
3617 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3618 call->_method_handle_invoke = _method_handle_invoke;
3619 call->_vtable_index = _vtable_index;
3620 call->_method = _method;
3621 call->_bci = _bci;
3622 call->_optimized_virtual = _optimized_virtual;
3623 call->_tf = _tf;
3624 call->_entry_point = _entry_point;
3625 call->_cnt = _cnt;
3626 call->_argsize = _argsize;
3627 call->_oop_map = _oop_map;
3628 call->_jvms = _jvms;
3629 call->_jvmadj = _jvmadj;
3630 call->_in_rms = _in_rms;
3631 call->_nesting = _nesting;
3632
3633 // New call needs all inputs of old call.
3634 // Req...
3635 for (uint i = 0; i < req(); ++i) {
3636 // The expanded node does not need toc any more.
3637 // Add the inline cache constant here instead. This expresses the
3638 // register of the inline cache must be live at the call.
3639 // Else we would have to adapt JVMState by -1.
3640 if (i == mach_constant_base_node_input()) {
3641 call->add_req(loadConLNodes_IC._last);
3642 } else {
3643 call->add_req(in(i));
3644 }
3645 }
3646 // ...as well as prec
3647 for (uint i = req(); i < len(); ++i) {
3648 call->add_prec(in(i));
3649 }
3650
3651 // Remember nodes loading the inline cache into r19.
3652 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3653 call->_load_ic_node = loadConLNodes_IC._small;
3654
3655 // Operands for new nodes.
3656 call->_opnds[0] = _opnds[0];
3657 call->_opnds[1] = _opnds[1];
3658
3659 // Only the inline cache is associated with a register.
3660 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3661
3662 // Push new nodes.
3663 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3664 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3665 nodes->push(call);
3666 %}
3667
3668 // Compound version of call dynamic
3669 // Toc is only passed so that it can be used in ins_encode statement.
3670 // In the code we have to use $constanttablebase.
3671 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3672 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3673 MacroAssembler _masm(&cbuf);
3674 int start_offset = __ offset();
3675
3676 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3677 #if 0
3678 int vtable_index = this->_vtable_index;
3679 if (_vtable_index < 0) {
3680 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3681 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3682 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3683
3684 // Virtual call relocation will point to ic load.
3685 address virtual_call_meta_addr = __ pc();
3686 // Load a clear inline cache.
3687 AddressLiteral empty_ic((address) Universe::non_oop_word());
3688 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3689 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3690 // to determine who we intended to call.
3691 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3692 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3693 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3694 "Fix constant in ret_addr_offset()");
3695 } else {
3696 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3697 // Go thru the vtable. Get receiver klass. Receiver already
3698 // checked for non-null. If we'll go thru a C2I adapter, the
3699 // interpreter expects method in R19_method.
3700
3701 __ load_klass(R11_scratch1, R3);
3702
3703 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3704 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3705 __ li(R19_method, v_off);
3706 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3707 // NOTE: for vtable dispatches, the vtable entry will never be
3708 // null. However it may very well end up in handle_wrong_method
3709 // if the method is abstract for the particular class.
3710 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3711 // Call target. Either compiled code or C2I adapter.
3712 __ mtctr(R11_scratch1);
3713 __ bctrl();
3714 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3715 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3716 }
3717 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3718 "Fix constant in ret_addr_offset()");
3719 }
3720 #endif
3721 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3722 %}
3723
3724 // a runtime call
3725 enc_class enc_java_to_runtime_call (method meth) %{
3726 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3727
3728 MacroAssembler _masm(&cbuf);
3729 const address start_pc = __ pc();
3730
3731 #if defined(ABI_ELFv2)
3732 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3733 __ call_c(entry, relocInfo::runtime_call_type);
3734 #else
3735 // The function we're going to call.
3736 FunctionDescriptor fdtemp;
3737 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3738
3739 Register Rtoc = R12_scratch2;
3740 // Calculate the method's TOC.
3741 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3742 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3743 // pool entries; call_c_using_toc will optimize the call.
3744 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3745 #endif
3746
3747 // Check the ret_addr_offset.
3748 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3749 "Fix constant in ret_addr_offset()");
3750 %}
3751
3752 // Move to ctr for leaf call.
3753 // This enc_class is needed so that scheduler gets proper
3754 // input mapping for latency computation.
3755 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3756 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3757 MacroAssembler _masm(&cbuf);
3758 __ mtctr($src$$Register);
3759 %}
3760
3761 // Postalloc expand emitter for runtime leaf calls.
3762 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3763 loadConLNodesTuple loadConLNodes_Entry;
3764 #if defined(ABI_ELFv2)
3765 jlong entry_address = (jlong) this->entry_point();
3766 assert(entry_address, "need address here");
3767 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3768 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3769 #else
3770 // Get the struct that describes the function we are about to call.
3771 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3772 assert(fd, "need fd here");
3773 jlong entry_address = (jlong) fd->entry();
3774 // new nodes
3775 loadConLNodesTuple loadConLNodes_Env;
3776 loadConLNodesTuple loadConLNodes_Toc;
3777
3778 // Create nodes and operands for loading the entry point.
3779 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3780 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3781
3782
3783 // Create nodes and operands for loading the env pointer.
3784 if (fd->env() != NULL) {
3785 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3786 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3787 } else {
3788 loadConLNodes_Env._large_hi = NULL;
3789 loadConLNodes_Env._large_lo = NULL;
3790 loadConLNodes_Env._small = NULL;
3791 loadConLNodes_Env._last = new loadConL16Node();
3792 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3793 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3794 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3795 }
3796
3797 // Create nodes and operands for loading the Toc point.
3798 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3799 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3800 #endif // ABI_ELFv2
3801 // mtctr node
3802 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3803
3804 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3805 mtctr->add_req(0, loadConLNodes_Entry._last);
3806
3807 mtctr->_opnds[0] = new iRegLdstOper();
3808 mtctr->_opnds[1] = new iRegLdstOper();
3809
3810 // call node
3811 MachCallLeafNode *call = new CallLeafDirectNode();
3812
3813 call->_opnds[0] = _opnds[0];
3814 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3815
3816 // Make the new call node look like the old one.
3817 call->_name = _name;
3818 call->_tf = _tf;
3819 call->_entry_point = _entry_point;
3820 call->_cnt = _cnt;
3821 call->_argsize = _argsize;
3822 call->_oop_map = _oop_map;
3823 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3824 call->_jvms = NULL;
3825 call->_jvmadj = _jvmadj;
3826 call->_in_rms = _in_rms;
3827 call->_nesting = _nesting;
3828
3829
3830 // New call needs all inputs of old call.
3831 // Req...
3832 for (uint i = 0; i < req(); ++i) {
3833 if (i != mach_constant_base_node_input()) {
3834 call->add_req(in(i));
3835 }
3836 }
3837
3838 // These must be reqired edges, as the registers are live up to
3839 // the call. Else the constants are handled as kills.
3840 call->add_req(mtctr);
3841 #if !defined(ABI_ELFv2)
3842 call->add_req(loadConLNodes_Env._last);
3843 call->add_req(loadConLNodes_Toc._last);
3844 #endif
3845
3846 // ...as well as prec
3847 for (uint i = req(); i < len(); ++i) {
3848 call->add_prec(in(i));
3849 }
3850
3851 // registers
3852 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3853
3854 // Insert the new nodes.
3855 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3856 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3857 #if !defined(ABI_ELFv2)
3858 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3859 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3860 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3861 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3862 #endif
3863 nodes->push(mtctr);
3864 nodes->push(call);
3865 %}
3866 %}
3867
3868 //----------FRAME--------------------------------------------------------------
3869 // Definition of frame structure and management information.
3870
3871 frame %{
3872 // What direction does stack grow in (assumed to be same for native & Java).
3873 stack_direction(TOWARDS_LOW);
3874
3875 // These two registers define part of the calling convention between
3876 // compiled code and the interpreter.
3877
3878 // Inline Cache Register or method for I2C.
3879 inline_cache_reg(R19); // R19_method
3880
3881 // Method Oop Register when calling interpreter.
3882 interpreter_method_oop_reg(R19); // R19_method
3883
3884 // Optional: name the operand used by cisc-spilling to access
3885 // [stack_pointer + offset].
3886 cisc_spilling_operand_name(indOffset);
3887
3888 // Number of stack slots consumed by a Monitor enter.
3889 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3890
3891 // Compiled code's Frame Pointer.
3892 frame_pointer(R1); // R1_SP
3893
3894 // Interpreter stores its frame pointer in a register which is
3895 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3896 // interpreted java to compiled java.
3897 //
3898 // R14_state holds pointer to caller's cInterpreter.
3899 interpreter_frame_pointer(R14); // R14_state
3900
3901 stack_alignment(frame::alignment_in_bytes);
3902
3903 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3904
3905 // Number of outgoing stack slots killed above the
3906 // out_preserve_stack_slots for calls to C. Supports the var-args
3907 // backing area for register parms.
3908 //
3909 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3910
3911 // The after-PROLOG location of the return address. Location of
3912 // return address specifies a type (REG or STACK) and a number
3913 // representing the register number (i.e. - use a register name) or
3914 // stack slot.
3915 //
3916 // A: Link register is stored in stack slot ...
3917 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3918 // J: Therefore, we make sure that the link register is also in R11_scratch1
3919 // at the end of the prolog.
3920 // B: We use R20, now.
3921 //return_addr(REG R20);
3922
3923 // G: After reading the comments made by all the luminaries on their
3924 // failure to tell the compiler where the return address really is,
3925 // I hardly dare to try myself. However, I'm convinced it's in slot
3926 // 4 what apparently works and saves us some spills.
3927 return_addr(STACK 4);
3928
3929 // This is the body of the function
3930 //
3931 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3932 // uint length, // length of array
3933 // bool is_outgoing)
3934 //
3935 // The `sig' array is to be updated. sig[j] represents the location
3936 // of the j-th argument, either a register or a stack slot.
3937
3938 // Comment taken from i486.ad:
3939 // Body of function which returns an integer array locating
3940 // arguments either in registers or in stack slots. Passed an array
3941 // of ideal registers called "sig" and a "length" count. Stack-slot
3942 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3943 // arguments for a CALLEE. Incoming stack arguments are
3944 // automatically biased by the preserve_stack_slots field above.
3945 calling_convention %{
3946 // No difference between ingoing/outgoing. Just pass false.
3947 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3948 %}
3949
3950 // Comment taken from i486.ad:
3951 // Body of function which returns an integer array locating
3952 // arguments either in registers or in stack slots. Passed an array
3953 // of ideal registers called "sig" and a "length" count. Stack-slot
3954 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3955 // arguments for a CALLEE. Incoming stack arguments are
3956 // automatically biased by the preserve_stack_slots field above.
3957 c_calling_convention %{
3958 // This is obviously always outgoing.
3959 // C argument in register AND stack slot.
3960 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3961 %}
3962
3963 // Location of native (C/C++) and interpreter return values. This
3964 // is specified to be the same as Java. In the 32-bit VM, long
3965 // values are actually returned from native calls in O0:O1 and
3966 // returned to the interpreter in I0:I1. The copying to and from
3967 // the register pairs is done by the appropriate call and epilog
3968 // opcodes. This simplifies the register allocator.
3969 c_return_value %{
3970 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3971 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3972 "only return normal values");
3973 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3974 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3975 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3976 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3977 %}
3978
3979 // Location of compiled Java return values. Same as C
3980 return_value %{
3981 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3982 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3983 "only return normal values");
3984 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3985 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3986 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3987 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3988 %}
3989 %}
3990
3991
3992 //----------ATTRIBUTES---------------------------------------------------------
3993
3994 //----------Operand Attributes-------------------------------------------------
3995 op_attrib op_cost(1); // Required cost attribute.
3996
3997 //----------Instruction Attributes---------------------------------------------
3998
3999 // Cost attribute. required.
4000 ins_attrib ins_cost(DEFAULT_COST);
4001
4002 // Is this instruction a non-matching short branch variant of some
4003 // long branch? Not required.
4004 ins_attrib ins_short_branch(0);
4005
4006 ins_attrib ins_is_TrapBasedCheckNode(true);
4007
4008 // Number of constants.
4009 // This instruction uses the given number of constants
4010 // (optional attribute).
4011 // This is needed to determine in time whether the constant pool will
4012 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4013 // is determined. It's also used to compute the constant pool size
4014 // in Output().
4015 ins_attrib ins_num_consts(0);
4016
4017 // Required alignment attribute (must be a power of 2) specifies the
4018 // alignment that some part of the instruction (not necessarily the
4019 // start) requires. If > 1, a compute_padding() function must be
4020 // provided for the instruction.
4021 ins_attrib ins_alignment(1);
4022
4023 // Enforce/prohibit rematerializations.
4024 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4025 // then rematerialization of that instruction is prohibited and the
4026 // instruction's value will be spilled if necessary.
4027 // Causes that MachNode::rematerialize() returns false.
4028 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4029 // then rematerialization should be enforced and a copy of the instruction
4030 // should be inserted if possible; rematerialization is not guaranteed.
4031 // Note: this may result in rematerializations in front of every use.
4032 // Causes that MachNode::rematerialize() can return true.
4033 // (optional attribute)
4034 ins_attrib ins_cannot_rematerialize(false);
4035 ins_attrib ins_should_rematerialize(false);
4036
4037 // Instruction has variable size depending on alignment.
4038 ins_attrib ins_variable_size_depending_on_alignment(false);
4039
4040 // Instruction is a nop.
4041 ins_attrib ins_is_nop(false);
4042
4043 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4044 ins_attrib ins_use_mach_if_fast_lock_node(false);
4045
4046 // Field for the toc offset of a constant.
4047 //
4048 // This is needed if the toc offset is not encodable as an immediate in
4049 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4050 // added to the toc, and from this a load with immediate is performed.
4051 // With postalloc expand, we get two nodes that require the same offset
4052 // but which don't know about each other. The offset is only known
4053 // when the constant is added to the constant pool during emitting.
4054 // It is generated in the 'hi'-node adding the upper bits, and saved
4055 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4056 // the offset from there when it gets encoded.
4057 ins_attrib ins_field_const_toc_offset(0);
4058 ins_attrib ins_field_const_toc_offset_hi_node(0);
4059
4060 // A field that can hold the instructions offset in the code buffer.
4061 // Set in the nodes emitter.
4062 ins_attrib ins_field_cbuf_insts_offset(-1);
4063
4064 // Fields for referencing a call's load-IC-node.
4065 // If the toc offset can not be encoded as an immediate in a load, we
4066 // use two nodes.
4067 ins_attrib ins_field_load_ic_hi_node(0);
4068 ins_attrib ins_field_load_ic_node(0);
4069
4070 //----------OPERANDS-----------------------------------------------------------
4071 // Operand definitions must precede instruction definitions for correct
4072 // parsing in the ADLC because operands constitute user defined types
4073 // which are used in instruction definitions.
4074 //
4075 // Formats are generated automatically for constants and base registers.
4076
4077 //----------Simple Operands----------------------------------------------------
4078 // Immediate Operands
4079
4080 // Integer Immediate: 32-bit
4081 operand immI() %{
4082 match(ConI);
4083 op_cost(40);
4084 format %{ %}
4085 interface(CONST_INTER);
4086 %}
4087
4088 operand immI8() %{
4089 predicate(Assembler::is_simm(n->get_int(), 8));
4090 op_cost(0);
4091 match(ConI);
4092 format %{ %}
4093 interface(CONST_INTER);
4094 %}
4095
4096 // Integer Immediate: 16-bit
4097 operand immI16() %{
4098 predicate(Assembler::is_simm(n->get_int(), 16));
4099 op_cost(0);
4100 match(ConI);
4101 format %{ %}
4102 interface(CONST_INTER);
4103 %}
4104
4105 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4106 operand immIhi16() %{
4107 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4108 match(ConI);
4109 op_cost(0);
4110 format %{ %}
4111 interface(CONST_INTER);
4112 %}
4113
4114 operand immInegpow2() %{
4115 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4116 match(ConI);
4117 op_cost(0);
4118 format %{ %}
4119 interface(CONST_INTER);
4120 %}
4121
4122 operand immIpow2minus1() %{
4123 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4124 match(ConI);
4125 op_cost(0);
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4129
4130 operand immIpowerOf2() %{
4131 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4132 match(ConI);
4133 op_cost(0);
4134 format %{ %}
4135 interface(CONST_INTER);
4136 %}
4137
4138 // Unsigned Integer Immediate: the values 0-31
4139 operand uimmI5() %{
4140 predicate(Assembler::is_uimm(n->get_int(), 5));
4141 match(ConI);
4142 op_cost(0);
4143 format %{ %}
4144 interface(CONST_INTER);
4145 %}
4146
4147 // Unsigned Integer Immediate: 6-bit
4148 operand uimmI6() %{
4149 predicate(Assembler::is_uimm(n->get_int(), 6));
4150 match(ConI);
4151 op_cost(0);
4152 format %{ %}
4153 interface(CONST_INTER);
4154 %}
4155
4156 // Unsigned Integer Immediate: 6-bit int, greater than 32
4157 operand uimmI6_ge32() %{
4158 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4159 match(ConI);
4160 op_cost(0);
4161 format %{ %}
4162 interface(CONST_INTER);
4163 %}
4164
4165 // Unsigned Integer Immediate: 15-bit
4166 operand uimmI15() %{
4167 predicate(Assembler::is_uimm(n->get_int(), 15));
4168 match(ConI);
4169 op_cost(0);
4170 format %{ %}
4171 interface(CONST_INTER);
4172 %}
4173
4174 // Unsigned Integer Immediate: 16-bit
4175 operand uimmI16() %{
4176 predicate(Assembler::is_uimm(n->get_int(), 16));
4177 match(ConI);
4178 op_cost(0);
4179 format %{ %}
4180 interface(CONST_INTER);
4181 %}
4182
4183 // constant 'int 0'.
4184 operand immI_0() %{
4185 predicate(n->get_int() == 0);
4186 match(ConI);
4187 op_cost(0);
4188 format %{ %}
4189 interface(CONST_INTER);
4190 %}
4191
4192 // constant 'int 1'.
4193 operand immI_1() %{
4194 predicate(n->get_int() == 1);
4195 match(ConI);
4196 op_cost(0);
4197 format %{ %}
4198 interface(CONST_INTER);
4199 %}
4200
4201 // constant 'int -1'.
4202 operand immI_minus1() %{
4203 predicate(n->get_int() == -1);
4204 match(ConI);
4205 op_cost(0);
4206 format %{ %}
4207 interface(CONST_INTER);
4208 %}
4209
4210 // int value 16.
4211 operand immI_16() %{
4212 predicate(n->get_int() == 16);
4213 match(ConI);
4214 op_cost(0);
4215 format %{ %}
4216 interface(CONST_INTER);
4217 %}
4218
4219 // int value 24.
4220 operand immI_24() %{
4221 predicate(n->get_int() == 24);
4222 match(ConI);
4223 op_cost(0);
4224 format %{ %}
4225 interface(CONST_INTER);
4226 %}
4227
4228 // Compressed oops constants
4229 // Pointer Immediate
4230 operand immN() %{
4231 match(ConN);
4232
4233 op_cost(10);
4234 format %{ %}
4235 interface(CONST_INTER);
4236 %}
4237
4238 // NULL Pointer Immediate
4239 operand immN_0() %{
4240 predicate(n->get_narrowcon() == 0);
4241 match(ConN);
4242
4243 op_cost(0);
4244 format %{ %}
4245 interface(CONST_INTER);
4246 %}
4247
4248 // Compressed klass constants
4249 operand immNKlass() %{
4250 match(ConNKlass);
4251
4252 op_cost(0);
4253 format %{ %}
4254 interface(CONST_INTER);
4255 %}
4256
4257 // This operand can be used to avoid matching of an instruct
4258 // with chain rule.
4259 operand immNKlass_NM() %{
4260 match(ConNKlass);
4261 predicate(false);
4262 op_cost(0);
4263 format %{ %}
4264 interface(CONST_INTER);
4265 %}
4266
4267 // Pointer Immediate: 64-bit
4268 operand immP() %{
4269 match(ConP);
4270 op_cost(0);
4271 format %{ %}
4272 interface(CONST_INTER);
4273 %}
4274
4275 // Operand to avoid match of loadConP.
4276 // This operand can be used to avoid matching of an instruct
4277 // with chain rule.
4278 operand immP_NM() %{
4279 match(ConP);
4280 predicate(false);
4281 op_cost(0);
4282 format %{ %}
4283 interface(CONST_INTER);
4284 %}
4285
4286 // costant 'pointer 0'.
4287 operand immP_0() %{
4288 predicate(n->get_ptr() == 0);
4289 match(ConP);
4290 op_cost(0);
4291 format %{ %}
4292 interface(CONST_INTER);
4293 %}
4294
4295 // pointer 0x0 or 0x1
4296 operand immP_0or1() %{
4297 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4298 match(ConP);
4299 op_cost(0);
4300 format %{ %}
4301 interface(CONST_INTER);
4302 %}
4303
4304 operand immL() %{
4305 match(ConL);
4306 op_cost(40);
4307 format %{ %}
4308 interface(CONST_INTER);
4309 %}
4310
4311 // Long Immediate: 16-bit
4312 operand immL16() %{
4313 predicate(Assembler::is_simm(n->get_long(), 16));
4314 match(ConL);
4315 op_cost(0);
4316 format %{ %}
4317 interface(CONST_INTER);
4318 %}
4319
4320 // Long Immediate: 16-bit, 4-aligned
4321 operand immL16Alg4() %{
4322 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4323 match(ConL);
4324 op_cost(0);
4325 format %{ %}
4326 interface(CONST_INTER);
4327 %}
4328
4329 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4330 operand immL32hi16() %{
4331 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4332 match(ConL);
4333 op_cost(0);
4334 format %{ %}
4335 interface(CONST_INTER);
4336 %}
4337
4338 // Long Immediate: 32-bit
4339 operand immL32() %{
4340 predicate(Assembler::is_simm(n->get_long(), 32));
4341 match(ConL);
4342 op_cost(0);
4343 format %{ %}
4344 interface(CONST_INTER);
4345 %}
4346
4347 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4348 operand immLhighest16() %{
4349 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4350 match(ConL);
4351 op_cost(0);
4352 format %{ %}
4353 interface(CONST_INTER);
4354 %}
4355
4356 operand immLnegpow2() %{
4357 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4358 match(ConL);
4359 op_cost(0);
4360 format %{ %}
4361 interface(CONST_INTER);
4362 %}
4363
4364 operand immLpow2minus1() %{
4365 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4366 (n->get_long() != (jlong)0xffffffffffffffffL));
4367 match(ConL);
4368 op_cost(0);
4369 format %{ %}
4370 interface(CONST_INTER);
4371 %}
4372
4373 // constant 'long 0'.
4374 operand immL_0() %{
4375 predicate(n->get_long() == 0L);
4376 match(ConL);
4377 op_cost(0);
4378 format %{ %}
4379 interface(CONST_INTER);
4380 %}
4381
4382 // constat ' long -1'.
4383 operand immL_minus1() %{
4384 predicate(n->get_long() == -1L);
4385 match(ConL);
4386 op_cost(0);
4387 format %{ %}
4388 interface(CONST_INTER);
4389 %}
4390
4391 // Long Immediate: low 32-bit mask
4392 operand immL_32bits() %{
4393 predicate(n->get_long() == 0xFFFFFFFFL);
4394 match(ConL);
4395 op_cost(0);
4396 format %{ %}
4397 interface(CONST_INTER);
4398 %}
4399
4400 // Unsigned Long Immediate: 16-bit
4401 operand uimmL16() %{
4402 predicate(Assembler::is_uimm(n->get_long(), 16));
4403 match(ConL);
4404 op_cost(0);
4405 format %{ %}
4406 interface(CONST_INTER);
4407 %}
4408
4409 // Float Immediate
4410 operand immF() %{
4411 match(ConF);
4412 op_cost(40);
4413 format %{ %}
4414 interface(CONST_INTER);
4415 %}
4416
4417 // constant 'float +0.0'.
4418 operand immF_0() %{
4419 predicate((n->getf() == 0) &&
4420 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4421 match(ConF);
4422 op_cost(0);
4423 format %{ %}
4424 interface(CONST_INTER);
4425 %}
4426
4427 // Double Immediate
4428 operand immD() %{
4429 match(ConD);
4430 op_cost(40);
4431 format %{ %}
4432 interface(CONST_INTER);
4433 %}
4434
4435 // Integer Register Operands
4436 // Integer Destination Register
4437 // See definition of reg_class bits32_reg_rw.
4438 operand iRegIdst() %{
4439 constraint(ALLOC_IN_RC(bits32_reg_rw));
4440 match(RegI);
4441 match(rscratch1RegI);
4442 match(rscratch2RegI);
4443 match(rarg1RegI);
4444 match(rarg2RegI);
4445 match(rarg3RegI);
4446 match(rarg4RegI);
4447 format %{ %}
4448 interface(REG_INTER);
4449 %}
4450
4451 // Integer Source Register
4452 // See definition of reg_class bits32_reg_ro.
4453 operand iRegIsrc() %{
4454 constraint(ALLOC_IN_RC(bits32_reg_ro));
4455 match(RegI);
4456 match(rscratch1RegI);
4457 match(rscratch2RegI);
4458 match(rarg1RegI);
4459 match(rarg2RegI);
4460 match(rarg3RegI);
4461 match(rarg4RegI);
4462 format %{ %}
4463 interface(REG_INTER);
4464 %}
4465
4466 operand rscratch1RegI() %{
4467 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4468 match(iRegIdst);
4469 format %{ %}
4470 interface(REG_INTER);
4471 %}
4472
4473 operand rscratch2RegI() %{
4474 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4475 match(iRegIdst);
4476 format %{ %}
4477 interface(REG_INTER);
4478 %}
4479
4480 operand rarg1RegI() %{
4481 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4482 match(iRegIdst);
4483 format %{ %}
4484 interface(REG_INTER);
4485 %}
4486
4487 operand rarg2RegI() %{
4488 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4489 match(iRegIdst);
4490 format %{ %}
4491 interface(REG_INTER);
4492 %}
4493
4494 operand rarg3RegI() %{
4495 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4496 match(iRegIdst);
4497 format %{ %}
4498 interface(REG_INTER);
4499 %}
4500
4501 operand rarg4RegI() %{
4502 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4503 match(iRegIdst);
4504 format %{ %}
4505 interface(REG_INTER);
4506 %}
4507
4508 operand rarg1RegL() %{
4509 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4510 match(iRegLdst);
4511 format %{ %}
4512 interface(REG_INTER);
4513 %}
4514
4515 operand rarg2RegL() %{
4516 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4517 match(iRegLdst);
4518 format %{ %}
4519 interface(REG_INTER);
4520 %}
4521
4522 operand rarg3RegL() %{
4523 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4524 match(iRegLdst);
4525 format %{ %}
4526 interface(REG_INTER);
4527 %}
4528
4529 operand rarg4RegL() %{
4530 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4531 match(iRegLdst);
4532 format %{ %}
4533 interface(REG_INTER);
4534 %}
4535
4536 // Pointer Destination Register
4537 // See definition of reg_class bits64_reg_rw.
4538 operand iRegPdst() %{
4539 constraint(ALLOC_IN_RC(bits64_reg_rw));
4540 match(RegP);
4541 match(rscratch1RegP);
4542 match(rscratch2RegP);
4543 match(rarg1RegP);
4544 match(rarg2RegP);
4545 match(rarg3RegP);
4546 match(rarg4RegP);
4547 format %{ %}
4548 interface(REG_INTER);
4549 %}
4550
4551 // Pointer Destination Register
4552 // Operand not using r11 and r12 (killed in epilog).
4553 operand iRegPdstNoScratch() %{
4554 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4555 match(RegP);
4556 match(rarg1RegP);
4557 match(rarg2RegP);
4558 match(rarg3RegP);
4559 match(rarg4RegP);
4560 format %{ %}
4561 interface(REG_INTER);
4562 %}
4563
4564 // Pointer Source Register
4565 // See definition of reg_class bits64_reg_ro.
4566 operand iRegPsrc() %{
4567 constraint(ALLOC_IN_RC(bits64_reg_ro));
4568 match(RegP);
4569 match(iRegPdst);
4570 match(rscratch1RegP);
4571 match(rscratch2RegP);
4572 match(rarg1RegP);
4573 match(rarg2RegP);
4574 match(rarg3RegP);
4575 match(rarg4RegP);
4576 match(threadRegP);
4577 format %{ %}
4578 interface(REG_INTER);
4579 %}
4580
4581 // Thread operand.
4582 operand threadRegP() %{
4583 constraint(ALLOC_IN_RC(thread_bits64_reg));
4584 match(iRegPdst);
4585 format %{ "R16" %}
4586 interface(REG_INTER);
4587 %}
4588
4589 operand rscratch1RegP() %{
4590 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4591 match(iRegPdst);
4592 format %{ "R11" %}
4593 interface(REG_INTER);
4594 %}
4595
4596 operand rscratch2RegP() %{
4597 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4598 match(iRegPdst);
4599 format %{ %}
4600 interface(REG_INTER);
4601 %}
4602
4603 operand rarg1RegP() %{
4604 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4605 match(iRegPdst);
4606 format %{ %}
4607 interface(REG_INTER);
4608 %}
4609
4610 operand rarg2RegP() %{
4611 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4612 match(iRegPdst);
4613 format %{ %}
4614 interface(REG_INTER);
4615 %}
4616
4617 operand rarg3RegP() %{
4618 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4619 match(iRegPdst);
4620 format %{ %}
4621 interface(REG_INTER);
4622 %}
4623
4624 operand rarg4RegP() %{
4625 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4626 match(iRegPdst);
4627 format %{ %}
4628 interface(REG_INTER);
4629 %}
4630
4631 operand iRegNsrc() %{
4632 constraint(ALLOC_IN_RC(bits32_reg_ro));
4633 match(RegN);
4634 match(iRegNdst);
4635
4636 format %{ %}
4637 interface(REG_INTER);
4638 %}
4639
4640 operand iRegNdst() %{
4641 constraint(ALLOC_IN_RC(bits32_reg_rw));
4642 match(RegN);
4643
4644 format %{ %}
4645 interface(REG_INTER);
4646 %}
4647
4648 // Long Destination Register
4649 // See definition of reg_class bits64_reg_rw.
4650 operand iRegLdst() %{
4651 constraint(ALLOC_IN_RC(bits64_reg_rw));
4652 match(RegL);
4653 match(rscratch1RegL);
4654 match(rscratch2RegL);
4655 format %{ %}
4656 interface(REG_INTER);
4657 %}
4658
4659 // Long Source Register
4660 // See definition of reg_class bits64_reg_ro.
4661 operand iRegLsrc() %{
4662 constraint(ALLOC_IN_RC(bits64_reg_ro));
4663 match(RegL);
4664 match(iRegLdst);
4665 match(rscratch1RegL);
4666 match(rscratch2RegL);
4667 format %{ %}
4668 interface(REG_INTER);
4669 %}
4670
4671 // Special operand for ConvL2I.
4672 operand iRegL2Isrc(iRegLsrc reg) %{
4673 constraint(ALLOC_IN_RC(bits64_reg_ro));
4674 match(ConvL2I reg);
4675 format %{ "ConvL2I($reg)" %}
4676 interface(REG_INTER)
4677 %}
4678
4679 operand rscratch1RegL() %{
4680 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4681 match(RegL);
4682 format %{ %}
4683 interface(REG_INTER);
4684 %}
4685
4686 operand rscratch2RegL() %{
4687 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4688 match(RegL);
4689 format %{ %}
4690 interface(REG_INTER);
4691 %}
4692
4693 // Condition Code Flag Registers
4694 operand flagsReg() %{
4695 constraint(ALLOC_IN_RC(int_flags));
4696 match(RegFlags);
4697 format %{ %}
4698 interface(REG_INTER);
4699 %}
4700
4701 // Condition Code Flag Register CR0
4702 operand flagsRegCR0() %{
4703 constraint(ALLOC_IN_RC(int_flags_CR0));
4704 match(RegFlags);
4705 format %{ "CR0" %}
4706 interface(REG_INTER);
4707 %}
4708
4709 operand flagsRegCR1() %{
4710 constraint(ALLOC_IN_RC(int_flags_CR1));
4711 match(RegFlags);
4712 format %{ "CR1" %}
4713 interface(REG_INTER);
4714 %}
4715
4716 operand flagsRegCR6() %{
4717 constraint(ALLOC_IN_RC(int_flags_CR6));
4718 match(RegFlags);
4719 format %{ "CR6" %}
4720 interface(REG_INTER);
4721 %}
4722
4723 operand regCTR() %{
4724 constraint(ALLOC_IN_RC(ctr_reg));
4725 // RegFlags should work. Introducing a RegSpecial type would cause a
4726 // lot of changes.
4727 match(RegFlags);
4728 format %{"SR_CTR" %}
4729 interface(REG_INTER);
4730 %}
4731
4732 operand regD() %{
4733 constraint(ALLOC_IN_RC(dbl_reg));
4734 match(RegD);
4735 format %{ %}
4736 interface(REG_INTER);
4737 %}
4738
4739 operand regF() %{
4740 constraint(ALLOC_IN_RC(flt_reg));
4741 match(RegF);
4742 format %{ %}
4743 interface(REG_INTER);
4744 %}
4745
4746 // Special Registers
4747
4748 // Method Register
4749 operand inline_cache_regP(iRegPdst reg) %{
4750 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4751 match(reg);
4752 format %{ %}
4753 interface(REG_INTER);
4754 %}
4755
4756 operand compiler_method_oop_regP(iRegPdst reg) %{
4757 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4758 match(reg);
4759 format %{ %}
4760 interface(REG_INTER);
4761 %}
4762
4763 operand interpreter_method_oop_regP(iRegPdst reg) %{
4764 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4765 match(reg);
4766 format %{ %}
4767 interface(REG_INTER);
4768 %}
4769
4770 // Operands to remove register moves in unscaled mode.
4771 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4772 operand iRegP2N(iRegPsrc reg) %{
4773 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4774 constraint(ALLOC_IN_RC(bits64_reg_ro));
4775 match(EncodeP reg);
4776 format %{ "$reg" %}
4777 interface(REG_INTER)
4778 %}
4779
4780 operand iRegN2P(iRegNsrc reg) %{
4781 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4782 constraint(ALLOC_IN_RC(bits32_reg_ro));
4783 match(DecodeN reg);
4784 match(DecodeNKlass reg);
4785 format %{ "$reg" %}
4786 interface(REG_INTER)
4787 %}
4788
4789 //----------Complex Operands---------------------------------------------------
4790 // Indirect Memory Reference
4791 operand indirect(iRegPsrc reg) %{
4792 constraint(ALLOC_IN_RC(bits64_reg_ro));
4793 match(reg);
4794 op_cost(100);
4795 format %{ "[$reg]" %}
4796 interface(MEMORY_INTER) %{
4797 base($reg);
4798 index(0x0);
4799 scale(0x0);
4800 disp(0x0);
4801 %}
4802 %}
4803
4804 // Indirect with Offset
4805 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4806 constraint(ALLOC_IN_RC(bits64_reg_ro));
4807 match(AddP reg offset);
4808 op_cost(100);
4809 format %{ "[$reg + $offset]" %}
4810 interface(MEMORY_INTER) %{
4811 base($reg);
4812 index(0x0);
4813 scale(0x0);
4814 disp($offset);
4815 %}
4816 %}
4817
4818 // Indirect with 4-aligned Offset
4819 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4820 constraint(ALLOC_IN_RC(bits64_reg_ro));
4821 match(AddP reg offset);
4822 op_cost(100);
4823 format %{ "[$reg + $offset]" %}
4824 interface(MEMORY_INTER) %{
4825 base($reg);
4826 index(0x0);
4827 scale(0x0);
4828 disp($offset);
4829 %}
4830 %}
4831
4832 //----------Complex Operands for Compressed OOPs-------------------------------
4833 // Compressed OOPs with narrow_oop_shift == 0.
4834
4835 // Indirect Memory Reference, compressed OOP
4836 operand indirectNarrow(iRegNsrc reg) %{
4837 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4838 constraint(ALLOC_IN_RC(bits64_reg_ro));
4839 match(DecodeN reg);
4840 match(DecodeNKlass reg);
4841 op_cost(100);
4842 format %{ "[$reg]" %}
4843 interface(MEMORY_INTER) %{
4844 base($reg);
4845 index(0x0);
4846 scale(0x0);
4847 disp(0x0);
4848 %}
4849 %}
4850
4851 // Indirect with Offset, compressed OOP
4852 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4853 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4854 constraint(ALLOC_IN_RC(bits64_reg_ro));
4855 match(AddP (DecodeN reg) offset);
4856 match(AddP (DecodeNKlass reg) offset);
4857 op_cost(100);
4858 format %{ "[$reg + $offset]" %}
4859 interface(MEMORY_INTER) %{
4860 base($reg);
4861 index(0x0);
4862 scale(0x0);
4863 disp($offset);
4864 %}
4865 %}
4866
4867 // Indirect with 4-aligned Offset, compressed OOP
4868 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4869 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4870 constraint(ALLOC_IN_RC(bits64_reg_ro));
4871 match(AddP (DecodeN reg) offset);
4872 match(AddP (DecodeNKlass reg) offset);
4873 op_cost(100);
4874 format %{ "[$reg + $offset]" %}
4875 interface(MEMORY_INTER) %{
4876 base($reg);
4877 index(0x0);
4878 scale(0x0);
4879 disp($offset);
4880 %}
4881 %}
4882
4883 //----------Special Memory Operands--------------------------------------------
4884 // Stack Slot Operand
4885 //
4886 // This operand is used for loading and storing temporary values on
4887 // the stack where a match requires a value to flow through memory.
4888 operand stackSlotI(sRegI reg) %{
4889 constraint(ALLOC_IN_RC(stack_slots));
4890 op_cost(100);
4891 //match(RegI);
4892 format %{ "[sp+$reg]" %}
4893 interface(MEMORY_INTER) %{
4894 base(0x1); // R1_SP
4895 index(0x0);
4896 scale(0x0);
4897 disp($reg); // Stack Offset
4898 %}
4899 %}
4900
4901 operand stackSlotL(sRegL reg) %{
4902 constraint(ALLOC_IN_RC(stack_slots));
4903 op_cost(100);
4904 //match(RegL);
4905 format %{ "[sp+$reg]" %}
4906 interface(MEMORY_INTER) %{
4907 base(0x1); // R1_SP
4908 index(0x0);
4909 scale(0x0);
4910 disp($reg); // Stack Offset
4911 %}
4912 %}
4913
4914 operand stackSlotP(sRegP reg) %{
4915 constraint(ALLOC_IN_RC(stack_slots));
4916 op_cost(100);
4917 //match(RegP);
4918 format %{ "[sp+$reg]" %}
4919 interface(MEMORY_INTER) %{
4920 base(0x1); // R1_SP
4921 index(0x0);
4922 scale(0x0);
4923 disp($reg); // Stack Offset
4924 %}
4925 %}
4926
4927 operand stackSlotF(sRegF reg) %{
4928 constraint(ALLOC_IN_RC(stack_slots));
4929 op_cost(100);
4930 //match(RegF);
4931 format %{ "[sp+$reg]" %}
4932 interface(MEMORY_INTER) %{
4933 base(0x1); // R1_SP
4934 index(0x0);
4935 scale(0x0);
4936 disp($reg); // Stack Offset
4937 %}
4938 %}
4939
4940 operand stackSlotD(sRegD reg) %{
4941 constraint(ALLOC_IN_RC(stack_slots));
4942 op_cost(100);
4943 //match(RegD);
4944 format %{ "[sp+$reg]" %}
4945 interface(MEMORY_INTER) %{
4946 base(0x1); // R1_SP
4947 index(0x0);
4948 scale(0x0);
4949 disp($reg); // Stack Offset
4950 %}
4951 %}
4952
4953 // Operands for expressing Control Flow
4954 // NOTE: Label is a predefined operand which should not be redefined in
4955 // the AD file. It is generically handled within the ADLC.
4956
4957 //----------Conditional Branch Operands----------------------------------------
4958 // Comparison Op
4959 //
4960 // This is the operation of the comparison, and is limited to the
4961 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4962 // (!=).
4963 //
4964 // Other attributes of the comparison, such as unsignedness, are specified
4965 // by the comparison instruction that sets a condition code flags register.
4966 // That result is represented by a flags operand whose subtype is appropriate
4967 // to the unsignedness (etc.) of the comparison.
4968 //
4969 // Later, the instruction which matches both the Comparison Op (a Bool) and
4970 // the flags (produced by the Cmp) specifies the coding of the comparison op
4971 // by matching a specific subtype of Bool operand below.
4972
4973 // When used for floating point comparisons: unordered same as less.
4974 operand cmpOp() %{
4975 match(Bool);
4976 format %{ "" %}
4977 interface(COND_INTER) %{
4978 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4979 // BO & BI
4980 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4981 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4982 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4983 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4984 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4985 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4986 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4987 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4988 %}
4989 %}
4990
4991 //----------OPERAND CLASSES----------------------------------------------------
4992 // Operand Classes are groups of operands that are used to simplify
4993 // instruction definitions by not requiring the AD writer to specify
4994 // seperate instructions for every form of operand when the
4995 // instruction accepts multiple operand types with the same basic
4996 // encoding and format. The classic case of this is memory operands.
4997 // Indirect is not included since its use is limited to Compare & Swap.
4998
4999 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
5000 // Memory operand where offsets are 4-aligned. Required for ld, std.
5001 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
5002 opclass indirectMemory(indirect, indirectNarrow);
5003
5004 // Special opclass for I and ConvL2I.
5005 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5006
5007 // Operand classes to match encode and decode. iRegN_P2N is only used
5008 // for storeN. I have never seen an encode node elsewhere.
5009 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5010 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5011
5012 //----------PIPELINE-----------------------------------------------------------
5013
5014 pipeline %{
5015
5016 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5017 // J. Res. & Dev., No. 1, Jan. 2002.
5018
5019 //----------ATTRIBUTES---------------------------------------------------------
5020 attributes %{
5021
5022 // Power4 instructions are of fixed length.
5023 fixed_size_instructions;
5024
5025 // TODO: if `bundle' means number of instructions fetched
5026 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5027 // max instructions issued per cycle, this is 5.
5028 max_instructions_per_bundle = 8;
5029
5030 // A Power4 instruction is 4 bytes long.
5031 instruction_unit_size = 4;
5032
5033 // The Power4 processor fetches 64 bytes...
5034 instruction_fetch_unit_size = 64;
5035
5036 // ...in one line
5037 instruction_fetch_units = 1
5038
5039 // Unused, list one so that array generated by adlc is not empty.
5040 // Aix compiler chokes if _nop_count = 0.
5041 nops(fxNop);
5042 %}
5043
5044 //----------RESOURCES----------------------------------------------------------
5045 // Resources are the functional units available to the machine
5046 resources(
5047 PPC_BR, // branch unit
5048 PPC_CR, // condition unit
5049 PPC_FX1, // integer arithmetic unit 1
5050 PPC_FX2, // integer arithmetic unit 2
5051 PPC_LDST1, // load/store unit 1
5052 PPC_LDST2, // load/store unit 2
5053 PPC_FP1, // float arithmetic unit 1
5054 PPC_FP2, // float arithmetic unit 2
5055 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5056 PPC_FX = PPC_FX1 | PPC_FX2,
5057 PPC_FP = PPC_FP1 | PPC_FP2
5058 );
5059
5060 //----------PIPELINE DESCRIPTION-----------------------------------------------
5061 // Pipeline Description specifies the stages in the machine's pipeline
5062 pipe_desc(
5063 // Power4 longest pipeline path
5064 PPC_IF, // instruction fetch
5065 PPC_IC,
5066 //PPC_BP, // branch prediction
5067 PPC_D0, // decode
5068 PPC_D1, // decode
5069 PPC_D2, // decode
5070 PPC_D3, // decode
5071 PPC_Xfer1,
5072 PPC_GD, // group definition
5073 PPC_MP, // map
5074 PPC_ISS, // issue
5075 PPC_RF, // resource fetch
5076 PPC_EX1, // execute (all units)
5077 PPC_EX2, // execute (FP, LDST)
5078 PPC_EX3, // execute (FP, LDST)
5079 PPC_EX4, // execute (FP)
5080 PPC_EX5, // execute (FP)
5081 PPC_EX6, // execute (FP)
5082 PPC_WB, // write back
5083 PPC_Xfer2,
5084 PPC_CP
5085 );
5086
5087 //----------PIPELINE CLASSES---------------------------------------------------
5088 // Pipeline Classes describe the stages in which input and output are
5089 // referenced by the hardware pipeline.
5090
5091 // Simple pipeline classes.
5092
5093 // Default pipeline class.
5094 pipe_class pipe_class_default() %{
5095 single_instruction;
5096 fixed_latency(2);
5097 %}
5098
5099 // Pipeline class for empty instructions.
5100 pipe_class pipe_class_empty() %{
5101 single_instruction;
5102 fixed_latency(0);
5103 %}
5104
5105 // Pipeline class for compares.
5106 pipe_class pipe_class_compare() %{
5107 single_instruction;
5108 fixed_latency(16);
5109 %}
5110
5111 // Pipeline class for traps.
5112 pipe_class pipe_class_trap() %{
5113 single_instruction;
5114 fixed_latency(100);
5115 %}
5116
5117 // Pipeline class for memory operations.
5118 pipe_class pipe_class_memory() %{
5119 single_instruction;
5120 fixed_latency(16);
5121 %}
5122
5123 // Pipeline class for call.
5124 pipe_class pipe_class_call() %{
5125 single_instruction;
5126 fixed_latency(100);
5127 %}
5128
5129 // Define the class for the Nop node.
5130 define %{
5131 MachNop = pipe_class_default;
5132 %}
5133
5134 %}
5135
5136 //----------INSTRUCTIONS-------------------------------------------------------
5137
5138 // Naming of instructions:
5139 // opA_operB / opA_operB_operC:
5140 // Operation 'op' with one or two source operands 'oper'. Result
5141 // type is A, source operand types are B and C.
5142 // Iff A == B == C, B and C are left out.
5143 //
5144 // The instructions are ordered according to the following scheme:
5145 // - loads
5146 // - load constants
5147 // - prefetch
5148 // - store
5149 // - encode/decode
5150 // - membar
5151 // - conditional moves
5152 // - compare & swap
5153 // - arithmetic and logic operations
5154 // * int: Add, Sub, Mul, Div, Mod
5155 // * int: lShift, arShift, urShift, rot
5156 // * float: Add, Sub, Mul, Div
5157 // * and, or, xor ...
5158 // - register moves: float <-> int, reg <-> stack, repl
5159 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5160 // - conv (low level type cast requiring bit changes (sign extend etc)
5161 // - compares, range & zero checks.
5162 // - branches
5163 // - complex operations, intrinsics, min, max, replicate
5164 // - lock
5165 // - Calls
5166 //
5167 // If there are similar instructions with different types they are sorted:
5168 // int before float
5169 // small before big
5170 // signed before unsigned
5171 // e.g., loadS before loadUS before loadI before loadF.
5172
5173
5174 //----------Load/Store Instructions--------------------------------------------
5175
5176 //----------Load Instructions--------------------------------------------------
5177
5178 // Converts byte to int.
5179 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5180 // reuses the 'amount' operand, but adlc expects that operand specification
5181 // and operands in match rule are equivalent.
5182 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5183 effect(DEF dst, USE src);
5184 format %{ "EXTSB $dst, $src \t// byte->int" %}
5185 size(4);
5186 ins_encode %{
5187 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5188 __ extsb($dst$$Register, $src$$Register);
5189 %}
5190 ins_pipe(pipe_class_default);
5191 %}
5192
5193 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5194 // match-rule, false predicate
5195 match(Set dst (LoadB mem));
5196 predicate(false);
5197
5198 format %{ "LBZ $dst, $mem" %}
5199 size(4);
5200 ins_encode( enc_lbz(dst, mem) );
5201 ins_pipe(pipe_class_memory);
5202 %}
5203
5204 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5205 // match-rule, false predicate
5206 match(Set dst (LoadB mem));
5207 predicate(false);
5208
5209 format %{ "LBZ $dst, $mem\n\t"
5210 "TWI $dst\n\t"
5211 "ISYNC" %}
5212 size(12);
5213 ins_encode( enc_lbz_ac(dst, mem) );
5214 ins_pipe(pipe_class_memory);
5215 %}
5216
5217 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5218 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5219 match(Set dst (LoadB mem));
5220 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5221 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5222 expand %{
5223 iRegIdst tmp;
5224 loadUB_indirect(tmp, mem);
5225 convB2I_reg_2(dst, tmp);
5226 %}
5227 %}
5228
5229 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5230 match(Set dst (LoadB mem));
5231 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5232 expand %{
5233 iRegIdst tmp;
5234 loadUB_indirect_ac(tmp, mem);
5235 convB2I_reg_2(dst, tmp);
5236 %}
5237 %}
5238
5239 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5240 // match-rule, false predicate
5241 match(Set dst (LoadB mem));
5242 predicate(false);
5243
5244 format %{ "LBZ $dst, $mem" %}
5245 size(4);
5246 ins_encode( enc_lbz(dst, mem) );
5247 ins_pipe(pipe_class_memory);
5248 %}
5249
5250 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5251 // match-rule, false predicate
5252 match(Set dst (LoadB mem));
5253 predicate(false);
5254
5255 format %{ "LBZ $dst, $mem\n\t"
5256 "TWI $dst\n\t"
5257 "ISYNC" %}
5258 size(12);
5259 ins_encode( enc_lbz_ac(dst, mem) );
5260 ins_pipe(pipe_class_memory);
5261 %}
5262
5263 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5264 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5265 match(Set dst (LoadB mem));
5266 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5267 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5268
5269 expand %{
5270 iRegIdst tmp;
5271 loadUB_indOffset16(tmp, mem);
5272 convB2I_reg_2(dst, tmp);
5273 %}
5274 %}
5275
5276 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5277 match(Set dst (LoadB mem));
5278 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5279
5280 expand %{
5281 iRegIdst tmp;
5282 loadUB_indOffset16_ac(tmp, mem);
5283 convB2I_reg_2(dst, tmp);
5284 %}
5285 %}
5286
5287 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5288 instruct loadUB(iRegIdst dst, memory mem) %{
5289 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5290 match(Set dst (LoadUB mem));
5291 ins_cost(MEMORY_REF_COST);
5292
5293 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5294 size(4);
5295 ins_encode( enc_lbz(dst, mem) );
5296 ins_pipe(pipe_class_memory);
5297 %}
5298
5299 // Load Unsigned Byte (8bit UNsigned) acquire.
5300 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5301 match(Set dst (LoadUB mem));
5302 ins_cost(3*MEMORY_REF_COST);
5303
5304 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5305 "TWI $dst\n\t"
5306 "ISYNC" %}
5307 size(12);
5308 ins_encode( enc_lbz_ac(dst, mem) );
5309 ins_pipe(pipe_class_memory);
5310 %}
5311
5312 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5313 instruct loadUB2L(iRegLdst dst, memory mem) %{
5314 match(Set dst (ConvI2L (LoadUB mem)));
5315 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5316 ins_cost(MEMORY_REF_COST);
5317
5318 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5319 size(4);
5320 ins_encode( enc_lbz(dst, mem) );
5321 ins_pipe(pipe_class_memory);
5322 %}
5323
5324 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5325 match(Set dst (ConvI2L (LoadUB mem)));
5326 ins_cost(3*MEMORY_REF_COST);
5327
5328 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5329 "TWI $dst\n\t"
5330 "ISYNC" %}
5331 size(12);
5332 ins_encode( enc_lbz_ac(dst, mem) );
5333 ins_pipe(pipe_class_memory);
5334 %}
5335
5336 // Load Short (16bit signed)
5337 instruct loadS(iRegIdst dst, memory mem) %{
5338 match(Set dst (LoadS mem));
5339 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5340 ins_cost(MEMORY_REF_COST);
5341
5342 format %{ "LHA $dst, $mem" %}
5343 size(4);
5344 ins_encode %{
5345 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5346 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5347 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5348 %}
5349 ins_pipe(pipe_class_memory);
5350 %}
5351
5352 // Load Short (16bit signed) acquire.
5353 instruct loadS_ac(iRegIdst dst, memory mem) %{
5354 match(Set dst (LoadS mem));
5355 ins_cost(3*MEMORY_REF_COST);
5356
5357 format %{ "LHA $dst, $mem\t acquire\n\t"
5358 "TWI $dst\n\t"
5359 "ISYNC" %}
5360 size(12);
5361 ins_encode %{
5362 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5363 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5364 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5365 __ twi_0($dst$$Register);
5366 __ isync();
5367 %}
5368 ins_pipe(pipe_class_memory);
5369 %}
5370
5371 // Load Char (16bit unsigned)
5372 instruct loadUS(iRegIdst dst, memory mem) %{
5373 match(Set dst (LoadUS mem));
5374 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5375 ins_cost(MEMORY_REF_COST);
5376
5377 format %{ "LHZ $dst, $mem" %}
5378 size(4);
5379 ins_encode( enc_lhz(dst, mem) );
5380 ins_pipe(pipe_class_memory);
5381 %}
5382
5383 // Load Char (16bit unsigned) acquire.
5384 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5385 match(Set dst (LoadUS mem));
5386 ins_cost(3*MEMORY_REF_COST);
5387
5388 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5389 "TWI $dst\n\t"
5390 "ISYNC" %}
5391 size(12);
5392 ins_encode( enc_lhz_ac(dst, mem) );
5393 ins_pipe(pipe_class_memory);
5394 %}
5395
5396 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5397 instruct loadUS2L(iRegLdst dst, memory mem) %{
5398 match(Set dst (ConvI2L (LoadUS mem)));
5399 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5400 ins_cost(MEMORY_REF_COST);
5401
5402 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5403 size(4);
5404 ins_encode( enc_lhz(dst, mem) );
5405 ins_pipe(pipe_class_memory);
5406 %}
5407
5408 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5409 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5410 match(Set dst (ConvI2L (LoadUS mem)));
5411 ins_cost(3*MEMORY_REF_COST);
5412
5413 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5414 "TWI $dst\n\t"
5415 "ISYNC" %}
5416 size(12);
5417 ins_encode( enc_lhz_ac(dst, mem) );
5418 ins_pipe(pipe_class_memory);
5419 %}
5420
5421 // Load Integer.
5422 instruct loadI(iRegIdst dst, memory mem) %{
5423 match(Set dst (LoadI mem));
5424 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5425 ins_cost(MEMORY_REF_COST);
5426
5427 format %{ "LWZ $dst, $mem" %}
5428 size(4);
5429 ins_encode( enc_lwz(dst, mem) );
5430 ins_pipe(pipe_class_memory);
5431 %}
5432
5433 // Load Integer acquire.
5434 instruct loadI_ac(iRegIdst dst, memory mem) %{
5435 match(Set dst (LoadI mem));
5436 ins_cost(3*MEMORY_REF_COST);
5437
5438 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5439 "TWI $dst\n\t"
5440 "ISYNC" %}
5441 size(12);
5442 ins_encode( enc_lwz_ac(dst, mem) );
5443 ins_pipe(pipe_class_memory);
5444 %}
5445
5446 // Match loading integer and casting it to unsigned int in
5447 // long register.
5448 // LoadI + ConvI2L + AndL 0xffffffff.
5449 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5450 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5451 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5452 ins_cost(MEMORY_REF_COST);
5453
5454 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5455 size(4);
5456 ins_encode( enc_lwz(dst, mem) );
5457 ins_pipe(pipe_class_memory);
5458 %}
5459
5460 // Match loading integer and casting it to long.
5461 instruct loadI2L(iRegLdst dst, memory mem) %{
5462 match(Set dst (ConvI2L (LoadI mem)));
5463 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5464 ins_cost(MEMORY_REF_COST);
5465
5466 format %{ "LWA $dst, $mem \t// loadI2L" %}
5467 size(4);
5468 ins_encode %{
5469 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5470 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5471 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5472 %}
5473 ins_pipe(pipe_class_memory);
5474 %}
5475
5476 // Match loading integer and casting it to long - acquire.
5477 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5478 match(Set dst (ConvI2L (LoadI mem)));
5479 ins_cost(3*MEMORY_REF_COST);
5480
5481 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5482 "TWI $dst\n\t"
5483 "ISYNC" %}
5484 size(12);
5485 ins_encode %{
5486 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5487 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5488 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5489 __ twi_0($dst$$Register);
5490 __ isync();
5491 %}
5492 ins_pipe(pipe_class_memory);
5493 %}
5494
5495 // Load Long - aligned
5496 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5497 match(Set dst (LoadL mem));
5498 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5499 ins_cost(MEMORY_REF_COST);
5500
5501 format %{ "LD $dst, $mem \t// long" %}
5502 size(4);
5503 ins_encode( enc_ld(dst, mem) );
5504 ins_pipe(pipe_class_memory);
5505 %}
5506
5507 // Load Long - aligned acquire.
5508 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5509 match(Set dst (LoadL mem));
5510 ins_cost(3*MEMORY_REF_COST);
5511
5512 format %{ "LD $dst, $mem \t// long acquire\n\t"
5513 "TWI $dst\n\t"
5514 "ISYNC" %}
5515 size(12);
5516 ins_encode( enc_ld_ac(dst, mem) );
5517 ins_pipe(pipe_class_memory);
5518 %}
5519
5520 // Load Long - UNaligned
5521 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5522 match(Set dst (LoadL_unaligned mem));
5523 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5524 ins_cost(MEMORY_REF_COST);
5525
5526 format %{ "LD $dst, $mem \t// unaligned long" %}
5527 size(4);
5528 ins_encode( enc_ld(dst, mem) );
5529 ins_pipe(pipe_class_memory);
5530 %}
5531
5532 // Load nodes for superwords
5533
5534 // Load Aligned Packed Byte
5535 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5536 predicate(n->as_LoadVector()->memory_size() == 8);
5537 match(Set dst (LoadVector mem));
5538 ins_cost(MEMORY_REF_COST);
5539
5540 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5541 size(4);
5542 ins_encode( enc_ld(dst, mem) );
5543 ins_pipe(pipe_class_memory);
5544 %}
5545
5546 // Load Range, range = array length (=jint)
5547 instruct loadRange(iRegIdst dst, memory mem) %{
5548 match(Set dst (LoadRange mem));
5549 ins_cost(MEMORY_REF_COST);
5550
5551 format %{ "LWZ $dst, $mem \t// range" %}
5552 size(4);
5553 ins_encode( enc_lwz(dst, mem) );
5554 ins_pipe(pipe_class_memory);
5555 %}
5556
5557 // Load Compressed Pointer
5558 instruct loadN(iRegNdst dst, memory mem) %{
5559 match(Set dst (LoadN mem));
5560 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5561 ins_cost(MEMORY_REF_COST);
5562
5563 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5564 size(4);
5565 ins_encode( enc_lwz(dst, mem) );
5566 ins_pipe(pipe_class_memory);
5567 %}
5568
5569 // Load Compressed Pointer acquire.
5570 instruct loadN_ac(iRegNdst dst, memory mem) %{
5571 match(Set dst (LoadN mem));
5572 ins_cost(3*MEMORY_REF_COST);
5573
5574 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5575 "TWI $dst\n\t"
5576 "ISYNC" %}
5577 size(12);
5578 ins_encode( enc_lwz_ac(dst, mem) );
5579 ins_pipe(pipe_class_memory);
5580 %}
5581
5582 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5583 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5584 match(Set dst (DecodeN (LoadN mem)));
5585 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5586 ins_cost(MEMORY_REF_COST);
5587
5588 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5589 size(4);
5590 ins_encode( enc_lwz(dst, mem) );
5591 ins_pipe(pipe_class_memory);
5592 %}
5593
5594 // Load Pointer
5595 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5596 match(Set dst (LoadP mem));
5597 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5598 ins_cost(MEMORY_REF_COST);
5599
5600 format %{ "LD $dst, $mem \t// ptr" %}
5601 size(4);
5602 ins_encode( enc_ld(dst, mem) );
5603 ins_pipe(pipe_class_memory);
5604 %}
5605
5606 // Load Pointer acquire.
5607 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5608 match(Set dst (LoadP mem));
5609 ins_cost(3*MEMORY_REF_COST);
5610
5611 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5612 "TWI $dst\n\t"
5613 "ISYNC" %}
5614 size(12);
5615 ins_encode( enc_ld_ac(dst, mem) );
5616 ins_pipe(pipe_class_memory);
5617 %}
5618
5619 // LoadP + CastP2L
5620 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5621 match(Set dst (CastP2X (LoadP mem)));
5622 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5623 ins_cost(MEMORY_REF_COST);
5624
5625 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5626 size(4);
5627 ins_encode( enc_ld(dst, mem) );
5628 ins_pipe(pipe_class_memory);
5629 %}
5630
5631 // Load compressed klass pointer.
5632 instruct loadNKlass(iRegNdst dst, memory mem) %{
5633 match(Set dst (LoadNKlass mem));
5634 ins_cost(MEMORY_REF_COST);
5635
5636 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5637 size(4);
5638 ins_encode( enc_lwz(dst, mem) );
5639 ins_pipe(pipe_class_memory);
5640 %}
5641
5642 // Load Klass Pointer
5643 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5644 match(Set dst (LoadKlass mem));
5645 ins_cost(MEMORY_REF_COST);
5646
5647 format %{ "LD $dst, $mem \t// klass ptr" %}
5648 size(4);
5649 ins_encode( enc_ld(dst, mem) );
5650 ins_pipe(pipe_class_memory);
5651 %}
5652
5653 // Load Float
5654 instruct loadF(regF dst, memory mem) %{
5655 match(Set dst (LoadF mem));
5656 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5657 ins_cost(MEMORY_REF_COST);
5658
5659 format %{ "LFS $dst, $mem" %}
5660 size(4);
5661 ins_encode %{
5662 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5663 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5664 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5665 %}
5666 ins_pipe(pipe_class_memory);
5667 %}
5668
5669 // Load Float acquire.
5670 instruct loadF_ac(regF dst, memory mem) %{
5671 match(Set dst (LoadF mem));
5672 ins_cost(3*MEMORY_REF_COST);
5673
5674 format %{ "LFS $dst, $mem \t// acquire\n\t"
5675 "FCMPU cr0, $dst, $dst\n\t"
5676 "BNE cr0, next\n"
5677 "next:\n\t"
5678 "ISYNC" %}
5679 size(16);
5680 ins_encode %{
5681 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5682 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5683 Label next;
5684 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5685 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5686 __ bne(CCR0, next);
5687 __ bind(next);
5688 __ isync();
5689 %}
5690 ins_pipe(pipe_class_memory);
5691 %}
5692
5693 // Load Double - aligned
5694 instruct loadD(regD dst, memory mem) %{
5695 match(Set dst (LoadD mem));
5696 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5697 ins_cost(MEMORY_REF_COST);
5698
5699 format %{ "LFD $dst, $mem" %}
5700 size(4);
5701 ins_encode( enc_lfd(dst, mem) );
5702 ins_pipe(pipe_class_memory);
5703 %}
5704
5705 // Load Double - aligned acquire.
5706 instruct loadD_ac(regD dst, memory mem) %{
5707 match(Set dst (LoadD mem));
5708 ins_cost(3*MEMORY_REF_COST);
5709
5710 format %{ "LFD $dst, $mem \t// acquire\n\t"
5711 "FCMPU cr0, $dst, $dst\n\t"
5712 "BNE cr0, next\n"
5713 "next:\n\t"
5714 "ISYNC" %}
5715 size(16);
5716 ins_encode %{
5717 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5718 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5719 Label next;
5720 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5721 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5722 __ bne(CCR0, next);
5723 __ bind(next);
5724 __ isync();
5725 %}
5726 ins_pipe(pipe_class_memory);
5727 %}
5728
5729 // Load Double - UNaligned
5730 instruct loadD_unaligned(regD dst, memory mem) %{
5731 match(Set dst (LoadD_unaligned mem));
5732 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5733 ins_cost(MEMORY_REF_COST);
5734
5735 format %{ "LFD $dst, $mem" %}
5736 size(4);
5737 ins_encode( enc_lfd(dst, mem) );
5738 ins_pipe(pipe_class_memory);
5739 %}
5740
5741 //----------Constants--------------------------------------------------------
5742
5743 // Load MachConstantTableBase: add hi offset to global toc.
5744 // TODO: Handle hidden register r29 in bundler!
5745 instruct loadToc_hi(iRegLdst dst) %{
5746 effect(DEF dst);
5747 ins_cost(DEFAULT_COST);
5748
5749 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5750 size(4);
5751 ins_encode %{
5752 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5753 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5754 %}
5755 ins_pipe(pipe_class_default);
5756 %}
5757
5758 // Load MachConstantTableBase: add lo offset to global toc.
5759 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5760 effect(DEF dst, USE src);
5761 ins_cost(DEFAULT_COST);
5762
5763 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5764 size(4);
5765 ins_encode %{
5766 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5767 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5768 %}
5769 ins_pipe(pipe_class_default);
5770 %}
5771
5772 // Load 16-bit integer constant 0xssss????
5773 instruct loadConI16(iRegIdst dst, immI16 src) %{
5774 match(Set dst src);
5775
5776 format %{ "LI $dst, $src" %}
5777 size(4);
5778 ins_encode %{
5779 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5780 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5781 %}
5782 ins_pipe(pipe_class_default);
5783 %}
5784
5785 // Load integer constant 0x????0000
5786 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5787 match(Set dst src);
5788 ins_cost(DEFAULT_COST);
5789
5790 format %{ "LIS $dst, $src.hi" %}
5791 size(4);
5792 ins_encode %{
5793 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5794 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5795 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5796 %}
5797 ins_pipe(pipe_class_default);
5798 %}
5799
5800 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5801 // and sign extended), this adds the low 16 bits.
5802 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5803 // no match-rule, false predicate
5804 effect(DEF dst, USE src1, USE src2);
5805 predicate(false);
5806
5807 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5808 size(4);
5809 ins_encode %{
5810 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5811 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5812 %}
5813 ins_pipe(pipe_class_default);
5814 %}
5815
5816 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5817 match(Set dst src);
5818 ins_cost(DEFAULT_COST*2);
5819
5820 expand %{
5821 // Would like to use $src$$constant.
5822 immI16 srcLo %{ _opnds[1]->constant() %}
5823 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5824 immIhi16 srcHi %{ _opnds[1]->constant() %}
5825 iRegIdst tmpI;
5826 loadConIhi16(tmpI, srcHi);
5827 loadConI32_lo16(dst, tmpI, srcLo);
5828 %}
5829 %}
5830
5831 // No constant pool entries required.
5832 instruct loadConL16(iRegLdst dst, immL16 src) %{
5833 match(Set dst src);
5834
5835 format %{ "LI $dst, $src \t// long" %}
5836 size(4);
5837 ins_encode %{
5838 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5839 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5840 %}
5841 ins_pipe(pipe_class_default);
5842 %}
5843
5844 // Load long constant 0xssssssss????0000
5845 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5846 match(Set dst src);
5847 ins_cost(DEFAULT_COST);
5848
5849 format %{ "LIS $dst, $src.hi \t// long" %}
5850 size(4);
5851 ins_encode %{
5852 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5853 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5854 %}
5855 ins_pipe(pipe_class_default);
5856 %}
5857
5858 // To load a 32 bit constant: merge lower 16 bits into already loaded
5859 // high 16 bits.
5860 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5861 // no match-rule, false predicate
5862 effect(DEF dst, USE src1, USE src2);
5863 predicate(false);
5864
5865 format %{ "ORI $dst, $src1, $src2.lo" %}
5866 size(4);
5867 ins_encode %{
5868 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5869 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5870 %}
5871 ins_pipe(pipe_class_default);
5872 %}
5873
5874 // Load 32-bit long constant
5875 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5876 match(Set dst src);
5877 ins_cost(DEFAULT_COST*2);
5878
5879 expand %{
5880 // Would like to use $src$$constant.
5881 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5882 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5883 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5884 iRegLdst tmpL;
5885 loadConL32hi16(tmpL, srcHi);
5886 loadConL32_lo16(dst, tmpL, srcLo);
5887 %}
5888 %}
5889
5890 // Load long constant 0x????000000000000.
5891 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5892 match(Set dst src);
5893 ins_cost(DEFAULT_COST);
5894
5895 expand %{
5896 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5897 immI shift32 %{ 32 %}
5898 iRegLdst tmpL;
5899 loadConL32hi16(tmpL, srcHi);
5900 lshiftL_regL_immI(dst, tmpL, shift32);
5901 %}
5902 %}
5903
5904 // Expand node for constant pool load: small offset.
5905 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5906 effect(DEF dst, USE src, USE toc);
5907 ins_cost(MEMORY_REF_COST);
5908
5909 ins_num_consts(1);
5910 // Needed so that CallDynamicJavaDirect can compute the address of this
5911 // instruction for relocation.
5912 ins_field_cbuf_insts_offset(int);
5913
5914 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5915 size(4);
5916 ins_encode( enc_load_long_constL(dst, src, toc) );
5917 ins_pipe(pipe_class_memory);
5918 %}
5919
5920 // Expand node for constant pool load: large offset.
5921 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5922 effect(DEF dst, USE src, USE toc);
5923 predicate(false);
5924
5925 ins_num_consts(1);
5926 ins_field_const_toc_offset(int);
5927 // Needed so that CallDynamicJavaDirect can compute the address of this
5928 // instruction for relocation.
5929 ins_field_cbuf_insts_offset(int);
5930
5931 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5932 size(4);
5933 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5934 ins_pipe(pipe_class_default);
5935 %}
5936
5937 // Expand node for constant pool load: large offset.
5938 // No constant pool entries required.
5939 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5940 effect(DEF dst, USE src, USE base);
5941 predicate(false);
5942
5943 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5944
5945 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5946 size(4);
5947 ins_encode %{
5948 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5949 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5950 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5951 %}
5952 ins_pipe(pipe_class_memory);
5953 %}
5954
5955 // Load long constant from constant table. Expand in case of
5956 // offset > 16 bit is needed.
5957 // Adlc adds toc node MachConstantTableBase.
5958 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5959 match(Set dst src);
5960 ins_cost(MEMORY_REF_COST);
5961
5962 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5963 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5964 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5965 %}
5966
5967 // Load NULL as compressed oop.
5968 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5969 match(Set dst src);
5970 ins_cost(DEFAULT_COST);
5971
5972 format %{ "LI $dst, $src \t// compressed ptr" %}
5973 size(4);
5974 ins_encode %{
5975 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5976 __ li($dst$$Register, 0);
5977 %}
5978 ins_pipe(pipe_class_default);
5979 %}
5980
5981 // Load hi part of compressed oop constant.
5982 instruct loadConN_hi(iRegNdst dst, immN src) %{
5983 effect(DEF dst, USE src);
5984 ins_cost(DEFAULT_COST);
5985
5986 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5987 size(4);
5988 ins_encode %{
5989 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5990 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5991 %}
5992 ins_pipe(pipe_class_default);
5993 %}
5994
5995 // Add lo part of compressed oop constant to already loaded hi part.
5996 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5997 effect(DEF dst, USE src1, USE src2);
5998 ins_cost(DEFAULT_COST);
5999
6000 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6001 size(4);
6002 ins_encode %{
6003 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6004 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6005 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6006 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6007 __ relocate(rspec, 1);
6008 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6009 %}
6010 ins_pipe(pipe_class_default);
6011 %}
6012
6013 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6014 // leaving the upper 32 bits with sign-extension bits.
6015 // This clears these bits: dst = src & 0xFFFFFFFF.
6016 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6017 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6018 effect(DEF dst, USE src);
6019 predicate(false);
6020
6021 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6022 size(4);
6023 ins_encode %{
6024 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6025 __ clrldi($dst$$Register, $src$$Register, 0x20);
6026 %}
6027 ins_pipe(pipe_class_default);
6028 %}
6029
6030 // Loading ConN must be postalloc expanded so that edges between
6031 // the nodes are safe. They may not interfere with a safepoint.
6032 // GL TODO: This needs three instructions: better put this into the constant pool.
6033 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6034 match(Set dst src);
6035 ins_cost(DEFAULT_COST*2);
6036
6037 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6038 postalloc_expand %{
6039 MachNode *m1 = new loadConN_hiNode();
6040 MachNode *m2 = new loadConN_loNode();
6041 MachNode *m3 = new clearMs32bNode();
6042 m1->add_req(NULL);
6043 m2->add_req(NULL, m1);
6044 m3->add_req(NULL, m2);
6045 m1->_opnds[0] = op_dst;
6046 m1->_opnds[1] = op_src;
6047 m2->_opnds[0] = op_dst;
6048 m2->_opnds[1] = op_dst;
6049 m2->_opnds[2] = op_src;
6050 m3->_opnds[0] = op_dst;
6051 m3->_opnds[1] = op_dst;
6052 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6053 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6054 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6055 nodes->push(m1);
6056 nodes->push(m2);
6057 nodes->push(m3);
6058 %}
6059 %}
6060
6061 // We have seen a safepoint between the hi and lo parts, and this node was handled
6062 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6063 // not a narrow oop.
6064 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6065 match(Set dst src);
6066 effect(DEF dst, USE src);
6067 ins_cost(DEFAULT_COST);
6068
6069 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6070 size(4);
6071 ins_encode %{
6072 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6073 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6074 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6075 %}
6076 ins_pipe(pipe_class_default);
6077 %}
6078
6079 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6080 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6081 match(Set dst src1);
6082 effect(TEMP src2);
6083 ins_cost(DEFAULT_COST);
6084
6085 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6086 size(4);
6087 ins_encode %{
6088 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6089 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6090 %}
6091 ins_pipe(pipe_class_default);
6092 %}
6093
6094 // This needs a match rule so that build_oop_map knows this is
6095 // not a narrow oop.
6096 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6097 match(Set dst src1);
6098 effect(TEMP src2);
6099 ins_cost(DEFAULT_COST);
6100
6101 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6102 size(4);
6103 ins_encode %{
6104 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6105 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6106 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6107 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6108 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6109
6110 __ relocate(rspec, 1);
6111 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6112 %}
6113 ins_pipe(pipe_class_default);
6114 %}
6115
6116 // Loading ConNKlass must be postalloc expanded so that edges between
6117 // the nodes are safe. They may not interfere with a safepoint.
6118 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6119 match(Set dst src);
6120 ins_cost(DEFAULT_COST*2);
6121
6122 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6123 postalloc_expand %{
6124 // Load high bits into register. Sign extended.
6125 MachNode *m1 = new loadConNKlass_hiNode();
6126 m1->add_req(NULL);
6127 m1->_opnds[0] = op_dst;
6128 m1->_opnds[1] = op_src;
6129 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6130 nodes->push(m1);
6131
6132 MachNode *m2 = m1;
6133 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6134 // Value might be 1-extended. Mask out these bits.
6135 m2 = new loadConNKlass_maskNode();
6136 m2->add_req(NULL, m1);
6137 m2->_opnds[0] = op_dst;
6138 m2->_opnds[1] = op_src;
6139 m2->_opnds[2] = op_dst;
6140 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6141 nodes->push(m2);
6142 }
6143
6144 MachNode *m3 = new loadConNKlass_loNode();
6145 m3->add_req(NULL, m2);
6146 m3->_opnds[0] = op_dst;
6147 m3->_opnds[1] = op_src;
6148 m3->_opnds[2] = op_dst;
6149 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6150 nodes->push(m3);
6151 %}
6152 %}
6153
6154 // 0x1 is used in object initialization (initial object header).
6155 // No constant pool entries required.
6156 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6157 match(Set dst src);
6158
6159 format %{ "LI $dst, $src \t// ptr" %}
6160 size(4);
6161 ins_encode %{
6162 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6163 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6164 %}
6165 ins_pipe(pipe_class_default);
6166 %}
6167
6168 // Expand node for constant pool load: small offset.
6169 // The match rule is needed to generate the correct bottom_type(),
6170 // however this node should never match. The use of predicate is not
6171 // possible since ADLC forbids predicates for chain rules. The higher
6172 // costs do not prevent matching in this case. For that reason the
6173 // operand immP_NM with predicate(false) is used.
6174 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6175 match(Set dst src);
6176 effect(TEMP toc);
6177
6178 ins_num_consts(1);
6179
6180 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6181 size(4);
6182 ins_encode( enc_load_long_constP(dst, src, toc) );
6183 ins_pipe(pipe_class_memory);
6184 %}
6185
6186 // Expand node for constant pool load: large offset.
6187 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6188 effect(DEF dst, USE src, USE toc);
6189 predicate(false);
6190
6191 ins_num_consts(1);
6192 ins_field_const_toc_offset(int);
6193
6194 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6195 size(4);
6196 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6197 ins_pipe(pipe_class_default);
6198 %}
6199
6200 // Expand node for constant pool load: large offset.
6201 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6202 match(Set dst src);
6203 effect(TEMP base);
6204
6205 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6206
6207 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6208 size(4);
6209 ins_encode %{
6210 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6211 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6212 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6213 %}
6214 ins_pipe(pipe_class_memory);
6215 %}
6216
6217 // Load pointer constant from constant table. Expand in case an
6218 // offset > 16 bit is needed.
6219 // Adlc adds toc node MachConstantTableBase.
6220 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6221 match(Set dst src);
6222 ins_cost(MEMORY_REF_COST);
6223
6224 // This rule does not use "expand" because then
6225 // the result type is not known to be an Oop. An ADLC
6226 // enhancement will be needed to make that work - not worth it!
6227
6228 // If this instruction rematerializes, it prolongs the live range
6229 // of the toc node, causing illegal graphs.
6230 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6231 ins_cannot_rematerialize(true);
6232
6233 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6234 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6235 %}
6236
6237 // Expand node for constant pool load: small offset.
6238 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6239 effect(DEF dst, USE src, USE toc);
6240 ins_cost(MEMORY_REF_COST);
6241
6242 ins_num_consts(1);
6243
6244 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6245 size(4);
6246 ins_encode %{
6247 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6248 address float_address = __ float_constant($src$$constant);
6249 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6250 %}
6251 ins_pipe(pipe_class_memory);
6252 %}
6253
6254 // Expand node for constant pool load: large offset.
6255 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6256 effect(DEF dst, USE src, USE toc);
6257 ins_cost(MEMORY_REF_COST);
6258
6259 ins_num_consts(1);
6260
6261 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6262 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6263 "ADDIS $toc, $toc, -offset_hi"%}
6264 size(12);
6265 ins_encode %{
6266 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6267 FloatRegister Rdst = $dst$$FloatRegister;
6268 Register Rtoc = $toc$$Register;
6269 address float_address = __ float_constant($src$$constant);
6270 int offset = __ offset_to_method_toc(float_address);
6271 int hi = (offset + (1<<15))>>16;
6272 int lo = offset - hi * (1<<16);
6273
6274 __ addis(Rtoc, Rtoc, hi);
6275 __ lfs(Rdst, lo, Rtoc);
6276 __ addis(Rtoc, Rtoc, -hi);
6277 %}
6278 ins_pipe(pipe_class_memory);
6279 %}
6280
6281 // Adlc adds toc node MachConstantTableBase.
6282 instruct loadConF_Ex(regF dst, immF src) %{
6283 match(Set dst src);
6284 ins_cost(MEMORY_REF_COST);
6285
6286 // See loadConP.
6287 ins_cannot_rematerialize(true);
6288
6289 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6290 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6291 %}
6292
6293 // Expand node for constant pool load: small offset.
6294 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6295 effect(DEF dst, USE src, USE toc);
6296 ins_cost(MEMORY_REF_COST);
6297
6298 ins_num_consts(1);
6299
6300 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6301 size(4);
6302 ins_encode %{
6303 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6304 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6305 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6306 %}
6307 ins_pipe(pipe_class_memory);
6308 %}
6309
6310 // Expand node for constant pool load: large offset.
6311 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6312 effect(DEF dst, USE src, USE toc);
6313 ins_cost(MEMORY_REF_COST);
6314
6315 ins_num_consts(1);
6316
6317 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6318 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6319 "ADDIS $toc, $toc, -offset_hi" %}
6320 size(12);
6321 ins_encode %{
6322 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6323 FloatRegister Rdst = $dst$$FloatRegister;
6324 Register Rtoc = $toc$$Register;
6325 address float_address = __ double_constant($src$$constant);
6326 int offset = __ offset_to_method_toc(float_address);
6327 int hi = (offset + (1<<15))>>16;
6328 int lo = offset - hi * (1<<16);
6329
6330 __ addis(Rtoc, Rtoc, hi);
6331 __ lfd(Rdst, lo, Rtoc);
6332 __ addis(Rtoc, Rtoc, -hi);
6333 %}
6334 ins_pipe(pipe_class_memory);
6335 %}
6336
6337 // Adlc adds toc node MachConstantTableBase.
6338 instruct loadConD_Ex(regD dst, immD src) %{
6339 match(Set dst src);
6340 ins_cost(MEMORY_REF_COST);
6341
6342 // See loadConP.
6343 ins_cannot_rematerialize(true);
6344
6345 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6346 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6347 %}
6348
6349 // Prefetch instructions.
6350 // Must be safe to execute with invalid address (cannot fault).
6351
6352 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6353 match(PrefetchRead (AddP mem src));
6354 ins_cost(MEMORY_REF_COST);
6355
6356 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6357 size(4);
6358 ins_encode %{
6359 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6360 __ dcbt($src$$Register, $mem$$base$$Register);
6361 %}
6362 ins_pipe(pipe_class_memory);
6363 %}
6364
6365 instruct prefetchr_no_offset(indirectMemory mem) %{
6366 match(PrefetchRead mem);
6367 ins_cost(MEMORY_REF_COST);
6368
6369 format %{ "PREFETCH $mem" %}
6370 size(4);
6371 ins_encode %{
6372 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6373 __ dcbt($mem$$base$$Register);
6374 %}
6375 ins_pipe(pipe_class_memory);
6376 %}
6377
6378 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6379 match(PrefetchWrite (AddP mem src));
6380 ins_cost(MEMORY_REF_COST);
6381
6382 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6383 size(4);
6384 ins_encode %{
6385 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6386 __ dcbtst($src$$Register, $mem$$base$$Register);
6387 %}
6388 ins_pipe(pipe_class_memory);
6389 %}
6390
6391 instruct prefetchw_no_offset(indirectMemory mem) %{
6392 match(PrefetchWrite mem);
6393 ins_cost(MEMORY_REF_COST);
6394
6395 format %{ "PREFETCH $mem" %}
6396 size(4);
6397 ins_encode %{
6398 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6399 __ dcbtst($mem$$base$$Register);
6400 %}
6401 ins_pipe(pipe_class_memory);
6402 %}
6403
6404 // Special prefetch versions which use the dcbz instruction.
6405 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6406 match(PrefetchAllocation (AddP mem src));
6407 predicate(AllocatePrefetchStyle == 3);
6408 ins_cost(MEMORY_REF_COST);
6409
6410 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6411 size(4);
6412 ins_encode %{
6413 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6414 __ dcbz($src$$Register, $mem$$base$$Register);
6415 %}
6416 ins_pipe(pipe_class_memory);
6417 %}
6418
6419 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6420 match(PrefetchAllocation mem);
6421 predicate(AllocatePrefetchStyle == 3);
6422 ins_cost(MEMORY_REF_COST);
6423
6424 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6425 size(4);
6426 ins_encode %{
6427 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6428 __ dcbz($mem$$base$$Register);
6429 %}
6430 ins_pipe(pipe_class_memory);
6431 %}
6432
6433 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6434 match(PrefetchAllocation (AddP mem src));
6435 predicate(AllocatePrefetchStyle != 3);
6436 ins_cost(MEMORY_REF_COST);
6437
6438 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6439 size(4);
6440 ins_encode %{
6441 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6442 __ dcbtst($src$$Register, $mem$$base$$Register);
6443 %}
6444 ins_pipe(pipe_class_memory);
6445 %}
6446
6447 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6448 match(PrefetchAllocation mem);
6449 predicate(AllocatePrefetchStyle != 3);
6450 ins_cost(MEMORY_REF_COST);
6451
6452 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6453 size(4);
6454 ins_encode %{
6455 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6456 __ dcbtst($mem$$base$$Register);
6457 %}
6458 ins_pipe(pipe_class_memory);
6459 %}
6460
6461 //----------Store Instructions-------------------------------------------------
6462
6463 // Store Byte
6464 instruct storeB(memory mem, iRegIsrc src) %{
6465 match(Set mem (StoreB mem src));
6466 ins_cost(MEMORY_REF_COST);
6467
6468 format %{ "STB $src, $mem \t// byte" %}
6469 size(4);
6470 ins_encode %{
6471 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6472 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6473 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6474 %}
6475 ins_pipe(pipe_class_memory);
6476 %}
6477
6478 // Store Char/Short
6479 instruct storeC(memory mem, iRegIsrc src) %{
6480 match(Set mem (StoreC mem src));
6481 ins_cost(MEMORY_REF_COST);
6482
6483 format %{ "STH $src, $mem \t// short" %}
6484 size(4);
6485 ins_encode %{
6486 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6487 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6488 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6489 %}
6490 ins_pipe(pipe_class_memory);
6491 %}
6492
6493 // Store Integer
6494 instruct storeI(memory mem, iRegIsrc src) %{
6495 match(Set mem (StoreI mem src));
6496 ins_cost(MEMORY_REF_COST);
6497
6498 format %{ "STW $src, $mem" %}
6499 size(4);
6500 ins_encode( enc_stw(src, mem) );
6501 ins_pipe(pipe_class_memory);
6502 %}
6503
6504 // ConvL2I + StoreI.
6505 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6506 match(Set mem (StoreI mem (ConvL2I src)));
6507 ins_cost(MEMORY_REF_COST);
6508
6509 format %{ "STW l2i($src), $mem" %}
6510 size(4);
6511 ins_encode( enc_stw(src, mem) );
6512 ins_pipe(pipe_class_memory);
6513 %}
6514
6515 // Store Long
6516 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6517 match(Set mem (StoreL mem src));
6518 ins_cost(MEMORY_REF_COST);
6519
6520 format %{ "STD $src, $mem \t// long" %}
6521 size(4);
6522 ins_encode( enc_std(src, mem) );
6523 ins_pipe(pipe_class_memory);
6524 %}
6525
6526 // Store super word nodes.
6527
6528 // Store Aligned Packed Byte long register to memory
6529 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6530 predicate(n->as_StoreVector()->memory_size() == 8);
6531 match(Set mem (StoreVector mem src));
6532 ins_cost(MEMORY_REF_COST);
6533
6534 format %{ "STD $mem, $src \t// packed8B" %}
6535 size(4);
6536 ins_encode( enc_std(src, mem) );
6537 ins_pipe(pipe_class_memory);
6538 %}
6539
6540 // Store Compressed Oop
6541 instruct storeN(memory dst, iRegN_P2N src) %{
6542 match(Set dst (StoreN dst src));
6543 ins_cost(MEMORY_REF_COST);
6544
6545 format %{ "STW $src, $dst \t// compressed oop" %}
6546 size(4);
6547 ins_encode( enc_stw(src, dst) );
6548 ins_pipe(pipe_class_memory);
6549 %}
6550
6551 // Store Compressed KLass
6552 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6553 match(Set dst (StoreNKlass dst src));
6554 ins_cost(MEMORY_REF_COST);
6555
6556 format %{ "STW $src, $dst \t// compressed klass" %}
6557 size(4);
6558 ins_encode( enc_stw(src, dst) );
6559 ins_pipe(pipe_class_memory);
6560 %}
6561
6562 // Store Pointer
6563 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6564 match(Set dst (StoreP dst src));
6565 ins_cost(MEMORY_REF_COST);
6566
6567 format %{ "STD $src, $dst \t// ptr" %}
6568 size(4);
6569 ins_encode( enc_std(src, dst) );
6570 ins_pipe(pipe_class_memory);
6571 %}
6572
6573 // Store Float
6574 instruct storeF(memory mem, regF src) %{
6575 match(Set mem (StoreF mem src));
6576 ins_cost(MEMORY_REF_COST);
6577
6578 format %{ "STFS $src, $mem" %}
6579 size(4);
6580 ins_encode( enc_stfs(src, mem) );
6581 ins_pipe(pipe_class_memory);
6582 %}
6583
6584 // Store Double
6585 instruct storeD(memory mem, regD src) %{
6586 match(Set mem (StoreD mem src));
6587 ins_cost(MEMORY_REF_COST);
6588
6589 format %{ "STFD $src, $mem" %}
6590 size(4);
6591 ins_encode( enc_stfd(src, mem) );
6592 ins_pipe(pipe_class_memory);
6593 %}
6594
6595 //----------Store Instructions With Zeros--------------------------------------
6596
6597 // Card-mark for CMS garbage collection.
6598 // This cardmark does an optimization so that it must not always
6599 // do a releasing store. For this, it gets the address of
6600 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6601 // (Using releaseFieldAddr in the match rule is a hack.)
6602 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6603 match(Set mem (StoreCM mem releaseFieldAddr));
6604 predicate(false);
6605 ins_cost(MEMORY_REF_COST);
6606
6607 // See loadConP.
6608 ins_cannot_rematerialize(true);
6609
6610 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6611 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6612 ins_pipe(pipe_class_memory);
6613 %}
6614
6615 // Card-mark for CMS garbage collection.
6616 // This cardmark does an optimization so that it must not always
6617 // do a releasing store. For this, it needs the constant address of
6618 // CMSCollectorCardTableModRefBSExt::_requires_release.
6619 // This constant address is split off here by expand so we can use
6620 // adlc / matcher functionality to load it from the constant section.
6621 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6622 match(Set mem (StoreCM mem zero));
6623 predicate(UseConcMarkSweepGC);
6624
6625 expand %{
6626 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6627 iRegLdst releaseFieldAddress;
6628 loadConL_Ex(releaseFieldAddress, baseImm);
6629 storeCM_CMS(mem, releaseFieldAddress);
6630 %}
6631 %}
6632
6633 instruct storeCM_G1(memory mem, immI_0 zero) %{
6634 match(Set mem (StoreCM mem zero));
6635 predicate(UseG1GC);
6636 ins_cost(MEMORY_REF_COST);
6637
6638 ins_cannot_rematerialize(true);
6639
6640 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6641 size(8);
6642 ins_encode %{
6643 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6644 __ li(R0, 0);
6645 //__ release(); // G1: oops are allowed to get visible after dirty marking
6646 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6647 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6648 %}
6649 ins_pipe(pipe_class_memory);
6650 %}
6651
6652 // Convert oop pointer into compressed form.
6653
6654 // Nodes for postalloc expand.
6655
6656 // Shift node for expand.
6657 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6658 // The match rule is needed to make it a 'MachTypeNode'!
6659 match(Set dst (EncodeP src));
6660 predicate(false);
6661
6662 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6663 size(4);
6664 ins_encode %{
6665 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6666 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6667 %}
6668 ins_pipe(pipe_class_default);
6669 %}
6670
6671 // Add node for expand.
6672 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6673 // The match rule is needed to make it a 'MachTypeNode'!
6674 match(Set dst (EncodeP src));
6675 predicate(false);
6676
6677 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6678 size(4);
6679 ins_encode %{
6680 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6681 __ subf($dst$$Register, R30, $src$$Register);
6682 %}
6683 ins_pipe(pipe_class_default);
6684 %}
6685
6686 // Conditional sub base.
6687 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6688 // The match rule is needed to make it a 'MachTypeNode'!
6689 match(Set dst (EncodeP (Binary crx src1)));
6690 predicate(false);
6691
6692 ins_variable_size_depending_on_alignment(true);
6693
6694 format %{ "BEQ $crx, done\n\t"
6695 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6696 "done:" %}
6697 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6698 ins_encode %{
6699 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6700 Label done;
6701 __ beq($crx$$CondRegister, done);
6702 __ subf($dst$$Register, R30, $src1$$Register);
6703 // TODO PPC port __ endgroup_if_needed(_size == 12);
6704 __ bind(done);
6705 %}
6706 ins_pipe(pipe_class_default);
6707 %}
6708
6709 // Power 7 can use isel instruction
6710 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6711 // The match rule is needed to make it a 'MachTypeNode'!
6712 match(Set dst (EncodeP (Binary crx src1)));
6713 predicate(false);
6714
6715 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6716 size(4);
6717 ins_encode %{
6718 // This is a Power7 instruction for which no machine description exists.
6719 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6720 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6721 %}
6722 ins_pipe(pipe_class_default);
6723 %}
6724
6725 // base != 0
6726 // 32G aligned narrow oop base.
6727 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6728 match(Set dst (EncodeP src));
6729 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6730
6731 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6732 size(4);
6733 ins_encode %{
6734 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6735 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6736 %}
6737 ins_pipe(pipe_class_default);
6738 %}
6739
6740 // shift != 0, base != 0
6741 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6742 match(Set dst (EncodeP src));
6743 effect(TEMP crx);
6744 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6745 Universe::narrow_oop_shift() != 0 &&
6746 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6747
6748 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6749 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6750 %}
6751
6752 // shift != 0, base != 0
6753 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6754 match(Set dst (EncodeP src));
6755 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6756 Universe::narrow_oop_shift() != 0 &&
6757 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6758
6759 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6760 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6761 %}
6762
6763 // shift != 0, base == 0
6764 // TODO: This is the same as encodeP_shift. Merge!
6765 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6766 match(Set dst (EncodeP src));
6767 predicate(Universe::narrow_oop_shift() != 0 &&
6768 Universe::narrow_oop_base() ==0);
6769
6770 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6771 size(4);
6772 ins_encode %{
6773 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6774 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6775 %}
6776 ins_pipe(pipe_class_default);
6777 %}
6778
6779 // Compressed OOPs with narrow_oop_shift == 0.
6780 // shift == 0, base == 0
6781 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6782 match(Set dst (EncodeP src));
6783 predicate(Universe::narrow_oop_shift() == 0);
6784
6785 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6786 // variable size, 0 or 4.
6787 ins_encode %{
6788 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6789 __ mr_if_needed($dst$$Register, $src$$Register);
6790 %}
6791 ins_pipe(pipe_class_default);
6792 %}
6793
6794 // Decode nodes.
6795
6796 // Shift node for expand.
6797 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6798 // The match rule is needed to make it a 'MachTypeNode'!
6799 match(Set dst (DecodeN src));
6800 predicate(false);
6801
6802 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6803 size(4);
6804 ins_encode %{
6805 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6806 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6807 %}
6808 ins_pipe(pipe_class_default);
6809 %}
6810
6811 // Add node for expand.
6812 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6813 // The match rule is needed to make it a 'MachTypeNode'!
6814 match(Set dst (DecodeN src));
6815 predicate(false);
6816
6817 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6818 size(4);
6819 ins_encode %{
6820 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6821 __ add($dst$$Register, $src$$Register, R30);
6822 %}
6823 ins_pipe(pipe_class_default);
6824 %}
6825
6826 // conditianal add base for expand
6827 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6828 // The match rule is needed to make it a 'MachTypeNode'!
6829 // NOTICE that the rule is nonsense - we just have to make sure that:
6830 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6831 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6832 match(Set dst (DecodeN (Binary crx src1)));
6833 predicate(false);
6834
6835 ins_variable_size_depending_on_alignment(true);
6836
6837 format %{ "BEQ $crx, done\n\t"
6838 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6839 "done:" %}
6840 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6841 ins_encode %{
6842 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6843 Label done;
6844 __ beq($crx$$CondRegister, done);
6845 __ add($dst$$Register, $src1$$Register, R30);
6846 // TODO PPC port __ endgroup_if_needed(_size == 12);
6847 __ bind(done);
6848 %}
6849 ins_pipe(pipe_class_default);
6850 %}
6851
6852 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6853 // The match rule is needed to make it a 'MachTypeNode'!
6854 // NOTICE that the rule is nonsense - we just have to make sure that:
6855 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6856 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6857 match(Set dst (DecodeN (Binary crx src1)));
6858 predicate(false);
6859
6860 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6861 size(4);
6862 ins_encode %{
6863 // This is a Power7 instruction for which no machine description exists.
6864 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6865 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6866 %}
6867 ins_pipe(pipe_class_default);
6868 %}
6869
6870 // shift != 0, base != 0
6871 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6872 match(Set dst (DecodeN src));
6873 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6874 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6875 Universe::narrow_oop_shift() != 0 &&
6876 Universe::narrow_oop_base() != 0);
6877 effect(TEMP crx);
6878
6879 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6880 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6881 %}
6882
6883 // shift != 0, base == 0
6884 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6885 match(Set dst (DecodeN src));
6886 predicate(Universe::narrow_oop_shift() != 0 &&
6887 Universe::narrow_oop_base() == 0);
6888
6889 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6890 size(4);
6891 ins_encode %{
6892 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6893 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6894 %}
6895 ins_pipe(pipe_class_default);
6896 %}
6897
6898 // src != 0, shift != 0, base != 0
6899 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6900 match(Set dst (DecodeN src));
6901 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6902 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6903 Universe::narrow_oop_shift() != 0 &&
6904 Universe::narrow_oop_base() != 0);
6905
6906 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6907 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6908 %}
6909
6910 // Compressed OOPs with narrow_oop_shift == 0.
6911 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6912 match(Set dst (DecodeN src));
6913 predicate(Universe::narrow_oop_shift() == 0);
6914 ins_cost(DEFAULT_COST);
6915
6916 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6917 // variable size, 0 or 4.
6918 ins_encode %{
6919 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6920 __ mr_if_needed($dst$$Register, $src$$Register);
6921 %}
6922 ins_pipe(pipe_class_default);
6923 %}
6924
6925 // Convert compressed oop into int for vectors alignment masking.
6926 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6927 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6928 predicate(Universe::narrow_oop_shift() == 0);
6929 ins_cost(DEFAULT_COST);
6930
6931 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6932 // variable size, 0 or 4.
6933 ins_encode %{
6934 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6935 __ mr_if_needed($dst$$Register, $src$$Register);
6936 %}
6937 ins_pipe(pipe_class_default);
6938 %}
6939
6940 // Convert klass pointer into compressed form.
6941
6942 // Nodes for postalloc expand.
6943
6944 // Shift node for expand.
6945 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6946 // The match rule is needed to make it a 'MachTypeNode'!
6947 match(Set dst (EncodePKlass src));
6948 predicate(false);
6949
6950 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6951 size(4);
6952 ins_encode %{
6953 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6954 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6955 %}
6956 ins_pipe(pipe_class_default);
6957 %}
6958
6959 // Add node for expand.
6960 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6961 // The match rule is needed to make it a 'MachTypeNode'!
6962 match(Set dst (EncodePKlass (Binary base src)));
6963 predicate(false);
6964
6965 format %{ "SUB $dst, $base, $src \t// encode" %}
6966 size(4);
6967 ins_encode %{
6968 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6969 __ subf($dst$$Register, $base$$Register, $src$$Register);
6970 %}
6971 ins_pipe(pipe_class_default);
6972 %}
6973
6974 // base != 0
6975 // 32G aligned narrow oop base.
6976 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6977 match(Set dst (EncodePKlass src));
6978 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6979
6980 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6981 size(4);
6982 ins_encode %{
6983 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6984 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
6985 %}
6986 ins_pipe(pipe_class_default);
6987 %}
6988
6989 // shift != 0, base != 0
6990 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6991 match(Set dst (EncodePKlass (Binary base src)));
6992 predicate(false);
6993
6994 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6995 postalloc_expand %{
6996 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
6997 n1->add_req(n_region, n_base, n_src);
6998 n1->_opnds[0] = op_dst;
6999 n1->_opnds[1] = op_base;
7000 n1->_opnds[2] = op_src;
7001 n1->_bottom_type = _bottom_type;
7002
7003 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7004 n2->add_req(n_region, n1);
7005 n2->_opnds[0] = op_dst;
7006 n2->_opnds[1] = op_dst;
7007 n2->_bottom_type = _bottom_type;
7008 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7009 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7010
7011 nodes->push(n1);
7012 nodes->push(n2);
7013 %}
7014 %}
7015
7016 // shift != 0, base != 0
7017 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7018 match(Set dst (EncodePKlass src));
7019 //predicate(Universe::narrow_klass_shift() != 0 &&
7020 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7021
7022 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7023 ins_cost(DEFAULT_COST*2); // Don't count constant.
7024 expand %{
7025 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7026 iRegLdst base;
7027 loadConL_Ex(base, baseImm);
7028 encodePKlass_not_null_Ex(dst, base, src);
7029 %}
7030 %}
7031
7032 // Decode nodes.
7033
7034 // Shift node for expand.
7035 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7036 // The match rule is needed to make it a 'MachTypeNode'!
7037 match(Set dst (DecodeNKlass src));
7038 predicate(false);
7039
7040 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7041 size(4);
7042 ins_encode %{
7043 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7044 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7045 %}
7046 ins_pipe(pipe_class_default);
7047 %}
7048
7049 // Add node for expand.
7050
7051 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7052 // The match rule is needed to make it a 'MachTypeNode'!
7053 match(Set dst (DecodeNKlass (Binary base src)));
7054 predicate(false);
7055
7056 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7057 size(4);
7058 ins_encode %{
7059 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7060 __ add($dst$$Register, $base$$Register, $src$$Register);
7061 %}
7062 ins_pipe(pipe_class_default);
7063 %}
7064
7065 // src != 0, shift != 0, base != 0
7066 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7067 match(Set dst (DecodeNKlass (Binary base src)));
7068 //effect(kill src); // We need a register for the immediate result after shifting.
7069 predicate(false);
7070
7071 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7072 postalloc_expand %{
7073 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7074 n1->add_req(n_region, n_base, n_src);
7075 n1->_opnds[0] = op_dst;
7076 n1->_opnds[1] = op_base;
7077 n1->_opnds[2] = op_src;
7078 n1->_bottom_type = _bottom_type;
7079
7080 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7081 n2->add_req(n_region, n1);
7082 n2->_opnds[0] = op_dst;
7083 n2->_opnds[1] = op_dst;
7084 n2->_bottom_type = _bottom_type;
7085
7086 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7087 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7088
7089 nodes->push(n1);
7090 nodes->push(n2);
7091 %}
7092 %}
7093
7094 // src != 0, shift != 0, base != 0
7095 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7096 match(Set dst (DecodeNKlass src));
7097 // predicate(Universe::narrow_klass_shift() != 0 &&
7098 // Universe::narrow_klass_base() != 0);
7099
7100 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7101
7102 ins_cost(DEFAULT_COST*2); // Don't count constant.
7103 expand %{
7104 // We add first, then we shift. Like this, we can get along with one register less.
7105 // But we have to load the base pre-shifted.
7106 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7107 iRegLdst base;
7108 loadConL_Ex(base, baseImm);
7109 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7110 %}
7111 %}
7112
7113 //----------MemBar Instructions-----------------------------------------------
7114 // Memory barrier flavors
7115
7116 instruct membar_acquire() %{
7117 match(LoadFence);
7118 ins_cost(4*MEMORY_REF_COST);
7119
7120 format %{ "MEMBAR-acquire" %}
7121 size(4);
7122 ins_encode %{
7123 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7124 __ acquire();
7125 %}
7126 ins_pipe(pipe_class_default);
7127 %}
7128
7129 instruct unnecessary_membar_acquire() %{
7130 match(MemBarAcquire);
7131 ins_cost(0);
7132
7133 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7134 size(0);
7135 ins_encode( /*empty*/ );
7136 ins_pipe(pipe_class_default);
7137 %}
7138
7139 instruct membar_acquire_lock() %{
7140 match(MemBarAcquireLock);
7141 ins_cost(0);
7142
7143 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7144 size(0);
7145 ins_encode( /*empty*/ );
7146 ins_pipe(pipe_class_default);
7147 %}
7148
7149 instruct membar_release() %{
7150 match(MemBarRelease);
7151 match(StoreFence);
7152 ins_cost(4*MEMORY_REF_COST);
7153
7154 format %{ "MEMBAR-release" %}
7155 size(4);
7156 ins_encode %{
7157 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7158 __ release();
7159 %}
7160 ins_pipe(pipe_class_default);
7161 %}
7162
7163 instruct membar_storestore() %{
7164 match(MemBarStoreStore);
7165 ins_cost(4*MEMORY_REF_COST);
7166
7167 format %{ "MEMBAR-store-store" %}
7168 size(4);
7169 ins_encode %{
7170 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7171 __ membar(Assembler::StoreStore);
7172 %}
7173 ins_pipe(pipe_class_default);
7174 %}
7175
7176 instruct membar_release_lock() %{
7177 match(MemBarReleaseLock);
7178 ins_cost(0);
7179
7180 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7181 size(0);
7182 ins_encode( /*empty*/ );
7183 ins_pipe(pipe_class_default);
7184 %}
7185
7186 instruct membar_volatile() %{
7187 match(MemBarVolatile);
7188 ins_cost(4*MEMORY_REF_COST);
7189
7190 format %{ "MEMBAR-volatile" %}
7191 size(4);
7192 ins_encode %{
7193 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7194 __ fence();
7195 %}
7196 ins_pipe(pipe_class_default);
7197 %}
7198
7199 // This optimization is wrong on PPC. The following pattern is not supported:
7200 // MemBarVolatile
7201 // ^ ^
7202 // | |
7203 // CtrlProj MemProj
7204 // ^ ^
7205 // | |
7206 // | Load
7207 // |
7208 // MemBarVolatile
7209 //
7210 // The first MemBarVolatile could get optimized out! According to
7211 // Vladimir, this pattern can not occur on Oracle platforms.
7212 // However, it does occur on PPC64 (because of membars in
7213 // inline_unsafe_load_store).
7214 //
7215 // Add this node again if we found a good solution for inline_unsafe_load_store().
7216 // Don't forget to look at the implementation of post_store_load_barrier again,
7217 // we did other fixes in that method.
7218 //instruct unnecessary_membar_volatile() %{
7219 // match(MemBarVolatile);
7220 // predicate(Matcher::post_store_load_barrier(n));
7221 // ins_cost(0);
7222 //
7223 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7224 // size(0);
7225 // ins_encode( /*empty*/ );
7226 // ins_pipe(pipe_class_default);
7227 //%}
7228
7229 instruct membar_CPUOrder() %{
7230 match(MemBarCPUOrder);
7231 ins_cost(0);
7232
7233 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7234 size(0);
7235 ins_encode( /*empty*/ );
7236 ins_pipe(pipe_class_default);
7237 %}
7238
7239 //----------Conditional Move---------------------------------------------------
7240
7241 // Cmove using isel.
7242 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7243 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7244 predicate(VM_Version::has_isel());
7245 ins_cost(DEFAULT_COST);
7246
7247 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7248 size(4);
7249 ins_encode %{
7250 // This is a Power7 instruction for which no machine description
7251 // exists. Anyways, the scheduler should be off on Power7.
7252 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7253 int cc = $cmp$$cmpcode;
7254 __ isel($dst$$Register, $crx$$CondRegister,
7255 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7256 %}
7257 ins_pipe(pipe_class_default);
7258 %}
7259
7260 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7261 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7262 predicate(!VM_Version::has_isel());
7263 ins_cost(DEFAULT_COST+BRANCH_COST);
7264
7265 ins_variable_size_depending_on_alignment(true);
7266
7267 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7268 // Worst case is branch + move + stop, no stop without scheduler
7269 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7270 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7271 ins_pipe(pipe_class_default);
7272 %}
7273
7274 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7275 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7276 ins_cost(DEFAULT_COST+BRANCH_COST);
7277
7278 ins_variable_size_depending_on_alignment(true);
7279
7280 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7281 // Worst case is branch + move + stop, no stop without scheduler
7282 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7283 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7284 ins_pipe(pipe_class_default);
7285 %}
7286
7287 // Cmove using isel.
7288 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7289 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7290 predicate(VM_Version::has_isel());
7291 ins_cost(DEFAULT_COST);
7292
7293 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7294 size(4);
7295 ins_encode %{
7296 // This is a Power7 instruction for which no machine description
7297 // exists. Anyways, the scheduler should be off on Power7.
7298 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7299 int cc = $cmp$$cmpcode;
7300 __ isel($dst$$Register, $crx$$CondRegister,
7301 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7302 %}
7303 ins_pipe(pipe_class_default);
7304 %}
7305
7306 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7307 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7308 predicate(!VM_Version::has_isel());
7309 ins_cost(DEFAULT_COST+BRANCH_COST);
7310
7311 ins_variable_size_depending_on_alignment(true);
7312
7313 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7314 // Worst case is branch + move + stop, no stop without scheduler.
7315 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7316 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7317 ins_pipe(pipe_class_default);
7318 %}
7319
7320 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7321 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7322 ins_cost(DEFAULT_COST+BRANCH_COST);
7323
7324 ins_variable_size_depending_on_alignment(true);
7325
7326 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7327 // Worst case is branch + move + stop, no stop without scheduler.
7328 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7329 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7330 ins_pipe(pipe_class_default);
7331 %}
7332
7333 // Cmove using isel.
7334 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7335 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7336 predicate(VM_Version::has_isel());
7337 ins_cost(DEFAULT_COST);
7338
7339 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7340 size(4);
7341 ins_encode %{
7342 // This is a Power7 instruction for which no machine description
7343 // exists. Anyways, the scheduler should be off on Power7.
7344 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7345 int cc = $cmp$$cmpcode;
7346 __ isel($dst$$Register, $crx$$CondRegister,
7347 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7348 %}
7349 ins_pipe(pipe_class_default);
7350 %}
7351
7352 // Conditional move for RegN. Only cmov(reg, reg).
7353 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7354 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7355 predicate(!VM_Version::has_isel());
7356 ins_cost(DEFAULT_COST+BRANCH_COST);
7357
7358 ins_variable_size_depending_on_alignment(true);
7359
7360 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7361 // Worst case is branch + move + stop, no stop without scheduler.
7362 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7363 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7364 ins_pipe(pipe_class_default);
7365 %}
7366
7367 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7368 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7369 ins_cost(DEFAULT_COST+BRANCH_COST);
7370
7371 ins_variable_size_depending_on_alignment(true);
7372
7373 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7374 // Worst case is branch + move + stop, no stop without scheduler.
7375 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7376 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7377 ins_pipe(pipe_class_default);
7378 %}
7379
7380 // Cmove using isel.
7381 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7382 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7383 predicate(VM_Version::has_isel());
7384 ins_cost(DEFAULT_COST);
7385
7386 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7387 size(4);
7388 ins_encode %{
7389 // This is a Power7 instruction for which no machine description
7390 // exists. Anyways, the scheduler should be off on Power7.
7391 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7392 int cc = $cmp$$cmpcode;
7393 __ isel($dst$$Register, $crx$$CondRegister,
7394 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7395 %}
7396 ins_pipe(pipe_class_default);
7397 %}
7398
7399 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7400 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7401 predicate(!VM_Version::has_isel());
7402 ins_cost(DEFAULT_COST+BRANCH_COST);
7403
7404 ins_variable_size_depending_on_alignment(true);
7405
7406 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7407 // Worst case is branch + move + stop, no stop without scheduler.
7408 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7409 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7410 ins_pipe(pipe_class_default);
7411 %}
7412
7413 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7414 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7415 ins_cost(DEFAULT_COST+BRANCH_COST);
7416
7417 ins_variable_size_depending_on_alignment(true);
7418
7419 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7420 // Worst case is branch + move + stop, no stop without scheduler.
7421 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7422 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7423 ins_pipe(pipe_class_default);
7424 %}
7425
7426 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7427 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7428 ins_cost(DEFAULT_COST+BRANCH_COST);
7429
7430 ins_variable_size_depending_on_alignment(true);
7431
7432 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7433 // Worst case is branch + move + stop, no stop without scheduler.
7434 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7435 ins_encode %{
7436 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7437 Label done;
7438 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7439 // Branch if not (cmp crx).
7440 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7441 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7442 // TODO PPC port __ endgroup_if_needed(_size == 12);
7443 __ bind(done);
7444 %}
7445 ins_pipe(pipe_class_default);
7446 %}
7447
7448 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7449 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7450 ins_cost(DEFAULT_COST+BRANCH_COST);
7451
7452 ins_variable_size_depending_on_alignment(true);
7453
7454 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7455 // Worst case is branch + move + stop, no stop without scheduler.
7456 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7457 ins_encode %{
7458 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7459 Label done;
7460 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7461 // Branch if not (cmp crx).
7462 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7463 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7464 // TODO PPC port __ endgroup_if_needed(_size == 12);
7465 __ bind(done);
7466 %}
7467 ins_pipe(pipe_class_default);
7468 %}
7469
7470 //----------Conditional_store--------------------------------------------------
7471 // Conditional-store of the updated heap-top.
7472 // Used during allocation of the shared heap.
7473 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7474
7475 // As compareAndSwapL, but return flag register instead of boolean value in
7476 // int register.
7477 // Used by sun/misc/AtomicLongCSImpl.java.
7478 // Mem_ptr must be a memory operand, else this node does not get
7479 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7480 // can be rematerialized which leads to errors.
7481 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7482 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7483 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7484 ins_encode %{
7485 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7486 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7487 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7488 noreg, NULL, true);
7489 %}
7490 ins_pipe(pipe_class_default);
7491 %}
7492
7493 // As compareAndSwapP, but return flag register instead of boolean value in
7494 // int register.
7495 // This instruction is matched if UseTLAB is off.
7496 // Mem_ptr must be a memory operand, else this node does not get
7497 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7498 // can be rematerialized which leads to errors.
7499 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7500 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7501 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7502 ins_encode %{
7503 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7504 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7505 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7506 noreg, NULL, true);
7507 %}
7508 ins_pipe(pipe_class_default);
7509 %}
7510
7511 // Implement LoadPLocked. Must be ordered against changes of the memory location
7512 // by storePConditional.
7513 // Don't know whether this is ever used.
7514 instruct loadPLocked(iRegPdst dst, memory mem) %{
7515 match(Set dst (LoadPLocked mem));
7516 ins_cost(MEMORY_REF_COST);
7517
7518 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7519 "TWI $dst\n\t"
7520 "ISYNC" %}
7521 size(12);
7522 ins_encode( enc_ld_ac(dst, mem) );
7523 ins_pipe(pipe_class_memory);
7524 %}
7525
7526 //----------Compare-And-Swap---------------------------------------------------
7527
7528 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7529 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7530 // matched.
7531
7532 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7533 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7534 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7535 // Variable size: instruction count smaller if regs are disjoint.
7536 ins_encode %{
7537 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7538 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7539 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7540 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7541 $res$$Register, true);
7542 %}
7543 ins_pipe(pipe_class_default);
7544 %}
7545
7546 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7547 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7548 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7549 // Variable size: instruction count smaller if regs are disjoint.
7550 ins_encode %{
7551 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7552 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7553 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7554 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7555 $res$$Register, true);
7556 %}
7557 ins_pipe(pipe_class_default);
7558 %}
7559
7560 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7561 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7562 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7563 // Variable size: instruction count smaller if regs are disjoint.
7564 ins_encode %{
7565 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7566 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7567 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7568 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7569 $res$$Register, NULL, true);
7570 %}
7571 ins_pipe(pipe_class_default);
7572 %}
7573
7574 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7575 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7576 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7577 // Variable size: instruction count smaller if regs are disjoint.
7578 ins_encode %{
7579 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7580 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7581 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7582 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7583 $res$$Register, NULL, true);
7584 %}
7585 ins_pipe(pipe_class_default);
7586 %}
7587
7588 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7589 match(Set res (GetAndAddI mem_ptr src));
7590 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7591 // Variable size: instruction count smaller if regs are disjoint.
7592 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7593 ins_pipe(pipe_class_default);
7594 %}
7595
7596 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7597 match(Set res (GetAndAddL mem_ptr src));
7598 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7599 // Variable size: instruction count smaller if regs are disjoint.
7600 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7601 ins_pipe(pipe_class_default);
7602 %}
7603
7604 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7605 match(Set res (GetAndSetI mem_ptr src));
7606 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7607 // Variable size: instruction count smaller if regs are disjoint.
7608 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7609 ins_pipe(pipe_class_default);
7610 %}
7611
7612 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7613 match(Set res (GetAndSetL mem_ptr src));
7614 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7615 // Variable size: instruction count smaller if regs are disjoint.
7616 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7617 ins_pipe(pipe_class_default);
7618 %}
7619
7620 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7621 match(Set res (GetAndSetP mem_ptr src));
7622 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7623 // Variable size: instruction count smaller if regs are disjoint.
7624 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7625 ins_pipe(pipe_class_default);
7626 %}
7627
7628 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7629 match(Set res (GetAndSetN mem_ptr src));
7630 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7631 // Variable size: instruction count smaller if regs are disjoint.
7632 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7633 ins_pipe(pipe_class_default);
7634 %}
7635
7636 //----------Arithmetic Instructions--------------------------------------------
7637 // Addition Instructions
7638
7639 // Register Addition
7640 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7641 match(Set dst (AddI src1 src2));
7642 format %{ "ADD $dst, $src1, $src2" %}
7643 size(4);
7644 ins_encode %{
7645 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7646 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7647 %}
7648 ins_pipe(pipe_class_default);
7649 %}
7650
7651 // Expand does not work with above instruct. (??)
7652 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7653 // no match-rule
7654 effect(DEF dst, USE src1, USE src2);
7655 format %{ "ADD $dst, $src1, $src2" %}
7656 size(4);
7657 ins_encode %{
7658 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7659 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7660 %}
7661 ins_pipe(pipe_class_default);
7662 %}
7663
7664 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7665 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7666 ins_cost(DEFAULT_COST*3);
7667
7668 expand %{
7669 // FIXME: we should do this in the ideal world.
7670 iRegIdst tmp1;
7671 iRegIdst tmp2;
7672 addI_reg_reg(tmp1, src1, src2);
7673 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7674 addI_reg_reg(dst, tmp1, tmp2);
7675 %}
7676 %}
7677
7678 // Immediate Addition
7679 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7680 match(Set dst (AddI src1 src2));
7681 format %{ "ADDI $dst, $src1, $src2" %}
7682 size(4);
7683 ins_encode %{
7684 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7685 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7686 %}
7687 ins_pipe(pipe_class_default);
7688 %}
7689
7690 // Immediate Addition with 16-bit shifted operand
7691 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7692 match(Set dst (AddI src1 src2));
7693 format %{ "ADDIS $dst, $src1, $src2" %}
7694 size(4);
7695 ins_encode %{
7696 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7697 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7698 %}
7699 ins_pipe(pipe_class_default);
7700 %}
7701
7702 // Long Addition
7703 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7704 match(Set dst (AddL src1 src2));
7705 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7706 size(4);
7707 ins_encode %{
7708 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7709 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7710 %}
7711 ins_pipe(pipe_class_default);
7712 %}
7713
7714 // Expand does not work with above instruct. (??)
7715 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7716 // no match-rule
7717 effect(DEF dst, USE src1, USE src2);
7718 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7719 size(4);
7720 ins_encode %{
7721 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7722 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7723 %}
7724 ins_pipe(pipe_class_default);
7725 %}
7726
7727 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7728 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7729 ins_cost(DEFAULT_COST*3);
7730
7731 expand %{
7732 // FIXME: we should do this in the ideal world.
7733 iRegLdst tmp1;
7734 iRegLdst tmp2;
7735 addL_reg_reg(tmp1, src1, src2);
7736 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7737 addL_reg_reg(dst, tmp1, tmp2);
7738 %}
7739 %}
7740
7741 // AddL + ConvL2I.
7742 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7743 match(Set dst (ConvL2I (AddL src1 src2)));
7744
7745 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7746 size(4);
7747 ins_encode %{
7748 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7749 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7750 %}
7751 ins_pipe(pipe_class_default);
7752 %}
7753
7754 // No constant pool entries required.
7755 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7756 match(Set dst (AddL src1 src2));
7757
7758 format %{ "ADDI $dst, $src1, $src2" %}
7759 size(4);
7760 ins_encode %{
7761 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7762 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7763 %}
7764 ins_pipe(pipe_class_default);
7765 %}
7766
7767 // Long Immediate Addition with 16-bit shifted operand.
7768 // No constant pool entries required.
7769 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7770 match(Set dst (AddL src1 src2));
7771
7772 format %{ "ADDIS $dst, $src1, $src2" %}
7773 size(4);
7774 ins_encode %{
7775 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7776 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7777 %}
7778 ins_pipe(pipe_class_default);
7779 %}
7780
7781 // Pointer Register Addition
7782 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7783 match(Set dst (AddP src1 src2));
7784 format %{ "ADD $dst, $src1, $src2" %}
7785 size(4);
7786 ins_encode %{
7787 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7788 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7789 %}
7790 ins_pipe(pipe_class_default);
7791 %}
7792
7793 // Pointer Immediate Addition
7794 // No constant pool entries required.
7795 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7796 match(Set dst (AddP src1 src2));
7797
7798 format %{ "ADDI $dst, $src1, $src2" %}
7799 size(4);
7800 ins_encode %{
7801 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7802 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7803 %}
7804 ins_pipe(pipe_class_default);
7805 %}
7806
7807 // Pointer Immediate Addition with 16-bit shifted operand.
7808 // No constant pool entries required.
7809 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7810 match(Set dst (AddP src1 src2));
7811
7812 format %{ "ADDIS $dst, $src1, $src2" %}
7813 size(4);
7814 ins_encode %{
7815 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7816 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7817 %}
7818 ins_pipe(pipe_class_default);
7819 %}
7820
7821 //---------------------
7822 // Subtraction Instructions
7823
7824 // Register Subtraction
7825 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7826 match(Set dst (SubI src1 src2));
7827 format %{ "SUBF $dst, $src2, $src1" %}
7828 size(4);
7829 ins_encode %{
7830 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7831 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7832 %}
7833 ins_pipe(pipe_class_default);
7834 %}
7835
7836 // Immediate Subtraction
7837 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7838 // so this rule seems to be unused.
7839 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7840 match(Set dst (SubI src1 src2));
7841 format %{ "SUBI $dst, $src1, $src2" %}
7842 size(4);
7843 ins_encode %{
7844 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7845 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7846 %}
7847 ins_pipe(pipe_class_default);
7848 %}
7849
7850 // SubI from constant (using subfic).
7851 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7852 match(Set dst (SubI src1 src2));
7853 format %{ "SUBI $dst, $src1, $src2" %}
7854
7855 size(4);
7856 ins_encode %{
7857 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7858 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7859 %}
7860 ins_pipe(pipe_class_default);
7861 %}
7862
7863 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7864 // positive integers and 0xF...F for negative ones.
7865 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7866 // no match-rule, false predicate
7867 effect(DEF dst, USE src);
7868 predicate(false);
7869
7870 format %{ "SRAWI $dst, $src, #31" %}
7871 size(4);
7872 ins_encode %{
7873 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7874 __ srawi($dst$$Register, $src$$Register, 0x1f);
7875 %}
7876 ins_pipe(pipe_class_default);
7877 %}
7878
7879 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7880 match(Set dst (AbsI src));
7881 ins_cost(DEFAULT_COST*3);
7882
7883 expand %{
7884 iRegIdst tmp1;
7885 iRegIdst tmp2;
7886 signmask32I_regI(tmp1, src);
7887 xorI_reg_reg(tmp2, tmp1, src);
7888 subI_reg_reg(dst, tmp2, tmp1);
7889 %}
7890 %}
7891
7892 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7893 match(Set dst (SubI zero src2));
7894 format %{ "NEG $dst, $src2" %}
7895 size(4);
7896 ins_encode %{
7897 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7898 __ neg($dst$$Register, $src2$$Register);
7899 %}
7900 ins_pipe(pipe_class_default);
7901 %}
7902
7903 // Long subtraction
7904 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7905 match(Set dst (SubL src1 src2));
7906 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7907 size(4);
7908 ins_encode %{
7909 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7910 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7911 %}
7912 ins_pipe(pipe_class_default);
7913 %}
7914
7915 // SubL + convL2I.
7916 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7917 match(Set dst (ConvL2I (SubL src1 src2)));
7918
7919 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7920 size(4);
7921 ins_encode %{
7922 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7923 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7924 %}
7925 ins_pipe(pipe_class_default);
7926 %}
7927
7928 // Immediate Subtraction
7929 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7930 // so this rule seems to be unused.
7931 // No constant pool entries required.
7932 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7933 match(Set dst (SubL src1 src2));
7934
7935 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7936 size(4);
7937 ins_encode %{
7938 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7939 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7940 %}
7941 ins_pipe(pipe_class_default);
7942 %}
7943
7944 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7945 // positive longs and 0xF...F for negative ones.
7946 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7947 // no match-rule, false predicate
7948 effect(DEF dst, USE src);
7949 predicate(false);
7950
7951 format %{ "SRADI $dst, $src, #63" %}
7952 size(4);
7953 ins_encode %{
7954 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7955 __ sradi($dst$$Register, $src$$Register, 0x3f);
7956 %}
7957 ins_pipe(pipe_class_default);
7958 %}
7959
7960 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7961 // positive longs and 0xF...F for negative ones.
7962 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7963 // no match-rule, false predicate
7964 effect(DEF dst, USE src);
7965 predicate(false);
7966
7967 format %{ "SRADI $dst, $src, #63" %}
7968 size(4);
7969 ins_encode %{
7970 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7971 __ sradi($dst$$Register, $src$$Register, 0x3f);
7972 %}
7973 ins_pipe(pipe_class_default);
7974 %}
7975
7976 // Long negation
7977 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7978 match(Set dst (SubL zero src2));
7979 format %{ "NEG $dst, $src2 \t// long" %}
7980 size(4);
7981 ins_encode %{
7982 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7983 __ neg($dst$$Register, $src2$$Register);
7984 %}
7985 ins_pipe(pipe_class_default);
7986 %}
7987
7988 // NegL + ConvL2I.
7989 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7990 match(Set dst (ConvL2I (SubL zero src2)));
7991
7992 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7993 size(4);
7994 ins_encode %{
7995 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7996 __ neg($dst$$Register, $src2$$Register);
7997 %}
7998 ins_pipe(pipe_class_default);
7999 %}
8000
8001 // Multiplication Instructions
8002 // Integer Multiplication
8003
8004 // Register Multiplication
8005 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8006 match(Set dst (MulI src1 src2));
8007 ins_cost(DEFAULT_COST);
8008
8009 format %{ "MULLW $dst, $src1, $src2" %}
8010 size(4);
8011 ins_encode %{
8012 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8013 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8014 %}
8015 ins_pipe(pipe_class_default);
8016 %}
8017
8018 // Immediate Multiplication
8019 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8020 match(Set dst (MulI src1 src2));
8021 ins_cost(DEFAULT_COST);
8022
8023 format %{ "MULLI $dst, $src1, $src2" %}
8024 size(4);
8025 ins_encode %{
8026 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8027 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8028 %}
8029 ins_pipe(pipe_class_default);
8030 %}
8031
8032 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8033 match(Set dst (MulL src1 src2));
8034 ins_cost(DEFAULT_COST);
8035
8036 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8037 size(4);
8038 ins_encode %{
8039 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8040 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8041 %}
8042 ins_pipe(pipe_class_default);
8043 %}
8044
8045 // Multiply high for optimized long division by constant.
8046 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8047 match(Set dst (MulHiL src1 src2));
8048 ins_cost(DEFAULT_COST);
8049
8050 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8051 size(4);
8052 ins_encode %{
8053 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8054 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8055 %}
8056 ins_pipe(pipe_class_default);
8057 %}
8058
8059 // Immediate Multiplication
8060 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8061 match(Set dst (MulL src1 src2));
8062 ins_cost(DEFAULT_COST);
8063
8064 format %{ "MULLI $dst, $src1, $src2" %}
8065 size(4);
8066 ins_encode %{
8067 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8068 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8069 %}
8070 ins_pipe(pipe_class_default);
8071 %}
8072
8073 // Integer Division with Immediate -1: Negate.
8074 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8075 match(Set dst (DivI src1 src2));
8076 ins_cost(DEFAULT_COST);
8077
8078 format %{ "NEG $dst, $src1 \t// /-1" %}
8079 size(4);
8080 ins_encode %{
8081 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8082 __ neg($dst$$Register, $src1$$Register);
8083 %}
8084 ins_pipe(pipe_class_default);
8085 %}
8086
8087 // Integer Division with constant, but not -1.
8088 // We should be able to improve this by checking the type of src2.
8089 // It might well be that src2 is known to be positive.
8090 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8091 match(Set dst (DivI src1 src2));
8092 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8093 ins_cost(2*DEFAULT_COST);
8094
8095 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8096 size(4);
8097 ins_encode %{
8098 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8099 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8100 %}
8101 ins_pipe(pipe_class_default);
8102 %}
8103
8104 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8105 effect(USE_DEF dst, USE src1, USE crx);
8106 predicate(false);
8107
8108 ins_variable_size_depending_on_alignment(true);
8109
8110 format %{ "CMOVE $dst, neg($src1), $crx" %}
8111 // Worst case is branch + move + stop, no stop without scheduler.
8112 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8113 ins_encode %{
8114 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8115 Label done;
8116 __ bne($crx$$CondRegister, done);
8117 __ neg($dst$$Register, $src1$$Register);
8118 // TODO PPC port __ endgroup_if_needed(_size == 12);
8119 __ bind(done);
8120 %}
8121 ins_pipe(pipe_class_default);
8122 %}
8123
8124 // Integer Division with Registers not containing constants.
8125 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8126 match(Set dst (DivI src1 src2));
8127 ins_cost(10*DEFAULT_COST);
8128
8129 expand %{
8130 immI16 imm %{ (int)-1 %}
8131 flagsReg tmp1;
8132 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8133 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8134 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8135 %}
8136 %}
8137
8138 // Long Division with Immediate -1: Negate.
8139 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8140 match(Set dst (DivL src1 src2));
8141 ins_cost(DEFAULT_COST);
8142
8143 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8144 size(4);
8145 ins_encode %{
8146 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8147 __ neg($dst$$Register, $src1$$Register);
8148 %}
8149 ins_pipe(pipe_class_default);
8150 %}
8151
8152 // Long Division with constant, but not -1.
8153 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8154 match(Set dst (DivL src1 src2));
8155 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8156 ins_cost(2*DEFAULT_COST);
8157
8158 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8159 size(4);
8160 ins_encode %{
8161 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8162 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8163 %}
8164 ins_pipe(pipe_class_default);
8165 %}
8166
8167 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8168 effect(USE_DEF dst, USE src1, USE crx);
8169 predicate(false);
8170
8171 ins_variable_size_depending_on_alignment(true);
8172
8173 format %{ "CMOVE $dst, neg($src1), $crx" %}
8174 // Worst case is branch + move + stop, no stop without scheduler.
8175 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8176 ins_encode %{
8177 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8178 Label done;
8179 __ bne($crx$$CondRegister, done);
8180 __ neg($dst$$Register, $src1$$Register);
8181 // TODO PPC port __ endgroup_if_needed(_size == 12);
8182 __ bind(done);
8183 %}
8184 ins_pipe(pipe_class_default);
8185 %}
8186
8187 // Long Division with Registers not containing constants.
8188 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8189 match(Set dst (DivL src1 src2));
8190 ins_cost(10*DEFAULT_COST);
8191
8192 expand %{
8193 immL16 imm %{ (int)-1 %}
8194 flagsReg tmp1;
8195 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8196 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8197 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8198 %}
8199 %}
8200
8201 // Integer Remainder with registers.
8202 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8203 match(Set dst (ModI src1 src2));
8204 ins_cost(10*DEFAULT_COST);
8205
8206 expand %{
8207 immI16 imm %{ (int)-1 %}
8208 flagsReg tmp1;
8209 iRegIdst tmp2;
8210 iRegIdst tmp3;
8211 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8212 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8213 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8214 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8215 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8216 %}
8217 %}
8218
8219 // Long Remainder with registers
8220 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8221 match(Set dst (ModL src1 src2));
8222 ins_cost(10*DEFAULT_COST);
8223
8224 expand %{
8225 immL16 imm %{ (int)-1 %}
8226 flagsReg tmp1;
8227 iRegLdst tmp2;
8228 iRegLdst tmp3;
8229 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8230 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8231 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8232 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8233 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8234 %}
8235 %}
8236
8237 // Integer Shift Instructions
8238
8239 // Register Shift Left
8240
8241 // Clear all but the lowest #mask bits.
8242 // Used to normalize shift amounts in registers.
8243 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8244 // no match-rule, false predicate
8245 effect(DEF dst, USE src, USE mask);
8246 predicate(false);
8247
8248 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8249 size(4);
8250 ins_encode %{
8251 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8252 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8253 %}
8254 ins_pipe(pipe_class_default);
8255 %}
8256
8257 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8258 // no match-rule, false predicate
8259 effect(DEF dst, USE src1, USE src2);
8260 predicate(false);
8261
8262 format %{ "SLW $dst, $src1, $src2" %}
8263 size(4);
8264 ins_encode %{
8265 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8266 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8267 %}
8268 ins_pipe(pipe_class_default);
8269 %}
8270
8271 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8272 match(Set dst (LShiftI src1 src2));
8273 ins_cost(DEFAULT_COST*2);
8274 expand %{
8275 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8276 iRegIdst tmpI;
8277 maskI_reg_imm(tmpI, src2, mask);
8278 lShiftI_reg_reg(dst, src1, tmpI);
8279 %}
8280 %}
8281
8282 // Register Shift Left Immediate
8283 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8284 match(Set dst (LShiftI src1 src2));
8285
8286 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8287 size(4);
8288 ins_encode %{
8289 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8290 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8291 %}
8292 ins_pipe(pipe_class_default);
8293 %}
8294
8295 // AndI with negpow2-constant + LShiftI
8296 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8297 match(Set dst (LShiftI (AndI src1 src2) src3));
8298 predicate(UseRotateAndMaskInstructionsPPC64);
8299
8300 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8301 size(4);
8302 ins_encode %{
8303 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8304 long src2 = $src2$$constant;
8305 long src3 = $src3$$constant;
8306 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8307 if (maskbits >= 32) {
8308 __ li($dst$$Register, 0); // addi
8309 } else {
8310 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8311 }
8312 %}
8313 ins_pipe(pipe_class_default);
8314 %}
8315
8316 // RShiftI + AndI with negpow2-constant + LShiftI
8317 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8318 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8319 predicate(UseRotateAndMaskInstructionsPPC64);
8320
8321 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8322 size(4);
8323 ins_encode %{
8324 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8325 long src2 = $src2$$constant;
8326 long src3 = $src3$$constant;
8327 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8328 if (maskbits >= 32) {
8329 __ li($dst$$Register, 0); // addi
8330 } else {
8331 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8332 }
8333 %}
8334 ins_pipe(pipe_class_default);
8335 %}
8336
8337 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8338 // no match-rule, false predicate
8339 effect(DEF dst, USE src1, USE src2);
8340 predicate(false);
8341
8342 format %{ "SLD $dst, $src1, $src2" %}
8343 size(4);
8344 ins_encode %{
8345 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8346 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8347 %}
8348 ins_pipe(pipe_class_default);
8349 %}
8350
8351 // Register Shift Left
8352 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8353 match(Set dst (LShiftL src1 src2));
8354 ins_cost(DEFAULT_COST*2);
8355 expand %{
8356 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8357 iRegIdst tmpI;
8358 maskI_reg_imm(tmpI, src2, mask);
8359 lShiftL_regL_regI(dst, src1, tmpI);
8360 %}
8361 %}
8362
8363 // Register Shift Left Immediate
8364 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8365 match(Set dst (LShiftL src1 src2));
8366 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8367 size(4);
8368 ins_encode %{
8369 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8370 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8371 %}
8372 ins_pipe(pipe_class_default);
8373 %}
8374
8375 // If we shift more than 32 bits, we need not convert I2L.
8376 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8377 match(Set dst (LShiftL (ConvI2L src1) src2));
8378 ins_cost(DEFAULT_COST);
8379
8380 size(4);
8381 format %{ "SLDI $dst, i2l($src1), $src2" %}
8382 ins_encode %{
8383 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8384 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8385 %}
8386 ins_pipe(pipe_class_default);
8387 %}
8388
8389 // Shift a postivie int to the left.
8390 // Clrlsldi clears the upper 32 bits and shifts.
8391 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8392 match(Set dst (LShiftL (ConvI2L src1) src2));
8393 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8394
8395 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8396 size(4);
8397 ins_encode %{
8398 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8399 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8400 %}
8401 ins_pipe(pipe_class_default);
8402 %}
8403
8404 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8405 // no match-rule, false predicate
8406 effect(DEF dst, USE src1, USE src2);
8407 predicate(false);
8408
8409 format %{ "SRAW $dst, $src1, $src2" %}
8410 size(4);
8411 ins_encode %{
8412 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8413 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8414 %}
8415 ins_pipe(pipe_class_default);
8416 %}
8417
8418 // Register Arithmetic Shift Right
8419 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8420 match(Set dst (RShiftI src1 src2));
8421 ins_cost(DEFAULT_COST*2);
8422 expand %{
8423 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8424 iRegIdst tmpI;
8425 maskI_reg_imm(tmpI, src2, mask);
8426 arShiftI_reg_reg(dst, src1, tmpI);
8427 %}
8428 %}
8429
8430 // Register Arithmetic Shift Right Immediate
8431 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8432 match(Set dst (RShiftI src1 src2));
8433
8434 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8435 size(4);
8436 ins_encode %{
8437 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8438 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8439 %}
8440 ins_pipe(pipe_class_default);
8441 %}
8442
8443 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8444 // no match-rule, false predicate
8445 effect(DEF dst, USE src1, USE src2);
8446 predicate(false);
8447
8448 format %{ "SRAD $dst, $src1, $src2" %}
8449 size(4);
8450 ins_encode %{
8451 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8452 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8453 %}
8454 ins_pipe(pipe_class_default);
8455 %}
8456
8457 // Register Shift Right Arithmetic Long
8458 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8459 match(Set dst (RShiftL src1 src2));
8460 ins_cost(DEFAULT_COST*2);
8461
8462 expand %{
8463 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8464 iRegIdst tmpI;
8465 maskI_reg_imm(tmpI, src2, mask);
8466 arShiftL_regL_regI(dst, src1, tmpI);
8467 %}
8468 %}
8469
8470 // Register Shift Right Immediate
8471 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8472 match(Set dst (RShiftL src1 src2));
8473
8474 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8475 size(4);
8476 ins_encode %{
8477 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8478 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8479 %}
8480 ins_pipe(pipe_class_default);
8481 %}
8482
8483 // RShiftL + ConvL2I
8484 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8485 match(Set dst (ConvL2I (RShiftL src1 src2)));
8486
8487 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8488 size(4);
8489 ins_encode %{
8490 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8491 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8492 %}
8493 ins_pipe(pipe_class_default);
8494 %}
8495
8496 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8497 // no match-rule, false predicate
8498 effect(DEF dst, USE src1, USE src2);
8499 predicate(false);
8500
8501 format %{ "SRW $dst, $src1, $src2" %}
8502 size(4);
8503 ins_encode %{
8504 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8505 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8506 %}
8507 ins_pipe(pipe_class_default);
8508 %}
8509
8510 // Register Shift Right
8511 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8512 match(Set dst (URShiftI src1 src2));
8513 ins_cost(DEFAULT_COST*2);
8514
8515 expand %{
8516 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8517 iRegIdst tmpI;
8518 maskI_reg_imm(tmpI, src2, mask);
8519 urShiftI_reg_reg(dst, src1, tmpI);
8520 %}
8521 %}
8522
8523 // Register Shift Right Immediate
8524 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8525 match(Set dst (URShiftI src1 src2));
8526
8527 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8528 size(4);
8529 ins_encode %{
8530 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8531 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8532 %}
8533 ins_pipe(pipe_class_default);
8534 %}
8535
8536 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8537 // no match-rule, false predicate
8538 effect(DEF dst, USE src1, USE src2);
8539 predicate(false);
8540
8541 format %{ "SRD $dst, $src1, $src2" %}
8542 size(4);
8543 ins_encode %{
8544 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8545 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8546 %}
8547 ins_pipe(pipe_class_default);
8548 %}
8549
8550 // Register Shift Right
8551 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8552 match(Set dst (URShiftL src1 src2));
8553 ins_cost(DEFAULT_COST*2);
8554
8555 expand %{
8556 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8557 iRegIdst tmpI;
8558 maskI_reg_imm(tmpI, src2, mask);
8559 urShiftL_regL_regI(dst, src1, tmpI);
8560 %}
8561 %}
8562
8563 // Register Shift Right Immediate
8564 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8565 match(Set dst (URShiftL src1 src2));
8566
8567 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8568 size(4);
8569 ins_encode %{
8570 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8571 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8572 %}
8573 ins_pipe(pipe_class_default);
8574 %}
8575
8576 // URShiftL + ConvL2I.
8577 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8578 match(Set dst (ConvL2I (URShiftL src1 src2)));
8579
8580 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8581 size(4);
8582 ins_encode %{
8583 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8584 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8585 %}
8586 ins_pipe(pipe_class_default);
8587 %}
8588
8589 // Register Shift Right Immediate with a CastP2X
8590 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8591 match(Set dst (URShiftL (CastP2X src1) src2));
8592
8593 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8594 size(4);
8595 ins_encode %{
8596 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8597 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8598 %}
8599 ins_pipe(pipe_class_default);
8600 %}
8601
8602 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8603 match(Set dst (ConvL2I (ConvI2L src)));
8604
8605 format %{ "EXTSW $dst, $src \t// int->int" %}
8606 size(4);
8607 ins_encode %{
8608 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8609 __ extsw($dst$$Register, $src$$Register);
8610 %}
8611 ins_pipe(pipe_class_default);
8612 %}
8613
8614 //----------Rotate Instructions------------------------------------------------
8615
8616 // Rotate Left by 8-bit immediate
8617 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8618 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8619 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8620
8621 format %{ "ROTLWI $dst, $src, $lshift" %}
8622 size(4);
8623 ins_encode %{
8624 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8625 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8626 %}
8627 ins_pipe(pipe_class_default);
8628 %}
8629
8630 // Rotate Right by 8-bit immediate
8631 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8632 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8633 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8634
8635 format %{ "ROTRWI $dst, $rshift" %}
8636 size(4);
8637 ins_encode %{
8638 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8639 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8640 %}
8641 ins_pipe(pipe_class_default);
8642 %}
8643
8644 //----------Floating Point Arithmetic Instructions-----------------------------
8645
8646 // Add float single precision
8647 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8648 match(Set dst (AddF src1 src2));
8649
8650 format %{ "FADDS $dst, $src1, $src2" %}
8651 size(4);
8652 ins_encode %{
8653 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8654 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8655 %}
8656 ins_pipe(pipe_class_default);
8657 %}
8658
8659 // Add float double precision
8660 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8661 match(Set dst (AddD src1 src2));
8662
8663 format %{ "FADD $dst, $src1, $src2" %}
8664 size(4);
8665 ins_encode %{
8666 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8667 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8668 %}
8669 ins_pipe(pipe_class_default);
8670 %}
8671
8672 // Sub float single precision
8673 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8674 match(Set dst (SubF src1 src2));
8675
8676 format %{ "FSUBS $dst, $src1, $src2" %}
8677 size(4);
8678 ins_encode %{
8679 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8680 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8681 %}
8682 ins_pipe(pipe_class_default);
8683 %}
8684
8685 // Sub float double precision
8686 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8687 match(Set dst (SubD src1 src2));
8688 format %{ "FSUB $dst, $src1, $src2" %}
8689 size(4);
8690 ins_encode %{
8691 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8692 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8693 %}
8694 ins_pipe(pipe_class_default);
8695 %}
8696
8697 // Mul float single precision
8698 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8699 match(Set dst (MulF src1 src2));
8700 format %{ "FMULS $dst, $src1, $src2" %}
8701 size(4);
8702 ins_encode %{
8703 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8704 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8705 %}
8706 ins_pipe(pipe_class_default);
8707 %}
8708
8709 // Mul float double precision
8710 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8711 match(Set dst (MulD src1 src2));
8712 format %{ "FMUL $dst, $src1, $src2" %}
8713 size(4);
8714 ins_encode %{
8715 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8716 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8717 %}
8718 ins_pipe(pipe_class_default);
8719 %}
8720
8721 // Div float single precision
8722 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8723 match(Set dst (DivF src1 src2));
8724 format %{ "FDIVS $dst, $src1, $src2" %}
8725 size(4);
8726 ins_encode %{
8727 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8728 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8729 %}
8730 ins_pipe(pipe_class_default);
8731 %}
8732
8733 // Div float double precision
8734 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8735 match(Set dst (DivD src1 src2));
8736 format %{ "FDIV $dst, $src1, $src2" %}
8737 size(4);
8738 ins_encode %{
8739 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8740 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8741 %}
8742 ins_pipe(pipe_class_default);
8743 %}
8744
8745 // Absolute float single precision
8746 instruct absF_reg(regF dst, regF src) %{
8747 match(Set dst (AbsF src));
8748 format %{ "FABS $dst, $src \t// float" %}
8749 size(4);
8750 ins_encode %{
8751 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8752 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8753 %}
8754 ins_pipe(pipe_class_default);
8755 %}
8756
8757 // Absolute float double precision
8758 instruct absD_reg(regD dst, regD src) %{
8759 match(Set dst (AbsD src));
8760 format %{ "FABS $dst, $src \t// double" %}
8761 size(4);
8762 ins_encode %{
8763 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8764 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8765 %}
8766 ins_pipe(pipe_class_default);
8767 %}
8768
8769 instruct negF_reg(regF dst, regF src) %{
8770 match(Set dst (NegF src));
8771 format %{ "FNEG $dst, $src \t// float" %}
8772 size(4);
8773 ins_encode %{
8774 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8775 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8776 %}
8777 ins_pipe(pipe_class_default);
8778 %}
8779
8780 instruct negD_reg(regD dst, regD src) %{
8781 match(Set dst (NegD src));
8782 format %{ "FNEG $dst, $src \t// double" %}
8783 size(4);
8784 ins_encode %{
8785 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8786 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8787 %}
8788 ins_pipe(pipe_class_default);
8789 %}
8790
8791 // AbsF + NegF.
8792 instruct negF_absF_reg(regF dst, regF src) %{
8793 match(Set dst (NegF (AbsF src)));
8794 format %{ "FNABS $dst, $src \t// float" %}
8795 size(4);
8796 ins_encode %{
8797 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8798 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8799 %}
8800 ins_pipe(pipe_class_default);
8801 %}
8802
8803 // AbsD + NegD.
8804 instruct negD_absD_reg(regD dst, regD src) %{
8805 match(Set dst (NegD (AbsD src)));
8806 format %{ "FNABS $dst, $src \t// double" %}
8807 size(4);
8808 ins_encode %{
8809 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8810 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8811 %}
8812 ins_pipe(pipe_class_default);
8813 %}
8814
8815 // VM_Version::has_fsqrt() decides if this node will be used.
8816 // Sqrt float double precision
8817 instruct sqrtD_reg(regD dst, regD src) %{
8818 match(Set dst (SqrtD src));
8819 format %{ "FSQRT $dst, $src" %}
8820 size(4);
8821 ins_encode %{
8822 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8823 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8824 %}
8825 ins_pipe(pipe_class_default);
8826 %}
8827
8828 // Single-precision sqrt.
8829 instruct sqrtF_reg(regF dst, regF src) %{
8830 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8831 predicate(VM_Version::has_fsqrts());
8832 ins_cost(DEFAULT_COST);
8833
8834 format %{ "FSQRTS $dst, $src" %}
8835 size(4);
8836 ins_encode %{
8837 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8838 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8839 %}
8840 ins_pipe(pipe_class_default);
8841 %}
8842
8843 instruct roundDouble_nop(regD dst) %{
8844 match(Set dst (RoundDouble dst));
8845 ins_cost(0);
8846
8847 format %{ " -- \t// RoundDouble not needed - empty" %}
8848 size(0);
8849 // PPC results are already "rounded" (i.e., normal-format IEEE).
8850 ins_encode( /*empty*/ );
8851 ins_pipe(pipe_class_default);
8852 %}
8853
8854 instruct roundFloat_nop(regF dst) %{
8855 match(Set dst (RoundFloat dst));
8856 ins_cost(0);
8857
8858 format %{ " -- \t// RoundFloat not needed - empty" %}
8859 size(0);
8860 // PPC results are already "rounded" (i.e., normal-format IEEE).
8861 ins_encode( /*empty*/ );
8862 ins_pipe(pipe_class_default);
8863 %}
8864
8865 //----------Logical Instructions-----------------------------------------------
8866
8867 // And Instructions
8868
8869 // Register And
8870 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8871 match(Set dst (AndI src1 src2));
8872 format %{ "AND $dst, $src1, $src2" %}
8873 size(4);
8874 ins_encode %{
8875 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8876 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8877 %}
8878 ins_pipe(pipe_class_default);
8879 %}
8880
8881 // Immediate And
8882 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8883 match(Set dst (AndI src1 src2));
8884 effect(KILL cr0);
8885
8886 format %{ "ANDI $dst, $src1, $src2" %}
8887 size(4);
8888 ins_encode %{
8889 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8890 // FIXME: avoid andi_ ?
8891 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8892 %}
8893 ins_pipe(pipe_class_default);
8894 %}
8895
8896 // Immediate And where the immediate is a negative power of 2.
8897 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8898 match(Set dst (AndI src1 src2));
8899 format %{ "ANDWI $dst, $src1, $src2" %}
8900 size(4);
8901 ins_encode %{
8902 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8903 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8904 %}
8905 ins_pipe(pipe_class_default);
8906 %}
8907
8908 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8909 match(Set dst (AndI src1 src2));
8910 format %{ "ANDWI $dst, $src1, $src2" %}
8911 size(4);
8912 ins_encode %{
8913 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8914 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8915 %}
8916 ins_pipe(pipe_class_default);
8917 %}
8918
8919 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8920 match(Set dst (AndI src1 src2));
8921 predicate(UseRotateAndMaskInstructionsPPC64);
8922 format %{ "ANDWI $dst, $src1, $src2" %}
8923 size(4);
8924 ins_encode %{
8925 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8926 __ rlwinm($dst$$Register, $src1$$Register, 0,
8927 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8928 %}
8929 ins_pipe(pipe_class_default);
8930 %}
8931
8932 // Register And Long
8933 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8934 match(Set dst (AndL src1 src2));
8935 ins_cost(DEFAULT_COST);
8936
8937 format %{ "AND $dst, $src1, $src2 \t// long" %}
8938 size(4);
8939 ins_encode %{
8940 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8941 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8942 %}
8943 ins_pipe(pipe_class_default);
8944 %}
8945
8946 // Immediate And long
8947 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8948 match(Set dst (AndL src1 src2));
8949 effect(KILL cr0);
8950 ins_cost(DEFAULT_COST);
8951
8952 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8953 size(4);
8954 ins_encode %{
8955 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8956 // FIXME: avoid andi_ ?
8957 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8958 %}
8959 ins_pipe(pipe_class_default);
8960 %}
8961
8962 // Immediate And Long where the immediate is a negative power of 2.
8963 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8964 match(Set dst (AndL src1 src2));
8965 format %{ "ANDDI $dst, $src1, $src2" %}
8966 size(4);
8967 ins_encode %{
8968 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8969 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8970 %}
8971 ins_pipe(pipe_class_default);
8972 %}
8973
8974 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8975 match(Set dst (AndL src1 src2));
8976 format %{ "ANDDI $dst, $src1, $src2" %}
8977 size(4);
8978 ins_encode %{
8979 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8980 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8981 %}
8982 ins_pipe(pipe_class_default);
8983 %}
8984
8985 // AndL + ConvL2I.
8986 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8987 match(Set dst (ConvL2I (AndL src1 src2)));
8988 ins_cost(DEFAULT_COST);
8989
8990 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8991 size(4);
8992 ins_encode %{
8993 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8994 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8995 %}
8996 ins_pipe(pipe_class_default);
8997 %}
8998
8999 // Or Instructions
9000
9001 // Register Or
9002 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9003 match(Set dst (OrI src1 src2));
9004 format %{ "OR $dst, $src1, $src2" %}
9005 size(4);
9006 ins_encode %{
9007 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9008 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9009 %}
9010 ins_pipe(pipe_class_default);
9011 %}
9012
9013 // Expand does not work with above instruct. (??)
9014 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9015 // no match-rule
9016 effect(DEF dst, USE src1, USE src2);
9017 format %{ "OR $dst, $src1, $src2" %}
9018 size(4);
9019 ins_encode %{
9020 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9021 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9022 %}
9023 ins_pipe(pipe_class_default);
9024 %}
9025
9026 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9027 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9028 ins_cost(DEFAULT_COST*3);
9029
9030 expand %{
9031 // FIXME: we should do this in the ideal world.
9032 iRegIdst tmp1;
9033 iRegIdst tmp2;
9034 orI_reg_reg(tmp1, src1, src2);
9035 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9036 orI_reg_reg(dst, tmp1, tmp2);
9037 %}
9038 %}
9039
9040 // Immediate Or
9041 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9042 match(Set dst (OrI src1 src2));
9043 format %{ "ORI $dst, $src1, $src2" %}
9044 size(4);
9045 ins_encode %{
9046 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9047 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9048 %}
9049 ins_pipe(pipe_class_default);
9050 %}
9051
9052 // Register Or Long
9053 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9054 match(Set dst (OrL src1 src2));
9055 ins_cost(DEFAULT_COST);
9056
9057 size(4);
9058 format %{ "OR $dst, $src1, $src2 \t// long" %}
9059 ins_encode %{
9060 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9061 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9062 %}
9063 ins_pipe(pipe_class_default);
9064 %}
9065
9066 // OrL + ConvL2I.
9067 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9068 match(Set dst (ConvL2I (OrL src1 src2)));
9069 ins_cost(DEFAULT_COST);
9070
9071 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9072 size(4);
9073 ins_encode %{
9074 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9075 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9076 %}
9077 ins_pipe(pipe_class_default);
9078 %}
9079
9080 // Immediate Or long
9081 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9082 match(Set dst (OrL src1 con));
9083 ins_cost(DEFAULT_COST);
9084
9085 format %{ "ORI $dst, $src1, $con \t// long" %}
9086 size(4);
9087 ins_encode %{
9088 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9089 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9090 %}
9091 ins_pipe(pipe_class_default);
9092 %}
9093
9094 // Xor Instructions
9095
9096 // Register Xor
9097 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9098 match(Set dst (XorI src1 src2));
9099 format %{ "XOR $dst, $src1, $src2" %}
9100 size(4);
9101 ins_encode %{
9102 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9103 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9104 %}
9105 ins_pipe(pipe_class_default);
9106 %}
9107
9108 // Expand does not work with above instruct. (??)
9109 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9110 // no match-rule
9111 effect(DEF dst, USE src1, USE src2);
9112 format %{ "XOR $dst, $src1, $src2" %}
9113 size(4);
9114 ins_encode %{
9115 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9116 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9117 %}
9118 ins_pipe(pipe_class_default);
9119 %}
9120
9121 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9122 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9123 ins_cost(DEFAULT_COST*3);
9124
9125 expand %{
9126 // FIXME: we should do this in the ideal world.
9127 iRegIdst tmp1;
9128 iRegIdst tmp2;
9129 xorI_reg_reg(tmp1, src1, src2);
9130 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9131 xorI_reg_reg(dst, tmp1, tmp2);
9132 %}
9133 %}
9134
9135 // Immediate Xor
9136 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9137 match(Set dst (XorI src1 src2));
9138 format %{ "XORI $dst, $src1, $src2" %}
9139 size(4);
9140 ins_encode %{
9141 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9142 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9143 %}
9144 ins_pipe(pipe_class_default);
9145 %}
9146
9147 // Register Xor Long
9148 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9149 match(Set dst (XorL src1 src2));
9150 ins_cost(DEFAULT_COST);
9151
9152 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9153 size(4);
9154 ins_encode %{
9155 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9156 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9157 %}
9158 ins_pipe(pipe_class_default);
9159 %}
9160
9161 // XorL + ConvL2I.
9162 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9163 match(Set dst (ConvL2I (XorL src1 src2)));
9164 ins_cost(DEFAULT_COST);
9165
9166 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9167 size(4);
9168 ins_encode %{
9169 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9170 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9171 %}
9172 ins_pipe(pipe_class_default);
9173 %}
9174
9175 // Immediate Xor Long
9176 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9177 match(Set dst (XorL src1 src2));
9178 ins_cost(DEFAULT_COST);
9179
9180 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9181 size(4);
9182 ins_encode %{
9183 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9184 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9185 %}
9186 ins_pipe(pipe_class_default);
9187 %}
9188
9189 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9190 match(Set dst (XorI src1 src2));
9191 ins_cost(DEFAULT_COST);
9192
9193 format %{ "NOT $dst, $src1 ($src2)" %}
9194 size(4);
9195 ins_encode %{
9196 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9197 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9198 %}
9199 ins_pipe(pipe_class_default);
9200 %}
9201
9202 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9203 match(Set dst (XorL src1 src2));
9204 ins_cost(DEFAULT_COST);
9205
9206 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9207 size(4);
9208 ins_encode %{
9209 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9210 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9211 %}
9212 ins_pipe(pipe_class_default);
9213 %}
9214
9215 // And-complement
9216 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9217 match(Set dst (AndI (XorI src1 src2) src3));
9218 ins_cost(DEFAULT_COST);
9219
9220 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9221 size(4);
9222 ins_encode( enc_andc(dst, src3, src1) );
9223 ins_pipe(pipe_class_default);
9224 %}
9225
9226 // And-complement
9227 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9228 // no match-rule, false predicate
9229 effect(DEF dst, USE src1, USE src2);
9230 predicate(false);
9231
9232 format %{ "ANDC $dst, $src1, $src2" %}
9233 size(4);
9234 ins_encode %{
9235 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9236 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9237 %}
9238 ins_pipe(pipe_class_default);
9239 %}
9240
9241 //----------Moves between int/long and float/double----------------------------
9242 //
9243 // The following rules move values from int/long registers/stack-locations
9244 // to float/double registers/stack-locations and vice versa, without doing any
9245 // conversions. These rules are used to implement the bit-conversion methods
9246 // of java.lang.Float etc., e.g.
9247 // int floatToIntBits(float value)
9248 // float intBitsToFloat(int bits)
9249 //
9250 // Notes on the implementation on ppc64:
9251 // We only provide rules which move between a register and a stack-location,
9252 // because we always have to go through memory when moving between a float
9253 // register and an integer register.
9254
9255 //---------- Chain stack slots between similar types --------
9256
9257 // These are needed so that the rules below can match.
9258
9259 // Load integer from stack slot
9260 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9261 match(Set dst src);
9262 ins_cost(MEMORY_REF_COST);
9263
9264 format %{ "LWZ $dst, $src" %}
9265 size(4);
9266 ins_encode( enc_lwz(dst, src) );
9267 ins_pipe(pipe_class_memory);
9268 %}
9269
9270 // Store integer to stack slot
9271 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9272 match(Set dst src);
9273 ins_cost(MEMORY_REF_COST);
9274
9275 format %{ "STW $src, $dst \t// stk" %}
9276 size(4);
9277 ins_encode( enc_stw(src, dst) ); // rs=rt
9278 ins_pipe(pipe_class_memory);
9279 %}
9280
9281 // Load long from stack slot
9282 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9283 match(Set dst src);
9284 ins_cost(MEMORY_REF_COST);
9285
9286 format %{ "LD $dst, $src \t// long" %}
9287 size(4);
9288 ins_encode( enc_ld(dst, src) );
9289 ins_pipe(pipe_class_memory);
9290 %}
9291
9292 // Store long to stack slot
9293 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9294 match(Set dst src);
9295 ins_cost(MEMORY_REF_COST);
9296
9297 format %{ "STD $src, $dst \t// long" %}
9298 size(4);
9299 ins_encode( enc_std(src, dst) ); // rs=rt
9300 ins_pipe(pipe_class_memory);
9301 %}
9302
9303 //----------Moves between int and float
9304
9305 // Move float value from float stack-location to integer register.
9306 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9307 match(Set dst (MoveF2I src));
9308 ins_cost(MEMORY_REF_COST);
9309
9310 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9311 size(4);
9312 ins_encode( enc_lwz(dst, src) );
9313 ins_pipe(pipe_class_memory);
9314 %}
9315
9316 // Move float value from float register to integer stack-location.
9317 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9318 match(Set dst (MoveF2I src));
9319 ins_cost(MEMORY_REF_COST);
9320
9321 format %{ "STFS $src, $dst \t// MoveF2I" %}
9322 size(4);
9323 ins_encode( enc_stfs(src, dst) );
9324 ins_pipe(pipe_class_memory);
9325 %}
9326
9327 // Move integer value from integer stack-location to float register.
9328 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9329 match(Set dst (MoveI2F src));
9330 ins_cost(MEMORY_REF_COST);
9331
9332 format %{ "LFS $dst, $src \t// MoveI2F" %}
9333 size(4);
9334 ins_encode %{
9335 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9336 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9337 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9338 %}
9339 ins_pipe(pipe_class_memory);
9340 %}
9341
9342 // Move integer value from integer register to float stack-location.
9343 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9344 match(Set dst (MoveI2F src));
9345 ins_cost(MEMORY_REF_COST);
9346
9347 format %{ "STW $src, $dst \t// MoveI2F" %}
9348 size(4);
9349 ins_encode( enc_stw(src, dst) );
9350 ins_pipe(pipe_class_memory);
9351 %}
9352
9353 //----------Moves between long and float
9354
9355 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9356 // no match-rule, false predicate
9357 effect(DEF dst, USE src);
9358 predicate(false);
9359
9360 format %{ "storeD $src, $dst \t// STACK" %}
9361 size(4);
9362 ins_encode( enc_stfd(src, dst) );
9363 ins_pipe(pipe_class_default);
9364 %}
9365
9366 //----------Moves between long and double
9367
9368 // Move double value from double stack-location to long register.
9369 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9370 match(Set dst (MoveD2L src));
9371 ins_cost(MEMORY_REF_COST);
9372 size(4);
9373 format %{ "LD $dst, $src \t// MoveD2L" %}
9374 ins_encode( enc_ld(dst, src) );
9375 ins_pipe(pipe_class_memory);
9376 %}
9377
9378 // Move double value from double register to long stack-location.
9379 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9380 match(Set dst (MoveD2L src));
9381 effect(DEF dst, USE src);
9382 ins_cost(MEMORY_REF_COST);
9383
9384 format %{ "STFD $src, $dst \t// MoveD2L" %}
9385 size(4);
9386 ins_encode( enc_stfd(src, dst) );
9387 ins_pipe(pipe_class_memory);
9388 %}
9389
9390 // Move long value from long stack-location to double register.
9391 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9392 match(Set dst (MoveL2D src));
9393 ins_cost(MEMORY_REF_COST);
9394
9395 format %{ "LFD $dst, $src \t// MoveL2D" %}
9396 size(4);
9397 ins_encode( enc_lfd(dst, src) );
9398 ins_pipe(pipe_class_memory);
9399 %}
9400
9401 // Move long value from long register to double stack-location.
9402 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9403 match(Set dst (MoveL2D src));
9404 ins_cost(MEMORY_REF_COST);
9405
9406 format %{ "STD $src, $dst \t// MoveL2D" %}
9407 size(4);
9408 ins_encode( enc_std(src, dst) );
9409 ins_pipe(pipe_class_memory);
9410 %}
9411
9412 //----------Register Move Instructions-----------------------------------------
9413
9414 // Replicate for Superword
9415
9416 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9417 predicate(false);
9418 effect(DEF dst, USE src);
9419
9420 format %{ "MR $dst, $src \t// replicate " %}
9421 // variable size, 0 or 4.
9422 ins_encode %{
9423 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9424 __ mr_if_needed($dst$$Register, $src$$Register);
9425 %}
9426 ins_pipe(pipe_class_default);
9427 %}
9428
9429 //----------Cast instructions (Java-level type cast)---------------------------
9430
9431 // Cast Long to Pointer for unsafe natives.
9432 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9433 match(Set dst (CastX2P src));
9434
9435 format %{ "MR $dst, $src \t// Long->Ptr" %}
9436 // variable size, 0 or 4.
9437 ins_encode %{
9438 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9439 __ mr_if_needed($dst$$Register, $src$$Register);
9440 %}
9441 ins_pipe(pipe_class_default);
9442 %}
9443
9444 // Cast Pointer to Long for unsafe natives.
9445 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9446 match(Set dst (CastP2X src));
9447
9448 format %{ "MR $dst, $src \t// Ptr->Long" %}
9449 // variable size, 0 or 4.
9450 ins_encode %{
9451 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9452 __ mr_if_needed($dst$$Register, $src$$Register);
9453 %}
9454 ins_pipe(pipe_class_default);
9455 %}
9456
9457 instruct castPP(iRegPdst dst) %{
9458 match(Set dst (CastPP dst));
9459 format %{ " -- \t// castPP of $dst" %}
9460 size(0);
9461 ins_encode( /*empty*/ );
9462 ins_pipe(pipe_class_default);
9463 %}
9464
9465 instruct castII(iRegIdst dst) %{
9466 match(Set dst (CastII dst));
9467 format %{ " -- \t// castII of $dst" %}
9468 size(0);
9469 ins_encode( /*empty*/ );
9470 ins_pipe(pipe_class_default);
9471 %}
9472
9473 instruct checkCastPP(iRegPdst dst) %{
9474 match(Set dst (CheckCastPP dst));
9475 format %{ " -- \t// checkcastPP of $dst" %}
9476 size(0);
9477 ins_encode( /*empty*/ );
9478 ins_pipe(pipe_class_default);
9479 %}
9480
9481 //----------Convert instructions-----------------------------------------------
9482
9483 // Convert to boolean.
9484
9485 // int_to_bool(src) : { 1 if src != 0
9486 // { 0 else
9487 //
9488 // strategy:
9489 // 1) Count leading zeros of 32 bit-value src,
9490 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9491 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9492 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9493
9494 // convI2Bool
9495 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9496 match(Set dst (Conv2B src));
9497 predicate(UseCountLeadingZerosInstructionsPPC64);
9498 ins_cost(DEFAULT_COST);
9499
9500 expand %{
9501 immI shiftAmount %{ 0x5 %}
9502 uimmI16 mask %{ 0x1 %}
9503 iRegIdst tmp1;
9504 iRegIdst tmp2;
9505 countLeadingZerosI(tmp1, src);
9506 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9507 xorI_reg_uimm16(dst, tmp2, mask);
9508 %}
9509 %}
9510
9511 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9512 match(Set dst (Conv2B src));
9513 effect(TEMP crx);
9514 predicate(!UseCountLeadingZerosInstructionsPPC64);
9515 ins_cost(DEFAULT_COST);
9516
9517 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9518 "LI $dst, #0\n\t"
9519 "BEQ $crx, done\n\t"
9520 "LI $dst, #1\n"
9521 "done:" %}
9522 size(16);
9523 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9524 ins_pipe(pipe_class_compare);
9525 %}
9526
9527 // ConvI2B + XorI
9528 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9529 match(Set dst (XorI (Conv2B src) mask));
9530 predicate(UseCountLeadingZerosInstructionsPPC64);
9531 ins_cost(DEFAULT_COST);
9532
9533 expand %{
9534 immI shiftAmount %{ 0x5 %}
9535 iRegIdst tmp1;
9536 countLeadingZerosI(tmp1, src);
9537 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9538 %}
9539 %}
9540
9541 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9542 match(Set dst (XorI (Conv2B src) mask));
9543 effect(TEMP crx);
9544 predicate(!UseCountLeadingZerosInstructionsPPC64);
9545 ins_cost(DEFAULT_COST);
9546
9547 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9548 "LI $dst, #1\n\t"
9549 "BEQ $crx, done\n\t"
9550 "LI $dst, #0\n"
9551 "done:" %}
9552 size(16);
9553 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9554 ins_pipe(pipe_class_compare);
9555 %}
9556
9557 // AndI 0b0..010..0 + ConvI2B
9558 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9559 match(Set dst (Conv2B (AndI src mask)));
9560 predicate(UseRotateAndMaskInstructionsPPC64);
9561 ins_cost(DEFAULT_COST);
9562
9563 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9564 size(4);
9565 ins_encode %{
9566 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9567 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9568 %}
9569 ins_pipe(pipe_class_default);
9570 %}
9571
9572 // Convert pointer to boolean.
9573 //
9574 // ptr_to_bool(src) : { 1 if src != 0
9575 // { 0 else
9576 //
9577 // strategy:
9578 // 1) Count leading zeros of 64 bit-value src,
9579 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9580 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9581 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9582
9583 // ConvP2B
9584 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9585 match(Set dst (Conv2B src));
9586 predicate(UseCountLeadingZerosInstructionsPPC64);
9587 ins_cost(DEFAULT_COST);
9588
9589 expand %{
9590 immI shiftAmount %{ 0x6 %}
9591 uimmI16 mask %{ 0x1 %}
9592 iRegIdst tmp1;
9593 iRegIdst tmp2;
9594 countLeadingZerosP(tmp1, src);
9595 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9596 xorI_reg_uimm16(dst, tmp2, mask);
9597 %}
9598 %}
9599
9600 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9601 match(Set dst (Conv2B src));
9602 effect(TEMP crx);
9603 predicate(!UseCountLeadingZerosInstructionsPPC64);
9604 ins_cost(DEFAULT_COST);
9605
9606 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9607 "LI $dst, #0\n\t"
9608 "BEQ $crx, done\n\t"
9609 "LI $dst, #1\n"
9610 "done:" %}
9611 size(16);
9612 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9613 ins_pipe(pipe_class_compare);
9614 %}
9615
9616 // ConvP2B + XorI
9617 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9618 match(Set dst (XorI (Conv2B src) mask));
9619 predicate(UseCountLeadingZerosInstructionsPPC64);
9620 ins_cost(DEFAULT_COST);
9621
9622 expand %{
9623 immI shiftAmount %{ 0x6 %}
9624 iRegIdst tmp1;
9625 countLeadingZerosP(tmp1, src);
9626 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9627 %}
9628 %}
9629
9630 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9631 match(Set dst (XorI (Conv2B src) mask));
9632 effect(TEMP crx);
9633 predicate(!UseCountLeadingZerosInstructionsPPC64);
9634 ins_cost(DEFAULT_COST);
9635
9636 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9637 "LI $dst, #1\n\t"
9638 "BEQ $crx, done\n\t"
9639 "LI $dst, #0\n"
9640 "done:" %}
9641 size(16);
9642 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9643 ins_pipe(pipe_class_compare);
9644 %}
9645
9646 // if src1 < src2, return -1 else return 0
9647 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9648 match(Set dst (CmpLTMask src1 src2));
9649 ins_cost(DEFAULT_COST*4);
9650
9651 expand %{
9652 iRegLdst src1s;
9653 iRegLdst src2s;
9654 iRegLdst diff;
9655 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9656 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9657 subL_reg_reg(diff, src1s, src2s);
9658 // Need to consider >=33 bit result, therefore we need signmaskL.
9659 signmask64I_regL(dst, diff);
9660 %}
9661 %}
9662
9663 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9664 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9665 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9666 size(4);
9667 ins_encode %{
9668 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9669 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9670 %}
9671 ins_pipe(pipe_class_default);
9672 %}
9673
9674 //----------Arithmetic Conversion Instructions---------------------------------
9675
9676 // Convert to Byte -- nop
9677 // Convert to Short -- nop
9678
9679 // Convert to Int
9680
9681 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9682 match(Set dst (RShiftI (LShiftI src amount) amount));
9683 format %{ "EXTSB $dst, $src \t// byte->int" %}
9684 size(4);
9685 ins_encode %{
9686 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9687 __ extsb($dst$$Register, $src$$Register);
9688 %}
9689 ins_pipe(pipe_class_default);
9690 %}
9691
9692 // LShiftI 16 + RShiftI 16 converts short to int.
9693 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9694 match(Set dst (RShiftI (LShiftI src amount) amount));
9695 format %{ "EXTSH $dst, $src \t// short->int" %}
9696 size(4);
9697 ins_encode %{
9698 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9699 __ extsh($dst$$Register, $src$$Register);
9700 %}
9701 ins_pipe(pipe_class_default);
9702 %}
9703
9704 // ConvL2I + ConvI2L: Sign extend int in long register.
9705 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9706 match(Set dst (ConvI2L (ConvL2I src)));
9707
9708 format %{ "EXTSW $dst, $src \t// long->long" %}
9709 size(4);
9710 ins_encode %{
9711 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9712 __ extsw($dst$$Register, $src$$Register);
9713 %}
9714 ins_pipe(pipe_class_default);
9715 %}
9716
9717 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9718 match(Set dst (ConvL2I src));
9719 format %{ "MR $dst, $src \t// long->int" %}
9720 // variable size, 0 or 4
9721 ins_encode %{
9722 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9723 __ mr_if_needed($dst$$Register, $src$$Register);
9724 %}
9725 ins_pipe(pipe_class_default);
9726 %}
9727
9728 instruct convD2IRaw_regD(regD dst, regD src) %{
9729 // no match-rule, false predicate
9730 effect(DEF dst, USE src);
9731 predicate(false);
9732
9733 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9734 size(4);
9735 ins_encode %{
9736 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9737 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9738 %}
9739 ins_pipe(pipe_class_default);
9740 %}
9741
9742 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9743 // no match-rule, false predicate
9744 effect(DEF dst, USE crx, USE src);
9745 predicate(false);
9746
9747 ins_variable_size_depending_on_alignment(true);
9748
9749 format %{ "cmovI $crx, $dst, $src" %}
9750 // Worst case is branch + move + stop, no stop without scheduler.
9751 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9752 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9753 ins_pipe(pipe_class_default);
9754 %}
9755
9756 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9757 // no match-rule, false predicate
9758 effect(DEF dst, USE crx, USE mem);
9759 predicate(false);
9760
9761 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9762 postalloc_expand %{
9763 //
9764 // replaces
9765 //
9766 // region dst crx mem
9767 // \ | | /
9768 // dst=cmovI_bso_stackSlotL_conLvalue0
9769 //
9770 // with
9771 //
9772 // region dst
9773 // \ /
9774 // dst=loadConI16(0)
9775 // |
9776 // ^ region dst crx mem
9777 // | \ | | /
9778 // dst=cmovI_bso_stackSlotL
9779 //
9780
9781 // Create new nodes.
9782 MachNode *m1 = new loadConI16Node();
9783 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9784
9785 // inputs for new nodes
9786 m1->add_req(n_region);
9787 m2->add_req(n_region, n_crx, n_mem);
9788
9789 // precedences for new nodes
9790 m2->add_prec(m1);
9791
9792 // operands for new nodes
9793 m1->_opnds[0] = op_dst;
9794 m1->_opnds[1] = new immI16Oper(0);
9795
9796 m2->_opnds[0] = op_dst;
9797 m2->_opnds[1] = op_crx;
9798 m2->_opnds[2] = op_mem;
9799
9800 // registers for new nodes
9801 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9802 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9803
9804 // Insert new nodes.
9805 nodes->push(m1);
9806 nodes->push(m2);
9807 %}
9808 %}
9809
9810 // Double to Int conversion, NaN is mapped to 0.
9811 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9812 match(Set dst (ConvD2I src));
9813 ins_cost(DEFAULT_COST);
9814
9815 expand %{
9816 regD tmpD;
9817 stackSlotL tmpS;
9818 flagsReg crx;
9819 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9820 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9821 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9822 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9823 %}
9824 %}
9825
9826 instruct convF2IRaw_regF(regF dst, regF src) %{
9827 // no match-rule, false predicate
9828 effect(DEF dst, USE src);
9829 predicate(false);
9830
9831 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9832 size(4);
9833 ins_encode %{
9834 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9835 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9836 %}
9837 ins_pipe(pipe_class_default);
9838 %}
9839
9840 // Float to Int conversion, NaN is mapped to 0.
9841 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9842 match(Set dst (ConvF2I src));
9843 ins_cost(DEFAULT_COST);
9844
9845 expand %{
9846 regF tmpF;
9847 stackSlotL tmpS;
9848 flagsReg crx;
9849 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9850 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9851 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9852 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9853 %}
9854 %}
9855
9856 // Convert to Long
9857
9858 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9859 match(Set dst (ConvI2L src));
9860 format %{ "EXTSW $dst, $src \t// int->long" %}
9861 size(4);
9862 ins_encode %{
9863 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9864 __ extsw($dst$$Register, $src$$Register);
9865 %}
9866 ins_pipe(pipe_class_default);
9867 %}
9868
9869 // Zero-extend: convert unsigned int to long (convUI2L).
9870 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9871 match(Set dst (AndL (ConvI2L src) mask));
9872 ins_cost(DEFAULT_COST);
9873
9874 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9875 size(4);
9876 ins_encode %{
9877 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9878 __ clrldi($dst$$Register, $src$$Register, 32);
9879 %}
9880 ins_pipe(pipe_class_default);
9881 %}
9882
9883 // Zero-extend: convert unsigned int to long in long register.
9884 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9885 match(Set dst (AndL src mask));
9886 ins_cost(DEFAULT_COST);
9887
9888 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9889 size(4);
9890 ins_encode %{
9891 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9892 __ clrldi($dst$$Register, $src$$Register, 32);
9893 %}
9894 ins_pipe(pipe_class_default);
9895 %}
9896
9897 instruct convF2LRaw_regF(regF dst, regF src) %{
9898 // no match-rule, false predicate
9899 effect(DEF dst, USE src);
9900 predicate(false);
9901
9902 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9903 size(4);
9904 ins_encode %{
9905 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9906 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9907 %}
9908 ins_pipe(pipe_class_default);
9909 %}
9910
9911 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9912 // no match-rule, false predicate
9913 effect(DEF dst, USE crx, USE src);
9914 predicate(false);
9915
9916 ins_variable_size_depending_on_alignment(true);
9917
9918 format %{ "cmovL $crx, $dst, $src" %}
9919 // Worst case is branch + move + stop, no stop without scheduler.
9920 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9921 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9922 ins_pipe(pipe_class_default);
9923 %}
9924
9925 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9926 // no match-rule, false predicate
9927 effect(DEF dst, USE crx, USE mem);
9928 predicate(false);
9929
9930 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9931 postalloc_expand %{
9932 //
9933 // replaces
9934 //
9935 // region dst crx mem
9936 // \ | | /
9937 // dst=cmovL_bso_stackSlotL_conLvalue0
9938 //
9939 // with
9940 //
9941 // region dst
9942 // \ /
9943 // dst=loadConL16(0)
9944 // |
9945 // ^ region dst crx mem
9946 // | \ | | /
9947 // dst=cmovL_bso_stackSlotL
9948 //
9949
9950 // Create new nodes.
9951 MachNode *m1 = new loadConL16Node();
9952 MachNode *m2 = new cmovL_bso_stackSlotLNode();
9953
9954 // inputs for new nodes
9955 m1->add_req(n_region);
9956 m2->add_req(n_region, n_crx, n_mem);
9957 m2->add_prec(m1);
9958
9959 // operands for new nodes
9960 m1->_opnds[0] = op_dst;
9961 m1->_opnds[1] = new immL16Oper(0);
9962 m2->_opnds[0] = op_dst;
9963 m2->_opnds[1] = op_crx;
9964 m2->_opnds[2] = op_mem;
9965
9966 // registers for new nodes
9967 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9968 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9969
9970 // Insert new nodes.
9971 nodes->push(m1);
9972 nodes->push(m2);
9973 %}
9974 %}
9975
9976 // Float to Long conversion, NaN is mapped to 0.
9977 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9978 match(Set dst (ConvF2L src));
9979 ins_cost(DEFAULT_COST);
9980
9981 expand %{
9982 regF tmpF;
9983 stackSlotL tmpS;
9984 flagsReg crx;
9985 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9986 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9987 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9988 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9989 %}
9990 %}
9991
9992 instruct convD2LRaw_regD(regD dst, regD src) %{
9993 // no match-rule, false predicate
9994 effect(DEF dst, USE src);
9995 predicate(false);
9996
9997 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9998 size(4);
9999 ins_encode %{
10000 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10001 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10002 %}
10003 ins_pipe(pipe_class_default);
10004 %}
10005
10006 // Double to Long conversion, NaN is mapped to 0.
10007 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10008 match(Set dst (ConvD2L src));
10009 ins_cost(DEFAULT_COST);
10010
10011 expand %{
10012 regD tmpD;
10013 stackSlotL tmpS;
10014 flagsReg crx;
10015 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10016 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10017 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10018 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10019 %}
10020 %}
10021
10022 // Convert to Float
10023
10024 // Placed here as needed in expand.
10025 instruct convL2DRaw_regD(regD dst, regD src) %{
10026 // no match-rule, false predicate
10027 effect(DEF dst, USE src);
10028 predicate(false);
10029
10030 format %{ "FCFID $dst, $src \t// convL2D" %}
10031 size(4);
10032 ins_encode %{
10033 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10034 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10035 %}
10036 ins_pipe(pipe_class_default);
10037 %}
10038
10039 // Placed here as needed in expand.
10040 instruct convD2F_reg(regF dst, regD src) %{
10041 match(Set dst (ConvD2F src));
10042 format %{ "FRSP $dst, $src \t// convD2F" %}
10043 size(4);
10044 ins_encode %{
10045 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10046 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10047 %}
10048 ins_pipe(pipe_class_default);
10049 %}
10050
10051 // Integer to Float conversion.
10052 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10053 match(Set dst (ConvI2F src));
10054 predicate(!VM_Version::has_fcfids());
10055 ins_cost(DEFAULT_COST);
10056
10057 expand %{
10058 iRegLdst tmpL;
10059 stackSlotL tmpS;
10060 regD tmpD;
10061 regD tmpD2;
10062 convI2L_reg(tmpL, src); // Sign-extension int to long.
10063 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10064 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10065 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10066 convD2F_reg(dst, tmpD2); // Convert double to float.
10067 %}
10068 %}
10069
10070 instruct convL2FRaw_regF(regF dst, regD src) %{
10071 // no match-rule, false predicate
10072 effect(DEF dst, USE src);
10073 predicate(false);
10074
10075 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10076 size(4);
10077 ins_encode %{
10078 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10079 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10080 %}
10081 ins_pipe(pipe_class_default);
10082 %}
10083
10084 // Integer to Float conversion. Special version for Power7.
10085 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10086 match(Set dst (ConvI2F src));
10087 predicate(VM_Version::has_fcfids());
10088 ins_cost(DEFAULT_COST);
10089
10090 expand %{
10091 iRegLdst tmpL;
10092 stackSlotL tmpS;
10093 regD tmpD;
10094 convI2L_reg(tmpL, src); // Sign-extension int to long.
10095 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10096 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10097 convL2FRaw_regF(dst, tmpD); // Convert to float.
10098 %}
10099 %}
10100
10101 // L2F to avoid runtime call.
10102 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10103 match(Set dst (ConvL2F src));
10104 predicate(VM_Version::has_fcfids());
10105 ins_cost(DEFAULT_COST);
10106
10107 expand %{
10108 stackSlotL tmpS;
10109 regD tmpD;
10110 regL_to_stkL(tmpS, src); // Store long to stack.
10111 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10112 convL2FRaw_regF(dst, tmpD); // Convert to float.
10113 %}
10114 %}
10115
10116 // Moved up as used in expand.
10117 //instruct convD2F_reg(regF dst, regD src) %{%}
10118
10119 // Convert to Double
10120
10121 // Integer to Double conversion.
10122 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10123 match(Set dst (ConvI2D src));
10124 ins_cost(DEFAULT_COST);
10125
10126 expand %{
10127 iRegLdst tmpL;
10128 stackSlotL tmpS;
10129 regD tmpD;
10130 convI2L_reg(tmpL, src); // Sign-extension int to long.
10131 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10132 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10133 convL2DRaw_regD(dst, tmpD); // Convert to double.
10134 %}
10135 %}
10136
10137 // Long to Double conversion
10138 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10139 match(Set dst (ConvL2D src));
10140 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10141
10142 expand %{
10143 regD tmpD;
10144 moveL2D_stack_reg(tmpD, src);
10145 convL2DRaw_regD(dst, tmpD);
10146 %}
10147 %}
10148
10149 instruct convF2D_reg(regD dst, regF src) %{
10150 match(Set dst (ConvF2D src));
10151 format %{ "FMR $dst, $src \t// float->double" %}
10152 // variable size, 0 or 4
10153 ins_encode %{
10154 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10155 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10156 %}
10157 ins_pipe(pipe_class_default);
10158 %}
10159
10160 //----------Control Flow Instructions------------------------------------------
10161 // Compare Instructions
10162
10163 // Compare Integers
10164 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10165 match(Set crx (CmpI src1 src2));
10166 size(4);
10167 format %{ "CMPW $crx, $src1, $src2" %}
10168 ins_encode %{
10169 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10170 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10171 %}
10172 ins_pipe(pipe_class_compare);
10173 %}
10174
10175 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10176 match(Set crx (CmpI src1 src2));
10177 format %{ "CMPWI $crx, $src1, $src2" %}
10178 size(4);
10179 ins_encode %{
10180 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10181 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10182 %}
10183 ins_pipe(pipe_class_compare);
10184 %}
10185
10186 // (src1 & src2) == 0?
10187 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10188 match(Set cr0 (CmpI (AndI src1 src2) zero));
10189 // r0 is killed
10190 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10191 size(4);
10192 ins_encode %{
10193 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10194 // FIXME: avoid andi_ ?
10195 __ andi_(R0, $src1$$Register, $src2$$constant);
10196 %}
10197 ins_pipe(pipe_class_compare);
10198 %}
10199
10200 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10201 match(Set crx (CmpL src1 src2));
10202 format %{ "CMPD $crx, $src1, $src2" %}
10203 size(4);
10204 ins_encode %{
10205 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10206 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10207 %}
10208 ins_pipe(pipe_class_compare);
10209 %}
10210
10211 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10212 match(Set crx (CmpL src1 src2));
10213 format %{ "CMPDI $crx, $src1, $src2" %}
10214 size(4);
10215 ins_encode %{
10216 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10217 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10218 %}
10219 ins_pipe(pipe_class_compare);
10220 %}
10221
10222 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10223 match(Set cr0 (CmpL (AndL src1 src2) zero));
10224 // r0 is killed
10225 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10226 size(4);
10227 ins_encode %{
10228 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10229 __ and_(R0, $src1$$Register, $src2$$Register);
10230 %}
10231 ins_pipe(pipe_class_compare);
10232 %}
10233
10234 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10235 match(Set cr0 (CmpL (AndL src1 src2) zero));
10236 // r0 is killed
10237 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10238 size(4);
10239 ins_encode %{
10240 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10241 // FIXME: avoid andi_ ?
10242 __ andi_(R0, $src1$$Register, $src2$$constant);
10243 %}
10244 ins_pipe(pipe_class_compare);
10245 %}
10246
10247 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10248 // no match-rule, false predicate
10249 effect(DEF dst, USE crx);
10250 predicate(false);
10251
10252 ins_variable_size_depending_on_alignment(true);
10253
10254 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10255 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10256 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10257 ins_encode %{
10258 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10259 Label done;
10260 // li(Rdst, 0); // equal -> 0
10261 __ beq($crx$$CondRegister, done);
10262 __ li($dst$$Register, 1); // greater -> +1
10263 __ bgt($crx$$CondRegister, done);
10264 __ li($dst$$Register, -1); // unordered or less -> -1
10265 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10266 __ bind(done);
10267 %}
10268 ins_pipe(pipe_class_compare);
10269 %}
10270
10271 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10272 // no match-rule, false predicate
10273 effect(DEF dst, USE crx);
10274 predicate(false);
10275
10276 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10277 postalloc_expand %{
10278 //
10279 // replaces
10280 //
10281 // region crx
10282 // \ |
10283 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10284 //
10285 // with
10286 //
10287 // region
10288 // \
10289 // dst=loadConI16(0)
10290 // |
10291 // ^ region crx
10292 // | \ |
10293 // dst=cmovI_conIvalueMinus1_conIvalue1
10294 //
10295
10296 // Create new nodes.
10297 MachNode *m1 = new loadConI16Node();
10298 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10299
10300 // inputs for new nodes
10301 m1->add_req(n_region);
10302 m2->add_req(n_region, n_crx);
10303 m2->add_prec(m1);
10304
10305 // operands for new nodes
10306 m1->_opnds[0] = op_dst;
10307 m1->_opnds[1] = new immI16Oper(0);
10308 m2->_opnds[0] = op_dst;
10309 m2->_opnds[1] = op_crx;
10310
10311 // registers for new nodes
10312 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10313 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10314
10315 // Insert new nodes.
10316 nodes->push(m1);
10317 nodes->push(m2);
10318 %}
10319 %}
10320
10321 // Manifest a CmpL3 result in an integer register. Very painful.
10322 // This is the test to avoid.
10323 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10324 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10325 match(Set dst (CmpL3 src1 src2));
10326 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10327
10328 expand %{
10329 flagsReg tmp1;
10330 cmpL_reg_reg(tmp1, src1, src2);
10331 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10332 %}
10333 %}
10334
10335 // Implicit range checks.
10336 // A range check in the ideal world has one of the following shapes:
10337 // - (If le (CmpU length index)), (IfTrue throw exception)
10338 // - (If lt (CmpU index length)), (IfFalse throw exception)
10339 //
10340 // Match range check 'If le (CmpU length index)'.
10341 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10342 match(If cmp (CmpU src_length index));
10343 effect(USE labl);
10344 predicate(TrapBasedRangeChecks &&
10345 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10346 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10347 (Matcher::branches_to_uncommon_trap(_leaf)));
10348
10349 ins_is_TrapBasedCheckNode(true);
10350
10351 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10352 size(4);
10353 ins_encode %{
10354 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10355 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10356 __ trap_range_check_le($src_length$$Register, $index$$constant);
10357 } else {
10358 // Both successors are uncommon traps, probability is 0.
10359 // Node got flipped during fixup flow.
10360 assert($cmp$$cmpcode == 0x9, "must be greater");
10361 __ trap_range_check_g($src_length$$Register, $index$$constant);
10362 }
10363 %}
10364 ins_pipe(pipe_class_trap);
10365 %}
10366
10367 // Match range check 'If lt (CmpU index length)'.
10368 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10369 match(If cmp (CmpU src_index src_length));
10370 effect(USE labl);
10371 predicate(TrapBasedRangeChecks &&
10372 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10373 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10374 (Matcher::branches_to_uncommon_trap(_leaf)));
10375
10376 ins_is_TrapBasedCheckNode(true);
10377
10378 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10379 size(4);
10380 ins_encode %{
10381 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10382 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10383 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10384 } else {
10385 // Both successors are uncommon traps, probability is 0.
10386 // Node got flipped during fixup flow.
10387 assert($cmp$$cmpcode == 0x8, "must be less");
10388 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10389 }
10390 %}
10391 ins_pipe(pipe_class_trap);
10392 %}
10393
10394 // Match range check 'If lt (CmpU index length)'.
10395 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10396 match(If cmp (CmpU src_index length));
10397 effect(USE labl);
10398 predicate(TrapBasedRangeChecks &&
10399 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10400 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10401 (Matcher::branches_to_uncommon_trap(_leaf)));
10402
10403 ins_is_TrapBasedCheckNode(true);
10404
10405 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10406 size(4);
10407 ins_encode %{
10408 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10409 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10410 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10411 } else {
10412 // Both successors are uncommon traps, probability is 0.
10413 // Node got flipped during fixup flow.
10414 assert($cmp$$cmpcode == 0x8, "must be less");
10415 __ trap_range_check_l($src_index$$Register, $length$$constant);
10416 }
10417 %}
10418 ins_pipe(pipe_class_trap);
10419 %}
10420
10421 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10422 match(Set crx (CmpU src1 src2));
10423 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10424 size(4);
10425 ins_encode %{
10426 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10427 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10428 %}
10429 ins_pipe(pipe_class_compare);
10430 %}
10431
10432 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10433 match(Set crx (CmpU src1 src2));
10434 size(4);
10435 format %{ "CMPLWI $crx, $src1, $src2" %}
10436 ins_encode %{
10437 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10438 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10439 %}
10440 ins_pipe(pipe_class_compare);
10441 %}
10442
10443 // Implicit zero checks (more implicit null checks).
10444 // No constant pool entries required.
10445 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10446 match(If cmp (CmpN value zero));
10447 effect(USE labl);
10448 predicate(TrapBasedNullChecks &&
10449 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10450 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10451 Matcher::branches_to_uncommon_trap(_leaf));
10452 ins_cost(1);
10453
10454 ins_is_TrapBasedCheckNode(true);
10455
10456 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10457 size(4);
10458 ins_encode %{
10459 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10460 if ($cmp$$cmpcode == 0xA) {
10461 __ trap_null_check($value$$Register);
10462 } else {
10463 // Both successors are uncommon traps, probability is 0.
10464 // Node got flipped during fixup flow.
10465 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10466 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10467 }
10468 %}
10469 ins_pipe(pipe_class_trap);
10470 %}
10471
10472 // Compare narrow oops.
10473 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10474 match(Set crx (CmpN src1 src2));
10475
10476 size(4);
10477 ins_cost(DEFAULT_COST);
10478 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10479 ins_encode %{
10480 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10481 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10482 %}
10483 ins_pipe(pipe_class_compare);
10484 %}
10485
10486 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10487 match(Set crx (CmpN src1 src2));
10488 // Make this more expensive than zeroCheckN_iReg_imm0.
10489 ins_cost(DEFAULT_COST);
10490
10491 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10492 size(4);
10493 ins_encode %{
10494 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10495 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10496 %}
10497 ins_pipe(pipe_class_compare);
10498 %}
10499
10500 // Implicit zero checks (more implicit null checks).
10501 // No constant pool entries required.
10502 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10503 match(If cmp (CmpP value zero));
10504 effect(USE labl);
10505 predicate(TrapBasedNullChecks &&
10506 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10507 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10508 Matcher::branches_to_uncommon_trap(_leaf));
10509
10510 ins_is_TrapBasedCheckNode(true);
10511
10512 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10513 size(4);
10514 ins_encode %{
10515 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10516 if ($cmp$$cmpcode == 0xA) {
10517 __ trap_null_check($value$$Register);
10518 } else {
10519 // Both successors are uncommon traps, probability is 0.
10520 // Node got flipped during fixup flow.
10521 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10522 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10523 }
10524 %}
10525 ins_pipe(pipe_class_trap);
10526 %}
10527
10528 // Compare Pointers
10529 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10530 match(Set crx (CmpP src1 src2));
10531 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10532 size(4);
10533 ins_encode %{
10534 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10535 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10536 %}
10537 ins_pipe(pipe_class_compare);
10538 %}
10539
10540 // Used in postalloc expand.
10541 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10542 // This match rule prevents reordering of node before a safepoint.
10543 // This only makes sense if this instructions is used exclusively
10544 // for the expansion of EncodeP!
10545 match(Set crx (CmpP src1 src2));
10546 predicate(false);
10547
10548 format %{ "CMPDI $crx, $src1, $src2" %}
10549 size(4);
10550 ins_encode %{
10551 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10552 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10553 %}
10554 ins_pipe(pipe_class_compare);
10555 %}
10556
10557 //----------Float Compares----------------------------------------------------
10558
10559 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10560 // no match-rule, false predicate
10561 effect(DEF crx, USE src1, USE src2);
10562 predicate(false);
10563
10564 format %{ "cmpFUrd $crx, $src1, $src2" %}
10565 size(4);
10566 ins_encode %{
10567 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10568 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10569 %}
10570 ins_pipe(pipe_class_default);
10571 %}
10572
10573 instruct cmov_bns_less(flagsReg crx) %{
10574 // no match-rule, false predicate
10575 effect(DEF crx);
10576 predicate(false);
10577
10578 ins_variable_size_depending_on_alignment(true);
10579
10580 format %{ "cmov $crx" %}
10581 // Worst case is branch + move + stop, no stop without scheduler.
10582 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10583 ins_encode %{
10584 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10585 Label done;
10586 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10587 __ li(R0, 0);
10588 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10589 // TODO PPC port __ endgroup_if_needed(_size == 16);
10590 __ bind(done);
10591 %}
10592 ins_pipe(pipe_class_default);
10593 %}
10594
10595 // Compare floating, generate condition code.
10596 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10597 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10598 //
10599 // The following code sequence occurs a lot in mpegaudio:
10600 //
10601 // block BXX:
10602 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10603 // cmpFUrd CCR6, F11, F9
10604 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10605 // cmov CCR6
10606 // 8: instruct branchConSched:
10607 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10608 match(Set crx (CmpF src1 src2));
10609 ins_cost(DEFAULT_COST+BRANCH_COST);
10610
10611 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10612 postalloc_expand %{
10613 //
10614 // replaces
10615 //
10616 // region src1 src2
10617 // \ | |
10618 // crx=cmpF_reg_reg
10619 //
10620 // with
10621 //
10622 // region src1 src2
10623 // \ | |
10624 // crx=cmpFUnordered_reg_reg
10625 // |
10626 // ^ region
10627 // | \
10628 // crx=cmov_bns_less
10629 //
10630
10631 // Create new nodes.
10632 MachNode *m1 = new cmpFUnordered_reg_regNode();
10633 MachNode *m2 = new cmov_bns_lessNode();
10634
10635 // inputs for new nodes
10636 m1->add_req(n_region, n_src1, n_src2);
10637 m2->add_req(n_region);
10638 m2->add_prec(m1);
10639
10640 // operands for new nodes
10641 m1->_opnds[0] = op_crx;
10642 m1->_opnds[1] = op_src1;
10643 m1->_opnds[2] = op_src2;
10644 m2->_opnds[0] = op_crx;
10645
10646 // registers for new nodes
10647 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10648 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10649
10650 // Insert new nodes.
10651 nodes->push(m1);
10652 nodes->push(m2);
10653 %}
10654 %}
10655
10656 // Compare float, generate -1,0,1
10657 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10658 match(Set dst (CmpF3 src1 src2));
10659 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10660
10661 expand %{
10662 flagsReg tmp1;
10663 cmpFUnordered_reg_reg(tmp1, src1, src2);
10664 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10665 %}
10666 %}
10667
10668 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10669 // no match-rule, false predicate
10670 effect(DEF crx, USE src1, USE src2);
10671 predicate(false);
10672
10673 format %{ "cmpFUrd $crx, $src1, $src2" %}
10674 size(4);
10675 ins_encode %{
10676 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10677 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10678 %}
10679 ins_pipe(pipe_class_default);
10680 %}
10681
10682 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10683 match(Set crx (CmpD src1 src2));
10684 ins_cost(DEFAULT_COST+BRANCH_COST);
10685
10686 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10687 postalloc_expand %{
10688 //
10689 // replaces
10690 //
10691 // region src1 src2
10692 // \ | |
10693 // crx=cmpD_reg_reg
10694 //
10695 // with
10696 //
10697 // region src1 src2
10698 // \ | |
10699 // crx=cmpDUnordered_reg_reg
10700 // |
10701 // ^ region
10702 // | \
10703 // crx=cmov_bns_less
10704 //
10705
10706 // create new nodes
10707 MachNode *m1 = new cmpDUnordered_reg_regNode();
10708 MachNode *m2 = new cmov_bns_lessNode();
10709
10710 // inputs for new nodes
10711 m1->add_req(n_region, n_src1, n_src2);
10712 m2->add_req(n_region);
10713 m2->add_prec(m1);
10714
10715 // operands for new nodes
10716 m1->_opnds[0] = op_crx;
10717 m1->_opnds[1] = op_src1;
10718 m1->_opnds[2] = op_src2;
10719 m2->_opnds[0] = op_crx;
10720
10721 // registers for new nodes
10722 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10723 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10724
10725 // Insert new nodes.
10726 nodes->push(m1);
10727 nodes->push(m2);
10728 %}
10729 %}
10730
10731 // Compare double, generate -1,0,1
10732 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10733 match(Set dst (CmpD3 src1 src2));
10734 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10735
10736 expand %{
10737 flagsReg tmp1;
10738 cmpDUnordered_reg_reg(tmp1, src1, src2);
10739 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10740 %}
10741 %}
10742
10743 //----------Branches---------------------------------------------------------
10744 // Jump
10745
10746 // Direct Branch.
10747 instruct branch(label labl) %{
10748 match(Goto);
10749 effect(USE labl);
10750 ins_cost(BRANCH_COST);
10751
10752 format %{ "B $labl" %}
10753 size(4);
10754 ins_encode %{
10755 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10756 Label d; // dummy
10757 __ bind(d);
10758 Label* p = $labl$$label;
10759 // `p' is `NULL' when this encoding class is used only to
10760 // determine the size of the encoded instruction.
10761 Label& l = (NULL == p)? d : *(p);
10762 __ b(l);
10763 %}
10764 ins_pipe(pipe_class_default);
10765 %}
10766
10767 // Conditional Near Branch
10768 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10769 // Same match rule as `branchConFar'.
10770 match(If cmp crx);
10771 effect(USE lbl);
10772 ins_cost(BRANCH_COST);
10773
10774 // If set to 1 this indicates that the current instruction is a
10775 // short variant of a long branch. This avoids using this
10776 // instruction in first-pass matching. It will then only be used in
10777 // the `Shorten_branches' pass.
10778 ins_short_branch(1);
10779
10780 format %{ "B$cmp $crx, $lbl" %}
10781 size(4);
10782 ins_encode( enc_bc(crx, cmp, lbl) );
10783 ins_pipe(pipe_class_default);
10784 %}
10785
10786 // This is for cases when the ppc64 `bc' instruction does not
10787 // reach far enough. So we emit a far branch here, which is more
10788 // expensive.
10789 //
10790 // Conditional Far Branch
10791 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10792 // Same match rule as `branchCon'.
10793 match(If cmp crx);
10794 effect(USE crx, USE lbl);
10795 predicate(!false /* TODO: PPC port HB_Schedule*/);
10796 // Higher cost than `branchCon'.
10797 ins_cost(5*BRANCH_COST);
10798
10799 // This is not a short variant of a branch, but the long variant.
10800 ins_short_branch(0);
10801
10802 format %{ "B_FAR$cmp $crx, $lbl" %}
10803 size(8);
10804 ins_encode( enc_bc_far(crx, cmp, lbl) );
10805 ins_pipe(pipe_class_default);
10806 %}
10807
10808 // Conditional Branch used with Power6 scheduler (can be far or short).
10809 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10810 // Same match rule as `branchCon'.
10811 match(If cmp crx);
10812 effect(USE crx, USE lbl);
10813 predicate(false /* TODO: PPC port HB_Schedule*/);
10814 // Higher cost than `branchCon'.
10815 ins_cost(5*BRANCH_COST);
10816
10817 // Actually size doesn't depend on alignment but on shortening.
10818 ins_variable_size_depending_on_alignment(true);
10819 // long variant.
10820 ins_short_branch(0);
10821
10822 format %{ "B_FAR$cmp $crx, $lbl" %}
10823 size(8); // worst case
10824 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10825 ins_pipe(pipe_class_default);
10826 %}
10827
10828 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10829 match(CountedLoopEnd cmp crx);
10830 effect(USE labl);
10831 ins_cost(BRANCH_COST);
10832
10833 // short variant.
10834 ins_short_branch(1);
10835
10836 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10837 size(4);
10838 ins_encode( enc_bc(crx, cmp, labl) );
10839 ins_pipe(pipe_class_default);
10840 %}
10841
10842 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10843 match(CountedLoopEnd cmp crx);
10844 effect(USE labl);
10845 predicate(!false /* TODO: PPC port HB_Schedule */);
10846 ins_cost(BRANCH_COST);
10847
10848 // Long variant.
10849 ins_short_branch(0);
10850
10851 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10852 size(8);
10853 ins_encode( enc_bc_far(crx, cmp, labl) );
10854 ins_pipe(pipe_class_default);
10855 %}
10856
10857 // Conditional Branch used with Power6 scheduler (can be far or short).
10858 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10859 match(CountedLoopEnd cmp crx);
10860 effect(USE labl);
10861 predicate(false /* TODO: PPC port HB_Schedule */);
10862 // Higher cost than `branchCon'.
10863 ins_cost(5*BRANCH_COST);
10864
10865 // Actually size doesn't depend on alignment but on shortening.
10866 ins_variable_size_depending_on_alignment(true);
10867 // Long variant.
10868 ins_short_branch(0);
10869
10870 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10871 size(8); // worst case
10872 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10873 ins_pipe(pipe_class_default);
10874 %}
10875
10876 // ============================================================================
10877 // Java runtime operations, intrinsics and other complex operations.
10878
10879 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10880 // array for an instance of the superklass. Set a hidden internal cache on a
10881 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10882 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10883 //
10884 // GL TODO: Improve this.
10885 // - result should not be a TEMP
10886 // - Add match rule as on sparc avoiding additional Cmp.
10887 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10888 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10889 match(Set result (PartialSubtypeCheck subklass superklass));
10890 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10891 ins_cost(DEFAULT_COST*10);
10892
10893 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10894 ins_encode %{
10895 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10896 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10897 $tmp_klass$$Register, NULL, $result$$Register);
10898 %}
10899 ins_pipe(pipe_class_default);
10900 %}
10901
10902 // inlined locking and unlocking
10903
10904 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10905 match(Set crx (FastLock oop box));
10906 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10907 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10908
10909 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10910 ins_encode %{
10911 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10912 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10913 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10914 // If locking was successfull, crx should indicate 'EQ'.
10915 // The compiler generates a branch to the runtime call to
10916 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10917 %}
10918 ins_pipe(pipe_class_compare);
10919 %}
10920
10921 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10922 match(Set crx (FastUnlock oop box));
10923 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10924
10925 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10926 ins_encode %{
10927 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10928 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10929 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10930 // If unlocking was successfull, crx should indicate 'EQ'.
10931 // The compiler generates a branch to the runtime call to
10932 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10933 %}
10934 ins_pipe(pipe_class_compare);
10935 %}
10936
10937 // Align address.
10938 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10939 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10940
10941 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10942 size(4);
10943 ins_encode %{
10944 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10945 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10946 %}
10947 ins_pipe(pipe_class_default);
10948 %}
10949
10950 // Array size computation.
10951 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10952 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10953
10954 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10955 size(4);
10956 ins_encode %{
10957 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10958 __ subf($dst$$Register, $start$$Register, $end$$Register);
10959 %}
10960 ins_pipe(pipe_class_default);
10961 %}
10962
10963 // Clear-array with dynamic array-size.
10964 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10965 match(Set dummy (ClearArray cnt base));
10966 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10967 ins_cost(MEMORY_REF_COST);
10968
10969 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10970
10971 format %{ "ClearArray $cnt, $base" %}
10972 ins_encode %{
10973 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10974 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10975 %}
10976 ins_pipe(pipe_class_default);
10977 %}
10978
10979 // String_IndexOf for needle of length 1.
10980 //
10981 // Match needle into immediate operands: no loadConP node needed. Saves one
10982 // register and two instructions over string_indexOf_imm1Node.
10983 //
10984 // Assumes register result differs from all input registers.
10985 //
10986 // Preserves registers haystack, haycnt
10987 // Kills registers tmp1, tmp2
10988 // Defines registers result
10989 //
10990 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10991 //
10992 // Unfortunately this does not match too often. In many situations the AddP is used
10993 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10994 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10995 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10996 iRegIdst tmp1, iRegIdst tmp2,
10997 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10998 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10999 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11000
11001 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11002
11003 ins_cost(150);
11004 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11005 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11006
11007 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11008 ins_encode %{
11009 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11010 immPOper *needleOper = (immPOper *)$needleImm;
11011 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11012 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11013
11014 __ string_indexof_1($result$$Register,
11015 $haystack$$Register, $haycnt$$Register,
11016 R0, needle_values->char_at(0),
11017 $tmp1$$Register, $tmp2$$Register);
11018 %}
11019 ins_pipe(pipe_class_compare);
11020 %}
11021
11022 // String_IndexOf for needle of length 1.
11023 //
11024 // Special case requires less registers and emits less instructions.
11025 //
11026 // Assumes register result differs from all input registers.
11027 //
11028 // Preserves registers haystack, haycnt
11029 // Kills registers tmp1, tmp2, needle
11030 // Defines registers result
11031 //
11032 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11033 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11034 rscratch2RegP needle, immI_1 needlecntImm,
11035 iRegIdst tmp1, iRegIdst tmp2,
11036 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11037 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11038 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
11039 TEMP tmp1, TEMP tmp2);
11040 // Required for EA: check if it is still a type_array.
11041 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11042 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11043 ins_cost(180);
11044
11045 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11046
11047 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11048 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11049 ins_encode %{
11050 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11051 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11052 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11053 guarantee(needle_values, "sanity");
11054 if (needle_values != NULL) {
11055 __ string_indexof_1($result$$Register,
11056 $haystack$$Register, $haycnt$$Register,
11057 R0, needle_values->char_at(0),
11058 $tmp1$$Register, $tmp2$$Register);
11059 } else {
11060 __ string_indexof_1($result$$Register,
11061 $haystack$$Register, $haycnt$$Register,
11062 $needle$$Register, 0,
11063 $tmp1$$Register, $tmp2$$Register);
11064 }
11065 %}
11066 ins_pipe(pipe_class_compare);
11067 %}
11068
11069 // String_IndexOf.
11070 //
11071 // Length of needle as immediate. This saves instruction loading constant needle
11072 // length.
11073 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11074 // completely or do it in vector instruction. This should save registers for
11075 // needlecnt and needle.
11076 //
11077 // Assumes register result differs from all input registers.
11078 // Overwrites haycnt, needlecnt.
11079 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11080 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11081 iRegPsrc needle, uimmI15 needlecntImm,
11082 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11083 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11084 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11085 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11086 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11087 // Required for EA: check if it is still a type_array.
11088 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11089 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11090 ins_cost(250);
11091
11092 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11093
11094 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11095 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11096 ins_encode %{
11097 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11098 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11099 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11100
11101 __ string_indexof($result$$Register,
11102 $haystack$$Register, $haycnt$$Register,
11103 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11104 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11105 %}
11106 ins_pipe(pipe_class_compare);
11107 %}
11108
11109 // StrIndexOf node.
11110 //
11111 // Assumes register result differs from all input registers.
11112 // Overwrites haycnt, needlecnt.
11113 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11114 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11115 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11116 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11117 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11118 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11119 TEMP result,
11120 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11121 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11122 ins_cost(300);
11123
11124 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11125
11126 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11127 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11128 ins_encode %{
11129 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11130 __ string_indexof($result$$Register,
11131 $haystack$$Register, $haycnt$$Register,
11132 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11133 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11134 %}
11135 ins_pipe(pipe_class_compare);
11136 %}
11137
11138 // String equals with immediate.
11139 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11140 iRegPdst tmp1, iRegPdst tmp2,
11141 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11142 match(Set result (StrEquals (Binary str1 str2) cntImm));
11143 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11144 KILL cr0, KILL cr6, KILL ctr);
11145 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11146 ins_cost(250);
11147
11148 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11149
11150 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11151 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11152 ins_encode %{
11153 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11154 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11155 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11156 %}
11157 ins_pipe(pipe_class_compare);
11158 %}
11159
11160 // String equals.
11161 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11162 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11163 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11164 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11165 match(Set result (StrEquals (Binary str1 str2) cnt));
11166 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11167 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11168 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11169 ins_cost(300);
11170
11171 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11172
11173 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11174 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11175 ins_encode %{
11176 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11177 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11178 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11179 %}
11180 ins_pipe(pipe_class_compare);
11181 %}
11182
11183 // String compare.
11184 // Char[] pointers are passed in.
11185 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11186 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11187 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11188 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11189 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11190 ins_cost(300);
11191
11192 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11193
11194 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11195 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11196 ins_encode %{
11197 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11198 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11199 $result$$Register, $tmp$$Register);
11200 %}
11201 ins_pipe(pipe_class_compare);
11202 %}
11203
11204 //---------- Min/Max Instructions ---------------------------------------------
11205
11206 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11207 match(Set dst (MinI src1 src2));
11208 ins_cost(DEFAULT_COST*6);
11209
11210 expand %{
11211 iRegLdst src1s;
11212 iRegLdst src2s;
11213 iRegLdst diff;
11214 iRegLdst sm;
11215 iRegLdst doz; // difference or zero
11216 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11217 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11218 subL_reg_reg(diff, src2s, src1s);
11219 // Need to consider >=33 bit result, therefore we need signmaskL.
11220 signmask64L_regL(sm, diff);
11221 andL_reg_reg(doz, diff, sm); // <=0
11222 addI_regL_regL(dst, doz, src1s);
11223 %}
11224 %}
11225
11226 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11227 match(Set dst (MaxI src1 src2));
11228 ins_cost(DEFAULT_COST*6);
11229
11230 expand %{
11231 iRegLdst src1s;
11232 iRegLdst src2s;
11233 iRegLdst diff;
11234 iRegLdst sm;
11235 iRegLdst doz; // difference or zero
11236 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11237 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11238 subL_reg_reg(diff, src2s, src1s);
11239 // Need to consider >=33 bit result, therefore we need signmaskL.
11240 signmask64L_regL(sm, diff);
11241 andcL_reg_reg(doz, diff, sm); // >=0
11242 addI_regL_regL(dst, doz, src1s);
11243 %}
11244 %}
11245
11246 //---------- Population Count Instructions ------------------------------------
11247
11248 // Popcnt for Power7.
11249 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11250 match(Set dst (PopCountI src));
11251 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11252 ins_cost(DEFAULT_COST);
11253
11254 format %{ "POPCNTW $dst, $src" %}
11255 size(4);
11256 ins_encode %{
11257 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11258 __ popcntw($dst$$Register, $src$$Register);
11259 %}
11260 ins_pipe(pipe_class_default);
11261 %}
11262
11263 // Popcnt for Power7.
11264 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11265 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11266 match(Set dst (PopCountL src));
11267 ins_cost(DEFAULT_COST);
11268
11269 format %{ "POPCNTD $dst, $src" %}
11270 size(4);
11271 ins_encode %{
11272 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11273 __ popcntd($dst$$Register, $src$$Register);
11274 %}
11275 ins_pipe(pipe_class_default);
11276 %}
11277
11278 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11279 match(Set dst (CountLeadingZerosI src));
11280 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11281 ins_cost(DEFAULT_COST);
11282
11283 format %{ "CNTLZW $dst, $src" %}
11284 size(4);
11285 ins_encode %{
11286 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11287 __ cntlzw($dst$$Register, $src$$Register);
11288 %}
11289 ins_pipe(pipe_class_default);
11290 %}
11291
11292 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11293 match(Set dst (CountLeadingZerosL src));
11294 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11295 ins_cost(DEFAULT_COST);
11296
11297 format %{ "CNTLZD $dst, $src" %}
11298 size(4);
11299 ins_encode %{
11300 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11301 __ cntlzd($dst$$Register, $src$$Register);
11302 %}
11303 ins_pipe(pipe_class_default);
11304 %}
11305
11306 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11307 // no match-rule, false predicate
11308 effect(DEF dst, USE src);
11309 predicate(false);
11310
11311 format %{ "CNTLZD $dst, $src" %}
11312 size(4);
11313 ins_encode %{
11314 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11315 __ cntlzd($dst$$Register, $src$$Register);
11316 %}
11317 ins_pipe(pipe_class_default);
11318 %}
11319
11320 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11321 match(Set dst (CountTrailingZerosI src));
11322 predicate(UseCountLeadingZerosInstructionsPPC64);
11323 ins_cost(DEFAULT_COST);
11324
11325 expand %{
11326 immI16 imm1 %{ (int)-1 %}
11327 immI16 imm2 %{ (int)32 %}
11328 immI_minus1 m1 %{ -1 %}
11329 iRegIdst tmpI1;
11330 iRegIdst tmpI2;
11331 iRegIdst tmpI3;
11332 addI_reg_imm16(tmpI1, src, imm1);
11333 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11334 countLeadingZerosI(tmpI3, tmpI2);
11335 subI_imm16_reg(dst, imm2, tmpI3);
11336 %}
11337 %}
11338
11339 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11340 match(Set dst (CountTrailingZerosL src));
11341 predicate(UseCountLeadingZerosInstructionsPPC64);
11342 ins_cost(DEFAULT_COST);
11343
11344 expand %{
11345 immL16 imm1 %{ (long)-1 %}
11346 immI16 imm2 %{ (int)64 %}
11347 iRegLdst tmpL1;
11348 iRegLdst tmpL2;
11349 iRegIdst tmpL3;
11350 addL_reg_imm16(tmpL1, src, imm1);
11351 andcL_reg_reg(tmpL2, tmpL1, src);
11352 countLeadingZerosL(tmpL3, tmpL2);
11353 subI_imm16_reg(dst, imm2, tmpL3);
11354 %}
11355 %}
11356
11357 // Expand nodes for byte_reverse_int.
11358 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11359 effect(DEF dst, USE src, USE pos, USE shift);
11360 predicate(false);
11361
11362 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11363 size(4);
11364 ins_encode %{
11365 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11366 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11367 %}
11368 ins_pipe(pipe_class_default);
11369 %}
11370
11371 // As insrwi_a, but with USE_DEF.
11372 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11373 effect(USE_DEF dst, USE src, USE pos, USE shift);
11374 predicate(false);
11375
11376 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11377 size(4);
11378 ins_encode %{
11379 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11380 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11381 %}
11382 ins_pipe(pipe_class_default);
11383 %}
11384
11385 // Just slightly faster than java implementation.
11386 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11387 match(Set dst (ReverseBytesI src));
11388 predicate(UseCountLeadingZerosInstructionsPPC64);
11389 ins_cost(DEFAULT_COST);
11390
11391 expand %{
11392 immI16 imm24 %{ (int) 24 %}
11393 immI16 imm16 %{ (int) 16 %}
11394 immI16 imm8 %{ (int) 8 %}
11395 immI16 imm4 %{ (int) 4 %}
11396 immI16 imm0 %{ (int) 0 %}
11397 iRegLdst tmpI1;
11398 iRegLdst tmpI2;
11399 iRegLdst tmpI3;
11400
11401 urShiftI_reg_imm(tmpI1, src, imm24);
11402 insrwi_a(dst, tmpI1, imm24, imm8);
11403 urShiftI_reg_imm(tmpI2, src, imm16);
11404 insrwi(dst, tmpI2, imm8, imm16);
11405 urShiftI_reg_imm(tmpI3, src, imm8);
11406 insrwi(dst, tmpI3, imm8, imm8);
11407 insrwi(dst, src, imm0, imm8);
11408 %}
11409 %}
11410
11411 //---------- Replicate Vector Instructions ------------------------------------
11412
11413 // Insrdi does replicate if src == dst.
11414 instruct repl32(iRegLdst dst) %{
11415 predicate(false);
11416 effect(USE_DEF dst);
11417
11418 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11419 size(4);
11420 ins_encode %{
11421 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11422 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11423 %}
11424 ins_pipe(pipe_class_default);
11425 %}
11426
11427 // Insrdi does replicate if src == dst.
11428 instruct repl48(iRegLdst dst) %{
11429 predicate(false);
11430 effect(USE_DEF dst);
11431
11432 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11433 size(4);
11434 ins_encode %{
11435 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11436 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11437 %}
11438 ins_pipe(pipe_class_default);
11439 %}
11440
11441 // Insrdi does replicate if src == dst.
11442 instruct repl56(iRegLdst dst) %{
11443 predicate(false);
11444 effect(USE_DEF dst);
11445
11446 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11447 size(4);
11448 ins_encode %{
11449 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11450 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11451 %}
11452 ins_pipe(pipe_class_default);
11453 %}
11454
11455 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11456 match(Set dst (ReplicateB src));
11457 predicate(n->as_Vector()->length() == 8);
11458 expand %{
11459 moveReg(dst, src);
11460 repl56(dst);
11461 repl48(dst);
11462 repl32(dst);
11463 %}
11464 %}
11465
11466 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11467 match(Set dst (ReplicateB zero));
11468 predicate(n->as_Vector()->length() == 8);
11469 format %{ "LI $dst, #0 \t// replicate8B" %}
11470 size(4);
11471 ins_encode %{
11472 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11473 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11474 %}
11475 ins_pipe(pipe_class_default);
11476 %}
11477
11478 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11479 match(Set dst (ReplicateB src));
11480 predicate(n->as_Vector()->length() == 8);
11481 format %{ "LI $dst, #-1 \t// replicate8B" %}
11482 size(4);
11483 ins_encode %{
11484 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11485 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11486 %}
11487 ins_pipe(pipe_class_default);
11488 %}
11489
11490 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11491 match(Set dst (ReplicateS src));
11492 predicate(n->as_Vector()->length() == 4);
11493 expand %{
11494 moveReg(dst, src);
11495 repl48(dst);
11496 repl32(dst);
11497 %}
11498 %}
11499
11500 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11501 match(Set dst (ReplicateS zero));
11502 predicate(n->as_Vector()->length() == 4);
11503 format %{ "LI $dst, #0 \t// replicate4C" %}
11504 size(4);
11505 ins_encode %{
11506 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11507 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11508 %}
11509 ins_pipe(pipe_class_default);
11510 %}
11511
11512 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11513 match(Set dst (ReplicateS src));
11514 predicate(n->as_Vector()->length() == 4);
11515 format %{ "LI $dst, -1 \t// replicate4C" %}
11516 size(4);
11517 ins_encode %{
11518 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11519 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11520 %}
11521 ins_pipe(pipe_class_default);
11522 %}
11523
11524 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11525 match(Set dst (ReplicateI src));
11526 predicate(n->as_Vector()->length() == 2);
11527 ins_cost(2 * DEFAULT_COST);
11528 expand %{
11529 moveReg(dst, src);
11530 repl32(dst);
11531 %}
11532 %}
11533
11534 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11535 match(Set dst (ReplicateI zero));
11536 predicate(n->as_Vector()->length() == 2);
11537 format %{ "LI $dst, #0 \t// replicate4C" %}
11538 size(4);
11539 ins_encode %{
11540 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11541 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11542 %}
11543 ins_pipe(pipe_class_default);
11544 %}
11545
11546 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11547 match(Set dst (ReplicateI src));
11548 predicate(n->as_Vector()->length() == 2);
11549 format %{ "LI $dst, -1 \t// replicate4C" %}
11550 size(4);
11551 ins_encode %{
11552 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11553 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11554 %}
11555 ins_pipe(pipe_class_default);
11556 %}
11557
11558 // Move float to int register via stack, replicate.
11559 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11560 match(Set dst (ReplicateF src));
11561 predicate(n->as_Vector()->length() == 2);
11562 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11563 expand %{
11564 stackSlotL tmpS;
11565 iRegIdst tmpI;
11566 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11567 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11568 moveReg(dst, tmpI); // Move int to long reg.
11569 repl32(dst); // Replicate bitpattern.
11570 %}
11571 %}
11572
11573 // Replicate scalar constant to packed float values in Double register
11574 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11575 match(Set dst (ReplicateF src));
11576 predicate(n->as_Vector()->length() == 2);
11577 ins_cost(5 * DEFAULT_COST);
11578
11579 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11580 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11581 %}
11582
11583 // Replicate scalar zero constant to packed float values in Double register
11584 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11585 match(Set dst (ReplicateF zero));
11586 predicate(n->as_Vector()->length() == 2);
11587
11588 format %{ "LI $dst, #0 \t// replicate2F" %}
11589 ins_encode %{
11590 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11591 __ li($dst$$Register, 0x0);
11592 %}
11593 ins_pipe(pipe_class_default);
11594 %}
11595
11596 // ============================================================================
11597 // Safepoint Instruction
11598
11599 instruct safePoint_poll(iRegPdst poll) %{
11600 match(SafePoint poll);
11601 predicate(LoadPollAddressFromThread);
11602
11603 // It caused problems to add the effect that r0 is killed, but this
11604 // effect no longer needs to be mentioned, since r0 is not contained
11605 // in a reg_class.
11606
11607 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11608 size(4);
11609 ins_encode( enc_poll(0x0, poll) );
11610 ins_pipe(pipe_class_default);
11611 %}
11612
11613 // Safepoint without per-thread support. Load address of page to poll
11614 // as constant.
11615 // Rscratch2RegP is R12.
11616 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11617 // a seperate node so that the oop map is at the right location.
11618 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11619 match(SafePoint poll);
11620 predicate(!LoadPollAddressFromThread);
11621
11622 // It caused problems to add the effect that r0 is killed, but this
11623 // effect no longer needs to be mentioned, since r0 is not contained
11624 // in a reg_class.
11625
11626 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11627 ins_encode( enc_poll(0x0, poll) );
11628 ins_pipe(pipe_class_default);
11629 %}
11630
11631 // ============================================================================
11632 // Call Instructions
11633
11634 // Call Java Static Instruction
11635
11636 // Schedulable version of call static node.
11637 instruct CallStaticJavaDirect(method meth) %{
11638 match(CallStaticJava);
11639 effect(USE meth);
11640 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11641 ins_cost(CALL_COST);
11642
11643 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11644
11645 format %{ "CALL,static $meth \t// ==> " %}
11646 size(4);
11647 ins_encode( enc_java_static_call(meth) );
11648 ins_pipe(pipe_class_call);
11649 %}
11650
11651 // Schedulable version of call static node.
11652 instruct CallStaticJavaDirectHandle(method meth) %{
11653 match(CallStaticJava);
11654 effect(USE meth);
11655 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11656 ins_cost(CALL_COST);
11657
11658 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11659
11660 format %{ "CALL,static $meth \t// ==> " %}
11661 ins_encode( enc_java_handle_call(meth) );
11662 ins_pipe(pipe_class_call);
11663 %}
11664
11665 // Call Java Dynamic Instruction
11666
11667 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11668 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11669 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11670 // The call destination must still be placed in the constant pool.
11671 instruct CallDynamicJavaDirectSched(method meth) %{
11672 match(CallDynamicJava); // To get all the data fields we need ...
11673 effect(USE meth);
11674 predicate(false); // ... but never match.
11675
11676 ins_field_load_ic_hi_node(loadConL_hiNode*);
11677 ins_field_load_ic_node(loadConLNode*);
11678 ins_num_consts(1 /* 1 patchable constant: call destination */);
11679
11680 format %{ "BL \t// dynamic $meth ==> " %}
11681 size(4);
11682 ins_encode( enc_java_dynamic_call_sched(meth) );
11683 ins_pipe(pipe_class_call);
11684 %}
11685
11686 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11687 // We use postalloc expanded calls if we use inline caches
11688 // and do not update method data.
11689 //
11690 // This instruction has two constants: inline cache (IC) and call destination.
11691 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11692 // one constant.
11693 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11694 match(CallDynamicJava);
11695 effect(USE meth);
11696 predicate(UseInlineCaches);
11697 ins_cost(CALL_COST);
11698
11699 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11700
11701 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11702 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11703 %}
11704
11705 // Compound version of call dynamic java
11706 // We use postalloc expanded calls if we use inline caches
11707 // and do not update method data.
11708 instruct CallDynamicJavaDirect(method meth) %{
11709 match(CallDynamicJava);
11710 effect(USE meth);
11711 predicate(!UseInlineCaches);
11712 ins_cost(CALL_COST);
11713
11714 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11715 ins_num_consts(4);
11716
11717 format %{ "CALL,dynamic $meth \t// ==> " %}
11718 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11719 ins_pipe(pipe_class_call);
11720 %}
11721
11722 // Call Runtime Instruction
11723
11724 instruct CallRuntimeDirect(method meth) %{
11725 match(CallRuntime);
11726 effect(USE meth);
11727 ins_cost(CALL_COST);
11728
11729 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11730 // env for callee, C-toc.
11731 ins_num_consts(3);
11732
11733 format %{ "CALL,runtime" %}
11734 ins_encode( enc_java_to_runtime_call(meth) );
11735 ins_pipe(pipe_class_call);
11736 %}
11737
11738 // Call Leaf
11739
11740 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11741 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11742 effect(DEF dst, USE src);
11743
11744 ins_num_consts(1);
11745
11746 format %{ "MTCTR $src" %}
11747 size(4);
11748 ins_encode( enc_leaf_call_mtctr(src) );
11749 ins_pipe(pipe_class_default);
11750 %}
11751
11752 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11753 instruct CallLeafDirect(method meth) %{
11754 match(CallLeaf); // To get the data all the data fields we need ...
11755 effect(USE meth);
11756 predicate(false); // but never match.
11757
11758 format %{ "BCTRL \t// leaf call $meth ==> " %}
11759 size(4);
11760 ins_encode %{
11761 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11762 __ bctrl();
11763 %}
11764 ins_pipe(pipe_class_call);
11765 %}
11766
11767 // postalloc expand of CallLeafDirect.
11768 // Load adress to call from TOC, then bl to it.
11769 instruct CallLeafDirect_Ex(method meth) %{
11770 match(CallLeaf);
11771 effect(USE meth);
11772 ins_cost(CALL_COST);
11773
11774 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11775 // env for callee, C-toc.
11776 ins_num_consts(3);
11777
11778 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11779 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11780 %}
11781
11782 // Call runtime without safepoint - same as CallLeaf.
11783 // postalloc expand of CallLeafNoFPDirect.
11784 // Load adress to call from TOC, then bl to it.
11785 instruct CallLeafNoFPDirect_Ex(method meth) %{
11786 match(CallLeafNoFP);
11787 effect(USE meth);
11788 ins_cost(CALL_COST);
11789
11790 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11791 // env for callee, C-toc.
11792 ins_num_consts(3);
11793
11794 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11795 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11796 %}
11797
11798 // Tail Call; Jump from runtime stub to Java code.
11799 // Also known as an 'interprocedural jump'.
11800 // Target of jump will eventually return to caller.
11801 // TailJump below removes the return address.
11802 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11803 match(TailCall jump_target method_oop);
11804 ins_cost(CALL_COST);
11805
11806 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11807 "BCTR \t// tail call" %}
11808 size(8);
11809 ins_encode %{
11810 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11811 __ mtctr($jump_target$$Register);
11812 __ bctr();
11813 %}
11814 ins_pipe(pipe_class_call);
11815 %}
11816
11817 // Return Instruction
11818 instruct Ret() %{
11819 match(Return);
11820 format %{ "BLR \t// branch to link register" %}
11821 size(4);
11822 ins_encode %{
11823 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11824 // LR is restored in MachEpilogNode. Just do the RET here.
11825 __ blr();
11826 %}
11827 ins_pipe(pipe_class_default);
11828 %}
11829
11830 // Tail Jump; remove the return address; jump to target.
11831 // TailCall above leaves the return address around.
11832 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11833 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11834 // "restore" before this instruction (in Epilogue), we need to materialize it
11835 // in %i0.
11836 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11837 match(TailJump jump_target ex_oop);
11838 ins_cost(CALL_COST);
11839
11840 format %{ "LD R4_ARG2 = LR\n\t"
11841 "MTCTR $jump_target\n\t"
11842 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11843 size(12);
11844 ins_encode %{
11845 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11846 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11847 __ mtctr($jump_target$$Register);
11848 __ bctr();
11849 %}
11850 ins_pipe(pipe_class_call);
11851 %}
11852
11853 // Create exception oop: created by stack-crawling runtime code.
11854 // Created exception is now available to this handler, and is setup
11855 // just prior to jumping to this handler. No code emitted.
11856 instruct CreateException(rarg1RegP ex_oop) %{
11857 match(Set ex_oop (CreateEx));
11858 ins_cost(0);
11859
11860 format %{ " -- \t// exception oop; no code emitted" %}
11861 size(0);
11862 ins_encode( /*empty*/ );
11863 ins_pipe(pipe_class_default);
11864 %}
11865
11866 // Rethrow exception: The exception oop will come in the first
11867 // argument position. Then JUMP (not call) to the rethrow stub code.
11868 instruct RethrowException() %{
11869 match(Rethrow);
11870 ins_cost(CALL_COST);
11871
11872 format %{ "Jmp rethrow_stub" %}
11873 ins_encode %{
11874 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11875 cbuf.set_insts_mark();
11876 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11877 %}
11878 ins_pipe(pipe_class_call);
11879 %}
11880
11881 // Die now.
11882 instruct ShouldNotReachHere() %{
11883 match(Halt);
11884 ins_cost(CALL_COST);
11885
11886 format %{ "ShouldNotReachHere" %}
11887 size(4);
11888 ins_encode %{
11889 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11890 __ trap_should_not_reach_here();
11891 %}
11892 ins_pipe(pipe_class_default);
11893 %}
11894
11895 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11896 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11897 // Get a DEF on threadRegP, no costs, no encoding, use
11898 // 'ins_should_rematerialize(true)' to avoid spilling.
11899 instruct tlsLoadP(threadRegP dst) %{
11900 match(Set dst (ThreadLocal));
11901 ins_cost(0);
11902
11903 ins_should_rematerialize(true);
11904
11905 format %{ " -- \t// $dst=Thread::current(), empty" %}
11906 size(0);
11907 ins_encode( /*empty*/ );
11908 ins_pipe(pipe_class_empty);
11909 %}
11910
11911 //---Some PPC specific nodes---------------------------------------------------
11912
11913 // Stop a group.
11914 instruct endGroup() %{
11915 ins_cost(0);
11916
11917 ins_is_nop(true);
11918
11919 format %{ "End Bundle (ori r1, r1, 0)" %}
11920 size(4);
11921 ins_encode %{
11922 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11923 __ endgroup();
11924 %}
11925 ins_pipe(pipe_class_default);
11926 %}
11927
11928 // Nop instructions
11929
11930 instruct fxNop() %{
11931 ins_cost(0);
11932
11933 ins_is_nop(true);
11934
11935 format %{ "fxNop" %}
11936 size(4);
11937 ins_encode %{
11938 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11939 __ nop();
11940 %}
11941 ins_pipe(pipe_class_default);
11942 %}
11943
11944 instruct fpNop0() %{
11945 ins_cost(0);
11946
11947 ins_is_nop(true);
11948
11949 format %{ "fpNop0" %}
11950 size(4);
11951 ins_encode %{
11952 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11953 __ fpnop0();
11954 %}
11955 ins_pipe(pipe_class_default);
11956 %}
11957
11958 instruct fpNop1() %{
11959 ins_cost(0);
11960
11961 ins_is_nop(true);
11962
11963 format %{ "fpNop1" %}
11964 size(4);
11965 ins_encode %{
11966 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11967 __ fpnop1();
11968 %}
11969 ins_pipe(pipe_class_default);
11970 %}
11971
11972 instruct brNop0() %{
11973 ins_cost(0);
11974 size(4);
11975 format %{ "brNop0" %}
11976 ins_encode %{
11977 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11978 __ brnop0();
11979 %}
11980 ins_is_nop(true);
11981 ins_pipe(pipe_class_default);
11982 %}
11983
11984 instruct brNop1() %{
11985 ins_cost(0);
11986
11987 ins_is_nop(true);
11988
11989 format %{ "brNop1" %}
11990 size(4);
11991 ins_encode %{
11992 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11993 __ brnop1();
11994 %}
11995 ins_pipe(pipe_class_default);
11996 %}
11997
11998 instruct brNop2() %{
11999 ins_cost(0);
12000
12001 ins_is_nop(true);
12002
12003 format %{ "brNop2" %}
12004 size(4);
12005 ins_encode %{
12006 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12007 __ brnop2();
12008 %}
12009 ins_pipe(pipe_class_default);
12010 %}
12011
12012 //----------PEEPHOLE RULES-----------------------------------------------------
12013 // These must follow all instruction definitions as they use the names
12014 // defined in the instructions definitions.
12015 //
12016 // peepmatch ( root_instr_name [preceeding_instruction]* );
12017 //
12018 // peepconstraint %{
12019 // (instruction_number.operand_name relational_op instruction_number.operand_name
12020 // [, ...] );
12021 // // instruction numbers are zero-based using left to right order in peepmatch
12022 //
12023 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12024 // // provide an instruction_number.operand_name for each operand that appears
12025 // // in the replacement instruction's match rule
12026 //
12027 // ---------VM FLAGS---------------------------------------------------------
12028 //
12029 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12030 //
12031 // Each peephole rule is given an identifying number starting with zero and
12032 // increasing by one in the order seen by the parser. An individual peephole
12033 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12034 // on the command-line.
12035 //
12036 // ---------CURRENT LIMITATIONS----------------------------------------------
12037 //
12038 // Only match adjacent instructions in same basic block
12039 // Only equality constraints
12040 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12041 // Only one replacement instruction
12042 //
12043 // ---------EXAMPLE----------------------------------------------------------
12044 //
12045 // // pertinent parts of existing instructions in architecture description
12046 // instruct movI(eRegI dst, eRegI src) %{
12047 // match(Set dst (CopyI src));
12048 // %}
12049 //
12050 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12051 // match(Set dst (AddI dst src));
12052 // effect(KILL cr);
12053 // %}
12054 //
12055 // // Change (inc mov) to lea
12056 // peephole %{
12057 // // increment preceeded by register-register move
12058 // peepmatch ( incI_eReg movI );
12059 // // require that the destination register of the increment
12060 // // match the destination register of the move
12061 // peepconstraint ( 0.dst == 1.dst );
12062 // // construct a replacement instruction that sets
12063 // // the destination to ( move's source register + one )
12064 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12065 // %}
12066 //
12067 // Implementation no longer uses movX instructions since
12068 // machine-independent system no longer uses CopyX nodes.
12069 //
12070 // peephole %{
12071 // peepmatch ( incI_eReg movI );
12072 // peepconstraint ( 0.dst == 1.dst );
12073 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12074 // %}
12075 //
12076 // peephole %{
12077 // peepmatch ( decI_eReg movI );
12078 // peepconstraint ( 0.dst == 1.dst );
12079 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12080 // %}
12081 //
12082 // peephole %{
12083 // peepmatch ( addI_eReg_imm movI );
12084 // peepconstraint ( 0.dst == 1.dst );
12085 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12086 // %}
12087 //
12088 // peephole %{
12089 // peepmatch ( addP_eReg_imm movP );
12090 // peepconstraint ( 0.dst == 1.dst );
12091 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12092 // %}
12093
12094 // // Change load of spilled value to only a spill
12095 // instruct storeI(memory mem, eRegI src) %{
12096 // match(Set mem (StoreI mem src));
12097 // %}
12098 //
12099 // instruct loadI(eRegI dst, memory mem) %{
12100 // match(Set dst (LoadI mem));
12101 // %}
12102 //
12103 peephole %{
12104 peepmatch ( loadI storeI );
12105 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12106 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12107 %}
12108
12109 peephole %{
12110 peepmatch ( loadL storeL );
12111 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12112 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12113 %}
12114
12115 peephole %{
12116 peepmatch ( loadP storeP );
12117 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12118 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12119 %}
12120
12121 //----------SMARTSPILL RULES---------------------------------------------------
12122 // These must follow all instruction definitions as they use the names
12123 // defined in the instructions definitions.