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src/cpu/ppc/vm/vm_version_ppc.cpp

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rev 7507 : 8066964: ppc64: argument and return type profiling, fix problem with popframe


 117   // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
 118   _supports_cx8 = true;
 119 
 120   UseSSE = 0; // Only on x86 and x64
 121 
 122   intx cache_line_size = _measured_cache_line_size;
 123 
 124   if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
 125 
 126   if (AllocatePrefetchStyle == 4) {
 127     AllocatePrefetchStepSize = cache_line_size; // Need exact value.
 128     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
 129     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
 130   } else {
 131     if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
 132     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
 133     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
 134   }
 135 
 136   assert(AllocatePrefetchLines > 0, "invalid value");
 137   if (AllocatePrefetchLines < 1) // Set valid value in product VM.
 138     AllocatePrefetchLines = 1; // Conservative value.

 139 
 140   if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size)
 141     AllocatePrefetchStyle = 1; // Fall back if inappropriate.

 142 
 143   assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");





























 144 }
 145 
 146 void VM_Version::print_features() {
 147   tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
 148 }
 149 
 150 #ifdef COMPILER2
 151 // Determine section size on power6: If section size is 8 instructions,
 152 // there should be a difference between the two testloops of ~15 %. If
 153 // no difference is detected the section is assumed to be 32 instructions.
 154 void VM_Version::determine_section_size() {
 155 
 156   int unroll = 80;
 157 
 158   const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
 159 
 160   // Allocate space for the code.
 161   ResourceMark rm;
 162   CodeBuffer cb("detect_section_size", code_size, 0);
 163   MacroAssembler* a = new MacroAssembler(&cb);




 117   // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
 118   _supports_cx8 = true;
 119 
 120   UseSSE = 0; // Only on x86 and x64
 121 
 122   intx cache_line_size = _measured_cache_line_size;
 123 
 124   if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
 125 
 126   if (AllocatePrefetchStyle == 4) {
 127     AllocatePrefetchStepSize = cache_line_size; // Need exact value.
 128     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
 129     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
 130   } else {
 131     if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
 132     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
 133     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
 134   }
 135 
 136   assert(AllocatePrefetchLines > 0, "invalid value");
 137   if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
 138     AllocatePrefetchLines = 1; // Conservative value.
 139   }
 140 
 141   if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
 142     AllocatePrefetchStyle = 1; // Fall back if inappropriate.
 143   }
 144 
 145   assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
 146 
 147   if (UseCRC32Intrinsics) {
 148     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 149       warning("CRC32 intrinsics  are not available on this CPU");
 150     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 151   }
 152 
 153   // The AES intrinsic stubs require AES instruction support.
 154   if (UseAES) {
 155     warning("AES instructions are not available on this CPU");
 156     FLAG_SET_DEFAULT(UseAES, false);
 157   }
 158   if (UseAESIntrinsics) {
 159     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 160       warning("AES intrinsics are not available on this CPU");
 161     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 162   }
 163 
 164   if (UseSHA) {
 165     warning("SHA instructions are not available on this CPU");
 166     FLAG_SET_DEFAULT(UseSHA, false);
 167   }
 168   if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
 169     warning("SHA intrinsics are not available on this CPU");
 170     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 171     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 172     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 173   }
 174 
 175 }
 176 
 177 void VM_Version::print_features() {
 178   tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
 179 }
 180 
 181 #ifdef COMPILER2
 182 // Determine section size on power6: If section size is 8 instructions,
 183 // there should be a difference between the two testloops of ~15 %. If
 184 // no difference is detected the section is assumed to be 32 instructions.
 185 void VM_Version::determine_section_size() {
 186 
 187   int unroll = 80;
 188 
 189   const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
 190 
 191   // Allocate space for the code.
 192   ResourceMark rm;
 193   CodeBuffer cb("detect_section_size", code_size, 0);
 194   MacroAssembler* a = new MacroAssembler(&cb);


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