1 // 2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved. 3 // Copyright 2012, 2015 SAP AG. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 // 25 26 // 27 // PPC64 Architecture Description File 28 // 29 30 //----------REGISTER DEFINITION BLOCK------------------------------------------ 31 // This information is used by the matcher and the register allocator to 32 // describe individual registers and classes of registers within the target 33 // architecture. 34 register %{ 35 //----------Architecture Description Register Definitions---------------------- 36 // General Registers 37 // "reg_def" name (register save type, C convention save type, 38 // ideal register type, encoding); 39 // 40 // Register Save Types: 41 // 42 // NS = No-Save: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, & 44 // that they do not need to be saved at call sites. 45 // 46 // SOC = Save-On-Call: The register allocator assumes that these registers 47 // can be used without saving upon entry to the method, 48 // but that they must be saved at call sites. 49 // These are called "volatiles" on ppc. 50 // 51 // SOE = Save-On-Entry: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, but they do not need to be saved at call 54 // sites. 55 // These are called "nonvolatiles" on ppc. 56 // 57 // AS = Always-Save: The register allocator assumes that these registers 58 // must be saved before using them upon entry to the 59 // method, & that they must be saved at call sites. 60 // 61 // Ideal Register Type is used to determine how to save & restore a 62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 64 // 65 // The encoding number is the actual bit-pattern placed into the opcodes. 66 // 67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI 68 // Supplement Version 1.7 as of 2003-10-29. 69 // 70 // For each 64-bit register we must define two registers: the register 71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', 72 // e.g. R3_H, which is needed by the allocator, but is not used 73 // for stores, loads, etc. 74 75 // ---------------------------- 76 // Integer/Long Registers 77 // ---------------------------- 78 79 // PPC64 has 32 64-bit integer registers. 80 81 // types: v = volatile, nv = non-volatile, s = system 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); 146 147 148 // ---------------------------- 149 // Float/Double Registers 150 // ---------------------------- 151 152 // Double Registers 153 // The rules of ADL require that double registers be defined in pairs. 154 // Each pair must be two 32-bit values, but not necessarily a pair of 155 // single float registers. In each pair, ADLC-assigned register numbers 156 // must be adjacent, with the lower number even. Finally, when the 157 // CPU stores such a register pair to memory, the word associated with 158 // the lower ADLC-assigned number must be stored to the lower address. 159 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single 161 // or double precision floating-point value. 162 163 // types: v = volatile, nv = non-volatile, s = system 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); 228 229 // ---------------------------- 230 // Special Registers 231 // ---------------------------- 232 233 // Condition Codes Flag Registers 234 235 // PPC64 has 8 condition code "registers" which are all contained 236 // in the CR register. 237 238 // types: v = volatile, nv = non-volatile, s = system 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v 247 248 // Special registers of PPC64 249 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v 256 257 258 // ---------------------------- 259 // Specify priority of register selection within phases of register 260 // allocation. Highest priority is first. A useful heuristic is to 261 // give registers a low priority when they are required by machine 262 // instructions, like EAX and EDX on I486, and choose no-save registers 263 // before save-on-call, & save-on-call before save-on-entry. Registers 264 // which participate in fixed calling sequences should come last. 265 // Registers which are used as pairs must fall on an even boundary. 266 267 // It's worth about 1% on SPEC geomean to get this right. 268 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g. 271 // R3_num. Therefore, R3_num may not be (and in reality is not) 272 // the same as R3->encoding()! Furthermore, we cannot make any 273 // assumptions on ordering, e.g. R3_num may be less than R2_num. 274 // Additionally, the function 275 // static enum RC rc_class(OptoReg::Name reg ) 276 // maps a given <register>_num value to its chunk type (except for flags) 277 // and its current implementation relies on chunk0 and chunk1 having a 278 // size of 64 each. 279 280 // If you change this allocation class, please have a look at the 281 // default values for the parameters RoundRobinIntegerRegIntervalStart 282 // and RoundRobinFloatRegIntervalStart 283 284 alloc_class chunk0 ( 285 // Chunk0 contains *all* 64 integer registers halves. 286 287 // "non-volatile" registers 288 R14, R14_H, 289 R15, R15_H, 290 R17, R17_H, 291 R18, R18_H, 292 R19, R19_H, 293 R20, R20_H, 294 R21, R21_H, 295 R22, R22_H, 296 R23, R23_H, 297 R24, R24_H, 298 R25, R25_H, 299 R26, R26_H, 300 R27, R27_H, 301 R28, R28_H, 302 R29, R29_H, 303 R30, R30_H, 304 R31, R31_H, 305 306 // scratch/special registers 307 R11, R11_H, 308 R12, R12_H, 309 310 // argument registers 311 R10, R10_H, 312 R9, R9_H, 313 R8, R8_H, 314 R7, R7_H, 315 R6, R6_H, 316 R5, R5_H, 317 R4, R4_H, 318 R3, R3_H, 319 320 // special registers, not available for allocation 321 R16, R16_H, // R16_thread 322 R13, R13_H, // system thread id 323 R2, R2_H, // may be used for TOC 324 R1, R1_H, // SP 325 R0, R0_H // R0 (scratch) 326 ); 327 328 // If you change this allocation class, please have a look at the 329 // default values for the parameters RoundRobinIntegerRegIntervalStart 330 // and RoundRobinFloatRegIntervalStart 331 332 alloc_class chunk1 ( 333 // Chunk1 contains *all* 64 floating-point registers halves. 334 335 // scratch register 336 F0, F0_H, 337 338 // argument registers 339 F13, F13_H, 340 F12, F12_H, 341 F11, F11_H, 342 F10, F10_H, 343 F9, F9_H, 344 F8, F8_H, 345 F7, F7_H, 346 F6, F6_H, 347 F5, F5_H, 348 F4, F4_H, 349 F3, F3_H, 350 F2, F2_H, 351 F1, F1_H, 352 353 // non-volatile registers 354 F14, F14_H, 355 F15, F15_H, 356 F16, F16_H, 357 F17, F17_H, 358 F18, F18_H, 359 F19, F19_H, 360 F20, F20_H, 361 F21, F21_H, 362 F22, F22_H, 363 F23, F23_H, 364 F24, F24_H, 365 F25, F25_H, 366 F26, F26_H, 367 F27, F27_H, 368 F28, F28_H, 369 F29, F29_H, 370 F30, F30_H, 371 F31, F31_H 372 ); 373 374 alloc_class chunk2 ( 375 // Chunk2 contains *all* 8 condition code registers. 376 377 CCR0, 378 CCR1, 379 CCR2, 380 CCR3, 381 CCR4, 382 CCR5, 383 CCR6, 384 CCR7 385 ); 386 387 alloc_class chunk3 ( 388 // special registers 389 // These registers are not allocated, but used for nodes generated by postalloc expand. 390 SR_XER, 391 SR_LR, 392 SR_CTR, 393 SR_VRSAVE, 394 SR_SPEFSCR, 395 SR_PPR 396 ); 397 398 //-------Architecture Description Register Classes----------------------- 399 400 // Several register classes are automatically defined based upon 401 // information in this architecture description. 402 403 // 1) reg_class inline_cache_reg ( as defined in frame section ) 404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 407 // 408 409 // ---------------------------- 410 // 32 Bit Register Classes 411 // ---------------------------- 412 413 // We specify registers twice, once as read/write, and once read-only. 414 // We use the read-only registers for source operands. With this, we 415 // can include preset read only registers in this class, as a hard-coded 416 // '0'-register. (We used to simulate this on ppc.) 417 418 // 32 bit registers that can be read and written i.e. these registers 419 // can be dest (or src) of normal instructions. 420 reg_class bits32_reg_rw( 421 /*R0*/ // R0 422 /*R1*/ // SP 423 R2, // TOC 424 R3, 425 R4, 426 R5, 427 R6, 428 R7, 429 R8, 430 R9, 431 R10, 432 R11, 433 R12, 434 /*R13*/ // system thread id 435 R14, 436 R15, 437 /*R16*/ // R16_thread 438 R17, 439 R18, 440 R19, 441 R20, 442 R21, 443 R22, 444 R23, 445 R24, 446 R25, 447 R26, 448 R27, 449 R28, 450 /*R29*/ // global TOC 451 /*R30*/ // Narrow Oop Base 452 R31 453 ); 454 455 // 32 bit registers that can only be read i.e. these registers can 456 // only be src of all instructions. 457 reg_class bits32_reg_ro( 458 /*R0*/ // R0 459 /*R1*/ // SP 460 R2 // TOC 461 R3, 462 R4, 463 R5, 464 R6, 465 R7, 466 R8, 467 R9, 468 R10, 469 R11, 470 R12, 471 /*R13*/ // system thread id 472 R14, 473 R15, 474 /*R16*/ // R16_thread 475 R17, 476 R18, 477 R19, 478 R20, 479 R21, 480 R22, 481 R23, 482 R24, 483 R25, 484 R26, 485 R27, 486 R28, 487 /*R29*/ 488 /*R30*/ // Narrow Oop Base 489 R31 490 ); 491 492 // Complement-required-in-pipeline operands for narrow oops. 493 reg_class bits32_reg_ro_not_complement ( 494 /*R0*/ // R0 495 R1, // SP 496 R2, // TOC 497 R3, 498 R4, 499 R5, 500 R6, 501 R7, 502 R8, 503 R9, 504 R10, 505 R11, 506 R12, 507 /*R13,*/ // system thread id 508 R14, 509 R15, 510 R16, // R16_thread 511 R17, 512 R18, 513 R19, 514 R20, 515 R21, 516 R22, 517 /*R23, 518 R24, 519 R25, 520 R26, 521 R27, 522 R28,*/ 523 /*R29,*/ // TODO: let allocator handle TOC!! 524 /*R30,*/ 525 R31 526 ); 527 528 // Complement-required-in-pipeline operands for narrow oops. 529 // See 64-bit declaration. 530 reg_class bits32_reg_ro_complement ( 531 R23, 532 R24, 533 R25, 534 R26, 535 R27, 536 R28 537 ); 538 539 reg_class rscratch1_bits32_reg(R11); 540 reg_class rscratch2_bits32_reg(R12); 541 reg_class rarg1_bits32_reg(R3); 542 reg_class rarg2_bits32_reg(R4); 543 reg_class rarg3_bits32_reg(R5); 544 reg_class rarg4_bits32_reg(R6); 545 546 // ---------------------------- 547 // 64 Bit Register Classes 548 // ---------------------------- 549 // 64-bit build means 64-bit pointers means hi/lo pairs 550 551 reg_class rscratch1_bits64_reg(R11_H, R11); 552 reg_class rscratch2_bits64_reg(R12_H, R12); 553 reg_class rarg1_bits64_reg(R3_H, R3); 554 reg_class rarg2_bits64_reg(R4_H, R4); 555 reg_class rarg3_bits64_reg(R5_H, R5); 556 reg_class rarg4_bits64_reg(R6_H, R6); 557 // Thread register, 'written' by tlsLoadP, see there. 558 reg_class thread_bits64_reg(R16_H, R16); 559 560 reg_class r19_bits64_reg(R19_H, R19); 561 562 // 64 bit registers that can be read and written i.e. these registers 563 // can be dest (or src) of normal instructions. 564 reg_class bits64_reg_rw( 565 /*R0_H, R0*/ // R0 566 /*R1_H, R1*/ // SP 567 R2_H, R2, // TOC 568 R3_H, R3, 569 R4_H, R4, 570 R5_H, R5, 571 R6_H, R6, 572 R7_H, R7, 573 R8_H, R8, 574 R9_H, R9, 575 R10_H, R10, 576 R11_H, R11, 577 R12_H, R12, 578 /*R13_H, R13*/ // system thread id 579 R14_H, R14, 580 R15_H, R15, 581 /*R16_H, R16*/ // R16_thread 582 R17_H, R17, 583 R18_H, R18, 584 R19_H, R19, 585 R20_H, R20, 586 R21_H, R21, 587 R22_H, R22, 588 R23_H, R23, 589 R24_H, R24, 590 R25_H, R25, 591 R26_H, R26, 592 R27_H, R27, 593 R28_H, R28, 594 /*R29_H, R29*/ 595 /*R30_H, R30*/ 596 R31_H, R31 597 ); 598 599 // 64 bit registers used excluding r2, r11 and r12 600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses 601 // r2, r11 and r12 internally. 602 reg_class bits64_reg_leaf_call( 603 /*R0_H, R0*/ // R0 604 /*R1_H, R1*/ // SP 605 /*R2_H, R2*/ // TOC 606 R3_H, R3, 607 R4_H, R4, 608 R5_H, R5, 609 R6_H, R6, 610 R7_H, R7, 611 R8_H, R8, 612 R9_H, R9, 613 R10_H, R10, 614 /*R11_H, R11*/ 615 /*R12_H, R12*/ 616 /*R13_H, R13*/ // system thread id 617 R14_H, R14, 618 R15_H, R15, 619 /*R16_H, R16*/ // R16_thread 620 R17_H, R17, 621 R18_H, R18, 622 R19_H, R19, 623 R20_H, R20, 624 R21_H, R21, 625 R22_H, R22, 626 R23_H, R23, 627 R24_H, R24, 628 R25_H, R25, 629 R26_H, R26, 630 R27_H, R27, 631 R28_H, R28, 632 /*R29_H, R29*/ 633 /*R30_H, R30*/ 634 R31_H, R31 635 ); 636 637 // Used to hold the TOC to avoid collisions with expanded DynamicCall 638 // which uses r19 as inline cache internally and expanded LeafCall which uses 639 // r2, r11 and r12 internally. 640 reg_class bits64_constant_table_base( 641 /*R0_H, R0*/ // R0 642 /*R1_H, R1*/ // SP 643 /*R2_H, R2*/ // TOC 644 R3_H, R3, 645 R4_H, R4, 646 R5_H, R5, 647 R6_H, R6, 648 R7_H, R7, 649 R8_H, R8, 650 R9_H, R9, 651 R10_H, R10, 652 /*R11_H, R11*/ 653 /*R12_H, R12*/ 654 /*R13_H, R13*/ // system thread id 655 R14_H, R14, 656 R15_H, R15, 657 /*R16_H, R16*/ // R16_thread 658 R17_H, R17, 659 R18_H, R18, 660 /*R19_H, R19*/ 661 R20_H, R20, 662 R21_H, R21, 663 R22_H, R22, 664 R23_H, R23, 665 R24_H, R24, 666 R25_H, R25, 667 R26_H, R26, 668 R27_H, R27, 669 R28_H, R28, 670 /*R29_H, R29*/ 671 /*R30_H, R30*/ 672 R31_H, R31 673 ); 674 675 // 64 bit registers that can only be read i.e. these registers can 676 // only be src of all instructions. 677 reg_class bits64_reg_ro( 678 /*R0_H, R0*/ // R0 679 R1_H, R1, 680 R2_H, R2, // TOC 681 R3_H, R3, 682 R4_H, R4, 683 R5_H, R5, 684 R6_H, R6, 685 R7_H, R7, 686 R8_H, R8, 687 R9_H, R9, 688 R10_H, R10, 689 R11_H, R11, 690 R12_H, R12, 691 /*R13_H, R13*/ // system thread id 692 R14_H, R14, 693 R15_H, R15, 694 R16_H, R16, // R16_thread 695 R17_H, R17, 696 R18_H, R18, 697 R19_H, R19, 698 R20_H, R20, 699 R21_H, R21, 700 R22_H, R22, 701 R23_H, R23, 702 R24_H, R24, 703 R25_H, R25, 704 R26_H, R26, 705 R27_H, R27, 706 R28_H, R28, 707 /*R29_H, R29*/ // TODO: let allocator handle TOC!! 708 /*R30_H, R30,*/ 709 R31_H, R31 710 ); 711 712 // Complement-required-in-pipeline operands. 713 reg_class bits64_reg_ro_not_complement ( 714 /*R0_H, R0*/ // R0 715 R1_H, R1, // SP 716 R2_H, R2, // TOC 717 R3_H, R3, 718 R4_H, R4, 719 R5_H, R5, 720 R6_H, R6, 721 R7_H, R7, 722 R8_H, R8, 723 R9_H, R9, 724 R10_H, R10, 725 R11_H, R11, 726 R12_H, R12, 727 /*R13_H, R13*/ // system thread id 728 R14_H, R14, 729 R15_H, R15, 730 R16_H, R16, // R16_thread 731 R17_H, R17, 732 R18_H, R18, 733 R19_H, R19, 734 R20_H, R20, 735 R21_H, R21, 736 R22_H, R22, 737 /*R23_H, R23, 738 R24_H, R24, 739 R25_H, R25, 740 R26_H, R26, 741 R27_H, R27, 742 R28_H, R28,*/ 743 /*R29_H, R29*/ // TODO: let allocator handle TOC!! 744 /*R30_H, R30,*/ 745 R31_H, R31 746 ); 747 748 // Complement-required-in-pipeline operands. 749 // This register mask is used for the trap instructions that implement 750 // the null checks on AIX. The trap instruction first computes the 751 // complement of the value it shall trap on. Because of this, the 752 // instruction can not be scheduled in the same cycle as an other 753 // instruction reading the normal value of the same register. So we 754 // force the value to check into 'bits64_reg_ro_not_complement' 755 // and then copy it to 'bits64_reg_ro_complement' for the trap. 756 reg_class bits64_reg_ro_complement ( 757 R23_H, R23, 758 R24_H, R24, 759 R25_H, R25, 760 R26_H, R26, 761 R27_H, R27, 762 R28_H, R28 763 ); 764 765 766 // ---------------------------- 767 // Special Class for Condition Code Flags Register 768 769 reg_class int_flags( 770 /*CCR0*/ // scratch 771 /*CCR1*/ // scratch 772 /*CCR2*/ // nv! 773 /*CCR3*/ // nv! 774 /*CCR4*/ // nv! 775 CCR5, 776 CCR6, 777 CCR7 778 ); 779 780 reg_class int_flags_CR0(CCR0); 781 reg_class int_flags_CR1(CCR1); 782 reg_class int_flags_CR6(CCR6); 783 reg_class ctr_reg(SR_CTR); 784 785 // ---------------------------- 786 // Float Register Classes 787 // ---------------------------- 788 789 reg_class flt_reg( 790 /*F0*/ // scratch 791 F1, 792 F2, 793 F3, 794 F4, 795 F5, 796 F6, 797 F7, 798 F8, 799 F9, 800 F10, 801 F11, 802 F12, 803 F13, 804 F14, // nv! 805 F15, // nv! 806 F16, // nv! 807 F17, // nv! 808 F18, // nv! 809 F19, // nv! 810 F20, // nv! 811 F21, // nv! 812 F22, // nv! 813 F23, // nv! 814 F24, // nv! 815 F25, // nv! 816 F26, // nv! 817 F27, // nv! 818 F28, // nv! 819 F29, // nv! 820 F30, // nv! 821 F31 // nv! 822 ); 823 824 // Double precision float registers have virtual `high halves' that 825 // are needed by the allocator. 826 reg_class dbl_reg( 827 /*F0, F0_H*/ // scratch 828 F1, F1_H, 829 F2, F2_H, 830 F3, F3_H, 831 F4, F4_H, 832 F5, F5_H, 833 F6, F6_H, 834 F7, F7_H, 835 F8, F8_H, 836 F9, F9_H, 837 F10, F10_H, 838 F11, F11_H, 839 F12, F12_H, 840 F13, F13_H, 841 F14, F14_H, // nv! 842 F15, F15_H, // nv! 843 F16, F16_H, // nv! 844 F17, F17_H, // nv! 845 F18, F18_H, // nv! 846 F19, F19_H, // nv! 847 F20, F20_H, // nv! 848 F21, F21_H, // nv! 849 F22, F22_H, // nv! 850 F23, F23_H, // nv! 851 F24, F24_H, // nv! 852 F25, F25_H, // nv! 853 F26, F26_H, // nv! 854 F27, F27_H, // nv! 855 F28, F28_H, // nv! 856 F29, F29_H, // nv! 857 F30, F30_H, // nv! 858 F31, F31_H // nv! 859 ); 860 861 %} 862 863 //----------DEFINITION BLOCK--------------------------------------------------- 864 // Define name --> value mappings to inform the ADLC of an integer valued name 865 // Current support includes integer values in the range [0, 0x7FFFFFFF] 866 // Format: 867 // int_def <name> ( <int_value>, <expression>); 868 // Generated Code in ad_<arch>.hpp 869 // #define <name> (<expression>) 870 // // value == <int_value> 871 // Generated code in ad_<arch>.cpp adlc_verification() 872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 873 // 874 definitions %{ 875 // The default cost (of an ALU instruction). 876 int_def DEFAULT_COST_LOW ( 30, 30); 877 int_def DEFAULT_COST ( 100, 100); 878 int_def HUGE_COST (1000000, 1000000); 879 880 // Memory refs 881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); 882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); 883 884 // Branches are even more expensive. 885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); 886 int_def CALL_COST ( 1300, DEFAULT_COST * 13); 887 %} 888 889 890 //----------SOURCE BLOCK------------------------------------------------------- 891 // This is a block of C++ code which provides values, functions, and 892 // definitions necessary in the rest of the architecture description. 893 source_hpp %{ 894 // Header information of the source block. 895 // Method declarations/definitions which are used outside 896 // the ad-scope can conveniently be defined here. 897 // 898 // To keep related declarations/definitions/uses close together, 899 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 900 901 // Returns true if Node n is followed by a MemBar node that 902 // will do an acquire. If so, this node must not do the acquire 903 // operation. 904 bool followed_by_acquire(const Node *n); 905 %} 906 907 source %{ 908 909 // Optimize load-acquire. 910 // 911 // Check if acquire is unnecessary due to following operation that does 912 // acquire anyways. 913 // Walk the pattern: 914 // 915 // n: Load.acq 916 // | 917 // MemBarAcquire 918 // | | 919 // Proj(ctrl) Proj(mem) 920 // | | 921 // MemBarRelease/Volatile 922 // 923 bool followed_by_acquire(const Node *load) { 924 assert(load->is_Load(), "So far implemented only for loads."); 925 926 // Find MemBarAcquire. 927 const Node *mba = NULL; 928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 929 const Node *out = load->fast_out(i); 930 if (out->Opcode() == Op_MemBarAcquire) { 931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. 932 mba = out; 933 break; 934 } 935 } 936 if (!mba) return false; 937 938 // Find following MemBar node. 939 // 940 // The following node must be reachable by control AND memory 941 // edge to assure no other operations are in between the two nodes. 942 // 943 // So first get the Proj node, mem_proj, to use it to iterate forward. 944 Node *mem_proj = NULL; 945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { 946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found 947 assert(mem_proj->is_Proj(), "only projections here"); 948 ProjNode *proj = mem_proj->as_Proj(); 949 if (proj->_con == TypeFunc::Memory && 950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only 951 break; 952 } 953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); 954 955 // Search MemBar behind Proj. If there are other memory operations 956 // behind the Proj we lost. 957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { 958 Node *x = mem_proj->fast_out(j); 959 // Proj might have an edge to a store or load node which precedes the membar. 960 if (x->is_Mem()) return false; 961 962 // On PPC64 release and volatile are implemented by an instruction 963 // that also has acquire semantics. I.e. there is no need for an 964 // acquire before these. 965 int xop = x->Opcode(); 966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { 967 // Make sure we're not missing Call/Phi/MergeMem by checking 968 // control edges. The control edge must directly lead back 969 // to the MemBarAcquire 970 Node *ctrl_proj = x->in(0); 971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { 972 return true; 973 } 974 } 975 } 976 977 return false; 978 } 979 980 #define __ _masm. 981 982 // Tertiary op of a LoadP or StoreP encoding. 983 #define REGP_OP true 984 985 // **************************************************************************** 986 987 // REQUIRED FUNCTIONALITY 988 989 // !!!!! Special hack to get all type of calls to specify the byte offset 990 // from the start of the call to the point where the return address 991 // will point. 992 993 // PPC port: Removed use of lazy constant construct. 994 995 int MachCallStaticJavaNode::ret_addr_offset() { 996 // It's only a single branch-and-link instruction. 997 return 4; 998 } 999 1000 int MachCallDynamicJavaNode::ret_addr_offset() { 1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use 1002 // postalloc expanded calls if we use inline caches and do not update method data. 1003 if (UseInlineCaches) 1004 return 4; 1005 1006 int vtable_index = this->_vtable_index; 1007 if (vtable_index < 0) { 1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 1010 return 12; 1011 } else { 1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 1013 return 24; 1014 } 1015 } 1016 1017 int MachCallRuntimeNode::ret_addr_offset() { 1018 #if defined(ABI_ELFv2) 1019 return 28; 1020 #else 1021 return 40; 1022 #endif 1023 } 1024 1025 //============================================================================= 1026 1027 // condition code conversions 1028 1029 static int cc_to_boint(int cc) { 1030 return Assembler::bcondCRbiIs0 | (cc & 8); 1031 } 1032 1033 static int cc_to_inverse_boint(int cc) { 1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); 1035 } 1036 1037 static int cc_to_biint(int cc, int flags_reg) { 1038 return (flags_reg << 2) | (cc & 3); 1039 } 1040 1041 //============================================================================= 1042 1043 // Compute padding required for nodes which need alignment. The padding 1044 // is the number of bytes (not instructions) which will be inserted before 1045 // the instruction. The padding must match the size of a NOP instruction. 1046 1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { 1048 return (3*4-current_offset)&31; 1049 } 1050 1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const { 1052 return (2*4-current_offset)&31; 1053 } 1054 1055 int string_indexOf_immNode::compute_padding(int current_offset) const { 1056 return (3*4-current_offset)&31; 1057 } 1058 1059 int string_indexOfNode::compute_padding(int current_offset) const { 1060 return (1*4-current_offset)&31; 1061 } 1062 1063 int string_compareNode::compute_padding(int current_offset) const { 1064 return (4*4-current_offset)&31; 1065 } 1066 1067 int string_equals_immNode::compute_padding(int current_offset) const { 1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). 1069 return (2*4-current_offset)&31; 1070 } 1071 1072 int string_equalsNode::compute_padding(int current_offset) const { 1073 return (7*4-current_offset)&31; 1074 } 1075 1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const { 1077 return (2*4-current_offset)&31; 1078 } 1079 1080 //============================================================================= 1081 1082 // Indicate if the safepoint node needs the polling page as an input. 1083 bool SafePointNode::needs_polling_address_input() { 1084 // The address is loaded from thread by a seperate node. 1085 return true; 1086 } 1087 1088 //============================================================================= 1089 1090 // Emit an interrupt that is caught by the debugger (for debugging compiler). 1091 void emit_break(CodeBuffer &cbuf) { 1092 MacroAssembler _masm(&cbuf); 1093 __ illtrap(); 1094 } 1095 1096 #ifndef PRODUCT 1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1098 st->print("BREAKPOINT"); 1099 } 1100 #endif 1101 1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1103 emit_break(cbuf); 1104 } 1105 1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 1107 return MachNode::size(ra_); 1108 } 1109 1110 //============================================================================= 1111 1112 void emit_nop(CodeBuffer &cbuf) { 1113 MacroAssembler _masm(&cbuf); 1114 __ nop(); 1115 } 1116 1117 static inline void emit_long(CodeBuffer &cbuf, int value) { 1118 *((int*)(cbuf.insts_end())) = value; 1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); 1120 } 1121 1122 //============================================================================= 1123 1124 %} // interrupt source 1125 1126 source_hpp %{ // Header information of the source block. 1127 1128 //-------------------------------------------------------------- 1129 //---< Used for optimization in Compile::Shorten_branches >--- 1130 //-------------------------------------------------------------- 1131 1132 const uint trampoline_stub_size = 6 * BytesPerInstWord; 1133 1134 class CallStubImpl { 1135 1136 public: 1137 1138 // Emit call stub, compiled java to interpreter. 1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 1140 1141 // Size of call trampoline stub. 1142 // This doesn't need to be accurate to the byte, but it 1143 // must be larger than or equal to the real size of the stub. 1144 static uint size_call_trampoline() { 1145 return trampoline_stub_size; 1146 } 1147 1148 // number of relocations needed by a call trampoline stub 1149 static uint reloc_call_trampoline() { 1150 return 5; 1151 } 1152 1153 }; 1154 1155 %} // end source_hpp 1156 1157 source %{ 1158 1159 // Emit a trampoline stub for a call to a target which is too far away. 1160 // 1161 // code sequences: 1162 // 1163 // call-site: 1164 // branch-and-link to <destination> or <trampoline stub> 1165 // 1166 // Related trampoline stub for this call-site in the stub section: 1167 // load the call target from the constant pool 1168 // branch via CTR (LR/link still points to the call-site above) 1169 1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { 1171 // Start the stub. 1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2); 1173 if (stub == NULL) { 1174 Compile::current()->env()->record_out_of_memory_failure(); 1175 return; 1176 } 1177 1178 // For java_to_interp stubs we use R11_scratch1 as scratch register 1179 // and in call trampoline stubs we use R12_scratch2. This way we 1180 // can distinguish them (see is_NativeCallTrampolineStub_at()). 1181 Register reg_scratch = R12_scratch2; 1182 1183 // Create a trampoline stub relocation which relates this trampoline stub 1184 // with the call instruction at insts_call_instruction_offset in the 1185 // instructions code-section. 1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset)); 1187 const int stub_start_offset = __ offset(); 1188 1189 // Now, create the trampoline stub's code: 1190 // - load the TOC 1191 // - load the call target from the constant pool 1192 // - call 1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); 1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false); 1195 __ mtctr(reg_scratch); 1196 __ bctr(); 1197 1198 const address stub_start_addr = __ addr_at(stub_start_offset); 1199 1200 // FIXME: Assert that the trampoline stub can be identified and patched. 1201 1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct. 1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(), 1204 "encoded offset into the constant pool must match"); 1205 // Trampoline_stub_size should be good. 1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size"); 1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 1208 1209 // End the stub. 1210 __ end_a_stub(); 1211 } 1212 1213 //============================================================================= 1214 1215 // Emit an inline branch-and-link call and a related trampoline stub. 1216 // 1217 // code sequences: 1218 // 1219 // call-site: 1220 // branch-and-link to <destination> or <trampoline stub> 1221 // 1222 // Related trampoline stub for this call-site in the stub section: 1223 // load the call target from the constant pool 1224 // branch via CTR (LR/link still points to the call-site above) 1225 // 1226 1227 typedef struct { 1228 int insts_call_instruction_offset; 1229 int ret_addr_offset; 1230 } EmitCallOffsets; 1231 1232 // Emit a branch-and-link instruction that branches to a trampoline. 1233 // - Remember the offset of the branch-and-link instruction. 1234 // - Add a relocation at the branch-and-link instruction. 1235 // - Emit a branch-and-link. 1236 // - Remember the return pc offset. 1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { 1238 EmitCallOffsets offsets = { -1, -1 }; 1239 const int start_offset = __ offset(); 1240 offsets.insts_call_instruction_offset = __ offset(); 1241 1242 // No entry point given, use the current pc. 1243 if (entry_point == NULL) entry_point = __ pc(); 1244 1245 if (!Compile::current()->in_scratch_emit_size()) { 1246 // Put the entry point as a constant into the constant pool. 1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 1249 1250 // Emit the trampoline stub which will be related to the branch-and-link below. 1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 1252 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full. 1253 __ relocate(rtype); 1254 } 1255 1256 // Note: At this point we do not have the address of the trampoline 1257 // stub, and the entry point might be too far away for bl, so __ pc() 1258 // serves as dummy and the bl will be patched later. 1259 __ bl((address) __ pc()); 1260 1261 offsets.ret_addr_offset = __ offset() - start_offset; 1262 1263 return offsets; 1264 } 1265 1266 //============================================================================= 1267 1268 // Factory for creating loadConL* nodes for large/small constant pool. 1269 1270 static inline jlong replicate_immF(float con) { 1271 // Replicate float con 2 times and pack into vector. 1272 int val = *((int*)&con); 1273 jlong lval = val; 1274 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 1275 return lval; 1276 } 1277 1278 //============================================================================= 1279 1280 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); 1281 int Compile::ConstantTable::calculate_table_base_offset() const { 1282 return 0; // absolute addressing, no offset 1283 } 1284 1285 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } 1286 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1287 iRegPdstOper *op_dst = new iRegPdstOper(); 1288 MachNode *m1 = new loadToc_hiNode(); 1289 MachNode *m2 = new loadToc_loNode(); 1290 1291 m1->add_req(NULL); 1292 m2->add_req(NULL, m1); 1293 m1->_opnds[0] = op_dst; 1294 m2->_opnds[0] = op_dst; 1295 m2->_opnds[1] = op_dst; 1296 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1297 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1298 nodes->push(m1); 1299 nodes->push(m2); 1300 } 1301 1302 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1303 // Is postalloc expanded. 1304 ShouldNotReachHere(); 1305 } 1306 1307 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1308 return 0; 1309 } 1310 1311 #ifndef PRODUCT 1312 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1313 st->print("-- \t// MachConstantBaseNode (empty encoding)"); 1314 } 1315 #endif 1316 1317 //============================================================================= 1318 1319 #ifndef PRODUCT 1320 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1321 Compile* C = ra_->C; 1322 const long framesize = C->frame_slots() << LogBytesPerInt; 1323 1324 st->print("PROLOG\n\t"); 1325 if (C->need_stack_bang(framesize)) { 1326 st->print("stack_overflow_check\n\t"); 1327 } 1328 1329 if (!false /* TODO: PPC port C->is_frameless_method()*/) { 1330 st->print("save return pc\n\t"); 1331 st->print("push frame %ld\n\t", -framesize); 1332 } 1333 } 1334 #endif 1335 1336 // Macro used instead of the common __ to emulate the pipes of PPC. 1337 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the 1338 // micro scheduler to cope with "hand written" assembler like in the prolog. Though 1339 // still no scheduling of this code is possible, the micro scheduler is aware of the 1340 // code and can update its internal data. The following mechanism is used to achieve this: 1341 // The micro scheduler calls size() of each compound node during scheduling. size() does a 1342 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. 1343 #if 0 // TODO: PPC port 1344 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1345 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ 1346 _masm. 1347 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1348 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) 1349 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1350 C->hb_scheduling()->_pdScheduling->advance_offset 1351 #else 1352 #define ___(op) if (UsePower6SchedulerPPC64) \ 1353 Unimplemented(); \ 1354 _masm. 1355 #define ___stop if (UsePower6SchedulerPPC64) \ 1356 Unimplemented() 1357 #define ___advance if (UsePower6SchedulerPPC64) \ 1358 Unimplemented() 1359 #endif 1360 1361 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1362 Compile* C = ra_->C; 1363 MacroAssembler _masm(&cbuf); 1364 1365 const long framesize = C->frame_size_in_bytes(); 1366 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment"); 1367 1368 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1369 1370 const Register return_pc = R20; // Must match return_addr() in frame section. 1371 const Register callers_sp = R21; 1372 const Register push_frame_temp = R22; 1373 const Register toc_temp = R23; 1374 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); 1375 1376 if (method_is_frameless) { 1377 // Add nop at beginning of all frameless methods to prevent any 1378 // oop instructions from getting overwritten by make_not_entrant 1379 // (patching attempt would fail). 1380 ___(nop) nop(); 1381 } else { 1382 // Get return pc. 1383 ___(mflr) mflr(return_pc); 1384 } 1385 1386 // Calls to C2R adapters often do not accept exceptional returns. 1387 // We require that their callers must bang for them. But be 1388 // careful, because some VM calls (such as call site linkage) can 1389 // use several kilobytes of stack. But the stack safety zone should 1390 // account for that. See bugs 4446381, 4468289, 4497237. 1391 1392 int bangsize = C->bang_size_in_bytes(); 1393 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect"); 1394 if (C->need_stack_bang(bangsize) && UseStackBanging) { 1395 // Unfortunately we cannot use the function provided in 1396 // assembler.cpp as we have to emulate the pipes. So I had to 1397 // insert the code of generate_stack_overflow_check(), see 1398 // assembler.cpp for some illuminative comments. 1399 const int page_size = os::vm_page_size(); 1400 int bang_end = StackShadowPages * page_size; 1401 1402 // This is how far the previous frame's stack banging extended. 1403 const int bang_end_safe = bang_end; 1404 1405 if (bangsize > page_size) { 1406 bang_end += bangsize; 1407 } 1408 1409 int bang_offset = bang_end_safe; 1410 1411 while (bang_offset <= bang_end) { 1412 // Need at least one stack bang at end of shadow zone. 1413 1414 // Again I had to copy code, this time from assembler_ppc.cpp, 1415 // bang_stack_with_offset - see there for comments. 1416 1417 // Stack grows down, caller passes positive offset. 1418 assert(bang_offset > 0, "must bang with positive offset"); 1419 1420 long stdoffset = -bang_offset; 1421 1422 if (Assembler::is_simm(stdoffset, 16)) { 1423 // Signed 16 bit offset, a simple std is ok. 1424 if (UseLoadInstructionsForStackBangingPPC64) { 1425 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); 1426 } else { 1427 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); 1428 } 1429 } else if (Assembler::is_simm(stdoffset, 31)) { 1430 // Use largeoffset calculations for addis & ld/std. 1431 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); 1432 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); 1433 1434 Register tmp = R11; 1435 ___(addis) addis(tmp, R1_SP, hi); 1436 if (UseLoadInstructionsForStackBangingPPC64) { 1437 ___(ld) ld(R0, lo, tmp); 1438 } else { 1439 ___(std) std(R0, lo, tmp); 1440 } 1441 } else { 1442 ShouldNotReachHere(); 1443 } 1444 1445 bang_offset += page_size; 1446 } 1447 // R11 trashed 1448 } // C->need_stack_bang(framesize) && UseStackBanging 1449 1450 unsigned int bytes = (unsigned int)framesize; 1451 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 1452 ciMethod *currMethod = C->method(); 1453 1454 // Optimized version for most common case. 1455 if (UsePower6SchedulerPPC64 && 1456 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && 1457 !(false /* ConstantsALot TODO: PPC port*/)) { 1458 ___(or) mr(callers_sp, R1_SP); 1459 ___(std) std(return_pc, _abi(lr), R1_SP); 1460 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1461 return; 1462 } 1463 1464 if (!method_is_frameless) { 1465 // Get callers sp. 1466 ___(or) mr(callers_sp, R1_SP); 1467 1468 // Push method's frame, modifies SP. 1469 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); 1470 // The ABI is already accounted for in 'framesize' via the 1471 // 'out_preserve' area. 1472 Register tmp = push_frame_temp; 1473 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). 1474 if (Assembler::is_simm(-offset, 16)) { 1475 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1476 } else { 1477 long x = -offset; 1478 // Had to insert load_const(tmp, -offset). 1479 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); 1480 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); 1481 ___(rldicr) sldi(tmp, tmp, 32); 1482 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); 1483 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); 1484 1485 ___(stdux) stdux(R1_SP, R1_SP, tmp); 1486 } 1487 } 1488 #if 0 // TODO: PPC port 1489 // For testing large constant pools, emit a lot of constants to constant pool. 1490 // "Randomize" const_size. 1491 if (ConstantsALot) { 1492 const int num_consts = const_size(); 1493 for (int i = 0; i < num_consts; i++) { 1494 __ long_constant(0xB0B5B00BBABE); 1495 } 1496 } 1497 #endif 1498 if (!method_is_frameless) { 1499 // Save return pc. 1500 ___(std) std(return_pc, _abi(lr), callers_sp); 1501 } 1502 } 1503 #undef ___ 1504 #undef ___stop 1505 #undef ___advance 1506 1507 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1508 // Variable size. determine dynamically. 1509 return MachNode::size(ra_); 1510 } 1511 1512 int MachPrologNode::reloc() const { 1513 // Return number of relocatable values contained in this instruction. 1514 return 1; // 1 reloc entry for load_const(toc). 1515 } 1516 1517 //============================================================================= 1518 1519 #ifndef PRODUCT 1520 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1521 Compile* C = ra_->C; 1522 1523 st->print("EPILOG\n\t"); 1524 st->print("restore return pc\n\t"); 1525 st->print("pop frame\n\t"); 1526 1527 if (do_polling() && C->is_method_compilation()) { 1528 st->print("touch polling page\n\t"); 1529 } 1530 } 1531 #endif 1532 1533 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1534 Compile* C = ra_->C; 1535 MacroAssembler _masm(&cbuf); 1536 1537 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; 1538 assert(framesize >= 0, "negative frame-size?"); 1539 1540 const bool method_needs_polling = do_polling() && C->is_method_compilation(); 1541 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1542 const Register return_pc = R11; 1543 const Register polling_page = R12; 1544 1545 if (!method_is_frameless) { 1546 // Restore return pc relative to callers' sp. 1547 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); 1548 } 1549 1550 if (method_needs_polling) { 1551 if (LoadPollAddressFromThread) { 1552 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1553 Unimplemented(); 1554 } else { 1555 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() 1556 } 1557 } 1558 1559 if (!method_is_frameless) { 1560 // Move return pc to LR. 1561 __ mtlr(return_pc); 1562 // Pop frame (fixed frame-size). 1563 __ addi(R1_SP, R1_SP, (int)framesize); 1564 } 1565 1566 if (method_needs_polling) { 1567 // We need to mark the code position where the load from the safepoint 1568 // polling page was emitted as relocInfo::poll_return_type here. 1569 __ relocate(relocInfo::poll_return_type); 1570 __ load_from_polling_page(polling_page); 1571 } 1572 } 1573 1574 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1575 // Variable size. Determine dynamically. 1576 return MachNode::size(ra_); 1577 } 1578 1579 int MachEpilogNode::reloc() const { 1580 // Return number of relocatable values contained in this instruction. 1581 return 1; // 1 for load_from_polling_page. 1582 } 1583 1584 const Pipeline * MachEpilogNode::pipeline() const { 1585 return MachNode::pipeline_class(); 1586 } 1587 1588 // This method seems to be obsolete. It is declared in machnode.hpp 1589 // and defined in all *.ad files, but it is never called. Should we 1590 // get rid of it? 1591 int MachEpilogNode::safepoint_offset() const { 1592 assert(do_polling(), "no return for this epilog node"); 1593 return 0; 1594 } 1595 1596 #if 0 // TODO: PPC port 1597 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1598 MacroAssembler _masm(&cbuf); 1599 if (LoadPollAddressFromThread) { 1600 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1601 } else { 1602 _masm.nop(); 1603 } 1604 } 1605 1606 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { 1607 if (LoadPollAddressFromThread) { 1608 return 4; 1609 } else { 1610 return 4; 1611 } 1612 } 1613 1614 #ifndef PRODUCT 1615 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1616 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); 1617 } 1618 #endif 1619 1620 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { 1621 return RSCRATCH1_BITS64_REG_mask(); 1622 } 1623 #endif // PPC port 1624 1625 // ============================================================================= 1626 1627 // Figure out which register class each belongs in: rc_int, rc_float or 1628 // rc_stack. 1629 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1630 1631 static enum RC rc_class(OptoReg::Name reg) { 1632 // Return the register class for the given register. The given register 1633 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 1634 // enumeration in adGlobals_ppc.hpp. 1635 1636 if (reg == OptoReg::Bad) return rc_bad; 1637 1638 // We have 64 integer register halves, starting at index 0. 1639 if (reg < 64) return rc_int; 1640 1641 // We have 64 floating-point register halves, starting at index 64. 1642 if (reg < 64+64) return rc_float; 1643 1644 // Between float regs & stack are the flags regs. 1645 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); 1646 1647 return rc_stack; 1648 } 1649 1650 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, 1651 bool do_print, Compile* C, outputStream *st) { 1652 1653 assert(opcode == Assembler::LD_OPCODE || 1654 opcode == Assembler::STD_OPCODE || 1655 opcode == Assembler::LWZ_OPCODE || 1656 opcode == Assembler::STW_OPCODE || 1657 opcode == Assembler::LFD_OPCODE || 1658 opcode == Assembler::STFD_OPCODE || 1659 opcode == Assembler::LFS_OPCODE || 1660 opcode == Assembler::STFS_OPCODE, 1661 "opcode not supported"); 1662 1663 if (cbuf) { 1664 int d = 1665 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? 1666 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) 1667 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. 1668 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); 1669 } 1670 #ifndef PRODUCT 1671 else if (do_print) { 1672 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", 1673 op_str, 1674 Matcher::regName[reg], 1675 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); 1676 } 1677 #endif 1678 return 4; // size 1679 } 1680 1681 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { 1682 Compile* C = ra_->C; 1683 1684 // Get registers to move. 1685 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1686 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1687 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1688 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1689 1690 enum RC src_hi_rc = rc_class(src_hi); 1691 enum RC src_lo_rc = rc_class(src_lo); 1692 enum RC dst_hi_rc = rc_class(dst_hi); 1693 enum RC dst_lo_rc = rc_class(dst_lo); 1694 1695 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1696 if (src_hi != OptoReg::Bad) 1697 assert((src_lo&1)==0 && src_lo+1==src_hi && 1698 (dst_lo&1)==0 && dst_lo+1==dst_hi, 1699 "expected aligned-adjacent pairs"); 1700 // Generate spill code! 1701 int size = 0; 1702 1703 if (src_lo == dst_lo && src_hi == dst_hi) 1704 return size; // Self copy, no move. 1705 1706 // -------------------------------------- 1707 // Memory->Memory Spill. Use R0 to hold the value. 1708 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1709 int src_offset = ra_->reg2offset(src_lo); 1710 int dst_offset = ra_->reg2offset(dst_lo); 1711 if (src_hi != OptoReg::Bad) { 1712 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, 1713 "expected same type of move for high parts"); 1714 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); 1715 if (!cbuf && !do_size) st->print("\n\t"); 1716 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); 1717 } else { 1718 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); 1719 if (!cbuf && !do_size) st->print("\n\t"); 1720 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); 1721 } 1722 return size; 1723 } 1724 1725 // -------------------------------------- 1726 // Check for float->int copy; requires a trip through memory. 1727 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1728 Unimplemented(); 1729 } 1730 1731 // -------------------------------------- 1732 // Check for integer reg-reg copy. 1733 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1734 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1735 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1736 size = (Rsrc != Rdst) ? 4 : 0; 1737 1738 if (cbuf) { 1739 MacroAssembler _masm(cbuf); 1740 if (size) { 1741 __ mr(Rdst, Rsrc); 1742 } 1743 } 1744 #ifndef PRODUCT 1745 else if (!do_size) { 1746 if (size) { 1747 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1748 } else { 1749 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1750 } 1751 } 1752 #endif 1753 return size; 1754 } 1755 1756 // Check for integer store. 1757 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1758 int dst_offset = ra_->reg2offset(dst_lo); 1759 if (src_hi != OptoReg::Bad) { 1760 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, 1761 "expected same type of move for high parts"); 1762 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1763 } else { 1764 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); 1765 } 1766 return size; 1767 } 1768 1769 // Check for integer load. 1770 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1771 int src_offset = ra_->reg2offset(src_lo); 1772 if (src_hi != OptoReg::Bad) { 1773 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, 1774 "expected same type of move for high parts"); 1775 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1776 } else { 1777 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); 1778 } 1779 return size; 1780 } 1781 1782 // Check for float reg-reg copy. 1783 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1784 if (cbuf) { 1785 MacroAssembler _masm(cbuf); 1786 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1787 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1788 __ fmr(Rdst, Rsrc); 1789 } 1790 #ifndef PRODUCT 1791 else if (!do_size) { 1792 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1793 } 1794 #endif 1795 return 4; 1796 } 1797 1798 // Check for float store. 1799 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1800 int dst_offset = ra_->reg2offset(dst_lo); 1801 if (src_hi != OptoReg::Bad) { 1802 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, 1803 "expected same type of move for high parts"); 1804 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1805 } else { 1806 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); 1807 } 1808 return size; 1809 } 1810 1811 // Check for float load. 1812 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1813 int src_offset = ra_->reg2offset(src_lo); 1814 if (src_hi != OptoReg::Bad) { 1815 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, 1816 "expected same type of move for high parts"); 1817 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1818 } else { 1819 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); 1820 } 1821 return size; 1822 } 1823 1824 // -------------------------------------------------------------------- 1825 // Check for hi bits still needing moving. Only happens for misaligned 1826 // arguments to native calls. 1827 if (src_hi == dst_hi) 1828 return size; // Self copy; no move. 1829 1830 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1831 ShouldNotReachHere(); // Unimplemented 1832 return 0; 1833 } 1834 1835 #ifndef PRODUCT 1836 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1837 if (!ra_) 1838 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); 1839 else 1840 implementation(NULL, ra_, false, st); 1841 } 1842 #endif 1843 1844 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1845 implementation(&cbuf, ra_, false, NULL); 1846 } 1847 1848 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1849 return implementation(NULL, ra_, true, NULL); 1850 } 1851 1852 #if 0 // TODO: PPC port 1853 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { 1854 #ifndef PRODUCT 1855 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; 1856 #endif 1857 assert(ra_->node_regs_max_index() != 0, ""); 1858 1859 // Get registers to move. 1860 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); 1861 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); 1862 OptoReg::Name dst_hi = ra_->get_reg_second(n); 1863 OptoReg::Name dst_lo = ra_->get_reg_first(n); 1864 1865 enum RC src_lo_rc = rc_class(src_lo); 1866 enum RC dst_lo_rc = rc_class(dst_lo); 1867 1868 if (src_lo == dst_lo && src_hi == dst_hi) 1869 return ppc64Opcode_none; // Self copy, no move. 1870 1871 // -------------------------------------- 1872 // Memory->Memory Spill. Use R0 to hold the value. 1873 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1874 return ppc64Opcode_compound; 1875 } 1876 1877 // -------------------------------------- 1878 // Check for float->int copy; requires a trip through memory. 1879 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1880 Unimplemented(); 1881 } 1882 1883 // -------------------------------------- 1884 // Check for integer reg-reg copy. 1885 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1886 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1887 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1888 if (Rsrc == Rdst) { 1889 return ppc64Opcode_none; 1890 } else { 1891 return ppc64Opcode_or; 1892 } 1893 } 1894 1895 // Check for integer store. 1896 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1897 if (src_hi != OptoReg::Bad) { 1898 return ppc64Opcode_std; 1899 } else { 1900 return ppc64Opcode_stw; 1901 } 1902 } 1903 1904 // Check for integer load. 1905 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1906 if (src_hi != OptoReg::Bad) { 1907 return ppc64Opcode_ld; 1908 } else { 1909 return ppc64Opcode_lwz; 1910 } 1911 } 1912 1913 // Check for float reg-reg copy. 1914 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1915 return ppc64Opcode_fmr; 1916 } 1917 1918 // Check for float store. 1919 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1920 if (src_hi != OptoReg::Bad) { 1921 return ppc64Opcode_stfd; 1922 } else { 1923 return ppc64Opcode_stfs; 1924 } 1925 } 1926 1927 // Check for float load. 1928 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1929 if (src_hi != OptoReg::Bad) { 1930 return ppc64Opcode_lfd; 1931 } else { 1932 return ppc64Opcode_lfs; 1933 } 1934 } 1935 1936 // -------------------------------------------------------------------- 1937 // Check for hi bits still needing moving. Only happens for misaligned 1938 // arguments to native calls. 1939 if (src_hi == dst_hi) { 1940 return ppc64Opcode_none; // Self copy; no move. 1941 } 1942 1943 ShouldNotReachHere(); 1944 return ppc64Opcode_undefined; 1945 } 1946 #endif // PPC port 1947 1948 #ifndef PRODUCT 1949 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1950 st->print("NOP \t// %d nops to pad for loops.", _count); 1951 } 1952 #endif 1953 1954 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1955 MacroAssembler _masm(&cbuf); 1956 // _count contains the number of nops needed for padding. 1957 for (int i = 0; i < _count; i++) { 1958 __ nop(); 1959 } 1960 } 1961 1962 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1963 return _count * 4; 1964 } 1965 1966 #ifndef PRODUCT 1967 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1968 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1969 char reg_str[128]; 1970 ra_->dump_register(this, reg_str); 1971 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset); 1972 } 1973 #endif 1974 1975 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1976 MacroAssembler _masm(&cbuf); 1977 1978 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1979 int reg = ra_->get_encode(this); 1980 1981 if (Assembler::is_simm(offset, 16)) { 1982 __ addi(as_Register(reg), R1, offset); 1983 } else { 1984 ShouldNotReachHere(); 1985 } 1986 } 1987 1988 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1989 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). 1990 return 4; 1991 } 1992 1993 #ifndef PRODUCT 1994 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1995 st->print_cr("---- MachUEPNode ----"); 1996 st->print_cr("..."); 1997 } 1998 #endif 1999 2000 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 2001 // This is the unverified entry point. 2002 MacroAssembler _masm(&cbuf); 2003 2004 // Inline_cache contains a klass. 2005 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 2006 Register receiver_klass = R12_scratch2; // tmp 2007 2008 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 2009 assert(R11_scratch1 == R11, "need prologue scratch register"); 2010 2011 // Check for NULL argument if we don't have implicit null checks. 2012 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { 2013 if (TrapBasedNullChecks) { 2014 __ trap_null_check(R3_ARG1); 2015 } else { 2016 Label valid; 2017 __ cmpdi(CCR0, R3_ARG1, 0); 2018 __ bne_predict_taken(CCR0, valid); 2019 // We have a null argument, branch to ic_miss_stub. 2020 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 2021 relocInfo::runtime_call_type); 2022 __ bind(valid); 2023 } 2024 } 2025 // Assume argument is not NULL, load klass from receiver. 2026 __ load_klass(receiver_klass, R3_ARG1); 2027 2028 if (TrapBasedICMissChecks) { 2029 __ trap_ic_miss_check(receiver_klass, ic_klass); 2030 } else { 2031 Label valid; 2032 __ cmpd(CCR0, receiver_klass, ic_klass); 2033 __ beq_predict_taken(CCR0, valid); 2034 // We have an unexpected klass, branch to ic_miss_stub. 2035 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 2036 relocInfo::runtime_call_type); 2037 __ bind(valid); 2038 } 2039 2040 // Argument is valid and klass is as expected, continue. 2041 } 2042 2043 #if 0 // TODO: PPC port 2044 // Optimize UEP code on z (save a load_const() call in main path). 2045 int MachUEPNode::ep_offset() { 2046 return 0; 2047 } 2048 #endif 2049 2050 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 2051 // Variable size. Determine dynamically. 2052 return MachNode::size(ra_); 2053 } 2054 2055 //============================================================================= 2056 2057 %} // interrupt source 2058 2059 source_hpp %{ // Header information of the source block. 2060 2061 class HandlerImpl { 2062 2063 public: 2064 2065 static int emit_exception_handler(CodeBuffer &cbuf); 2066 static int emit_deopt_handler(CodeBuffer& cbuf); 2067 2068 static uint size_exception_handler() { 2069 // The exception_handler is a b64_patchable. 2070 return MacroAssembler::b64_patchable_size; 2071 } 2072 2073 static uint size_deopt_handler() { 2074 // The deopt_handler is a bl64_patchable. 2075 return MacroAssembler::bl64_patchable_size; 2076 } 2077 2078 }; 2079 2080 %} // end source_hpp 2081 2082 source %{ 2083 2084 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 2085 MacroAssembler _masm(&cbuf); 2086 2087 address base = __ start_a_stub(size_exception_handler()); 2088 if (base == NULL) return 0; // CodeBuffer::expand failed 2089 2090 int offset = __ offset(); 2091 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), 2092 relocInfo::runtime_call_type); 2093 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); 2094 __ end_a_stub(); 2095 2096 return offset; 2097 } 2098 2099 // The deopt_handler is like the exception handler, but it calls to 2100 // the deoptimization blob instead of jumping to the exception blob. 2101 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 2102 MacroAssembler _masm(&cbuf); 2103 2104 address base = __ start_a_stub(size_deopt_handler()); 2105 if (base == NULL) return 0; // CodeBuffer::expand failed 2106 2107 int offset = __ offset(); 2108 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), 2109 relocInfo::runtime_call_type); 2110 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 2111 __ end_a_stub(); 2112 2113 return offset; 2114 } 2115 2116 //============================================================================= 2117 2118 // Use a frame slots bias for frameless methods if accessing the stack. 2119 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { 2120 if (as_Register(reg_enc) == R1_SP) { 2121 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); 2122 } 2123 return 0; 2124 } 2125 2126 const bool Matcher::match_rule_supported(int opcode) { 2127 if (!has_match_rule(opcode)) 2128 return false; 2129 2130 switch (opcode) { 2131 case Op_SqrtD: 2132 return VM_Version::has_fsqrt(); 2133 case Op_CountLeadingZerosI: 2134 case Op_CountLeadingZerosL: 2135 case Op_CountTrailingZerosI: 2136 case Op_CountTrailingZerosL: 2137 if (!UseCountLeadingZerosInstructionsPPC64) 2138 return false; 2139 break; 2140 2141 case Op_PopCountI: 2142 case Op_PopCountL: 2143 return (UsePopCountInstruction && VM_Version::has_popcntw()); 2144 2145 case Op_StrComp: 2146 return SpecialStringCompareTo; 2147 case Op_StrEquals: 2148 return SpecialStringEquals; 2149 case Op_StrIndexOf: 2150 return SpecialStringIndexOf; 2151 } 2152 2153 return true; // Per default match rules are supported. 2154 } 2155 2156 int Matcher::regnum_to_fpu_offset(int regnum) { 2157 // No user for this method? 2158 Unimplemented(); 2159 return 999; 2160 } 2161 2162 const bool Matcher::convL2FSupported(void) { 2163 // fcfids can do the conversion (>= Power7). 2164 // fcfid + frsp showed rounding problem when result should be 0x3f800001. 2165 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. 2166 } 2167 2168 // Vector width in bytes. 2169 const int Matcher::vector_width_in_bytes(BasicType bt) { 2170 assert(MaxVectorSize == 8, ""); 2171 return 8; 2172 } 2173 2174 // Vector ideal reg. 2175 const int Matcher::vector_ideal_reg(int size) { 2176 assert(MaxVectorSize == 8 && size == 8, ""); 2177 return Op_RegL; 2178 } 2179 2180 const int Matcher::vector_shift_count_ideal_reg(int size) { 2181 fatal("vector shift is not supported"); 2182 return Node::NotAMachineReg; 2183 } 2184 2185 // Limits on vector size (number of elements) loaded into vector. 2186 const int Matcher::max_vector_size(const BasicType bt) { 2187 assert(is_java_primitive(bt), "only primitive type vectors"); 2188 return vector_width_in_bytes(bt)/type2aelembytes(bt); 2189 } 2190 2191 const int Matcher::min_vector_size(const BasicType bt) { 2192 return max_vector_size(bt); // Same as max. 2193 } 2194 2195 // PPC doesn't support misaligned vectors store/load. 2196 const bool Matcher::misaligned_vectors_ok() { 2197 return false; 2198 } 2199 2200 // PPC AES support not yet implemented 2201 const bool Matcher::pass_original_key_for_aes() { 2202 return false; 2203 } 2204 2205 // RETURNS: whether this branch offset is short enough that a short 2206 // branch can be used. 2207 // 2208 // If the platform does not provide any short branch variants, then 2209 // this method should return `false' for offset 0. 2210 // 2211 // `Compile::Fill_buffer' will decide on basis of this information 2212 // whether to do the pass `Compile::Shorten_branches' at all. 2213 // 2214 // And `Compile::Shorten_branches' will decide on basis of this 2215 // information whether to replace particular branch sites by short 2216 // ones. 2217 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 2218 // Is the offset within the range of a ppc64 pc relative branch? 2219 bool b; 2220 2221 const int safety_zone = 3 * BytesPerInstWord; 2222 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), 2223 29 - 16 + 1 + 2); 2224 return b; 2225 } 2226 2227 const bool Matcher::isSimpleConstant64(jlong value) { 2228 // Probably always true, even if a temp register is required. 2229 return true; 2230 } 2231 /* TODO: PPC port 2232 // Make a new machine dependent decode node (with its operands). 2233 MachTypeNode *Matcher::make_decode_node() { 2234 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, 2235 "This method is only implemented for unscaled cOops mode so far"); 2236 MachTypeNode *decode = new decodeN_unscaledNode(); 2237 decode->set_opnd_array(0, new iRegPdstOper()); 2238 decode->set_opnd_array(1, new iRegNsrcOper()); 2239 return decode; 2240 } 2241 */ 2242 // Threshold size for cleararray. 2243 const int Matcher::init_array_short_size = 8 * BytesPerLong; 2244 2245 // false => size gets scaled to BytesPerLong, ok. 2246 const bool Matcher::init_array_count_is_in_bytes = false; 2247 2248 // Use conditional move (CMOVL) on Power7. 2249 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves 2250 2251 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. 2252 // fsel doesn't accept a condition register as input, so this would be slightly different. 2253 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 2254 2255 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). 2256 const bool Matcher::require_postalloc_expand = true; 2257 2258 // Should the Matcher clone shifts on addressing modes, expecting them to 2259 // be subsumed into complex addressing expressions or compute them into 2260 // registers? True for Intel but false for most RISCs. 2261 const bool Matcher::clone_shift_expressions = false; 2262 2263 // Do we need to mask the count passed to shift instructions or does 2264 // the cpu only look at the lower 5/6 bits anyway? 2265 // Off, as masks are generated in expand rules where required. 2266 // Constant shift counts are handled in Ideal phase. 2267 const bool Matcher::need_masked_shift_count = false; 2268 2269 // This affects two different things: 2270 // - how Decode nodes are matched 2271 // - how ImplicitNullCheck opportunities are recognized 2272 // If true, the matcher will try to remove all Decodes and match them 2273 // (as operands) into nodes. NullChecks are not prepared to deal with 2274 // Decodes by final_graph_reshaping(). 2275 // If false, final_graph_reshaping() forces the decode behind the Cmp 2276 // for a NullCheck. The matcher matches the Decode node into a register. 2277 // Implicit_null_check optimization moves the Decode along with the 2278 // memory operation back up before the NullCheck. 2279 bool Matcher::narrow_oop_use_complex_address() { 2280 // TODO: PPC port if (MatchDecodeNodes) return true; 2281 return false; 2282 } 2283 2284 bool Matcher::narrow_klass_use_complex_address() { 2285 NOT_LP64(ShouldNotCallThis()); 2286 assert(UseCompressedClassPointers, "only for compressed klass code"); 2287 // TODO: PPC port if (MatchDecodeNodes) return true; 2288 return false; 2289 } 2290 2291 // Is it better to copy float constants, or load them directly from memory? 2292 // Intel can load a float constant from a direct address, requiring no 2293 // extra registers. Most RISCs will have to materialize an address into a 2294 // register first, so they would do better to copy the constant from stack. 2295 const bool Matcher::rematerialize_float_constants = false; 2296 2297 // If CPU can load and store mis-aligned doubles directly then no fixup is 2298 // needed. Else we split the double into 2 integer pieces and move it 2299 // piece-by-piece. Only happens when passing doubles into C code as the 2300 // Java calling convention forces doubles to be aligned. 2301 const bool Matcher::misaligned_doubles_ok = true; 2302 2303 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2304 Unimplemented(); 2305 } 2306 2307 // Advertise here if the CPU requires explicit rounding operations 2308 // to implement the UseStrictFP mode. 2309 const bool Matcher::strict_fp_requires_explicit_rounding = false; 2310 2311 // Do floats take an entire double register or just half? 2312 // 2313 // A float occupies a ppc64 double register. For the allocator, a 2314 // ppc64 double register appears as a pair of float registers. 2315 bool Matcher::float_in_double() { return true; } 2316 2317 // Do ints take an entire long register or just half? 2318 // The relevant question is how the int is callee-saved: 2319 // the whole long is written but de-opt'ing will have to extract 2320 // the relevant 32 bits. 2321 const bool Matcher::int_in_long = true; 2322 2323 // Constants for c2c and c calling conventions. 2324 2325 const MachRegisterNumbers iarg_reg[8] = { 2326 R3_num, R4_num, R5_num, R6_num, 2327 R7_num, R8_num, R9_num, R10_num 2328 }; 2329 2330 const MachRegisterNumbers farg_reg[13] = { 2331 F1_num, F2_num, F3_num, F4_num, 2332 F5_num, F6_num, F7_num, F8_num, 2333 F9_num, F10_num, F11_num, F12_num, 2334 F13_num 2335 }; 2336 2337 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); 2338 2339 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); 2340 2341 // Return whether or not this register is ever used as an argument. This 2342 // function is used on startup to build the trampoline stubs in generateOptoStub. 2343 // Registers not mentioned will be killed by the VM call in the trampoline, and 2344 // arguments in those registers not be available to the callee. 2345 bool Matcher::can_be_java_arg(int reg) { 2346 // We return true for all registers contained in iarg_reg[] and 2347 // farg_reg[] and their virtual halves. 2348 // We must include the virtual halves in order to get STDs and LDs 2349 // instead of STWs and LWs in the trampoline stubs. 2350 2351 if ( reg == R3_num || reg == R3_H_num 2352 || reg == R4_num || reg == R4_H_num 2353 || reg == R5_num || reg == R5_H_num 2354 || reg == R6_num || reg == R6_H_num 2355 || reg == R7_num || reg == R7_H_num 2356 || reg == R8_num || reg == R8_H_num 2357 || reg == R9_num || reg == R9_H_num 2358 || reg == R10_num || reg == R10_H_num) 2359 return true; 2360 2361 if ( reg == F1_num || reg == F1_H_num 2362 || reg == F2_num || reg == F2_H_num 2363 || reg == F3_num || reg == F3_H_num 2364 || reg == F4_num || reg == F4_H_num 2365 || reg == F5_num || reg == F5_H_num 2366 || reg == F6_num || reg == F6_H_num 2367 || reg == F7_num || reg == F7_H_num 2368 || reg == F8_num || reg == F8_H_num 2369 || reg == F9_num || reg == F9_H_num 2370 || reg == F10_num || reg == F10_H_num 2371 || reg == F11_num || reg == F11_H_num 2372 || reg == F12_num || reg == F12_H_num 2373 || reg == F13_num || reg == F13_H_num) 2374 return true; 2375 2376 return false; 2377 } 2378 2379 bool Matcher::is_spillable_arg(int reg) { 2380 return can_be_java_arg(reg); 2381 } 2382 2383 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 2384 return false; 2385 } 2386 2387 // Register for DIVI projection of divmodI. 2388 RegMask Matcher::divI_proj_mask() { 2389 ShouldNotReachHere(); 2390 return RegMask(); 2391 } 2392 2393 // Register for MODI projection of divmodI. 2394 RegMask Matcher::modI_proj_mask() { 2395 ShouldNotReachHere(); 2396 return RegMask(); 2397 } 2398 2399 // Register for DIVL projection of divmodL. 2400 RegMask Matcher::divL_proj_mask() { 2401 ShouldNotReachHere(); 2402 return RegMask(); 2403 } 2404 2405 // Register for MODL projection of divmodL. 2406 RegMask Matcher::modL_proj_mask() { 2407 ShouldNotReachHere(); 2408 return RegMask(); 2409 } 2410 2411 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2412 return RegMask(); 2413 } 2414 2415 %} 2416 2417 //----------ENCODING BLOCK----------------------------------------------------- 2418 // This block specifies the encoding classes used by the compiler to output 2419 // byte streams. Encoding classes are parameterized macros used by 2420 // Machine Instruction Nodes in order to generate the bit encoding of the 2421 // instruction. Operands specify their base encoding interface with the 2422 // interface keyword. There are currently supported four interfaces, 2423 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2424 // operand to generate a function which returns its register number when 2425 // queried. CONST_INTER causes an operand to generate a function which 2426 // returns the value of the constant when queried. MEMORY_INTER causes an 2427 // operand to generate four functions which return the Base Register, the 2428 // Index Register, the Scale Value, and the Offset Value of the operand when 2429 // queried. COND_INTER causes an operand to generate six functions which 2430 // return the encoding code (ie - encoding bits for the instruction) 2431 // associated with each basic boolean condition for a conditional instruction. 2432 // 2433 // Instructions specify two basic values for encoding. Again, a function 2434 // is available to check if the constant displacement is an oop. They use the 2435 // ins_encode keyword to specify their encoding classes (which must be 2436 // a sequence of enc_class names, and their parameters, specified in 2437 // the encoding block), and they use the 2438 // opcode keyword to specify, in order, their primary, secondary, and 2439 // tertiary opcode. Only the opcode sections which a particular instruction 2440 // needs for encoding need to be specified. 2441 encode %{ 2442 enc_class enc_unimplemented %{ 2443 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2444 MacroAssembler _masm(&cbuf); 2445 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 2446 %} 2447 2448 enc_class enc_untested %{ 2449 #ifdef ASSERT 2450 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2451 MacroAssembler _masm(&cbuf); 2452 __ untested("Untested mach node encoding in AD file."); 2453 #else 2454 // TODO: PPC port $archOpcode(ppc64Opcode_none); 2455 #endif 2456 %} 2457 2458 enc_class enc_lbz(iRegIdst dst, memory mem) %{ 2459 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); 2460 MacroAssembler _masm(&cbuf); 2461 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2462 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2463 %} 2464 2465 // Load acquire. 2466 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ 2467 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2468 MacroAssembler _masm(&cbuf); 2469 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2470 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2471 __ twi_0($dst$$Register); 2472 __ isync(); 2473 %} 2474 2475 enc_class enc_lhz(iRegIdst dst, memory mem) %{ 2476 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); 2477 2478 MacroAssembler _masm(&cbuf); 2479 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2480 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2481 %} 2482 2483 // Load acquire. 2484 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ 2485 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2486 2487 MacroAssembler _masm(&cbuf); 2488 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2489 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2490 __ twi_0($dst$$Register); 2491 __ isync(); 2492 %} 2493 2494 enc_class enc_lwz(iRegIdst dst, memory mem) %{ 2495 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); 2496 2497 MacroAssembler _masm(&cbuf); 2498 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2499 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2500 %} 2501 2502 // Load acquire. 2503 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ 2504 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2505 2506 MacroAssembler _masm(&cbuf); 2507 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2508 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2509 __ twi_0($dst$$Register); 2510 __ isync(); 2511 %} 2512 2513 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ 2514 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2515 MacroAssembler _masm(&cbuf); 2516 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2517 // Operand 'ds' requires 4-alignment. 2518 assert((Idisp & 0x3) == 0, "unaligned offset"); 2519 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2520 %} 2521 2522 // Load acquire. 2523 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ 2524 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2525 MacroAssembler _masm(&cbuf); 2526 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2527 // Operand 'ds' requires 4-alignment. 2528 assert((Idisp & 0x3) == 0, "unaligned offset"); 2529 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2530 __ twi_0($dst$$Register); 2531 __ isync(); 2532 %} 2533 2534 enc_class enc_lfd(RegF dst, memory mem) %{ 2535 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 2536 MacroAssembler _masm(&cbuf); 2537 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2538 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 2539 %} 2540 2541 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ 2542 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2543 2544 MacroAssembler _masm(&cbuf); 2545 int toc_offset = 0; 2546 2547 if (!ra_->C->in_scratch_emit_size()) { 2548 address const_toc_addr; 2549 // Create a non-oop constant, no relocation needed. 2550 // If it is an IC, it has a virtual_call_Relocation. 2551 const_toc_addr = __ long_constant((jlong)$src$$constant); 2552 2553 // Get the constant's TOC offset. 2554 toc_offset = __ offset_to_method_toc(const_toc_addr); 2555 2556 // Keep the current instruction offset in mind. 2557 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); 2558 } 2559 2560 __ ld($dst$$Register, toc_offset, $toc$$Register); 2561 %} 2562 2563 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ 2564 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2565 2566 MacroAssembler _masm(&cbuf); 2567 2568 if (!ra_->C->in_scratch_emit_size()) { 2569 address const_toc_addr; 2570 // Create a non-oop constant, no relocation needed. 2571 // If it is an IC, it has a virtual_call_Relocation. 2572 const_toc_addr = __ long_constant((jlong)$src$$constant); 2573 2574 // Get the constant's TOC offset. 2575 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2576 // Store the toc offset of the constant. 2577 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; 2578 2579 // Also keep the current instruction offset in mind. 2580 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); 2581 } 2582 2583 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2584 %} 2585 2586 %} // encode 2587 2588 source %{ 2589 2590 typedef struct { 2591 loadConL_hiNode *_large_hi; 2592 loadConL_loNode *_large_lo; 2593 loadConLNode *_small; 2594 MachNode *_last; 2595 } loadConLNodesTuple; 2596 2597 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, 2598 OptoReg::Name reg_second, OptoReg::Name reg_first) { 2599 loadConLNodesTuple nodes; 2600 2601 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2602 if (large_constant_pool) { 2603 // Create new nodes. 2604 loadConL_hiNode *m1 = new loadConL_hiNode(); 2605 loadConL_loNode *m2 = new loadConL_loNode(); 2606 2607 // inputs for new nodes 2608 m1->add_req(NULL, toc); 2609 m2->add_req(NULL, m1); 2610 2611 // operands for new nodes 2612 m1->_opnds[0] = new iRegLdstOper(); // dst 2613 m1->_opnds[1] = immSrc; // src 2614 m1->_opnds[2] = new iRegPdstOper(); // toc 2615 m2->_opnds[0] = new iRegLdstOper(); // dst 2616 m2->_opnds[1] = immSrc; // src 2617 m2->_opnds[2] = new iRegLdstOper(); // base 2618 2619 // Initialize ins_attrib TOC fields. 2620 m1->_const_toc_offset = -1; 2621 m2->_const_toc_offset_hi_node = m1; 2622 2623 // Initialize ins_attrib instruction offset. 2624 m1->_cbuf_insts_offset = -1; 2625 2626 // register allocation for new nodes 2627 ra_->set_pair(m1->_idx, reg_second, reg_first); 2628 ra_->set_pair(m2->_idx, reg_second, reg_first); 2629 2630 // Create result. 2631 nodes._large_hi = m1; 2632 nodes._large_lo = m2; 2633 nodes._small = NULL; 2634 nodes._last = nodes._large_lo; 2635 assert(m2->bottom_type()->isa_long(), "must be long"); 2636 } else { 2637 loadConLNode *m2 = new loadConLNode(); 2638 2639 // inputs for new nodes 2640 m2->add_req(NULL, toc); 2641 2642 // operands for new nodes 2643 m2->_opnds[0] = new iRegLdstOper(); // dst 2644 m2->_opnds[1] = immSrc; // src 2645 m2->_opnds[2] = new iRegPdstOper(); // toc 2646 2647 // Initialize ins_attrib instruction offset. 2648 m2->_cbuf_insts_offset = -1; 2649 2650 // register allocation for new nodes 2651 ra_->set_pair(m2->_idx, reg_second, reg_first); 2652 2653 // Create result. 2654 nodes._large_hi = NULL; 2655 nodes._large_lo = NULL; 2656 nodes._small = m2; 2657 nodes._last = nodes._small; 2658 assert(m2->bottom_type()->isa_long(), "must be long"); 2659 } 2660 2661 return nodes; 2662 } 2663 2664 %} // source 2665 2666 encode %{ 2667 // Postalloc expand emitter for loading a long constant from the method's TOC. 2668 // Enc_class needed as consttanttablebase is not supported by postalloc 2669 // expand. 2670 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ 2671 // Create new nodes. 2672 loadConLNodesTuple loadConLNodes = 2673 loadConLNodesTuple_create(ra_, n_toc, op_src, 2674 ra_->get_reg_second(this), ra_->get_reg_first(this)); 2675 2676 // Push new nodes. 2677 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 2678 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 2679 2680 // some asserts 2681 assert(nodes->length() >= 1, "must have created at least 1 node"); 2682 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 2683 %} 2684 2685 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ 2686 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2687 2688 MacroAssembler _masm(&cbuf); 2689 int toc_offset = 0; 2690 2691 if (!ra_->C->in_scratch_emit_size()) { 2692 intptr_t val = $src$$constant; 2693 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2694 address const_toc_addr; 2695 if (constant_reloc == relocInfo::oop_type) { 2696 // Create an oop constant and a corresponding relocation. 2697 AddressLiteral a = __ allocate_oop_address((jobject)val); 2698 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2699 __ relocate(a.rspec()); 2700 } else if (constant_reloc == relocInfo::metadata_type) { 2701 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2702 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2703 __ relocate(a.rspec()); 2704 } else { 2705 // Create a non-oop constant, no relocation needed. 2706 const_toc_addr = __ long_constant((jlong)$src$$constant); 2707 } 2708 2709 // Get the constant's TOC offset. 2710 toc_offset = __ offset_to_method_toc(const_toc_addr); 2711 } 2712 2713 __ ld($dst$$Register, toc_offset, $toc$$Register); 2714 %} 2715 2716 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ 2717 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2718 2719 MacroAssembler _masm(&cbuf); 2720 if (!ra_->C->in_scratch_emit_size()) { 2721 intptr_t val = $src$$constant; 2722 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2723 address const_toc_addr; 2724 if (constant_reloc == relocInfo::oop_type) { 2725 // Create an oop constant and a corresponding relocation. 2726 AddressLiteral a = __ allocate_oop_address((jobject)val); 2727 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2728 __ relocate(a.rspec()); 2729 } else if (constant_reloc == relocInfo::metadata_type) { 2730 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2731 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2732 __ relocate(a.rspec()); 2733 } else { // non-oop pointers, e.g. card mark base, heap top 2734 // Create a non-oop constant, no relocation needed. 2735 const_toc_addr = __ long_constant((jlong)$src$$constant); 2736 } 2737 2738 // Get the constant's TOC offset. 2739 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2740 // Store the toc offset of the constant. 2741 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; 2742 } 2743 2744 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2745 %} 2746 2747 // Postalloc expand emitter for loading a ptr constant from the method's TOC. 2748 // Enc_class needed as consttanttablebase is not supported by postalloc 2749 // expand. 2750 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ 2751 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2752 if (large_constant_pool) { 2753 // Create new nodes. 2754 loadConP_hiNode *m1 = new loadConP_hiNode(); 2755 loadConP_loNode *m2 = new loadConP_loNode(); 2756 2757 // inputs for new nodes 2758 m1->add_req(NULL, n_toc); 2759 m2->add_req(NULL, m1); 2760 2761 // operands for new nodes 2762 m1->_opnds[0] = new iRegPdstOper(); // dst 2763 m1->_opnds[1] = op_src; // src 2764 m1->_opnds[2] = new iRegPdstOper(); // toc 2765 m2->_opnds[0] = new iRegPdstOper(); // dst 2766 m2->_opnds[1] = op_src; // src 2767 m2->_opnds[2] = new iRegLdstOper(); // base 2768 2769 // Initialize ins_attrib TOC fields. 2770 m1->_const_toc_offset = -1; 2771 m2->_const_toc_offset_hi_node = m1; 2772 2773 // Register allocation for new nodes. 2774 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2775 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2776 2777 nodes->push(m1); 2778 nodes->push(m2); 2779 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2780 } else { 2781 loadConPNode *m2 = new loadConPNode(); 2782 2783 // inputs for new nodes 2784 m2->add_req(NULL, n_toc); 2785 2786 // operands for new nodes 2787 m2->_opnds[0] = new iRegPdstOper(); // dst 2788 m2->_opnds[1] = op_src; // src 2789 m2->_opnds[2] = new iRegPdstOper(); // toc 2790 2791 // Register allocation for new nodes. 2792 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2793 2794 nodes->push(m2); 2795 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2796 } 2797 %} 2798 2799 // Enc_class needed as consttanttablebase is not supported by postalloc 2800 // expand. 2801 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ 2802 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2803 2804 MachNode *m2; 2805 if (large_constant_pool) { 2806 m2 = new loadConFCompNode(); 2807 } else { 2808 m2 = new loadConFNode(); 2809 } 2810 // inputs for new nodes 2811 m2->add_req(NULL, n_toc); 2812 2813 // operands for new nodes 2814 m2->_opnds[0] = op_dst; 2815 m2->_opnds[1] = op_src; 2816 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2817 2818 // register allocation for new nodes 2819 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2820 nodes->push(m2); 2821 %} 2822 2823 // Enc_class needed as consttanttablebase is not supported by postalloc 2824 // expand. 2825 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ 2826 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2827 2828 MachNode *m2; 2829 if (large_constant_pool) { 2830 m2 = new loadConDCompNode(); 2831 } else { 2832 m2 = new loadConDNode(); 2833 } 2834 // inputs for new nodes 2835 m2->add_req(NULL, n_toc); 2836 2837 // operands for new nodes 2838 m2->_opnds[0] = op_dst; 2839 m2->_opnds[1] = op_src; 2840 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2841 2842 // register allocation for new nodes 2843 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2844 nodes->push(m2); 2845 %} 2846 2847 enc_class enc_stw(iRegIsrc src, memory mem) %{ 2848 // TODO: PPC port $archOpcode(ppc64Opcode_stw); 2849 MacroAssembler _masm(&cbuf); 2850 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2851 __ stw($src$$Register, Idisp, $mem$$base$$Register); 2852 %} 2853 2854 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ 2855 // TODO: PPC port $archOpcode(ppc64Opcode_std); 2856 MacroAssembler _masm(&cbuf); 2857 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2858 // Operand 'ds' requires 4-alignment. 2859 assert((Idisp & 0x3) == 0, "unaligned offset"); 2860 __ std($src$$Register, Idisp, $mem$$base$$Register); 2861 %} 2862 2863 enc_class enc_stfs(RegF src, memory mem) %{ 2864 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); 2865 MacroAssembler _masm(&cbuf); 2866 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2867 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); 2868 %} 2869 2870 enc_class enc_stfd(RegF src, memory mem) %{ 2871 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); 2872 MacroAssembler _masm(&cbuf); 2873 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2874 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); 2875 %} 2876 2877 // Use release_store for card-marking to ensure that previous 2878 // oop-stores are visible before the card-mark change. 2879 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{ 2880 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2881 // FIXME: Implement this as a cmove and use a fixed condition code 2882 // register which is written on every transition to compiled code, 2883 // e.g. in call-stub and when returning from runtime stubs. 2884 // 2885 // Proposed code sequence for the cmove implementation: 2886 // 2887 // Label skip_release; 2888 // __ beq(CCRfixed, skip_release); 2889 // __ release(); 2890 // __ bind(skip_release); 2891 // __ stb(card mark); 2892 2893 MacroAssembler _masm(&cbuf); 2894 Label skip_storestore; 2895 2896 #if 0 // TODO: PPC port 2897 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the 2898 // StoreStore barrier conditionally. 2899 __ lwz(R0, 0, $releaseFieldAddr$$Register); 2900 __ cmpwi(CCR0, R0, 0); 2901 __ beq_predict_taken(CCR0, skip_storestore); 2902 #endif 2903 __ li(R0, 0); 2904 __ membar(Assembler::StoreStore); 2905 #if 0 // TODO: PPC port 2906 __ bind(skip_storestore); 2907 #endif 2908 2909 // Do the store. 2910 if ($mem$$index == 0) { 2911 __ stb(R0, $mem$$disp, $mem$$base$$Register); 2912 } else { 2913 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); 2914 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); 2915 } 2916 %} 2917 2918 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ 2919 2920 if (VM_Version::has_isel()) { 2921 // use isel instruction with Power 7 2922 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2923 encodeP_subNode *n_sub_base = new encodeP_subNode(); 2924 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2925 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode(); 2926 2927 n_compare->add_req(n_region, n_src); 2928 n_compare->_opnds[0] = op_crx; 2929 n_compare->_opnds[1] = op_src; 2930 n_compare->_opnds[2] = new immL16Oper(0); 2931 2932 n_sub_base->add_req(n_region, n_src); 2933 n_sub_base->_opnds[0] = op_dst; 2934 n_sub_base->_opnds[1] = op_src; 2935 n_sub_base->_bottom_type = _bottom_type; 2936 2937 n_shift->add_req(n_region, n_sub_base); 2938 n_shift->_opnds[0] = op_dst; 2939 n_shift->_opnds[1] = op_dst; 2940 n_shift->_bottom_type = _bottom_type; 2941 2942 n_cond_set->add_req(n_region, n_compare, n_shift); 2943 n_cond_set->_opnds[0] = op_dst; 2944 n_cond_set->_opnds[1] = op_crx; 2945 n_cond_set->_opnds[2] = op_dst; 2946 n_cond_set->_bottom_type = _bottom_type; 2947 2948 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2949 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2950 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2951 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2952 2953 nodes->push(n_compare); 2954 nodes->push(n_sub_base); 2955 nodes->push(n_shift); 2956 nodes->push(n_cond_set); 2957 2958 } else { 2959 // before Power 7 2960 moveRegNode *n_move = new moveRegNode(); 2961 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2962 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2963 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode(); 2964 2965 n_move->add_req(n_region, n_src); 2966 n_move->_opnds[0] = op_dst; 2967 n_move->_opnds[1] = op_src; 2968 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. 2969 2970 n_compare->add_req(n_region, n_src); 2971 n_compare->add_prec(n_move); 2972 2973 n_compare->_opnds[0] = op_crx; 2974 n_compare->_opnds[1] = op_src; 2975 n_compare->_opnds[2] = new immL16Oper(0); 2976 2977 n_sub_base->add_req(n_region, n_compare, n_src); 2978 n_sub_base->_opnds[0] = op_dst; 2979 n_sub_base->_opnds[1] = op_crx; 2980 n_sub_base->_opnds[2] = op_src; 2981 n_sub_base->_bottom_type = _bottom_type; 2982 2983 n_shift->add_req(n_region, n_sub_base); 2984 n_shift->_opnds[0] = op_dst; 2985 n_shift->_opnds[1] = op_dst; 2986 n_shift->_bottom_type = _bottom_type; 2987 2988 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2989 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2990 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2991 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2992 2993 nodes->push(n_move); 2994 nodes->push(n_compare); 2995 nodes->push(n_sub_base); 2996 nodes->push(n_shift); 2997 } 2998 2999 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 3000 %} 3001 3002 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ 3003 3004 encodeP_subNode *n1 = new encodeP_subNode(); 3005 n1->add_req(n_region, n_src); 3006 n1->_opnds[0] = op_dst; 3007 n1->_opnds[1] = op_src; 3008 n1->_bottom_type = _bottom_type; 3009 3010 encodeP_shiftNode *n2 = new encodeP_shiftNode(); 3011 n2->add_req(n_region, n1); 3012 n2->_opnds[0] = op_dst; 3013 n2->_opnds[1] = op_dst; 3014 n2->_bottom_type = _bottom_type; 3015 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3016 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3017 3018 nodes->push(n1); 3019 nodes->push(n2); 3020 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 3021 %} 3022 3023 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 3024 decodeN_shiftNode *n_shift = new decodeN_shiftNode(); 3025 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 3026 3027 n_compare->add_req(n_region, n_src); 3028 n_compare->_opnds[0] = op_crx; 3029 n_compare->_opnds[1] = op_src; 3030 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 3031 3032 n_shift->add_req(n_region, n_src); 3033 n_shift->_opnds[0] = op_dst; 3034 n_shift->_opnds[1] = op_src; 3035 n_shift->_bottom_type = _bottom_type; 3036 3037 if (VM_Version::has_isel()) { 3038 // use isel instruction with Power 7 3039 3040 decodeN_addNode *n_add_base = new decodeN_addNode(); 3041 n_add_base->add_req(n_region, n_shift); 3042 n_add_base->_opnds[0] = op_dst; 3043 n_add_base->_opnds[1] = op_dst; 3044 n_add_base->_bottom_type = _bottom_type; 3045 3046 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 3047 n_cond_set->add_req(n_region, n_compare, n_add_base); 3048 n_cond_set->_opnds[0] = op_dst; 3049 n_cond_set->_opnds[1] = op_crx; 3050 n_cond_set->_opnds[2] = op_dst; 3051 n_cond_set->_bottom_type = _bottom_type; 3052 3053 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3054 ra_->set_oop(n_cond_set, true); 3055 3056 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3057 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 3058 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3059 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3060 3061 nodes->push(n_compare); 3062 nodes->push(n_shift); 3063 nodes->push(n_add_base); 3064 nodes->push(n_cond_set); 3065 3066 } else { 3067 // before Power 7 3068 cond_add_baseNode *n_add_base = new cond_add_baseNode(); 3069 3070 n_add_base->add_req(n_region, n_compare, n_shift); 3071 n_add_base->_opnds[0] = op_dst; 3072 n_add_base->_opnds[1] = op_crx; 3073 n_add_base->_opnds[2] = op_dst; 3074 n_add_base->_bottom_type = _bottom_type; 3075 3076 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3077 ra_->set_oop(n_add_base, true); 3078 3079 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3080 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 3081 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3082 3083 nodes->push(n_compare); 3084 nodes->push(n_shift); 3085 nodes->push(n_add_base); 3086 } 3087 %} 3088 3089 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ 3090 decodeN_shiftNode *n1 = new decodeN_shiftNode(); 3091 n1->add_req(n_region, n_src); 3092 n1->_opnds[0] = op_dst; 3093 n1->_opnds[1] = op_src; 3094 n1->_bottom_type = _bottom_type; 3095 3096 decodeN_addNode *n2 = new decodeN_addNode(); 3097 n2->add_req(n_region, n1); 3098 n2->_opnds[0] = op_dst; 3099 n2->_opnds[1] = op_dst; 3100 n2->_bottom_type = _bottom_type; 3101 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3102 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3103 3104 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3105 ra_->set_oop(n2, true); 3106 3107 nodes->push(n1); 3108 nodes->push(n2); 3109 %} 3110 3111 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{ 3112 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3113 3114 MacroAssembler _masm(&cbuf); 3115 int cc = $cmp$$cmpcode; 3116 int flags_reg = $crx$$reg; 3117 Label done; 3118 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3119 // Branch if not (cmp crx). 3120 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); 3121 __ mr($dst$$Register, $src$$Register); 3122 // TODO PPC port __ endgroup_if_needed(_size == 12); 3123 __ bind(done); 3124 %} 3125 3126 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{ 3127 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3128 3129 MacroAssembler _masm(&cbuf); 3130 Label done; 3131 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3132 // Branch if not (cmp crx). 3133 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 3134 __ li($dst$$Register, $src$$constant); 3135 // TODO PPC port __ endgroup_if_needed(_size == 12); 3136 __ bind(done); 3137 %} 3138 3139 // New atomics. 3140 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3141 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3142 3143 MacroAssembler _masm(&cbuf); 3144 Register Rtmp = R0; 3145 Register Rres = $res$$Register; 3146 Register Rsrc = $src$$Register; 3147 Register Rptr = $mem_ptr$$Register; 3148 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3149 Register Rold = RegCollision ? Rtmp : Rres; 3150 3151 Label Lretry; 3152 __ bind(Lretry); 3153 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3154 __ add(Rtmp, Rsrc, Rold); 3155 __ stwcx_(Rtmp, Rptr); 3156 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3157 __ bne_predict_not_taken(CCR0, Lretry); 3158 } else { 3159 __ bne( CCR0, Lretry); 3160 } 3161 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3162 __ fence(); 3163 %} 3164 3165 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3166 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3167 3168 MacroAssembler _masm(&cbuf); 3169 Register Rtmp = R0; 3170 Register Rres = $res$$Register; 3171 Register Rsrc = $src$$Register; 3172 Register Rptr = $mem_ptr$$Register; 3173 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3174 Register Rold = RegCollision ? Rtmp : Rres; 3175 3176 Label Lretry; 3177 __ bind(Lretry); 3178 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3179 __ add(Rtmp, Rsrc, Rold); 3180 __ stdcx_(Rtmp, Rptr); 3181 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3182 __ bne_predict_not_taken(CCR0, Lretry); 3183 } else { 3184 __ bne( CCR0, Lretry); 3185 } 3186 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3187 __ fence(); 3188 %} 3189 3190 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3191 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3192 3193 MacroAssembler _masm(&cbuf); 3194 Register Rtmp = R0; 3195 Register Rres = $res$$Register; 3196 Register Rsrc = $src$$Register; 3197 Register Rptr = $mem_ptr$$Register; 3198 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3199 Register Rold = RegCollision ? Rtmp : Rres; 3200 3201 Label Lretry; 3202 __ bind(Lretry); 3203 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3204 __ stwcx_(Rsrc, Rptr); 3205 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3206 __ bne_predict_not_taken(CCR0, Lretry); 3207 } else { 3208 __ bne( CCR0, Lretry); 3209 } 3210 if (RegCollision) __ mr(Rres, Rtmp); 3211 __ fence(); 3212 %} 3213 3214 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3215 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3216 3217 MacroAssembler _masm(&cbuf); 3218 Register Rtmp = R0; 3219 Register Rres = $res$$Register; 3220 Register Rsrc = $src$$Register; 3221 Register Rptr = $mem_ptr$$Register; 3222 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3223 Register Rold = RegCollision ? Rtmp : Rres; 3224 3225 Label Lretry; 3226 __ bind(Lretry); 3227 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3228 __ stdcx_(Rsrc, Rptr); 3229 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3230 __ bne_predict_not_taken(CCR0, Lretry); 3231 } else { 3232 __ bne( CCR0, Lretry); 3233 } 3234 if (RegCollision) __ mr(Rres, Rtmp); 3235 __ fence(); 3236 %} 3237 3238 // This enc_class is needed so that scheduler gets proper 3239 // input mapping for latency computation. 3240 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 3241 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 3242 MacroAssembler _masm(&cbuf); 3243 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 3244 %} 3245 3246 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3247 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3248 3249 MacroAssembler _masm(&cbuf); 3250 3251 Label done; 3252 __ cmpwi($crx$$CondRegister, $src$$Register, 0); 3253 __ li($dst$$Register, $zero$$constant); 3254 __ beq($crx$$CondRegister, done); 3255 __ li($dst$$Register, $notzero$$constant); 3256 __ bind(done); 3257 %} 3258 3259 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3260 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3261 3262 MacroAssembler _masm(&cbuf); 3263 3264 Label done; 3265 __ cmpdi($crx$$CondRegister, $src$$Register, 0); 3266 __ li($dst$$Register, $zero$$constant); 3267 __ beq($crx$$CondRegister, done); 3268 __ li($dst$$Register, $notzero$$constant); 3269 __ bind(done); 3270 %} 3271 3272 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{ 3273 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3274 3275 MacroAssembler _masm(&cbuf); 3276 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 3277 Label done; 3278 __ bso($crx$$CondRegister, done); 3279 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 3280 // TODO PPC port __ endgroup_if_needed(_size == 12); 3281 __ bind(done); 3282 %} 3283 3284 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{ 3285 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3286 3287 MacroAssembler _masm(&cbuf); 3288 Label d; // dummy 3289 __ bind(d); 3290 Label* p = ($lbl$$label); 3291 // `p' is `NULL' when this encoding class is used only to 3292 // determine the size of the encoded instruction. 3293 Label& l = (NULL == p)? d : *(p); 3294 int cc = $cmp$$cmpcode; 3295 int flags_reg = $crx$$reg; 3296 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3297 int bhint = Assembler::bhintNoHint; 3298 3299 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3300 if (_prob <= PROB_NEVER) { 3301 bhint = Assembler::bhintIsNotTaken; 3302 } else if (_prob >= PROB_ALWAYS) { 3303 bhint = Assembler::bhintIsTaken; 3304 } 3305 } 3306 3307 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3308 cc_to_biint(cc, flags_reg), 3309 l); 3310 %} 3311 3312 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{ 3313 // The scheduler doesn't know about branch shortening, so we set the opcode 3314 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3315 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3316 3317 MacroAssembler _masm(&cbuf); 3318 Label d; // dummy 3319 __ bind(d); 3320 Label* p = ($lbl$$label); 3321 // `p' is `NULL' when this encoding class is used only to 3322 // determine the size of the encoded instruction. 3323 Label& l = (NULL == p)? d : *(p); 3324 int cc = $cmp$$cmpcode; 3325 int flags_reg = $crx$$reg; 3326 int bhint = Assembler::bhintNoHint; 3327 3328 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3329 if (_prob <= PROB_NEVER) { 3330 bhint = Assembler::bhintIsNotTaken; 3331 } else if (_prob >= PROB_ALWAYS) { 3332 bhint = Assembler::bhintIsTaken; 3333 } 3334 } 3335 3336 // Tell the conditional far branch to optimize itself when being relocated. 3337 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3338 cc_to_biint(cc, flags_reg), 3339 l, 3340 MacroAssembler::bc_far_optimize_on_relocate); 3341 %} 3342 3343 // Branch used with Power6 scheduling (can be shortened without changing the node). 3344 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{ 3345 // The scheduler doesn't know about branch shortening, so we set the opcode 3346 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3347 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3348 3349 MacroAssembler _masm(&cbuf); 3350 Label d; // dummy 3351 __ bind(d); 3352 Label* p = ($lbl$$label); 3353 // `p' is `NULL' when this encoding class is used only to 3354 // determine the size of the encoded instruction. 3355 Label& l = (NULL == p)? d : *(p); 3356 int cc = $cmp$$cmpcode; 3357 int flags_reg = $crx$$reg; 3358 int bhint = Assembler::bhintNoHint; 3359 3360 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3361 if (_prob <= PROB_NEVER) { 3362 bhint = Assembler::bhintIsNotTaken; 3363 } else if (_prob >= PROB_ALWAYS) { 3364 bhint = Assembler::bhintIsTaken; 3365 } 3366 } 3367 3368 #if 0 // TODO: PPC port 3369 if (_size == 8) { 3370 // Tell the conditional far branch to optimize itself when being relocated. 3371 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3372 cc_to_biint(cc, flags_reg), 3373 l, 3374 MacroAssembler::bc_far_optimize_on_relocate); 3375 } else { 3376 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3377 cc_to_biint(cc, flags_reg), 3378 l); 3379 } 3380 #endif 3381 Unimplemented(); 3382 %} 3383 3384 // Postalloc expand emitter for loading a replicatef float constant from 3385 // the method's TOC. 3386 // Enc_class needed as consttanttablebase is not supported by postalloc 3387 // expand. 3388 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ 3389 // Create new nodes. 3390 3391 // Make an operand with the bit pattern to load as float. 3392 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF())); 3393 3394 loadConLNodesTuple loadConLNodes = 3395 loadConLNodesTuple_create(ra_, n_toc, op_repl, 3396 ra_->get_reg_second(this), ra_->get_reg_first(this)); 3397 3398 // Push new nodes. 3399 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 3400 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 3401 3402 assert(nodes->length() >= 1, "must have created at least 1 node"); 3403 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 3404 %} 3405 3406 // This enc_class is needed so that scheduler gets proper 3407 // input mapping for latency computation. 3408 enc_class enc_poll(immI dst, iRegLdst poll) %{ 3409 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 3410 // Fake operand dst needed for PPC scheduler. 3411 assert($dst$$constant == 0x0, "dst must be 0x0"); 3412 3413 MacroAssembler _masm(&cbuf); 3414 // Mark the code position where the load from the safepoint 3415 // polling page was emitted as relocInfo::poll_type. 3416 __ relocate(relocInfo::poll_type); 3417 __ load_from_polling_page($poll$$Register); 3418 %} 3419 3420 // A Java static call or a runtime call. 3421 // 3422 // Branch-and-link relative to a trampoline. 3423 // The trampoline loads the target address and does a long branch to there. 3424 // In case we call java, the trampoline branches to a interpreter_stub 3425 // which loads the inline cache and the real call target from the constant pool. 3426 // 3427 // This basically looks like this: 3428 // 3429 // >>>> consts -+ -+ 3430 // | |- offset1 3431 // [call target1] | <-+ 3432 // [IC cache] |- offset2 3433 // [call target2] <--+ 3434 // 3435 // <<<< consts 3436 // >>>> insts 3437 // 3438 // bl offset16 -+ -+ ??? // How many bits available? 3439 // | | 3440 // <<<< insts | | 3441 // >>>> stubs | | 3442 // | |- trampoline_stub_Reloc 3443 // trampoline stub: | <-+ 3444 // r2 = toc | 3445 // r2 = [r2 + offset1] | // Load call target1 from const section 3446 // mtctr r2 | 3447 // bctr |- static_stub_Reloc 3448 // comp_to_interp_stub: <---+ 3449 // r1 = toc 3450 // ICreg = [r1 + IC_offset] // Load IC from const section 3451 // r1 = [r1 + offset2] // Load call target2 from const section 3452 // mtctr r1 3453 // bctr 3454 // 3455 // <<<< stubs 3456 // 3457 // The call instruction in the code either 3458 // - Branches directly to a compiled method if the offset is encodable in instruction. 3459 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. 3460 // - Branches to the compiled_to_interp stub if the target is interpreted. 3461 // 3462 // Further there are three relocations from the loads to the constants in 3463 // the constant section. 3464 // 3465 // Usage of r1 and r2 in the stubs allows to distinguish them. 3466 enc_class enc_java_static_call(method meth) %{ 3467 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3468 3469 MacroAssembler _masm(&cbuf); 3470 address entry_point = (address)$meth$$method; 3471 3472 if (!_method) { 3473 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. 3474 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); 3475 } else { 3476 // Remember the offset not the address. 3477 const int start_offset = __ offset(); 3478 // The trampoline stub. 3479 if (!Compile::current()->in_scratch_emit_size()) { 3480 // No entry point given, use the current pc. 3481 // Make sure branch fits into 3482 if (entry_point == 0) entry_point = __ pc(); 3483 3484 // Put the entry point as a constant into the constant pool. 3485 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3486 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3487 3488 // Emit the trampoline stub which will be related to the branch-and-link below. 3489 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3490 if (Compile::current()->env()->failing()) { return; } // Code cache may be full. 3491 __ relocate(_optimized_virtual ? 3492 relocInfo::opt_virtual_call_type : relocInfo::static_call_type); 3493 } 3494 3495 // The real call. 3496 // Note: At this point we do not have the address of the trampoline 3497 // stub, and the entry point might be too far away for bl, so __ pc() 3498 // serves as dummy and the bl will be patched later. 3499 cbuf.set_insts_mark(); 3500 __ bl(__ pc()); // Emits a relocation. 3501 3502 // The stub for call to interpreter. 3503 CompiledStaticCall::emit_to_interp_stub(cbuf); 3504 } 3505 %} 3506 3507 // Emit a method handle call. 3508 // 3509 // Method handle calls from compiled to compiled are going thru a 3510 // c2i -> i2c adapter, extending the frame for their arguments. The 3511 // caller however, returns directly to the compiled callee, that has 3512 // to cope with the extended frame. We restore the original frame by 3513 // loading the callers sp and adding the calculated framesize. 3514 enc_class enc_java_handle_call(method meth) %{ 3515 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3516 3517 MacroAssembler _masm(&cbuf); 3518 address entry_point = (address)$meth$$method; 3519 3520 // Remember the offset not the address. 3521 const int start_offset = __ offset(); 3522 // The trampoline stub. 3523 if (!ra_->C->in_scratch_emit_size()) { 3524 // No entry point given, use the current pc. 3525 // Make sure branch fits into 3526 if (entry_point == 0) entry_point = __ pc(); 3527 3528 // Put the entry point as a constant into the constant pool. 3529 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3530 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3531 3532 // Emit the trampoline stub which will be related to the branch-and-link below. 3533 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3534 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3535 assert(_optimized_virtual, "methodHandle call should be a virtual call"); 3536 __ relocate(relocInfo::opt_virtual_call_type); 3537 } 3538 3539 // The real call. 3540 // Note: At this point we do not have the address of the trampoline 3541 // stub, and the entry point might be too far away for bl, so __ pc() 3542 // serves as dummy and the bl will be patched later. 3543 cbuf.set_insts_mark(); 3544 __ bl(__ pc()); // Emits a relocation. 3545 3546 assert(_method, "execute next statement conditionally"); 3547 // The stub for call to interpreter. 3548 CompiledStaticCall::emit_to_interp_stub(cbuf); 3549 3550 // Restore original sp. 3551 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp. 3552 const long framesize = ra_->C->frame_slots() << LogBytesPerInt; 3553 unsigned int bytes = (unsigned int)framesize; 3554 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 3555 if (Assembler::is_simm(-offset, 16)) { 3556 __ addi(R1_SP, R11_scratch1, -offset); 3557 } else { 3558 __ load_const_optimized(R12_scratch2, -offset); 3559 __ add(R1_SP, R11_scratch1, R12_scratch2); 3560 } 3561 #ifdef ASSERT 3562 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp. 3563 __ cmpd(CCR0, R11_scratch1, R12_scratch2); 3564 __ asm_assert_eq("backlink changed", 0x8000); 3565 #endif 3566 // If fails should store backlink before unextending. 3567 3568 if (ra_->C->env()->failing()) { 3569 return; 3570 } 3571 %} 3572 3573 // Second node of expanded dynamic call - the call. 3574 enc_class enc_java_dynamic_call_sched(method meth) %{ 3575 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3576 3577 MacroAssembler _masm(&cbuf); 3578 3579 if (!ra_->C->in_scratch_emit_size()) { 3580 // Create a call trampoline stub for the given method. 3581 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; 3582 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 3583 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 3584 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 3585 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3586 3587 // Build relocation at call site with ic position as data. 3588 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 3589 (_load_ic_hi_node == NULL && _load_ic_node != NULL), 3590 "must have one, but can't have both"); 3591 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || 3592 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), 3593 "must contain instruction offset"); 3594 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL 3595 ? _load_ic_hi_node->_cbuf_insts_offset 3596 : _load_ic_node->_cbuf_insts_offset; 3597 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); 3598 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), 3599 "should be load from TOC"); 3600 3601 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 3602 } 3603 3604 // At this point I do not have the address of the trampoline stub, 3605 // and the entry point might be too far away for bl. Pc() serves 3606 // as dummy and bl will be patched later. 3607 __ bl((address) __ pc()); 3608 %} 3609 3610 // postalloc expand emitter for virtual calls. 3611 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ 3612 3613 // Create the nodes for loading the IC from the TOC. 3614 loadConLNodesTuple loadConLNodes_IC = 3615 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()), 3616 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); 3617 3618 // Create the call node. 3619 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode(); 3620 call->_method_handle_invoke = _method_handle_invoke; 3621 call->_vtable_index = _vtable_index; 3622 call->_method = _method; 3623 call->_bci = _bci; 3624 call->_optimized_virtual = _optimized_virtual; 3625 call->_tf = _tf; 3626 call->_entry_point = _entry_point; 3627 call->_cnt = _cnt; 3628 call->_argsize = _argsize; 3629 call->_oop_map = _oop_map; 3630 call->_jvms = _jvms; 3631 call->_jvmadj = _jvmadj; 3632 call->_in_rms = _in_rms; 3633 call->_nesting = _nesting; 3634 3635 // New call needs all inputs of old call. 3636 // Req... 3637 for (uint i = 0; i < req(); ++i) { 3638 // The expanded node does not need toc any more. 3639 // Add the inline cache constant here instead. This expresses the 3640 // register of the inline cache must be live at the call. 3641 // Else we would have to adapt JVMState by -1. 3642 if (i == mach_constant_base_node_input()) { 3643 call->add_req(loadConLNodes_IC._last); 3644 } else { 3645 call->add_req(in(i)); 3646 } 3647 } 3648 // ...as well as prec 3649 for (uint i = req(); i < len(); ++i) { 3650 call->add_prec(in(i)); 3651 } 3652 3653 // Remember nodes loading the inline cache into r19. 3654 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; 3655 call->_load_ic_node = loadConLNodes_IC._small; 3656 3657 // Operands for new nodes. 3658 call->_opnds[0] = _opnds[0]; 3659 call->_opnds[1] = _opnds[1]; 3660 3661 // Only the inline cache is associated with a register. 3662 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); 3663 3664 // Push new nodes. 3665 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); 3666 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); 3667 nodes->push(call); 3668 %} 3669 3670 // Compound version of call dynamic 3671 // Toc is only passed so that it can be used in ins_encode statement. 3672 // In the code we have to use $constanttablebase. 3673 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 3674 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3675 MacroAssembler _masm(&cbuf); 3676 int start_offset = __ offset(); 3677 3678 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 3679 #if 0 3680 int vtable_index = this->_vtable_index; 3681 if (_vtable_index < 0) { 3682 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 3683 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 3684 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 3685 3686 // Virtual call relocation will point to ic load. 3687 address virtual_call_meta_addr = __ pc(); 3688 // Load a clear inline cache. 3689 AddressLiteral empty_ic((address) Universe::non_oop_word()); 3690 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc); 3691 // CALL to fixup routine. Fixup routine uses ScopeDesc info 3692 // to determine who we intended to call. 3693 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 3694 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); 3695 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3696 "Fix constant in ret_addr_offset()"); 3697 } else { 3698 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 3699 // Go thru the vtable. Get receiver klass. Receiver already 3700 // checked for non-null. If we'll go thru a C2I adapter, the 3701 // interpreter expects method in R19_method. 3702 3703 __ load_klass(R11_scratch1, R3); 3704 3705 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); 3706 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); 3707 __ li(R19_method, v_off); 3708 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); 3709 // NOTE: for vtable dispatches, the vtable entry will never be 3710 // null. However it may very well end up in handle_wrong_method 3711 // if the method is abstract for the particular class. 3712 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); 3713 // Call target. Either compiled code or C2I adapter. 3714 __ mtctr(R11_scratch1); 3715 __ bctrl(); 3716 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { 3717 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); 3718 } 3719 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3720 "Fix constant in ret_addr_offset()"); 3721 } 3722 #endif 3723 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 3724 %} 3725 3726 // a runtime call 3727 enc_class enc_java_to_runtime_call (method meth) %{ 3728 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3729 3730 MacroAssembler _masm(&cbuf); 3731 const address start_pc = __ pc(); 3732 3733 #if defined(ABI_ELFv2) 3734 address entry= !($meth$$method) ? NULL : (address)$meth$$method; 3735 __ call_c(entry, relocInfo::runtime_call_type); 3736 #else 3737 // The function we're going to call. 3738 FunctionDescriptor fdtemp; 3739 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; 3740 3741 Register Rtoc = R12_scratch2; 3742 // Calculate the method's TOC. 3743 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); 3744 // Put entry, env, toc into the constant pool, this needs up to 3 constant 3745 // pool entries; call_c_using_toc will optimize the call. 3746 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); 3747 #endif 3748 3749 // Check the ret_addr_offset. 3750 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, 3751 "Fix constant in ret_addr_offset()"); 3752 %} 3753 3754 // Move to ctr for leaf call. 3755 // This enc_class is needed so that scheduler gets proper 3756 // input mapping for latency computation. 3757 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ 3758 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); 3759 MacroAssembler _masm(&cbuf); 3760 __ mtctr($src$$Register); 3761 %} 3762 3763 // Postalloc expand emitter for runtime leaf calls. 3764 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ 3765 loadConLNodesTuple loadConLNodes_Entry; 3766 #if defined(ABI_ELFv2) 3767 jlong entry_address = (jlong) this->entry_point(); 3768 assert(entry_address, "need address here"); 3769 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3770 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3771 #else 3772 // Get the struct that describes the function we are about to call. 3773 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); 3774 assert(fd, "need fd here"); 3775 jlong entry_address = (jlong) fd->entry(); 3776 // new nodes 3777 loadConLNodesTuple loadConLNodes_Env; 3778 loadConLNodesTuple loadConLNodes_Toc; 3779 3780 // Create nodes and operands for loading the entry point. 3781 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3782 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3783 3784 3785 // Create nodes and operands for loading the env pointer. 3786 if (fd->env() != NULL) { 3787 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()), 3788 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3789 } else { 3790 loadConLNodes_Env._large_hi = NULL; 3791 loadConLNodes_Env._large_lo = NULL; 3792 loadConLNodes_Env._small = NULL; 3793 loadConLNodes_Env._last = new loadConL16Node(); 3794 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper(); 3795 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0); 3796 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3797 } 3798 3799 // Create nodes and operands for loading the Toc point. 3800 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()), 3801 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); 3802 #endif // ABI_ELFv2 3803 // mtctr node 3804 MachNode *mtctr = new CallLeafDirect_mtctrNode(); 3805 3806 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); 3807 mtctr->add_req(0, loadConLNodes_Entry._last); 3808 3809 mtctr->_opnds[0] = new iRegLdstOper(); 3810 mtctr->_opnds[1] = new iRegLdstOper(); 3811 3812 // call node 3813 MachCallLeafNode *call = new CallLeafDirectNode(); 3814 3815 call->_opnds[0] = _opnds[0]; 3816 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later. 3817 3818 // Make the new call node look like the old one. 3819 call->_name = _name; 3820 call->_tf = _tf; 3821 call->_entry_point = _entry_point; 3822 call->_cnt = _cnt; 3823 call->_argsize = _argsize; 3824 call->_oop_map = _oop_map; 3825 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); 3826 call->_jvms = NULL; 3827 call->_jvmadj = _jvmadj; 3828 call->_in_rms = _in_rms; 3829 call->_nesting = _nesting; 3830 3831 3832 // New call needs all inputs of old call. 3833 // Req... 3834 for (uint i = 0; i < req(); ++i) { 3835 if (i != mach_constant_base_node_input()) { 3836 call->add_req(in(i)); 3837 } 3838 } 3839 3840 // These must be reqired edges, as the registers are live up to 3841 // the call. Else the constants are handled as kills. 3842 call->add_req(mtctr); 3843 #if !defined(ABI_ELFv2) 3844 call->add_req(loadConLNodes_Env._last); 3845 call->add_req(loadConLNodes_Toc._last); 3846 #endif 3847 3848 // ...as well as prec 3849 for (uint i = req(); i < len(); ++i) { 3850 call->add_prec(in(i)); 3851 } 3852 3853 // registers 3854 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); 3855 3856 // Insert the new nodes. 3857 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); 3858 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); 3859 #if !defined(ABI_ELFv2) 3860 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); 3861 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); 3862 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); 3863 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); 3864 #endif 3865 nodes->push(mtctr); 3866 nodes->push(call); 3867 %} 3868 %} 3869 3870 //----------FRAME-------------------------------------------------------------- 3871 // Definition of frame structure and management information. 3872 3873 frame %{ 3874 // What direction does stack grow in (assumed to be same for native & Java). 3875 stack_direction(TOWARDS_LOW); 3876 3877 // These two registers define part of the calling convention between 3878 // compiled code and the interpreter. 3879 3880 // Inline Cache Register or method for I2C. 3881 inline_cache_reg(R19); // R19_method 3882 3883 // Method Oop Register when calling interpreter. 3884 interpreter_method_oop_reg(R19); // R19_method 3885 3886 // Optional: name the operand used by cisc-spilling to access 3887 // [stack_pointer + offset]. 3888 cisc_spilling_operand_name(indOffset); 3889 3890 // Number of stack slots consumed by a Monitor enter. 3891 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); 3892 3893 // Compiled code's Frame Pointer. 3894 frame_pointer(R1); // R1_SP 3895 3896 // Interpreter stores its frame pointer in a register which is 3897 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 3898 // interpreted java to compiled java. 3899 // 3900 // R14_state holds pointer to caller's cInterpreter. 3901 interpreter_frame_pointer(R14); // R14_state 3902 3903 stack_alignment(frame::alignment_in_bytes); 3904 3905 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); 3906 3907 // Number of outgoing stack slots killed above the 3908 // out_preserve_stack_slots for calls to C. Supports the var-args 3909 // backing area for register parms. 3910 // 3911 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 3912 3913 // The after-PROLOG location of the return address. Location of 3914 // return address specifies a type (REG or STACK) and a number 3915 // representing the register number (i.e. - use a register name) or 3916 // stack slot. 3917 // 3918 // A: Link register is stored in stack slot ... 3919 // M: ... but it's in the caller's frame according to PPC-64 ABI. 3920 // J: Therefore, we make sure that the link register is also in R11_scratch1 3921 // at the end of the prolog. 3922 // B: We use R20, now. 3923 //return_addr(REG R20); 3924 3925 // G: After reading the comments made by all the luminaries on their 3926 // failure to tell the compiler where the return address really is, 3927 // I hardly dare to try myself. However, I'm convinced it's in slot 3928 // 4 what apparently works and saves us some spills. 3929 return_addr(STACK 4); 3930 3931 // This is the body of the function 3932 // 3933 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs 3934 // uint length, // length of array 3935 // bool is_outgoing) 3936 // 3937 // The `sig' array is to be updated. sig[j] represents the location 3938 // of the j-th argument, either a register or a stack slot. 3939 3940 // Comment taken from i486.ad: 3941 // Body of function which returns an integer array locating 3942 // arguments either in registers or in stack slots. Passed an array 3943 // of ideal registers called "sig" and a "length" count. Stack-slot 3944 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3945 // arguments for a CALLEE. Incoming stack arguments are 3946 // automatically biased by the preserve_stack_slots field above. 3947 calling_convention %{ 3948 // No difference between ingoing/outgoing. Just pass false. 3949 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3950 %} 3951 3952 // Comment taken from i486.ad: 3953 // Body of function which returns an integer array locating 3954 // arguments either in registers or in stack slots. Passed an array 3955 // of ideal registers called "sig" and a "length" count. Stack-slot 3956 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3957 // arguments for a CALLEE. Incoming stack arguments are 3958 // automatically biased by the preserve_stack_slots field above. 3959 c_calling_convention %{ 3960 // This is obviously always outgoing. 3961 // C argument in register AND stack slot. 3962 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3963 %} 3964 3965 // Location of native (C/C++) and interpreter return values. This 3966 // is specified to be the same as Java. In the 32-bit VM, long 3967 // values are actually returned from native calls in O0:O1 and 3968 // returned to the interpreter in I0:I1. The copying to and from 3969 // the register pairs is done by the appropriate call and epilog 3970 // opcodes. This simplifies the register allocator. 3971 c_return_value %{ 3972 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3973 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3974 "only return normal values"); 3975 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3976 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3977 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3978 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3979 %} 3980 3981 // Location of compiled Java return values. Same as C 3982 return_value %{ 3983 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3984 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3985 "only return normal values"); 3986 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3987 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3988 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3989 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3990 %} 3991 %} 3992 3993 3994 //----------ATTRIBUTES--------------------------------------------------------- 3995 3996 //----------Operand Attributes------------------------------------------------- 3997 op_attrib op_cost(1); // Required cost attribute. 3998 3999 //----------Instruction Attributes--------------------------------------------- 4000 4001 // Cost attribute. required. 4002 ins_attrib ins_cost(DEFAULT_COST); 4003 4004 // Is this instruction a non-matching short branch variant of some 4005 // long branch? Not required. 4006 ins_attrib ins_short_branch(0); 4007 4008 ins_attrib ins_is_TrapBasedCheckNode(true); 4009 4010 // Number of constants. 4011 // This instruction uses the given number of constants 4012 // (optional attribute). 4013 // This is needed to determine in time whether the constant pool will 4014 // exceed 4000 entries. Before postalloc_expand the overall number of constants 4015 // is determined. It's also used to compute the constant pool size 4016 // in Output(). 4017 ins_attrib ins_num_consts(0); 4018 4019 // Required alignment attribute (must be a power of 2) specifies the 4020 // alignment that some part of the instruction (not necessarily the 4021 // start) requires. If > 1, a compute_padding() function must be 4022 // provided for the instruction. 4023 ins_attrib ins_alignment(1); 4024 4025 // Enforce/prohibit rematerializations. 4026 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 4027 // then rematerialization of that instruction is prohibited and the 4028 // instruction's value will be spilled if necessary. 4029 // Causes that MachNode::rematerialize() returns false. 4030 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 4031 // then rematerialization should be enforced and a copy of the instruction 4032 // should be inserted if possible; rematerialization is not guaranteed. 4033 // Note: this may result in rematerializations in front of every use. 4034 // Causes that MachNode::rematerialize() can return true. 4035 // (optional attribute) 4036 ins_attrib ins_cannot_rematerialize(false); 4037 ins_attrib ins_should_rematerialize(false); 4038 4039 // Instruction has variable size depending on alignment. 4040 ins_attrib ins_variable_size_depending_on_alignment(false); 4041 4042 // Instruction is a nop. 4043 ins_attrib ins_is_nop(false); 4044 4045 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). 4046 ins_attrib ins_use_mach_if_fast_lock_node(false); 4047 4048 // Field for the toc offset of a constant. 4049 // 4050 // This is needed if the toc offset is not encodable as an immediate in 4051 // the PPC load instruction. If so, the upper (hi) bits of the offset are 4052 // added to the toc, and from this a load with immediate is performed. 4053 // With postalloc expand, we get two nodes that require the same offset 4054 // but which don't know about each other. The offset is only known 4055 // when the constant is added to the constant pool during emitting. 4056 // It is generated in the 'hi'-node adding the upper bits, and saved 4057 // in this node. The 'lo'-node has a link to the 'hi'-node and reads 4058 // the offset from there when it gets encoded. 4059 ins_attrib ins_field_const_toc_offset(0); 4060 ins_attrib ins_field_const_toc_offset_hi_node(0); 4061 4062 // A field that can hold the instructions offset in the code buffer. 4063 // Set in the nodes emitter. 4064 ins_attrib ins_field_cbuf_insts_offset(-1); 4065 4066 // Fields for referencing a call's load-IC-node. 4067 // If the toc offset can not be encoded as an immediate in a load, we 4068 // use two nodes. 4069 ins_attrib ins_field_load_ic_hi_node(0); 4070 ins_attrib ins_field_load_ic_node(0); 4071 4072 //----------OPERANDS----------------------------------------------------------- 4073 // Operand definitions must precede instruction definitions for correct 4074 // parsing in the ADLC because operands constitute user defined types 4075 // which are used in instruction definitions. 4076 // 4077 // Formats are generated automatically for constants and base registers. 4078 4079 //----------Simple Operands---------------------------------------------------- 4080 // Immediate Operands 4081 4082 // Integer Immediate: 32-bit 4083 operand immI() %{ 4084 match(ConI); 4085 op_cost(40); 4086 format %{ %} 4087 interface(CONST_INTER); 4088 %} 4089 4090 operand immI8() %{ 4091 predicate(Assembler::is_simm(n->get_int(), 8)); 4092 op_cost(0); 4093 match(ConI); 4094 format %{ %} 4095 interface(CONST_INTER); 4096 %} 4097 4098 // Integer Immediate: 16-bit 4099 operand immI16() %{ 4100 predicate(Assembler::is_simm(n->get_int(), 16)); 4101 op_cost(0); 4102 match(ConI); 4103 format %{ %} 4104 interface(CONST_INTER); 4105 %} 4106 4107 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. 4108 operand immIhi16() %{ 4109 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); 4110 match(ConI); 4111 op_cost(0); 4112 format %{ %} 4113 interface(CONST_INTER); 4114 %} 4115 4116 operand immInegpow2() %{ 4117 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); 4118 match(ConI); 4119 op_cost(0); 4120 format %{ %} 4121 interface(CONST_INTER); 4122 %} 4123 4124 operand immIpow2minus1() %{ 4125 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); 4126 match(ConI); 4127 op_cost(0); 4128 format %{ %} 4129 interface(CONST_INTER); 4130 %} 4131 4132 operand immIpowerOf2() %{ 4133 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); 4134 match(ConI); 4135 op_cost(0); 4136 format %{ %} 4137 interface(CONST_INTER); 4138 %} 4139 4140 // Unsigned Integer Immediate: the values 0-31 4141 operand uimmI5() %{ 4142 predicate(Assembler::is_uimm(n->get_int(), 5)); 4143 match(ConI); 4144 op_cost(0); 4145 format %{ %} 4146 interface(CONST_INTER); 4147 %} 4148 4149 // Unsigned Integer Immediate: 6-bit 4150 operand uimmI6() %{ 4151 predicate(Assembler::is_uimm(n->get_int(), 6)); 4152 match(ConI); 4153 op_cost(0); 4154 format %{ %} 4155 interface(CONST_INTER); 4156 %} 4157 4158 // Unsigned Integer Immediate: 6-bit int, greater than 32 4159 operand uimmI6_ge32() %{ 4160 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); 4161 match(ConI); 4162 op_cost(0); 4163 format %{ %} 4164 interface(CONST_INTER); 4165 %} 4166 4167 // Unsigned Integer Immediate: 15-bit 4168 operand uimmI15() %{ 4169 predicate(Assembler::is_uimm(n->get_int(), 15)); 4170 match(ConI); 4171 op_cost(0); 4172 format %{ %} 4173 interface(CONST_INTER); 4174 %} 4175 4176 // Unsigned Integer Immediate: 16-bit 4177 operand uimmI16() %{ 4178 predicate(Assembler::is_uimm(n->get_int(), 16)); 4179 match(ConI); 4180 op_cost(0); 4181 format %{ %} 4182 interface(CONST_INTER); 4183 %} 4184 4185 // constant 'int 0'. 4186 operand immI_0() %{ 4187 predicate(n->get_int() == 0); 4188 match(ConI); 4189 op_cost(0); 4190 format %{ %} 4191 interface(CONST_INTER); 4192 %} 4193 4194 // constant 'int 1'. 4195 operand immI_1() %{ 4196 predicate(n->get_int() == 1); 4197 match(ConI); 4198 op_cost(0); 4199 format %{ %} 4200 interface(CONST_INTER); 4201 %} 4202 4203 // constant 'int -1'. 4204 operand immI_minus1() %{ 4205 predicate(n->get_int() == -1); 4206 match(ConI); 4207 op_cost(0); 4208 format %{ %} 4209 interface(CONST_INTER); 4210 %} 4211 4212 // int value 16. 4213 operand immI_16() %{ 4214 predicate(n->get_int() == 16); 4215 match(ConI); 4216 op_cost(0); 4217 format %{ %} 4218 interface(CONST_INTER); 4219 %} 4220 4221 // int value 24. 4222 operand immI_24() %{ 4223 predicate(n->get_int() == 24); 4224 match(ConI); 4225 op_cost(0); 4226 format %{ %} 4227 interface(CONST_INTER); 4228 %} 4229 4230 // Compressed oops constants 4231 // Pointer Immediate 4232 operand immN() %{ 4233 match(ConN); 4234 4235 op_cost(10); 4236 format %{ %} 4237 interface(CONST_INTER); 4238 %} 4239 4240 // NULL Pointer Immediate 4241 operand immN_0() %{ 4242 predicate(n->get_narrowcon() == 0); 4243 match(ConN); 4244 4245 op_cost(0); 4246 format %{ %} 4247 interface(CONST_INTER); 4248 %} 4249 4250 // Compressed klass constants 4251 operand immNKlass() %{ 4252 match(ConNKlass); 4253 4254 op_cost(0); 4255 format %{ %} 4256 interface(CONST_INTER); 4257 %} 4258 4259 // This operand can be used to avoid matching of an instruct 4260 // with chain rule. 4261 operand immNKlass_NM() %{ 4262 match(ConNKlass); 4263 predicate(false); 4264 op_cost(0); 4265 format %{ %} 4266 interface(CONST_INTER); 4267 %} 4268 4269 // Pointer Immediate: 64-bit 4270 operand immP() %{ 4271 match(ConP); 4272 op_cost(0); 4273 format %{ %} 4274 interface(CONST_INTER); 4275 %} 4276 4277 // Operand to avoid match of loadConP. 4278 // This operand can be used to avoid matching of an instruct 4279 // with chain rule. 4280 operand immP_NM() %{ 4281 match(ConP); 4282 predicate(false); 4283 op_cost(0); 4284 format %{ %} 4285 interface(CONST_INTER); 4286 %} 4287 4288 // costant 'pointer 0'. 4289 operand immP_0() %{ 4290 predicate(n->get_ptr() == 0); 4291 match(ConP); 4292 op_cost(0); 4293 format %{ %} 4294 interface(CONST_INTER); 4295 %} 4296 4297 // pointer 0x0 or 0x1 4298 operand immP_0or1() %{ 4299 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); 4300 match(ConP); 4301 op_cost(0); 4302 format %{ %} 4303 interface(CONST_INTER); 4304 %} 4305 4306 operand immL() %{ 4307 match(ConL); 4308 op_cost(40); 4309 format %{ %} 4310 interface(CONST_INTER); 4311 %} 4312 4313 // Long Immediate: 16-bit 4314 operand immL16() %{ 4315 predicate(Assembler::is_simm(n->get_long(), 16)); 4316 match(ConL); 4317 op_cost(0); 4318 format %{ %} 4319 interface(CONST_INTER); 4320 %} 4321 4322 // Long Immediate: 16-bit, 4-aligned 4323 operand immL16Alg4() %{ 4324 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); 4325 match(ConL); 4326 op_cost(0); 4327 format %{ %} 4328 interface(CONST_INTER); 4329 %} 4330 4331 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. 4332 operand immL32hi16() %{ 4333 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); 4334 match(ConL); 4335 op_cost(0); 4336 format %{ %} 4337 interface(CONST_INTER); 4338 %} 4339 4340 // Long Immediate: 32-bit 4341 operand immL32() %{ 4342 predicate(Assembler::is_simm(n->get_long(), 32)); 4343 match(ConL); 4344 op_cost(0); 4345 format %{ %} 4346 interface(CONST_INTER); 4347 %} 4348 4349 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. 4350 operand immLhighest16() %{ 4351 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); 4352 match(ConL); 4353 op_cost(0); 4354 format %{ %} 4355 interface(CONST_INTER); 4356 %} 4357 4358 operand immLnegpow2() %{ 4359 predicate(is_power_of_2_long((jlong)-(n->get_long()))); 4360 match(ConL); 4361 op_cost(0); 4362 format %{ %} 4363 interface(CONST_INTER); 4364 %} 4365 4366 operand immLpow2minus1() %{ 4367 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && 4368 (n->get_long() != (jlong)0xffffffffffffffffL)); 4369 match(ConL); 4370 op_cost(0); 4371 format %{ %} 4372 interface(CONST_INTER); 4373 %} 4374 4375 // constant 'long 0'. 4376 operand immL_0() %{ 4377 predicate(n->get_long() == 0L); 4378 match(ConL); 4379 op_cost(0); 4380 format %{ %} 4381 interface(CONST_INTER); 4382 %} 4383 4384 // constat ' long -1'. 4385 operand immL_minus1() %{ 4386 predicate(n->get_long() == -1L); 4387 match(ConL); 4388 op_cost(0); 4389 format %{ %} 4390 interface(CONST_INTER); 4391 %} 4392 4393 // Long Immediate: low 32-bit mask 4394 operand immL_32bits() %{ 4395 predicate(n->get_long() == 0xFFFFFFFFL); 4396 match(ConL); 4397 op_cost(0); 4398 format %{ %} 4399 interface(CONST_INTER); 4400 %} 4401 4402 // Unsigned Long Immediate: 16-bit 4403 operand uimmL16() %{ 4404 predicate(Assembler::is_uimm(n->get_long(), 16)); 4405 match(ConL); 4406 op_cost(0); 4407 format %{ %} 4408 interface(CONST_INTER); 4409 %} 4410 4411 // Float Immediate 4412 operand immF() %{ 4413 match(ConF); 4414 op_cost(40); 4415 format %{ %} 4416 interface(CONST_INTER); 4417 %} 4418 4419 // constant 'float +0.0'. 4420 operand immF_0() %{ 4421 predicate((n->getf() == 0) && 4422 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0)); 4423 match(ConF); 4424 op_cost(0); 4425 format %{ %} 4426 interface(CONST_INTER); 4427 %} 4428 4429 // Double Immediate 4430 operand immD() %{ 4431 match(ConD); 4432 op_cost(40); 4433 format %{ %} 4434 interface(CONST_INTER); 4435 %} 4436 4437 // Integer Register Operands 4438 // Integer Destination Register 4439 // See definition of reg_class bits32_reg_rw. 4440 operand iRegIdst() %{ 4441 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4442 match(RegI); 4443 match(rscratch1RegI); 4444 match(rscratch2RegI); 4445 match(rarg1RegI); 4446 match(rarg2RegI); 4447 match(rarg3RegI); 4448 match(rarg4RegI); 4449 format %{ %} 4450 interface(REG_INTER); 4451 %} 4452 4453 // Integer Source Register 4454 // See definition of reg_class bits32_reg_ro. 4455 operand iRegIsrc() %{ 4456 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4457 match(RegI); 4458 match(rscratch1RegI); 4459 match(rscratch2RegI); 4460 match(rarg1RegI); 4461 match(rarg2RegI); 4462 match(rarg3RegI); 4463 match(rarg4RegI); 4464 format %{ %} 4465 interface(REG_INTER); 4466 %} 4467 4468 operand rscratch1RegI() %{ 4469 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); 4470 match(iRegIdst); 4471 format %{ %} 4472 interface(REG_INTER); 4473 %} 4474 4475 operand rscratch2RegI() %{ 4476 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); 4477 match(iRegIdst); 4478 format %{ %} 4479 interface(REG_INTER); 4480 %} 4481 4482 operand rarg1RegI() %{ 4483 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); 4484 match(iRegIdst); 4485 format %{ %} 4486 interface(REG_INTER); 4487 %} 4488 4489 operand rarg2RegI() %{ 4490 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); 4491 match(iRegIdst); 4492 format %{ %} 4493 interface(REG_INTER); 4494 %} 4495 4496 operand rarg3RegI() %{ 4497 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); 4498 match(iRegIdst); 4499 format %{ %} 4500 interface(REG_INTER); 4501 %} 4502 4503 operand rarg4RegI() %{ 4504 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); 4505 match(iRegIdst); 4506 format %{ %} 4507 interface(REG_INTER); 4508 %} 4509 4510 operand rarg1RegL() %{ 4511 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4512 match(iRegLdst); 4513 format %{ %} 4514 interface(REG_INTER); 4515 %} 4516 4517 operand rarg2RegL() %{ 4518 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4519 match(iRegLdst); 4520 format %{ %} 4521 interface(REG_INTER); 4522 %} 4523 4524 operand rarg3RegL() %{ 4525 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4526 match(iRegLdst); 4527 format %{ %} 4528 interface(REG_INTER); 4529 %} 4530 4531 operand rarg4RegL() %{ 4532 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4533 match(iRegLdst); 4534 format %{ %} 4535 interface(REG_INTER); 4536 %} 4537 4538 // Pointer Destination Register 4539 // See definition of reg_class bits64_reg_rw. 4540 operand iRegPdst() %{ 4541 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4542 match(RegP); 4543 match(rscratch1RegP); 4544 match(rscratch2RegP); 4545 match(rarg1RegP); 4546 match(rarg2RegP); 4547 match(rarg3RegP); 4548 match(rarg4RegP); 4549 format %{ %} 4550 interface(REG_INTER); 4551 %} 4552 4553 // Pointer Destination Register 4554 // Operand not using r11 and r12 (killed in epilog). 4555 operand iRegPdstNoScratch() %{ 4556 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); 4557 match(RegP); 4558 match(rarg1RegP); 4559 match(rarg2RegP); 4560 match(rarg3RegP); 4561 match(rarg4RegP); 4562 format %{ %} 4563 interface(REG_INTER); 4564 %} 4565 4566 // Pointer Source Register 4567 // See definition of reg_class bits64_reg_ro. 4568 operand iRegPsrc() %{ 4569 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4570 match(RegP); 4571 match(iRegPdst); 4572 match(rscratch1RegP); 4573 match(rscratch2RegP); 4574 match(rarg1RegP); 4575 match(rarg2RegP); 4576 match(rarg3RegP); 4577 match(rarg4RegP); 4578 match(threadRegP); 4579 format %{ %} 4580 interface(REG_INTER); 4581 %} 4582 4583 // Thread operand. 4584 operand threadRegP() %{ 4585 constraint(ALLOC_IN_RC(thread_bits64_reg)); 4586 match(iRegPdst); 4587 format %{ "R16" %} 4588 interface(REG_INTER); 4589 %} 4590 4591 operand rscratch1RegP() %{ 4592 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4593 match(iRegPdst); 4594 format %{ "R11" %} 4595 interface(REG_INTER); 4596 %} 4597 4598 operand rscratch2RegP() %{ 4599 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4600 match(iRegPdst); 4601 format %{ %} 4602 interface(REG_INTER); 4603 %} 4604 4605 operand rarg1RegP() %{ 4606 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4607 match(iRegPdst); 4608 format %{ %} 4609 interface(REG_INTER); 4610 %} 4611 4612 operand rarg2RegP() %{ 4613 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4614 match(iRegPdst); 4615 format %{ %} 4616 interface(REG_INTER); 4617 %} 4618 4619 operand rarg3RegP() %{ 4620 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4621 match(iRegPdst); 4622 format %{ %} 4623 interface(REG_INTER); 4624 %} 4625 4626 operand rarg4RegP() %{ 4627 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4628 match(iRegPdst); 4629 format %{ %} 4630 interface(REG_INTER); 4631 %} 4632 4633 operand iRegNsrc() %{ 4634 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4635 match(RegN); 4636 match(iRegNdst); 4637 4638 format %{ %} 4639 interface(REG_INTER); 4640 %} 4641 4642 operand iRegNdst() %{ 4643 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4644 match(RegN); 4645 4646 format %{ %} 4647 interface(REG_INTER); 4648 %} 4649 4650 // Long Destination Register 4651 // See definition of reg_class bits64_reg_rw. 4652 operand iRegLdst() %{ 4653 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4654 match(RegL); 4655 match(rscratch1RegL); 4656 match(rscratch2RegL); 4657 format %{ %} 4658 interface(REG_INTER); 4659 %} 4660 4661 // Long Source Register 4662 // See definition of reg_class bits64_reg_ro. 4663 operand iRegLsrc() %{ 4664 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4665 match(RegL); 4666 match(iRegLdst); 4667 match(rscratch1RegL); 4668 match(rscratch2RegL); 4669 format %{ %} 4670 interface(REG_INTER); 4671 %} 4672 4673 // Special operand for ConvL2I. 4674 operand iRegL2Isrc(iRegLsrc reg) %{ 4675 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4676 match(ConvL2I reg); 4677 format %{ "ConvL2I($reg)" %} 4678 interface(REG_INTER) 4679 %} 4680 4681 operand rscratch1RegL() %{ 4682 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4683 match(RegL); 4684 format %{ %} 4685 interface(REG_INTER); 4686 %} 4687 4688 operand rscratch2RegL() %{ 4689 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4690 match(RegL); 4691 format %{ %} 4692 interface(REG_INTER); 4693 %} 4694 4695 // Condition Code Flag Registers 4696 operand flagsReg() %{ 4697 constraint(ALLOC_IN_RC(int_flags)); 4698 match(RegFlags); 4699 format %{ %} 4700 interface(REG_INTER); 4701 %} 4702 4703 // Condition Code Flag Register CR0 4704 operand flagsRegCR0() %{ 4705 constraint(ALLOC_IN_RC(int_flags_CR0)); 4706 match(RegFlags); 4707 format %{ "CR0" %} 4708 interface(REG_INTER); 4709 %} 4710 4711 operand flagsRegCR1() %{ 4712 constraint(ALLOC_IN_RC(int_flags_CR1)); 4713 match(RegFlags); 4714 format %{ "CR1" %} 4715 interface(REG_INTER); 4716 %} 4717 4718 operand flagsRegCR6() %{ 4719 constraint(ALLOC_IN_RC(int_flags_CR6)); 4720 match(RegFlags); 4721 format %{ "CR6" %} 4722 interface(REG_INTER); 4723 %} 4724 4725 operand regCTR() %{ 4726 constraint(ALLOC_IN_RC(ctr_reg)); 4727 // RegFlags should work. Introducing a RegSpecial type would cause a 4728 // lot of changes. 4729 match(RegFlags); 4730 format %{"SR_CTR" %} 4731 interface(REG_INTER); 4732 %} 4733 4734 operand regD() %{ 4735 constraint(ALLOC_IN_RC(dbl_reg)); 4736 match(RegD); 4737 format %{ %} 4738 interface(REG_INTER); 4739 %} 4740 4741 operand regF() %{ 4742 constraint(ALLOC_IN_RC(flt_reg)); 4743 match(RegF); 4744 format %{ %} 4745 interface(REG_INTER); 4746 %} 4747 4748 // Special Registers 4749 4750 // Method Register 4751 operand inline_cache_regP(iRegPdst reg) %{ 4752 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg 4753 match(reg); 4754 format %{ %} 4755 interface(REG_INTER); 4756 %} 4757 4758 operand compiler_method_oop_regP(iRegPdst reg) %{ 4759 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg 4760 match(reg); 4761 format %{ %} 4762 interface(REG_INTER); 4763 %} 4764 4765 operand interpreter_method_oop_regP(iRegPdst reg) %{ 4766 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg 4767 match(reg); 4768 format %{ %} 4769 interface(REG_INTER); 4770 %} 4771 4772 // Operands to remove register moves in unscaled mode. 4773 // Match read/write registers with an EncodeP node if neither shift nor add are required. 4774 operand iRegP2N(iRegPsrc reg) %{ 4775 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); 4776 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4777 match(EncodeP reg); 4778 format %{ "$reg" %} 4779 interface(REG_INTER) 4780 %} 4781 4782 operand iRegN2P(iRegNsrc reg) %{ 4783 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4784 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4785 match(DecodeN reg); 4786 match(DecodeNKlass reg); 4787 format %{ "$reg" %} 4788 interface(REG_INTER) 4789 %} 4790 4791 //----------Complex Operands--------------------------------------------------- 4792 // Indirect Memory Reference 4793 operand indirect(iRegPsrc reg) %{ 4794 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4795 match(reg); 4796 op_cost(100); 4797 format %{ "[$reg]" %} 4798 interface(MEMORY_INTER) %{ 4799 base($reg); 4800 index(0x0); 4801 scale(0x0); 4802 disp(0x0); 4803 %} 4804 %} 4805 4806 // Indirect with Offset 4807 operand indOffset16(iRegPsrc reg, immL16 offset) %{ 4808 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4809 match(AddP reg offset); 4810 op_cost(100); 4811 format %{ "[$reg + $offset]" %} 4812 interface(MEMORY_INTER) %{ 4813 base($reg); 4814 index(0x0); 4815 scale(0x0); 4816 disp($offset); 4817 %} 4818 %} 4819 4820 // Indirect with 4-aligned Offset 4821 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ 4822 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4823 match(AddP reg offset); 4824 op_cost(100); 4825 format %{ "[$reg + $offset]" %} 4826 interface(MEMORY_INTER) %{ 4827 base($reg); 4828 index(0x0); 4829 scale(0x0); 4830 disp($offset); 4831 %} 4832 %} 4833 4834 //----------Complex Operands for Compressed OOPs------------------------------- 4835 // Compressed OOPs with narrow_oop_shift == 0. 4836 4837 // Indirect Memory Reference, compressed OOP 4838 operand indirectNarrow(iRegNsrc reg) %{ 4839 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4840 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4841 match(DecodeN reg); 4842 match(DecodeNKlass reg); 4843 op_cost(100); 4844 format %{ "[$reg]" %} 4845 interface(MEMORY_INTER) %{ 4846 base($reg); 4847 index(0x0); 4848 scale(0x0); 4849 disp(0x0); 4850 %} 4851 %} 4852 4853 // Indirect with Offset, compressed OOP 4854 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ 4855 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4856 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4857 match(AddP (DecodeN reg) offset); 4858 match(AddP (DecodeNKlass reg) offset); 4859 op_cost(100); 4860 format %{ "[$reg + $offset]" %} 4861 interface(MEMORY_INTER) %{ 4862 base($reg); 4863 index(0x0); 4864 scale(0x0); 4865 disp($offset); 4866 %} 4867 %} 4868 4869 // Indirect with 4-aligned Offset, compressed OOP 4870 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ 4871 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4872 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4873 match(AddP (DecodeN reg) offset); 4874 match(AddP (DecodeNKlass reg) offset); 4875 op_cost(100); 4876 format %{ "[$reg + $offset]" %} 4877 interface(MEMORY_INTER) %{ 4878 base($reg); 4879 index(0x0); 4880 scale(0x0); 4881 disp($offset); 4882 %} 4883 %} 4884 4885 //----------Special Memory Operands-------------------------------------------- 4886 // Stack Slot Operand 4887 // 4888 // This operand is used for loading and storing temporary values on 4889 // the stack where a match requires a value to flow through memory. 4890 operand stackSlotI(sRegI reg) %{ 4891 constraint(ALLOC_IN_RC(stack_slots)); 4892 op_cost(100); 4893 //match(RegI); 4894 format %{ "[sp+$reg]" %} 4895 interface(MEMORY_INTER) %{ 4896 base(0x1); // R1_SP 4897 index(0x0); 4898 scale(0x0); 4899 disp($reg); // Stack Offset 4900 %} 4901 %} 4902 4903 operand stackSlotL(sRegL reg) %{ 4904 constraint(ALLOC_IN_RC(stack_slots)); 4905 op_cost(100); 4906 //match(RegL); 4907 format %{ "[sp+$reg]" %} 4908 interface(MEMORY_INTER) %{ 4909 base(0x1); // R1_SP 4910 index(0x0); 4911 scale(0x0); 4912 disp($reg); // Stack Offset 4913 %} 4914 %} 4915 4916 operand stackSlotP(sRegP reg) %{ 4917 constraint(ALLOC_IN_RC(stack_slots)); 4918 op_cost(100); 4919 //match(RegP); 4920 format %{ "[sp+$reg]" %} 4921 interface(MEMORY_INTER) %{ 4922 base(0x1); // R1_SP 4923 index(0x0); 4924 scale(0x0); 4925 disp($reg); // Stack Offset 4926 %} 4927 %} 4928 4929 operand stackSlotF(sRegF reg) %{ 4930 constraint(ALLOC_IN_RC(stack_slots)); 4931 op_cost(100); 4932 //match(RegF); 4933 format %{ "[sp+$reg]" %} 4934 interface(MEMORY_INTER) %{ 4935 base(0x1); // R1_SP 4936 index(0x0); 4937 scale(0x0); 4938 disp($reg); // Stack Offset 4939 %} 4940 %} 4941 4942 operand stackSlotD(sRegD reg) %{ 4943 constraint(ALLOC_IN_RC(stack_slots)); 4944 op_cost(100); 4945 //match(RegD); 4946 format %{ "[sp+$reg]" %} 4947 interface(MEMORY_INTER) %{ 4948 base(0x1); // R1_SP 4949 index(0x0); 4950 scale(0x0); 4951 disp($reg); // Stack Offset 4952 %} 4953 %} 4954 4955 // Operands for expressing Control Flow 4956 // NOTE: Label is a predefined operand which should not be redefined in 4957 // the AD file. It is generically handled within the ADLC. 4958 4959 //----------Conditional Branch Operands---------------------------------------- 4960 // Comparison Op 4961 // 4962 // This is the operation of the comparison, and is limited to the 4963 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE 4964 // (!=). 4965 // 4966 // Other attributes of the comparison, such as unsignedness, are specified 4967 // by the comparison instruction that sets a condition code flags register. 4968 // That result is represented by a flags operand whose subtype is appropriate 4969 // to the unsignedness (etc.) of the comparison. 4970 // 4971 // Later, the instruction which matches both the Comparison Op (a Bool) and 4972 // the flags (produced by the Cmp) specifies the coding of the comparison op 4973 // by matching a specific subtype of Bool operand below. 4974 4975 // When used for floating point comparisons: unordered same as less. 4976 operand cmpOp() %{ 4977 match(Bool); 4978 format %{ "" %} 4979 interface(COND_INTER) %{ 4980 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. 4981 // BO & BI 4982 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal 4983 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal 4984 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less 4985 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less 4986 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater 4987 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater 4988 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow 4989 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow 4990 %} 4991 %} 4992 4993 //----------OPERAND CLASSES---------------------------------------------------- 4994 // Operand Classes are groups of operands that are used to simplify 4995 // instruction definitions by not requiring the AD writer to specify 4996 // seperate instructions for every form of operand when the 4997 // instruction accepts multiple operand types with the same basic 4998 // encoding and format. The classic case of this is memory operands. 4999 // Indirect is not included since its use is limited to Compare & Swap. 5000 5001 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow); 5002 // Memory operand where offsets are 4-aligned. Required for ld, std. 5003 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4); 5004 opclass indirectMemory(indirect, indirectNarrow); 5005 5006 // Special opclass for I and ConvL2I. 5007 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); 5008 5009 // Operand classes to match encode and decode. iRegN_P2N is only used 5010 // for storeN. I have never seen an encode node elsewhere. 5011 opclass iRegN_P2N(iRegNsrc, iRegP2N); 5012 opclass iRegP_N2P(iRegPsrc, iRegN2P); 5013 5014 //----------PIPELINE----------------------------------------------------------- 5015 5016 pipeline %{ 5017 5018 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM 5019 // J. Res. & Dev., No. 1, Jan. 2002. 5020 5021 //----------ATTRIBUTES--------------------------------------------------------- 5022 attributes %{ 5023 5024 // Power4 instructions are of fixed length. 5025 fixed_size_instructions; 5026 5027 // TODO: if `bundle' means number of instructions fetched 5028 // per cycle, this is 8. If `bundle' means Power4 `group', that is 5029 // max instructions issued per cycle, this is 5. 5030 max_instructions_per_bundle = 8; 5031 5032 // A Power4 instruction is 4 bytes long. 5033 instruction_unit_size = 4; 5034 5035 // The Power4 processor fetches 64 bytes... 5036 instruction_fetch_unit_size = 64; 5037 5038 // ...in one line 5039 instruction_fetch_units = 1 5040 5041 // Unused, list one so that array generated by adlc is not empty. 5042 // Aix compiler chokes if _nop_count = 0. 5043 nops(fxNop); 5044 %} 5045 5046 //----------RESOURCES---------------------------------------------------------- 5047 // Resources are the functional units available to the machine 5048 resources( 5049 PPC_BR, // branch unit 5050 PPC_CR, // condition unit 5051 PPC_FX1, // integer arithmetic unit 1 5052 PPC_FX2, // integer arithmetic unit 2 5053 PPC_LDST1, // load/store unit 1 5054 PPC_LDST2, // load/store unit 2 5055 PPC_FP1, // float arithmetic unit 1 5056 PPC_FP2, // float arithmetic unit 2 5057 PPC_LDST = PPC_LDST1 | PPC_LDST2, 5058 PPC_FX = PPC_FX1 | PPC_FX2, 5059 PPC_FP = PPC_FP1 | PPC_FP2 5060 ); 5061 5062 //----------PIPELINE DESCRIPTION----------------------------------------------- 5063 // Pipeline Description specifies the stages in the machine's pipeline 5064 pipe_desc( 5065 // Power4 longest pipeline path 5066 PPC_IF, // instruction fetch 5067 PPC_IC, 5068 //PPC_BP, // branch prediction 5069 PPC_D0, // decode 5070 PPC_D1, // decode 5071 PPC_D2, // decode 5072 PPC_D3, // decode 5073 PPC_Xfer1, 5074 PPC_GD, // group definition 5075 PPC_MP, // map 5076 PPC_ISS, // issue 5077 PPC_RF, // resource fetch 5078 PPC_EX1, // execute (all units) 5079 PPC_EX2, // execute (FP, LDST) 5080 PPC_EX3, // execute (FP, LDST) 5081 PPC_EX4, // execute (FP) 5082 PPC_EX5, // execute (FP) 5083 PPC_EX6, // execute (FP) 5084 PPC_WB, // write back 5085 PPC_Xfer2, 5086 PPC_CP 5087 ); 5088 5089 //----------PIPELINE CLASSES--------------------------------------------------- 5090 // Pipeline Classes describe the stages in which input and output are 5091 // referenced by the hardware pipeline. 5092 5093 // Simple pipeline classes. 5094 5095 // Default pipeline class. 5096 pipe_class pipe_class_default() %{ 5097 single_instruction; 5098 fixed_latency(2); 5099 %} 5100 5101 // Pipeline class for empty instructions. 5102 pipe_class pipe_class_empty() %{ 5103 single_instruction; 5104 fixed_latency(0); 5105 %} 5106 5107 // Pipeline class for compares. 5108 pipe_class pipe_class_compare() %{ 5109 single_instruction; 5110 fixed_latency(16); 5111 %} 5112 5113 // Pipeline class for traps. 5114 pipe_class pipe_class_trap() %{ 5115 single_instruction; 5116 fixed_latency(100); 5117 %} 5118 5119 // Pipeline class for memory operations. 5120 pipe_class pipe_class_memory() %{ 5121 single_instruction; 5122 fixed_latency(16); 5123 %} 5124 5125 // Pipeline class for call. 5126 pipe_class pipe_class_call() %{ 5127 single_instruction; 5128 fixed_latency(100); 5129 %} 5130 5131 // Define the class for the Nop node. 5132 define %{ 5133 MachNop = pipe_class_default; 5134 %} 5135 5136 %} 5137 5138 //----------INSTRUCTIONS------------------------------------------------------- 5139 5140 // Naming of instructions: 5141 // opA_operB / opA_operB_operC: 5142 // Operation 'op' with one or two source operands 'oper'. Result 5143 // type is A, source operand types are B and C. 5144 // Iff A == B == C, B and C are left out. 5145 // 5146 // The instructions are ordered according to the following scheme: 5147 // - loads 5148 // - load constants 5149 // - prefetch 5150 // - store 5151 // - encode/decode 5152 // - membar 5153 // - conditional moves 5154 // - compare & swap 5155 // - arithmetic and logic operations 5156 // * int: Add, Sub, Mul, Div, Mod 5157 // * int: lShift, arShift, urShift, rot 5158 // * float: Add, Sub, Mul, Div 5159 // * and, or, xor ... 5160 // - register moves: float <-> int, reg <-> stack, repl 5161 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. 5162 // - conv (low level type cast requiring bit changes (sign extend etc) 5163 // - compares, range & zero checks. 5164 // - branches 5165 // - complex operations, intrinsics, min, max, replicate 5166 // - lock 5167 // - Calls 5168 // 5169 // If there are similar instructions with different types they are sorted: 5170 // int before float 5171 // small before big 5172 // signed before unsigned 5173 // e.g., loadS before loadUS before loadI before loadF. 5174 5175 5176 //----------Load/Store Instructions-------------------------------------------- 5177 5178 //----------Load Instructions-------------------------------------------------- 5179 5180 // Converts byte to int. 5181 // As convB2I_reg, but without match rule. The match rule of convB2I_reg 5182 // reuses the 'amount' operand, but adlc expects that operand specification 5183 // and operands in match rule are equivalent. 5184 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ 5185 effect(DEF dst, USE src); 5186 format %{ "EXTSB $dst, $src \t// byte->int" %} 5187 size(4); 5188 ins_encode %{ 5189 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 5190 __ extsb($dst$$Register, $src$$Register); 5191 %} 5192 ins_pipe(pipe_class_default); 5193 %} 5194 5195 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ 5196 // match-rule, false predicate 5197 match(Set dst (LoadB mem)); 5198 predicate(false); 5199 5200 format %{ "LBZ $dst, $mem" %} 5201 size(4); 5202 ins_encode( enc_lbz(dst, mem) ); 5203 ins_pipe(pipe_class_memory); 5204 %} 5205 5206 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ 5207 // match-rule, false predicate 5208 match(Set dst (LoadB mem)); 5209 predicate(false); 5210 5211 format %{ "LBZ $dst, $mem\n\t" 5212 "TWI $dst\n\t" 5213 "ISYNC" %} 5214 size(12); 5215 ins_encode( enc_lbz_ac(dst, mem) ); 5216 ins_pipe(pipe_class_memory); 5217 %} 5218 5219 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5220 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ 5221 match(Set dst (LoadB mem)); 5222 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5223 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5224 expand %{ 5225 iRegIdst tmp; 5226 loadUB_indirect(tmp, mem); 5227 convB2I_reg_2(dst, tmp); 5228 %} 5229 %} 5230 5231 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ 5232 match(Set dst (LoadB mem)); 5233 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5234 expand %{ 5235 iRegIdst tmp; 5236 loadUB_indirect_ac(tmp, mem); 5237 convB2I_reg_2(dst, tmp); 5238 %} 5239 %} 5240 5241 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ 5242 // match-rule, false predicate 5243 match(Set dst (LoadB mem)); 5244 predicate(false); 5245 5246 format %{ "LBZ $dst, $mem" %} 5247 size(4); 5248 ins_encode( enc_lbz(dst, mem) ); 5249 ins_pipe(pipe_class_memory); 5250 %} 5251 5252 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ 5253 // match-rule, false predicate 5254 match(Set dst (LoadB mem)); 5255 predicate(false); 5256 5257 format %{ "LBZ $dst, $mem\n\t" 5258 "TWI $dst\n\t" 5259 "ISYNC" %} 5260 size(12); 5261 ins_encode( enc_lbz_ac(dst, mem) ); 5262 ins_pipe(pipe_class_memory); 5263 %} 5264 5265 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5266 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ 5267 match(Set dst (LoadB mem)); 5268 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5269 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5270 5271 expand %{ 5272 iRegIdst tmp; 5273 loadUB_indOffset16(tmp, mem); 5274 convB2I_reg_2(dst, tmp); 5275 %} 5276 %} 5277 5278 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ 5279 match(Set dst (LoadB mem)); 5280 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5281 5282 expand %{ 5283 iRegIdst tmp; 5284 loadUB_indOffset16_ac(tmp, mem); 5285 convB2I_reg_2(dst, tmp); 5286 %} 5287 %} 5288 5289 // Load Unsigned Byte (8bit UNsigned) into an int reg. 5290 instruct loadUB(iRegIdst dst, memory mem) %{ 5291 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5292 match(Set dst (LoadUB mem)); 5293 ins_cost(MEMORY_REF_COST); 5294 5295 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} 5296 size(4); 5297 ins_encode( enc_lbz(dst, mem) ); 5298 ins_pipe(pipe_class_memory); 5299 %} 5300 5301 // Load Unsigned Byte (8bit UNsigned) acquire. 5302 instruct loadUB_ac(iRegIdst dst, memory mem) %{ 5303 match(Set dst (LoadUB mem)); 5304 ins_cost(3*MEMORY_REF_COST); 5305 5306 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" 5307 "TWI $dst\n\t" 5308 "ISYNC" %} 5309 size(12); 5310 ins_encode( enc_lbz_ac(dst, mem) ); 5311 ins_pipe(pipe_class_memory); 5312 %} 5313 5314 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 5315 instruct loadUB2L(iRegLdst dst, memory mem) %{ 5316 match(Set dst (ConvI2L (LoadUB mem))); 5317 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5318 ins_cost(MEMORY_REF_COST); 5319 5320 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} 5321 size(4); 5322 ins_encode( enc_lbz(dst, mem) ); 5323 ins_pipe(pipe_class_memory); 5324 %} 5325 5326 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ 5327 match(Set dst (ConvI2L (LoadUB mem))); 5328 ins_cost(3*MEMORY_REF_COST); 5329 5330 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" 5331 "TWI $dst\n\t" 5332 "ISYNC" %} 5333 size(12); 5334 ins_encode( enc_lbz_ac(dst, mem) ); 5335 ins_pipe(pipe_class_memory); 5336 %} 5337 5338 // Load Short (16bit signed) 5339 instruct loadS(iRegIdst dst, memory mem) %{ 5340 match(Set dst (LoadS mem)); 5341 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5342 ins_cost(MEMORY_REF_COST); 5343 5344 format %{ "LHA $dst, $mem" %} 5345 size(4); 5346 ins_encode %{ 5347 // TODO: PPC port $archOpcode(ppc64Opcode_lha); 5348 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5349 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5350 %} 5351 ins_pipe(pipe_class_memory); 5352 %} 5353 5354 // Load Short (16bit signed) acquire. 5355 instruct loadS_ac(iRegIdst dst, memory mem) %{ 5356 match(Set dst (LoadS mem)); 5357 ins_cost(3*MEMORY_REF_COST); 5358 5359 format %{ "LHA $dst, $mem\t acquire\n\t" 5360 "TWI $dst\n\t" 5361 "ISYNC" %} 5362 size(12); 5363 ins_encode %{ 5364 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5365 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5366 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5367 __ twi_0($dst$$Register); 5368 __ isync(); 5369 %} 5370 ins_pipe(pipe_class_memory); 5371 %} 5372 5373 // Load Char (16bit unsigned) 5374 instruct loadUS(iRegIdst dst, memory mem) %{ 5375 match(Set dst (LoadUS mem)); 5376 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5377 ins_cost(MEMORY_REF_COST); 5378 5379 format %{ "LHZ $dst, $mem" %} 5380 size(4); 5381 ins_encode( enc_lhz(dst, mem) ); 5382 ins_pipe(pipe_class_memory); 5383 %} 5384 5385 // Load Char (16bit unsigned) acquire. 5386 instruct loadUS_ac(iRegIdst dst, memory mem) %{ 5387 match(Set dst (LoadUS mem)); 5388 ins_cost(3*MEMORY_REF_COST); 5389 5390 format %{ "LHZ $dst, $mem \t// acquire\n\t" 5391 "TWI $dst\n\t" 5392 "ISYNC" %} 5393 size(12); 5394 ins_encode( enc_lhz_ac(dst, mem) ); 5395 ins_pipe(pipe_class_memory); 5396 %} 5397 5398 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 5399 instruct loadUS2L(iRegLdst dst, memory mem) %{ 5400 match(Set dst (ConvI2L (LoadUS mem))); 5401 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5402 ins_cost(MEMORY_REF_COST); 5403 5404 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} 5405 size(4); 5406 ins_encode( enc_lhz(dst, mem) ); 5407 ins_pipe(pipe_class_memory); 5408 %} 5409 5410 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. 5411 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ 5412 match(Set dst (ConvI2L (LoadUS mem))); 5413 ins_cost(3*MEMORY_REF_COST); 5414 5415 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" 5416 "TWI $dst\n\t" 5417 "ISYNC" %} 5418 size(12); 5419 ins_encode( enc_lhz_ac(dst, mem) ); 5420 ins_pipe(pipe_class_memory); 5421 %} 5422 5423 // Load Integer. 5424 instruct loadI(iRegIdst dst, memory mem) %{ 5425 match(Set dst (LoadI mem)); 5426 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5427 ins_cost(MEMORY_REF_COST); 5428 5429 format %{ "LWZ $dst, $mem" %} 5430 size(4); 5431 ins_encode( enc_lwz(dst, mem) ); 5432 ins_pipe(pipe_class_memory); 5433 %} 5434 5435 // Load Integer acquire. 5436 instruct loadI_ac(iRegIdst dst, memory mem) %{ 5437 match(Set dst (LoadI mem)); 5438 ins_cost(3*MEMORY_REF_COST); 5439 5440 format %{ "LWZ $dst, $mem \t// load acquire\n\t" 5441 "TWI $dst\n\t" 5442 "ISYNC" %} 5443 size(12); 5444 ins_encode( enc_lwz_ac(dst, mem) ); 5445 ins_pipe(pipe_class_memory); 5446 %} 5447 5448 // Match loading integer and casting it to unsigned int in 5449 // long register. 5450 // LoadI + ConvI2L + AndL 0xffffffff. 5451 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 5452 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5453 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); 5454 ins_cost(MEMORY_REF_COST); 5455 5456 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} 5457 size(4); 5458 ins_encode( enc_lwz(dst, mem) ); 5459 ins_pipe(pipe_class_memory); 5460 %} 5461 5462 // Match loading integer and casting it to long. 5463 instruct loadI2L(iRegLdst dst, memory mem) %{ 5464 match(Set dst (ConvI2L (LoadI mem))); 5465 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5466 ins_cost(MEMORY_REF_COST); 5467 5468 format %{ "LWA $dst, $mem \t// loadI2L" %} 5469 size(4); 5470 ins_encode %{ 5471 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5472 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5473 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5474 %} 5475 ins_pipe(pipe_class_memory); 5476 %} 5477 5478 // Match loading integer and casting it to long - acquire. 5479 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ 5480 match(Set dst (ConvI2L (LoadI mem))); 5481 ins_cost(3*MEMORY_REF_COST); 5482 5483 format %{ "LWA $dst, $mem \t// loadI2L acquire" 5484 "TWI $dst\n\t" 5485 "ISYNC" %} 5486 size(12); 5487 ins_encode %{ 5488 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5489 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5490 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5491 __ twi_0($dst$$Register); 5492 __ isync(); 5493 %} 5494 ins_pipe(pipe_class_memory); 5495 %} 5496 5497 // Load Long - aligned 5498 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ 5499 match(Set dst (LoadL mem)); 5500 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5501 ins_cost(MEMORY_REF_COST); 5502 5503 format %{ "LD $dst, $mem \t// long" %} 5504 size(4); 5505 ins_encode( enc_ld(dst, mem) ); 5506 ins_pipe(pipe_class_memory); 5507 %} 5508 5509 // Load Long - aligned acquire. 5510 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ 5511 match(Set dst (LoadL mem)); 5512 ins_cost(3*MEMORY_REF_COST); 5513 5514 format %{ "LD $dst, $mem \t// long acquire\n\t" 5515 "TWI $dst\n\t" 5516 "ISYNC" %} 5517 size(12); 5518 ins_encode( enc_ld_ac(dst, mem) ); 5519 ins_pipe(pipe_class_memory); 5520 %} 5521 5522 // Load Long - UNaligned 5523 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ 5524 match(Set dst (LoadL_unaligned mem)); 5525 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5526 ins_cost(MEMORY_REF_COST); 5527 5528 format %{ "LD $dst, $mem \t// unaligned long" %} 5529 size(4); 5530 ins_encode( enc_ld(dst, mem) ); 5531 ins_pipe(pipe_class_memory); 5532 %} 5533 5534 // Load nodes for superwords 5535 5536 // Load Aligned Packed Byte 5537 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ 5538 predicate(n->as_LoadVector()->memory_size() == 8); 5539 match(Set dst (LoadVector mem)); 5540 ins_cost(MEMORY_REF_COST); 5541 5542 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} 5543 size(4); 5544 ins_encode( enc_ld(dst, mem) ); 5545 ins_pipe(pipe_class_memory); 5546 %} 5547 5548 // Load Range, range = array length (=jint) 5549 instruct loadRange(iRegIdst dst, memory mem) %{ 5550 match(Set dst (LoadRange mem)); 5551 ins_cost(MEMORY_REF_COST); 5552 5553 format %{ "LWZ $dst, $mem \t// range" %} 5554 size(4); 5555 ins_encode( enc_lwz(dst, mem) ); 5556 ins_pipe(pipe_class_memory); 5557 %} 5558 5559 // Load Compressed Pointer 5560 instruct loadN(iRegNdst dst, memory mem) %{ 5561 match(Set dst (LoadN mem)); 5562 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5563 ins_cost(MEMORY_REF_COST); 5564 5565 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} 5566 size(4); 5567 ins_encode( enc_lwz(dst, mem) ); 5568 ins_pipe(pipe_class_memory); 5569 %} 5570 5571 // Load Compressed Pointer acquire. 5572 instruct loadN_ac(iRegNdst dst, memory mem) %{ 5573 match(Set dst (LoadN mem)); 5574 ins_cost(3*MEMORY_REF_COST); 5575 5576 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" 5577 "TWI $dst\n\t" 5578 "ISYNC" %} 5579 size(12); 5580 ins_encode( enc_lwz_ac(dst, mem) ); 5581 ins_pipe(pipe_class_memory); 5582 %} 5583 5584 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. 5585 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ 5586 match(Set dst (DecodeN (LoadN mem))); 5587 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); 5588 ins_cost(MEMORY_REF_COST); 5589 5590 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5591 size(4); 5592 ins_encode( enc_lwz(dst, mem) ); 5593 ins_pipe(pipe_class_memory); 5594 %} 5595 5596 // Load Pointer 5597 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ 5598 match(Set dst (LoadP mem)); 5599 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5600 ins_cost(MEMORY_REF_COST); 5601 5602 format %{ "LD $dst, $mem \t// ptr" %} 5603 size(4); 5604 ins_encode( enc_ld(dst, mem) ); 5605 ins_pipe(pipe_class_memory); 5606 %} 5607 5608 // Load Pointer acquire. 5609 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ 5610 match(Set dst (LoadP mem)); 5611 ins_cost(3*MEMORY_REF_COST); 5612 5613 format %{ "LD $dst, $mem \t// ptr acquire\n\t" 5614 "TWI $dst\n\t" 5615 "ISYNC" %} 5616 size(12); 5617 ins_encode( enc_ld_ac(dst, mem) ); 5618 ins_pipe(pipe_class_memory); 5619 %} 5620 5621 // LoadP + CastP2L 5622 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ 5623 match(Set dst (CastP2X (LoadP mem))); 5624 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5625 ins_cost(MEMORY_REF_COST); 5626 5627 format %{ "LD $dst, $mem \t// ptr + p2x" %} 5628 size(4); 5629 ins_encode( enc_ld(dst, mem) ); 5630 ins_pipe(pipe_class_memory); 5631 %} 5632 5633 // Load compressed klass pointer. 5634 instruct loadNKlass(iRegNdst dst, memory mem) %{ 5635 match(Set dst (LoadNKlass mem)); 5636 ins_cost(MEMORY_REF_COST); 5637 5638 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} 5639 size(4); 5640 ins_encode( enc_lwz(dst, mem) ); 5641 ins_pipe(pipe_class_memory); 5642 %} 5643 5644 // Load Klass Pointer 5645 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 5646 match(Set dst (LoadKlass mem)); 5647 ins_cost(MEMORY_REF_COST); 5648 5649 format %{ "LD $dst, $mem \t// klass ptr" %} 5650 size(4); 5651 ins_encode( enc_ld(dst, mem) ); 5652 ins_pipe(pipe_class_memory); 5653 %} 5654 5655 // Load Float 5656 instruct loadF(regF dst, memory mem) %{ 5657 match(Set dst (LoadF mem)); 5658 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5659 ins_cost(MEMORY_REF_COST); 5660 5661 format %{ "LFS $dst, $mem" %} 5662 size(4); 5663 ins_encode %{ 5664 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 5665 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5666 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5667 %} 5668 ins_pipe(pipe_class_memory); 5669 %} 5670 5671 // Load Float acquire. 5672 instruct loadF_ac(regF dst, memory mem) %{ 5673 match(Set dst (LoadF mem)); 5674 ins_cost(3*MEMORY_REF_COST); 5675 5676 format %{ "LFS $dst, $mem \t// acquire\n\t" 5677 "FCMPU cr0, $dst, $dst\n\t" 5678 "BNE cr0, next\n" 5679 "next:\n\t" 5680 "ISYNC" %} 5681 size(16); 5682 ins_encode %{ 5683 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5684 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5685 Label next; 5686 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5687 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5688 __ bne(CCR0, next); 5689 __ bind(next); 5690 __ isync(); 5691 %} 5692 ins_pipe(pipe_class_memory); 5693 %} 5694 5695 // Load Double - aligned 5696 instruct loadD(regD dst, memory mem) %{ 5697 match(Set dst (LoadD mem)); 5698 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5699 ins_cost(MEMORY_REF_COST); 5700 5701 format %{ "LFD $dst, $mem" %} 5702 size(4); 5703 ins_encode( enc_lfd(dst, mem) ); 5704 ins_pipe(pipe_class_memory); 5705 %} 5706 5707 // Load Double - aligned acquire. 5708 instruct loadD_ac(regD dst, memory mem) %{ 5709 match(Set dst (LoadD mem)); 5710 ins_cost(3*MEMORY_REF_COST); 5711 5712 format %{ "LFD $dst, $mem \t// acquire\n\t" 5713 "FCMPU cr0, $dst, $dst\n\t" 5714 "BNE cr0, next\n" 5715 "next:\n\t" 5716 "ISYNC" %} 5717 size(16); 5718 ins_encode %{ 5719 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5720 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5721 Label next; 5722 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5723 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5724 __ bne(CCR0, next); 5725 __ bind(next); 5726 __ isync(); 5727 %} 5728 ins_pipe(pipe_class_memory); 5729 %} 5730 5731 // Load Double - UNaligned 5732 instruct loadD_unaligned(regD dst, memory mem) %{ 5733 match(Set dst (LoadD_unaligned mem)); 5734 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5735 ins_cost(MEMORY_REF_COST); 5736 5737 format %{ "LFD $dst, $mem" %} 5738 size(4); 5739 ins_encode( enc_lfd(dst, mem) ); 5740 ins_pipe(pipe_class_memory); 5741 %} 5742 5743 //----------Constants-------------------------------------------------------- 5744 5745 // Load MachConstantTableBase: add hi offset to global toc. 5746 // TODO: Handle hidden register r29 in bundler! 5747 instruct loadToc_hi(iRegLdst dst) %{ 5748 effect(DEF dst); 5749 ins_cost(DEFAULT_COST); 5750 5751 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} 5752 size(4); 5753 ins_encode %{ 5754 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5755 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); 5756 %} 5757 ins_pipe(pipe_class_default); 5758 %} 5759 5760 // Load MachConstantTableBase: add lo offset to global toc. 5761 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ 5762 effect(DEF dst, USE src); 5763 ins_cost(DEFAULT_COST); 5764 5765 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} 5766 size(4); 5767 ins_encode %{ 5768 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5769 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); 5770 %} 5771 ins_pipe(pipe_class_default); 5772 %} 5773 5774 // Load 16-bit integer constant 0xssss???? 5775 instruct loadConI16(iRegIdst dst, immI16 src) %{ 5776 match(Set dst src); 5777 5778 format %{ "LI $dst, $src" %} 5779 size(4); 5780 ins_encode %{ 5781 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5782 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 5783 %} 5784 ins_pipe(pipe_class_default); 5785 %} 5786 5787 // Load integer constant 0x????0000 5788 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ 5789 match(Set dst src); 5790 ins_cost(DEFAULT_COST); 5791 5792 format %{ "LIS $dst, $src.hi" %} 5793 size(4); 5794 ins_encode %{ 5795 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5796 // Lis sign extends 16-bit src then shifts it 16 bit to the left. 5797 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5798 %} 5799 ins_pipe(pipe_class_default); 5800 %} 5801 5802 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted 5803 // and sign extended), this adds the low 16 bits. 5804 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 5805 // no match-rule, false predicate 5806 effect(DEF dst, USE src1, USE src2); 5807 predicate(false); 5808 5809 format %{ "ORI $dst, $src1.hi, $src2.lo" %} 5810 size(4); 5811 ins_encode %{ 5812 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5813 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5814 %} 5815 ins_pipe(pipe_class_default); 5816 %} 5817 5818 instruct loadConI_Ex(iRegIdst dst, immI src) %{ 5819 match(Set dst src); 5820 ins_cost(DEFAULT_COST*2); 5821 5822 expand %{ 5823 // Would like to use $src$$constant. 5824 immI16 srcLo %{ _opnds[1]->constant() %} 5825 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5826 immIhi16 srcHi %{ _opnds[1]->constant() %} 5827 iRegIdst tmpI; 5828 loadConIhi16(tmpI, srcHi); 5829 loadConI32_lo16(dst, tmpI, srcLo); 5830 %} 5831 %} 5832 5833 // No constant pool entries required. 5834 instruct loadConL16(iRegLdst dst, immL16 src) %{ 5835 match(Set dst src); 5836 5837 format %{ "LI $dst, $src \t// long" %} 5838 size(4); 5839 ins_encode %{ 5840 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5841 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); 5842 %} 5843 ins_pipe(pipe_class_default); 5844 %} 5845 5846 // Load long constant 0xssssssss????0000 5847 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ 5848 match(Set dst src); 5849 ins_cost(DEFAULT_COST); 5850 5851 format %{ "LIS $dst, $src.hi \t// long" %} 5852 size(4); 5853 ins_encode %{ 5854 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5855 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5856 %} 5857 ins_pipe(pipe_class_default); 5858 %} 5859 5860 // To load a 32 bit constant: merge lower 16 bits into already loaded 5861 // high 16 bits. 5862 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 5863 // no match-rule, false predicate 5864 effect(DEF dst, USE src1, USE src2); 5865 predicate(false); 5866 5867 format %{ "ORI $dst, $src1, $src2.lo" %} 5868 size(4); 5869 ins_encode %{ 5870 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5871 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5872 %} 5873 ins_pipe(pipe_class_default); 5874 %} 5875 5876 // Load 32-bit long constant 5877 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ 5878 match(Set dst src); 5879 ins_cost(DEFAULT_COST*2); 5880 5881 expand %{ 5882 // Would like to use $src$$constant. 5883 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} 5884 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5885 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} 5886 iRegLdst tmpL; 5887 loadConL32hi16(tmpL, srcHi); 5888 loadConL32_lo16(dst, tmpL, srcLo); 5889 %} 5890 %} 5891 5892 // Load long constant 0x????000000000000. 5893 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ 5894 match(Set dst src); 5895 ins_cost(DEFAULT_COST); 5896 5897 expand %{ 5898 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} 5899 immI shift32 %{ 32 %} 5900 iRegLdst tmpL; 5901 loadConL32hi16(tmpL, srcHi); 5902 lshiftL_regL_immI(dst, tmpL, shift32); 5903 %} 5904 %} 5905 5906 // Expand node for constant pool load: small offset. 5907 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ 5908 effect(DEF dst, USE src, USE toc); 5909 ins_cost(MEMORY_REF_COST); 5910 5911 ins_num_consts(1); 5912 // Needed so that CallDynamicJavaDirect can compute the address of this 5913 // instruction for relocation. 5914 ins_field_cbuf_insts_offset(int); 5915 5916 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} 5917 size(4); 5918 ins_encode( enc_load_long_constL(dst, src, toc) ); 5919 ins_pipe(pipe_class_memory); 5920 %} 5921 5922 // Expand node for constant pool load: large offset. 5923 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ 5924 effect(DEF dst, USE src, USE toc); 5925 predicate(false); 5926 5927 ins_num_consts(1); 5928 ins_field_const_toc_offset(int); 5929 // Needed so that CallDynamicJavaDirect can compute the address of this 5930 // instruction for relocation. 5931 ins_field_cbuf_insts_offset(int); 5932 5933 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} 5934 size(4); 5935 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); 5936 ins_pipe(pipe_class_default); 5937 %} 5938 5939 // Expand node for constant pool load: large offset. 5940 // No constant pool entries required. 5941 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ 5942 effect(DEF dst, USE src, USE base); 5943 predicate(false); 5944 5945 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); 5946 5947 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} 5948 size(4); 5949 ins_encode %{ 5950 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 5951 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 5952 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 5953 %} 5954 ins_pipe(pipe_class_memory); 5955 %} 5956 5957 // Load long constant from constant table. Expand in case of 5958 // offset > 16 bit is needed. 5959 // Adlc adds toc node MachConstantTableBase. 5960 instruct loadConL_Ex(iRegLdst dst, immL src) %{ 5961 match(Set dst src); 5962 ins_cost(MEMORY_REF_COST); 5963 5964 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} 5965 // We can not inline the enc_class for the expand as that does not support constanttablebase. 5966 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); 5967 %} 5968 5969 // Load NULL as compressed oop. 5970 instruct loadConN0(iRegNdst dst, immN_0 src) %{ 5971 match(Set dst src); 5972 ins_cost(DEFAULT_COST); 5973 5974 format %{ "LI $dst, $src \t// compressed ptr" %} 5975 size(4); 5976 ins_encode %{ 5977 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5978 __ li($dst$$Register, 0); 5979 %} 5980 ins_pipe(pipe_class_default); 5981 %} 5982 5983 // Load hi part of compressed oop constant. 5984 instruct loadConN_hi(iRegNdst dst, immN src) %{ 5985 effect(DEF dst, USE src); 5986 ins_cost(DEFAULT_COST); 5987 5988 format %{ "LIS $dst, $src \t// narrow oop hi" %} 5989 size(4); 5990 ins_encode %{ 5991 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5992 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); 5993 %} 5994 ins_pipe(pipe_class_default); 5995 %} 5996 5997 // Add lo part of compressed oop constant to already loaded hi part. 5998 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ 5999 effect(DEF dst, USE src1, USE src2); 6000 ins_cost(DEFAULT_COST); 6001 6002 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} 6003 size(4); 6004 ins_encode %{ 6005 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6006 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6007 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); 6008 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6009 __ relocate(rspec, 1); 6010 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); 6011 %} 6012 ins_pipe(pipe_class_default); 6013 %} 6014 6015 // Needed to postalloc expand loadConN: ConN is loaded as ConI 6016 // leaving the upper 32 bits with sign-extension bits. 6017 // This clears these bits: dst = src & 0xFFFFFFFF. 6018 // TODO: Eventually call this maskN_regN_FFFFFFFF. 6019 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ 6020 effect(DEF dst, USE src); 6021 predicate(false); 6022 6023 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask 6024 size(4); 6025 ins_encode %{ 6026 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6027 __ clrldi($dst$$Register, $src$$Register, 0x20); 6028 %} 6029 ins_pipe(pipe_class_default); 6030 %} 6031 6032 // Optimize DecodeN for disjoint base. 6033 // Load base of compressed oops into a register 6034 instruct loadBase(iRegLdst dst) %{ 6035 effect(DEF dst); 6036 6037 format %{ "MR $dst, r30_heapbase" %} 6038 size(4); 6039 ins_encode %{ 6040 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6041 __ mr($dst$$Register, R30); 6042 %} 6043 ins_pipe(pipe_class_default); 6044 %} 6045 6046 // Loading ConN must be postalloc expanded so that edges between 6047 // the nodes are safe. They may not interfere with a safepoint. 6048 // GL TODO: This needs three instructions: better put this into the constant pool. 6049 instruct loadConN_Ex(iRegNdst dst, immN src) %{ 6050 match(Set dst src); 6051 ins_cost(DEFAULT_COST*2); 6052 6053 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6054 postalloc_expand %{ 6055 MachNode *m1 = new loadConN_hiNode(); 6056 MachNode *m2 = new loadConN_loNode(); 6057 MachNode *m3 = new clearMs32bNode(); 6058 m1->add_req(NULL); 6059 m2->add_req(NULL, m1); 6060 m3->add_req(NULL, m2); 6061 m1->_opnds[0] = op_dst; 6062 m1->_opnds[1] = op_src; 6063 m2->_opnds[0] = op_dst; 6064 m2->_opnds[1] = op_dst; 6065 m2->_opnds[2] = op_src; 6066 m3->_opnds[0] = op_dst; 6067 m3->_opnds[1] = op_dst; 6068 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6069 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6070 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6071 nodes->push(m1); 6072 nodes->push(m2); 6073 nodes->push(m3); 6074 %} 6075 %} 6076 6077 // We have seen a safepoint between the hi and lo parts, and this node was handled 6078 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is 6079 // not a narrow oop. 6080 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{ 6081 match(Set dst src); 6082 effect(DEF dst, USE src); 6083 ins_cost(DEFAULT_COST); 6084 6085 format %{ "LIS $dst, $src \t// narrow klass hi" %} 6086 size(4); 6087 ins_encode %{ 6088 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6089 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); 6090 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); 6091 %} 6092 ins_pipe(pipe_class_default); 6093 %} 6094 6095 // As loadConNKlass_hi this must be recognized as narrow klass, not oop! 6096 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6097 match(Set dst src1); 6098 effect(TEMP src2); 6099 ins_cost(DEFAULT_COST); 6100 6101 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask 6102 size(4); 6103 ins_encode %{ 6104 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6105 __ clrldi($dst$$Register, $src2$$Register, 0x20); 6106 %} 6107 ins_pipe(pipe_class_default); 6108 %} 6109 6110 // This needs a match rule so that build_oop_map knows this is 6111 // not a narrow oop. 6112 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6113 match(Set dst src1); 6114 effect(TEMP src2); 6115 ins_cost(DEFAULT_COST); 6116 6117 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %} 6118 size(4); 6119 ins_encode %{ 6120 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 6121 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 6122 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6123 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 6124 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6125 6126 __ relocate(rspec, 1); 6127 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); 6128 %} 6129 ins_pipe(pipe_class_default); 6130 %} 6131 6132 // Loading ConNKlass must be postalloc expanded so that edges between 6133 // the nodes are safe. They may not interfere with a safepoint. 6134 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ 6135 match(Set dst src); 6136 ins_cost(DEFAULT_COST*2); 6137 6138 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6139 postalloc_expand %{ 6140 // Load high bits into register. Sign extended. 6141 MachNode *m1 = new loadConNKlass_hiNode(); 6142 m1->add_req(NULL); 6143 m1->_opnds[0] = op_dst; 6144 m1->_opnds[1] = op_src; 6145 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6146 nodes->push(m1); 6147 6148 MachNode *m2 = m1; 6149 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 6150 // Value might be 1-extended. Mask out these bits. 6151 m2 = new loadConNKlass_maskNode(); 6152 m2->add_req(NULL, m1); 6153 m2->_opnds[0] = op_dst; 6154 m2->_opnds[1] = op_src; 6155 m2->_opnds[2] = op_dst; 6156 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6157 nodes->push(m2); 6158 } 6159 6160 MachNode *m3 = new loadConNKlass_loNode(); 6161 m3->add_req(NULL, m2); 6162 m3->_opnds[0] = op_dst; 6163 m3->_opnds[1] = op_src; 6164 m3->_opnds[2] = op_dst; 6165 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6166 nodes->push(m3); 6167 %} 6168 %} 6169 6170 // 0x1 is used in object initialization (initial object header). 6171 // No constant pool entries required. 6172 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ 6173 match(Set dst src); 6174 6175 format %{ "LI $dst, $src \t// ptr" %} 6176 size(4); 6177 ins_encode %{ 6178 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6179 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 6180 %} 6181 ins_pipe(pipe_class_default); 6182 %} 6183 6184 // Expand node for constant pool load: small offset. 6185 // The match rule is needed to generate the correct bottom_type(), 6186 // however this node should never match. The use of predicate is not 6187 // possible since ADLC forbids predicates for chain rules. The higher 6188 // costs do not prevent matching in this case. For that reason the 6189 // operand immP_NM with predicate(false) is used. 6190 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6191 match(Set dst src); 6192 effect(TEMP toc); 6193 6194 ins_num_consts(1); 6195 6196 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} 6197 size(4); 6198 ins_encode( enc_load_long_constP(dst, src, toc) ); 6199 ins_pipe(pipe_class_memory); 6200 %} 6201 6202 // Expand node for constant pool load: large offset. 6203 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6204 effect(DEF dst, USE src, USE toc); 6205 predicate(false); 6206 6207 ins_num_consts(1); 6208 ins_field_const_toc_offset(int); 6209 6210 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} 6211 size(4); 6212 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); 6213 ins_pipe(pipe_class_default); 6214 %} 6215 6216 // Expand node for constant pool load: large offset. 6217 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ 6218 match(Set dst src); 6219 effect(TEMP base); 6220 6221 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); 6222 6223 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} 6224 size(4); 6225 ins_encode %{ 6226 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 6227 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 6228 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 6229 %} 6230 ins_pipe(pipe_class_memory); 6231 %} 6232 6233 // Load pointer constant from constant table. Expand in case an 6234 // offset > 16 bit is needed. 6235 // Adlc adds toc node MachConstantTableBase. 6236 instruct loadConP_Ex(iRegPdst dst, immP src) %{ 6237 match(Set dst src); 6238 ins_cost(MEMORY_REF_COST); 6239 6240 // This rule does not use "expand" because then 6241 // the result type is not known to be an Oop. An ADLC 6242 // enhancement will be needed to make that work - not worth it! 6243 6244 // If this instruction rematerializes, it prolongs the live range 6245 // of the toc node, causing illegal graphs. 6246 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). 6247 ins_cannot_rematerialize(true); 6248 6249 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} 6250 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); 6251 %} 6252 6253 // Expand node for constant pool load: small offset. 6254 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ 6255 effect(DEF dst, USE src, USE toc); 6256 ins_cost(MEMORY_REF_COST); 6257 6258 ins_num_consts(1); 6259 6260 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} 6261 size(4); 6262 ins_encode %{ 6263 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 6264 address float_address = __ float_constant($src$$constant); 6265 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); 6266 %} 6267 ins_pipe(pipe_class_memory); 6268 %} 6269 6270 // Expand node for constant pool load: large offset. 6271 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ 6272 effect(DEF dst, USE src, USE toc); 6273 ins_cost(MEMORY_REF_COST); 6274 6275 ins_num_consts(1); 6276 6277 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6278 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" 6279 "ADDIS $toc, $toc, -offset_hi"%} 6280 size(12); 6281 ins_encode %{ 6282 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6283 FloatRegister Rdst = $dst$$FloatRegister; 6284 Register Rtoc = $toc$$Register; 6285 address float_address = __ float_constant($src$$constant); 6286 int offset = __ offset_to_method_toc(float_address); 6287 int hi = (offset + (1<<15))>>16; 6288 int lo = offset - hi * (1<<16); 6289 6290 __ addis(Rtoc, Rtoc, hi); 6291 __ lfs(Rdst, lo, Rtoc); 6292 __ addis(Rtoc, Rtoc, -hi); 6293 %} 6294 ins_pipe(pipe_class_memory); 6295 %} 6296 6297 // Adlc adds toc node MachConstantTableBase. 6298 instruct loadConF_Ex(regF dst, immF src) %{ 6299 match(Set dst src); 6300 ins_cost(MEMORY_REF_COST); 6301 6302 // See loadConP. 6303 ins_cannot_rematerialize(true); 6304 6305 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6306 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); 6307 %} 6308 6309 // Expand node for constant pool load: small offset. 6310 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ 6311 effect(DEF dst, USE src, USE toc); 6312 ins_cost(MEMORY_REF_COST); 6313 6314 ins_num_consts(1); 6315 6316 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} 6317 size(4); 6318 ins_encode %{ 6319 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 6320 int offset = __ offset_to_method_toc(__ double_constant($src$$constant)); 6321 __ lfd($dst$$FloatRegister, offset, $toc$$Register); 6322 %} 6323 ins_pipe(pipe_class_memory); 6324 %} 6325 6326 // Expand node for constant pool load: large offset. 6327 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ 6328 effect(DEF dst, USE src, USE toc); 6329 ins_cost(MEMORY_REF_COST); 6330 6331 ins_num_consts(1); 6332 6333 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6334 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" 6335 "ADDIS $toc, $toc, -offset_hi" %} 6336 size(12); 6337 ins_encode %{ 6338 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6339 FloatRegister Rdst = $dst$$FloatRegister; 6340 Register Rtoc = $toc$$Register; 6341 address float_address = __ double_constant($src$$constant); 6342 int offset = __ offset_to_method_toc(float_address); 6343 int hi = (offset + (1<<15))>>16; 6344 int lo = offset - hi * (1<<16); 6345 6346 __ addis(Rtoc, Rtoc, hi); 6347 __ lfd(Rdst, lo, Rtoc); 6348 __ addis(Rtoc, Rtoc, -hi); 6349 %} 6350 ins_pipe(pipe_class_memory); 6351 %} 6352 6353 // Adlc adds toc node MachConstantTableBase. 6354 instruct loadConD_Ex(regD dst, immD src) %{ 6355 match(Set dst src); 6356 ins_cost(MEMORY_REF_COST); 6357 6358 // See loadConP. 6359 ins_cannot_rematerialize(true); 6360 6361 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6362 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); 6363 %} 6364 6365 // Prefetch instructions. 6366 // Must be safe to execute with invalid address (cannot fault). 6367 6368 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{ 6369 match(PrefetchRead (AddP mem src)); 6370 ins_cost(MEMORY_REF_COST); 6371 6372 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %} 6373 size(4); 6374 ins_encode %{ 6375 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); 6376 __ dcbt($src$$Register, $mem$$base$$Register); 6377 %} 6378 ins_pipe(pipe_class_memory); 6379 %} 6380 6381 instruct prefetchr_no_offset(indirectMemory mem) %{ 6382 match(PrefetchRead mem); 6383 ins_cost(MEMORY_REF_COST); 6384 6385 format %{ "PREFETCH $mem" %} 6386 size(4); 6387 ins_encode %{ 6388 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); 6389 __ dcbt($mem$$base$$Register); 6390 %} 6391 ins_pipe(pipe_class_memory); 6392 %} 6393 6394 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{ 6395 match(PrefetchWrite (AddP mem src)); 6396 ins_cost(MEMORY_REF_COST); 6397 6398 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %} 6399 size(4); 6400 ins_encode %{ 6401 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6402 __ dcbtst($src$$Register, $mem$$base$$Register); 6403 %} 6404 ins_pipe(pipe_class_memory); 6405 %} 6406 6407 instruct prefetchw_no_offset(indirectMemory mem) %{ 6408 match(PrefetchWrite mem); 6409 ins_cost(MEMORY_REF_COST); 6410 6411 format %{ "PREFETCH $mem" %} 6412 size(4); 6413 ins_encode %{ 6414 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6415 __ dcbtst($mem$$base$$Register); 6416 %} 6417 ins_pipe(pipe_class_memory); 6418 %} 6419 6420 // Special prefetch versions which use the dcbz instruction. 6421 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ 6422 match(PrefetchAllocation (AddP mem src)); 6423 predicate(AllocatePrefetchStyle == 3); 6424 ins_cost(MEMORY_REF_COST); 6425 6426 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} 6427 size(4); 6428 ins_encode %{ 6429 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6430 __ dcbz($src$$Register, $mem$$base$$Register); 6431 %} 6432 ins_pipe(pipe_class_memory); 6433 %} 6434 6435 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ 6436 match(PrefetchAllocation mem); 6437 predicate(AllocatePrefetchStyle == 3); 6438 ins_cost(MEMORY_REF_COST); 6439 6440 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} 6441 size(4); 6442 ins_encode %{ 6443 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6444 __ dcbz($mem$$base$$Register); 6445 %} 6446 ins_pipe(pipe_class_memory); 6447 %} 6448 6449 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ 6450 match(PrefetchAllocation (AddP mem src)); 6451 predicate(AllocatePrefetchStyle != 3); 6452 ins_cost(MEMORY_REF_COST); 6453 6454 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} 6455 size(4); 6456 ins_encode %{ 6457 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6458 __ dcbtst($src$$Register, $mem$$base$$Register); 6459 %} 6460 ins_pipe(pipe_class_memory); 6461 %} 6462 6463 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ 6464 match(PrefetchAllocation mem); 6465 predicate(AllocatePrefetchStyle != 3); 6466 ins_cost(MEMORY_REF_COST); 6467 6468 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} 6469 size(4); 6470 ins_encode %{ 6471 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6472 __ dcbtst($mem$$base$$Register); 6473 %} 6474 ins_pipe(pipe_class_memory); 6475 %} 6476 6477 //----------Store Instructions------------------------------------------------- 6478 6479 // Store Byte 6480 instruct storeB(memory mem, iRegIsrc src) %{ 6481 match(Set mem (StoreB mem src)); 6482 ins_cost(MEMORY_REF_COST); 6483 6484 format %{ "STB $src, $mem \t// byte" %} 6485 size(4); 6486 ins_encode %{ 6487 // TODO: PPC port $archOpcode(ppc64Opcode_stb); 6488 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6489 __ stb($src$$Register, Idisp, $mem$$base$$Register); 6490 %} 6491 ins_pipe(pipe_class_memory); 6492 %} 6493 6494 // Store Char/Short 6495 instruct storeC(memory mem, iRegIsrc src) %{ 6496 match(Set mem (StoreC mem src)); 6497 ins_cost(MEMORY_REF_COST); 6498 6499 format %{ "STH $src, $mem \t// short" %} 6500 size(4); 6501 ins_encode %{ 6502 // TODO: PPC port $archOpcode(ppc64Opcode_sth); 6503 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6504 __ sth($src$$Register, Idisp, $mem$$base$$Register); 6505 %} 6506 ins_pipe(pipe_class_memory); 6507 %} 6508 6509 // Store Integer 6510 instruct storeI(memory mem, iRegIsrc src) %{ 6511 match(Set mem (StoreI mem src)); 6512 ins_cost(MEMORY_REF_COST); 6513 6514 format %{ "STW $src, $mem" %} 6515 size(4); 6516 ins_encode( enc_stw(src, mem) ); 6517 ins_pipe(pipe_class_memory); 6518 %} 6519 6520 // ConvL2I + StoreI. 6521 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ 6522 match(Set mem (StoreI mem (ConvL2I src))); 6523 ins_cost(MEMORY_REF_COST); 6524 6525 format %{ "STW l2i($src), $mem" %} 6526 size(4); 6527 ins_encode( enc_stw(src, mem) ); 6528 ins_pipe(pipe_class_memory); 6529 %} 6530 6531 // Store Long 6532 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ 6533 match(Set mem (StoreL mem src)); 6534 ins_cost(MEMORY_REF_COST); 6535 6536 format %{ "STD $src, $mem \t// long" %} 6537 size(4); 6538 ins_encode( enc_std(src, mem) ); 6539 ins_pipe(pipe_class_memory); 6540 %} 6541 6542 // Store super word nodes. 6543 6544 // Store Aligned Packed Byte long register to memory 6545 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ 6546 predicate(n->as_StoreVector()->memory_size() == 8); 6547 match(Set mem (StoreVector mem src)); 6548 ins_cost(MEMORY_REF_COST); 6549 6550 format %{ "STD $mem, $src \t// packed8B" %} 6551 size(4); 6552 ins_encode( enc_std(src, mem) ); 6553 ins_pipe(pipe_class_memory); 6554 %} 6555 6556 // Store Compressed Oop 6557 instruct storeN(memory dst, iRegN_P2N src) %{ 6558 match(Set dst (StoreN dst src)); 6559 ins_cost(MEMORY_REF_COST); 6560 6561 format %{ "STW $src, $dst \t// compressed oop" %} 6562 size(4); 6563 ins_encode( enc_stw(src, dst) ); 6564 ins_pipe(pipe_class_memory); 6565 %} 6566 6567 // Store Compressed KLass 6568 instruct storeNKlass(memory dst, iRegN_P2N src) %{ 6569 match(Set dst (StoreNKlass dst src)); 6570 ins_cost(MEMORY_REF_COST); 6571 6572 format %{ "STW $src, $dst \t// compressed klass" %} 6573 size(4); 6574 ins_encode( enc_stw(src, dst) ); 6575 ins_pipe(pipe_class_memory); 6576 %} 6577 6578 // Store Pointer 6579 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ 6580 match(Set dst (StoreP dst src)); 6581 ins_cost(MEMORY_REF_COST); 6582 6583 format %{ "STD $src, $dst \t// ptr" %} 6584 size(4); 6585 ins_encode( enc_std(src, dst) ); 6586 ins_pipe(pipe_class_memory); 6587 %} 6588 6589 // Store Float 6590 instruct storeF(memory mem, regF src) %{ 6591 match(Set mem (StoreF mem src)); 6592 ins_cost(MEMORY_REF_COST); 6593 6594 format %{ "STFS $src, $mem" %} 6595 size(4); 6596 ins_encode( enc_stfs(src, mem) ); 6597 ins_pipe(pipe_class_memory); 6598 %} 6599 6600 // Store Double 6601 instruct storeD(memory mem, regD src) %{ 6602 match(Set mem (StoreD mem src)); 6603 ins_cost(MEMORY_REF_COST); 6604 6605 format %{ "STFD $src, $mem" %} 6606 size(4); 6607 ins_encode( enc_stfd(src, mem) ); 6608 ins_pipe(pipe_class_memory); 6609 %} 6610 6611 //----------Store Instructions With Zeros-------------------------------------- 6612 6613 // Card-mark for CMS garbage collection. 6614 // This cardmark does an optimization so that it must not always 6615 // do a releasing store. For this, it gets the address of 6616 // CMSCollectorCardTableModRefBSExt::_requires_release as input. 6617 // (Using releaseFieldAddr in the match rule is a hack.) 6618 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{ 6619 match(Set mem (StoreCM mem releaseFieldAddr)); 6620 predicate(false); 6621 ins_cost(MEMORY_REF_COST); 6622 6623 // See loadConP. 6624 ins_cannot_rematerialize(true); 6625 6626 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} 6627 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) ); 6628 ins_pipe(pipe_class_memory); 6629 %} 6630 6631 // Card-mark for CMS garbage collection. 6632 // This cardmark does an optimization so that it must not always 6633 // do a releasing store. For this, it needs the constant address of 6634 // CMSCollectorCardTableModRefBSExt::_requires_release. 6635 // This constant address is split off here by expand so we can use 6636 // adlc / matcher functionality to load it from the constant section. 6637 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ 6638 match(Set mem (StoreCM mem zero)); 6639 predicate(UseConcMarkSweepGC); 6640 6641 expand %{ 6642 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} 6643 iRegLdst releaseFieldAddress; 6644 loadConL_Ex(releaseFieldAddress, baseImm); 6645 storeCM_CMS(mem, releaseFieldAddress); 6646 %} 6647 %} 6648 6649 instruct storeCM_G1(memory mem, immI_0 zero) %{ 6650 match(Set mem (StoreCM mem zero)); 6651 predicate(UseG1GC); 6652 ins_cost(MEMORY_REF_COST); 6653 6654 ins_cannot_rematerialize(true); 6655 6656 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} 6657 size(8); 6658 ins_encode %{ 6659 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6660 __ li(R0, 0); 6661 //__ release(); // G1: oops are allowed to get visible after dirty marking 6662 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); 6663 __ stb(R0, $mem$$disp, $mem$$base$$Register); 6664 %} 6665 ins_pipe(pipe_class_memory); 6666 %} 6667 6668 // Convert oop pointer into compressed form. 6669 6670 // Nodes for postalloc expand. 6671 6672 // Shift node for expand. 6673 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ 6674 // The match rule is needed to make it a 'MachTypeNode'! 6675 match(Set dst (EncodeP src)); 6676 predicate(false); 6677 6678 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6679 size(4); 6680 ins_encode %{ 6681 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6682 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6683 %} 6684 ins_pipe(pipe_class_default); 6685 %} 6686 6687 // Add node for expand. 6688 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ 6689 // The match rule is needed to make it a 'MachTypeNode'! 6690 match(Set dst (EncodeP src)); 6691 predicate(false); 6692 6693 format %{ "SUB $dst, $src, oop_base \t// encode" %} 6694 size(4); 6695 ins_encode %{ 6696 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6697 __ subf($dst$$Register, R30, $src$$Register); 6698 %} 6699 ins_pipe(pipe_class_default); 6700 %} 6701 6702 // Conditional sub base. 6703 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ 6704 // The match rule is needed to make it a 'MachTypeNode'! 6705 match(Set dst (EncodeP (Binary crx src1))); 6706 predicate(false); 6707 6708 ins_variable_size_depending_on_alignment(true); 6709 6710 format %{ "BEQ $crx, done\n\t" 6711 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n" 6712 "done:" %} 6713 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 6714 ins_encode %{ 6715 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 6716 Label done; 6717 __ beq($crx$$CondRegister, done); 6718 __ subf($dst$$Register, R30, $src1$$Register); 6719 // TODO PPC port __ endgroup_if_needed(_size == 12); 6720 __ bind(done); 6721 %} 6722 ins_pipe(pipe_class_default); 6723 %} 6724 6725 // Power 7 can use isel instruction 6726 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ 6727 // The match rule is needed to make it a 'MachTypeNode'! 6728 match(Set dst (EncodeP (Binary crx src1))); 6729 predicate(false); 6730 6731 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} 6732 size(4); 6733 ins_encode %{ 6734 // This is a Power7 instruction for which no machine description exists. 6735 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6736 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6737 %} 6738 ins_pipe(pipe_class_default); 6739 %} 6740 6741 // Disjoint narrow oop base. 6742 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6743 match(Set dst (EncodeP src)); 6744 predicate(Universe::narrow_oop_base_disjoint()); 6745 6746 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6747 size(4); 6748 ins_encode %{ 6749 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6750 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6751 %} 6752 ins_pipe(pipe_class_default); 6753 %} 6754 6755 // shift != 0, base != 0 6756 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ 6757 match(Set dst (EncodeP src)); 6758 effect(TEMP crx); 6759 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && 6760 Universe::narrow_oop_shift() != 0 && 6761 Universe::narrow_oop_base_overlaps()); 6762 6763 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} 6764 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); 6765 %} 6766 6767 // shift != 0, base != 0 6768 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ 6769 match(Set dst (EncodeP src)); 6770 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && 6771 Universe::narrow_oop_shift() != 0 && 6772 Universe::narrow_oop_base_overlaps()); 6773 6774 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} 6775 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); 6776 %} 6777 6778 // shift != 0, base == 0 6779 // TODO: This is the same as encodeP_shift. Merge! 6780 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ 6781 match(Set dst (EncodeP src)); 6782 predicate(Universe::narrow_oop_shift() != 0 && 6783 Universe::narrow_oop_base() ==0); 6784 6785 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} 6786 size(4); 6787 ins_encode %{ 6788 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6789 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6790 %} 6791 ins_pipe(pipe_class_default); 6792 %} 6793 6794 // Compressed OOPs with narrow_oop_shift == 0. 6795 // shift == 0, base == 0 6796 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ 6797 match(Set dst (EncodeP src)); 6798 predicate(Universe::narrow_oop_shift() == 0); 6799 6800 format %{ "MR $dst, $src \t// Ptr->Narrow" %} 6801 // variable size, 0 or 4. 6802 ins_encode %{ 6803 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6804 __ mr_if_needed($dst$$Register, $src$$Register); 6805 %} 6806 ins_pipe(pipe_class_default); 6807 %} 6808 6809 // Decode nodes. 6810 6811 // Shift node for expand. 6812 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ 6813 // The match rule is needed to make it a 'MachTypeNode'! 6814 match(Set dst (DecodeN src)); 6815 predicate(false); 6816 6817 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} 6818 size(4); 6819 ins_encode %{ 6820 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6821 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6822 %} 6823 ins_pipe(pipe_class_default); 6824 %} 6825 6826 // Add node for expand. 6827 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ 6828 // The match rule is needed to make it a 'MachTypeNode'! 6829 match(Set dst (DecodeN src)); 6830 predicate(false); 6831 6832 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %} 6833 size(4); 6834 ins_encode %{ 6835 // TODO: PPC port $archOpcode(ppc64Opcode_add); 6836 __ add($dst$$Register, $src$$Register, R30); 6837 %} 6838 ins_pipe(pipe_class_default); 6839 %} 6840 6841 // conditianal add base for expand 6842 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ 6843 // The match rule is needed to make it a 'MachTypeNode'! 6844 // NOTICE that the rule is nonsense - we just have to make sure that: 6845 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6846 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6847 match(Set dst (DecodeN (Binary crx src1))); 6848 predicate(false); 6849 6850 ins_variable_size_depending_on_alignment(true); 6851 6852 format %{ "BEQ $crx, done\n\t" 6853 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n" 6854 "done:" %} 6855 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8); 6856 ins_encode %{ 6857 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 6858 Label done; 6859 __ beq($crx$$CondRegister, done); 6860 __ add($dst$$Register, $src1$$Register, R30); 6861 // TODO PPC port __ endgroup_if_needed(_size == 12); 6862 __ bind(done); 6863 %} 6864 ins_pipe(pipe_class_default); 6865 %} 6866 6867 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ 6868 // The match rule is needed to make it a 'MachTypeNode'! 6869 // NOTICE that the rule is nonsense - we just have to make sure that: 6870 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6871 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6872 match(Set dst (DecodeN (Binary crx src1))); 6873 predicate(false); 6874 6875 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} 6876 size(4); 6877 ins_encode %{ 6878 // This is a Power7 instruction for which no machine description exists. 6879 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6880 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6881 %} 6882 ins_pipe(pipe_class_default); 6883 %} 6884 6885 // shift != 0, base != 0 6886 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6887 match(Set dst (DecodeN src)); 6888 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6889 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6890 Universe::narrow_oop_shift() != 0 && 6891 Universe::narrow_oop_base() != 0); 6892 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex. 6893 effect(TEMP crx); 6894 6895 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} 6896 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); 6897 %} 6898 6899 // shift != 0, base == 0 6900 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ 6901 match(Set dst (DecodeN src)); 6902 predicate(Universe::narrow_oop_shift() != 0 && 6903 Universe::narrow_oop_base() == 0); 6904 6905 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} 6906 size(4); 6907 ins_encode %{ 6908 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6909 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6910 %} 6911 ins_pipe(pipe_class_default); 6912 %} 6913 6914 // Optimize DecodeN for disjoint base. 6915 // Shift narrow oop and or it into register that already contains the heap base. 6916 // Base == dst must hold, and is assured by construction in postaloc_expand. 6917 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{ 6918 match(Set dst (DecodeN src)); 6919 effect(TEMP base); 6920 predicate(false); 6921 6922 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %} 6923 size(4); 6924 ins_encode %{ 6925 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 6926 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift()); 6927 %} 6928 ins_pipe(pipe_class_default); 6929 %} 6930 6931 // Optimize DecodeN for disjoint base. 6932 // This node requires only one cycle on the critical path. 6933 // We must postalloc_expand as we can not express use_def effects where 6934 // the used register is L and the def'ed register P. 6935 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{ 6936 match(Set dst (DecodeN src)); 6937 effect(TEMP_DEF dst); 6938 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6939 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6940 Universe::narrow_oop_base_disjoint()); 6941 ins_cost(DEFAULT_COST); 6942 6943 format %{ "MOV $dst, R30 \t\n" 6944 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %} 6945 postalloc_expand %{ 6946 loadBaseNode *n1 = new loadBaseNode(); 6947 n1->add_req(NULL); 6948 n1->_opnds[0] = op_dst; 6949 6950 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6951 n2->add_req(n_region, n_src, n1); 6952 n2->_opnds[0] = op_dst; 6953 n2->_opnds[1] = op_src; 6954 n2->_opnds[2] = op_dst; 6955 n2->_bottom_type = _bottom_type; 6956 6957 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6958 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6959 6960 nodes->push(n1); 6961 nodes->push(n2); 6962 %} 6963 %} 6964 6965 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6966 match(Set dst (DecodeN src)); 6967 effect(TEMP_DEF dst, TEMP crx); 6968 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6969 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6970 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel()); 6971 ins_cost(3 * DEFAULT_COST); 6972 6973 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %} 6974 postalloc_expand %{ 6975 loadBaseNode *n1 = new loadBaseNode(); 6976 n1->add_req(NULL); 6977 n1->_opnds[0] = op_dst; 6978 6979 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 6980 n_compare->add_req(n_region, n_src); 6981 n_compare->_opnds[0] = op_crx; 6982 n_compare->_opnds[1] = op_src; 6983 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 6984 6985 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6986 n2->add_req(n_region, n_src, n1); 6987 n2->_opnds[0] = op_dst; 6988 n2->_opnds[1] = op_src; 6989 n2->_opnds[2] = op_dst; 6990 n2->_bottom_type = _bottom_type; 6991 6992 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 6993 n_cond_set->add_req(n_region, n_compare, n2); 6994 n_cond_set->_opnds[0] = op_dst; 6995 n_cond_set->_opnds[1] = op_crx; 6996 n_cond_set->_opnds[2] = op_dst; 6997 n_cond_set->_bottom_type = _bottom_type; 6998 6999 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 7000 ra_->set_oop(n_cond_set, true); 7001 7002 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7003 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 7004 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7005 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7006 7007 nodes->push(n1); 7008 nodes->push(n_compare); 7009 nodes->push(n2); 7010 nodes->push(n_cond_set); 7011 %} 7012 %} 7013 7014 // src != 0, shift != 0, base != 0 7015 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ 7016 match(Set dst (DecodeN src)); 7017 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 7018 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 7019 Universe::narrow_oop_shift() != 0 && 7020 Universe::narrow_oop_base() != 0); 7021 ins_cost(2 * DEFAULT_COST); 7022 7023 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} 7024 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); 7025 %} 7026 7027 // Compressed OOPs with narrow_oop_shift == 0. 7028 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ 7029 match(Set dst (DecodeN src)); 7030 predicate(Universe::narrow_oop_shift() == 0); 7031 ins_cost(DEFAULT_COST); 7032 7033 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} 7034 // variable size, 0 or 4. 7035 ins_encode %{ 7036 // TODO: PPC port $archOpcode(ppc64Opcode_or); 7037 __ mr_if_needed($dst$$Register, $src$$Register); 7038 %} 7039 ins_pipe(pipe_class_default); 7040 %} 7041 7042 // Convert compressed oop into int for vectors alignment masking. 7043 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ 7044 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 7045 predicate(Universe::narrow_oop_shift() == 0); 7046 ins_cost(DEFAULT_COST); 7047 7048 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} 7049 // variable size, 0 or 4. 7050 ins_encode %{ 7051 // TODO: PPC port $archOpcode(ppc64Opcode_or); 7052 __ mr_if_needed($dst$$Register, $src$$Register); 7053 %} 7054 ins_pipe(pipe_class_default); 7055 %} 7056 7057 // Convert klass pointer into compressed form. 7058 7059 // Nodes for postalloc expand. 7060 7061 // Shift node for expand. 7062 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ 7063 // The match rule is needed to make it a 'MachTypeNode'! 7064 match(Set dst (EncodePKlass src)); 7065 predicate(false); 7066 7067 format %{ "SRDI $dst, $src, 3 \t// encode" %} 7068 size(4); 7069 ins_encode %{ 7070 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 7071 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7072 %} 7073 ins_pipe(pipe_class_default); 7074 %} 7075 7076 // Add node for expand. 7077 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7078 // The match rule is needed to make it a 'MachTypeNode'! 7079 match(Set dst (EncodePKlass (Binary base src))); 7080 predicate(false); 7081 7082 format %{ "SUB $dst, $base, $src \t// encode" %} 7083 size(4); 7084 ins_encode %{ 7085 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7086 __ subf($dst$$Register, $base$$Register, $src$$Register); 7087 %} 7088 ins_pipe(pipe_class_default); 7089 %} 7090 7091 // Disjoint narrow oop base. 7092 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{ 7093 match(Set dst (EncodePKlass src)); 7094 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); 7095 7096 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 7097 size(4); 7098 ins_encode %{ 7099 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 7100 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32); 7101 %} 7102 ins_pipe(pipe_class_default); 7103 %} 7104 7105 // shift != 0, base != 0 7106 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ 7107 match(Set dst (EncodePKlass (Binary base src))); 7108 predicate(false); 7109 7110 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7111 postalloc_expand %{ 7112 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode(); 7113 n1->add_req(n_region, n_base, n_src); 7114 n1->_opnds[0] = op_dst; 7115 n1->_opnds[1] = op_base; 7116 n1->_opnds[2] = op_src; 7117 n1->_bottom_type = _bottom_type; 7118 7119 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode(); 7120 n2->add_req(n_region, n1); 7121 n2->_opnds[0] = op_dst; 7122 n2->_opnds[1] = op_dst; 7123 n2->_bottom_type = _bottom_type; 7124 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7125 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7126 7127 nodes->push(n1); 7128 nodes->push(n2); 7129 %} 7130 %} 7131 7132 // shift != 0, base != 0 7133 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ 7134 match(Set dst (EncodePKlass src)); 7135 //predicate(Universe::narrow_klass_shift() != 0 && 7136 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); 7137 7138 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7139 ins_cost(DEFAULT_COST*2); // Don't count constant. 7140 expand %{ 7141 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} 7142 iRegLdst base; 7143 loadConL_Ex(base, baseImm); 7144 encodePKlass_not_null_Ex(dst, base, src); 7145 %} 7146 %} 7147 7148 // Decode nodes. 7149 7150 // Shift node for expand. 7151 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ 7152 // The match rule is needed to make it a 'MachTypeNode'! 7153 match(Set dst (DecodeNKlass src)); 7154 predicate(false); 7155 7156 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} 7157 size(4); 7158 ins_encode %{ 7159 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 7160 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7161 %} 7162 ins_pipe(pipe_class_default); 7163 %} 7164 7165 // Add node for expand. 7166 7167 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7168 // The match rule is needed to make it a 'MachTypeNode'! 7169 match(Set dst (DecodeNKlass (Binary base src))); 7170 predicate(false); 7171 7172 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} 7173 size(4); 7174 ins_encode %{ 7175 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7176 __ add($dst$$Register, $base$$Register, $src$$Register); 7177 %} 7178 ins_pipe(pipe_class_default); 7179 %} 7180 7181 // src != 0, shift != 0, base != 0 7182 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ 7183 match(Set dst (DecodeNKlass (Binary base src))); 7184 //effect(kill src); // We need a register for the immediate result after shifting. 7185 predicate(false); 7186 7187 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} 7188 postalloc_expand %{ 7189 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode(); 7190 n1->add_req(n_region, n_base, n_src); 7191 n1->_opnds[0] = op_dst; 7192 n1->_opnds[1] = op_base; 7193 n1->_opnds[2] = op_src; 7194 n1->_bottom_type = _bottom_type; 7195 7196 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode(); 7197 n2->add_req(n_region, n1); 7198 n2->_opnds[0] = op_dst; 7199 n2->_opnds[1] = op_dst; 7200 n2->_bottom_type = _bottom_type; 7201 7202 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7203 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7204 7205 nodes->push(n1); 7206 nodes->push(n2); 7207 %} 7208 %} 7209 7210 // src != 0, shift != 0, base != 0 7211 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ 7212 match(Set dst (DecodeNKlass src)); 7213 // predicate(Universe::narrow_klass_shift() != 0 && 7214 // Universe::narrow_klass_base() != 0); 7215 7216 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} 7217 7218 ins_cost(DEFAULT_COST*2); // Don't count constant. 7219 expand %{ 7220 // We add first, then we shift. Like this, we can get along with one register less. 7221 // But we have to load the base pre-shifted. 7222 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} 7223 iRegLdst base; 7224 loadConL_Ex(base, baseImm); 7225 decodeNKlass_notNull_addBase_Ex(dst, base, src); 7226 %} 7227 %} 7228 7229 //----------MemBar Instructions----------------------------------------------- 7230 // Memory barrier flavors 7231 7232 instruct membar_acquire() %{ 7233 match(LoadFence); 7234 ins_cost(4*MEMORY_REF_COST); 7235 7236 format %{ "MEMBAR-acquire" %} 7237 size(4); 7238 ins_encode %{ 7239 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7240 __ acquire(); 7241 %} 7242 ins_pipe(pipe_class_default); 7243 %} 7244 7245 instruct unnecessary_membar_acquire() %{ 7246 match(MemBarAcquire); 7247 ins_cost(0); 7248 7249 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} 7250 size(0); 7251 ins_encode( /*empty*/ ); 7252 ins_pipe(pipe_class_default); 7253 %} 7254 7255 instruct membar_acquire_lock() %{ 7256 match(MemBarAcquireLock); 7257 ins_cost(0); 7258 7259 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} 7260 size(0); 7261 ins_encode( /*empty*/ ); 7262 ins_pipe(pipe_class_default); 7263 %} 7264 7265 instruct membar_release() %{ 7266 match(MemBarRelease); 7267 match(StoreFence); 7268 ins_cost(4*MEMORY_REF_COST); 7269 7270 format %{ "MEMBAR-release" %} 7271 size(4); 7272 ins_encode %{ 7273 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7274 __ release(); 7275 %} 7276 ins_pipe(pipe_class_default); 7277 %} 7278 7279 instruct membar_storestore() %{ 7280 match(MemBarStoreStore); 7281 ins_cost(4*MEMORY_REF_COST); 7282 7283 format %{ "MEMBAR-store-store" %} 7284 size(4); 7285 ins_encode %{ 7286 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7287 __ membar(Assembler::StoreStore); 7288 %} 7289 ins_pipe(pipe_class_default); 7290 %} 7291 7292 instruct membar_release_lock() %{ 7293 match(MemBarReleaseLock); 7294 ins_cost(0); 7295 7296 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} 7297 size(0); 7298 ins_encode( /*empty*/ ); 7299 ins_pipe(pipe_class_default); 7300 %} 7301 7302 instruct membar_volatile() %{ 7303 match(MemBarVolatile); 7304 ins_cost(4*MEMORY_REF_COST); 7305 7306 format %{ "MEMBAR-volatile" %} 7307 size(4); 7308 ins_encode %{ 7309 // TODO: PPC port $archOpcode(ppc64Opcode_sync); 7310 __ fence(); 7311 %} 7312 ins_pipe(pipe_class_default); 7313 %} 7314 7315 // This optimization is wrong on PPC. The following pattern is not supported: 7316 // MemBarVolatile 7317 // ^ ^ 7318 // | | 7319 // CtrlProj MemProj 7320 // ^ ^ 7321 // | | 7322 // | Load 7323 // | 7324 // MemBarVolatile 7325 // 7326 // The first MemBarVolatile could get optimized out! According to 7327 // Vladimir, this pattern can not occur on Oracle platforms. 7328 // However, it does occur on PPC64 (because of membars in 7329 // inline_unsafe_load_store). 7330 // 7331 // Add this node again if we found a good solution for inline_unsafe_load_store(). 7332 // Don't forget to look at the implementation of post_store_load_barrier again, 7333 // we did other fixes in that method. 7334 //instruct unnecessary_membar_volatile() %{ 7335 // match(MemBarVolatile); 7336 // predicate(Matcher::post_store_load_barrier(n)); 7337 // ins_cost(0); 7338 // 7339 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} 7340 // size(0); 7341 // ins_encode( /*empty*/ ); 7342 // ins_pipe(pipe_class_default); 7343 //%} 7344 7345 instruct membar_CPUOrder() %{ 7346 match(MemBarCPUOrder); 7347 ins_cost(0); 7348 7349 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} 7350 size(0); 7351 ins_encode( /*empty*/ ); 7352 ins_pipe(pipe_class_default); 7353 %} 7354 7355 //----------Conditional Move--------------------------------------------------- 7356 7357 // Cmove using isel. 7358 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ 7359 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7360 predicate(VM_Version::has_isel()); 7361 ins_cost(DEFAULT_COST); 7362 7363 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7364 size(4); 7365 ins_encode %{ 7366 // This is a Power7 instruction for which no machine description 7367 // exists. Anyways, the scheduler should be off on Power7. 7368 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7369 int cc = $cmp$$cmpcode; 7370 __ isel($dst$$Register, $crx$$CondRegister, 7371 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7372 %} 7373 ins_pipe(pipe_class_default); 7374 %} 7375 7376 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ 7377 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7378 predicate(!VM_Version::has_isel()); 7379 ins_cost(DEFAULT_COST+BRANCH_COST); 7380 7381 ins_variable_size_depending_on_alignment(true); 7382 7383 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7384 // Worst case is branch + move + stop, no stop without scheduler 7385 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7386 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7387 ins_pipe(pipe_class_default); 7388 %} 7389 7390 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{ 7391 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7392 ins_cost(DEFAULT_COST+BRANCH_COST); 7393 7394 ins_variable_size_depending_on_alignment(true); 7395 7396 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7397 // Worst case is branch + move + stop, no stop without scheduler 7398 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7399 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7400 ins_pipe(pipe_class_default); 7401 %} 7402 7403 // Cmove using isel. 7404 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ 7405 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7406 predicate(VM_Version::has_isel()); 7407 ins_cost(DEFAULT_COST); 7408 7409 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7410 size(4); 7411 ins_encode %{ 7412 // This is a Power7 instruction for which no machine description 7413 // exists. Anyways, the scheduler should be off on Power7. 7414 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7415 int cc = $cmp$$cmpcode; 7416 __ isel($dst$$Register, $crx$$CondRegister, 7417 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7418 %} 7419 ins_pipe(pipe_class_default); 7420 %} 7421 7422 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ 7423 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7424 predicate(!VM_Version::has_isel()); 7425 ins_cost(DEFAULT_COST+BRANCH_COST); 7426 7427 ins_variable_size_depending_on_alignment(true); 7428 7429 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7430 // Worst case is branch + move + stop, no stop without scheduler. 7431 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7432 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7433 ins_pipe(pipe_class_default); 7434 %} 7435 7436 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{ 7437 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7438 ins_cost(DEFAULT_COST+BRANCH_COST); 7439 7440 ins_variable_size_depending_on_alignment(true); 7441 7442 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7443 // Worst case is branch + move + stop, no stop without scheduler. 7444 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7445 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7446 ins_pipe(pipe_class_default); 7447 %} 7448 7449 // Cmove using isel. 7450 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ 7451 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7452 predicate(VM_Version::has_isel()); 7453 ins_cost(DEFAULT_COST); 7454 7455 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7456 size(4); 7457 ins_encode %{ 7458 // This is a Power7 instruction for which no machine description 7459 // exists. Anyways, the scheduler should be off on Power7. 7460 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7461 int cc = $cmp$$cmpcode; 7462 __ isel($dst$$Register, $crx$$CondRegister, 7463 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7464 %} 7465 ins_pipe(pipe_class_default); 7466 %} 7467 7468 // Conditional move for RegN. Only cmov(reg, reg). 7469 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ 7470 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7471 predicate(!VM_Version::has_isel()); 7472 ins_cost(DEFAULT_COST+BRANCH_COST); 7473 7474 ins_variable_size_depending_on_alignment(true); 7475 7476 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7477 // Worst case is branch + move + stop, no stop without scheduler. 7478 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7479 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7480 ins_pipe(pipe_class_default); 7481 %} 7482 7483 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{ 7484 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7485 ins_cost(DEFAULT_COST+BRANCH_COST); 7486 7487 ins_variable_size_depending_on_alignment(true); 7488 7489 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7490 // Worst case is branch + move + stop, no stop without scheduler. 7491 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7492 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7493 ins_pipe(pipe_class_default); 7494 %} 7495 7496 // Cmove using isel. 7497 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{ 7498 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7499 predicate(VM_Version::has_isel()); 7500 ins_cost(DEFAULT_COST); 7501 7502 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7503 size(4); 7504 ins_encode %{ 7505 // This is a Power7 instruction for which no machine description 7506 // exists. Anyways, the scheduler should be off on Power7. 7507 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7508 int cc = $cmp$$cmpcode; 7509 __ isel($dst$$Register, $crx$$CondRegister, 7510 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7511 %} 7512 ins_pipe(pipe_class_default); 7513 %} 7514 7515 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{ 7516 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7517 predicate(!VM_Version::has_isel()); 7518 ins_cost(DEFAULT_COST+BRANCH_COST); 7519 7520 ins_variable_size_depending_on_alignment(true); 7521 7522 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7523 // Worst case is branch + move + stop, no stop without scheduler. 7524 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7525 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7526 ins_pipe(pipe_class_default); 7527 %} 7528 7529 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{ 7530 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7531 ins_cost(DEFAULT_COST+BRANCH_COST); 7532 7533 ins_variable_size_depending_on_alignment(true); 7534 7535 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7536 // Worst case is branch + move + stop, no stop without scheduler. 7537 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7538 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7539 ins_pipe(pipe_class_default); 7540 %} 7541 7542 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{ 7543 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); 7544 ins_cost(DEFAULT_COST+BRANCH_COST); 7545 7546 ins_variable_size_depending_on_alignment(true); 7547 7548 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7549 // Worst case is branch + move + stop, no stop without scheduler. 7550 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7551 ins_encode %{ 7552 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7553 Label done; 7554 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7555 // Branch if not (cmp crx). 7556 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7557 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7558 // TODO PPC port __ endgroup_if_needed(_size == 12); 7559 __ bind(done); 7560 %} 7561 ins_pipe(pipe_class_default); 7562 %} 7563 7564 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{ 7565 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); 7566 ins_cost(DEFAULT_COST+BRANCH_COST); 7567 7568 ins_variable_size_depending_on_alignment(true); 7569 7570 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7571 // Worst case is branch + move + stop, no stop without scheduler. 7572 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7573 ins_encode %{ 7574 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7575 Label done; 7576 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7577 // Branch if not (cmp crx). 7578 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7579 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7580 // TODO PPC port __ endgroup_if_needed(_size == 12); 7581 __ bind(done); 7582 %} 7583 ins_pipe(pipe_class_default); 7584 %} 7585 7586 //----------Conditional_store-------------------------------------------------- 7587 // Conditional-store of the updated heap-top. 7588 // Used during allocation of the shared heap. 7589 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7590 7591 // As compareAndSwapL, but return flag register instead of boolean value in 7592 // int register. 7593 // Used by sun/misc/AtomicLongCSImpl.java. 7594 // Mem_ptr must be a memory operand, else this node does not get 7595 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7596 // can be rematerialized which leads to errors. 7597 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{ 7598 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); 7599 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7600 ins_encode %{ 7601 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7602 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7603 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(), 7604 noreg, NULL, true); 7605 %} 7606 ins_pipe(pipe_class_default); 7607 %} 7608 7609 // As compareAndSwapP, but return flag register instead of boolean value in 7610 // int register. 7611 // This instruction is matched if UseTLAB is off. 7612 // Mem_ptr must be a memory operand, else this node does not get 7613 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7614 // can be rematerialized which leads to errors. 7615 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ 7616 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal))); 7617 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7618 ins_encode %{ 7619 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7620 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7621 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), 7622 noreg, NULL, true); 7623 %} 7624 ins_pipe(pipe_class_default); 7625 %} 7626 7627 // Implement LoadPLocked. Must be ordered against changes of the memory location 7628 // by storePConditional. 7629 // Don't know whether this is ever used. 7630 instruct loadPLocked(iRegPdst dst, memory mem) %{ 7631 match(Set dst (LoadPLocked mem)); 7632 ins_cost(MEMORY_REF_COST); 7633 7634 format %{ "LD $dst, $mem \t// loadPLocked\n\t" 7635 "TWI $dst\n\t" 7636 "ISYNC" %} 7637 size(12); 7638 ins_encode( enc_ld_ac(dst, mem) ); 7639 ins_pipe(pipe_class_memory); 7640 %} 7641 7642 //----------Compare-And-Swap--------------------------------------------------- 7643 7644 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI 7645 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be 7646 // matched. 7647 7648 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{ 7649 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); 7650 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7651 // Variable size: instruction count smaller if regs are disjoint. 7652 ins_encode %{ 7653 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7654 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7655 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7656 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7657 $res$$Register, true); 7658 %} 7659 ins_pipe(pipe_class_default); 7660 %} 7661 7662 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{ 7663 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); 7664 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7665 // Variable size: instruction count smaller if regs are disjoint. 7666 ins_encode %{ 7667 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7668 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7669 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7670 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7671 $res$$Register, true); 7672 %} 7673 ins_pipe(pipe_class_default); 7674 %} 7675 7676 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{ 7677 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); 7678 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} 7679 // Variable size: instruction count smaller if regs are disjoint. 7680 ins_encode %{ 7681 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7682 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7683 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7684 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7685 $res$$Register, NULL, true); 7686 %} 7687 ins_pipe(pipe_class_default); 7688 %} 7689 7690 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{ 7691 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); 7692 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} 7693 // Variable size: instruction count smaller if regs are disjoint. 7694 ins_encode %{ 7695 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7696 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7697 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7698 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7699 $res$$Register, NULL, true); 7700 %} 7701 ins_pipe(pipe_class_default); 7702 %} 7703 7704 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 7705 match(Set res (GetAndAddI mem_ptr src)); 7706 format %{ "GetAndAddI $res, $mem_ptr, $src" %} 7707 // Variable size: instruction count smaller if regs are disjoint. 7708 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); 7709 ins_pipe(pipe_class_default); 7710 %} 7711 7712 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 7713 match(Set res (GetAndAddL mem_ptr src)); 7714 format %{ "GetAndAddL $res, $mem_ptr, $src" %} 7715 // Variable size: instruction count smaller if regs are disjoint. 7716 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); 7717 ins_pipe(pipe_class_default); 7718 %} 7719 7720 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 7721 match(Set res (GetAndSetI mem_ptr src)); 7722 format %{ "GetAndSetI $res, $mem_ptr, $src" %} 7723 // Variable size: instruction count smaller if regs are disjoint. 7724 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7725 ins_pipe(pipe_class_default); 7726 %} 7727 7728 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 7729 match(Set res (GetAndSetL mem_ptr src)); 7730 format %{ "GetAndSetL $res, $mem_ptr, $src" %} 7731 // Variable size: instruction count smaller if regs are disjoint. 7732 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7733 ins_pipe(pipe_class_default); 7734 %} 7735 7736 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{ 7737 match(Set res (GetAndSetP mem_ptr src)); 7738 format %{ "GetAndSetP $res, $mem_ptr, $src" %} 7739 // Variable size: instruction count smaller if regs are disjoint. 7740 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7741 ins_pipe(pipe_class_default); 7742 %} 7743 7744 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{ 7745 match(Set res (GetAndSetN mem_ptr src)); 7746 format %{ "GetAndSetN $res, $mem_ptr, $src" %} 7747 // Variable size: instruction count smaller if regs are disjoint. 7748 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7749 ins_pipe(pipe_class_default); 7750 %} 7751 7752 //----------Arithmetic Instructions-------------------------------------------- 7753 // Addition Instructions 7754 7755 // Register Addition 7756 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7757 match(Set dst (AddI src1 src2)); 7758 format %{ "ADD $dst, $src1, $src2" %} 7759 size(4); 7760 ins_encode %{ 7761 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7762 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7763 %} 7764 ins_pipe(pipe_class_default); 7765 %} 7766 7767 // Expand does not work with above instruct. (??) 7768 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7769 // no match-rule 7770 effect(DEF dst, USE src1, USE src2); 7771 format %{ "ADD $dst, $src1, $src2" %} 7772 size(4); 7773 ins_encode %{ 7774 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7775 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7776 %} 7777 ins_pipe(pipe_class_default); 7778 %} 7779 7780 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 7781 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); 7782 ins_cost(DEFAULT_COST*3); 7783 7784 expand %{ 7785 // FIXME: we should do this in the ideal world. 7786 iRegIdst tmp1; 7787 iRegIdst tmp2; 7788 addI_reg_reg(tmp1, src1, src2); 7789 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. 7790 addI_reg_reg(dst, tmp1, tmp2); 7791 %} 7792 %} 7793 7794 // Immediate Addition 7795 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7796 match(Set dst (AddI src1 src2)); 7797 format %{ "ADDI $dst, $src1, $src2" %} 7798 size(4); 7799 ins_encode %{ 7800 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7801 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7802 %} 7803 ins_pipe(pipe_class_default); 7804 %} 7805 7806 // Immediate Addition with 16-bit shifted operand 7807 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ 7808 match(Set dst (AddI src1 src2)); 7809 format %{ "ADDIS $dst, $src1, $src2" %} 7810 size(4); 7811 ins_encode %{ 7812 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7813 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7814 %} 7815 ins_pipe(pipe_class_default); 7816 %} 7817 7818 // Long Addition 7819 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7820 match(Set dst (AddL src1 src2)); 7821 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7822 size(4); 7823 ins_encode %{ 7824 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7825 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7826 %} 7827 ins_pipe(pipe_class_default); 7828 %} 7829 7830 // Expand does not work with above instruct. (??) 7831 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7832 // no match-rule 7833 effect(DEF dst, USE src1, USE src2); 7834 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7835 size(4); 7836 ins_encode %{ 7837 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7838 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7839 %} 7840 ins_pipe(pipe_class_default); 7841 %} 7842 7843 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ 7844 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); 7845 ins_cost(DEFAULT_COST*3); 7846 7847 expand %{ 7848 // FIXME: we should do this in the ideal world. 7849 iRegLdst tmp1; 7850 iRegLdst tmp2; 7851 addL_reg_reg(tmp1, src1, src2); 7852 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 7853 addL_reg_reg(dst, tmp1, tmp2); 7854 %} 7855 %} 7856 7857 // AddL + ConvL2I. 7858 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7859 match(Set dst (ConvL2I (AddL src1 src2))); 7860 7861 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} 7862 size(4); 7863 ins_encode %{ 7864 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7865 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7866 %} 7867 ins_pipe(pipe_class_default); 7868 %} 7869 7870 // No constant pool entries required. 7871 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7872 match(Set dst (AddL src1 src2)); 7873 7874 format %{ "ADDI $dst, $src1, $src2" %} 7875 size(4); 7876 ins_encode %{ 7877 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7878 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7879 %} 7880 ins_pipe(pipe_class_default); 7881 %} 7882 7883 // Long Immediate Addition with 16-bit shifted operand. 7884 // No constant pool entries required. 7885 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ 7886 match(Set dst (AddL src1 src2)); 7887 7888 format %{ "ADDIS $dst, $src1, $src2" %} 7889 size(4); 7890 ins_encode %{ 7891 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7892 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7893 %} 7894 ins_pipe(pipe_class_default); 7895 %} 7896 7897 // Pointer Register Addition 7898 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ 7899 match(Set dst (AddP src1 src2)); 7900 format %{ "ADD $dst, $src1, $src2" %} 7901 size(4); 7902 ins_encode %{ 7903 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7904 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7905 %} 7906 ins_pipe(pipe_class_default); 7907 %} 7908 7909 // Pointer Immediate Addition 7910 // No constant pool entries required. 7911 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ 7912 match(Set dst (AddP src1 src2)); 7913 7914 format %{ "ADDI $dst, $src1, $src2" %} 7915 size(4); 7916 ins_encode %{ 7917 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7918 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7919 %} 7920 ins_pipe(pipe_class_default); 7921 %} 7922 7923 // Pointer Immediate Addition with 16-bit shifted operand. 7924 // No constant pool entries required. 7925 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ 7926 match(Set dst (AddP src1 src2)); 7927 7928 format %{ "ADDIS $dst, $src1, $src2" %} 7929 size(4); 7930 ins_encode %{ 7931 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7932 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7933 %} 7934 ins_pipe(pipe_class_default); 7935 %} 7936 7937 //--------------------- 7938 // Subtraction Instructions 7939 7940 // Register Subtraction 7941 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7942 match(Set dst (SubI src1 src2)); 7943 format %{ "SUBF $dst, $src2, $src1" %} 7944 size(4); 7945 ins_encode %{ 7946 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7947 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7948 %} 7949 ins_pipe(pipe_class_default); 7950 %} 7951 7952 // Immediate Subtraction 7953 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal), 7954 // so this rule seems to be unused. 7955 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7956 match(Set dst (SubI src1 src2)); 7957 format %{ "SUBI $dst, $src1, $src2" %} 7958 size(4); 7959 ins_encode %{ 7960 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7961 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); 7962 %} 7963 ins_pipe(pipe_class_default); 7964 %} 7965 7966 // SubI from constant (using subfic). 7967 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ 7968 match(Set dst (SubI src1 src2)); 7969 format %{ "SUBI $dst, $src1, $src2" %} 7970 7971 size(4); 7972 ins_encode %{ 7973 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); 7974 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); 7975 %} 7976 ins_pipe(pipe_class_default); 7977 %} 7978 7979 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for 7980 // positive integers and 0xF...F for negative ones. 7981 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ 7982 // no match-rule, false predicate 7983 effect(DEF dst, USE src); 7984 predicate(false); 7985 7986 format %{ "SRAWI $dst, $src, #31" %} 7987 size(4); 7988 ins_encode %{ 7989 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 7990 __ srawi($dst$$Register, $src$$Register, 0x1f); 7991 %} 7992 ins_pipe(pipe_class_default); 7993 %} 7994 7995 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ 7996 match(Set dst (AbsI src)); 7997 ins_cost(DEFAULT_COST*3); 7998 7999 expand %{ 8000 iRegIdst tmp1; 8001 iRegIdst tmp2; 8002 signmask32I_regI(tmp1, src); 8003 xorI_reg_reg(tmp2, tmp1, src); 8004 subI_reg_reg(dst, tmp2, tmp1); 8005 %} 8006 %} 8007 8008 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ 8009 match(Set dst (SubI zero src2)); 8010 format %{ "NEG $dst, $src2" %} 8011 size(4); 8012 ins_encode %{ 8013 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8014 __ neg($dst$$Register, $src2$$Register); 8015 %} 8016 ins_pipe(pipe_class_default); 8017 %} 8018 8019 // Long subtraction 8020 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8021 match(Set dst (SubL src1 src2)); 8022 format %{ "SUBF $dst, $src2, $src1 \t// long" %} 8023 size(4); 8024 ins_encode %{ 8025 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 8026 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 8027 %} 8028 ins_pipe(pipe_class_default); 8029 %} 8030 8031 // SubL + convL2I. 8032 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8033 match(Set dst (ConvL2I (SubL src1 src2))); 8034 8035 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} 8036 size(4); 8037 ins_encode %{ 8038 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 8039 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 8040 %} 8041 ins_pipe(pipe_class_default); 8042 %} 8043 8044 // Immediate Subtraction 8045 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), 8046 // so this rule seems to be unused. 8047 // No constant pool entries required. 8048 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8049 match(Set dst (SubL src1 src2)); 8050 8051 format %{ "SUBI $dst, $src1, $src2 \t// long" %} 8052 size(4); 8053 ins_encode %{ 8054 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 8055 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); 8056 %} 8057 ins_pipe(pipe_class_default); 8058 %} 8059 8060 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 8061 // positive longs and 0xF...F for negative ones. 8062 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 8063 // no match-rule, false predicate 8064 effect(DEF dst, USE src); 8065 predicate(false); 8066 8067 format %{ "SRADI $dst, $src, #63" %} 8068 size(4); 8069 ins_encode %{ 8070 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8071 __ sradi($dst$$Register, $src$$Register, 0x3f); 8072 %} 8073 ins_pipe(pipe_class_default); 8074 %} 8075 8076 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 8077 // positive longs and 0xF...F for negative ones. 8078 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 8079 // no match-rule, false predicate 8080 effect(DEF dst, USE src); 8081 predicate(false); 8082 8083 format %{ "SRADI $dst, $src, #63" %} 8084 size(4); 8085 ins_encode %{ 8086 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8087 __ sradi($dst$$Register, $src$$Register, 0x3f); 8088 %} 8089 ins_pipe(pipe_class_default); 8090 %} 8091 8092 // Long negation 8093 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ 8094 match(Set dst (SubL zero src2)); 8095 format %{ "NEG $dst, $src2 \t// long" %} 8096 size(4); 8097 ins_encode %{ 8098 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8099 __ neg($dst$$Register, $src2$$Register); 8100 %} 8101 ins_pipe(pipe_class_default); 8102 %} 8103 8104 // NegL + ConvL2I. 8105 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ 8106 match(Set dst (ConvL2I (SubL zero src2))); 8107 8108 format %{ "NEG $dst, $src2 \t// long + l2i" %} 8109 size(4); 8110 ins_encode %{ 8111 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8112 __ neg($dst$$Register, $src2$$Register); 8113 %} 8114 ins_pipe(pipe_class_default); 8115 %} 8116 8117 // Multiplication Instructions 8118 // Integer Multiplication 8119 8120 // Register Multiplication 8121 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8122 match(Set dst (MulI src1 src2)); 8123 ins_cost(DEFAULT_COST); 8124 8125 format %{ "MULLW $dst, $src1, $src2" %} 8126 size(4); 8127 ins_encode %{ 8128 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); 8129 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); 8130 %} 8131 ins_pipe(pipe_class_default); 8132 %} 8133 8134 // Immediate Multiplication 8135 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 8136 match(Set dst (MulI src1 src2)); 8137 ins_cost(DEFAULT_COST); 8138 8139 format %{ "MULLI $dst, $src1, $src2" %} 8140 size(4); 8141 ins_encode %{ 8142 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8143 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8144 %} 8145 ins_pipe(pipe_class_default); 8146 %} 8147 8148 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8149 match(Set dst (MulL src1 src2)); 8150 ins_cost(DEFAULT_COST); 8151 8152 format %{ "MULLD $dst $src1, $src2 \t// long" %} 8153 size(4); 8154 ins_encode %{ 8155 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); 8156 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); 8157 %} 8158 ins_pipe(pipe_class_default); 8159 %} 8160 8161 // Multiply high for optimized long division by constant. 8162 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8163 match(Set dst (MulHiL src1 src2)); 8164 ins_cost(DEFAULT_COST); 8165 8166 format %{ "MULHD $dst $src1, $src2 \t// long" %} 8167 size(4); 8168 ins_encode %{ 8169 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); 8170 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); 8171 %} 8172 ins_pipe(pipe_class_default); 8173 %} 8174 8175 // Immediate Multiplication 8176 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8177 match(Set dst (MulL src1 src2)); 8178 ins_cost(DEFAULT_COST); 8179 8180 format %{ "MULLI $dst, $src1, $src2" %} 8181 size(4); 8182 ins_encode %{ 8183 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8184 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8185 %} 8186 ins_pipe(pipe_class_default); 8187 %} 8188 8189 // Integer Division with Immediate -1: Negate. 8190 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 8191 match(Set dst (DivI src1 src2)); 8192 ins_cost(DEFAULT_COST); 8193 8194 format %{ "NEG $dst, $src1 \t// /-1" %} 8195 size(4); 8196 ins_encode %{ 8197 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8198 __ neg($dst$$Register, $src1$$Register); 8199 %} 8200 ins_pipe(pipe_class_default); 8201 %} 8202 8203 // Integer Division with constant, but not -1. 8204 // We should be able to improve this by checking the type of src2. 8205 // It might well be that src2 is known to be positive. 8206 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8207 match(Set dst (DivI src1 src2)); 8208 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 8209 ins_cost(2*DEFAULT_COST); 8210 8211 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} 8212 size(4); 8213 ins_encode %{ 8214 // TODO: PPC port $archOpcode(ppc64Opcode_divw); 8215 __ divw($dst$$Register, $src1$$Register, $src2$$Register); 8216 %} 8217 ins_pipe(pipe_class_default); 8218 %} 8219 8220 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{ 8221 effect(USE_DEF dst, USE src1, USE crx); 8222 predicate(false); 8223 8224 ins_variable_size_depending_on_alignment(true); 8225 8226 format %{ "CMOVE $dst, neg($src1), $crx" %} 8227 // Worst case is branch + move + stop, no stop without scheduler. 8228 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8229 ins_encode %{ 8230 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8231 Label done; 8232 __ bne($crx$$CondRegister, done); 8233 __ neg($dst$$Register, $src1$$Register); 8234 // TODO PPC port __ endgroup_if_needed(_size == 12); 8235 __ bind(done); 8236 %} 8237 ins_pipe(pipe_class_default); 8238 %} 8239 8240 // Integer Division with Registers not containing constants. 8241 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8242 match(Set dst (DivI src1 src2)); 8243 ins_cost(10*DEFAULT_COST); 8244 8245 expand %{ 8246 immI16 imm %{ (int)-1 %} 8247 flagsReg tmp1; 8248 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8249 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8250 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8251 %} 8252 %} 8253 8254 // Long Division with Immediate -1: Negate. 8255 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 8256 match(Set dst (DivL src1 src2)); 8257 ins_cost(DEFAULT_COST); 8258 8259 format %{ "NEG $dst, $src1 \t// /-1, long" %} 8260 size(4); 8261 ins_encode %{ 8262 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8263 __ neg($dst$$Register, $src1$$Register); 8264 %} 8265 ins_pipe(pipe_class_default); 8266 %} 8267 8268 // Long Division with constant, but not -1. 8269 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8270 match(Set dst (DivL src1 src2)); 8271 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. 8272 ins_cost(2*DEFAULT_COST); 8273 8274 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} 8275 size(4); 8276 ins_encode %{ 8277 // TODO: PPC port $archOpcode(ppc64Opcode_divd); 8278 __ divd($dst$$Register, $src1$$Register, $src2$$Register); 8279 %} 8280 ins_pipe(pipe_class_default); 8281 %} 8282 8283 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{ 8284 effect(USE_DEF dst, USE src1, USE crx); 8285 predicate(false); 8286 8287 ins_variable_size_depending_on_alignment(true); 8288 8289 format %{ "CMOVE $dst, neg($src1), $crx" %} 8290 // Worst case is branch + move + stop, no stop without scheduler. 8291 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8292 ins_encode %{ 8293 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8294 Label done; 8295 __ bne($crx$$CondRegister, done); 8296 __ neg($dst$$Register, $src1$$Register); 8297 // TODO PPC port __ endgroup_if_needed(_size == 12); 8298 __ bind(done); 8299 %} 8300 ins_pipe(pipe_class_default); 8301 %} 8302 8303 // Long Division with Registers not containing constants. 8304 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8305 match(Set dst (DivL src1 src2)); 8306 ins_cost(10*DEFAULT_COST); 8307 8308 expand %{ 8309 immL16 imm %{ (int)-1 %} 8310 flagsReg tmp1; 8311 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8312 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8313 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8314 %} 8315 %} 8316 8317 // Integer Remainder with registers. 8318 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8319 match(Set dst (ModI src1 src2)); 8320 ins_cost(10*DEFAULT_COST); 8321 8322 expand %{ 8323 immI16 imm %{ (int)-1 %} 8324 flagsReg tmp1; 8325 iRegIdst tmp2; 8326 iRegIdst tmp3; 8327 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8328 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8329 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8330 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8331 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8332 %} 8333 %} 8334 8335 // Long Remainder with registers 8336 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ 8337 match(Set dst (ModL src1 src2)); 8338 ins_cost(10*DEFAULT_COST); 8339 8340 expand %{ 8341 immL16 imm %{ (int)-1 %} 8342 flagsReg tmp1; 8343 iRegLdst tmp2; 8344 iRegLdst tmp3; 8345 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8346 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8347 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8348 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8349 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8350 %} 8351 %} 8352 8353 // Integer Shift Instructions 8354 8355 // Register Shift Left 8356 8357 // Clear all but the lowest #mask bits. 8358 // Used to normalize shift amounts in registers. 8359 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ 8360 // no match-rule, false predicate 8361 effect(DEF dst, USE src, USE mask); 8362 predicate(false); 8363 8364 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} 8365 size(4); 8366 ins_encode %{ 8367 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8368 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); 8369 %} 8370 ins_pipe(pipe_class_default); 8371 %} 8372 8373 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8374 // no match-rule, false predicate 8375 effect(DEF dst, USE src1, USE src2); 8376 predicate(false); 8377 8378 format %{ "SLW $dst, $src1, $src2" %} 8379 size(4); 8380 ins_encode %{ 8381 // TODO: PPC port $archOpcode(ppc64Opcode_slw); 8382 __ slw($dst$$Register, $src1$$Register, $src2$$Register); 8383 %} 8384 ins_pipe(pipe_class_default); 8385 %} 8386 8387 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8388 match(Set dst (LShiftI src1 src2)); 8389 ins_cost(DEFAULT_COST*2); 8390 expand %{ 8391 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8392 iRegIdst tmpI; 8393 maskI_reg_imm(tmpI, src2, mask); 8394 lShiftI_reg_reg(dst, src1, tmpI); 8395 %} 8396 %} 8397 8398 // Register Shift Left Immediate 8399 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8400 match(Set dst (LShiftI src1 src2)); 8401 8402 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} 8403 size(4); 8404 ins_encode %{ 8405 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8406 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8407 %} 8408 ins_pipe(pipe_class_default); 8409 %} 8410 8411 // AndI with negpow2-constant + LShiftI 8412 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8413 match(Set dst (LShiftI (AndI src1 src2) src3)); 8414 predicate(UseRotateAndMaskInstructionsPPC64); 8415 8416 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} 8417 size(4); 8418 ins_encode %{ 8419 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8420 long src2 = $src2$$constant; 8421 long src3 = $src3$$constant; 8422 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8423 if (maskbits >= 32) { 8424 __ li($dst$$Register, 0); // addi 8425 } else { 8426 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); 8427 } 8428 %} 8429 ins_pipe(pipe_class_default); 8430 %} 8431 8432 // RShiftI + AndI with negpow2-constant + LShiftI 8433 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8434 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); 8435 predicate(UseRotateAndMaskInstructionsPPC64); 8436 8437 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} 8438 size(4); 8439 ins_encode %{ 8440 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8441 long src2 = $src2$$constant; 8442 long src3 = $src3$$constant; 8443 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8444 if (maskbits >= 32) { 8445 __ li($dst$$Register, 0); // addi 8446 } else { 8447 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); 8448 } 8449 %} 8450 ins_pipe(pipe_class_default); 8451 %} 8452 8453 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8454 // no match-rule, false predicate 8455 effect(DEF dst, USE src1, USE src2); 8456 predicate(false); 8457 8458 format %{ "SLD $dst, $src1, $src2" %} 8459 size(4); 8460 ins_encode %{ 8461 // TODO: PPC port $archOpcode(ppc64Opcode_sld); 8462 __ sld($dst$$Register, $src1$$Register, $src2$$Register); 8463 %} 8464 ins_pipe(pipe_class_default); 8465 %} 8466 8467 // Register Shift Left 8468 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8469 match(Set dst (LShiftL src1 src2)); 8470 ins_cost(DEFAULT_COST*2); 8471 expand %{ 8472 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8473 iRegIdst tmpI; 8474 maskI_reg_imm(tmpI, src2, mask); 8475 lShiftL_regL_regI(dst, src1, tmpI); 8476 %} 8477 %} 8478 8479 // Register Shift Left Immediate 8480 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8481 match(Set dst (LShiftL src1 src2)); 8482 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} 8483 size(4); 8484 ins_encode %{ 8485 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8486 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8487 %} 8488 ins_pipe(pipe_class_default); 8489 %} 8490 8491 // If we shift more than 32 bits, we need not convert I2L. 8492 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ 8493 match(Set dst (LShiftL (ConvI2L src1) src2)); 8494 ins_cost(DEFAULT_COST); 8495 8496 size(4); 8497 format %{ "SLDI $dst, i2l($src1), $src2" %} 8498 ins_encode %{ 8499 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8500 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8501 %} 8502 ins_pipe(pipe_class_default); 8503 %} 8504 8505 // Shift a postivie int to the left. 8506 // Clrlsldi clears the upper 32 bits and shifts. 8507 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ 8508 match(Set dst (LShiftL (ConvI2L src1) src2)); 8509 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); 8510 8511 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} 8512 size(4); 8513 ins_encode %{ 8514 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); 8515 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); 8516 %} 8517 ins_pipe(pipe_class_default); 8518 %} 8519 8520 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8521 // no match-rule, false predicate 8522 effect(DEF dst, USE src1, USE src2); 8523 predicate(false); 8524 8525 format %{ "SRAW $dst, $src1, $src2" %} 8526 size(4); 8527 ins_encode %{ 8528 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); 8529 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); 8530 %} 8531 ins_pipe(pipe_class_default); 8532 %} 8533 8534 // Register Arithmetic Shift Right 8535 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8536 match(Set dst (RShiftI src1 src2)); 8537 ins_cost(DEFAULT_COST*2); 8538 expand %{ 8539 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8540 iRegIdst tmpI; 8541 maskI_reg_imm(tmpI, src2, mask); 8542 arShiftI_reg_reg(dst, src1, tmpI); 8543 %} 8544 %} 8545 8546 // Register Arithmetic Shift Right Immediate 8547 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8548 match(Set dst (RShiftI src1 src2)); 8549 8550 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} 8551 size(4); 8552 ins_encode %{ 8553 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 8554 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8555 %} 8556 ins_pipe(pipe_class_default); 8557 %} 8558 8559 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8560 // no match-rule, false predicate 8561 effect(DEF dst, USE src1, USE src2); 8562 predicate(false); 8563 8564 format %{ "SRAD $dst, $src1, $src2" %} 8565 size(4); 8566 ins_encode %{ 8567 // TODO: PPC port $archOpcode(ppc64Opcode_srad); 8568 __ srad($dst$$Register, $src1$$Register, $src2$$Register); 8569 %} 8570 ins_pipe(pipe_class_default); 8571 %} 8572 8573 // Register Shift Right Arithmetic Long 8574 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8575 match(Set dst (RShiftL src1 src2)); 8576 ins_cost(DEFAULT_COST*2); 8577 8578 expand %{ 8579 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8580 iRegIdst tmpI; 8581 maskI_reg_imm(tmpI, src2, mask); 8582 arShiftL_regL_regI(dst, src1, tmpI); 8583 %} 8584 %} 8585 8586 // Register Shift Right Immediate 8587 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8588 match(Set dst (RShiftL src1 src2)); 8589 8590 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} 8591 size(4); 8592 ins_encode %{ 8593 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8594 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8595 %} 8596 ins_pipe(pipe_class_default); 8597 %} 8598 8599 // RShiftL + ConvL2I 8600 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8601 match(Set dst (ConvL2I (RShiftL src1 src2))); 8602 8603 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8604 size(4); 8605 ins_encode %{ 8606 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8607 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8608 %} 8609 ins_pipe(pipe_class_default); 8610 %} 8611 8612 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8613 // no match-rule, false predicate 8614 effect(DEF dst, USE src1, USE src2); 8615 predicate(false); 8616 8617 format %{ "SRW $dst, $src1, $src2" %} 8618 size(4); 8619 ins_encode %{ 8620 // TODO: PPC port $archOpcode(ppc64Opcode_srw); 8621 __ srw($dst$$Register, $src1$$Register, $src2$$Register); 8622 %} 8623 ins_pipe(pipe_class_default); 8624 %} 8625 8626 // Register Shift Right 8627 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8628 match(Set dst (URShiftI src1 src2)); 8629 ins_cost(DEFAULT_COST*2); 8630 8631 expand %{ 8632 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8633 iRegIdst tmpI; 8634 maskI_reg_imm(tmpI, src2, mask); 8635 urShiftI_reg_reg(dst, src1, tmpI); 8636 %} 8637 %} 8638 8639 // Register Shift Right Immediate 8640 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8641 match(Set dst (URShiftI src1 src2)); 8642 8643 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} 8644 size(4); 8645 ins_encode %{ 8646 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8647 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8648 %} 8649 ins_pipe(pipe_class_default); 8650 %} 8651 8652 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8653 // no match-rule, false predicate 8654 effect(DEF dst, USE src1, USE src2); 8655 predicate(false); 8656 8657 format %{ "SRD $dst, $src1, $src2" %} 8658 size(4); 8659 ins_encode %{ 8660 // TODO: PPC port $archOpcode(ppc64Opcode_srd); 8661 __ srd($dst$$Register, $src1$$Register, $src2$$Register); 8662 %} 8663 ins_pipe(pipe_class_default); 8664 %} 8665 8666 // Register Shift Right 8667 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8668 match(Set dst (URShiftL src1 src2)); 8669 ins_cost(DEFAULT_COST*2); 8670 8671 expand %{ 8672 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8673 iRegIdst tmpI; 8674 maskI_reg_imm(tmpI, src2, mask); 8675 urShiftL_regL_regI(dst, src1, tmpI); 8676 %} 8677 %} 8678 8679 // Register Shift Right Immediate 8680 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8681 match(Set dst (URShiftL src1 src2)); 8682 8683 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} 8684 size(4); 8685 ins_encode %{ 8686 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8687 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8688 %} 8689 ins_pipe(pipe_class_default); 8690 %} 8691 8692 // URShiftL + ConvL2I. 8693 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8694 match(Set dst (ConvL2I (URShiftL src1 src2))); 8695 8696 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8697 size(4); 8698 ins_encode %{ 8699 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8700 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8701 %} 8702 ins_pipe(pipe_class_default); 8703 %} 8704 8705 // Register Shift Right Immediate with a CastP2X 8706 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ 8707 match(Set dst (URShiftL (CastP2X src1) src2)); 8708 8709 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8710 size(4); 8711 ins_encode %{ 8712 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8713 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8714 %} 8715 ins_pipe(pipe_class_default); 8716 %} 8717 8718 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8719 match(Set dst (ConvL2I (ConvI2L src))); 8720 8721 format %{ "EXTSW $dst, $src \t// int->int" %} 8722 size(4); 8723 ins_encode %{ 8724 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 8725 __ extsw($dst$$Register, $src$$Register); 8726 %} 8727 ins_pipe(pipe_class_default); 8728 %} 8729 8730 //----------Rotate Instructions------------------------------------------------ 8731 8732 // Rotate Left by 8-bit immediate 8733 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ 8734 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 8735 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8736 8737 format %{ "ROTLWI $dst, $src, $lshift" %} 8738 size(4); 8739 ins_encode %{ 8740 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8741 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); 8742 %} 8743 ins_pipe(pipe_class_default); 8744 %} 8745 8746 // Rotate Right by 8-bit immediate 8747 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ 8748 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 8749 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8750 8751 format %{ "ROTRWI $dst, $rshift" %} 8752 size(4); 8753 ins_encode %{ 8754 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8755 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); 8756 %} 8757 ins_pipe(pipe_class_default); 8758 %} 8759 8760 //----------Floating Point Arithmetic Instructions----------------------------- 8761 8762 // Add float single precision 8763 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 8764 match(Set dst (AddF src1 src2)); 8765 8766 format %{ "FADDS $dst, $src1, $src2" %} 8767 size(4); 8768 ins_encode %{ 8769 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); 8770 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8771 %} 8772 ins_pipe(pipe_class_default); 8773 %} 8774 8775 // Add float double precision 8776 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 8777 match(Set dst (AddD src1 src2)); 8778 8779 format %{ "FADD $dst, $src1, $src2" %} 8780 size(4); 8781 ins_encode %{ 8782 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); 8783 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8784 %} 8785 ins_pipe(pipe_class_default); 8786 %} 8787 8788 // Sub float single precision 8789 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 8790 match(Set dst (SubF src1 src2)); 8791 8792 format %{ "FSUBS $dst, $src1, $src2" %} 8793 size(4); 8794 ins_encode %{ 8795 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); 8796 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8797 %} 8798 ins_pipe(pipe_class_default); 8799 %} 8800 8801 // Sub float double precision 8802 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 8803 match(Set dst (SubD src1 src2)); 8804 format %{ "FSUB $dst, $src1, $src2" %} 8805 size(4); 8806 ins_encode %{ 8807 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); 8808 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8809 %} 8810 ins_pipe(pipe_class_default); 8811 %} 8812 8813 // Mul float single precision 8814 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 8815 match(Set dst (MulF src1 src2)); 8816 format %{ "FMULS $dst, $src1, $src2" %} 8817 size(4); 8818 ins_encode %{ 8819 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); 8820 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8821 %} 8822 ins_pipe(pipe_class_default); 8823 %} 8824 8825 // Mul float double precision 8826 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 8827 match(Set dst (MulD src1 src2)); 8828 format %{ "FMUL $dst, $src1, $src2" %} 8829 size(4); 8830 ins_encode %{ 8831 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); 8832 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8833 %} 8834 ins_pipe(pipe_class_default); 8835 %} 8836 8837 // Div float single precision 8838 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 8839 match(Set dst (DivF src1 src2)); 8840 format %{ "FDIVS $dst, $src1, $src2" %} 8841 size(4); 8842 ins_encode %{ 8843 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); 8844 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8845 %} 8846 ins_pipe(pipe_class_default); 8847 %} 8848 8849 // Div float double precision 8850 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 8851 match(Set dst (DivD src1 src2)); 8852 format %{ "FDIV $dst, $src1, $src2" %} 8853 size(4); 8854 ins_encode %{ 8855 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); 8856 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8857 %} 8858 ins_pipe(pipe_class_default); 8859 %} 8860 8861 // Absolute float single precision 8862 instruct absF_reg(regF dst, regF src) %{ 8863 match(Set dst (AbsF src)); 8864 format %{ "FABS $dst, $src \t// float" %} 8865 size(4); 8866 ins_encode %{ 8867 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8868 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8869 %} 8870 ins_pipe(pipe_class_default); 8871 %} 8872 8873 // Absolute float double precision 8874 instruct absD_reg(regD dst, regD src) %{ 8875 match(Set dst (AbsD src)); 8876 format %{ "FABS $dst, $src \t// double" %} 8877 size(4); 8878 ins_encode %{ 8879 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8880 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8881 %} 8882 ins_pipe(pipe_class_default); 8883 %} 8884 8885 instruct negF_reg(regF dst, regF src) %{ 8886 match(Set dst (NegF src)); 8887 format %{ "FNEG $dst, $src \t// float" %} 8888 size(4); 8889 ins_encode %{ 8890 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8891 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8892 %} 8893 ins_pipe(pipe_class_default); 8894 %} 8895 8896 instruct negD_reg(regD dst, regD src) %{ 8897 match(Set dst (NegD src)); 8898 format %{ "FNEG $dst, $src \t// double" %} 8899 size(4); 8900 ins_encode %{ 8901 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8902 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8903 %} 8904 ins_pipe(pipe_class_default); 8905 %} 8906 8907 // AbsF + NegF. 8908 instruct negF_absF_reg(regF dst, regF src) %{ 8909 match(Set dst (NegF (AbsF src))); 8910 format %{ "FNABS $dst, $src \t// float" %} 8911 size(4); 8912 ins_encode %{ 8913 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8914 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8915 %} 8916 ins_pipe(pipe_class_default); 8917 %} 8918 8919 // AbsD + NegD. 8920 instruct negD_absD_reg(regD dst, regD src) %{ 8921 match(Set dst (NegD (AbsD src))); 8922 format %{ "FNABS $dst, $src \t// double" %} 8923 size(4); 8924 ins_encode %{ 8925 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8926 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8927 %} 8928 ins_pipe(pipe_class_default); 8929 %} 8930 8931 // VM_Version::has_fsqrt() decides if this node will be used. 8932 // Sqrt float double precision 8933 instruct sqrtD_reg(regD dst, regD src) %{ 8934 match(Set dst (SqrtD src)); 8935 format %{ "FSQRT $dst, $src" %} 8936 size(4); 8937 ins_encode %{ 8938 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); 8939 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); 8940 %} 8941 ins_pipe(pipe_class_default); 8942 %} 8943 8944 // Single-precision sqrt. 8945 instruct sqrtF_reg(regF dst, regF src) %{ 8946 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8947 predicate(VM_Version::has_fsqrts()); 8948 ins_cost(DEFAULT_COST); 8949 8950 format %{ "FSQRTS $dst, $src" %} 8951 size(4); 8952 ins_encode %{ 8953 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); 8954 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); 8955 %} 8956 ins_pipe(pipe_class_default); 8957 %} 8958 8959 instruct roundDouble_nop(regD dst) %{ 8960 match(Set dst (RoundDouble dst)); 8961 ins_cost(0); 8962 8963 format %{ " -- \t// RoundDouble not needed - empty" %} 8964 size(0); 8965 // PPC results are already "rounded" (i.e., normal-format IEEE). 8966 ins_encode( /*empty*/ ); 8967 ins_pipe(pipe_class_default); 8968 %} 8969 8970 instruct roundFloat_nop(regF dst) %{ 8971 match(Set dst (RoundFloat dst)); 8972 ins_cost(0); 8973 8974 format %{ " -- \t// RoundFloat not needed - empty" %} 8975 size(0); 8976 // PPC results are already "rounded" (i.e., normal-format IEEE). 8977 ins_encode( /*empty*/ ); 8978 ins_pipe(pipe_class_default); 8979 %} 8980 8981 //----------Logical Instructions----------------------------------------------- 8982 8983 // And Instructions 8984 8985 // Register And 8986 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8987 match(Set dst (AndI src1 src2)); 8988 format %{ "AND $dst, $src1, $src2" %} 8989 size(4); 8990 ins_encode %{ 8991 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8992 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8993 %} 8994 ins_pipe(pipe_class_default); 8995 %} 8996 8997 // Immediate And 8998 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ 8999 match(Set dst (AndI src1 src2)); 9000 effect(KILL cr0); 9001 9002 format %{ "ANDI $dst, $src1, $src2" %} 9003 size(4); 9004 ins_encode %{ 9005 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 9006 // FIXME: avoid andi_ ? 9007 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 9008 %} 9009 ins_pipe(pipe_class_default); 9010 %} 9011 9012 // Immediate And where the immediate is a negative power of 2. 9013 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ 9014 match(Set dst (AndI src1 src2)); 9015 format %{ "ANDWI $dst, $src1, $src2" %} 9016 size(4); 9017 ins_encode %{ 9018 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 9019 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); 9020 %} 9021 ins_pipe(pipe_class_default); 9022 %} 9023 9024 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ 9025 match(Set dst (AndI src1 src2)); 9026 format %{ "ANDWI $dst, $src1, $src2" %} 9027 size(4); 9028 ins_encode %{ 9029 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9030 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 9031 %} 9032 ins_pipe(pipe_class_default); 9033 %} 9034 9035 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ 9036 match(Set dst (AndI src1 src2)); 9037 predicate(UseRotateAndMaskInstructionsPPC64); 9038 format %{ "ANDWI $dst, $src1, $src2" %} 9039 size(4); 9040 ins_encode %{ 9041 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9042 __ rlwinm($dst$$Register, $src1$$Register, 0, 9043 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 9044 %} 9045 ins_pipe(pipe_class_default); 9046 %} 9047 9048 // Register And Long 9049 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9050 match(Set dst (AndL src1 src2)); 9051 ins_cost(DEFAULT_COST); 9052 9053 format %{ "AND $dst, $src1, $src2 \t// long" %} 9054 size(4); 9055 ins_encode %{ 9056 // TODO: PPC port $archOpcode(ppc64Opcode_and); 9057 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 9058 %} 9059 ins_pipe(pipe_class_default); 9060 %} 9061 9062 // Immediate And long 9063 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ 9064 match(Set dst (AndL src1 src2)); 9065 effect(KILL cr0); 9066 ins_cost(DEFAULT_COST); 9067 9068 format %{ "ANDI $dst, $src1, $src2 \t// long" %} 9069 size(4); 9070 ins_encode %{ 9071 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 9072 // FIXME: avoid andi_ ? 9073 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 9074 %} 9075 ins_pipe(pipe_class_default); 9076 %} 9077 9078 // Immediate And Long where the immediate is a negative power of 2. 9079 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ 9080 match(Set dst (AndL src1 src2)); 9081 format %{ "ANDDI $dst, $src1, $src2" %} 9082 size(4); 9083 ins_encode %{ 9084 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 9085 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); 9086 %} 9087 ins_pipe(pipe_class_default); 9088 %} 9089 9090 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 9091 match(Set dst (AndL src1 src2)); 9092 format %{ "ANDDI $dst, $src1, $src2" %} 9093 size(4); 9094 ins_encode %{ 9095 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9096 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 9097 %} 9098 ins_pipe(pipe_class_default); 9099 %} 9100 9101 // AndL + ConvL2I. 9102 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 9103 match(Set dst (ConvL2I (AndL src1 src2))); 9104 ins_cost(DEFAULT_COST); 9105 9106 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} 9107 size(4); 9108 ins_encode %{ 9109 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9110 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 9111 %} 9112 ins_pipe(pipe_class_default); 9113 %} 9114 9115 // Or Instructions 9116 9117 // Register Or 9118 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9119 match(Set dst (OrI src1 src2)); 9120 format %{ "OR $dst, $src1, $src2" %} 9121 size(4); 9122 ins_encode %{ 9123 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9124 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9125 %} 9126 ins_pipe(pipe_class_default); 9127 %} 9128 9129 // Expand does not work with above instruct. (??) 9130 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9131 // no match-rule 9132 effect(DEF dst, USE src1, USE src2); 9133 format %{ "OR $dst, $src1, $src2" %} 9134 size(4); 9135 ins_encode %{ 9136 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9137 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9138 %} 9139 ins_pipe(pipe_class_default); 9140 %} 9141 9142 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9143 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); 9144 ins_cost(DEFAULT_COST*3); 9145 9146 expand %{ 9147 // FIXME: we should do this in the ideal world. 9148 iRegIdst tmp1; 9149 iRegIdst tmp2; 9150 orI_reg_reg(tmp1, src1, src2); 9151 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 9152 orI_reg_reg(dst, tmp1, tmp2); 9153 %} 9154 %} 9155 9156 // Immediate Or 9157 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9158 match(Set dst (OrI src1 src2)); 9159 format %{ "ORI $dst, $src1, $src2" %} 9160 size(4); 9161 ins_encode %{ 9162 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9163 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 9164 %} 9165 ins_pipe(pipe_class_default); 9166 %} 9167 9168 // Register Or Long 9169 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9170 match(Set dst (OrL src1 src2)); 9171 ins_cost(DEFAULT_COST); 9172 9173 size(4); 9174 format %{ "OR $dst, $src1, $src2 \t// long" %} 9175 ins_encode %{ 9176 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9177 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9178 %} 9179 ins_pipe(pipe_class_default); 9180 %} 9181 9182 // OrL + ConvL2I. 9183 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9184 match(Set dst (ConvL2I (OrL src1 src2))); 9185 ins_cost(DEFAULT_COST); 9186 9187 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} 9188 size(4); 9189 ins_encode %{ 9190 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9191 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9192 %} 9193 ins_pipe(pipe_class_default); 9194 %} 9195 9196 // Immediate Or long 9197 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ 9198 match(Set dst (OrL src1 con)); 9199 ins_cost(DEFAULT_COST); 9200 9201 format %{ "ORI $dst, $src1, $con \t// long" %} 9202 size(4); 9203 ins_encode %{ 9204 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9205 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); 9206 %} 9207 ins_pipe(pipe_class_default); 9208 %} 9209 9210 // Xor Instructions 9211 9212 // Register Xor 9213 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9214 match(Set dst (XorI src1 src2)); 9215 format %{ "XOR $dst, $src1, $src2" %} 9216 size(4); 9217 ins_encode %{ 9218 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9219 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9220 %} 9221 ins_pipe(pipe_class_default); 9222 %} 9223 9224 // Expand does not work with above instruct. (??) 9225 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9226 // no match-rule 9227 effect(DEF dst, USE src1, USE src2); 9228 format %{ "XOR $dst, $src1, $src2" %} 9229 size(4); 9230 ins_encode %{ 9231 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9232 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9233 %} 9234 ins_pipe(pipe_class_default); 9235 %} 9236 9237 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9238 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); 9239 ins_cost(DEFAULT_COST*3); 9240 9241 expand %{ 9242 // FIXME: we should do this in the ideal world. 9243 iRegIdst tmp1; 9244 iRegIdst tmp2; 9245 xorI_reg_reg(tmp1, src1, src2); 9246 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. 9247 xorI_reg_reg(dst, tmp1, tmp2); 9248 %} 9249 %} 9250 9251 // Immediate Xor 9252 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9253 match(Set dst (XorI src1 src2)); 9254 format %{ "XORI $dst, $src1, $src2" %} 9255 size(4); 9256 ins_encode %{ 9257 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9258 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9259 %} 9260 ins_pipe(pipe_class_default); 9261 %} 9262 9263 // Register Xor Long 9264 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9265 match(Set dst (XorL src1 src2)); 9266 ins_cost(DEFAULT_COST); 9267 9268 format %{ "XOR $dst, $src1, $src2 \t// long" %} 9269 size(4); 9270 ins_encode %{ 9271 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9272 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9273 %} 9274 ins_pipe(pipe_class_default); 9275 %} 9276 9277 // XorL + ConvL2I. 9278 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9279 match(Set dst (ConvL2I (XorL src1 src2))); 9280 ins_cost(DEFAULT_COST); 9281 9282 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} 9283 size(4); 9284 ins_encode %{ 9285 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9286 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9287 %} 9288 ins_pipe(pipe_class_default); 9289 %} 9290 9291 // Immediate Xor Long 9292 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ 9293 match(Set dst (XorL src1 src2)); 9294 ins_cost(DEFAULT_COST); 9295 9296 format %{ "XORI $dst, $src1, $src2 \t// long" %} 9297 size(4); 9298 ins_encode %{ 9299 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9300 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9301 %} 9302 ins_pipe(pipe_class_default); 9303 %} 9304 9305 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 9306 match(Set dst (XorI src1 src2)); 9307 ins_cost(DEFAULT_COST); 9308 9309 format %{ "NOT $dst, $src1 ($src2)" %} 9310 size(4); 9311 ins_encode %{ 9312 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9313 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9314 %} 9315 ins_pipe(pipe_class_default); 9316 %} 9317 9318 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 9319 match(Set dst (XorL src1 src2)); 9320 ins_cost(DEFAULT_COST); 9321 9322 format %{ "NOT $dst, $src1 ($src2) \t// long" %} 9323 size(4); 9324 ins_encode %{ 9325 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9326 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9327 %} 9328 ins_pipe(pipe_class_default); 9329 %} 9330 9331 // And-complement 9332 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ 9333 match(Set dst (AndI (XorI src1 src2) src3)); 9334 ins_cost(DEFAULT_COST); 9335 9336 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} 9337 size(4); 9338 ins_encode( enc_andc(dst, src3, src1) ); 9339 ins_pipe(pipe_class_default); 9340 %} 9341 9342 // And-complement 9343 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9344 // no match-rule, false predicate 9345 effect(DEF dst, USE src1, USE src2); 9346 predicate(false); 9347 9348 format %{ "ANDC $dst, $src1, $src2" %} 9349 size(4); 9350 ins_encode %{ 9351 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 9352 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 9353 %} 9354 ins_pipe(pipe_class_default); 9355 %} 9356 9357 //----------Moves between int/long and float/double---------------------------- 9358 // 9359 // The following rules move values from int/long registers/stack-locations 9360 // to float/double registers/stack-locations and vice versa, without doing any 9361 // conversions. These rules are used to implement the bit-conversion methods 9362 // of java.lang.Float etc., e.g. 9363 // int floatToIntBits(float value) 9364 // float intBitsToFloat(int bits) 9365 // 9366 // Notes on the implementation on ppc64: 9367 // We only provide rules which move between a register and a stack-location, 9368 // because we always have to go through memory when moving between a float 9369 // register and an integer register. 9370 9371 //---------- Chain stack slots between similar types -------- 9372 9373 // These are needed so that the rules below can match. 9374 9375 // Load integer from stack slot 9376 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ 9377 match(Set dst src); 9378 ins_cost(MEMORY_REF_COST); 9379 9380 format %{ "LWZ $dst, $src" %} 9381 size(4); 9382 ins_encode( enc_lwz(dst, src) ); 9383 ins_pipe(pipe_class_memory); 9384 %} 9385 9386 // Store integer to stack slot 9387 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ 9388 match(Set dst src); 9389 ins_cost(MEMORY_REF_COST); 9390 9391 format %{ "STW $src, $dst \t// stk" %} 9392 size(4); 9393 ins_encode( enc_stw(src, dst) ); // rs=rt 9394 ins_pipe(pipe_class_memory); 9395 %} 9396 9397 // Load long from stack slot 9398 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ 9399 match(Set dst src); 9400 ins_cost(MEMORY_REF_COST); 9401 9402 format %{ "LD $dst, $src \t// long" %} 9403 size(4); 9404 ins_encode( enc_ld(dst, src) ); 9405 ins_pipe(pipe_class_memory); 9406 %} 9407 9408 // Store long to stack slot 9409 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ 9410 match(Set dst src); 9411 ins_cost(MEMORY_REF_COST); 9412 9413 format %{ "STD $src, $dst \t// long" %} 9414 size(4); 9415 ins_encode( enc_std(src, dst) ); // rs=rt 9416 ins_pipe(pipe_class_memory); 9417 %} 9418 9419 //----------Moves between int and float 9420 9421 // Move float value from float stack-location to integer register. 9422 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ 9423 match(Set dst (MoveF2I src)); 9424 ins_cost(MEMORY_REF_COST); 9425 9426 format %{ "LWZ $dst, $src \t// MoveF2I" %} 9427 size(4); 9428 ins_encode( enc_lwz(dst, src) ); 9429 ins_pipe(pipe_class_memory); 9430 %} 9431 9432 // Move float value from float register to integer stack-location. 9433 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ 9434 match(Set dst (MoveF2I src)); 9435 ins_cost(MEMORY_REF_COST); 9436 9437 format %{ "STFS $src, $dst \t// MoveF2I" %} 9438 size(4); 9439 ins_encode( enc_stfs(src, dst) ); 9440 ins_pipe(pipe_class_memory); 9441 %} 9442 9443 // Move integer value from integer stack-location to float register. 9444 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ 9445 match(Set dst (MoveI2F src)); 9446 ins_cost(MEMORY_REF_COST); 9447 9448 format %{ "LFS $dst, $src \t// MoveI2F" %} 9449 size(4); 9450 ins_encode %{ 9451 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 9452 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); 9453 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); 9454 %} 9455 ins_pipe(pipe_class_memory); 9456 %} 9457 9458 // Move integer value from integer register to float stack-location. 9459 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ 9460 match(Set dst (MoveI2F src)); 9461 ins_cost(MEMORY_REF_COST); 9462 9463 format %{ "STW $src, $dst \t// MoveI2F" %} 9464 size(4); 9465 ins_encode( enc_stw(src, dst) ); 9466 ins_pipe(pipe_class_memory); 9467 %} 9468 9469 //----------Moves between long and float 9470 9471 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ 9472 // no match-rule, false predicate 9473 effect(DEF dst, USE src); 9474 predicate(false); 9475 9476 format %{ "storeD $src, $dst \t// STACK" %} 9477 size(4); 9478 ins_encode( enc_stfd(src, dst) ); 9479 ins_pipe(pipe_class_default); 9480 %} 9481 9482 //----------Moves between long and double 9483 9484 // Move double value from double stack-location to long register. 9485 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ 9486 match(Set dst (MoveD2L src)); 9487 ins_cost(MEMORY_REF_COST); 9488 size(4); 9489 format %{ "LD $dst, $src \t// MoveD2L" %} 9490 ins_encode( enc_ld(dst, src) ); 9491 ins_pipe(pipe_class_memory); 9492 %} 9493 9494 // Move double value from double register to long stack-location. 9495 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ 9496 match(Set dst (MoveD2L src)); 9497 effect(DEF dst, USE src); 9498 ins_cost(MEMORY_REF_COST); 9499 9500 format %{ "STFD $src, $dst \t// MoveD2L" %} 9501 size(4); 9502 ins_encode( enc_stfd(src, dst) ); 9503 ins_pipe(pipe_class_memory); 9504 %} 9505 9506 // Move long value from long stack-location to double register. 9507 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ 9508 match(Set dst (MoveL2D src)); 9509 ins_cost(MEMORY_REF_COST); 9510 9511 format %{ "LFD $dst, $src \t// MoveL2D" %} 9512 size(4); 9513 ins_encode( enc_lfd(dst, src) ); 9514 ins_pipe(pipe_class_memory); 9515 %} 9516 9517 // Move long value from long register to double stack-location. 9518 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ 9519 match(Set dst (MoveL2D src)); 9520 ins_cost(MEMORY_REF_COST); 9521 9522 format %{ "STD $src, $dst \t// MoveL2D" %} 9523 size(4); 9524 ins_encode( enc_std(src, dst) ); 9525 ins_pipe(pipe_class_memory); 9526 %} 9527 9528 //----------Register Move Instructions----------------------------------------- 9529 9530 // Replicate for Superword 9531 9532 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ 9533 predicate(false); 9534 effect(DEF dst, USE src); 9535 9536 format %{ "MR $dst, $src \t// replicate " %} 9537 // variable size, 0 or 4. 9538 ins_encode %{ 9539 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9540 __ mr_if_needed($dst$$Register, $src$$Register); 9541 %} 9542 ins_pipe(pipe_class_default); 9543 %} 9544 9545 //----------Cast instructions (Java-level type cast)--------------------------- 9546 9547 // Cast Long to Pointer for unsafe natives. 9548 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ 9549 match(Set dst (CastX2P src)); 9550 9551 format %{ "MR $dst, $src \t// Long->Ptr" %} 9552 // variable size, 0 or 4. 9553 ins_encode %{ 9554 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9555 __ mr_if_needed($dst$$Register, $src$$Register); 9556 %} 9557 ins_pipe(pipe_class_default); 9558 %} 9559 9560 // Cast Pointer to Long for unsafe natives. 9561 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ 9562 match(Set dst (CastP2X src)); 9563 9564 format %{ "MR $dst, $src \t// Ptr->Long" %} 9565 // variable size, 0 or 4. 9566 ins_encode %{ 9567 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9568 __ mr_if_needed($dst$$Register, $src$$Register); 9569 %} 9570 ins_pipe(pipe_class_default); 9571 %} 9572 9573 instruct castPP(iRegPdst dst) %{ 9574 match(Set dst (CastPP dst)); 9575 format %{ " -- \t// castPP of $dst" %} 9576 size(0); 9577 ins_encode( /*empty*/ ); 9578 ins_pipe(pipe_class_default); 9579 %} 9580 9581 instruct castII(iRegIdst dst) %{ 9582 match(Set dst (CastII dst)); 9583 format %{ " -- \t// castII of $dst" %} 9584 size(0); 9585 ins_encode( /*empty*/ ); 9586 ins_pipe(pipe_class_default); 9587 %} 9588 9589 instruct checkCastPP(iRegPdst dst) %{ 9590 match(Set dst (CheckCastPP dst)); 9591 format %{ " -- \t// checkcastPP of $dst" %} 9592 size(0); 9593 ins_encode( /*empty*/ ); 9594 ins_pipe(pipe_class_default); 9595 %} 9596 9597 //----------Convert instructions----------------------------------------------- 9598 9599 // Convert to boolean. 9600 9601 // int_to_bool(src) : { 1 if src != 0 9602 // { 0 else 9603 // 9604 // strategy: 9605 // 1) Count leading zeros of 32 bit-value src, 9606 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. 9607 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9608 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9609 9610 // convI2Bool 9611 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ 9612 match(Set dst (Conv2B src)); 9613 predicate(UseCountLeadingZerosInstructionsPPC64); 9614 ins_cost(DEFAULT_COST); 9615 9616 expand %{ 9617 immI shiftAmount %{ 0x5 %} 9618 uimmI16 mask %{ 0x1 %} 9619 iRegIdst tmp1; 9620 iRegIdst tmp2; 9621 countLeadingZerosI(tmp1, src); 9622 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9623 xorI_reg_uimm16(dst, tmp2, mask); 9624 %} 9625 %} 9626 9627 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ 9628 match(Set dst (Conv2B src)); 9629 effect(TEMP crx); 9630 predicate(!UseCountLeadingZerosInstructionsPPC64); 9631 ins_cost(DEFAULT_COST); 9632 9633 format %{ "CMPWI $crx, $src, #0 \t// convI2B" 9634 "LI $dst, #0\n\t" 9635 "BEQ $crx, done\n\t" 9636 "LI $dst, #1\n" 9637 "done:" %} 9638 size(16); 9639 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); 9640 ins_pipe(pipe_class_compare); 9641 %} 9642 9643 // ConvI2B + XorI 9644 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ 9645 match(Set dst (XorI (Conv2B src) mask)); 9646 predicate(UseCountLeadingZerosInstructionsPPC64); 9647 ins_cost(DEFAULT_COST); 9648 9649 expand %{ 9650 immI shiftAmount %{ 0x5 %} 9651 iRegIdst tmp1; 9652 countLeadingZerosI(tmp1, src); 9653 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9654 %} 9655 %} 9656 9657 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ 9658 match(Set dst (XorI (Conv2B src) mask)); 9659 effect(TEMP crx); 9660 predicate(!UseCountLeadingZerosInstructionsPPC64); 9661 ins_cost(DEFAULT_COST); 9662 9663 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" 9664 "LI $dst, #1\n\t" 9665 "BEQ $crx, done\n\t" 9666 "LI $dst, #0\n" 9667 "done:" %} 9668 size(16); 9669 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); 9670 ins_pipe(pipe_class_compare); 9671 %} 9672 9673 // AndI 0b0..010..0 + ConvI2B 9674 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ 9675 match(Set dst (Conv2B (AndI src mask))); 9676 predicate(UseRotateAndMaskInstructionsPPC64); 9677 ins_cost(DEFAULT_COST); 9678 9679 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} 9680 size(4); 9681 ins_encode %{ 9682 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9683 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); 9684 %} 9685 ins_pipe(pipe_class_default); 9686 %} 9687 9688 // Convert pointer to boolean. 9689 // 9690 // ptr_to_bool(src) : { 1 if src != 0 9691 // { 0 else 9692 // 9693 // strategy: 9694 // 1) Count leading zeros of 64 bit-value src, 9695 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. 9696 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9697 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9698 9699 // ConvP2B 9700 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ 9701 match(Set dst (Conv2B src)); 9702 predicate(UseCountLeadingZerosInstructionsPPC64); 9703 ins_cost(DEFAULT_COST); 9704 9705 expand %{ 9706 immI shiftAmount %{ 0x6 %} 9707 uimmI16 mask %{ 0x1 %} 9708 iRegIdst tmp1; 9709 iRegIdst tmp2; 9710 countLeadingZerosP(tmp1, src); 9711 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9712 xorI_reg_uimm16(dst, tmp2, mask); 9713 %} 9714 %} 9715 9716 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ 9717 match(Set dst (Conv2B src)); 9718 effect(TEMP crx); 9719 predicate(!UseCountLeadingZerosInstructionsPPC64); 9720 ins_cost(DEFAULT_COST); 9721 9722 format %{ "CMPDI $crx, $src, #0 \t// convP2B" 9723 "LI $dst, #0\n\t" 9724 "BEQ $crx, done\n\t" 9725 "LI $dst, #1\n" 9726 "done:" %} 9727 size(16); 9728 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); 9729 ins_pipe(pipe_class_compare); 9730 %} 9731 9732 // ConvP2B + XorI 9733 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ 9734 match(Set dst (XorI (Conv2B src) mask)); 9735 predicate(UseCountLeadingZerosInstructionsPPC64); 9736 ins_cost(DEFAULT_COST); 9737 9738 expand %{ 9739 immI shiftAmount %{ 0x6 %} 9740 iRegIdst tmp1; 9741 countLeadingZerosP(tmp1, src); 9742 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9743 %} 9744 %} 9745 9746 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ 9747 match(Set dst (XorI (Conv2B src) mask)); 9748 effect(TEMP crx); 9749 predicate(!UseCountLeadingZerosInstructionsPPC64); 9750 ins_cost(DEFAULT_COST); 9751 9752 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" 9753 "LI $dst, #1\n\t" 9754 "BEQ $crx, done\n\t" 9755 "LI $dst, #0\n" 9756 "done:" %} 9757 size(16); 9758 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); 9759 ins_pipe(pipe_class_compare); 9760 %} 9761 9762 // if src1 < src2, return -1 else return 0 9763 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9764 match(Set dst (CmpLTMask src1 src2)); 9765 ins_cost(DEFAULT_COST*4); 9766 9767 expand %{ 9768 iRegLdst src1s; 9769 iRegLdst src2s; 9770 iRegLdst diff; 9771 convI2L_reg(src1s, src1); // Ensure proper sign extension. 9772 convI2L_reg(src2s, src2); // Ensure proper sign extension. 9773 subL_reg_reg(diff, src1s, src2s); 9774 // Need to consider >=33 bit result, therefore we need signmaskL. 9775 signmask64I_regL(dst, diff); 9776 %} 9777 %} 9778 9779 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ 9780 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 9781 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} 9782 size(4); 9783 ins_encode %{ 9784 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 9785 __ srawi($dst$$Register, $src1$$Register, 0x1f); 9786 %} 9787 ins_pipe(pipe_class_default); 9788 %} 9789 9790 //----------Arithmetic Conversion Instructions--------------------------------- 9791 9792 // Convert to Byte -- nop 9793 // Convert to Short -- nop 9794 9795 // Convert to Int 9796 9797 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ 9798 match(Set dst (RShiftI (LShiftI src amount) amount)); 9799 format %{ "EXTSB $dst, $src \t// byte->int" %} 9800 size(4); 9801 ins_encode %{ 9802 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 9803 __ extsb($dst$$Register, $src$$Register); 9804 %} 9805 ins_pipe(pipe_class_default); 9806 %} 9807 9808 // LShiftI 16 + RShiftI 16 converts short to int. 9809 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ 9810 match(Set dst (RShiftI (LShiftI src amount) amount)); 9811 format %{ "EXTSH $dst, $src \t// short->int" %} 9812 size(4); 9813 ins_encode %{ 9814 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); 9815 __ extsh($dst$$Register, $src$$Register); 9816 %} 9817 ins_pipe(pipe_class_default); 9818 %} 9819 9820 // ConvL2I + ConvI2L: Sign extend int in long register. 9821 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ 9822 match(Set dst (ConvI2L (ConvL2I src))); 9823 9824 format %{ "EXTSW $dst, $src \t// long->long" %} 9825 size(4); 9826 ins_encode %{ 9827 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9828 __ extsw($dst$$Register, $src$$Register); 9829 %} 9830 ins_pipe(pipe_class_default); 9831 %} 9832 9833 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ 9834 match(Set dst (ConvL2I src)); 9835 format %{ "MR $dst, $src \t// long->int" %} 9836 // variable size, 0 or 4 9837 ins_encode %{ 9838 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9839 __ mr_if_needed($dst$$Register, $src$$Register); 9840 %} 9841 ins_pipe(pipe_class_default); 9842 %} 9843 9844 instruct convD2IRaw_regD(regD dst, regD src) %{ 9845 // no match-rule, false predicate 9846 effect(DEF dst, USE src); 9847 predicate(false); 9848 9849 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} 9850 size(4); 9851 ins_encode %{ 9852 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; 9853 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9854 %} 9855 ins_pipe(pipe_class_default); 9856 %} 9857 9858 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{ 9859 // no match-rule, false predicate 9860 effect(DEF dst, USE crx, USE src); 9861 predicate(false); 9862 9863 ins_variable_size_depending_on_alignment(true); 9864 9865 format %{ "cmovI $crx, $dst, $src" %} 9866 // Worst case is branch + move + stop, no stop without scheduler. 9867 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 9868 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9869 ins_pipe(pipe_class_default); 9870 %} 9871 9872 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{ 9873 // no match-rule, false predicate 9874 effect(DEF dst, USE crx, USE mem); 9875 predicate(false); 9876 9877 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} 9878 postalloc_expand %{ 9879 // 9880 // replaces 9881 // 9882 // region dst crx mem 9883 // \ | | / 9884 // dst=cmovI_bso_stackSlotL_conLvalue0 9885 // 9886 // with 9887 // 9888 // region dst 9889 // \ / 9890 // dst=loadConI16(0) 9891 // | 9892 // ^ region dst crx mem 9893 // | \ | | / 9894 // dst=cmovI_bso_stackSlotL 9895 // 9896 9897 // Create new nodes. 9898 MachNode *m1 = new loadConI16Node(); 9899 MachNode *m2 = new cmovI_bso_stackSlotLNode(); 9900 9901 // inputs for new nodes 9902 m1->add_req(n_region); 9903 m2->add_req(n_region, n_crx, n_mem); 9904 9905 // precedences for new nodes 9906 m2->add_prec(m1); 9907 9908 // operands for new nodes 9909 m1->_opnds[0] = op_dst; 9910 m1->_opnds[1] = new immI16Oper(0); 9911 9912 m2->_opnds[0] = op_dst; 9913 m2->_opnds[1] = op_crx; 9914 m2->_opnds[2] = op_mem; 9915 9916 // registers for new nodes 9917 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9918 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9919 9920 // Insert new nodes. 9921 nodes->push(m1); 9922 nodes->push(m2); 9923 %} 9924 %} 9925 9926 // Double to Int conversion, NaN is mapped to 0. 9927 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ 9928 match(Set dst (ConvD2I src)); 9929 ins_cost(DEFAULT_COST); 9930 9931 expand %{ 9932 regD tmpD; 9933 stackSlotL tmpS; 9934 flagsReg crx; 9935 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9936 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). 9937 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 9938 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9939 %} 9940 %} 9941 9942 instruct convF2IRaw_regF(regF dst, regF src) %{ 9943 // no match-rule, false predicate 9944 effect(DEF dst, USE src); 9945 predicate(false); 9946 9947 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} 9948 size(4); 9949 ins_encode %{ 9950 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9951 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9952 %} 9953 ins_pipe(pipe_class_default); 9954 %} 9955 9956 // Float to Int conversion, NaN is mapped to 0. 9957 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ 9958 match(Set dst (ConvF2I src)); 9959 ins_cost(DEFAULT_COST); 9960 9961 expand %{ 9962 regF tmpF; 9963 stackSlotL tmpS; 9964 flagsReg crx; 9965 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9966 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). 9967 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9968 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9969 %} 9970 %} 9971 9972 // Convert to Long 9973 9974 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ 9975 match(Set dst (ConvI2L src)); 9976 format %{ "EXTSW $dst, $src \t// int->long" %} 9977 size(4); 9978 ins_encode %{ 9979 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9980 __ extsw($dst$$Register, $src$$Register); 9981 %} 9982 ins_pipe(pipe_class_default); 9983 %} 9984 9985 // Zero-extend: convert unsigned int to long (convUI2L). 9986 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ 9987 match(Set dst (AndL (ConvI2L src) mask)); 9988 ins_cost(DEFAULT_COST); 9989 9990 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9991 size(4); 9992 ins_encode %{ 9993 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9994 __ clrldi($dst$$Register, $src$$Register, 32); 9995 %} 9996 ins_pipe(pipe_class_default); 9997 %} 9998 9999 // Zero-extend: convert unsigned int to long in long register. 10000 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ 10001 match(Set dst (AndL src mask)); 10002 ins_cost(DEFAULT_COST); 10003 10004 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 10005 size(4); 10006 ins_encode %{ 10007 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 10008 __ clrldi($dst$$Register, $src$$Register, 32); 10009 %} 10010 ins_pipe(pipe_class_default); 10011 %} 10012 10013 instruct convF2LRaw_regF(regF dst, regF src) %{ 10014 // no match-rule, false predicate 10015 effect(DEF dst, USE src); 10016 predicate(false); 10017 10018 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} 10019 size(4); 10020 ins_encode %{ 10021 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 10022 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 10023 %} 10024 ins_pipe(pipe_class_default); 10025 %} 10026 10027 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{ 10028 // no match-rule, false predicate 10029 effect(DEF dst, USE crx, USE src); 10030 predicate(false); 10031 10032 ins_variable_size_depending_on_alignment(true); 10033 10034 format %{ "cmovL $crx, $dst, $src" %} 10035 // Worst case is branch + move + stop, no stop without scheduler. 10036 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 10037 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 10038 ins_pipe(pipe_class_default); 10039 %} 10040 10041 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{ 10042 // no match-rule, false predicate 10043 effect(DEF dst, USE crx, USE mem); 10044 predicate(false); 10045 10046 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} 10047 postalloc_expand %{ 10048 // 10049 // replaces 10050 // 10051 // region dst crx mem 10052 // \ | | / 10053 // dst=cmovL_bso_stackSlotL_conLvalue0 10054 // 10055 // with 10056 // 10057 // region dst 10058 // \ / 10059 // dst=loadConL16(0) 10060 // | 10061 // ^ region dst crx mem 10062 // | \ | | / 10063 // dst=cmovL_bso_stackSlotL 10064 // 10065 10066 // Create new nodes. 10067 MachNode *m1 = new loadConL16Node(); 10068 MachNode *m2 = new cmovL_bso_stackSlotLNode(); 10069 10070 // inputs for new nodes 10071 m1->add_req(n_region); 10072 m2->add_req(n_region, n_crx, n_mem); 10073 m2->add_prec(m1); 10074 10075 // operands for new nodes 10076 m1->_opnds[0] = op_dst; 10077 m1->_opnds[1] = new immL16Oper(0); 10078 m2->_opnds[0] = op_dst; 10079 m2->_opnds[1] = op_crx; 10080 m2->_opnds[2] = op_mem; 10081 10082 // registers for new nodes 10083 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10084 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10085 10086 // Insert new nodes. 10087 nodes->push(m1); 10088 nodes->push(m2); 10089 %} 10090 %} 10091 10092 // Float to Long conversion, NaN is mapped to 0. 10093 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ 10094 match(Set dst (ConvF2L src)); 10095 ins_cost(DEFAULT_COST); 10096 10097 expand %{ 10098 regF tmpF; 10099 stackSlotL tmpS; 10100 flagsReg crx; 10101 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10102 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). 10103 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 10104 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10105 %} 10106 %} 10107 10108 instruct convD2LRaw_regD(regD dst, regD src) %{ 10109 // no match-rule, false predicate 10110 effect(DEF dst, USE src); 10111 predicate(false); 10112 10113 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} 10114 size(4); 10115 ins_encode %{ 10116 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 10117 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 10118 %} 10119 ins_pipe(pipe_class_default); 10120 %} 10121 10122 // Double to Long conversion, NaN is mapped to 0. 10123 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ 10124 match(Set dst (ConvD2L src)); 10125 ins_cost(DEFAULT_COST); 10126 10127 expand %{ 10128 regD tmpD; 10129 stackSlotL tmpS; 10130 flagsReg crx; 10131 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10132 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). 10133 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 10134 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10135 %} 10136 %} 10137 10138 // Convert to Float 10139 10140 // Placed here as needed in expand. 10141 instruct convL2DRaw_regD(regD dst, regD src) %{ 10142 // no match-rule, false predicate 10143 effect(DEF dst, USE src); 10144 predicate(false); 10145 10146 format %{ "FCFID $dst, $src \t// convL2D" %} 10147 size(4); 10148 ins_encode %{ 10149 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10150 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); 10151 %} 10152 ins_pipe(pipe_class_default); 10153 %} 10154 10155 // Placed here as needed in expand. 10156 instruct convD2F_reg(regF dst, regD src) %{ 10157 match(Set dst (ConvD2F src)); 10158 format %{ "FRSP $dst, $src \t// convD2F" %} 10159 size(4); 10160 ins_encode %{ 10161 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); 10162 __ frsp($dst$$FloatRegister, $src$$FloatRegister); 10163 %} 10164 ins_pipe(pipe_class_default); 10165 %} 10166 10167 // Integer to Float conversion. 10168 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ 10169 match(Set dst (ConvI2F src)); 10170 predicate(!VM_Version::has_fcfids()); 10171 ins_cost(DEFAULT_COST); 10172 10173 expand %{ 10174 iRegLdst tmpL; 10175 stackSlotL tmpS; 10176 regD tmpD; 10177 regD tmpD2; 10178 convI2L_reg(tmpL, src); // Sign-extension int to long. 10179 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10180 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10181 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. 10182 convD2F_reg(dst, tmpD2); // Convert double to float. 10183 %} 10184 %} 10185 10186 instruct convL2FRaw_regF(regF dst, regD src) %{ 10187 // no match-rule, false predicate 10188 effect(DEF dst, USE src); 10189 predicate(false); 10190 10191 format %{ "FCFIDS $dst, $src \t// convL2F" %} 10192 size(4); 10193 ins_encode %{ 10194 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10195 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); 10196 %} 10197 ins_pipe(pipe_class_default); 10198 %} 10199 10200 // Integer to Float conversion. Special version for Power7. 10201 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ 10202 match(Set dst (ConvI2F src)); 10203 predicate(VM_Version::has_fcfids()); 10204 ins_cost(DEFAULT_COST); 10205 10206 expand %{ 10207 iRegLdst tmpL; 10208 stackSlotL tmpS; 10209 regD tmpD; 10210 convI2L_reg(tmpL, src); // Sign-extension int to long. 10211 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10212 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10213 convL2FRaw_regF(dst, tmpD); // Convert to float. 10214 %} 10215 %} 10216 10217 // L2F to avoid runtime call. 10218 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ 10219 match(Set dst (ConvL2F src)); 10220 predicate(VM_Version::has_fcfids()); 10221 ins_cost(DEFAULT_COST); 10222 10223 expand %{ 10224 stackSlotL tmpS; 10225 regD tmpD; 10226 regL_to_stkL(tmpS, src); // Store long to stack. 10227 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10228 convL2FRaw_regF(dst, tmpD); // Convert to float. 10229 %} 10230 %} 10231 10232 // Moved up as used in expand. 10233 //instruct convD2F_reg(regF dst, regD src) %{%} 10234 10235 // Convert to Double 10236 10237 // Integer to Double conversion. 10238 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ 10239 match(Set dst (ConvI2D src)); 10240 ins_cost(DEFAULT_COST); 10241 10242 expand %{ 10243 iRegLdst tmpL; 10244 stackSlotL tmpS; 10245 regD tmpD; 10246 convI2L_reg(tmpL, src); // Sign-extension int to long. 10247 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10248 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10249 convL2DRaw_regD(dst, tmpD); // Convert to double. 10250 %} 10251 %} 10252 10253 // Long to Double conversion 10254 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ 10255 match(Set dst (ConvL2D src)); 10256 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10257 10258 expand %{ 10259 regD tmpD; 10260 moveL2D_stack_reg(tmpD, src); 10261 convL2DRaw_regD(dst, tmpD); 10262 %} 10263 %} 10264 10265 instruct convF2D_reg(regD dst, regF src) %{ 10266 match(Set dst (ConvF2D src)); 10267 format %{ "FMR $dst, $src \t// float->double" %} 10268 // variable size, 0 or 4 10269 ins_encode %{ 10270 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 10271 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); 10272 %} 10273 ins_pipe(pipe_class_default); 10274 %} 10275 10276 //----------Control Flow Instructions------------------------------------------ 10277 // Compare Instructions 10278 10279 // Compare Integers 10280 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10281 match(Set crx (CmpI src1 src2)); 10282 size(4); 10283 format %{ "CMPW $crx, $src1, $src2" %} 10284 ins_encode %{ 10285 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10286 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10287 %} 10288 ins_pipe(pipe_class_compare); 10289 %} 10290 10291 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ 10292 match(Set crx (CmpI src1 src2)); 10293 format %{ "CMPWI $crx, $src1, $src2" %} 10294 size(4); 10295 ins_encode %{ 10296 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10297 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10298 %} 10299 ins_pipe(pipe_class_compare); 10300 %} 10301 10302 // (src1 & src2) == 0? 10303 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ 10304 match(Set cr0 (CmpI (AndI src1 src2) zero)); 10305 // r0 is killed 10306 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} 10307 size(4); 10308 ins_encode %{ 10309 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10310 // FIXME: avoid andi_ ? 10311 __ andi_(R0, $src1$$Register, $src2$$constant); 10312 %} 10313 ins_pipe(pipe_class_compare); 10314 %} 10315 10316 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ 10317 match(Set crx (CmpL src1 src2)); 10318 format %{ "CMPD $crx, $src1, $src2" %} 10319 size(4); 10320 ins_encode %{ 10321 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10322 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); 10323 %} 10324 ins_pipe(pipe_class_compare); 10325 %} 10326 10327 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ 10328 match(Set crx (CmpL src1 src2)); 10329 format %{ "CMPDI $crx, $src1, $src2" %} 10330 size(4); 10331 ins_encode %{ 10332 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10333 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10334 %} 10335 ins_pipe(pipe_class_compare); 10336 %} 10337 10338 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ 10339 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10340 // r0 is killed 10341 format %{ "AND R0, $src1, $src2 \t// BTST long" %} 10342 size(4); 10343 ins_encode %{ 10344 // TODO: PPC port $archOpcode(ppc64Opcode_and_); 10345 __ and_(R0, $src1$$Register, $src2$$Register); 10346 %} 10347 ins_pipe(pipe_class_compare); 10348 %} 10349 10350 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ 10351 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10352 // r0 is killed 10353 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} 10354 size(4); 10355 ins_encode %{ 10356 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10357 // FIXME: avoid andi_ ? 10358 __ andi_(R0, $src1$$Register, $src2$$constant); 10359 %} 10360 ins_pipe(pipe_class_compare); 10361 %} 10362 10363 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{ 10364 // no match-rule, false predicate 10365 effect(DEF dst, USE crx); 10366 predicate(false); 10367 10368 ins_variable_size_depending_on_alignment(true); 10369 10370 format %{ "cmovI $crx, $dst, -1, 0, +1" %} 10371 // Worst case is branch + move + branch + move + stop, no stop without scheduler. 10372 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); 10373 ins_encode %{ 10374 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 10375 Label done; 10376 // li(Rdst, 0); // equal -> 0 10377 __ beq($crx$$CondRegister, done); 10378 __ li($dst$$Register, 1); // greater -> +1 10379 __ bgt($crx$$CondRegister, done); 10380 __ li($dst$$Register, -1); // unordered or less -> -1 10381 // TODO: PPC port__ endgroup_if_needed(_size == 20); 10382 __ bind(done); 10383 %} 10384 ins_pipe(pipe_class_compare); 10385 %} 10386 10387 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{ 10388 // no match-rule, false predicate 10389 effect(DEF dst, USE crx); 10390 predicate(false); 10391 10392 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} 10393 postalloc_expand %{ 10394 // 10395 // replaces 10396 // 10397 // region crx 10398 // \ | 10399 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 10400 // 10401 // with 10402 // 10403 // region 10404 // \ 10405 // dst=loadConI16(0) 10406 // | 10407 // ^ region crx 10408 // | \ | 10409 // dst=cmovI_conIvalueMinus1_conIvalue1 10410 // 10411 10412 // Create new nodes. 10413 MachNode *m1 = new loadConI16Node(); 10414 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node(); 10415 10416 // inputs for new nodes 10417 m1->add_req(n_region); 10418 m2->add_req(n_region, n_crx); 10419 m2->add_prec(m1); 10420 10421 // operands for new nodes 10422 m1->_opnds[0] = op_dst; 10423 m1->_opnds[1] = new immI16Oper(0); 10424 m2->_opnds[0] = op_dst; 10425 m2->_opnds[1] = op_crx; 10426 10427 // registers for new nodes 10428 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10429 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10430 10431 // Insert new nodes. 10432 nodes->push(m1); 10433 nodes->push(m2); 10434 %} 10435 %} 10436 10437 // Manifest a CmpL3 result in an integer register. Very painful. 10438 // This is the test to avoid. 10439 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) 10440 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 10441 match(Set dst (CmpL3 src1 src2)); 10442 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10443 10444 expand %{ 10445 flagsReg tmp1; 10446 cmpL_reg_reg(tmp1, src1, src2); 10447 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10448 %} 10449 %} 10450 10451 // Implicit range checks. 10452 // A range check in the ideal world has one of the following shapes: 10453 // - (If le (CmpU length index)), (IfTrue throw exception) 10454 // - (If lt (CmpU index length)), (IfFalse throw exception) 10455 // 10456 // Match range check 'If le (CmpU length index)'. 10457 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ 10458 match(If cmp (CmpU src_length index)); 10459 effect(USE labl); 10460 predicate(TrapBasedRangeChecks && 10461 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 10462 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && 10463 (Matcher::branches_to_uncommon_trap(_leaf))); 10464 10465 ins_is_TrapBasedCheckNode(true); 10466 10467 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} 10468 size(4); 10469 ins_encode %{ 10470 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10471 if ($cmp$$cmpcode == 0x1 /* less_equal */) { 10472 __ trap_range_check_le($src_length$$Register, $index$$constant); 10473 } else { 10474 // Both successors are uncommon traps, probability is 0. 10475 // Node got flipped during fixup flow. 10476 assert($cmp$$cmpcode == 0x9, "must be greater"); 10477 __ trap_range_check_g($src_length$$Register, $index$$constant); 10478 } 10479 %} 10480 ins_pipe(pipe_class_trap); 10481 %} 10482 10483 // Match range check 'If lt (CmpU index length)'. 10484 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ 10485 match(If cmp (CmpU src_index src_length)); 10486 effect(USE labl); 10487 predicate(TrapBasedRangeChecks && 10488 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10489 _leaf->as_If()->_prob >= PROB_ALWAYS && 10490 (Matcher::branches_to_uncommon_trap(_leaf))); 10491 10492 ins_is_TrapBasedCheckNode(true); 10493 10494 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} 10495 size(4); 10496 ins_encode %{ 10497 // TODO: PPC port $archOpcode(ppc64Opcode_tw); 10498 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10499 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); 10500 } else { 10501 // Both successors are uncommon traps, probability is 0. 10502 // Node got flipped during fixup flow. 10503 assert($cmp$$cmpcode == 0x8, "must be less"); 10504 __ trap_range_check_l($src_index$$Register, $src_length$$Register); 10505 } 10506 %} 10507 ins_pipe(pipe_class_trap); 10508 %} 10509 10510 // Match range check 'If lt (CmpU index length)'. 10511 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ 10512 match(If cmp (CmpU src_index length)); 10513 effect(USE labl); 10514 predicate(TrapBasedRangeChecks && 10515 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10516 _leaf->as_If()->_prob >= PROB_ALWAYS && 10517 (Matcher::branches_to_uncommon_trap(_leaf))); 10518 10519 ins_is_TrapBasedCheckNode(true); 10520 10521 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} 10522 size(4); 10523 ins_encode %{ 10524 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10525 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10526 __ trap_range_check_ge($src_index$$Register, $length$$constant); 10527 } else { 10528 // Both successors are uncommon traps, probability is 0. 10529 // Node got flipped during fixup flow. 10530 assert($cmp$$cmpcode == 0x8, "must be less"); 10531 __ trap_range_check_l($src_index$$Register, $length$$constant); 10532 } 10533 %} 10534 ins_pipe(pipe_class_trap); 10535 %} 10536 10537 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10538 match(Set crx (CmpU src1 src2)); 10539 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} 10540 size(4); 10541 ins_encode %{ 10542 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10543 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10544 %} 10545 ins_pipe(pipe_class_compare); 10546 %} 10547 10548 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ 10549 match(Set crx (CmpU src1 src2)); 10550 size(4); 10551 format %{ "CMPLWI $crx, $src1, $src2" %} 10552 ins_encode %{ 10553 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10554 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10555 %} 10556 ins_pipe(pipe_class_compare); 10557 %} 10558 10559 // Implicit zero checks (more implicit null checks). 10560 // No constant pool entries required. 10561 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ 10562 match(If cmp (CmpN value zero)); 10563 effect(USE labl); 10564 predicate(TrapBasedNullChecks && 10565 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10566 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10567 Matcher::branches_to_uncommon_trap(_leaf)); 10568 ins_cost(1); 10569 10570 ins_is_TrapBasedCheckNode(true); 10571 10572 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} 10573 size(4); 10574 ins_encode %{ 10575 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10576 if ($cmp$$cmpcode == 0xA) { 10577 __ trap_null_check($value$$Register); 10578 } else { 10579 // Both successors are uncommon traps, probability is 0. 10580 // Node got flipped during fixup flow. 10581 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10582 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10583 } 10584 %} 10585 ins_pipe(pipe_class_trap); 10586 %} 10587 10588 // Compare narrow oops. 10589 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ 10590 match(Set crx (CmpN src1 src2)); 10591 10592 size(4); 10593 ins_cost(2); 10594 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} 10595 ins_encode %{ 10596 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10597 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10598 %} 10599 ins_pipe(pipe_class_compare); 10600 %} 10601 10602 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ 10603 match(Set crx (CmpN src1 src2)); 10604 // Make this more expensive than zeroCheckN_iReg_imm0. 10605 ins_cost(2); 10606 10607 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} 10608 size(4); 10609 ins_encode %{ 10610 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10611 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10612 %} 10613 ins_pipe(pipe_class_compare); 10614 %} 10615 10616 // Implicit zero checks (more implicit null checks). 10617 // No constant pool entries required. 10618 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ 10619 match(If cmp (CmpP value zero)); 10620 effect(USE labl); 10621 predicate(TrapBasedNullChecks && 10622 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10623 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10624 Matcher::branches_to_uncommon_trap(_leaf)); 10625 ins_cost(1); // Should not be cheaper than zeroCheckN. 10626 10627 ins_is_TrapBasedCheckNode(true); 10628 10629 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} 10630 size(4); 10631 ins_encode %{ 10632 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10633 if ($cmp$$cmpcode == 0xA) { 10634 __ trap_null_check($value$$Register); 10635 } else { 10636 // Both successors are uncommon traps, probability is 0. 10637 // Node got flipped during fixup flow. 10638 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10639 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10640 } 10641 %} 10642 ins_pipe(pipe_class_trap); 10643 %} 10644 10645 // Compare Pointers 10646 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ 10647 match(Set crx (CmpP src1 src2)); 10648 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} 10649 size(4); 10650 ins_encode %{ 10651 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10652 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); 10653 %} 10654 ins_pipe(pipe_class_compare); 10655 %} 10656 10657 // Used in postalloc expand. 10658 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ 10659 // This match rule prevents reordering of node before a safepoint. 10660 // This only makes sense if this instructions is used exclusively 10661 // for the expansion of EncodeP! 10662 match(Set crx (CmpP src1 src2)); 10663 predicate(false); 10664 10665 format %{ "CMPDI $crx, $src1, $src2" %} 10666 size(4); 10667 ins_encode %{ 10668 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10669 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10670 %} 10671 ins_pipe(pipe_class_compare); 10672 %} 10673 10674 //----------Float Compares---------------------------------------------------- 10675 10676 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ 10677 // no match-rule, false predicate 10678 effect(DEF crx, USE src1, USE src2); 10679 predicate(false); 10680 10681 format %{ "cmpFUrd $crx, $src1, $src2" %} 10682 size(4); 10683 ins_encode %{ 10684 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10685 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10686 %} 10687 ins_pipe(pipe_class_default); 10688 %} 10689 10690 instruct cmov_bns_less(flagsReg crx) %{ 10691 // no match-rule, false predicate 10692 effect(DEF crx); 10693 predicate(false); 10694 10695 ins_variable_size_depending_on_alignment(true); 10696 10697 format %{ "cmov $crx" %} 10698 // Worst case is branch + move + stop, no stop without scheduler. 10699 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); 10700 ins_encode %{ 10701 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); 10702 Label done; 10703 __ bns($crx$$CondRegister, done); // not unordered -> keep crx 10704 __ li(R0, 0); 10705 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' 10706 // TODO PPC port __ endgroup_if_needed(_size == 16); 10707 __ bind(done); 10708 %} 10709 ins_pipe(pipe_class_default); 10710 %} 10711 10712 // Compare floating, generate condition code. 10713 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ 10714 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? 10715 // 10716 // The following code sequence occurs a lot in mpegaudio: 10717 // 10718 // block BXX: 10719 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): 10720 // cmpFUrd CCR6, F11, F9 10721 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): 10722 // cmov CCR6 10723 // 8: instruct branchConSched: 10724 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 10725 match(Set crx (CmpF src1 src2)); 10726 ins_cost(DEFAULT_COST+BRANCH_COST); 10727 10728 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} 10729 postalloc_expand %{ 10730 // 10731 // replaces 10732 // 10733 // region src1 src2 10734 // \ | | 10735 // crx=cmpF_reg_reg 10736 // 10737 // with 10738 // 10739 // region src1 src2 10740 // \ | | 10741 // crx=cmpFUnordered_reg_reg 10742 // | 10743 // ^ region 10744 // | \ 10745 // crx=cmov_bns_less 10746 // 10747 10748 // Create new nodes. 10749 MachNode *m1 = new cmpFUnordered_reg_regNode(); 10750 MachNode *m2 = new cmov_bns_lessNode(); 10751 10752 // inputs for new nodes 10753 m1->add_req(n_region, n_src1, n_src2); 10754 m2->add_req(n_region); 10755 m2->add_prec(m1); 10756 10757 // operands for new nodes 10758 m1->_opnds[0] = op_crx; 10759 m1->_opnds[1] = op_src1; 10760 m1->_opnds[2] = op_src2; 10761 m2->_opnds[0] = op_crx; 10762 10763 // registers for new nodes 10764 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10765 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10766 10767 // Insert new nodes. 10768 nodes->push(m1); 10769 nodes->push(m2); 10770 %} 10771 %} 10772 10773 // Compare float, generate -1,0,1 10774 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ 10775 match(Set dst (CmpF3 src1 src2)); 10776 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10777 10778 expand %{ 10779 flagsReg tmp1; 10780 cmpFUnordered_reg_reg(tmp1, src1, src2); 10781 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10782 %} 10783 %} 10784 10785 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ 10786 // no match-rule, false predicate 10787 effect(DEF crx, USE src1, USE src2); 10788 predicate(false); 10789 10790 format %{ "cmpFUrd $crx, $src1, $src2" %} 10791 size(4); 10792 ins_encode %{ 10793 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10794 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10795 %} 10796 ins_pipe(pipe_class_default); 10797 %} 10798 10799 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ 10800 match(Set crx (CmpD src1 src2)); 10801 ins_cost(DEFAULT_COST+BRANCH_COST); 10802 10803 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} 10804 postalloc_expand %{ 10805 // 10806 // replaces 10807 // 10808 // region src1 src2 10809 // \ | | 10810 // crx=cmpD_reg_reg 10811 // 10812 // with 10813 // 10814 // region src1 src2 10815 // \ | | 10816 // crx=cmpDUnordered_reg_reg 10817 // | 10818 // ^ region 10819 // | \ 10820 // crx=cmov_bns_less 10821 // 10822 10823 // create new nodes 10824 MachNode *m1 = new cmpDUnordered_reg_regNode(); 10825 MachNode *m2 = new cmov_bns_lessNode(); 10826 10827 // inputs for new nodes 10828 m1->add_req(n_region, n_src1, n_src2); 10829 m2->add_req(n_region); 10830 m2->add_prec(m1); 10831 10832 // operands for new nodes 10833 m1->_opnds[0] = op_crx; 10834 m1->_opnds[1] = op_src1; 10835 m1->_opnds[2] = op_src2; 10836 m2->_opnds[0] = op_crx; 10837 10838 // registers for new nodes 10839 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10840 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10841 10842 // Insert new nodes. 10843 nodes->push(m1); 10844 nodes->push(m2); 10845 %} 10846 %} 10847 10848 // Compare double, generate -1,0,1 10849 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ 10850 match(Set dst (CmpD3 src1 src2)); 10851 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10852 10853 expand %{ 10854 flagsReg tmp1; 10855 cmpDUnordered_reg_reg(tmp1, src1, src2); 10856 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10857 %} 10858 %} 10859 10860 //----------Branches--------------------------------------------------------- 10861 // Jump 10862 10863 // Direct Branch. 10864 instruct branch(label labl) %{ 10865 match(Goto); 10866 effect(USE labl); 10867 ins_cost(BRANCH_COST); 10868 10869 format %{ "B $labl" %} 10870 size(4); 10871 ins_encode %{ 10872 // TODO: PPC port $archOpcode(ppc64Opcode_b); 10873 Label d; // dummy 10874 __ bind(d); 10875 Label* p = $labl$$label; 10876 // `p' is `NULL' when this encoding class is used only to 10877 // determine the size of the encoded instruction. 10878 Label& l = (NULL == p)? d : *(p); 10879 __ b(l); 10880 %} 10881 ins_pipe(pipe_class_default); 10882 %} 10883 10884 // Conditional Near Branch 10885 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{ 10886 // Same match rule as `branchConFar'. 10887 match(If cmp crx); 10888 effect(USE lbl); 10889 ins_cost(BRANCH_COST); 10890 10891 // If set to 1 this indicates that the current instruction is a 10892 // short variant of a long branch. This avoids using this 10893 // instruction in first-pass matching. It will then only be used in 10894 // the `Shorten_branches' pass. 10895 ins_short_branch(1); 10896 10897 format %{ "B$cmp $crx, $lbl" %} 10898 size(4); 10899 ins_encode( enc_bc(crx, cmp, lbl) ); 10900 ins_pipe(pipe_class_default); 10901 %} 10902 10903 // This is for cases when the ppc64 `bc' instruction does not 10904 // reach far enough. So we emit a far branch here, which is more 10905 // expensive. 10906 // 10907 // Conditional Far Branch 10908 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{ 10909 // Same match rule as `branchCon'. 10910 match(If cmp crx); 10911 effect(USE crx, USE lbl); 10912 predicate(!false /* TODO: PPC port HB_Schedule*/); 10913 // Higher cost than `branchCon'. 10914 ins_cost(5*BRANCH_COST); 10915 10916 // This is not a short variant of a branch, but the long variant. 10917 ins_short_branch(0); 10918 10919 format %{ "B_FAR$cmp $crx, $lbl" %} 10920 size(8); 10921 ins_encode( enc_bc_far(crx, cmp, lbl) ); 10922 ins_pipe(pipe_class_default); 10923 %} 10924 10925 // Conditional Branch used with Power6 scheduler (can be far or short). 10926 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{ 10927 // Same match rule as `branchCon'. 10928 match(If cmp crx); 10929 effect(USE crx, USE lbl); 10930 predicate(false /* TODO: PPC port HB_Schedule*/); 10931 // Higher cost than `branchCon'. 10932 ins_cost(5*BRANCH_COST); 10933 10934 // Actually size doesn't depend on alignment but on shortening. 10935 ins_variable_size_depending_on_alignment(true); 10936 // long variant. 10937 ins_short_branch(0); 10938 10939 format %{ "B_FAR$cmp $crx, $lbl" %} 10940 size(8); // worst case 10941 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); 10942 ins_pipe(pipe_class_default); 10943 %} 10944 10945 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{ 10946 match(CountedLoopEnd cmp crx); 10947 effect(USE labl); 10948 ins_cost(BRANCH_COST); 10949 10950 // short variant. 10951 ins_short_branch(1); 10952 10953 format %{ "B$cmp $crx, $labl \t// counted loop end" %} 10954 size(4); 10955 ins_encode( enc_bc(crx, cmp, labl) ); 10956 ins_pipe(pipe_class_default); 10957 %} 10958 10959 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{ 10960 match(CountedLoopEnd cmp crx); 10961 effect(USE labl); 10962 predicate(!false /* TODO: PPC port HB_Schedule */); 10963 ins_cost(BRANCH_COST); 10964 10965 // Long variant. 10966 ins_short_branch(0); 10967 10968 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10969 size(8); 10970 ins_encode( enc_bc_far(crx, cmp, labl) ); 10971 ins_pipe(pipe_class_default); 10972 %} 10973 10974 // Conditional Branch used with Power6 scheduler (can be far or short). 10975 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{ 10976 match(CountedLoopEnd cmp crx); 10977 effect(USE labl); 10978 predicate(false /* TODO: PPC port HB_Schedule */); 10979 // Higher cost than `branchCon'. 10980 ins_cost(5*BRANCH_COST); 10981 10982 // Actually size doesn't depend on alignment but on shortening. 10983 ins_variable_size_depending_on_alignment(true); 10984 // Long variant. 10985 ins_short_branch(0); 10986 10987 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10988 size(8); // worst case 10989 ins_encode( enc_bc_short_far(crx, cmp, labl) ); 10990 ins_pipe(pipe_class_default); 10991 %} 10992 10993 // ============================================================================ 10994 // Java runtime operations, intrinsics and other complex operations. 10995 10996 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10997 // array for an instance of the superklass. Set a hidden internal cache on a 10998 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10999 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 11000 // 11001 // GL TODO: Improve this. 11002 // - result should not be a TEMP 11003 // - Add match rule as on sparc avoiding additional Cmp. 11004 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, 11005 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ 11006 match(Set result (PartialSubtypeCheck subklass superklass)); 11007 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr); 11008 ins_cost(DEFAULT_COST*10); 11009 11010 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 11011 ins_encode %{ 11012 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11013 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 11014 $tmp_klass$$Register, NULL, $result$$Register); 11015 %} 11016 ins_pipe(pipe_class_default); 11017 %} 11018 11019 // inlined locking and unlocking 11020 11021 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 11022 match(Set crx (FastLock oop box)); 11023 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 11024 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking); 11025 11026 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %} 11027 ins_encode %{ 11028 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11029 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 11030 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); 11031 // If locking was successfull, crx should indicate 'EQ'. 11032 // The compiler generates a branch to the runtime call to 11033 // _complete_monitor_locking_Java for the case where crx is 'NE'. 11034 %} 11035 ins_pipe(pipe_class_compare); 11036 %} 11037 11038 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 11039 match(Set crx (FastUnlock oop box)); 11040 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 11041 11042 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} 11043 ins_encode %{ 11044 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11045 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 11046 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); 11047 // If unlocking was successfull, crx should indicate 'EQ'. 11048 // The compiler generates a branch to the runtime call to 11049 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 11050 %} 11051 ins_pipe(pipe_class_compare); 11052 %} 11053 11054 // Align address. 11055 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ 11056 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 11057 11058 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} 11059 size(4); 11060 ins_encode %{ 11061 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 11062 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); 11063 %} 11064 ins_pipe(pipe_class_default); 11065 %} 11066 11067 // Array size computation. 11068 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ 11069 match(Set dst (SubL (CastP2X end) (CastP2X start))); 11070 11071 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} 11072 size(4); 11073 ins_encode %{ 11074 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 11075 __ subf($dst$$Register, $start$$Register, $end$$Register); 11076 %} 11077 ins_pipe(pipe_class_default); 11078 %} 11079 11080 // Clear-array with dynamic array-size. 11081 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ 11082 match(Set dummy (ClearArray cnt base)); 11083 effect(USE_KILL cnt, USE_KILL base, KILL ctr); 11084 ins_cost(MEMORY_REF_COST); 11085 11086 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11087 11088 format %{ "ClearArray $cnt, $base" %} 11089 ins_encode %{ 11090 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11091 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 11092 %} 11093 ins_pipe(pipe_class_default); 11094 %} 11095 11096 // String_IndexOf for needle of length 1. 11097 // 11098 // Match needle into immediate operands: no loadConP node needed. Saves one 11099 // register and two instructions over string_indexOf_imm1Node. 11100 // 11101 // Assumes register result differs from all input registers. 11102 // 11103 // Preserves registers haystack, haycnt 11104 // Kills registers tmp1, tmp2 11105 // Defines registers result 11106 // 11107 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11108 // 11109 // Unfortunately this does not match too often. In many situations the AddP is used 11110 // by several nodes, even several StrIndexOf nodes, breaking the match tree. 11111 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11112 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11113 iRegIdst tmp1, iRegIdst tmp2, 11114 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11115 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported 11116 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11117 11118 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); 11119 11120 ins_cost(150); 11121 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11122 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11123 11124 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted 11125 ins_encode %{ 11126 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11127 immPOper *needleOper = (immPOper *)$needleImm; 11128 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11129 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11130 11131 __ string_indexof_1($result$$Register, 11132 $haystack$$Register, $haycnt$$Register, 11133 R0, needle_values->char_at(0), 11134 $tmp1$$Register, $tmp2$$Register); 11135 %} 11136 ins_pipe(pipe_class_compare); 11137 %} 11138 11139 // String_IndexOf for needle of length 1. 11140 // 11141 // Special case requires less registers and emits less instructions. 11142 // 11143 // Assumes register result differs from all input registers. 11144 // 11145 // Preserves registers haystack, haycnt 11146 // Kills registers tmp1, tmp2, needle 11147 // Defines registers result 11148 // 11149 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11150 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11151 rscratch2RegP needle, immI_1 needlecntImm, 11152 iRegIdst tmp1, iRegIdst tmp2, 11153 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11154 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11155 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result, 11156 TEMP tmp1, TEMP tmp2); 11157 // Required for EA: check if it is still a type_array. 11158 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11159 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11160 ins_cost(180); 11161 11162 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11163 11164 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11165 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11166 ins_encode %{ 11167 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11168 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11169 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11170 guarantee(needle_values, "sanity"); 11171 if (needle_values != NULL) { 11172 __ string_indexof_1($result$$Register, 11173 $haystack$$Register, $haycnt$$Register, 11174 R0, needle_values->char_at(0), 11175 $tmp1$$Register, $tmp2$$Register); 11176 } else { 11177 __ string_indexof_1($result$$Register, 11178 $haystack$$Register, $haycnt$$Register, 11179 $needle$$Register, 0, 11180 $tmp1$$Register, $tmp2$$Register); 11181 } 11182 %} 11183 ins_pipe(pipe_class_compare); 11184 %} 11185 11186 // String_IndexOf. 11187 // 11188 // Length of needle as immediate. This saves instruction loading constant needle 11189 // length. 11190 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle 11191 // completely or do it in vector instruction. This should save registers for 11192 // needlecnt and needle. 11193 // 11194 // Assumes register result differs from all input registers. 11195 // Overwrites haycnt, needlecnt. 11196 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11197 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11198 iRegPsrc needle, uimmI15 needlecntImm, 11199 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11200 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11201 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11202 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11203 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); 11204 // Required for EA: check if it is still a type_array. 11205 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11206 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11207 ins_cost(250); 11208 11209 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11210 11211 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11212 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11213 ins_encode %{ 11214 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11215 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11216 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11217 11218 __ string_indexof($result$$Register, 11219 $haystack$$Register, $haycnt$$Register, 11220 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11221 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11222 %} 11223 ins_pipe(pipe_class_compare); 11224 %} 11225 11226 // StrIndexOf node. 11227 // 11228 // Assumes register result differs from all input registers. 11229 // Overwrites haycnt, needlecnt. 11230 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11231 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11232 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11233 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11234 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11235 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11236 TEMP_DEF result, 11237 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); 11238 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported. 11239 ins_cost(300); 11240 11241 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11242 11243 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11244 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11245 ins_encode %{ 11246 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11247 __ string_indexof($result$$Register, 11248 $haystack$$Register, $haycnt$$Register, 11249 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11250 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11251 %} 11252 ins_pipe(pipe_class_compare); 11253 %} 11254 11255 // String equals with immediate. 11256 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, 11257 iRegPdst tmp1, iRegPdst tmp2, 11258 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ 11259 match(Set result (StrEquals (Binary str1 str2) cntImm)); 11260 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, 11261 KILL cr0, KILL cr6, KILL ctr); 11262 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11263 ins_cost(250); 11264 11265 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11266 11267 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" 11268 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} 11269 ins_encode %{ 11270 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11271 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, 11272 $result$$Register, $tmp1$$Register, $tmp2$$Register); 11273 %} 11274 ins_pipe(pipe_class_compare); 11275 %} 11276 11277 // String equals. 11278 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11279 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, 11280 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, 11281 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11282 match(Set result (StrEquals (Binary str1 str2) cnt)); 11283 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11284 KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11285 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11286 ins_cost(300); 11287 11288 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11289 11290 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" 11291 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11292 ins_encode %{ 11293 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11294 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, 11295 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11296 %} 11297 ins_pipe(pipe_class_compare); 11298 %} 11299 11300 // String compare. 11301 // Char[] pointers are passed in. 11302 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11303 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11304 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ 11305 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11306 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr); 11307 ins_cost(300); 11308 11309 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11310 11311 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" 11312 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} 11313 ins_encode %{ 11314 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11315 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, 11316 $result$$Register, $tmp$$Register); 11317 %} 11318 ins_pipe(pipe_class_compare); 11319 %} 11320 11321 //---------- Min/Max Instructions --------------------------------------------- 11322 11323 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11324 match(Set dst (MinI src1 src2)); 11325 ins_cost(DEFAULT_COST*6); 11326 11327 expand %{ 11328 iRegLdst src1s; 11329 iRegLdst src2s; 11330 iRegLdst diff; 11331 iRegLdst sm; 11332 iRegLdst doz; // difference or zero 11333 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11334 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11335 subL_reg_reg(diff, src2s, src1s); 11336 // Need to consider >=33 bit result, therefore we need signmaskL. 11337 signmask64L_regL(sm, diff); 11338 andL_reg_reg(doz, diff, sm); // <=0 11339 addI_regL_regL(dst, doz, src1s); 11340 %} 11341 %} 11342 11343 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11344 match(Set dst (MaxI src1 src2)); 11345 ins_cost(DEFAULT_COST*6); 11346 11347 expand %{ 11348 iRegLdst src1s; 11349 iRegLdst src2s; 11350 iRegLdst diff; 11351 iRegLdst sm; 11352 iRegLdst doz; // difference or zero 11353 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11354 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11355 subL_reg_reg(diff, src2s, src1s); 11356 // Need to consider >=33 bit result, therefore we need signmaskL. 11357 signmask64L_regL(sm, diff); 11358 andcL_reg_reg(doz, diff, sm); // >=0 11359 addI_regL_regL(dst, doz, src1s); 11360 %} 11361 %} 11362 11363 //---------- Population Count Instructions ------------------------------------ 11364 11365 // Popcnt for Power7. 11366 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ 11367 match(Set dst (PopCountI src)); 11368 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11369 ins_cost(DEFAULT_COST); 11370 11371 format %{ "POPCNTW $dst, $src" %} 11372 size(4); 11373 ins_encode %{ 11374 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11375 __ popcntw($dst$$Register, $src$$Register); 11376 %} 11377 ins_pipe(pipe_class_default); 11378 %} 11379 11380 // Popcnt for Power7. 11381 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ 11382 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11383 match(Set dst (PopCountL src)); 11384 ins_cost(DEFAULT_COST); 11385 11386 format %{ "POPCNTD $dst, $src" %} 11387 size(4); 11388 ins_encode %{ 11389 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11390 __ popcntd($dst$$Register, $src$$Register); 11391 %} 11392 ins_pipe(pipe_class_default); 11393 %} 11394 11395 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ 11396 match(Set dst (CountLeadingZerosI src)); 11397 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11398 ins_cost(DEFAULT_COST); 11399 11400 format %{ "CNTLZW $dst, $src" %} 11401 size(4); 11402 ins_encode %{ 11403 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); 11404 __ cntlzw($dst$$Register, $src$$Register); 11405 %} 11406 ins_pipe(pipe_class_default); 11407 %} 11408 11409 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ 11410 match(Set dst (CountLeadingZerosL src)); 11411 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11412 ins_cost(DEFAULT_COST); 11413 11414 format %{ "CNTLZD $dst, $src" %} 11415 size(4); 11416 ins_encode %{ 11417 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11418 __ cntlzd($dst$$Register, $src$$Register); 11419 %} 11420 ins_pipe(pipe_class_default); 11421 %} 11422 11423 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ 11424 // no match-rule, false predicate 11425 effect(DEF dst, USE src); 11426 predicate(false); 11427 11428 format %{ "CNTLZD $dst, $src" %} 11429 size(4); 11430 ins_encode %{ 11431 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11432 __ cntlzd($dst$$Register, $src$$Register); 11433 %} 11434 ins_pipe(pipe_class_default); 11435 %} 11436 11437 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ 11438 match(Set dst (CountTrailingZerosI src)); 11439 predicate(UseCountLeadingZerosInstructionsPPC64); 11440 ins_cost(DEFAULT_COST); 11441 11442 expand %{ 11443 immI16 imm1 %{ (int)-1 %} 11444 immI16 imm2 %{ (int)32 %} 11445 immI_minus1 m1 %{ -1 %} 11446 iRegIdst tmpI1; 11447 iRegIdst tmpI2; 11448 iRegIdst tmpI3; 11449 addI_reg_imm16(tmpI1, src, imm1); 11450 andcI_reg_reg(tmpI2, src, m1, tmpI1); 11451 countLeadingZerosI(tmpI3, tmpI2); 11452 subI_imm16_reg(dst, imm2, tmpI3); 11453 %} 11454 %} 11455 11456 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ 11457 match(Set dst (CountTrailingZerosL src)); 11458 predicate(UseCountLeadingZerosInstructionsPPC64); 11459 ins_cost(DEFAULT_COST); 11460 11461 expand %{ 11462 immL16 imm1 %{ (long)-1 %} 11463 immI16 imm2 %{ (int)64 %} 11464 iRegLdst tmpL1; 11465 iRegLdst tmpL2; 11466 iRegIdst tmpL3; 11467 addL_reg_imm16(tmpL1, src, imm1); 11468 andcL_reg_reg(tmpL2, tmpL1, src); 11469 countLeadingZerosL(tmpL3, tmpL2); 11470 subI_imm16_reg(dst, imm2, tmpL3); 11471 %} 11472 %} 11473 11474 // Expand nodes for byte_reverse_int. 11475 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11476 effect(DEF dst, USE src, USE pos, USE shift); 11477 predicate(false); 11478 11479 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11480 size(4); 11481 ins_encode %{ 11482 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11483 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11484 %} 11485 ins_pipe(pipe_class_default); 11486 %} 11487 11488 // As insrwi_a, but with USE_DEF. 11489 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11490 effect(USE_DEF dst, USE src, USE pos, USE shift); 11491 predicate(false); 11492 11493 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11494 size(4); 11495 ins_encode %{ 11496 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11497 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11498 %} 11499 ins_pipe(pipe_class_default); 11500 %} 11501 11502 // Just slightly faster than java implementation. 11503 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ 11504 match(Set dst (ReverseBytesI src)); 11505 predicate(UseCountLeadingZerosInstructionsPPC64); 11506 ins_cost(DEFAULT_COST); 11507 11508 expand %{ 11509 immI16 imm24 %{ (int) 24 %} 11510 immI16 imm16 %{ (int) 16 %} 11511 immI16 imm8 %{ (int) 8 %} 11512 immI16 imm4 %{ (int) 4 %} 11513 immI16 imm0 %{ (int) 0 %} 11514 iRegLdst tmpI1; 11515 iRegLdst tmpI2; 11516 iRegLdst tmpI3; 11517 11518 urShiftI_reg_imm(tmpI1, src, imm24); 11519 insrwi_a(dst, tmpI1, imm24, imm8); 11520 urShiftI_reg_imm(tmpI2, src, imm16); 11521 insrwi(dst, tmpI2, imm8, imm16); 11522 urShiftI_reg_imm(tmpI3, src, imm8); 11523 insrwi(dst, tmpI3, imm8, imm8); 11524 insrwi(dst, src, imm0, imm8); 11525 %} 11526 %} 11527 11528 //---------- Replicate Vector Instructions ------------------------------------ 11529 11530 // Insrdi does replicate if src == dst. 11531 instruct repl32(iRegLdst dst) %{ 11532 predicate(false); 11533 effect(USE_DEF dst); 11534 11535 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} 11536 size(4); 11537 ins_encode %{ 11538 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11539 __ insrdi($dst$$Register, $dst$$Register, 32, 0); 11540 %} 11541 ins_pipe(pipe_class_default); 11542 %} 11543 11544 // Insrdi does replicate if src == dst. 11545 instruct repl48(iRegLdst dst) %{ 11546 predicate(false); 11547 effect(USE_DEF dst); 11548 11549 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} 11550 size(4); 11551 ins_encode %{ 11552 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11553 __ insrdi($dst$$Register, $dst$$Register, 48, 0); 11554 %} 11555 ins_pipe(pipe_class_default); 11556 %} 11557 11558 // Insrdi does replicate if src == dst. 11559 instruct repl56(iRegLdst dst) %{ 11560 predicate(false); 11561 effect(USE_DEF dst); 11562 11563 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} 11564 size(4); 11565 ins_encode %{ 11566 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11567 __ insrdi($dst$$Register, $dst$$Register, 56, 0); 11568 %} 11569 ins_pipe(pipe_class_default); 11570 %} 11571 11572 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11573 match(Set dst (ReplicateB src)); 11574 predicate(n->as_Vector()->length() == 8); 11575 expand %{ 11576 moveReg(dst, src); 11577 repl56(dst); 11578 repl48(dst); 11579 repl32(dst); 11580 %} 11581 %} 11582 11583 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ 11584 match(Set dst (ReplicateB zero)); 11585 predicate(n->as_Vector()->length() == 8); 11586 format %{ "LI $dst, #0 \t// replicate8B" %} 11587 size(4); 11588 ins_encode %{ 11589 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11590 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11591 %} 11592 ins_pipe(pipe_class_default); 11593 %} 11594 11595 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11596 match(Set dst (ReplicateB src)); 11597 predicate(n->as_Vector()->length() == 8); 11598 format %{ "LI $dst, #-1 \t// replicate8B" %} 11599 size(4); 11600 ins_encode %{ 11601 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11602 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11603 %} 11604 ins_pipe(pipe_class_default); 11605 %} 11606 11607 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11608 match(Set dst (ReplicateS src)); 11609 predicate(n->as_Vector()->length() == 4); 11610 expand %{ 11611 moveReg(dst, src); 11612 repl48(dst); 11613 repl32(dst); 11614 %} 11615 %} 11616 11617 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ 11618 match(Set dst (ReplicateS zero)); 11619 predicate(n->as_Vector()->length() == 4); 11620 format %{ "LI $dst, #0 \t// replicate4C" %} 11621 size(4); 11622 ins_encode %{ 11623 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11624 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11625 %} 11626 ins_pipe(pipe_class_default); 11627 %} 11628 11629 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11630 match(Set dst (ReplicateS src)); 11631 predicate(n->as_Vector()->length() == 4); 11632 format %{ "LI $dst, -1 \t// replicate4C" %} 11633 size(4); 11634 ins_encode %{ 11635 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11636 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11637 %} 11638 ins_pipe(pipe_class_default); 11639 %} 11640 11641 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11642 match(Set dst (ReplicateI src)); 11643 predicate(n->as_Vector()->length() == 2); 11644 ins_cost(2 * DEFAULT_COST); 11645 expand %{ 11646 moveReg(dst, src); 11647 repl32(dst); 11648 %} 11649 %} 11650 11651 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ 11652 match(Set dst (ReplicateI zero)); 11653 predicate(n->as_Vector()->length() == 2); 11654 format %{ "LI $dst, #0 \t// replicate4C" %} 11655 size(4); 11656 ins_encode %{ 11657 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11658 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11659 %} 11660 ins_pipe(pipe_class_default); 11661 %} 11662 11663 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11664 match(Set dst (ReplicateI src)); 11665 predicate(n->as_Vector()->length() == 2); 11666 format %{ "LI $dst, -1 \t// replicate4C" %} 11667 size(4); 11668 ins_encode %{ 11669 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11670 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11671 %} 11672 ins_pipe(pipe_class_default); 11673 %} 11674 11675 // Move float to int register via stack, replicate. 11676 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ 11677 match(Set dst (ReplicateF src)); 11678 predicate(n->as_Vector()->length() == 2); 11679 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); 11680 expand %{ 11681 stackSlotL tmpS; 11682 iRegIdst tmpI; 11683 moveF2I_reg_stack(tmpS, src); // Move float to stack. 11684 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. 11685 moveReg(dst, tmpI); // Move int to long reg. 11686 repl32(dst); // Replicate bitpattern. 11687 %} 11688 %} 11689 11690 // Replicate scalar constant to packed float values in Double register 11691 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ 11692 match(Set dst (ReplicateF src)); 11693 predicate(n->as_Vector()->length() == 2); 11694 ins_cost(5 * DEFAULT_COST); 11695 11696 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} 11697 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); 11698 %} 11699 11700 // Replicate scalar zero constant to packed float values in Double register 11701 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ 11702 match(Set dst (ReplicateF zero)); 11703 predicate(n->as_Vector()->length() == 2); 11704 11705 format %{ "LI $dst, #0 \t// replicate2F" %} 11706 ins_encode %{ 11707 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11708 __ li($dst$$Register, 0x0); 11709 %} 11710 ins_pipe(pipe_class_default); 11711 %} 11712 11713 // ============================================================================ 11714 // Safepoint Instruction 11715 11716 instruct safePoint_poll(iRegPdst poll) %{ 11717 match(SafePoint poll); 11718 predicate(LoadPollAddressFromThread); 11719 11720 // It caused problems to add the effect that r0 is killed, but this 11721 // effect no longer needs to be mentioned, since r0 is not contained 11722 // in a reg_class. 11723 11724 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} 11725 size(4); 11726 ins_encode( enc_poll(0x0, poll) ); 11727 ins_pipe(pipe_class_default); 11728 %} 11729 11730 // Safepoint without per-thread support. Load address of page to poll 11731 // as constant. 11732 // Rscratch2RegP is R12. 11733 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be 11734 // a seperate node so that the oop map is at the right location. 11735 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ 11736 match(SafePoint poll); 11737 predicate(!LoadPollAddressFromThread); 11738 11739 // It caused problems to add the effect that r0 is killed, but this 11740 // effect no longer needs to be mentioned, since r0 is not contained 11741 // in a reg_class. 11742 11743 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %} 11744 ins_encode( enc_poll(0x0, poll) ); 11745 ins_pipe(pipe_class_default); 11746 %} 11747 11748 // ============================================================================ 11749 // Call Instructions 11750 11751 // Call Java Static Instruction 11752 11753 // Schedulable version of call static node. 11754 instruct CallStaticJavaDirect(method meth) %{ 11755 match(CallStaticJava); 11756 effect(USE meth); 11757 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11758 ins_cost(CALL_COST); 11759 11760 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11761 11762 format %{ "CALL,static $meth \t// ==> " %} 11763 size(4); 11764 ins_encode( enc_java_static_call(meth) ); 11765 ins_pipe(pipe_class_call); 11766 %} 11767 11768 // Schedulable version of call static node. 11769 instruct CallStaticJavaDirectHandle(method meth) %{ 11770 match(CallStaticJava); 11771 effect(USE meth); 11772 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11773 ins_cost(CALL_COST); 11774 11775 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11776 11777 format %{ "CALL,static $meth \t// ==> " %} 11778 ins_encode( enc_java_handle_call(meth) ); 11779 ins_pipe(pipe_class_call); 11780 %} 11781 11782 // Call Java Dynamic Instruction 11783 11784 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). 11785 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable 11786 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. 11787 // The call destination must still be placed in the constant pool. 11788 instruct CallDynamicJavaDirectSched(method meth) %{ 11789 match(CallDynamicJava); // To get all the data fields we need ... 11790 effect(USE meth); 11791 predicate(false); // ... but never match. 11792 11793 ins_field_load_ic_hi_node(loadConL_hiNode*); 11794 ins_field_load_ic_node(loadConLNode*); 11795 ins_num_consts(1 /* 1 patchable constant: call destination */); 11796 11797 format %{ "BL \t// dynamic $meth ==> " %} 11798 size(4); 11799 ins_encode( enc_java_dynamic_call_sched(meth) ); 11800 ins_pipe(pipe_class_call); 11801 %} 11802 11803 // Schedulable (i.e. postalloc expanded) version of call dynamic java. 11804 // We use postalloc expanded calls if we use inline caches 11805 // and do not update method data. 11806 // 11807 // This instruction has two constants: inline cache (IC) and call destination. 11808 // Loading the inline cache will be postalloc expanded, thus leaving a call with 11809 // one constant. 11810 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ 11811 match(CallDynamicJava); 11812 effect(USE meth); 11813 predicate(UseInlineCaches); 11814 ins_cost(CALL_COST); 11815 11816 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); 11817 11818 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} 11819 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); 11820 %} 11821 11822 // Compound version of call dynamic java 11823 // We use postalloc expanded calls if we use inline caches 11824 // and do not update method data. 11825 instruct CallDynamicJavaDirect(method meth) %{ 11826 match(CallDynamicJava); 11827 effect(USE meth); 11828 predicate(!UseInlineCaches); 11829 ins_cost(CALL_COST); 11830 11831 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). 11832 ins_num_consts(4); 11833 11834 format %{ "CALL,dynamic $meth \t// ==> " %} 11835 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); 11836 ins_pipe(pipe_class_call); 11837 %} 11838 11839 // Call Runtime Instruction 11840 11841 instruct CallRuntimeDirect(method meth) %{ 11842 match(CallRuntime); 11843 effect(USE meth); 11844 ins_cost(CALL_COST); 11845 11846 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11847 // env for callee, C-toc. 11848 ins_num_consts(3); 11849 11850 format %{ "CALL,runtime" %} 11851 ins_encode( enc_java_to_runtime_call(meth) ); 11852 ins_pipe(pipe_class_call); 11853 %} 11854 11855 // Call Leaf 11856 11857 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). 11858 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ 11859 effect(DEF dst, USE src); 11860 11861 ins_num_consts(1); 11862 11863 format %{ "MTCTR $src" %} 11864 size(4); 11865 ins_encode( enc_leaf_call_mtctr(src) ); 11866 ins_pipe(pipe_class_default); 11867 %} 11868 11869 // Used by postalloc expand of CallLeafDirect_Ex (actual call). 11870 instruct CallLeafDirect(method meth) %{ 11871 match(CallLeaf); // To get the data all the data fields we need ... 11872 effect(USE meth); 11873 predicate(false); // but never match. 11874 11875 format %{ "BCTRL \t// leaf call $meth ==> " %} 11876 size(4); 11877 ins_encode %{ 11878 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); 11879 __ bctrl(); 11880 %} 11881 ins_pipe(pipe_class_call); 11882 %} 11883 11884 // postalloc expand of CallLeafDirect. 11885 // Load adress to call from TOC, then bl to it. 11886 instruct CallLeafDirect_Ex(method meth) %{ 11887 match(CallLeaf); 11888 effect(USE meth); 11889 ins_cost(CALL_COST); 11890 11891 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, 11892 // env for callee, C-toc. 11893 ins_num_consts(3); 11894 11895 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} 11896 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11897 %} 11898 11899 // Call runtime without safepoint - same as CallLeaf. 11900 // postalloc expand of CallLeafNoFPDirect. 11901 // Load adress to call from TOC, then bl to it. 11902 instruct CallLeafNoFPDirect_Ex(method meth) %{ 11903 match(CallLeafNoFP); 11904 effect(USE meth); 11905 ins_cost(CALL_COST); 11906 11907 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11908 // env for callee, C-toc. 11909 ins_num_consts(3); 11910 11911 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} 11912 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11913 %} 11914 11915 // Tail Call; Jump from runtime stub to Java code. 11916 // Also known as an 'interprocedural jump'. 11917 // Target of jump will eventually return to caller. 11918 // TailJump below removes the return address. 11919 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ 11920 match(TailCall jump_target method_oop); 11921 ins_cost(CALL_COST); 11922 11923 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" 11924 "BCTR \t// tail call" %} 11925 size(8); 11926 ins_encode %{ 11927 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11928 __ mtctr($jump_target$$Register); 11929 __ bctr(); 11930 %} 11931 ins_pipe(pipe_class_call); 11932 %} 11933 11934 // Return Instruction 11935 instruct Ret() %{ 11936 match(Return); 11937 format %{ "BLR \t// branch to link register" %} 11938 size(4); 11939 ins_encode %{ 11940 // TODO: PPC port $archOpcode(ppc64Opcode_blr); 11941 // LR is restored in MachEpilogNode. Just do the RET here. 11942 __ blr(); 11943 %} 11944 ins_pipe(pipe_class_default); 11945 %} 11946 11947 // Tail Jump; remove the return address; jump to target. 11948 // TailCall above leaves the return address around. 11949 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 11950 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 11951 // "restore" before this instruction (in Epilogue), we need to materialize it 11952 // in %i0. 11953 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ 11954 match(TailJump jump_target ex_oop); 11955 ins_cost(CALL_COST); 11956 11957 format %{ "LD R4_ARG2 = LR\n\t" 11958 "MTCTR $jump_target\n\t" 11959 "BCTR \t// TailJump, exception oop: $ex_oop" %} 11960 size(12); 11961 ins_encode %{ 11962 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11963 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); 11964 __ mtctr($jump_target$$Register); 11965 __ bctr(); 11966 %} 11967 ins_pipe(pipe_class_call); 11968 %} 11969 11970 // Create exception oop: created by stack-crawling runtime code. 11971 // Created exception is now available to this handler, and is setup 11972 // just prior to jumping to this handler. No code emitted. 11973 instruct CreateException(rarg1RegP ex_oop) %{ 11974 match(Set ex_oop (CreateEx)); 11975 ins_cost(0); 11976 11977 format %{ " -- \t// exception oop; no code emitted" %} 11978 size(0); 11979 ins_encode( /*empty*/ ); 11980 ins_pipe(pipe_class_default); 11981 %} 11982 11983 // Rethrow exception: The exception oop will come in the first 11984 // argument position. Then JUMP (not call) to the rethrow stub code. 11985 instruct RethrowException() %{ 11986 match(Rethrow); 11987 ins_cost(CALL_COST); 11988 11989 format %{ "Jmp rethrow_stub" %} 11990 ins_encode %{ 11991 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11992 cbuf.set_insts_mark(); 11993 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); 11994 %} 11995 ins_pipe(pipe_class_call); 11996 %} 11997 11998 // Die now. 11999 instruct ShouldNotReachHere() %{ 12000 match(Halt); 12001 ins_cost(CALL_COST); 12002 12003 format %{ "ShouldNotReachHere" %} 12004 size(4); 12005 ins_encode %{ 12006 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 12007 __ trap_should_not_reach_here(); 12008 %} 12009 ins_pipe(pipe_class_default); 12010 %} 12011 12012 // This name is KNOWN by the ADLC and cannot be changed. The ADLC 12013 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. 12014 // Get a DEF on threadRegP, no costs, no encoding, use 12015 // 'ins_should_rematerialize(true)' to avoid spilling. 12016 instruct tlsLoadP(threadRegP dst) %{ 12017 match(Set dst (ThreadLocal)); 12018 ins_cost(0); 12019 12020 ins_should_rematerialize(true); 12021 12022 format %{ " -- \t// $dst=Thread::current(), empty" %} 12023 size(0); 12024 ins_encode( /*empty*/ ); 12025 ins_pipe(pipe_class_empty); 12026 %} 12027 12028 //---Some PPC specific nodes--------------------------------------------------- 12029 12030 // Stop a group. 12031 instruct endGroup() %{ 12032 ins_cost(0); 12033 12034 ins_is_nop(true); 12035 12036 format %{ "End Bundle (ori r1, r1, 0)" %} 12037 size(4); 12038 ins_encode %{ 12039 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); 12040 __ endgroup(); 12041 %} 12042 ins_pipe(pipe_class_default); 12043 %} 12044 12045 // Nop instructions 12046 12047 instruct fxNop() %{ 12048 ins_cost(0); 12049 12050 ins_is_nop(true); 12051 12052 format %{ "fxNop" %} 12053 size(4); 12054 ins_encode %{ 12055 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12056 __ nop(); 12057 %} 12058 ins_pipe(pipe_class_default); 12059 %} 12060 12061 instruct fpNop0() %{ 12062 ins_cost(0); 12063 12064 ins_is_nop(true); 12065 12066 format %{ "fpNop0" %} 12067 size(4); 12068 ins_encode %{ 12069 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12070 __ fpnop0(); 12071 %} 12072 ins_pipe(pipe_class_default); 12073 %} 12074 12075 instruct fpNop1() %{ 12076 ins_cost(0); 12077 12078 ins_is_nop(true); 12079 12080 format %{ "fpNop1" %} 12081 size(4); 12082 ins_encode %{ 12083 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12084 __ fpnop1(); 12085 %} 12086 ins_pipe(pipe_class_default); 12087 %} 12088 12089 instruct brNop0() %{ 12090 ins_cost(0); 12091 size(4); 12092 format %{ "brNop0" %} 12093 ins_encode %{ 12094 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12095 __ brnop0(); 12096 %} 12097 ins_is_nop(true); 12098 ins_pipe(pipe_class_default); 12099 %} 12100 12101 instruct brNop1() %{ 12102 ins_cost(0); 12103 12104 ins_is_nop(true); 12105 12106 format %{ "brNop1" %} 12107 size(4); 12108 ins_encode %{ 12109 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12110 __ brnop1(); 12111 %} 12112 ins_pipe(pipe_class_default); 12113 %} 12114 12115 instruct brNop2() %{ 12116 ins_cost(0); 12117 12118 ins_is_nop(true); 12119 12120 format %{ "brNop2" %} 12121 size(4); 12122 ins_encode %{ 12123 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12124 __ brnop2(); 12125 %} 12126 ins_pipe(pipe_class_default); 12127 %} 12128 12129 //----------PEEPHOLE RULES----------------------------------------------------- 12130 // These must follow all instruction definitions as they use the names 12131 // defined in the instructions definitions. 12132 // 12133 // peepmatch ( root_instr_name [preceeding_instruction]* ); 12134 // 12135 // peepconstraint %{ 12136 // (instruction_number.operand_name relational_op instruction_number.operand_name 12137 // [, ...] ); 12138 // // instruction numbers are zero-based using left to right order in peepmatch 12139 // 12140 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12141 // // provide an instruction_number.operand_name for each operand that appears 12142 // // in the replacement instruction's match rule 12143 // 12144 // ---------VM FLAGS--------------------------------------------------------- 12145 // 12146 // All peephole optimizations can be turned off using -XX:-OptoPeephole 12147 // 12148 // Each peephole rule is given an identifying number starting with zero and 12149 // increasing by one in the order seen by the parser. An individual peephole 12150 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12151 // on the command-line. 12152 // 12153 // ---------CURRENT LIMITATIONS---------------------------------------------- 12154 // 12155 // Only match adjacent instructions in same basic block 12156 // Only equality constraints 12157 // Only constraints between operands, not (0.dest_reg == EAX_enc) 12158 // Only one replacement instruction 12159 // 12160 // ---------EXAMPLE---------------------------------------------------------- 12161 // 12162 // // pertinent parts of existing instructions in architecture description 12163 // instruct movI(eRegI dst, eRegI src) %{ 12164 // match(Set dst (CopyI src)); 12165 // %} 12166 // 12167 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12168 // match(Set dst (AddI dst src)); 12169 // effect(KILL cr); 12170 // %} 12171 // 12172 // // Change (inc mov) to lea 12173 // peephole %{ 12174 // // increment preceeded by register-register move 12175 // peepmatch ( incI_eReg movI ); 12176 // // require that the destination register of the increment 12177 // // match the destination register of the move 12178 // peepconstraint ( 0.dst == 1.dst ); 12179 // // construct a replacement instruction that sets 12180 // // the destination to ( move's source register + one ) 12181 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12182 // %} 12183 // 12184 // Implementation no longer uses movX instructions since 12185 // machine-independent system no longer uses CopyX nodes. 12186 // 12187 // peephole %{ 12188 // peepmatch ( incI_eReg movI ); 12189 // peepconstraint ( 0.dst == 1.dst ); 12190 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12191 // %} 12192 // 12193 // peephole %{ 12194 // peepmatch ( decI_eReg movI ); 12195 // peepconstraint ( 0.dst == 1.dst ); 12196 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12197 // %} 12198 // 12199 // peephole %{ 12200 // peepmatch ( addI_eReg_imm movI ); 12201 // peepconstraint ( 0.dst == 1.dst ); 12202 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12203 // %} 12204 // 12205 // peephole %{ 12206 // peepmatch ( addP_eReg_imm movP ); 12207 // peepconstraint ( 0.dst == 1.dst ); 12208 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12209 // %} 12210 12211 // // Change load of spilled value to only a spill 12212 // instruct storeI(memory mem, eRegI src) %{ 12213 // match(Set mem (StoreI mem src)); 12214 // %} 12215 // 12216 // instruct loadI(eRegI dst, memory mem) %{ 12217 // match(Set dst (LoadI mem)); 12218 // %} 12219 // 12220 peephole %{ 12221 peepmatch ( loadI storeI ); 12222 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12223 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12224 %} 12225 12226 peephole %{ 12227 peepmatch ( loadL storeL ); 12228 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12229 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); 12230 %} 12231 12232 peephole %{ 12233 peepmatch ( loadP storeP ); 12234 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); 12235 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); 12236 %} 12237 12238 //----------SMARTSPILL RULES--------------------------------------------------- 12239 // These must follow all instruction definitions as they use the names 12240 // defined in the instructions definitions.