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src/cpu/ppc/vm/assembler_ppc.hpp
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rev 8107 : 8077838: Recent developments for ppc.
*** 222,235 ****
--- 222,238 ----
ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1),
ADDI_OPCODE = (14u << OPCODE_SHIFT),
ADDIS_OPCODE = (15u << OPCODE_SHIFT),
ADDIC__OPCODE = (13u << OPCODE_SHIFT),
ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1),
+ ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1),
+ ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1),
SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1),
SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1),
SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1),
SUBFIC_OPCODE = (8u << OPCODE_SHIFT),
+ SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1),
SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
*** 655,675 ****
ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
// Memory barriers
SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
// Trap instructions
TDI_OPCODE = (2u << OPCODE_SHIFT),
TWI_OPCODE = (3u << OPCODE_SHIFT),
TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
// Atomics.
LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
! STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
};
// Trap instructions TO bits
enum trap_to_bits {
--- 658,683 ----
ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
// Memory barriers
SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
+ // Wait instructions for polling.
+ WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1),
+
// Trap instructions
TDI_OPCODE = (2u << OPCODE_SHIFT),
TWI_OPCODE = (3u << OPCODE_SHIFT),
TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
// Atomics.
LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
+ LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
! STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
! STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
};
// Trap instructions TO bits
enum trap_to_bits {
*** 1169,1178 ****
--- 1177,1194 ----
inline void subfc_( Register d, Register a, Register b);
inline void adde( Register d, Register a, Register b);
inline void adde_( Register d, Register a, Register b);
inline void subfe( Register d, Register a, Register b);
inline void subfe_( Register d, Register a, Register b);
+ inline void addme( Register d, Register a);
+ inline void addme_( Register d, Register a);
+ inline void subfme( Register d, Register a);
+ inline void subfme_(Register d, Register a);
+ inline void addze( Register d, Register a);
+ inline void addze_( Register d, Register a);
+ inline void subfze( Register d, Register a);
+ inline void subfze_(Register d, Register a);
inline void neg( Register d, Register a);
inline void neg_( Register d, Register a);
inline void mulli( Register d, Register a, int si16);
inline void mulld( Register d, Register a, Register b);
inline void mulld_( Register d, Register a, Register b);
*** 1187,1196 ****
--- 1203,1244 ----
inline void divd( Register d, Register a, Register b);
inline void divd_( Register d, Register a, Register b);
inline void divw( Register d, Register a, Register b);
inline void divw_( Register d, Register a, Register b);
+ // Fixed-Point Arithmetic Instructions with Overflow detection
+ inline void addo( Register d, Register a, Register b);
+ inline void addo_( Register d, Register a, Register b);
+ inline void subfo( Register d, Register a, Register b);
+ inline void subfo_( Register d, Register a, Register b);
+ inline void addco( Register d, Register a, Register b);
+ inline void addco_( Register d, Register a, Register b);
+ inline void subfco( Register d, Register a, Register b);
+ inline void subfco_( Register d, Register a, Register b);
+ inline void addeo( Register d, Register a, Register b);
+ inline void addeo_( Register d, Register a, Register b);
+ inline void subfeo( Register d, Register a, Register b);
+ inline void subfeo_( Register d, Register a, Register b);
+ inline void addmeo( Register d, Register a);
+ inline void addmeo_( Register d, Register a);
+ inline void subfmeo( Register d, Register a);
+ inline void subfmeo_(Register d, Register a);
+ inline void addzeo( Register d, Register a);
+ inline void addzeo_( Register d, Register a);
+ inline void subfzeo( Register d, Register a);
+ inline void subfzeo_(Register d, Register a);
+ inline void nego( Register d, Register a);
+ inline void nego_( Register d, Register a);
+ inline void mulldo( Register d, Register a, Register b);
+ inline void mulldo_( Register d, Register a, Register b);
+ inline void mullwo( Register d, Register a, Register b);
+ inline void mullwo_( Register d, Register a, Register b);
+ inline void divdo( Register d, Register a, Register b);
+ inline void divdo_( Register d, Register a, Register b);
+ inline void divwo( Register d, Register a, Register b);
+ inline void divwo_( Register d, Register a, Register b);
+
// extended mnemonics
inline void li( Register d, int si16);
inline void lis( Register d, int si16);
inline void addir(Register d, int si16, Register a);
*** 1301,1311 ****
inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
// Set d = 0 if (cr.cc) equals 1, otherwise b.
inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
// PPC 1, section 3.3.11, Fixed-Point Logical Instructions
! void andi( Register a, Register s, int ui16); // optimized version
inline void andi_( Register a, Register s, int ui16);
inline void andis_( Register a, Register s, int ui16);
inline void ori( Register a, Register s, int ui16);
inline void oris( Register a, Register s, int ui16);
inline void xori( Register a, Register s, int ui16);
--- 1349,1359 ----
inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
// Set d = 0 if (cr.cc) equals 1, otherwise b.
inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
// PPC 1, section 3.3.11, Fixed-Point Logical Instructions
! void andi( Register a, Register s, long ui16); // optimized version
inline void andi_( Register a, Register s, int ui16);
inline void andis_( Register a, Register s, int ui16);
inline void ori( Register a, Register s, int ui16);
inline void oris( Register a, Register s, int ui16);
inline void xori( Register a, Register s, int ui16);
*** 1686,1703 ****
--- 1734,1758 ----
inline void ptesync();
inline void eieio();
inline void isync();
inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
+ // Wait instructions for polling. Attention: May result in SIGILL.
+ inline void wait();
+ inline void waitrsv(); // >=Power7
+
// atomics
inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
+ inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
inline bool lxarx_hint_exclusive_access();
inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
+ inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
inline void stwcx_( Register s, Register a, Register b);
inline void stdcx_( Register s, Register a, Register b);
+ inline void stqcx_( Register s, Register a, Register b);
// Instructions for adjusting thread priority for simultaneous
// multithreading (SMT) on Power5.
private:
inline void smt_prio_very_low();
*** 2052,2065 ****
--- 2107,2123 ----
inline void dcbtstct(Register s2, int ct);
// Atomics: use ra0mem to disallow R0 as base.
inline void lwarx_unchecked(Register d, Register b, int eh1);
inline void ldarx_unchecked(Register d, Register b, int eh1);
+ inline void lqarx_unchecked(Register d, Register b, int eh1);
inline void lwarx( Register d, Register b, bool hint_exclusive_access);
inline void ldarx( Register d, Register b, bool hint_exclusive_access);
+ inline void lqarx( Register d, Register b, bool hint_exclusive_access);
inline void stwcx_(Register s, Register b);
inline void stdcx_(Register s, Register b);
+ inline void stqcx_(Register s, Register b);
inline void lfs( FloatRegister d, int si16);
inline void lfsx( FloatRegister d, Register b);
inline void lfd( FloatRegister d, int si16);
inline void lfdx( FloatRegister d, Register b);
inline void stfs( FloatRegister s, int si16);
*** 2118,2127 ****
--- 2176,2199 ----
int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false);
inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
}
+ // If return_simm16_rest, the return value needs to get added afterwards.
+ int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false);
+ inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
+ return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
+ }
+
+ // If return_simm16_rest, the return value needs to get added afterwards.
+ inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) {
+ return add_const_optimized(d, s, -x, tmp, return_simm16_rest);
+ }
+ inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
+ return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
+ }
+
// Creation
Assembler(CodeBuffer* code) : AbstractAssembler(code) {
#ifdef CHECK_DELAY
delay_state = no_delay;
#endif
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