1 //
2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2015 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29,*/ // global TOC
451 R30,
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29,*/
488 R30,
489 R31
490 );
491
492 reg_class rscratch1_bits32_reg(R11);
493 reg_class rscratch2_bits32_reg(R12);
494 reg_class rarg1_bits32_reg(R3);
495 reg_class rarg2_bits32_reg(R4);
496 reg_class rarg3_bits32_reg(R5);
497 reg_class rarg4_bits32_reg(R6);
498
499 // ----------------------------
500 // 64 Bit Register Classes
501 // ----------------------------
502 // 64-bit build means 64-bit pointers means hi/lo pairs
503
504 reg_class rscratch1_bits64_reg(R11_H, R11);
505 reg_class rscratch2_bits64_reg(R12_H, R12);
506 reg_class rarg1_bits64_reg(R3_H, R3);
507 reg_class rarg2_bits64_reg(R4_H, R4);
508 reg_class rarg3_bits64_reg(R5_H, R5);
509 reg_class rarg4_bits64_reg(R6_H, R6);
510 // Thread register, 'written' by tlsLoadP, see there.
511 reg_class thread_bits64_reg(R16_H, R16);
512
513 reg_class r19_bits64_reg(R19_H, R19);
514
515 // 64 bit registers that can be read and written i.e. these registers
516 // can be dest (or src) of normal instructions.
517 reg_class bits64_reg_rw(
518 /*R0_H, R0*/ // R0
519 /*R1_H, R1*/ // SP
520 R2_H, R2, // TOC
521 R3_H, R3,
522 R4_H, R4,
523 R5_H, R5,
524 R6_H, R6,
525 R7_H, R7,
526 R8_H, R8,
527 R9_H, R9,
528 R10_H, R10,
529 R11_H, R11,
530 R12_H, R12,
531 /*R13_H, R13*/ // system thread id
532 R14_H, R14,
533 R15_H, R15,
534 /*R16_H, R16*/ // R16_thread
535 R17_H, R17,
536 R18_H, R18,
537 R19_H, R19,
538 R20_H, R20,
539 R21_H, R21,
540 R22_H, R22,
541 R23_H, R23,
542 R24_H, R24,
543 R25_H, R25,
544 R26_H, R26,
545 R27_H, R27,
546 R28_H, R28,
547 /*R29_H, R29,*/
548 R30_H, R30,
549 R31_H, R31
550 );
551
552 // 64 bit registers used excluding r2, r11 and r12
553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
554 // r2, r11 and r12 internally.
555 reg_class bits64_reg_leaf_call(
556 /*R0_H, R0*/ // R0
557 /*R1_H, R1*/ // SP
558 /*R2_H, R2*/ // TOC
559 R3_H, R3,
560 R4_H, R4,
561 R5_H, R5,
562 R6_H, R6,
563 R7_H, R7,
564 R8_H, R8,
565 R9_H, R9,
566 R10_H, R10,
567 /*R11_H, R11*/
568 /*R12_H, R12*/
569 /*R13_H, R13*/ // system thread id
570 R14_H, R14,
571 R15_H, R15,
572 /*R16_H, R16*/ // R16_thread
573 R17_H, R17,
574 R18_H, R18,
575 R19_H, R19,
576 R20_H, R20,
577 R21_H, R21,
578 R22_H, R22,
579 R23_H, R23,
580 R24_H, R24,
581 R25_H, R25,
582 R26_H, R26,
583 R27_H, R27,
584 R28_H, R28,
585 /*R29_H, R29,*/
586 R30_H, R30,
587 R31_H, R31
588 );
589
590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
591 // which uses r19 as inline cache internally and expanded LeafCall which uses
592 // r2, r11 and r12 internally.
593 reg_class bits64_constant_table_base(
594 /*R0_H, R0*/ // R0
595 /*R1_H, R1*/ // SP
596 /*R2_H, R2*/ // TOC
597 R3_H, R3,
598 R4_H, R4,
599 R5_H, R5,
600 R6_H, R6,
601 R7_H, R7,
602 R8_H, R8,
603 R9_H, R9,
604 R10_H, R10,
605 /*R11_H, R11*/
606 /*R12_H, R12*/
607 /*R13_H, R13*/ // system thread id
608 R14_H, R14,
609 R15_H, R15,
610 /*R16_H, R16*/ // R16_thread
611 R17_H, R17,
612 R18_H, R18,
613 /*R19_H, R19*/
614 R20_H, R20,
615 R21_H, R21,
616 R22_H, R22,
617 R23_H, R23,
618 R24_H, R24,
619 R25_H, R25,
620 R26_H, R26,
621 R27_H, R27,
622 R28_H, R28,
623 /*R29_H, R29,*/
624 R30_H, R30,
625 R31_H, R31
626 );
627
628 // 64 bit registers that can only be read i.e. these registers can
629 // only be src of all instructions.
630 reg_class bits64_reg_ro(
631 /*R0_H, R0*/ // R0
632 R1_H, R1,
633 R2_H, R2, // TOC
634 R3_H, R3,
635 R4_H, R4,
636 R5_H, R5,
637 R6_H, R6,
638 R7_H, R7,
639 R8_H, R8,
640 R9_H, R9,
641 R10_H, R10,
642 R11_H, R11,
643 R12_H, R12,
644 /*R13_H, R13*/ // system thread id
645 R14_H, R14,
646 R15_H, R15,
647 R16_H, R16, // R16_thread
648 R17_H, R17,
649 R18_H, R18,
650 R19_H, R19,
651 R20_H, R20,
652 R21_H, R21,
653 R22_H, R22,
654 R23_H, R23,
655 R24_H, R24,
656 R25_H, R25,
657 R26_H, R26,
658 R27_H, R27,
659 R28_H, R28,
660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
661 R30_H, R30,
662 R31_H, R31
663 );
664
665
666 // ----------------------------
667 // Special Class for Condition Code Flags Register
668
669 reg_class int_flags(
670 /*CCR0*/ // scratch
671 /*CCR1*/ // scratch
672 /*CCR2*/ // nv!
673 /*CCR3*/ // nv!
674 /*CCR4*/ // nv!
675 CCR5,
676 CCR6,
677 CCR7
678 );
679
680 reg_class int_flags_ro(
681 CCR0,
682 CCR1,
683 CCR2,
684 CCR3,
685 CCR4,
686 CCR5,
687 CCR6,
688 CCR7
689 );
690
691 reg_class int_flags_CR0(CCR0);
692 reg_class int_flags_CR1(CCR1);
693 reg_class int_flags_CR6(CCR6);
694 reg_class ctr_reg(SR_CTR);
695
696 // ----------------------------
697 // Float Register Classes
698 // ----------------------------
699
700 reg_class flt_reg(
701 /*F0*/ // scratch
702 F1,
703 F2,
704 F3,
705 F4,
706 F5,
707 F6,
708 F7,
709 F8,
710 F9,
711 F10,
712 F11,
713 F12,
714 F13,
715 F14, // nv!
716 F15, // nv!
717 F16, // nv!
718 F17, // nv!
719 F18, // nv!
720 F19, // nv!
721 F20, // nv!
722 F21, // nv!
723 F22, // nv!
724 F23, // nv!
725 F24, // nv!
726 F25, // nv!
727 F26, // nv!
728 F27, // nv!
729 F28, // nv!
730 F29, // nv!
731 F30, // nv!
732 F31 // nv!
733 );
734
735 // Double precision float registers have virtual `high halves' that
736 // are needed by the allocator.
737 reg_class dbl_reg(
738 /*F0, F0_H*/ // scratch
739 F1, F1_H,
740 F2, F2_H,
741 F3, F3_H,
742 F4, F4_H,
743 F5, F5_H,
744 F6, F6_H,
745 F7, F7_H,
746 F8, F8_H,
747 F9, F9_H,
748 F10, F10_H,
749 F11, F11_H,
750 F12, F12_H,
751 F13, F13_H,
752 F14, F14_H, // nv!
753 F15, F15_H, // nv!
754 F16, F16_H, // nv!
755 F17, F17_H, // nv!
756 F18, F18_H, // nv!
757 F19, F19_H, // nv!
758 F20, F20_H, // nv!
759 F21, F21_H, // nv!
760 F22, F22_H, // nv!
761 F23, F23_H, // nv!
762 F24, F24_H, // nv!
763 F25, F25_H, // nv!
764 F26, F26_H, // nv!
765 F27, F27_H, // nv!
766 F28, F28_H, // nv!
767 F29, F29_H, // nv!
768 F30, F30_H, // nv!
769 F31, F31_H // nv!
770 );
771
772 %}
773
774 //----------DEFINITION BLOCK---------------------------------------------------
775 // Define name --> value mappings to inform the ADLC of an integer valued name
776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
777 // Format:
778 // int_def <name> ( <int_value>, <expression>);
779 // Generated Code in ad_<arch>.hpp
780 // #define <name> (<expression>)
781 // // value == <int_value>
782 // Generated code in ad_<arch>.cpp adlc_verification()
783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
784 //
785 definitions %{
786 // The default cost (of an ALU instruction).
787 int_def DEFAULT_COST_LOW ( 30, 30);
788 int_def DEFAULT_COST ( 100, 100);
789 int_def HUGE_COST (1000000, 1000000);
790
791 // Memory refs
792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
794
795 // Branches are even more expensive.
796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
797 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
798 %}
799
800
801 //----------SOURCE BLOCK-------------------------------------------------------
802 // This is a block of C++ code which provides values, functions, and
803 // definitions necessary in the rest of the architecture description.
804 source_hpp %{
805 // Header information of the source block.
806 // Method declarations/definitions which are used outside
807 // the ad-scope can conveniently be defined here.
808 //
809 // To keep related declarations/definitions/uses close together,
810 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
811
812 // Returns true if Node n is followed by a MemBar node that
813 // will do an acquire. If so, this node must not do the acquire
814 // operation.
815 bool followed_by_acquire(const Node *n);
816 %}
817
818 source %{
819
820 // Optimize load-acquire.
821 //
822 // Check if acquire is unnecessary due to following operation that does
823 // acquire anyways.
824 // Walk the pattern:
825 //
826 // n: Load.acq
827 // |
828 // MemBarAcquire
829 // | |
830 // Proj(ctrl) Proj(mem)
831 // | |
832 // MemBarRelease/Volatile
833 //
834 bool followed_by_acquire(const Node *load) {
835 assert(load->is_Load(), "So far implemented only for loads.");
836
837 // Find MemBarAcquire.
838 const Node *mba = NULL;
839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
840 const Node *out = load->fast_out(i);
841 if (out->Opcode() == Op_MemBarAcquire) {
842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
843 mba = out;
844 break;
845 }
846 }
847 if (!mba) return false;
848
849 // Find following MemBar node.
850 //
851 // The following node must be reachable by control AND memory
852 // edge to assure no other operations are in between the two nodes.
853 //
854 // So first get the Proj node, mem_proj, to use it to iterate forward.
855 Node *mem_proj = NULL;
856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
858 assert(mem_proj->is_Proj(), "only projections here");
859 ProjNode *proj = mem_proj->as_Proj();
860 if (proj->_con == TypeFunc::Memory &&
861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
862 break;
863 }
864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
865
866 // Search MemBar behind Proj. If there are other memory operations
867 // behind the Proj we lost.
868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
869 Node *x = mem_proj->fast_out(j);
870 // Proj might have an edge to a store or load node which precedes the membar.
871 if (x->is_Mem()) return false;
872
873 // On PPC64 release and volatile are implemented by an instruction
874 // that also has acquire semantics. I.e. there is no need for an
875 // acquire before these.
876 int xop = x->Opcode();
877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
878 // Make sure we're not missing Call/Phi/MergeMem by checking
879 // control edges. The control edge must directly lead back
880 // to the MemBarAcquire
881 Node *ctrl_proj = x->in(0);
882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
883 return true;
884 }
885 }
886 }
887
888 return false;
889 }
890
891 #define __ _masm.
892
893 // Tertiary op of a LoadP or StoreP encoding.
894 #define REGP_OP true
895
896 // ****************************************************************************
897
898 // REQUIRED FUNCTIONALITY
899
900 // !!!!! Special hack to get all type of calls to specify the byte offset
901 // from the start of the call to the point where the return address
902 // will point.
903
904 // PPC port: Removed use of lazy constant construct.
905
906 int MachCallStaticJavaNode::ret_addr_offset() {
907 // It's only a single branch-and-link instruction.
908 return 4;
909 }
910
911 int MachCallDynamicJavaNode::ret_addr_offset() {
912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
913 // postalloc expanded calls if we use inline caches and do not update method data.
914 if (UseInlineCaches)
915 return 4;
916
917 int vtable_index = this->_vtable_index;
918 if (vtable_index < 0) {
919 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
921 return 12;
922 } else {
923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
924 return 24;
925 }
926 }
927
928 int MachCallRuntimeNode::ret_addr_offset() {
929 #if defined(ABI_ELFv2)
930 return 28;
931 #else
932 return 40;
933 #endif
934 }
935
936 //=============================================================================
937
938 // condition code conversions
939
940 static int cc_to_boint(int cc) {
941 return Assembler::bcondCRbiIs0 | (cc & 8);
942 }
943
944 static int cc_to_inverse_boint(int cc) {
945 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
946 }
947
948 static int cc_to_biint(int cc, int flags_reg) {
949 return (flags_reg << 2) | (cc & 3);
950 }
951
952 //=============================================================================
953
954 // Compute padding required for nodes which need alignment. The padding
955 // is the number of bytes (not instructions) which will be inserted before
956 // the instruction. The padding must match the size of a NOP instruction.
957
958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
959 return (3*4-current_offset)&31;
960 }
961
962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
963 return (2*4-current_offset)&31;
964 }
965
966 int string_indexOf_immNode::compute_padding(int current_offset) const {
967 return (3*4-current_offset)&31;
968 }
969
970 int string_indexOfNode::compute_padding(int current_offset) const {
971 return (1*4-current_offset)&31;
972 }
973
974 int string_compareNode::compute_padding(int current_offset) const {
975 return (4*4-current_offset)&31;
976 }
977
978 int string_equals_immNode::compute_padding(int current_offset) const {
979 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
980 return (2*4-current_offset)&31;
981 }
982
983 int string_equalsNode::compute_padding(int current_offset) const {
984 return (7*4-current_offset)&31;
985 }
986
987 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
988 return (2*4-current_offset)&31;
989 }
990
991 //=============================================================================
992
993 // Indicate if the safepoint node needs the polling page as an input.
994 bool SafePointNode::needs_polling_address_input() {
995 // The address is loaded from thread by a seperate node.
996 return true;
997 }
998
999 //=============================================================================
1000
1001 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1002 void emit_break(CodeBuffer &cbuf) {
1003 MacroAssembler _masm(&cbuf);
1004 __ illtrap();
1005 }
1006
1007 #ifndef PRODUCT
1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1009 st->print("BREAKPOINT");
1010 }
1011 #endif
1012
1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1014 emit_break(cbuf);
1015 }
1016
1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1018 return MachNode::size(ra_);
1019 }
1020
1021 //=============================================================================
1022
1023 void emit_nop(CodeBuffer &cbuf) {
1024 MacroAssembler _masm(&cbuf);
1025 __ nop();
1026 }
1027
1028 static inline void emit_long(CodeBuffer &cbuf, int value) {
1029 *((int*)(cbuf.insts_end())) = value;
1030 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1031 }
1032
1033 //=============================================================================
1034
1035 %} // interrupt source
1036
1037 source_hpp %{ // Header information of the source block.
1038
1039 //--------------------------------------------------------------
1040 //---< Used for optimization in Compile::Shorten_branches >---
1041 //--------------------------------------------------------------
1042
1043 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1044
1045 class CallStubImpl {
1046
1047 public:
1048
1049 // Emit call stub, compiled java to interpreter.
1050 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1051
1052 // Size of call trampoline stub.
1053 // This doesn't need to be accurate to the byte, but it
1054 // must be larger than or equal to the real size of the stub.
1055 static uint size_call_trampoline() {
1056 return trampoline_stub_size;
1057 }
1058
1059 // number of relocations needed by a call trampoline stub
1060 static uint reloc_call_trampoline() {
1061 return 5;
1062 }
1063
1064 };
1065
1066 %} // end source_hpp
1067
1068 source %{
1069
1070 // Emit a trampoline stub for a call to a target which is too far away.
1071 //
1072 // code sequences:
1073 //
1074 // call-site:
1075 // branch-and-link to <destination> or <trampoline stub>
1076 //
1077 // Related trampoline stub for this call-site in the stub section:
1078 // load the call target from the constant pool
1079 // branch via CTR (LR/link still points to the call-site above)
1080
1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1082 // Start the stub.
1083 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1084 if (stub == NULL) {
1085 Compile::current()->env()->record_out_of_memory_failure();
1086 return;
1087 }
1088
1089 // For java_to_interp stubs we use R11_scratch1 as scratch register
1090 // and in call trampoline stubs we use R12_scratch2. This way we
1091 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1092 Register reg_scratch = R12_scratch2;
1093
1094 // Create a trampoline stub relocation which relates this trampoline stub
1095 // with the call instruction at insts_call_instruction_offset in the
1096 // instructions code-section.
1097 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1098 const int stub_start_offset = __ offset();
1099
1100 // Now, create the trampoline stub's code:
1101 // - load the TOC
1102 // - load the call target from the constant pool
1103 // - call
1104 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1105 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1106 __ mtctr(reg_scratch);
1107 __ bctr();
1108
1109 const address stub_start_addr = __ addr_at(stub_start_offset);
1110
1111 // FIXME: Assert that the trampoline stub can be identified and patched.
1112
1113 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1114 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1115 "encoded offset into the constant pool must match");
1116 // Trampoline_stub_size should be good.
1117 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1118 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1119
1120 // End the stub.
1121 __ end_a_stub();
1122 }
1123
1124 //=============================================================================
1125
1126 // Emit an inline branch-and-link call and a related trampoline stub.
1127 //
1128 // code sequences:
1129 //
1130 // call-site:
1131 // branch-and-link to <destination> or <trampoline stub>
1132 //
1133 // Related trampoline stub for this call-site in the stub section:
1134 // load the call target from the constant pool
1135 // branch via CTR (LR/link still points to the call-site above)
1136 //
1137
1138 typedef struct {
1139 int insts_call_instruction_offset;
1140 int ret_addr_offset;
1141 } EmitCallOffsets;
1142
1143 // Emit a branch-and-link instruction that branches to a trampoline.
1144 // - Remember the offset of the branch-and-link instruction.
1145 // - Add a relocation at the branch-and-link instruction.
1146 // - Emit a branch-and-link.
1147 // - Remember the return pc offset.
1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1149 EmitCallOffsets offsets = { -1, -1 };
1150 const int start_offset = __ offset();
1151 offsets.insts_call_instruction_offset = __ offset();
1152
1153 // No entry point given, use the current pc.
1154 if (entry_point == NULL) entry_point = __ pc();
1155
1156 if (!Compile::current()->in_scratch_emit_size()) {
1157 // Put the entry point as a constant into the constant pool.
1158 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1159 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1160
1161 // Emit the trampoline stub which will be related to the branch-and-link below.
1162 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1163 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full.
1164 __ relocate(rtype);
1165 }
1166
1167 // Note: At this point we do not have the address of the trampoline
1168 // stub, and the entry point might be too far away for bl, so __ pc()
1169 // serves as dummy and the bl will be patched later.
1170 __ bl((address) __ pc());
1171
1172 offsets.ret_addr_offset = __ offset() - start_offset;
1173
1174 return offsets;
1175 }
1176
1177 //=============================================================================
1178
1179 // Factory for creating loadConL* nodes for large/small constant pool.
1180
1181 static inline jlong replicate_immF(float con) {
1182 // Replicate float con 2 times and pack into vector.
1183 int val = *((int*)&con);
1184 jlong lval = val;
1185 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1186 return lval;
1187 }
1188
1189 //=============================================================================
1190
1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1192 int Compile::ConstantTable::calculate_table_base_offset() const {
1193 return 0; // absolute addressing, no offset
1194 }
1195
1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1198 iRegPdstOper *op_dst = new iRegPdstOper();
1199 MachNode *m1 = new loadToc_hiNode();
1200 MachNode *m2 = new loadToc_loNode();
1201
1202 m1->add_req(NULL);
1203 m2->add_req(NULL, m1);
1204 m1->_opnds[0] = op_dst;
1205 m2->_opnds[0] = op_dst;
1206 m2->_opnds[1] = op_dst;
1207 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1208 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1209 nodes->push(m1);
1210 nodes->push(m2);
1211 }
1212
1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1214 // Is postalloc expanded.
1215 ShouldNotReachHere();
1216 }
1217
1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1219 return 0;
1220 }
1221
1222 #ifndef PRODUCT
1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1224 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1225 }
1226 #endif
1227
1228 //=============================================================================
1229
1230 #ifndef PRODUCT
1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1232 Compile* C = ra_->C;
1233 const long framesize = C->frame_slots() << LogBytesPerInt;
1234
1235 st->print("PROLOG\n\t");
1236 if (C->need_stack_bang(framesize)) {
1237 st->print("stack_overflow_check\n\t");
1238 }
1239
1240 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1241 st->print("save return pc\n\t");
1242 st->print("push frame %ld\n\t", -framesize);
1243 }
1244 }
1245 #endif
1246
1247 // Macro used instead of the common __ to emulate the pipes of PPC.
1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1250 // still no scheduling of this code is possible, the micro scheduler is aware of the
1251 // code and can update its internal data. The following mechanism is used to achieve this:
1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1254 #if 0 // TODO: PPC port
1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1256 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1257 _masm.
1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1259 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1261 C->hb_scheduling()->_pdScheduling->advance_offset
1262 #else
1263 #define ___(op) if (UsePower6SchedulerPPC64) \
1264 Unimplemented(); \
1265 _masm.
1266 #define ___stop if (UsePower6SchedulerPPC64) \
1267 Unimplemented()
1268 #define ___advance if (UsePower6SchedulerPPC64) \
1269 Unimplemented()
1270 #endif
1271
1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273 Compile* C = ra_->C;
1274 MacroAssembler _masm(&cbuf);
1275
1276 const long framesize = C->frame_size_in_bytes();
1277 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1278
1279 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1280
1281 const Register return_pc = R20; // Must match return_addr() in frame section.
1282 const Register callers_sp = R21;
1283 const Register push_frame_temp = R22;
1284 const Register toc_temp = R23;
1285 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1286
1287 if (method_is_frameless) {
1288 // Add nop at beginning of all frameless methods to prevent any
1289 // oop instructions from getting overwritten by make_not_entrant
1290 // (patching attempt would fail).
1291 ___(nop) nop();
1292 } else {
1293 // Get return pc.
1294 ___(mflr) mflr(return_pc);
1295 }
1296
1297 // Calls to C2R adapters often do not accept exceptional returns.
1298 // We require that their callers must bang for them. But be
1299 // careful, because some VM calls (such as call site linkage) can
1300 // use several kilobytes of stack. But the stack safety zone should
1301 // account for that. See bugs 4446381, 4468289, 4497237.
1302
1303 int bangsize = C->bang_size_in_bytes();
1304 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1305 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1306 // Unfortunately we cannot use the function provided in
1307 // assembler.cpp as we have to emulate the pipes. So I had to
1308 // insert the code of generate_stack_overflow_check(), see
1309 // assembler.cpp for some illuminative comments.
1310 const int page_size = os::vm_page_size();
1311 int bang_end = StackShadowPages * page_size;
1312
1313 // This is how far the previous frame's stack banging extended.
1314 const int bang_end_safe = bang_end;
1315
1316 if (bangsize > page_size) {
1317 bang_end += bangsize;
1318 }
1319
1320 int bang_offset = bang_end_safe;
1321
1322 while (bang_offset <= bang_end) {
1323 // Need at least one stack bang at end of shadow zone.
1324
1325 // Again I had to copy code, this time from assembler_ppc.cpp,
1326 // bang_stack_with_offset - see there for comments.
1327
1328 // Stack grows down, caller passes positive offset.
1329 assert(bang_offset > 0, "must bang with positive offset");
1330
1331 long stdoffset = -bang_offset;
1332
1333 if (Assembler::is_simm(stdoffset, 16)) {
1334 // Signed 16 bit offset, a simple std is ok.
1335 if (UseLoadInstructionsForStackBangingPPC64) {
1336 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1337 } else {
1338 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1339 }
1340 } else if (Assembler::is_simm(stdoffset, 31)) {
1341 // Use largeoffset calculations for addis & ld/std.
1342 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1343 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1344
1345 Register tmp = R11;
1346 ___(addis) addis(tmp, R1_SP, hi);
1347 if (UseLoadInstructionsForStackBangingPPC64) {
1348 ___(ld) ld(R0, lo, tmp);
1349 } else {
1350 ___(std) std(R0, lo, tmp);
1351 }
1352 } else {
1353 ShouldNotReachHere();
1354 }
1355
1356 bang_offset += page_size;
1357 }
1358 // R11 trashed
1359 } // C->need_stack_bang(framesize) && UseStackBanging
1360
1361 unsigned int bytes = (unsigned int)framesize;
1362 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1363 ciMethod *currMethod = C->method();
1364
1365 // Optimized version for most common case.
1366 if (UsePower6SchedulerPPC64 &&
1367 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1368 !(false /* ConstantsALot TODO: PPC port*/)) {
1369 ___(or) mr(callers_sp, R1_SP);
1370 ___(std) std(return_pc, _abi(lr), R1_SP);
1371 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1372 return;
1373 }
1374
1375 if (!method_is_frameless) {
1376 // Get callers sp.
1377 ___(or) mr(callers_sp, R1_SP);
1378
1379 // Push method's frame, modifies SP.
1380 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1381 // The ABI is already accounted for in 'framesize' via the
1382 // 'out_preserve' area.
1383 Register tmp = push_frame_temp;
1384 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1385 if (Assembler::is_simm(-offset, 16)) {
1386 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1387 } else {
1388 long x = -offset;
1389 // Had to insert load_const(tmp, -offset).
1390 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1391 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1392 ___(rldicr) sldi(tmp, tmp, 32);
1393 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1394 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1395
1396 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1397 }
1398 }
1399 #if 0 // TODO: PPC port
1400 // For testing large constant pools, emit a lot of constants to constant pool.
1401 // "Randomize" const_size.
1402 if (ConstantsALot) {
1403 const int num_consts = const_size();
1404 for (int i = 0; i < num_consts; i++) {
1405 __ long_constant(0xB0B5B00BBABE);
1406 }
1407 }
1408 #endif
1409 if (!method_is_frameless) {
1410 // Save return pc.
1411 ___(std) std(return_pc, _abi(lr), callers_sp);
1412 }
1413 }
1414 #undef ___
1415 #undef ___stop
1416 #undef ___advance
1417
1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1419 // Variable size. determine dynamically.
1420 return MachNode::size(ra_);
1421 }
1422
1423 int MachPrologNode::reloc() const {
1424 // Return number of relocatable values contained in this instruction.
1425 return 1; // 1 reloc entry for load_const(toc).
1426 }
1427
1428 //=============================================================================
1429
1430 #ifndef PRODUCT
1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1432 Compile* C = ra_->C;
1433
1434 st->print("EPILOG\n\t");
1435 st->print("restore return pc\n\t");
1436 st->print("pop frame\n\t");
1437
1438 if (do_polling() && C->is_method_compilation()) {
1439 st->print("touch polling page\n\t");
1440 }
1441 }
1442 #endif
1443
1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445 Compile* C = ra_->C;
1446 MacroAssembler _masm(&cbuf);
1447
1448 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1449 assert(framesize >= 0, "negative frame-size?");
1450
1451 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1452 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1453 const Register return_pc = R11;
1454 const Register polling_page = R12;
1455
1456 if (!method_is_frameless) {
1457 // Restore return pc relative to callers' sp.
1458 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1459 }
1460
1461 if (method_needs_polling) {
1462 if (LoadPollAddressFromThread) {
1463 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1464 Unimplemented();
1465 } else {
1466 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1467 }
1468 }
1469
1470 if (!method_is_frameless) {
1471 // Move return pc to LR.
1472 __ mtlr(return_pc);
1473 // Pop frame (fixed frame-size).
1474 __ addi(R1_SP, R1_SP, (int)framesize);
1475 }
1476
1477 if (method_needs_polling) {
1478 // We need to mark the code position where the load from the safepoint
1479 // polling page was emitted as relocInfo::poll_return_type here.
1480 __ relocate(relocInfo::poll_return_type);
1481 __ load_from_polling_page(polling_page);
1482 }
1483 }
1484
1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1486 // Variable size. Determine dynamically.
1487 return MachNode::size(ra_);
1488 }
1489
1490 int MachEpilogNode::reloc() const {
1491 // Return number of relocatable values contained in this instruction.
1492 return 1; // 1 for load_from_polling_page.
1493 }
1494
1495 const Pipeline * MachEpilogNode::pipeline() const {
1496 return MachNode::pipeline_class();
1497 }
1498
1499 // This method seems to be obsolete. It is declared in machnode.hpp
1500 // and defined in all *.ad files, but it is never called. Should we
1501 // get rid of it?
1502 int MachEpilogNode::safepoint_offset() const {
1503 assert(do_polling(), "no return for this epilog node");
1504 return 0;
1505 }
1506
1507 #if 0 // TODO: PPC port
1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1509 MacroAssembler _masm(&cbuf);
1510 if (LoadPollAddressFromThread) {
1511 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1512 } else {
1513 _masm.nop();
1514 }
1515 }
1516
1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1518 if (LoadPollAddressFromThread) {
1519 return 4;
1520 } else {
1521 return 4;
1522 }
1523 }
1524
1525 #ifndef PRODUCT
1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1527 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1528 }
1529 #endif
1530
1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1532 return RSCRATCH1_BITS64_REG_mask();
1533 }
1534 #endif // PPC port
1535
1536 // =============================================================================
1537
1538 // Figure out which register class each belongs in: rc_int, rc_float or
1539 // rc_stack.
1540 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1541
1542 static enum RC rc_class(OptoReg::Name reg) {
1543 // Return the register class for the given register. The given register
1544 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1545 // enumeration in adGlobals_ppc.hpp.
1546
1547 if (reg == OptoReg::Bad) return rc_bad;
1548
1549 // We have 64 integer register halves, starting at index 0.
1550 if (reg < 64) return rc_int;
1551
1552 // We have 64 floating-point register halves, starting at index 64.
1553 if (reg < 64+64) return rc_float;
1554
1555 // Between float regs & stack are the flags regs.
1556 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1557
1558 return rc_stack;
1559 }
1560
1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1562 bool do_print, Compile* C, outputStream *st) {
1563
1564 assert(opcode == Assembler::LD_OPCODE ||
1565 opcode == Assembler::STD_OPCODE ||
1566 opcode == Assembler::LWZ_OPCODE ||
1567 opcode == Assembler::STW_OPCODE ||
1568 opcode == Assembler::LFD_OPCODE ||
1569 opcode == Assembler::STFD_OPCODE ||
1570 opcode == Assembler::LFS_OPCODE ||
1571 opcode == Assembler::STFS_OPCODE,
1572 "opcode not supported");
1573
1574 if (cbuf) {
1575 int d =
1576 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1577 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1578 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1579 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1580 }
1581 #ifndef PRODUCT
1582 else if (do_print) {
1583 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1584 op_str,
1585 Matcher::regName[reg],
1586 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1587 }
1588 #endif
1589 return 4; // size
1590 }
1591
1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1593 Compile* C = ra_->C;
1594
1595 // Get registers to move.
1596 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1597 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1598 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1599 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1600
1601 enum RC src_hi_rc = rc_class(src_hi);
1602 enum RC src_lo_rc = rc_class(src_lo);
1603 enum RC dst_hi_rc = rc_class(dst_hi);
1604 enum RC dst_lo_rc = rc_class(dst_lo);
1605
1606 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1607 if (src_hi != OptoReg::Bad)
1608 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1609 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1610 "expected aligned-adjacent pairs");
1611 // Generate spill code!
1612 int size = 0;
1613
1614 if (src_lo == dst_lo && src_hi == dst_hi)
1615 return size; // Self copy, no move.
1616
1617 // --------------------------------------
1618 // Memory->Memory Spill. Use R0 to hold the value.
1619 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1620 int src_offset = ra_->reg2offset(src_lo);
1621 int dst_offset = ra_->reg2offset(dst_lo);
1622 if (src_hi != OptoReg::Bad) {
1623 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1624 "expected same type of move for high parts");
1625 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1626 if (!cbuf && !do_size) st->print("\n\t");
1627 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1628 } else {
1629 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1630 if (!cbuf && !do_size) st->print("\n\t");
1631 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1632 }
1633 return size;
1634 }
1635
1636 // --------------------------------------
1637 // Check for float->int copy; requires a trip through memory.
1638 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1639 Unimplemented();
1640 }
1641
1642 // --------------------------------------
1643 // Check for integer reg-reg copy.
1644 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1645 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1646 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1647 size = (Rsrc != Rdst) ? 4 : 0;
1648
1649 if (cbuf) {
1650 MacroAssembler _masm(cbuf);
1651 if (size) {
1652 __ mr(Rdst, Rsrc);
1653 }
1654 }
1655 #ifndef PRODUCT
1656 else if (!do_size) {
1657 if (size) {
1658 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1659 } else {
1660 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1661 }
1662 }
1663 #endif
1664 return size;
1665 }
1666
1667 // Check for integer store.
1668 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1669 int dst_offset = ra_->reg2offset(dst_lo);
1670 if (src_hi != OptoReg::Bad) {
1671 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1672 "expected same type of move for high parts");
1673 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1674 } else {
1675 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1676 }
1677 return size;
1678 }
1679
1680 // Check for integer load.
1681 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1682 int src_offset = ra_->reg2offset(src_lo);
1683 if (src_hi != OptoReg::Bad) {
1684 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1685 "expected same type of move for high parts");
1686 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1687 } else {
1688 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1689 }
1690 return size;
1691 }
1692
1693 // Check for float reg-reg copy.
1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1695 if (cbuf) {
1696 MacroAssembler _masm(cbuf);
1697 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1698 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1699 __ fmr(Rdst, Rsrc);
1700 }
1701 #ifndef PRODUCT
1702 else if (!do_size) {
1703 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1704 }
1705 #endif
1706 return 4;
1707 }
1708
1709 // Check for float store.
1710 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1711 int dst_offset = ra_->reg2offset(dst_lo);
1712 if (src_hi != OptoReg::Bad) {
1713 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1714 "expected same type of move for high parts");
1715 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1716 } else {
1717 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1718 }
1719 return size;
1720 }
1721
1722 // Check for float load.
1723 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1724 int src_offset = ra_->reg2offset(src_lo);
1725 if (src_hi != OptoReg::Bad) {
1726 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1727 "expected same type of move for high parts");
1728 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1729 } else {
1730 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1731 }
1732 return size;
1733 }
1734
1735 // --------------------------------------------------------------------
1736 // Check for hi bits still needing moving. Only happens for misaligned
1737 // arguments to native calls.
1738 if (src_hi == dst_hi)
1739 return size; // Self copy; no move.
1740
1741 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1742 ShouldNotReachHere(); // Unimplemented
1743 return 0;
1744 }
1745
1746 #ifndef PRODUCT
1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748 if (!ra_)
1749 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1750 else
1751 implementation(NULL, ra_, false, st);
1752 }
1753 #endif
1754
1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1756 implementation(&cbuf, ra_, false, NULL);
1757 }
1758
1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1760 return implementation(NULL, ra_, true, NULL);
1761 }
1762
1763 #if 0 // TODO: PPC port
1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1765 #ifndef PRODUCT
1766 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1767 #endif
1768 assert(ra_->node_regs_max_index() != 0, "");
1769
1770 // Get registers to move.
1771 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1772 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1773 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1774 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1775
1776 enum RC src_lo_rc = rc_class(src_lo);
1777 enum RC dst_lo_rc = rc_class(dst_lo);
1778
1779 if (src_lo == dst_lo && src_hi == dst_hi)
1780 return ppc64Opcode_none; // Self copy, no move.
1781
1782 // --------------------------------------
1783 // Memory->Memory Spill. Use R0 to hold the value.
1784 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1785 return ppc64Opcode_compound;
1786 }
1787
1788 // --------------------------------------
1789 // Check for float->int copy; requires a trip through memory.
1790 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1791 Unimplemented();
1792 }
1793
1794 // --------------------------------------
1795 // Check for integer reg-reg copy.
1796 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1797 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1798 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1799 if (Rsrc == Rdst) {
1800 return ppc64Opcode_none;
1801 } else {
1802 return ppc64Opcode_or;
1803 }
1804 }
1805
1806 // Check for integer store.
1807 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1808 if (src_hi != OptoReg::Bad) {
1809 return ppc64Opcode_std;
1810 } else {
1811 return ppc64Opcode_stw;
1812 }
1813 }
1814
1815 // Check for integer load.
1816 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1817 if (src_hi != OptoReg::Bad) {
1818 return ppc64Opcode_ld;
1819 } else {
1820 return ppc64Opcode_lwz;
1821 }
1822 }
1823
1824 // Check for float reg-reg copy.
1825 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1826 return ppc64Opcode_fmr;
1827 }
1828
1829 // Check for float store.
1830 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1831 if (src_hi != OptoReg::Bad) {
1832 return ppc64Opcode_stfd;
1833 } else {
1834 return ppc64Opcode_stfs;
1835 }
1836 }
1837
1838 // Check for float load.
1839 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1840 if (src_hi != OptoReg::Bad) {
1841 return ppc64Opcode_lfd;
1842 } else {
1843 return ppc64Opcode_lfs;
1844 }
1845 }
1846
1847 // --------------------------------------------------------------------
1848 // Check for hi bits still needing moving. Only happens for misaligned
1849 // arguments to native calls.
1850 if (src_hi == dst_hi) {
1851 return ppc64Opcode_none; // Self copy; no move.
1852 }
1853
1854 ShouldNotReachHere();
1855 return ppc64Opcode_undefined;
1856 }
1857 #endif // PPC port
1858
1859 #ifndef PRODUCT
1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1861 st->print("NOP \t// %d nops to pad for loops.", _count);
1862 }
1863 #endif
1864
1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1866 MacroAssembler _masm(&cbuf);
1867 // _count contains the number of nops needed for padding.
1868 for (int i = 0; i < _count; i++) {
1869 __ nop();
1870 }
1871 }
1872
1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1874 return _count * 4;
1875 }
1876
1877 #ifndef PRODUCT
1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1879 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1880 char reg_str[128];
1881 ra_->dump_register(this, reg_str);
1882 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1883 }
1884 #endif
1885
1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1887 MacroAssembler _masm(&cbuf);
1888
1889 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1890 int reg = ra_->get_encode(this);
1891
1892 if (Assembler::is_simm(offset, 16)) {
1893 __ addi(as_Register(reg), R1, offset);
1894 } else {
1895 ShouldNotReachHere();
1896 }
1897 }
1898
1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1900 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1901 return 4;
1902 }
1903
1904 #ifndef PRODUCT
1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1906 st->print_cr("---- MachUEPNode ----");
1907 st->print_cr("...");
1908 }
1909 #endif
1910
1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1912 // This is the unverified entry point.
1913 MacroAssembler _masm(&cbuf);
1914
1915 // Inline_cache contains a klass.
1916 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1917 Register receiver_klass = R12_scratch2; // tmp
1918
1919 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1920 assert(R11_scratch1 == R11, "need prologue scratch register");
1921
1922 // Check for NULL argument if we don't have implicit null checks.
1923 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1924 if (TrapBasedNullChecks) {
1925 __ trap_null_check(R3_ARG1);
1926 } else {
1927 Label valid;
1928 __ cmpdi(CCR0, R3_ARG1, 0);
1929 __ bne_predict_taken(CCR0, valid);
1930 // We have a null argument, branch to ic_miss_stub.
1931 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1932 relocInfo::runtime_call_type);
1933 __ bind(valid);
1934 }
1935 }
1936 // Assume argument is not NULL, load klass from receiver.
1937 __ load_klass(receiver_klass, R3_ARG1);
1938
1939 if (TrapBasedICMissChecks) {
1940 __ trap_ic_miss_check(receiver_klass, ic_klass);
1941 } else {
1942 Label valid;
1943 __ cmpd(CCR0, receiver_klass, ic_klass);
1944 __ beq_predict_taken(CCR0, valid);
1945 // We have an unexpected klass, branch to ic_miss_stub.
1946 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1947 relocInfo::runtime_call_type);
1948 __ bind(valid);
1949 }
1950
1951 // Argument is valid and klass is as expected, continue.
1952 }
1953
1954 #if 0 // TODO: PPC port
1955 // Optimize UEP code on z (save a load_const() call in main path).
1956 int MachUEPNode::ep_offset() {
1957 return 0;
1958 }
1959 #endif
1960
1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1962 // Variable size. Determine dynamically.
1963 return MachNode::size(ra_);
1964 }
1965
1966 //=============================================================================
1967
1968 %} // interrupt source
1969
1970 source_hpp %{ // Header information of the source block.
1971
1972 class HandlerImpl {
1973
1974 public:
1975
1976 static int emit_exception_handler(CodeBuffer &cbuf);
1977 static int emit_deopt_handler(CodeBuffer& cbuf);
1978
1979 static uint size_exception_handler() {
1980 // The exception_handler is a b64_patchable.
1981 return MacroAssembler::b64_patchable_size;
1982 }
1983
1984 static uint size_deopt_handler() {
1985 // The deopt_handler is a bl64_patchable.
1986 return MacroAssembler::bl64_patchable_size;
1987 }
1988
1989 };
1990
1991 %} // end source_hpp
1992
1993 source %{
1994
1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1996 MacroAssembler _masm(&cbuf);
1997
1998 address base = __ start_a_stub(size_exception_handler());
1999 if (base == NULL) return 0; // CodeBuffer::expand failed
2000
2001 int offset = __ offset();
2002 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2003 relocInfo::runtime_call_type);
2004 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2005 __ end_a_stub();
2006
2007 return offset;
2008 }
2009
2010 // The deopt_handler is like the exception handler, but it calls to
2011 // the deoptimization blob instead of jumping to the exception blob.
2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2013 MacroAssembler _masm(&cbuf);
2014
2015 address base = __ start_a_stub(size_deopt_handler());
2016 if (base == NULL) return 0; // CodeBuffer::expand failed
2017
2018 int offset = __ offset();
2019 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2020 relocInfo::runtime_call_type);
2021 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2022 __ end_a_stub();
2023
2024 return offset;
2025 }
2026
2027 //=============================================================================
2028
2029 // Use a frame slots bias for frameless methods if accessing the stack.
2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2031 if (as_Register(reg_enc) == R1_SP) {
2032 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2033 }
2034 return 0;
2035 }
2036
2037 const bool Matcher::match_rule_supported(int opcode) {
2038 if (!has_match_rule(opcode))
2039 return false;
2040
2041 switch (opcode) {
2042 case Op_SqrtD:
2043 return VM_Version::has_fsqrt();
2044 case Op_CountLeadingZerosI:
2045 case Op_CountLeadingZerosL:
2046 case Op_CountTrailingZerosI:
2047 case Op_CountTrailingZerosL:
2048 if (!UseCountLeadingZerosInstructionsPPC64)
2049 return false;
2050 break;
2051
2052 case Op_PopCountI:
2053 case Op_PopCountL:
2054 return (UsePopCountInstruction && VM_Version::has_popcntw());
2055
2056 case Op_StrComp:
2057 return SpecialStringCompareTo;
2058 case Op_StrEquals:
2059 return SpecialStringEquals;
2060 case Op_StrIndexOf:
2061 return SpecialStringIndexOf;
2062 }
2063
2064 return true; // Per default match rules are supported.
2065 }
2066
2067 int Matcher::regnum_to_fpu_offset(int regnum) {
2068 // No user for this method?
2069 Unimplemented();
2070 return 999;
2071 }
2072
2073 const bool Matcher::convL2FSupported(void) {
2074 // fcfids can do the conversion (>= Power7).
2075 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2076 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2077 }
2078
2079 // Vector width in bytes.
2080 const int Matcher::vector_width_in_bytes(BasicType bt) {
2081 assert(MaxVectorSize == 8, "");
2082 return 8;
2083 }
2084
2085 // Vector ideal reg.
2086 const int Matcher::vector_ideal_reg(int size) {
2087 assert(MaxVectorSize == 8 && size == 8, "");
2088 return Op_RegL;
2089 }
2090
2091 const int Matcher::vector_shift_count_ideal_reg(int size) {
2092 fatal("vector shift is not supported");
2093 return Node::NotAMachineReg;
2094 }
2095
2096 // Limits on vector size (number of elements) loaded into vector.
2097 const int Matcher::max_vector_size(const BasicType bt) {
2098 assert(is_java_primitive(bt), "only primitive type vectors");
2099 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2100 }
2101
2102 const int Matcher::min_vector_size(const BasicType bt) {
2103 return max_vector_size(bt); // Same as max.
2104 }
2105
2106 // PPC doesn't support misaligned vectors store/load.
2107 const bool Matcher::misaligned_vectors_ok() {
2108 return false;
2109 }
2110
2111 // PPC AES support not yet implemented
2112 const bool Matcher::pass_original_key_for_aes() {
2113 return false;
2114 }
2115
2116 // RETURNS: whether this branch offset is short enough that a short
2117 // branch can be used.
2118 //
2119 // If the platform does not provide any short branch variants, then
2120 // this method should return `false' for offset 0.
2121 //
2122 // `Compile::Fill_buffer' will decide on basis of this information
2123 // whether to do the pass `Compile::Shorten_branches' at all.
2124 //
2125 // And `Compile::Shorten_branches' will decide on basis of this
2126 // information whether to replace particular branch sites by short
2127 // ones.
2128 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2129 // Is the offset within the range of a ppc64 pc relative branch?
2130 bool b;
2131
2132 const int safety_zone = 3 * BytesPerInstWord;
2133 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2134 29 - 16 + 1 + 2);
2135 return b;
2136 }
2137
2138 const bool Matcher::isSimpleConstant64(jlong value) {
2139 // Probably always true, even if a temp register is required.
2140 return true;
2141 }
2142 /* TODO: PPC port
2143 // Make a new machine dependent decode node (with its operands).
2144 MachTypeNode *Matcher::make_decode_node() {
2145 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2146 "This method is only implemented for unscaled cOops mode so far");
2147 MachTypeNode *decode = new decodeN_unscaledNode();
2148 decode->set_opnd_array(0, new iRegPdstOper());
2149 decode->set_opnd_array(1, new iRegNsrcOper());
2150 return decode;
2151 }
2152 */
2153 // Threshold size for cleararray.
2154 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2155
2156 // false => size gets scaled to BytesPerLong, ok.
2157 const bool Matcher::init_array_count_is_in_bytes = false;
2158
2159 // Use conditional move (CMOVL) on Power7.
2160 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2161
2162 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2163 // fsel doesn't accept a condition register as input, so this would be slightly different.
2164 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2165
2166 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2167 const bool Matcher::require_postalloc_expand = true;
2168
2169 // Should the Matcher clone shifts on addressing modes, expecting them to
2170 // be subsumed into complex addressing expressions or compute them into
2171 // registers? True for Intel but false for most RISCs.
2172 const bool Matcher::clone_shift_expressions = false;
2173
2174 // Do we need to mask the count passed to shift instructions or does
2175 // the cpu only look at the lower 5/6 bits anyway?
2176 // Off, as masks are generated in expand rules where required.
2177 // Constant shift counts are handled in Ideal phase.
2178 const bool Matcher::need_masked_shift_count = false;
2179
2180 // This affects two different things:
2181 // - how Decode nodes are matched
2182 // - how ImplicitNullCheck opportunities are recognized
2183 // If true, the matcher will try to remove all Decodes and match them
2184 // (as operands) into nodes. NullChecks are not prepared to deal with
2185 // Decodes by final_graph_reshaping().
2186 // If false, final_graph_reshaping() forces the decode behind the Cmp
2187 // for a NullCheck. The matcher matches the Decode node into a register.
2188 // Implicit_null_check optimization moves the Decode along with the
2189 // memory operation back up before the NullCheck.
2190 bool Matcher::narrow_oop_use_complex_address() {
2191 // TODO: PPC port if (MatchDecodeNodes) return true;
2192 return false;
2193 }
2194
2195 bool Matcher::narrow_klass_use_complex_address() {
2196 NOT_LP64(ShouldNotCallThis());
2197 assert(UseCompressedClassPointers, "only for compressed klass code");
2198 // TODO: PPC port if (MatchDecodeNodes) return true;
2199 return false;
2200 }
2201
2202 // Is it better to copy float constants, or load them directly from memory?
2203 // Intel can load a float constant from a direct address, requiring no
2204 // extra registers. Most RISCs will have to materialize an address into a
2205 // register first, so they would do better to copy the constant from stack.
2206 const bool Matcher::rematerialize_float_constants = false;
2207
2208 // If CPU can load and store mis-aligned doubles directly then no fixup is
2209 // needed. Else we split the double into 2 integer pieces and move it
2210 // piece-by-piece. Only happens when passing doubles into C code as the
2211 // Java calling convention forces doubles to be aligned.
2212 const bool Matcher::misaligned_doubles_ok = true;
2213
2214 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2215 Unimplemented();
2216 }
2217
2218 // Advertise here if the CPU requires explicit rounding operations
2219 // to implement the UseStrictFP mode.
2220 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2221
2222 // Do floats take an entire double register or just half?
2223 //
2224 // A float occupies a ppc64 double register. For the allocator, a
2225 // ppc64 double register appears as a pair of float registers.
2226 bool Matcher::float_in_double() { return true; }
2227
2228 // Do ints take an entire long register or just half?
2229 // The relevant question is how the int is callee-saved:
2230 // the whole long is written but de-opt'ing will have to extract
2231 // the relevant 32 bits.
2232 const bool Matcher::int_in_long = true;
2233
2234 // Constants for c2c and c calling conventions.
2235
2236 const MachRegisterNumbers iarg_reg[8] = {
2237 R3_num, R4_num, R5_num, R6_num,
2238 R7_num, R8_num, R9_num, R10_num
2239 };
2240
2241 const MachRegisterNumbers farg_reg[13] = {
2242 F1_num, F2_num, F3_num, F4_num,
2243 F5_num, F6_num, F7_num, F8_num,
2244 F9_num, F10_num, F11_num, F12_num,
2245 F13_num
2246 };
2247
2248 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2249
2250 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2251
2252 // Return whether or not this register is ever used as an argument. This
2253 // function is used on startup to build the trampoline stubs in generateOptoStub.
2254 // Registers not mentioned will be killed by the VM call in the trampoline, and
2255 // arguments in those registers not be available to the callee.
2256 bool Matcher::can_be_java_arg(int reg) {
2257 // We return true for all registers contained in iarg_reg[] and
2258 // farg_reg[] and their virtual halves.
2259 // We must include the virtual halves in order to get STDs and LDs
2260 // instead of STWs and LWs in the trampoline stubs.
2261
2262 if ( reg == R3_num || reg == R3_H_num
2263 || reg == R4_num || reg == R4_H_num
2264 || reg == R5_num || reg == R5_H_num
2265 || reg == R6_num || reg == R6_H_num
2266 || reg == R7_num || reg == R7_H_num
2267 || reg == R8_num || reg == R8_H_num
2268 || reg == R9_num || reg == R9_H_num
2269 || reg == R10_num || reg == R10_H_num)
2270 return true;
2271
2272 if ( reg == F1_num || reg == F1_H_num
2273 || reg == F2_num || reg == F2_H_num
2274 || reg == F3_num || reg == F3_H_num
2275 || reg == F4_num || reg == F4_H_num
2276 || reg == F5_num || reg == F5_H_num
2277 || reg == F6_num || reg == F6_H_num
2278 || reg == F7_num || reg == F7_H_num
2279 || reg == F8_num || reg == F8_H_num
2280 || reg == F9_num || reg == F9_H_num
2281 || reg == F10_num || reg == F10_H_num
2282 || reg == F11_num || reg == F11_H_num
2283 || reg == F12_num || reg == F12_H_num
2284 || reg == F13_num || reg == F13_H_num)
2285 return true;
2286
2287 return false;
2288 }
2289
2290 bool Matcher::is_spillable_arg(int reg) {
2291 return can_be_java_arg(reg);
2292 }
2293
2294 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2295 return false;
2296 }
2297
2298 // Register for DIVI projection of divmodI.
2299 RegMask Matcher::divI_proj_mask() {
2300 ShouldNotReachHere();
2301 return RegMask();
2302 }
2303
2304 // Register for MODI projection of divmodI.
2305 RegMask Matcher::modI_proj_mask() {
2306 ShouldNotReachHere();
2307 return RegMask();
2308 }
2309
2310 // Register for DIVL projection of divmodL.
2311 RegMask Matcher::divL_proj_mask() {
2312 ShouldNotReachHere();
2313 return RegMask();
2314 }
2315
2316 // Register for MODL projection of divmodL.
2317 RegMask Matcher::modL_proj_mask() {
2318 ShouldNotReachHere();
2319 return RegMask();
2320 }
2321
2322 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2323 return RegMask();
2324 }
2325
2326 %}
2327
2328 //----------ENCODING BLOCK-----------------------------------------------------
2329 // This block specifies the encoding classes used by the compiler to output
2330 // byte streams. Encoding classes are parameterized macros used by
2331 // Machine Instruction Nodes in order to generate the bit encoding of the
2332 // instruction. Operands specify their base encoding interface with the
2333 // interface keyword. There are currently supported four interfaces,
2334 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2335 // operand to generate a function which returns its register number when
2336 // queried. CONST_INTER causes an operand to generate a function which
2337 // returns the value of the constant when queried. MEMORY_INTER causes an
2338 // operand to generate four functions which return the Base Register, the
2339 // Index Register, the Scale Value, and the Offset Value of the operand when
2340 // queried. COND_INTER causes an operand to generate six functions which
2341 // return the encoding code (ie - encoding bits for the instruction)
2342 // associated with each basic boolean condition for a conditional instruction.
2343 //
2344 // Instructions specify two basic values for encoding. Again, a function
2345 // is available to check if the constant displacement is an oop. They use the
2346 // ins_encode keyword to specify their encoding classes (which must be
2347 // a sequence of enc_class names, and their parameters, specified in
2348 // the encoding block), and they use the
2349 // opcode keyword to specify, in order, their primary, secondary, and
2350 // tertiary opcode. Only the opcode sections which a particular instruction
2351 // needs for encoding need to be specified.
2352 encode %{
2353 enc_class enc_unimplemented %{
2354 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2355 MacroAssembler _masm(&cbuf);
2356 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2357 %}
2358
2359 enc_class enc_untested %{
2360 #ifdef ASSERT
2361 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2362 MacroAssembler _masm(&cbuf);
2363 __ untested("Untested mach node encoding in AD file.");
2364 #else
2365 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2366 #endif
2367 %}
2368
2369 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2370 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2371 MacroAssembler _masm(&cbuf);
2372 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2373 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2374 %}
2375
2376 // Load acquire.
2377 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2378 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2379 MacroAssembler _masm(&cbuf);
2380 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2381 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2382 __ twi_0($dst$$Register);
2383 __ isync();
2384 %}
2385
2386 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2387 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2388
2389 MacroAssembler _masm(&cbuf);
2390 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2391 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2392 %}
2393
2394 // Load acquire.
2395 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2396 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2397
2398 MacroAssembler _masm(&cbuf);
2399 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2400 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2401 __ twi_0($dst$$Register);
2402 __ isync();
2403 %}
2404
2405 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2406 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2407
2408 MacroAssembler _masm(&cbuf);
2409 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2410 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2411 %}
2412
2413 // Load acquire.
2414 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2415 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2416
2417 MacroAssembler _masm(&cbuf);
2418 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2419 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2420 __ twi_0($dst$$Register);
2421 __ isync();
2422 %}
2423
2424 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2425 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2426 MacroAssembler _masm(&cbuf);
2427 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2428 // Operand 'ds' requires 4-alignment.
2429 assert((Idisp & 0x3) == 0, "unaligned offset");
2430 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2431 %}
2432
2433 // Load acquire.
2434 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2435 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2436 MacroAssembler _masm(&cbuf);
2437 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2438 // Operand 'ds' requires 4-alignment.
2439 assert((Idisp & 0x3) == 0, "unaligned offset");
2440 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2441 __ twi_0($dst$$Register);
2442 __ isync();
2443 %}
2444
2445 enc_class enc_lfd(RegF dst, memory mem) %{
2446 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2447 MacroAssembler _masm(&cbuf);
2448 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2449 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2450 %}
2451
2452 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2453 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2454
2455 MacroAssembler _masm(&cbuf);
2456 int toc_offset = 0;
2457
2458 if (!ra_->C->in_scratch_emit_size()) {
2459 address const_toc_addr;
2460 // Create a non-oop constant, no relocation needed.
2461 // If it is an IC, it has a virtual_call_Relocation.
2462 const_toc_addr = __ long_constant((jlong)$src$$constant);
2463
2464 // Get the constant's TOC offset.
2465 toc_offset = __ offset_to_method_toc(const_toc_addr);
2466
2467 // Keep the current instruction offset in mind.
2468 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2469 }
2470
2471 __ ld($dst$$Register, toc_offset, $toc$$Register);
2472 %}
2473
2474 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2475 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2476
2477 MacroAssembler _masm(&cbuf);
2478
2479 if (!ra_->C->in_scratch_emit_size()) {
2480 address const_toc_addr;
2481 // Create a non-oop constant, no relocation needed.
2482 // If it is an IC, it has a virtual_call_Relocation.
2483 const_toc_addr = __ long_constant((jlong)$src$$constant);
2484
2485 // Get the constant's TOC offset.
2486 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2487 // Store the toc offset of the constant.
2488 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2489
2490 // Also keep the current instruction offset in mind.
2491 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2492 }
2493
2494 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2495 %}
2496
2497 %} // encode
2498
2499 source %{
2500
2501 typedef struct {
2502 loadConL_hiNode *_large_hi;
2503 loadConL_loNode *_large_lo;
2504 loadConLNode *_small;
2505 MachNode *_last;
2506 } loadConLNodesTuple;
2507
2508 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2509 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2510 loadConLNodesTuple nodes;
2511
2512 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2513 if (large_constant_pool) {
2514 // Create new nodes.
2515 loadConL_hiNode *m1 = new loadConL_hiNode();
2516 loadConL_loNode *m2 = new loadConL_loNode();
2517
2518 // inputs for new nodes
2519 m1->add_req(NULL, toc);
2520 m2->add_req(NULL, m1);
2521
2522 // operands for new nodes
2523 m1->_opnds[0] = new iRegLdstOper(); // dst
2524 m1->_opnds[1] = immSrc; // src
2525 m1->_opnds[2] = new iRegPdstOper(); // toc
2526 m2->_opnds[0] = new iRegLdstOper(); // dst
2527 m2->_opnds[1] = immSrc; // src
2528 m2->_opnds[2] = new iRegLdstOper(); // base
2529
2530 // Initialize ins_attrib TOC fields.
2531 m1->_const_toc_offset = -1;
2532 m2->_const_toc_offset_hi_node = m1;
2533
2534 // Initialize ins_attrib instruction offset.
2535 m1->_cbuf_insts_offset = -1;
2536
2537 // register allocation for new nodes
2538 ra_->set_pair(m1->_idx, reg_second, reg_first);
2539 ra_->set_pair(m2->_idx, reg_second, reg_first);
2540
2541 // Create result.
2542 nodes._large_hi = m1;
2543 nodes._large_lo = m2;
2544 nodes._small = NULL;
2545 nodes._last = nodes._large_lo;
2546 assert(m2->bottom_type()->isa_long(), "must be long");
2547 } else {
2548 loadConLNode *m2 = new loadConLNode();
2549
2550 // inputs for new nodes
2551 m2->add_req(NULL, toc);
2552
2553 // operands for new nodes
2554 m2->_opnds[0] = new iRegLdstOper(); // dst
2555 m2->_opnds[1] = immSrc; // src
2556 m2->_opnds[2] = new iRegPdstOper(); // toc
2557
2558 // Initialize ins_attrib instruction offset.
2559 m2->_cbuf_insts_offset = -1;
2560
2561 // register allocation for new nodes
2562 ra_->set_pair(m2->_idx, reg_second, reg_first);
2563
2564 // Create result.
2565 nodes._large_hi = NULL;
2566 nodes._large_lo = NULL;
2567 nodes._small = m2;
2568 nodes._last = nodes._small;
2569 assert(m2->bottom_type()->isa_long(), "must be long");
2570 }
2571
2572 return nodes;
2573 }
2574
2575 %} // source
2576
2577 encode %{
2578 // Postalloc expand emitter for loading a long constant from the method's TOC.
2579 // Enc_class needed as consttanttablebase is not supported by postalloc
2580 // expand.
2581 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2582 // Create new nodes.
2583 loadConLNodesTuple loadConLNodes =
2584 loadConLNodesTuple_create(ra_, n_toc, op_src,
2585 ra_->get_reg_second(this), ra_->get_reg_first(this));
2586
2587 // Push new nodes.
2588 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2589 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2590
2591 // some asserts
2592 assert(nodes->length() >= 1, "must have created at least 1 node");
2593 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2594 %}
2595
2596 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2597 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2598
2599 MacroAssembler _masm(&cbuf);
2600 int toc_offset = 0;
2601
2602 if (!ra_->C->in_scratch_emit_size()) {
2603 intptr_t val = $src$$constant;
2604 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2605 address const_toc_addr;
2606 if (constant_reloc == relocInfo::oop_type) {
2607 // Create an oop constant and a corresponding relocation.
2608 AddressLiteral a = __ allocate_oop_address((jobject)val);
2609 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2610 __ relocate(a.rspec());
2611 } else if (constant_reloc == relocInfo::metadata_type) {
2612 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2613 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2614 __ relocate(a.rspec());
2615 } else {
2616 // Create a non-oop constant, no relocation needed.
2617 const_toc_addr = __ long_constant((jlong)$src$$constant);
2618 }
2619
2620 // Get the constant's TOC offset.
2621 toc_offset = __ offset_to_method_toc(const_toc_addr);
2622 }
2623
2624 __ ld($dst$$Register, toc_offset, $toc$$Register);
2625 %}
2626
2627 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2628 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2629
2630 MacroAssembler _masm(&cbuf);
2631 if (!ra_->C->in_scratch_emit_size()) {
2632 intptr_t val = $src$$constant;
2633 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2634 address const_toc_addr;
2635 if (constant_reloc == relocInfo::oop_type) {
2636 // Create an oop constant and a corresponding relocation.
2637 AddressLiteral a = __ allocate_oop_address((jobject)val);
2638 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2639 __ relocate(a.rspec());
2640 } else if (constant_reloc == relocInfo::metadata_type) {
2641 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2642 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2643 __ relocate(a.rspec());
2644 } else { // non-oop pointers, e.g. card mark base, heap top
2645 // Create a non-oop constant, no relocation needed.
2646 const_toc_addr = __ long_constant((jlong)$src$$constant);
2647 }
2648
2649 // Get the constant's TOC offset.
2650 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2651 // Store the toc offset of the constant.
2652 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2653 }
2654
2655 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2656 %}
2657
2658 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2659 // Enc_class needed as consttanttablebase is not supported by postalloc
2660 // expand.
2661 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2662 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2663 if (large_constant_pool) {
2664 // Create new nodes.
2665 loadConP_hiNode *m1 = new loadConP_hiNode();
2666 loadConP_loNode *m2 = new loadConP_loNode();
2667
2668 // inputs for new nodes
2669 m1->add_req(NULL, n_toc);
2670 m2->add_req(NULL, m1);
2671
2672 // operands for new nodes
2673 m1->_opnds[0] = new iRegPdstOper(); // dst
2674 m1->_opnds[1] = op_src; // src
2675 m1->_opnds[2] = new iRegPdstOper(); // toc
2676 m2->_opnds[0] = new iRegPdstOper(); // dst
2677 m2->_opnds[1] = op_src; // src
2678 m2->_opnds[2] = new iRegLdstOper(); // base
2679
2680 // Initialize ins_attrib TOC fields.
2681 m1->_const_toc_offset = -1;
2682 m2->_const_toc_offset_hi_node = m1;
2683
2684 // Register allocation for new nodes.
2685 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2686 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2687
2688 nodes->push(m1);
2689 nodes->push(m2);
2690 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2691 } else {
2692 loadConPNode *m2 = new loadConPNode();
2693
2694 // inputs for new nodes
2695 m2->add_req(NULL, n_toc);
2696
2697 // operands for new nodes
2698 m2->_opnds[0] = new iRegPdstOper(); // dst
2699 m2->_opnds[1] = op_src; // src
2700 m2->_opnds[2] = new iRegPdstOper(); // toc
2701
2702 // Register allocation for new nodes.
2703 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2704
2705 nodes->push(m2);
2706 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2707 }
2708 %}
2709
2710 // Enc_class needed as consttanttablebase is not supported by postalloc
2711 // expand.
2712 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2713 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2714
2715 MachNode *m2;
2716 if (large_constant_pool) {
2717 m2 = new loadConFCompNode();
2718 } else {
2719 m2 = new loadConFNode();
2720 }
2721 // inputs for new nodes
2722 m2->add_req(NULL, n_toc);
2723
2724 // operands for new nodes
2725 m2->_opnds[0] = op_dst;
2726 m2->_opnds[1] = op_src;
2727 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2728
2729 // register allocation for new nodes
2730 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2731 nodes->push(m2);
2732 %}
2733
2734 // Enc_class needed as consttanttablebase is not supported by postalloc
2735 // expand.
2736 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2737 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2738
2739 MachNode *m2;
2740 if (large_constant_pool) {
2741 m2 = new loadConDCompNode();
2742 } else {
2743 m2 = new loadConDNode();
2744 }
2745 // inputs for new nodes
2746 m2->add_req(NULL, n_toc);
2747
2748 // operands for new nodes
2749 m2->_opnds[0] = op_dst;
2750 m2->_opnds[1] = op_src;
2751 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2752
2753 // register allocation for new nodes
2754 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2755 nodes->push(m2);
2756 %}
2757
2758 enc_class enc_stw(iRegIsrc src, memory mem) %{
2759 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2760 MacroAssembler _masm(&cbuf);
2761 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2762 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2763 %}
2764
2765 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2766 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2767 MacroAssembler _masm(&cbuf);
2768 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2769 // Operand 'ds' requires 4-alignment.
2770 assert((Idisp & 0x3) == 0, "unaligned offset");
2771 __ std($src$$Register, Idisp, $mem$$base$$Register);
2772 %}
2773
2774 enc_class enc_stfs(RegF src, memory mem) %{
2775 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2776 MacroAssembler _masm(&cbuf);
2777 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2778 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2779 %}
2780
2781 enc_class enc_stfd(RegF src, memory mem) %{
2782 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2783 MacroAssembler _masm(&cbuf);
2784 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2785 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2786 %}
2787
2788 // Use release_store for card-marking to ensure that previous
2789 // oop-stores are visible before the card-mark change.
2790 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2791 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2792 // FIXME: Implement this as a cmove and use a fixed condition code
2793 // register which is written on every transition to compiled code,
2794 // e.g. in call-stub and when returning from runtime stubs.
2795 //
2796 // Proposed code sequence for the cmove implementation:
2797 //
2798 // Label skip_release;
2799 // __ beq(CCRfixed, skip_release);
2800 // __ release();
2801 // __ bind(skip_release);
2802 // __ stb(card mark);
2803
2804 MacroAssembler _masm(&cbuf);
2805 Label skip_storestore;
2806
2807 #if 0 // TODO: PPC port
2808 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2809 // StoreStore barrier conditionally.
2810 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2811 __ cmpwi($crx$$CondRegister, R0, 0);
2812 __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2813 #endif
2814 __ li(R0, 0);
2815 __ membar(Assembler::StoreStore);
2816 #if 0 // TODO: PPC port
2817 __ bind(skip_storestore);
2818 #endif
2819
2820 // Do the store.
2821 if ($mem$$index == 0) {
2822 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2823 } else {
2824 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2825 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2826 }
2827 %}
2828
2829 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2830
2831 if (VM_Version::has_isel()) {
2832 // use isel instruction with Power 7
2833 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2834 encodeP_subNode *n_sub_base = new encodeP_subNode();
2835 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2836 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2837
2838 n_compare->add_req(n_region, n_src);
2839 n_compare->_opnds[0] = op_crx;
2840 n_compare->_opnds[1] = op_src;
2841 n_compare->_opnds[2] = new immL16Oper(0);
2842
2843 n_sub_base->add_req(n_region, n_src);
2844 n_sub_base->_opnds[0] = op_dst;
2845 n_sub_base->_opnds[1] = op_src;
2846 n_sub_base->_bottom_type = _bottom_type;
2847
2848 n_shift->add_req(n_region, n_sub_base);
2849 n_shift->_opnds[0] = op_dst;
2850 n_shift->_opnds[1] = op_dst;
2851 n_shift->_bottom_type = _bottom_type;
2852
2853 n_cond_set->add_req(n_region, n_compare, n_shift);
2854 n_cond_set->_opnds[0] = op_dst;
2855 n_cond_set->_opnds[1] = op_crx;
2856 n_cond_set->_opnds[2] = op_dst;
2857 n_cond_set->_bottom_type = _bottom_type;
2858
2859 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2860 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2861 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2862 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2863
2864 nodes->push(n_compare);
2865 nodes->push(n_sub_base);
2866 nodes->push(n_shift);
2867 nodes->push(n_cond_set);
2868
2869 } else {
2870 // before Power 7
2871 moveRegNode *n_move = new moveRegNode();
2872 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2873 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2874 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2875
2876 n_move->add_req(n_region, n_src);
2877 n_move->_opnds[0] = op_dst;
2878 n_move->_opnds[1] = op_src;
2879 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2880
2881 n_compare->add_req(n_region, n_src);
2882 n_compare->add_prec(n_move);
2883
2884 n_compare->_opnds[0] = op_crx;
2885 n_compare->_opnds[1] = op_src;
2886 n_compare->_opnds[2] = new immL16Oper(0);
2887
2888 n_sub_base->add_req(n_region, n_compare, n_src);
2889 n_sub_base->_opnds[0] = op_dst;
2890 n_sub_base->_opnds[1] = op_crx;
2891 n_sub_base->_opnds[2] = op_src;
2892 n_sub_base->_bottom_type = _bottom_type;
2893
2894 n_shift->add_req(n_region, n_sub_base);
2895 n_shift->_opnds[0] = op_dst;
2896 n_shift->_opnds[1] = op_dst;
2897 n_shift->_bottom_type = _bottom_type;
2898
2899 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2900 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2901 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2902 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2903
2904 nodes->push(n_move);
2905 nodes->push(n_compare);
2906 nodes->push(n_sub_base);
2907 nodes->push(n_shift);
2908 }
2909
2910 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2911 %}
2912
2913 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2914
2915 encodeP_subNode *n1 = new encodeP_subNode();
2916 n1->add_req(n_region, n_src);
2917 n1->_opnds[0] = op_dst;
2918 n1->_opnds[1] = op_src;
2919 n1->_bottom_type = _bottom_type;
2920
2921 encodeP_shiftNode *n2 = new encodeP_shiftNode();
2922 n2->add_req(n_region, n1);
2923 n2->_opnds[0] = op_dst;
2924 n2->_opnds[1] = op_dst;
2925 n2->_bottom_type = _bottom_type;
2926 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2927 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2928
2929 nodes->push(n1);
2930 nodes->push(n2);
2931 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2932 %}
2933
2934 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2935 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
2936 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
2937
2938 n_compare->add_req(n_region, n_src);
2939 n_compare->_opnds[0] = op_crx;
2940 n_compare->_opnds[1] = op_src;
2941 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2942
2943 n_shift->add_req(n_region, n_src);
2944 n_shift->_opnds[0] = op_dst;
2945 n_shift->_opnds[1] = op_src;
2946 n_shift->_bottom_type = _bottom_type;
2947
2948 if (VM_Version::has_isel()) {
2949 // use isel instruction with Power 7
2950
2951 decodeN_addNode *n_add_base = new decodeN_addNode();
2952 n_add_base->add_req(n_region, n_shift);
2953 n_add_base->_opnds[0] = op_dst;
2954 n_add_base->_opnds[1] = op_dst;
2955 n_add_base->_bottom_type = _bottom_type;
2956
2957 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2958 n_cond_set->add_req(n_region, n_compare, n_add_base);
2959 n_cond_set->_opnds[0] = op_dst;
2960 n_cond_set->_opnds[1] = op_crx;
2961 n_cond_set->_opnds[2] = op_dst;
2962 n_cond_set->_bottom_type = _bottom_type;
2963
2964 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2965 ra_->set_oop(n_cond_set, true);
2966
2967 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2968 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2969 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2970 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2971
2972 nodes->push(n_compare);
2973 nodes->push(n_shift);
2974 nodes->push(n_add_base);
2975 nodes->push(n_cond_set);
2976
2977 } else {
2978 // before Power 7
2979 cond_add_baseNode *n_add_base = new cond_add_baseNode();
2980
2981 n_add_base->add_req(n_region, n_compare, n_shift);
2982 n_add_base->_opnds[0] = op_dst;
2983 n_add_base->_opnds[1] = op_crx;
2984 n_add_base->_opnds[2] = op_dst;
2985 n_add_base->_bottom_type = _bottom_type;
2986
2987 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2988 ra_->set_oop(n_add_base, true);
2989
2990 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2991 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2992 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2993
2994 nodes->push(n_compare);
2995 nodes->push(n_shift);
2996 nodes->push(n_add_base);
2997 }
2998 %}
2999
3000 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3001 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3002 n1->add_req(n_region, n_src);
3003 n1->_opnds[0] = op_dst;
3004 n1->_opnds[1] = op_src;
3005 n1->_bottom_type = _bottom_type;
3006
3007 decodeN_addNode *n2 = new decodeN_addNode();
3008 n2->add_req(n_region, n1);
3009 n2->_opnds[0] = op_dst;
3010 n2->_opnds[1] = op_dst;
3011 n2->_bottom_type = _bottom_type;
3012 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3013 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3014
3015 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3016 ra_->set_oop(n2, true);
3017
3018 nodes->push(n1);
3019 nodes->push(n2);
3020 %}
3021
3022 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3023 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3024
3025 MacroAssembler _masm(&cbuf);
3026 int cc = $cmp$$cmpcode;
3027 int flags_reg = $crx$$reg;
3028 Label done;
3029 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3030 // Branch if not (cmp crx).
3031 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3032 __ mr($dst$$Register, $src$$Register);
3033 // TODO PPC port __ endgroup_if_needed(_size == 12);
3034 __ bind(done);
3035 %}
3036
3037 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3038 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3039
3040 MacroAssembler _masm(&cbuf);
3041 Label done;
3042 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3043 // Branch if not (cmp crx).
3044 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3045 __ li($dst$$Register, $src$$constant);
3046 // TODO PPC port __ endgroup_if_needed(_size == 12);
3047 __ bind(done);
3048 %}
3049
3050 // New atomics.
3051 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3052 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3053
3054 MacroAssembler _masm(&cbuf);
3055 Register Rtmp = R0;
3056 Register Rres = $res$$Register;
3057 Register Rsrc = $src$$Register;
3058 Register Rptr = $mem_ptr$$Register;
3059 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3060 Register Rold = RegCollision ? Rtmp : Rres;
3061
3062 Label Lretry;
3063 __ bind(Lretry);
3064 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3065 __ add(Rtmp, Rsrc, Rold);
3066 __ stwcx_(Rtmp, Rptr);
3067 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3068 __ bne_predict_not_taken(CCR0, Lretry);
3069 } else {
3070 __ bne( CCR0, Lretry);
3071 }
3072 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3073 __ fence();
3074 %}
3075
3076 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3077 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3078
3079 MacroAssembler _masm(&cbuf);
3080 Register Rtmp = R0;
3081 Register Rres = $res$$Register;
3082 Register Rsrc = $src$$Register;
3083 Register Rptr = $mem_ptr$$Register;
3084 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3085 Register Rold = RegCollision ? Rtmp : Rres;
3086
3087 Label Lretry;
3088 __ bind(Lretry);
3089 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3090 __ add(Rtmp, Rsrc, Rold);
3091 __ stdcx_(Rtmp, Rptr);
3092 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3093 __ bne_predict_not_taken(CCR0, Lretry);
3094 } else {
3095 __ bne( CCR0, Lretry);
3096 }
3097 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3098 __ fence();
3099 %}
3100
3101 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3102 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3103
3104 MacroAssembler _masm(&cbuf);
3105 Register Rtmp = R0;
3106 Register Rres = $res$$Register;
3107 Register Rsrc = $src$$Register;
3108 Register Rptr = $mem_ptr$$Register;
3109 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3110 Register Rold = RegCollision ? Rtmp : Rres;
3111
3112 Label Lretry;
3113 __ bind(Lretry);
3114 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3115 __ stwcx_(Rsrc, Rptr);
3116 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3117 __ bne_predict_not_taken(CCR0, Lretry);
3118 } else {
3119 __ bne( CCR0, Lretry);
3120 }
3121 if (RegCollision) __ mr(Rres, Rtmp);
3122 __ fence();
3123 %}
3124
3125 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3126 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3127
3128 MacroAssembler _masm(&cbuf);
3129 Register Rtmp = R0;
3130 Register Rres = $res$$Register;
3131 Register Rsrc = $src$$Register;
3132 Register Rptr = $mem_ptr$$Register;
3133 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3134 Register Rold = RegCollision ? Rtmp : Rres;
3135
3136 Label Lretry;
3137 __ bind(Lretry);
3138 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3139 __ stdcx_(Rsrc, Rptr);
3140 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3141 __ bne_predict_not_taken(CCR0, Lretry);
3142 } else {
3143 __ bne( CCR0, Lretry);
3144 }
3145 if (RegCollision) __ mr(Rres, Rtmp);
3146 __ fence();
3147 %}
3148
3149 // This enc_class is needed so that scheduler gets proper
3150 // input mapping for latency computation.
3151 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3152 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3153 MacroAssembler _masm(&cbuf);
3154 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3155 %}
3156
3157 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3158 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3159
3160 MacroAssembler _masm(&cbuf);
3161
3162 Label done;
3163 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3164 __ li($dst$$Register, $zero$$constant);
3165 __ beq($crx$$CondRegister, done);
3166 __ li($dst$$Register, $notzero$$constant);
3167 __ bind(done);
3168 %}
3169
3170 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3171 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3172
3173 MacroAssembler _masm(&cbuf);
3174
3175 Label done;
3176 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3177 __ li($dst$$Register, $zero$$constant);
3178 __ beq($crx$$CondRegister, done);
3179 __ li($dst$$Register, $notzero$$constant);
3180 __ bind(done);
3181 %}
3182
3183 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3184 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3185
3186 MacroAssembler _masm(&cbuf);
3187 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3188 Label done;
3189 __ bso($crx$$CondRegister, done);
3190 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3191 // TODO PPC port __ endgroup_if_needed(_size == 12);
3192 __ bind(done);
3193 %}
3194
3195 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3196 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3197
3198 MacroAssembler _masm(&cbuf);
3199 Label d; // dummy
3200 __ bind(d);
3201 Label* p = ($lbl$$label);
3202 // `p' is `NULL' when this encoding class is used only to
3203 // determine the size of the encoded instruction.
3204 Label& l = (NULL == p)? d : *(p);
3205 int cc = $cmp$$cmpcode;
3206 int flags_reg = $crx$$reg;
3207 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3208 int bhint = Assembler::bhintNoHint;
3209
3210 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3211 if (_prob <= PROB_NEVER) {
3212 bhint = Assembler::bhintIsNotTaken;
3213 } else if (_prob >= PROB_ALWAYS) {
3214 bhint = Assembler::bhintIsTaken;
3215 }
3216 }
3217
3218 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3219 cc_to_biint(cc, flags_reg),
3220 l);
3221 %}
3222
3223 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3224 // The scheduler doesn't know about branch shortening, so we set the opcode
3225 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3226 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3227
3228 MacroAssembler _masm(&cbuf);
3229 Label d; // dummy
3230 __ bind(d);
3231 Label* p = ($lbl$$label);
3232 // `p' is `NULL' when this encoding class is used only to
3233 // determine the size of the encoded instruction.
3234 Label& l = (NULL == p)? d : *(p);
3235 int cc = $cmp$$cmpcode;
3236 int flags_reg = $crx$$reg;
3237 int bhint = Assembler::bhintNoHint;
3238
3239 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3240 if (_prob <= PROB_NEVER) {
3241 bhint = Assembler::bhintIsNotTaken;
3242 } else if (_prob >= PROB_ALWAYS) {
3243 bhint = Assembler::bhintIsTaken;
3244 }
3245 }
3246
3247 // Tell the conditional far branch to optimize itself when being relocated.
3248 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3249 cc_to_biint(cc, flags_reg),
3250 l,
3251 MacroAssembler::bc_far_optimize_on_relocate);
3252 %}
3253
3254 // Branch used with Power6 scheduling (can be shortened without changing the node).
3255 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3256 // The scheduler doesn't know about branch shortening, so we set the opcode
3257 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3258 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3259
3260 MacroAssembler _masm(&cbuf);
3261 Label d; // dummy
3262 __ bind(d);
3263 Label* p = ($lbl$$label);
3264 // `p' is `NULL' when this encoding class is used only to
3265 // determine the size of the encoded instruction.
3266 Label& l = (NULL == p)? d : *(p);
3267 int cc = $cmp$$cmpcode;
3268 int flags_reg = $crx$$reg;
3269 int bhint = Assembler::bhintNoHint;
3270
3271 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3272 if (_prob <= PROB_NEVER) {
3273 bhint = Assembler::bhintIsNotTaken;
3274 } else if (_prob >= PROB_ALWAYS) {
3275 bhint = Assembler::bhintIsTaken;
3276 }
3277 }
3278
3279 #if 0 // TODO: PPC port
3280 if (_size == 8) {
3281 // Tell the conditional far branch to optimize itself when being relocated.
3282 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3283 cc_to_biint(cc, flags_reg),
3284 l,
3285 MacroAssembler::bc_far_optimize_on_relocate);
3286 } else {
3287 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3288 cc_to_biint(cc, flags_reg),
3289 l);
3290 }
3291 #endif
3292 Unimplemented();
3293 %}
3294
3295 // Postalloc expand emitter for loading a replicatef float constant from
3296 // the method's TOC.
3297 // Enc_class needed as consttanttablebase is not supported by postalloc
3298 // expand.
3299 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3300 // Create new nodes.
3301
3302 // Make an operand with the bit pattern to load as float.
3303 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3304
3305 loadConLNodesTuple loadConLNodes =
3306 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3307 ra_->get_reg_second(this), ra_->get_reg_first(this));
3308
3309 // Push new nodes.
3310 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3311 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3312
3313 assert(nodes->length() >= 1, "must have created at least 1 node");
3314 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3315 %}
3316
3317 // This enc_class is needed so that scheduler gets proper
3318 // input mapping for latency computation.
3319 enc_class enc_poll(immI dst, iRegLdst poll) %{
3320 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3321 // Fake operand dst needed for PPC scheduler.
3322 assert($dst$$constant == 0x0, "dst must be 0x0");
3323
3324 MacroAssembler _masm(&cbuf);
3325 // Mark the code position where the load from the safepoint
3326 // polling page was emitted as relocInfo::poll_type.
3327 __ relocate(relocInfo::poll_type);
3328 __ load_from_polling_page($poll$$Register);
3329 %}
3330
3331 // A Java static call or a runtime call.
3332 //
3333 // Branch-and-link relative to a trampoline.
3334 // The trampoline loads the target address and does a long branch to there.
3335 // In case we call java, the trampoline branches to a interpreter_stub
3336 // which loads the inline cache and the real call target from the constant pool.
3337 //
3338 // This basically looks like this:
3339 //
3340 // >>>> consts -+ -+
3341 // | |- offset1
3342 // [call target1] | <-+
3343 // [IC cache] |- offset2
3344 // [call target2] <--+
3345 //
3346 // <<<< consts
3347 // >>>> insts
3348 //
3349 // bl offset16 -+ -+ ??? // How many bits available?
3350 // | |
3351 // <<<< insts | |
3352 // >>>> stubs | |
3353 // | |- trampoline_stub_Reloc
3354 // trampoline stub: | <-+
3355 // r2 = toc |
3356 // r2 = [r2 + offset1] | // Load call target1 from const section
3357 // mtctr r2 |
3358 // bctr |- static_stub_Reloc
3359 // comp_to_interp_stub: <---+
3360 // r1 = toc
3361 // ICreg = [r1 + IC_offset] // Load IC from const section
3362 // r1 = [r1 + offset2] // Load call target2 from const section
3363 // mtctr r1
3364 // bctr
3365 //
3366 // <<<< stubs
3367 //
3368 // The call instruction in the code either
3369 // - Branches directly to a compiled method if the offset is encodable in instruction.
3370 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3371 // - Branches to the compiled_to_interp stub if the target is interpreted.
3372 //
3373 // Further there are three relocations from the loads to the constants in
3374 // the constant section.
3375 //
3376 // Usage of r1 and r2 in the stubs allows to distinguish them.
3377 enc_class enc_java_static_call(method meth) %{
3378 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3379
3380 MacroAssembler _masm(&cbuf);
3381 address entry_point = (address)$meth$$method;
3382
3383 if (!_method) {
3384 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3385 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3386 } else {
3387 // Remember the offset not the address.
3388 const int start_offset = __ offset();
3389 // The trampoline stub.
3390 if (!Compile::current()->in_scratch_emit_size()) {
3391 // No entry point given, use the current pc.
3392 // Make sure branch fits into
3393 if (entry_point == 0) entry_point = __ pc();
3394
3395 // Put the entry point as a constant into the constant pool.
3396 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3397 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3398
3399 // Emit the trampoline stub which will be related to the branch-and-link below.
3400 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3401 if (Compile::current()->env()->failing()) { return; } // Code cache may be full.
3402 __ relocate(_optimized_virtual ?
3403 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3404 }
3405
3406 // The real call.
3407 // Note: At this point we do not have the address of the trampoline
3408 // stub, and the entry point might be too far away for bl, so __ pc()
3409 // serves as dummy and the bl will be patched later.
3410 cbuf.set_insts_mark();
3411 __ bl(__ pc()); // Emits a relocation.
3412
3413 // The stub for call to interpreter.
3414 CompiledStaticCall::emit_to_interp_stub(cbuf);
3415 }
3416 %}
3417
3418 // Emit a method handle call.
3419 //
3420 // Method handle calls from compiled to compiled are going thru a
3421 // c2i -> i2c adapter, extending the frame for their arguments. The
3422 // caller however, returns directly to the compiled callee, that has
3423 // to cope with the extended frame. We restore the original frame by
3424 // loading the callers sp and adding the calculated framesize.
3425 enc_class enc_java_handle_call(method meth) %{
3426 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3427
3428 MacroAssembler _masm(&cbuf);
3429 address entry_point = (address)$meth$$method;
3430
3431 // Remember the offset not the address.
3432 const int start_offset = __ offset();
3433 // The trampoline stub.
3434 if (!ra_->C->in_scratch_emit_size()) {
3435 // No entry point given, use the current pc.
3436 // Make sure branch fits into
3437 if (entry_point == 0) entry_point = __ pc();
3438
3439 // Put the entry point as a constant into the constant pool.
3440 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3441 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3442
3443 // Emit the trampoline stub which will be related to the branch-and-link below.
3444 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3445 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3446 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3447 __ relocate(relocInfo::opt_virtual_call_type);
3448 }
3449
3450 // The real call.
3451 // Note: At this point we do not have the address of the trampoline
3452 // stub, and the entry point might be too far away for bl, so __ pc()
3453 // serves as dummy and the bl will be patched later.
3454 cbuf.set_insts_mark();
3455 __ bl(__ pc()); // Emits a relocation.
3456
3457 assert(_method, "execute next statement conditionally");
3458 // The stub for call to interpreter.
3459 CompiledStaticCall::emit_to_interp_stub(cbuf);
3460
3461 // Restore original sp.
3462 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3463 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3464 unsigned int bytes = (unsigned int)framesize;
3465 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3466 if (Assembler::is_simm(-offset, 16)) {
3467 __ addi(R1_SP, R11_scratch1, -offset);
3468 } else {
3469 __ load_const_optimized(R12_scratch2, -offset);
3470 __ add(R1_SP, R11_scratch1, R12_scratch2);
3471 }
3472 #ifdef ASSERT
3473 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3474 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3475 __ asm_assert_eq("backlink changed", 0x8000);
3476 #endif
3477 // If fails should store backlink before unextending.
3478
3479 if (ra_->C->env()->failing()) {
3480 return;
3481 }
3482 %}
3483
3484 // Second node of expanded dynamic call - the call.
3485 enc_class enc_java_dynamic_call_sched(method meth) %{
3486 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3487
3488 MacroAssembler _masm(&cbuf);
3489
3490 if (!ra_->C->in_scratch_emit_size()) {
3491 // Create a call trampoline stub for the given method.
3492 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3493 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3494 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3495 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3496 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3497
3498 // Build relocation at call site with ic position as data.
3499 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3500 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3501 "must have one, but can't have both");
3502 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3503 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3504 "must contain instruction offset");
3505 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3506 ? _load_ic_hi_node->_cbuf_insts_offset
3507 : _load_ic_node->_cbuf_insts_offset;
3508 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3509 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3510 "should be load from TOC");
3511
3512 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3513 }
3514
3515 // At this point I do not have the address of the trampoline stub,
3516 // and the entry point might be too far away for bl. Pc() serves
3517 // as dummy and bl will be patched later.
3518 __ bl((address) __ pc());
3519 %}
3520
3521 // postalloc expand emitter for virtual calls.
3522 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3523
3524 // Create the nodes for loading the IC from the TOC.
3525 loadConLNodesTuple loadConLNodes_IC =
3526 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3527 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3528
3529 // Create the call node.
3530 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3531 call->_method_handle_invoke = _method_handle_invoke;
3532 call->_vtable_index = _vtable_index;
3533 call->_method = _method;
3534 call->_bci = _bci;
3535 call->_optimized_virtual = _optimized_virtual;
3536 call->_tf = _tf;
3537 call->_entry_point = _entry_point;
3538 call->_cnt = _cnt;
3539 call->_argsize = _argsize;
3540 call->_oop_map = _oop_map;
3541 call->_jvms = _jvms;
3542 call->_jvmadj = _jvmadj;
3543 call->_in_rms = _in_rms;
3544 call->_nesting = _nesting;
3545
3546 // New call needs all inputs of old call.
3547 // Req...
3548 for (uint i = 0; i < req(); ++i) {
3549 // The expanded node does not need toc any more.
3550 // Add the inline cache constant here instead. This expresses the
3551 // register of the inline cache must be live at the call.
3552 // Else we would have to adapt JVMState by -1.
3553 if (i == mach_constant_base_node_input()) {
3554 call->add_req(loadConLNodes_IC._last);
3555 } else {
3556 call->add_req(in(i));
3557 }
3558 }
3559 // ...as well as prec
3560 for (uint i = req(); i < len(); ++i) {
3561 call->add_prec(in(i));
3562 }
3563
3564 // Remember nodes loading the inline cache into r19.
3565 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3566 call->_load_ic_node = loadConLNodes_IC._small;
3567
3568 // Operands for new nodes.
3569 call->_opnds[0] = _opnds[0];
3570 call->_opnds[1] = _opnds[1];
3571
3572 // Only the inline cache is associated with a register.
3573 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3574
3575 // Push new nodes.
3576 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3577 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3578 nodes->push(call);
3579 %}
3580
3581 // Compound version of call dynamic
3582 // Toc is only passed so that it can be used in ins_encode statement.
3583 // In the code we have to use $constanttablebase.
3584 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3585 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3586 MacroAssembler _masm(&cbuf);
3587 int start_offset = __ offset();
3588
3589 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3590 #if 0
3591 int vtable_index = this->_vtable_index;
3592 if (_vtable_index < 0) {
3593 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3594 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3595 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3596
3597 // Virtual call relocation will point to ic load.
3598 address virtual_call_meta_addr = __ pc();
3599 // Load a clear inline cache.
3600 AddressLiteral empty_ic((address) Universe::non_oop_word());
3601 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3602 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3603 // to determine who we intended to call.
3604 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3605 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3606 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3607 "Fix constant in ret_addr_offset()");
3608 } else {
3609 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3610 // Go thru the vtable. Get receiver klass. Receiver already
3611 // checked for non-null. If we'll go thru a C2I adapter, the
3612 // interpreter expects method in R19_method.
3613
3614 __ load_klass(R11_scratch1, R3);
3615
3616 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3617 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3618 __ li(R19_method, v_off);
3619 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3620 // NOTE: for vtable dispatches, the vtable entry will never be
3621 // null. However it may very well end up in handle_wrong_method
3622 // if the method is abstract for the particular class.
3623 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3624 // Call target. Either compiled code or C2I adapter.
3625 __ mtctr(R11_scratch1);
3626 __ bctrl();
3627 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3628 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3629 }
3630 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3631 "Fix constant in ret_addr_offset()");
3632 }
3633 #endif
3634 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3635 %}
3636
3637 // a runtime call
3638 enc_class enc_java_to_runtime_call (method meth) %{
3639 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3640
3641 MacroAssembler _masm(&cbuf);
3642 const address start_pc = __ pc();
3643
3644 #if defined(ABI_ELFv2)
3645 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3646 __ call_c(entry, relocInfo::runtime_call_type);
3647 #else
3648 // The function we're going to call.
3649 FunctionDescriptor fdtemp;
3650 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3651
3652 Register Rtoc = R12_scratch2;
3653 // Calculate the method's TOC.
3654 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3655 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3656 // pool entries; call_c_using_toc will optimize the call.
3657 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3658 #endif
3659
3660 // Check the ret_addr_offset.
3661 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3662 "Fix constant in ret_addr_offset()");
3663 %}
3664
3665 // Move to ctr for leaf call.
3666 // This enc_class is needed so that scheduler gets proper
3667 // input mapping for latency computation.
3668 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3669 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3670 MacroAssembler _masm(&cbuf);
3671 __ mtctr($src$$Register);
3672 %}
3673
3674 // Postalloc expand emitter for runtime leaf calls.
3675 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3676 loadConLNodesTuple loadConLNodes_Entry;
3677 #if defined(ABI_ELFv2)
3678 jlong entry_address = (jlong) this->entry_point();
3679 assert(entry_address, "need address here");
3680 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3681 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3682 #else
3683 // Get the struct that describes the function we are about to call.
3684 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3685 assert(fd, "need fd here");
3686 jlong entry_address = (jlong) fd->entry();
3687 // new nodes
3688 loadConLNodesTuple loadConLNodes_Env;
3689 loadConLNodesTuple loadConLNodes_Toc;
3690
3691 // Create nodes and operands for loading the entry point.
3692 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3693 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3694
3695
3696 // Create nodes and operands for loading the env pointer.
3697 if (fd->env() != NULL) {
3698 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3699 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3700 } else {
3701 loadConLNodes_Env._large_hi = NULL;
3702 loadConLNodes_Env._large_lo = NULL;
3703 loadConLNodes_Env._small = NULL;
3704 loadConLNodes_Env._last = new loadConL16Node();
3705 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3706 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3707 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3708 }
3709
3710 // Create nodes and operands for loading the Toc point.
3711 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3712 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3713 #endif // ABI_ELFv2
3714 // mtctr node
3715 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3716
3717 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3718 mtctr->add_req(0, loadConLNodes_Entry._last);
3719
3720 mtctr->_opnds[0] = new iRegLdstOper();
3721 mtctr->_opnds[1] = new iRegLdstOper();
3722
3723 // call node
3724 MachCallLeafNode *call = new CallLeafDirectNode();
3725
3726 call->_opnds[0] = _opnds[0];
3727 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3728
3729 // Make the new call node look like the old one.
3730 call->_name = _name;
3731 call->_tf = _tf;
3732 call->_entry_point = _entry_point;
3733 call->_cnt = _cnt;
3734 call->_argsize = _argsize;
3735 call->_oop_map = _oop_map;
3736 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3737 call->_jvms = NULL;
3738 call->_jvmadj = _jvmadj;
3739 call->_in_rms = _in_rms;
3740 call->_nesting = _nesting;
3741
3742
3743 // New call needs all inputs of old call.
3744 // Req...
3745 for (uint i = 0; i < req(); ++i) {
3746 if (i != mach_constant_base_node_input()) {
3747 call->add_req(in(i));
3748 }
3749 }
3750
3751 // These must be reqired edges, as the registers are live up to
3752 // the call. Else the constants are handled as kills.
3753 call->add_req(mtctr);
3754 #if !defined(ABI_ELFv2)
3755 call->add_req(loadConLNodes_Env._last);
3756 call->add_req(loadConLNodes_Toc._last);
3757 #endif
3758
3759 // ...as well as prec
3760 for (uint i = req(); i < len(); ++i) {
3761 call->add_prec(in(i));
3762 }
3763
3764 // registers
3765 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3766
3767 // Insert the new nodes.
3768 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3769 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3770 #if !defined(ABI_ELFv2)
3771 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3772 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3773 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3774 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3775 #endif
3776 nodes->push(mtctr);
3777 nodes->push(call);
3778 %}
3779 %}
3780
3781 //----------FRAME--------------------------------------------------------------
3782 // Definition of frame structure and management information.
3783
3784 frame %{
3785 // What direction does stack grow in (assumed to be same for native & Java).
3786 stack_direction(TOWARDS_LOW);
3787
3788 // These two registers define part of the calling convention between
3789 // compiled code and the interpreter.
3790
3791 // Inline Cache Register or method for I2C.
3792 inline_cache_reg(R19); // R19_method
3793
3794 // Method Oop Register when calling interpreter.
3795 interpreter_method_oop_reg(R19); // R19_method
3796
3797 // Optional: name the operand used by cisc-spilling to access
3798 // [stack_pointer + offset].
3799 cisc_spilling_operand_name(indOffset);
3800
3801 // Number of stack slots consumed by a Monitor enter.
3802 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3803
3804 // Compiled code's Frame Pointer.
3805 frame_pointer(R1); // R1_SP
3806
3807 // Interpreter stores its frame pointer in a register which is
3808 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3809 // interpreted java to compiled java.
3810 //
3811 // R14_state holds pointer to caller's cInterpreter.
3812 interpreter_frame_pointer(R14); // R14_state
3813
3814 stack_alignment(frame::alignment_in_bytes);
3815
3816 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3817
3818 // Number of outgoing stack slots killed above the
3819 // out_preserve_stack_slots for calls to C. Supports the var-args
3820 // backing area for register parms.
3821 //
3822 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3823
3824 // The after-PROLOG location of the return address. Location of
3825 // return address specifies a type (REG or STACK) and a number
3826 // representing the register number (i.e. - use a register name) or
3827 // stack slot.
3828 //
3829 // A: Link register is stored in stack slot ...
3830 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3831 // J: Therefore, we make sure that the link register is also in R11_scratch1
3832 // at the end of the prolog.
3833 // B: We use R20, now.
3834 //return_addr(REG R20);
3835
3836 // G: After reading the comments made by all the luminaries on their
3837 // failure to tell the compiler where the return address really is,
3838 // I hardly dare to try myself. However, I'm convinced it's in slot
3839 // 4 what apparently works and saves us some spills.
3840 return_addr(STACK 4);
3841
3842 // This is the body of the function
3843 //
3844 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3845 // uint length, // length of array
3846 // bool is_outgoing)
3847 //
3848 // The `sig' array is to be updated. sig[j] represents the location
3849 // of the j-th argument, either a register or a stack slot.
3850
3851 // Comment taken from i486.ad:
3852 // Body of function which returns an integer array locating
3853 // arguments either in registers or in stack slots. Passed an array
3854 // of ideal registers called "sig" and a "length" count. Stack-slot
3855 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3856 // arguments for a CALLEE. Incoming stack arguments are
3857 // automatically biased by the preserve_stack_slots field above.
3858 calling_convention %{
3859 // No difference between ingoing/outgoing. Just pass false.
3860 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3861 %}
3862
3863 // Comment taken from i486.ad:
3864 // Body of function which returns an integer array locating
3865 // arguments either in registers or in stack slots. Passed an array
3866 // of ideal registers called "sig" and a "length" count. Stack-slot
3867 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3868 // arguments for a CALLEE. Incoming stack arguments are
3869 // automatically biased by the preserve_stack_slots field above.
3870 c_calling_convention %{
3871 // This is obviously always outgoing.
3872 // C argument in register AND stack slot.
3873 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3874 %}
3875
3876 // Location of native (C/C++) and interpreter return values. This
3877 // is specified to be the same as Java. In the 32-bit VM, long
3878 // values are actually returned from native calls in O0:O1 and
3879 // returned to the interpreter in I0:I1. The copying to and from
3880 // the register pairs is done by the appropriate call and epilog
3881 // opcodes. This simplifies the register allocator.
3882 c_return_value %{
3883 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3884 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3885 "only return normal values");
3886 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3887 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3888 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3889 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3890 %}
3891
3892 // Location of compiled Java return values. Same as C
3893 return_value %{
3894 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3895 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3896 "only return normal values");
3897 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3898 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3899 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3900 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3901 %}
3902 %}
3903
3904
3905 //----------ATTRIBUTES---------------------------------------------------------
3906
3907 //----------Operand Attributes-------------------------------------------------
3908 op_attrib op_cost(1); // Required cost attribute.
3909
3910 //----------Instruction Attributes---------------------------------------------
3911
3912 // Cost attribute. required.
3913 ins_attrib ins_cost(DEFAULT_COST);
3914
3915 // Is this instruction a non-matching short branch variant of some
3916 // long branch? Not required.
3917 ins_attrib ins_short_branch(0);
3918
3919 ins_attrib ins_is_TrapBasedCheckNode(true);
3920
3921 // Number of constants.
3922 // This instruction uses the given number of constants
3923 // (optional attribute).
3924 // This is needed to determine in time whether the constant pool will
3925 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3926 // is determined. It's also used to compute the constant pool size
3927 // in Output().
3928 ins_attrib ins_num_consts(0);
3929
3930 // Required alignment attribute (must be a power of 2) specifies the
3931 // alignment that some part of the instruction (not necessarily the
3932 // start) requires. If > 1, a compute_padding() function must be
3933 // provided for the instruction.
3934 ins_attrib ins_alignment(1);
3935
3936 // Enforce/prohibit rematerializations.
3937 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3938 // then rematerialization of that instruction is prohibited and the
3939 // instruction's value will be spilled if necessary.
3940 // Causes that MachNode::rematerialize() returns false.
3941 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3942 // then rematerialization should be enforced and a copy of the instruction
3943 // should be inserted if possible; rematerialization is not guaranteed.
3944 // Note: this may result in rematerializations in front of every use.
3945 // Causes that MachNode::rematerialize() can return true.
3946 // (optional attribute)
3947 ins_attrib ins_cannot_rematerialize(false);
3948 ins_attrib ins_should_rematerialize(false);
3949
3950 // Instruction has variable size depending on alignment.
3951 ins_attrib ins_variable_size_depending_on_alignment(false);
3952
3953 // Instruction is a nop.
3954 ins_attrib ins_is_nop(false);
3955
3956 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3957 ins_attrib ins_use_mach_if_fast_lock_node(false);
3958
3959 // Field for the toc offset of a constant.
3960 //
3961 // This is needed if the toc offset is not encodable as an immediate in
3962 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3963 // added to the toc, and from this a load with immediate is performed.
3964 // With postalloc expand, we get two nodes that require the same offset
3965 // but which don't know about each other. The offset is only known
3966 // when the constant is added to the constant pool during emitting.
3967 // It is generated in the 'hi'-node adding the upper bits, and saved
3968 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3969 // the offset from there when it gets encoded.
3970 ins_attrib ins_field_const_toc_offset(0);
3971 ins_attrib ins_field_const_toc_offset_hi_node(0);
3972
3973 // A field that can hold the instructions offset in the code buffer.
3974 // Set in the nodes emitter.
3975 ins_attrib ins_field_cbuf_insts_offset(-1);
3976
3977 // Fields for referencing a call's load-IC-node.
3978 // If the toc offset can not be encoded as an immediate in a load, we
3979 // use two nodes.
3980 ins_attrib ins_field_load_ic_hi_node(0);
3981 ins_attrib ins_field_load_ic_node(0);
3982
3983 //----------OPERANDS-----------------------------------------------------------
3984 // Operand definitions must precede instruction definitions for correct
3985 // parsing in the ADLC because operands constitute user defined types
3986 // which are used in instruction definitions.
3987 //
3988 // Formats are generated automatically for constants and base registers.
3989
3990 //----------Simple Operands----------------------------------------------------
3991 // Immediate Operands
3992
3993 // Integer Immediate: 32-bit
3994 operand immI() %{
3995 match(ConI);
3996 op_cost(40);
3997 format %{ %}
3998 interface(CONST_INTER);
3999 %}
4000
4001 operand immI8() %{
4002 predicate(Assembler::is_simm(n->get_int(), 8));
4003 op_cost(0);
4004 match(ConI);
4005 format %{ %}
4006 interface(CONST_INTER);
4007 %}
4008
4009 // Integer Immediate: 16-bit
4010 operand immI16() %{
4011 predicate(Assembler::is_simm(n->get_int(), 16));
4012 op_cost(0);
4013 match(ConI);
4014 format %{ %}
4015 interface(CONST_INTER);
4016 %}
4017
4018 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4019 operand immIhi16() %{
4020 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4021 match(ConI);
4022 op_cost(0);
4023 format %{ %}
4024 interface(CONST_INTER);
4025 %}
4026
4027 operand immInegpow2() %{
4028 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4029 match(ConI);
4030 op_cost(0);
4031 format %{ %}
4032 interface(CONST_INTER);
4033 %}
4034
4035 operand immIpow2minus1() %{
4036 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4037 match(ConI);
4038 op_cost(0);
4039 format %{ %}
4040 interface(CONST_INTER);
4041 %}
4042
4043 operand immIpowerOf2() %{
4044 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4045 match(ConI);
4046 op_cost(0);
4047 format %{ %}
4048 interface(CONST_INTER);
4049 %}
4050
4051 // Unsigned Integer Immediate: the values 0-31
4052 operand uimmI5() %{
4053 predicate(Assembler::is_uimm(n->get_int(), 5));
4054 match(ConI);
4055 op_cost(0);
4056 format %{ %}
4057 interface(CONST_INTER);
4058 %}
4059
4060 // Unsigned Integer Immediate: 6-bit
4061 operand uimmI6() %{
4062 predicate(Assembler::is_uimm(n->get_int(), 6));
4063 match(ConI);
4064 op_cost(0);
4065 format %{ %}
4066 interface(CONST_INTER);
4067 %}
4068
4069 // Unsigned Integer Immediate: 6-bit int, greater than 32
4070 operand uimmI6_ge32() %{
4071 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4072 match(ConI);
4073 op_cost(0);
4074 format %{ %}
4075 interface(CONST_INTER);
4076 %}
4077
4078 // Unsigned Integer Immediate: 15-bit
4079 operand uimmI15() %{
4080 predicate(Assembler::is_uimm(n->get_int(), 15));
4081 match(ConI);
4082 op_cost(0);
4083 format %{ %}
4084 interface(CONST_INTER);
4085 %}
4086
4087 // Unsigned Integer Immediate: 16-bit
4088 operand uimmI16() %{
4089 predicate(Assembler::is_uimm(n->get_int(), 16));
4090 match(ConI);
4091 op_cost(0);
4092 format %{ %}
4093 interface(CONST_INTER);
4094 %}
4095
4096 // constant 'int 0'.
4097 operand immI_0() %{
4098 predicate(n->get_int() == 0);
4099 match(ConI);
4100 op_cost(0);
4101 format %{ %}
4102 interface(CONST_INTER);
4103 %}
4104
4105 // constant 'int 1'.
4106 operand immI_1() %{
4107 predicate(n->get_int() == 1);
4108 match(ConI);
4109 op_cost(0);
4110 format %{ %}
4111 interface(CONST_INTER);
4112 %}
4113
4114 // constant 'int -1'.
4115 operand immI_minus1() %{
4116 predicate(n->get_int() == -1);
4117 match(ConI);
4118 op_cost(0);
4119 format %{ %}
4120 interface(CONST_INTER);
4121 %}
4122
4123 // int value 16.
4124 operand immI_16() %{
4125 predicate(n->get_int() == 16);
4126 match(ConI);
4127 op_cost(0);
4128 format %{ %}
4129 interface(CONST_INTER);
4130 %}
4131
4132 // int value 24.
4133 operand immI_24() %{
4134 predicate(n->get_int() == 24);
4135 match(ConI);
4136 op_cost(0);
4137 format %{ %}
4138 interface(CONST_INTER);
4139 %}
4140
4141 // Compressed oops constants
4142 // Pointer Immediate
4143 operand immN() %{
4144 match(ConN);
4145
4146 op_cost(10);
4147 format %{ %}
4148 interface(CONST_INTER);
4149 %}
4150
4151 // NULL Pointer Immediate
4152 operand immN_0() %{
4153 predicate(n->get_narrowcon() == 0);
4154 match(ConN);
4155
4156 op_cost(0);
4157 format %{ %}
4158 interface(CONST_INTER);
4159 %}
4160
4161 // Compressed klass constants
4162 operand immNKlass() %{
4163 match(ConNKlass);
4164
4165 op_cost(0);
4166 format %{ %}
4167 interface(CONST_INTER);
4168 %}
4169
4170 // This operand can be used to avoid matching of an instruct
4171 // with chain rule.
4172 operand immNKlass_NM() %{
4173 match(ConNKlass);
4174 predicate(false);
4175 op_cost(0);
4176 format %{ %}
4177 interface(CONST_INTER);
4178 %}
4179
4180 // Pointer Immediate: 64-bit
4181 operand immP() %{
4182 match(ConP);
4183 op_cost(0);
4184 format %{ %}
4185 interface(CONST_INTER);
4186 %}
4187
4188 // Operand to avoid match of loadConP.
4189 // This operand can be used to avoid matching of an instruct
4190 // with chain rule.
4191 operand immP_NM() %{
4192 match(ConP);
4193 predicate(false);
4194 op_cost(0);
4195 format %{ %}
4196 interface(CONST_INTER);
4197 %}
4198
4199 // costant 'pointer 0'.
4200 operand immP_0() %{
4201 predicate(n->get_ptr() == 0);
4202 match(ConP);
4203 op_cost(0);
4204 format %{ %}
4205 interface(CONST_INTER);
4206 %}
4207
4208 // pointer 0x0 or 0x1
4209 operand immP_0or1() %{
4210 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4211 match(ConP);
4212 op_cost(0);
4213 format %{ %}
4214 interface(CONST_INTER);
4215 %}
4216
4217 operand immL() %{
4218 match(ConL);
4219 op_cost(40);
4220 format %{ %}
4221 interface(CONST_INTER);
4222 %}
4223
4224 // Long Immediate: 16-bit
4225 operand immL16() %{
4226 predicate(Assembler::is_simm(n->get_long(), 16));
4227 match(ConL);
4228 op_cost(0);
4229 format %{ %}
4230 interface(CONST_INTER);
4231 %}
4232
4233 // Long Immediate: 16-bit, 4-aligned
4234 operand immL16Alg4() %{
4235 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4236 match(ConL);
4237 op_cost(0);
4238 format %{ %}
4239 interface(CONST_INTER);
4240 %}
4241
4242 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4243 operand immL32hi16() %{
4244 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4245 match(ConL);
4246 op_cost(0);
4247 format %{ %}
4248 interface(CONST_INTER);
4249 %}
4250
4251 // Long Immediate: 32-bit
4252 operand immL32() %{
4253 predicate(Assembler::is_simm(n->get_long(), 32));
4254 match(ConL);
4255 op_cost(0);
4256 format %{ %}
4257 interface(CONST_INTER);
4258 %}
4259
4260 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4261 operand immLhighest16() %{
4262 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4263 match(ConL);
4264 op_cost(0);
4265 format %{ %}
4266 interface(CONST_INTER);
4267 %}
4268
4269 operand immLnegpow2() %{
4270 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4271 match(ConL);
4272 op_cost(0);
4273 format %{ %}
4274 interface(CONST_INTER);
4275 %}
4276
4277 operand immLpow2minus1() %{
4278 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4279 (n->get_long() != (jlong)0xffffffffffffffffL));
4280 match(ConL);
4281 op_cost(0);
4282 format %{ %}
4283 interface(CONST_INTER);
4284 %}
4285
4286 // constant 'long 0'.
4287 operand immL_0() %{
4288 predicate(n->get_long() == 0L);
4289 match(ConL);
4290 op_cost(0);
4291 format %{ %}
4292 interface(CONST_INTER);
4293 %}
4294
4295 // constat ' long -1'.
4296 operand immL_minus1() %{
4297 predicate(n->get_long() == -1L);
4298 match(ConL);
4299 op_cost(0);
4300 format %{ %}
4301 interface(CONST_INTER);
4302 %}
4303
4304 // Long Immediate: low 32-bit mask
4305 operand immL_32bits() %{
4306 predicate(n->get_long() == 0xFFFFFFFFL);
4307 match(ConL);
4308 op_cost(0);
4309 format %{ %}
4310 interface(CONST_INTER);
4311 %}
4312
4313 // Unsigned Long Immediate: 16-bit
4314 operand uimmL16() %{
4315 predicate(Assembler::is_uimm(n->get_long(), 16));
4316 match(ConL);
4317 op_cost(0);
4318 format %{ %}
4319 interface(CONST_INTER);
4320 %}
4321
4322 // Float Immediate
4323 operand immF() %{
4324 match(ConF);
4325 op_cost(40);
4326 format %{ %}
4327 interface(CONST_INTER);
4328 %}
4329
4330 // Float Immediate: +0.0f.
4331 operand immF_0() %{
4332 predicate(jint_cast(n->getf()) == 0);
4333 match(ConF);
4334
4335 op_cost(0);
4336 format %{ %}
4337 interface(CONST_INTER);
4338 %}
4339
4340 // Double Immediate
4341 operand immD() %{
4342 match(ConD);
4343 op_cost(40);
4344 format %{ %}
4345 interface(CONST_INTER);
4346 %}
4347
4348 // Integer Register Operands
4349 // Integer Destination Register
4350 // See definition of reg_class bits32_reg_rw.
4351 operand iRegIdst() %{
4352 constraint(ALLOC_IN_RC(bits32_reg_rw));
4353 match(RegI);
4354 match(rscratch1RegI);
4355 match(rscratch2RegI);
4356 match(rarg1RegI);
4357 match(rarg2RegI);
4358 match(rarg3RegI);
4359 match(rarg4RegI);
4360 format %{ %}
4361 interface(REG_INTER);
4362 %}
4363
4364 // Integer Source Register
4365 // See definition of reg_class bits32_reg_ro.
4366 operand iRegIsrc() %{
4367 constraint(ALLOC_IN_RC(bits32_reg_ro));
4368 match(RegI);
4369 match(rscratch1RegI);
4370 match(rscratch2RegI);
4371 match(rarg1RegI);
4372 match(rarg2RegI);
4373 match(rarg3RegI);
4374 match(rarg4RegI);
4375 format %{ %}
4376 interface(REG_INTER);
4377 %}
4378
4379 operand rscratch1RegI() %{
4380 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4381 match(iRegIdst);
4382 format %{ %}
4383 interface(REG_INTER);
4384 %}
4385
4386 operand rscratch2RegI() %{
4387 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4388 match(iRegIdst);
4389 format %{ %}
4390 interface(REG_INTER);
4391 %}
4392
4393 operand rarg1RegI() %{
4394 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4395 match(iRegIdst);
4396 format %{ %}
4397 interface(REG_INTER);
4398 %}
4399
4400 operand rarg2RegI() %{
4401 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4402 match(iRegIdst);
4403 format %{ %}
4404 interface(REG_INTER);
4405 %}
4406
4407 operand rarg3RegI() %{
4408 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4409 match(iRegIdst);
4410 format %{ %}
4411 interface(REG_INTER);
4412 %}
4413
4414 operand rarg4RegI() %{
4415 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4416 match(iRegIdst);
4417 format %{ %}
4418 interface(REG_INTER);
4419 %}
4420
4421 operand rarg1RegL() %{
4422 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4423 match(iRegLdst);
4424 format %{ %}
4425 interface(REG_INTER);
4426 %}
4427
4428 operand rarg2RegL() %{
4429 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4430 match(iRegLdst);
4431 format %{ %}
4432 interface(REG_INTER);
4433 %}
4434
4435 operand rarg3RegL() %{
4436 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4437 match(iRegLdst);
4438 format %{ %}
4439 interface(REG_INTER);
4440 %}
4441
4442 operand rarg4RegL() %{
4443 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4444 match(iRegLdst);
4445 format %{ %}
4446 interface(REG_INTER);
4447 %}
4448
4449 // Pointer Destination Register
4450 // See definition of reg_class bits64_reg_rw.
4451 operand iRegPdst() %{
4452 constraint(ALLOC_IN_RC(bits64_reg_rw));
4453 match(RegP);
4454 match(rscratch1RegP);
4455 match(rscratch2RegP);
4456 match(rarg1RegP);
4457 match(rarg2RegP);
4458 match(rarg3RegP);
4459 match(rarg4RegP);
4460 format %{ %}
4461 interface(REG_INTER);
4462 %}
4463
4464 // Pointer Destination Register
4465 // Operand not using r11 and r12 (killed in epilog).
4466 operand iRegPdstNoScratch() %{
4467 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4468 match(RegP);
4469 match(rarg1RegP);
4470 match(rarg2RegP);
4471 match(rarg3RegP);
4472 match(rarg4RegP);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4476
4477 // Pointer Source Register
4478 // See definition of reg_class bits64_reg_ro.
4479 operand iRegPsrc() %{
4480 constraint(ALLOC_IN_RC(bits64_reg_ro));
4481 match(RegP);
4482 match(iRegPdst);
4483 match(rscratch1RegP);
4484 match(rscratch2RegP);
4485 match(rarg1RegP);
4486 match(rarg2RegP);
4487 match(rarg3RegP);
4488 match(rarg4RegP);
4489 match(threadRegP);
4490 format %{ %}
4491 interface(REG_INTER);
4492 %}
4493
4494 // Thread operand.
4495 operand threadRegP() %{
4496 constraint(ALLOC_IN_RC(thread_bits64_reg));
4497 match(iRegPdst);
4498 format %{ "R16" %}
4499 interface(REG_INTER);
4500 %}
4501
4502 operand rscratch1RegP() %{
4503 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4504 match(iRegPdst);
4505 format %{ "R11" %}
4506 interface(REG_INTER);
4507 %}
4508
4509 operand rscratch2RegP() %{
4510 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4511 match(iRegPdst);
4512 format %{ %}
4513 interface(REG_INTER);
4514 %}
4515
4516 operand rarg1RegP() %{
4517 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4518 match(iRegPdst);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4522
4523 operand rarg2RegP() %{
4524 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4525 match(iRegPdst);
4526 format %{ %}
4527 interface(REG_INTER);
4528 %}
4529
4530 operand rarg3RegP() %{
4531 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4532 match(iRegPdst);
4533 format %{ %}
4534 interface(REG_INTER);
4535 %}
4536
4537 operand rarg4RegP() %{
4538 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4539 match(iRegPdst);
4540 format %{ %}
4541 interface(REG_INTER);
4542 %}
4543
4544 operand iRegNsrc() %{
4545 constraint(ALLOC_IN_RC(bits32_reg_ro));
4546 match(RegN);
4547 match(iRegNdst);
4548
4549 format %{ %}
4550 interface(REG_INTER);
4551 %}
4552
4553 operand iRegNdst() %{
4554 constraint(ALLOC_IN_RC(bits32_reg_rw));
4555 match(RegN);
4556
4557 format %{ %}
4558 interface(REG_INTER);
4559 %}
4560
4561 // Long Destination Register
4562 // See definition of reg_class bits64_reg_rw.
4563 operand iRegLdst() %{
4564 constraint(ALLOC_IN_RC(bits64_reg_rw));
4565 match(RegL);
4566 match(rscratch1RegL);
4567 match(rscratch2RegL);
4568 format %{ %}
4569 interface(REG_INTER);
4570 %}
4571
4572 // Long Source Register
4573 // See definition of reg_class bits64_reg_ro.
4574 operand iRegLsrc() %{
4575 constraint(ALLOC_IN_RC(bits64_reg_ro));
4576 match(RegL);
4577 match(iRegLdst);
4578 match(rscratch1RegL);
4579 match(rscratch2RegL);
4580 format %{ %}
4581 interface(REG_INTER);
4582 %}
4583
4584 // Special operand for ConvL2I.
4585 operand iRegL2Isrc(iRegLsrc reg) %{
4586 constraint(ALLOC_IN_RC(bits64_reg_ro));
4587 match(ConvL2I reg);
4588 format %{ "ConvL2I($reg)" %}
4589 interface(REG_INTER)
4590 %}
4591
4592 operand rscratch1RegL() %{
4593 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4594 match(RegL);
4595 format %{ %}
4596 interface(REG_INTER);
4597 %}
4598
4599 operand rscratch2RegL() %{
4600 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4601 match(RegL);
4602 format %{ %}
4603 interface(REG_INTER);
4604 %}
4605
4606 // Condition Code Flag Registers
4607 operand flagsReg() %{
4608 constraint(ALLOC_IN_RC(int_flags));
4609 match(RegFlags);
4610 format %{ %}
4611 interface(REG_INTER);
4612 %}
4613
4614 operand flagsRegSrc() %{
4615 constraint(ALLOC_IN_RC(int_flags_ro));
4616 match(RegFlags);
4617 match(flagsReg);
4618 match(flagsRegCR0);
4619 format %{ %}
4620 interface(REG_INTER);
4621 %}
4622
4623 // Condition Code Flag Register CR0
4624 operand flagsRegCR0() %{
4625 constraint(ALLOC_IN_RC(int_flags_CR0));
4626 match(RegFlags);
4627 format %{ "CR0" %}
4628 interface(REG_INTER);
4629 %}
4630
4631 operand flagsRegCR1() %{
4632 constraint(ALLOC_IN_RC(int_flags_CR1));
4633 match(RegFlags);
4634 format %{ "CR1" %}
4635 interface(REG_INTER);
4636 %}
4637
4638 operand flagsRegCR6() %{
4639 constraint(ALLOC_IN_RC(int_flags_CR6));
4640 match(RegFlags);
4641 format %{ "CR6" %}
4642 interface(REG_INTER);
4643 %}
4644
4645 operand regCTR() %{
4646 constraint(ALLOC_IN_RC(ctr_reg));
4647 // RegFlags should work. Introducing a RegSpecial type would cause a
4648 // lot of changes.
4649 match(RegFlags);
4650 format %{"SR_CTR" %}
4651 interface(REG_INTER);
4652 %}
4653
4654 operand regD() %{
4655 constraint(ALLOC_IN_RC(dbl_reg));
4656 match(RegD);
4657 format %{ %}
4658 interface(REG_INTER);
4659 %}
4660
4661 operand regF() %{
4662 constraint(ALLOC_IN_RC(flt_reg));
4663 match(RegF);
4664 format %{ %}
4665 interface(REG_INTER);
4666 %}
4667
4668 // Special Registers
4669
4670 // Method Register
4671 operand inline_cache_regP(iRegPdst reg) %{
4672 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4673 match(reg);
4674 format %{ %}
4675 interface(REG_INTER);
4676 %}
4677
4678 operand compiler_method_oop_regP(iRegPdst reg) %{
4679 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4680 match(reg);
4681 format %{ %}
4682 interface(REG_INTER);
4683 %}
4684
4685 operand interpreter_method_oop_regP(iRegPdst reg) %{
4686 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4687 match(reg);
4688 format %{ %}
4689 interface(REG_INTER);
4690 %}
4691
4692 // Operands to remove register moves in unscaled mode.
4693 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4694 operand iRegP2N(iRegPsrc reg) %{
4695 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4696 constraint(ALLOC_IN_RC(bits64_reg_ro));
4697 match(EncodeP reg);
4698 format %{ "$reg" %}
4699 interface(REG_INTER)
4700 %}
4701
4702 operand iRegN2P(iRegNsrc reg) %{
4703 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4704 constraint(ALLOC_IN_RC(bits32_reg_ro));
4705 match(DecodeN reg);
4706 format %{ "$reg" %}
4707 interface(REG_INTER)
4708 %}
4709
4710 operand iRegN2P_klass(iRegNsrc reg) %{
4711 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4712 constraint(ALLOC_IN_RC(bits32_reg_ro));
4713 match(DecodeNKlass reg);
4714 format %{ "$reg" %}
4715 interface(REG_INTER)
4716 %}
4717
4718 //----------Complex Operands---------------------------------------------------
4719 // Indirect Memory Reference
4720 operand indirect(iRegPsrc reg) %{
4721 constraint(ALLOC_IN_RC(bits64_reg_ro));
4722 match(reg);
4723 op_cost(100);
4724 format %{ "[$reg]" %}
4725 interface(MEMORY_INTER) %{
4726 base($reg);
4727 index(0x0);
4728 scale(0x0);
4729 disp(0x0);
4730 %}
4731 %}
4732
4733 // Indirect with Offset
4734 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4735 constraint(ALLOC_IN_RC(bits64_reg_ro));
4736 match(AddP reg offset);
4737 op_cost(100);
4738 format %{ "[$reg + $offset]" %}
4739 interface(MEMORY_INTER) %{
4740 base($reg);
4741 index(0x0);
4742 scale(0x0);
4743 disp($offset);
4744 %}
4745 %}
4746
4747 // Indirect with 4-aligned Offset
4748 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4749 constraint(ALLOC_IN_RC(bits64_reg_ro));
4750 match(AddP reg offset);
4751 op_cost(100);
4752 format %{ "[$reg + $offset]" %}
4753 interface(MEMORY_INTER) %{
4754 base($reg);
4755 index(0x0);
4756 scale(0x0);
4757 disp($offset);
4758 %}
4759 %}
4760
4761 //----------Complex Operands for Compressed OOPs-------------------------------
4762 // Compressed OOPs with narrow_oop_shift == 0.
4763
4764 // Indirect Memory Reference, compressed OOP
4765 operand indirectNarrow(iRegNsrc reg) %{
4766 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4767 constraint(ALLOC_IN_RC(bits64_reg_ro));
4768 match(DecodeN reg);
4769 op_cost(100);
4770 format %{ "[$reg]" %}
4771 interface(MEMORY_INTER) %{
4772 base($reg);
4773 index(0x0);
4774 scale(0x0);
4775 disp(0x0);
4776 %}
4777 %}
4778
4779 operand indirectNarrow_klass(iRegNsrc reg) %{
4780 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4781 constraint(ALLOC_IN_RC(bits64_reg_ro));
4782 match(DecodeNKlass reg);
4783 op_cost(100);
4784 format %{ "[$reg]" %}
4785 interface(MEMORY_INTER) %{
4786 base($reg);
4787 index(0x0);
4788 scale(0x0);
4789 disp(0x0);
4790 %}
4791 %}
4792
4793 // Indirect with Offset, compressed OOP
4794 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4795 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4796 constraint(ALLOC_IN_RC(bits64_reg_ro));
4797 match(AddP (DecodeN reg) offset);
4798 op_cost(100);
4799 format %{ "[$reg + $offset]" %}
4800 interface(MEMORY_INTER) %{
4801 base($reg);
4802 index(0x0);
4803 scale(0x0);
4804 disp($offset);
4805 %}
4806 %}
4807
4808 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4809 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4810 constraint(ALLOC_IN_RC(bits64_reg_ro));
4811 match(AddP (DecodeNKlass reg) offset);
4812 op_cost(100);
4813 format %{ "[$reg + $offset]" %}
4814 interface(MEMORY_INTER) %{
4815 base($reg);
4816 index(0x0);
4817 scale(0x0);
4818 disp($offset);
4819 %}
4820 %}
4821
4822 // Indirect with 4-aligned Offset, compressed OOP
4823 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4824 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4825 constraint(ALLOC_IN_RC(bits64_reg_ro));
4826 match(AddP (DecodeN reg) offset);
4827 op_cost(100);
4828 format %{ "[$reg + $offset]" %}
4829 interface(MEMORY_INTER) %{
4830 base($reg);
4831 index(0x0);
4832 scale(0x0);
4833 disp($offset);
4834 %}
4835 %}
4836
4837 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4838 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4839 constraint(ALLOC_IN_RC(bits64_reg_ro));
4840 match(AddP (DecodeNKlass reg) offset);
4841 op_cost(100);
4842 format %{ "[$reg + $offset]" %}
4843 interface(MEMORY_INTER) %{
4844 base($reg);
4845 index(0x0);
4846 scale(0x0);
4847 disp($offset);
4848 %}
4849 %}
4850
4851 //----------Special Memory Operands--------------------------------------------
4852 // Stack Slot Operand
4853 //
4854 // This operand is used for loading and storing temporary values on
4855 // the stack where a match requires a value to flow through memory.
4856 operand stackSlotI(sRegI reg) %{
4857 constraint(ALLOC_IN_RC(stack_slots));
4858 op_cost(100);
4859 //match(RegI);
4860 format %{ "[sp+$reg]" %}
4861 interface(MEMORY_INTER) %{
4862 base(0x1); // R1_SP
4863 index(0x0);
4864 scale(0x0);
4865 disp($reg); // Stack Offset
4866 %}
4867 %}
4868
4869 operand stackSlotL(sRegL reg) %{
4870 constraint(ALLOC_IN_RC(stack_slots));
4871 op_cost(100);
4872 //match(RegL);
4873 format %{ "[sp+$reg]" %}
4874 interface(MEMORY_INTER) %{
4875 base(0x1); // R1_SP
4876 index(0x0);
4877 scale(0x0);
4878 disp($reg); // Stack Offset
4879 %}
4880 %}
4881
4882 operand stackSlotP(sRegP reg) %{
4883 constraint(ALLOC_IN_RC(stack_slots));
4884 op_cost(100);
4885 //match(RegP);
4886 format %{ "[sp+$reg]" %}
4887 interface(MEMORY_INTER) %{
4888 base(0x1); // R1_SP
4889 index(0x0);
4890 scale(0x0);
4891 disp($reg); // Stack Offset
4892 %}
4893 %}
4894
4895 operand stackSlotF(sRegF reg) %{
4896 constraint(ALLOC_IN_RC(stack_slots));
4897 op_cost(100);
4898 //match(RegF);
4899 format %{ "[sp+$reg]" %}
4900 interface(MEMORY_INTER) %{
4901 base(0x1); // R1_SP
4902 index(0x0);
4903 scale(0x0);
4904 disp($reg); // Stack Offset
4905 %}
4906 %}
4907
4908 operand stackSlotD(sRegD reg) %{
4909 constraint(ALLOC_IN_RC(stack_slots));
4910 op_cost(100);
4911 //match(RegD);
4912 format %{ "[sp+$reg]" %}
4913 interface(MEMORY_INTER) %{
4914 base(0x1); // R1_SP
4915 index(0x0);
4916 scale(0x0);
4917 disp($reg); // Stack Offset
4918 %}
4919 %}
4920
4921 // Operands for expressing Control Flow
4922 // NOTE: Label is a predefined operand which should not be redefined in
4923 // the AD file. It is generically handled within the ADLC.
4924
4925 //----------Conditional Branch Operands----------------------------------------
4926 // Comparison Op
4927 //
4928 // This is the operation of the comparison, and is limited to the
4929 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4930 // (!=).
4931 //
4932 // Other attributes of the comparison, such as unsignedness, are specified
4933 // by the comparison instruction that sets a condition code flags register.
4934 // That result is represented by a flags operand whose subtype is appropriate
4935 // to the unsignedness (etc.) of the comparison.
4936 //
4937 // Later, the instruction which matches both the Comparison Op (a Bool) and
4938 // the flags (produced by the Cmp) specifies the coding of the comparison op
4939 // by matching a specific subtype of Bool operand below.
4940
4941 // When used for floating point comparisons: unordered same as less.
4942 operand cmpOp() %{
4943 match(Bool);
4944 format %{ "" %}
4945 interface(COND_INTER) %{
4946 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4947 // BO & BI
4948 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4949 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4950 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4951 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4952 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4953 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4954 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4955 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4956 %}
4957 %}
4958
4959 //----------OPERAND CLASSES----------------------------------------------------
4960 // Operand Classes are groups of operands that are used to simplify
4961 // instruction definitions by not requiring the AD writer to specify
4962 // seperate instructions for every form of operand when the
4963 // instruction accepts multiple operand types with the same basic
4964 // encoding and format. The classic case of this is memory operands.
4965 // Indirect is not included since its use is limited to Compare & Swap.
4966
4967 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4968 // Memory operand where offsets are 4-aligned. Required for ld, std.
4969 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4970 opclass indirectMemory(indirect, indirectNarrow);
4971
4972 // Special opclass for I and ConvL2I.
4973 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4974
4975 // Operand classes to match encode and decode. iRegN_P2N is only used
4976 // for storeN. I have never seen an encode node elsewhere.
4977 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4978 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4979
4980 //----------PIPELINE-----------------------------------------------------------
4981
4982 pipeline %{
4983
4984 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4985 // J. Res. & Dev., No. 1, Jan. 2002.
4986
4987 //----------ATTRIBUTES---------------------------------------------------------
4988 attributes %{
4989
4990 // Power4 instructions are of fixed length.
4991 fixed_size_instructions;
4992
4993 // TODO: if `bundle' means number of instructions fetched
4994 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4995 // max instructions issued per cycle, this is 5.
4996 max_instructions_per_bundle = 8;
4997
4998 // A Power4 instruction is 4 bytes long.
4999 instruction_unit_size = 4;
5000
5001 // The Power4 processor fetches 64 bytes...
5002 instruction_fetch_unit_size = 64;
5003
5004 // ...in one line
5005 instruction_fetch_units = 1
5006
5007 // Unused, list one so that array generated by adlc is not empty.
5008 // Aix compiler chokes if _nop_count = 0.
5009 nops(fxNop);
5010 %}
5011
5012 //----------RESOURCES----------------------------------------------------------
5013 // Resources are the functional units available to the machine
5014 resources(
5015 PPC_BR, // branch unit
5016 PPC_CR, // condition unit
5017 PPC_FX1, // integer arithmetic unit 1
5018 PPC_FX2, // integer arithmetic unit 2
5019 PPC_LDST1, // load/store unit 1
5020 PPC_LDST2, // load/store unit 2
5021 PPC_FP1, // float arithmetic unit 1
5022 PPC_FP2, // float arithmetic unit 2
5023 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5024 PPC_FX = PPC_FX1 | PPC_FX2,
5025 PPC_FP = PPC_FP1 | PPC_FP2
5026 );
5027
5028 //----------PIPELINE DESCRIPTION-----------------------------------------------
5029 // Pipeline Description specifies the stages in the machine's pipeline
5030 pipe_desc(
5031 // Power4 longest pipeline path
5032 PPC_IF, // instruction fetch
5033 PPC_IC,
5034 //PPC_BP, // branch prediction
5035 PPC_D0, // decode
5036 PPC_D1, // decode
5037 PPC_D2, // decode
5038 PPC_D3, // decode
5039 PPC_Xfer1,
5040 PPC_GD, // group definition
5041 PPC_MP, // map
5042 PPC_ISS, // issue
5043 PPC_RF, // resource fetch
5044 PPC_EX1, // execute (all units)
5045 PPC_EX2, // execute (FP, LDST)
5046 PPC_EX3, // execute (FP, LDST)
5047 PPC_EX4, // execute (FP)
5048 PPC_EX5, // execute (FP)
5049 PPC_EX6, // execute (FP)
5050 PPC_WB, // write back
5051 PPC_Xfer2,
5052 PPC_CP
5053 );
5054
5055 //----------PIPELINE CLASSES---------------------------------------------------
5056 // Pipeline Classes describe the stages in which input and output are
5057 // referenced by the hardware pipeline.
5058
5059 // Simple pipeline classes.
5060
5061 // Default pipeline class.
5062 pipe_class pipe_class_default() %{
5063 single_instruction;
5064 fixed_latency(2);
5065 %}
5066
5067 // Pipeline class for empty instructions.
5068 pipe_class pipe_class_empty() %{
5069 single_instruction;
5070 fixed_latency(0);
5071 %}
5072
5073 // Pipeline class for compares.
5074 pipe_class pipe_class_compare() %{
5075 single_instruction;
5076 fixed_latency(16);
5077 %}
5078
5079 // Pipeline class for traps.
5080 pipe_class pipe_class_trap() %{
5081 single_instruction;
5082 fixed_latency(100);
5083 %}
5084
5085 // Pipeline class for memory operations.
5086 pipe_class pipe_class_memory() %{
5087 single_instruction;
5088 fixed_latency(16);
5089 %}
5090
5091 // Pipeline class for call.
5092 pipe_class pipe_class_call() %{
5093 single_instruction;
5094 fixed_latency(100);
5095 %}
5096
5097 // Define the class for the Nop node.
5098 define %{
5099 MachNop = pipe_class_default;
5100 %}
5101
5102 %}
5103
5104 //----------INSTRUCTIONS-------------------------------------------------------
5105
5106 // Naming of instructions:
5107 // opA_operB / opA_operB_operC:
5108 // Operation 'op' with one or two source operands 'oper'. Result
5109 // type is A, source operand types are B and C.
5110 // Iff A == B == C, B and C are left out.
5111 //
5112 // The instructions are ordered according to the following scheme:
5113 // - loads
5114 // - load constants
5115 // - prefetch
5116 // - store
5117 // - encode/decode
5118 // - membar
5119 // - conditional moves
5120 // - compare & swap
5121 // - arithmetic and logic operations
5122 // * int: Add, Sub, Mul, Div, Mod
5123 // * int: lShift, arShift, urShift, rot
5124 // * float: Add, Sub, Mul, Div
5125 // * and, or, xor ...
5126 // - register moves: float <-> int, reg <-> stack, repl
5127 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5128 // - conv (low level type cast requiring bit changes (sign extend etc)
5129 // - compares, range & zero checks.
5130 // - branches
5131 // - complex operations, intrinsics, min, max, replicate
5132 // - lock
5133 // - Calls
5134 //
5135 // If there are similar instructions with different types they are sorted:
5136 // int before float
5137 // small before big
5138 // signed before unsigned
5139 // e.g., loadS before loadUS before loadI before loadF.
5140
5141
5142 //----------Load/Store Instructions--------------------------------------------
5143
5144 //----------Load Instructions--------------------------------------------------
5145
5146 // Converts byte to int.
5147 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5148 // reuses the 'amount' operand, but adlc expects that operand specification
5149 // and operands in match rule are equivalent.
5150 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5151 effect(DEF dst, USE src);
5152 format %{ "EXTSB $dst, $src \t// byte->int" %}
5153 size(4);
5154 ins_encode %{
5155 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5156 __ extsb($dst$$Register, $src$$Register);
5157 %}
5158 ins_pipe(pipe_class_default);
5159 %}
5160
5161 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5162 // match-rule, false predicate
5163 match(Set dst (LoadB mem));
5164 predicate(false);
5165
5166 format %{ "LBZ $dst, $mem" %}
5167 size(4);
5168 ins_encode( enc_lbz(dst, mem) );
5169 ins_pipe(pipe_class_memory);
5170 %}
5171
5172 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5173 // match-rule, false predicate
5174 match(Set dst (LoadB mem));
5175 predicate(false);
5176
5177 format %{ "LBZ $dst, $mem\n\t"
5178 "TWI $dst\n\t"
5179 "ISYNC" %}
5180 size(12);
5181 ins_encode( enc_lbz_ac(dst, mem) );
5182 ins_pipe(pipe_class_memory);
5183 %}
5184
5185 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5186 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5187 match(Set dst (LoadB mem));
5188 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5189 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5190 expand %{
5191 iRegIdst tmp;
5192 loadUB_indirect(tmp, mem);
5193 convB2I_reg_2(dst, tmp);
5194 %}
5195 %}
5196
5197 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5198 match(Set dst (LoadB mem));
5199 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5200 expand %{
5201 iRegIdst tmp;
5202 loadUB_indirect_ac(tmp, mem);
5203 convB2I_reg_2(dst, tmp);
5204 %}
5205 %}
5206
5207 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5208 // match-rule, false predicate
5209 match(Set dst (LoadB mem));
5210 predicate(false);
5211
5212 format %{ "LBZ $dst, $mem" %}
5213 size(4);
5214 ins_encode( enc_lbz(dst, mem) );
5215 ins_pipe(pipe_class_memory);
5216 %}
5217
5218 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5219 // match-rule, false predicate
5220 match(Set dst (LoadB mem));
5221 predicate(false);
5222
5223 format %{ "LBZ $dst, $mem\n\t"
5224 "TWI $dst\n\t"
5225 "ISYNC" %}
5226 size(12);
5227 ins_encode( enc_lbz_ac(dst, mem) );
5228 ins_pipe(pipe_class_memory);
5229 %}
5230
5231 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5232 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5233 match(Set dst (LoadB mem));
5234 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5235 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5236
5237 expand %{
5238 iRegIdst tmp;
5239 loadUB_indOffset16(tmp, mem);
5240 convB2I_reg_2(dst, tmp);
5241 %}
5242 %}
5243
5244 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5245 match(Set dst (LoadB mem));
5246 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5247
5248 expand %{
5249 iRegIdst tmp;
5250 loadUB_indOffset16_ac(tmp, mem);
5251 convB2I_reg_2(dst, tmp);
5252 %}
5253 %}
5254
5255 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5256 instruct loadUB(iRegIdst dst, memory mem) %{
5257 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5258 match(Set dst (LoadUB mem));
5259 ins_cost(MEMORY_REF_COST);
5260
5261 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5262 size(4);
5263 ins_encode( enc_lbz(dst, mem) );
5264 ins_pipe(pipe_class_memory);
5265 %}
5266
5267 // Load Unsigned Byte (8bit UNsigned) acquire.
5268 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5269 match(Set dst (LoadUB mem));
5270 ins_cost(3*MEMORY_REF_COST);
5271
5272 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5273 "TWI $dst\n\t"
5274 "ISYNC" %}
5275 size(12);
5276 ins_encode( enc_lbz_ac(dst, mem) );
5277 ins_pipe(pipe_class_memory);
5278 %}
5279
5280 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5281 instruct loadUB2L(iRegLdst dst, memory mem) %{
5282 match(Set dst (ConvI2L (LoadUB mem)));
5283 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5284 ins_cost(MEMORY_REF_COST);
5285
5286 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5287 size(4);
5288 ins_encode( enc_lbz(dst, mem) );
5289 ins_pipe(pipe_class_memory);
5290 %}
5291
5292 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5293 match(Set dst (ConvI2L (LoadUB mem)));
5294 ins_cost(3*MEMORY_REF_COST);
5295
5296 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5297 "TWI $dst\n\t"
5298 "ISYNC" %}
5299 size(12);
5300 ins_encode( enc_lbz_ac(dst, mem) );
5301 ins_pipe(pipe_class_memory);
5302 %}
5303
5304 // Load Short (16bit signed)
5305 instruct loadS(iRegIdst dst, memory mem) %{
5306 match(Set dst (LoadS mem));
5307 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5308 ins_cost(MEMORY_REF_COST);
5309
5310 format %{ "LHA $dst, $mem" %}
5311 size(4);
5312 ins_encode %{
5313 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5314 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5315 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5316 %}
5317 ins_pipe(pipe_class_memory);
5318 %}
5319
5320 // Load Short (16bit signed) acquire.
5321 instruct loadS_ac(iRegIdst dst, memory mem) %{
5322 match(Set dst (LoadS mem));
5323 ins_cost(3*MEMORY_REF_COST);
5324
5325 format %{ "LHA $dst, $mem\t acquire\n\t"
5326 "TWI $dst\n\t"
5327 "ISYNC" %}
5328 size(12);
5329 ins_encode %{
5330 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5331 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5332 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5333 __ twi_0($dst$$Register);
5334 __ isync();
5335 %}
5336 ins_pipe(pipe_class_memory);
5337 %}
5338
5339 // Load Char (16bit unsigned)
5340 instruct loadUS(iRegIdst dst, memory mem) %{
5341 match(Set dst (LoadUS mem));
5342 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5343 ins_cost(MEMORY_REF_COST);
5344
5345 format %{ "LHZ $dst, $mem" %}
5346 size(4);
5347 ins_encode( enc_lhz(dst, mem) );
5348 ins_pipe(pipe_class_memory);
5349 %}
5350
5351 // Load Char (16bit unsigned) acquire.
5352 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5353 match(Set dst (LoadUS mem));
5354 ins_cost(3*MEMORY_REF_COST);
5355
5356 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5357 "TWI $dst\n\t"
5358 "ISYNC" %}
5359 size(12);
5360 ins_encode( enc_lhz_ac(dst, mem) );
5361 ins_pipe(pipe_class_memory);
5362 %}
5363
5364 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5365 instruct loadUS2L(iRegLdst dst, memory mem) %{
5366 match(Set dst (ConvI2L (LoadUS mem)));
5367 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5368 ins_cost(MEMORY_REF_COST);
5369
5370 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5371 size(4);
5372 ins_encode( enc_lhz(dst, mem) );
5373 ins_pipe(pipe_class_memory);
5374 %}
5375
5376 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5377 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5378 match(Set dst (ConvI2L (LoadUS mem)));
5379 ins_cost(3*MEMORY_REF_COST);
5380
5381 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5382 "TWI $dst\n\t"
5383 "ISYNC" %}
5384 size(12);
5385 ins_encode( enc_lhz_ac(dst, mem) );
5386 ins_pipe(pipe_class_memory);
5387 %}
5388
5389 // Load Integer.
5390 instruct loadI(iRegIdst dst, memory mem) %{
5391 match(Set dst (LoadI mem));
5392 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5393 ins_cost(MEMORY_REF_COST);
5394
5395 format %{ "LWZ $dst, $mem" %}
5396 size(4);
5397 ins_encode( enc_lwz(dst, mem) );
5398 ins_pipe(pipe_class_memory);
5399 %}
5400
5401 // Load Integer acquire.
5402 instruct loadI_ac(iRegIdst dst, memory mem) %{
5403 match(Set dst (LoadI mem));
5404 ins_cost(3*MEMORY_REF_COST);
5405
5406 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5407 "TWI $dst\n\t"
5408 "ISYNC" %}
5409 size(12);
5410 ins_encode( enc_lwz_ac(dst, mem) );
5411 ins_pipe(pipe_class_memory);
5412 %}
5413
5414 // Match loading integer and casting it to unsigned int in
5415 // long register.
5416 // LoadI + ConvI2L + AndL 0xffffffff.
5417 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5418 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5419 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5420 ins_cost(MEMORY_REF_COST);
5421
5422 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5423 size(4);
5424 ins_encode( enc_lwz(dst, mem) );
5425 ins_pipe(pipe_class_memory);
5426 %}
5427
5428 // Match loading integer and casting it to long.
5429 instruct loadI2L(iRegLdst dst, memory mem) %{
5430 match(Set dst (ConvI2L (LoadI mem)));
5431 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5432 ins_cost(MEMORY_REF_COST);
5433
5434 format %{ "LWA $dst, $mem \t// loadI2L" %}
5435 size(4);
5436 ins_encode %{
5437 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5438 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5439 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5440 %}
5441 ins_pipe(pipe_class_memory);
5442 %}
5443
5444 // Match loading integer and casting it to long - acquire.
5445 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5446 match(Set dst (ConvI2L (LoadI mem)));
5447 ins_cost(3*MEMORY_REF_COST);
5448
5449 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5450 "TWI $dst\n\t"
5451 "ISYNC" %}
5452 size(12);
5453 ins_encode %{
5454 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5455 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5456 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5457 __ twi_0($dst$$Register);
5458 __ isync();
5459 %}
5460 ins_pipe(pipe_class_memory);
5461 %}
5462
5463 // Load Long - aligned
5464 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5465 match(Set dst (LoadL mem));
5466 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5467 ins_cost(MEMORY_REF_COST);
5468
5469 format %{ "LD $dst, $mem \t// long" %}
5470 size(4);
5471 ins_encode( enc_ld(dst, mem) );
5472 ins_pipe(pipe_class_memory);
5473 %}
5474
5475 // Load Long - aligned acquire.
5476 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5477 match(Set dst (LoadL mem));
5478 ins_cost(3*MEMORY_REF_COST);
5479
5480 format %{ "LD $dst, $mem \t// long acquire\n\t"
5481 "TWI $dst\n\t"
5482 "ISYNC" %}
5483 size(12);
5484 ins_encode( enc_ld_ac(dst, mem) );
5485 ins_pipe(pipe_class_memory);
5486 %}
5487
5488 // Load Long - UNaligned
5489 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5490 match(Set dst (LoadL_unaligned mem));
5491 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5492 ins_cost(MEMORY_REF_COST);
5493
5494 format %{ "LD $dst, $mem \t// unaligned long" %}
5495 size(4);
5496 ins_encode( enc_ld(dst, mem) );
5497 ins_pipe(pipe_class_memory);
5498 %}
5499
5500 // Load nodes for superwords
5501
5502 // Load Aligned Packed Byte
5503 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5504 predicate(n->as_LoadVector()->memory_size() == 8);
5505 match(Set dst (LoadVector mem));
5506 ins_cost(MEMORY_REF_COST);
5507
5508 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5509 size(4);
5510 ins_encode( enc_ld(dst, mem) );
5511 ins_pipe(pipe_class_memory);
5512 %}
5513
5514 // Load Range, range = array length (=jint)
5515 instruct loadRange(iRegIdst dst, memory mem) %{
5516 match(Set dst (LoadRange mem));
5517 ins_cost(MEMORY_REF_COST);
5518
5519 format %{ "LWZ $dst, $mem \t// range" %}
5520 size(4);
5521 ins_encode( enc_lwz(dst, mem) );
5522 ins_pipe(pipe_class_memory);
5523 %}
5524
5525 // Load Compressed Pointer
5526 instruct loadN(iRegNdst dst, memory mem) %{
5527 match(Set dst (LoadN mem));
5528 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5529 ins_cost(MEMORY_REF_COST);
5530
5531 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5532 size(4);
5533 ins_encode( enc_lwz(dst, mem) );
5534 ins_pipe(pipe_class_memory);
5535 %}
5536
5537 // Load Compressed Pointer acquire.
5538 instruct loadN_ac(iRegNdst dst, memory mem) %{
5539 match(Set dst (LoadN mem));
5540 ins_cost(3*MEMORY_REF_COST);
5541
5542 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5543 "TWI $dst\n\t"
5544 "ISYNC" %}
5545 size(12);
5546 ins_encode( enc_lwz_ac(dst, mem) );
5547 ins_pipe(pipe_class_memory);
5548 %}
5549
5550 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5551 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5552 match(Set dst (DecodeN (LoadN mem)));
5553 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5554 ins_cost(MEMORY_REF_COST);
5555
5556 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5557 size(4);
5558 ins_encode( enc_lwz(dst, mem) );
5559 ins_pipe(pipe_class_memory);
5560 %}
5561
5562 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5563 match(Set dst (DecodeNKlass (LoadNKlass mem)));
5564 // SAPJVM GL 2014-05-21 Differs.
5565 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5566 _kids[0]->_leaf->as_Load()->is_unordered());
5567 ins_cost(MEMORY_REF_COST);
5568
5569 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5570 size(4);
5571 ins_encode( enc_lwz(dst, mem) );
5572 ins_pipe(pipe_class_memory);
5573 %}
5574
5575 // Load Pointer
5576 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5577 match(Set dst (LoadP mem));
5578 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5579 ins_cost(MEMORY_REF_COST);
5580
5581 format %{ "LD $dst, $mem \t// ptr" %}
5582 size(4);
5583 ins_encode( enc_ld(dst, mem) );
5584 ins_pipe(pipe_class_memory);
5585 %}
5586
5587 // Load Pointer acquire.
5588 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5589 match(Set dst (LoadP mem));
5590 ins_cost(3*MEMORY_REF_COST);
5591
5592 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5593 "TWI $dst\n\t"
5594 "ISYNC" %}
5595 size(12);
5596 ins_encode( enc_ld_ac(dst, mem) );
5597 ins_pipe(pipe_class_memory);
5598 %}
5599
5600 // LoadP + CastP2L
5601 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5602 match(Set dst (CastP2X (LoadP mem)));
5603 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5604 ins_cost(MEMORY_REF_COST);
5605
5606 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5607 size(4);
5608 ins_encode( enc_ld(dst, mem) );
5609 ins_pipe(pipe_class_memory);
5610 %}
5611
5612 // Load compressed klass pointer.
5613 instruct loadNKlass(iRegNdst dst, memory mem) %{
5614 match(Set dst (LoadNKlass mem));
5615 ins_cost(MEMORY_REF_COST);
5616
5617 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5618 size(4);
5619 ins_encode( enc_lwz(dst, mem) );
5620 ins_pipe(pipe_class_memory);
5621 %}
5622
5623 // Load Klass Pointer
5624 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5625 match(Set dst (LoadKlass mem));
5626 ins_cost(MEMORY_REF_COST);
5627
5628 format %{ "LD $dst, $mem \t// klass ptr" %}
5629 size(4);
5630 ins_encode( enc_ld(dst, mem) );
5631 ins_pipe(pipe_class_memory);
5632 %}
5633
5634 // Load Float
5635 instruct loadF(regF dst, memory mem) %{
5636 match(Set dst (LoadF mem));
5637 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5638 ins_cost(MEMORY_REF_COST);
5639
5640 format %{ "LFS $dst, $mem" %}
5641 size(4);
5642 ins_encode %{
5643 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5644 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5645 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5646 %}
5647 ins_pipe(pipe_class_memory);
5648 %}
5649
5650 // Load Float acquire.
5651 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5652 match(Set dst (LoadF mem));
5653 effect(TEMP cr0);
5654 ins_cost(3*MEMORY_REF_COST);
5655
5656 format %{ "LFS $dst, $mem \t// acquire\n\t"
5657 "FCMPU cr0, $dst, $dst\n\t"
5658 "BNE cr0, next\n"
5659 "next:\n\t"
5660 "ISYNC" %}
5661 size(16);
5662 ins_encode %{
5663 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5664 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5665 Label next;
5666 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5667 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5668 __ bne(CCR0, next);
5669 __ bind(next);
5670 __ isync();
5671 %}
5672 ins_pipe(pipe_class_memory);
5673 %}
5674
5675 // Load Double - aligned
5676 instruct loadD(regD dst, memory mem) %{
5677 match(Set dst (LoadD mem));
5678 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5679 ins_cost(MEMORY_REF_COST);
5680
5681 format %{ "LFD $dst, $mem" %}
5682 size(4);
5683 ins_encode( enc_lfd(dst, mem) );
5684 ins_pipe(pipe_class_memory);
5685 %}
5686
5687 // Load Double - aligned acquire.
5688 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5689 match(Set dst (LoadD mem));
5690 effect(TEMP cr0);
5691 ins_cost(3*MEMORY_REF_COST);
5692
5693 format %{ "LFD $dst, $mem \t// acquire\n\t"
5694 "FCMPU cr0, $dst, $dst\n\t"
5695 "BNE cr0, next\n"
5696 "next:\n\t"
5697 "ISYNC" %}
5698 size(16);
5699 ins_encode %{
5700 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5701 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5702 Label next;
5703 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5704 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5705 __ bne(CCR0, next);
5706 __ bind(next);
5707 __ isync();
5708 %}
5709 ins_pipe(pipe_class_memory);
5710 %}
5711
5712 // Load Double - UNaligned
5713 instruct loadD_unaligned(regD dst, memory mem) %{
5714 match(Set dst (LoadD_unaligned mem));
5715 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5716 ins_cost(MEMORY_REF_COST);
5717
5718 format %{ "LFD $dst, $mem" %}
5719 size(4);
5720 ins_encode( enc_lfd(dst, mem) );
5721 ins_pipe(pipe_class_memory);
5722 %}
5723
5724 //----------Constants--------------------------------------------------------
5725
5726 // Load MachConstantTableBase: add hi offset to global toc.
5727 // TODO: Handle hidden register r29 in bundler!
5728 instruct loadToc_hi(iRegLdst dst) %{
5729 effect(DEF dst);
5730 ins_cost(DEFAULT_COST);
5731
5732 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5733 size(4);
5734 ins_encode %{
5735 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5736 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5737 %}
5738 ins_pipe(pipe_class_default);
5739 %}
5740
5741 // Load MachConstantTableBase: add lo offset to global toc.
5742 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5743 effect(DEF dst, USE src);
5744 ins_cost(DEFAULT_COST);
5745
5746 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5747 size(4);
5748 ins_encode %{
5749 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5750 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5751 %}
5752 ins_pipe(pipe_class_default);
5753 %}
5754
5755 // Load 16-bit integer constant 0xssss????
5756 instruct loadConI16(iRegIdst dst, immI16 src) %{
5757 match(Set dst src);
5758
5759 format %{ "LI $dst, $src" %}
5760 size(4);
5761 ins_encode %{
5762 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5763 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5764 %}
5765 ins_pipe(pipe_class_default);
5766 %}
5767
5768 // Load integer constant 0x????0000
5769 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5770 match(Set dst src);
5771 ins_cost(DEFAULT_COST);
5772
5773 format %{ "LIS $dst, $src.hi" %}
5774 size(4);
5775 ins_encode %{
5776 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5777 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5778 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5779 %}
5780 ins_pipe(pipe_class_default);
5781 %}
5782
5783 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5784 // and sign extended), this adds the low 16 bits.
5785 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5786 // no match-rule, false predicate
5787 effect(DEF dst, USE src1, USE src2);
5788 predicate(false);
5789
5790 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5791 size(4);
5792 ins_encode %{
5793 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5794 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5795 %}
5796 ins_pipe(pipe_class_default);
5797 %}
5798
5799 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5800 match(Set dst src);
5801 ins_cost(DEFAULT_COST*2);
5802
5803 expand %{
5804 // Would like to use $src$$constant.
5805 immI16 srcLo %{ _opnds[1]->constant() %}
5806 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5807 immIhi16 srcHi %{ _opnds[1]->constant() %}
5808 iRegIdst tmpI;
5809 loadConIhi16(tmpI, srcHi);
5810 loadConI32_lo16(dst, tmpI, srcLo);
5811 %}
5812 %}
5813
5814 // No constant pool entries required.
5815 instruct loadConL16(iRegLdst dst, immL16 src) %{
5816 match(Set dst src);
5817
5818 format %{ "LI $dst, $src \t// long" %}
5819 size(4);
5820 ins_encode %{
5821 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5822 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5823 %}
5824 ins_pipe(pipe_class_default);
5825 %}
5826
5827 // Load long constant 0xssssssss????0000
5828 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5829 match(Set dst src);
5830 ins_cost(DEFAULT_COST);
5831
5832 format %{ "LIS $dst, $src.hi \t// long" %}
5833 size(4);
5834 ins_encode %{
5835 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5836 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5837 %}
5838 ins_pipe(pipe_class_default);
5839 %}
5840
5841 // To load a 32 bit constant: merge lower 16 bits into already loaded
5842 // high 16 bits.
5843 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5844 // no match-rule, false predicate
5845 effect(DEF dst, USE src1, USE src2);
5846 predicate(false);
5847
5848 format %{ "ORI $dst, $src1, $src2.lo" %}
5849 size(4);
5850 ins_encode %{
5851 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5852 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5853 %}
5854 ins_pipe(pipe_class_default);
5855 %}
5856
5857 // Load 32-bit long constant
5858 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5859 match(Set dst src);
5860 ins_cost(DEFAULT_COST*2);
5861
5862 expand %{
5863 // Would like to use $src$$constant.
5864 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5865 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5866 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5867 iRegLdst tmpL;
5868 loadConL32hi16(tmpL, srcHi);
5869 loadConL32_lo16(dst, tmpL, srcLo);
5870 %}
5871 %}
5872
5873 // Load long constant 0x????000000000000.
5874 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5875 match(Set dst src);
5876 ins_cost(DEFAULT_COST);
5877
5878 expand %{
5879 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5880 immI shift32 %{ 32 %}
5881 iRegLdst tmpL;
5882 loadConL32hi16(tmpL, srcHi);
5883 lshiftL_regL_immI(dst, tmpL, shift32);
5884 %}
5885 %}
5886
5887 // Expand node for constant pool load: small offset.
5888 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5889 effect(DEF dst, USE src, USE toc);
5890 ins_cost(MEMORY_REF_COST);
5891
5892 ins_num_consts(1);
5893 // Needed so that CallDynamicJavaDirect can compute the address of this
5894 // instruction for relocation.
5895 ins_field_cbuf_insts_offset(int);
5896
5897 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5898 size(4);
5899 ins_encode( enc_load_long_constL(dst, src, toc) );
5900 ins_pipe(pipe_class_memory);
5901 %}
5902
5903 // Expand node for constant pool load: large offset.
5904 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5905 effect(DEF dst, USE src, USE toc);
5906 predicate(false);
5907
5908 ins_num_consts(1);
5909 ins_field_const_toc_offset(int);
5910 // Needed so that CallDynamicJavaDirect can compute the address of this
5911 // instruction for relocation.
5912 ins_field_cbuf_insts_offset(int);
5913
5914 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5915 size(4);
5916 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5917 ins_pipe(pipe_class_default);
5918 %}
5919
5920 // Expand node for constant pool load: large offset.
5921 // No constant pool entries required.
5922 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5923 effect(DEF dst, USE src, USE base);
5924 predicate(false);
5925
5926 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5927
5928 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5929 size(4);
5930 ins_encode %{
5931 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5932 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5933 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5934 %}
5935 ins_pipe(pipe_class_memory);
5936 %}
5937
5938 // Load long constant from constant table. Expand in case of
5939 // offset > 16 bit is needed.
5940 // Adlc adds toc node MachConstantTableBase.
5941 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5942 match(Set dst src);
5943 ins_cost(MEMORY_REF_COST);
5944
5945 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5946 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5947 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5948 %}
5949
5950 // Load NULL as compressed oop.
5951 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5952 match(Set dst src);
5953 ins_cost(DEFAULT_COST);
5954
5955 format %{ "LI $dst, $src \t// compressed ptr" %}
5956 size(4);
5957 ins_encode %{
5958 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5959 __ li($dst$$Register, 0);
5960 %}
5961 ins_pipe(pipe_class_default);
5962 %}
5963
5964 // Load hi part of compressed oop constant.
5965 instruct loadConN_hi(iRegNdst dst, immN src) %{
5966 effect(DEF dst, USE src);
5967 ins_cost(DEFAULT_COST);
5968
5969 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5970 size(4);
5971 ins_encode %{
5972 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5973 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5974 %}
5975 ins_pipe(pipe_class_default);
5976 %}
5977
5978 // Add lo part of compressed oop constant to already loaded hi part.
5979 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5980 effect(DEF dst, USE src1, USE src2);
5981 ins_cost(DEFAULT_COST);
5982
5983 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5984 size(4);
5985 ins_encode %{
5986 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5987 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5988 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5989 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5990 __ relocate(rspec, 1);
5991 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5992 %}
5993 ins_pipe(pipe_class_default);
5994 %}
5995
5996 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5997 // leaving the upper 32 bits with sign-extension bits.
5998 // This clears these bits: dst = src & 0xFFFFFFFF.
5999 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6000 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6001 effect(DEF dst, USE src);
6002 predicate(false);
6003
6004 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6005 size(4);
6006 ins_encode %{
6007 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6008 __ clrldi($dst$$Register, $src$$Register, 0x20);
6009 %}
6010 ins_pipe(pipe_class_default);
6011 %}
6012
6013 // Optimize DecodeN for disjoint base.
6014 // Load base of compressed oops into a register
6015 instruct loadBase(iRegLdst dst) %{
6016 effect(DEF dst);
6017
6018 format %{ "LoadConst $dst, heapbase" %}
6019 ins_encode %{
6020 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6021 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6022 %}
6023 ins_pipe(pipe_class_default);
6024 %}
6025
6026 // Loading ConN must be postalloc expanded so that edges between
6027 // the nodes are safe. They may not interfere with a safepoint.
6028 // GL TODO: This needs three instructions: better put this into the constant pool.
6029 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6030 match(Set dst src);
6031 ins_cost(DEFAULT_COST*2);
6032
6033 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6034 postalloc_expand %{
6035 MachNode *m1 = new loadConN_hiNode();
6036 MachNode *m2 = new loadConN_loNode();
6037 MachNode *m3 = new clearMs32bNode();
6038 m1->add_req(NULL);
6039 m2->add_req(NULL, m1);
6040 m3->add_req(NULL, m2);
6041 m1->_opnds[0] = op_dst;
6042 m1->_opnds[1] = op_src;
6043 m2->_opnds[0] = op_dst;
6044 m2->_opnds[1] = op_dst;
6045 m2->_opnds[2] = op_src;
6046 m3->_opnds[0] = op_dst;
6047 m3->_opnds[1] = op_dst;
6048 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6049 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6050 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6051 nodes->push(m1);
6052 nodes->push(m2);
6053 nodes->push(m3);
6054 %}
6055 %}
6056
6057 // We have seen a safepoint between the hi and lo parts, and this node was handled
6058 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6059 // not a narrow oop.
6060 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6061 match(Set dst src);
6062 effect(DEF dst, USE src);
6063 ins_cost(DEFAULT_COST);
6064
6065 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6066 size(4);
6067 ins_encode %{
6068 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6069 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6070 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6071 %}
6072 ins_pipe(pipe_class_default);
6073 %}
6074
6075 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6076 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6077 match(Set dst src1);
6078 effect(TEMP src2);
6079 ins_cost(DEFAULT_COST);
6080
6081 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6082 size(4);
6083 ins_encode %{
6084 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6085 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6086 %}
6087 ins_pipe(pipe_class_default);
6088 %}
6089
6090 // This needs a match rule so that build_oop_map knows this is
6091 // not a narrow oop.
6092 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6093 match(Set dst src1);
6094 effect(TEMP src2);
6095 ins_cost(DEFAULT_COST);
6096
6097 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6098 size(4);
6099 ins_encode %{
6100 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6101 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6102 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6103 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6104 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6105
6106 __ relocate(rspec, 1);
6107 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6108 %}
6109 ins_pipe(pipe_class_default);
6110 %}
6111
6112 // Loading ConNKlass must be postalloc expanded so that edges between
6113 // the nodes are safe. They may not interfere with a safepoint.
6114 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6115 match(Set dst src);
6116 ins_cost(DEFAULT_COST*2);
6117
6118 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6119 postalloc_expand %{
6120 // Load high bits into register. Sign extended.
6121 MachNode *m1 = new loadConNKlass_hiNode();
6122 m1->add_req(NULL);
6123 m1->_opnds[0] = op_dst;
6124 m1->_opnds[1] = op_src;
6125 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6126 nodes->push(m1);
6127
6128 MachNode *m2 = m1;
6129 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6130 // Value might be 1-extended. Mask out these bits.
6131 m2 = new loadConNKlass_maskNode();
6132 m2->add_req(NULL, m1);
6133 m2->_opnds[0] = op_dst;
6134 m2->_opnds[1] = op_src;
6135 m2->_opnds[2] = op_dst;
6136 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6137 nodes->push(m2);
6138 }
6139
6140 MachNode *m3 = new loadConNKlass_loNode();
6141 m3->add_req(NULL, m2);
6142 m3->_opnds[0] = op_dst;
6143 m3->_opnds[1] = op_src;
6144 m3->_opnds[2] = op_dst;
6145 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6146 nodes->push(m3);
6147 %}
6148 %}
6149
6150 // 0x1 is used in object initialization (initial object header).
6151 // No constant pool entries required.
6152 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6153 match(Set dst src);
6154
6155 format %{ "LI $dst, $src \t// ptr" %}
6156 size(4);
6157 ins_encode %{
6158 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6159 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6160 %}
6161 ins_pipe(pipe_class_default);
6162 %}
6163
6164 // Expand node for constant pool load: small offset.
6165 // The match rule is needed to generate the correct bottom_type(),
6166 // however this node should never match. The use of predicate is not
6167 // possible since ADLC forbids predicates for chain rules. The higher
6168 // costs do not prevent matching in this case. For that reason the
6169 // operand immP_NM with predicate(false) is used.
6170 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6171 match(Set dst src);
6172 effect(TEMP toc);
6173
6174 ins_num_consts(1);
6175
6176 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6177 size(4);
6178 ins_encode( enc_load_long_constP(dst, src, toc) );
6179 ins_pipe(pipe_class_memory);
6180 %}
6181
6182 // Expand node for constant pool load: large offset.
6183 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6184 effect(DEF dst, USE src, USE toc);
6185 predicate(false);
6186
6187 ins_num_consts(1);
6188 ins_field_const_toc_offset(int);
6189
6190 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6191 size(4);
6192 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6193 ins_pipe(pipe_class_default);
6194 %}
6195
6196 // Expand node for constant pool load: large offset.
6197 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6198 match(Set dst src);
6199 effect(TEMP base);
6200
6201 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6202
6203 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6204 size(4);
6205 ins_encode %{
6206 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6207 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6208 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6209 %}
6210 ins_pipe(pipe_class_memory);
6211 %}
6212
6213 // Load pointer constant from constant table. Expand in case an
6214 // offset > 16 bit is needed.
6215 // Adlc adds toc node MachConstantTableBase.
6216 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6217 match(Set dst src);
6218 ins_cost(MEMORY_REF_COST);
6219
6220 // This rule does not use "expand" because then
6221 // the result type is not known to be an Oop. An ADLC
6222 // enhancement will be needed to make that work - not worth it!
6223
6224 // If this instruction rematerializes, it prolongs the live range
6225 // of the toc node, causing illegal graphs.
6226 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6227 ins_cannot_rematerialize(true);
6228
6229 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6230 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6231 %}
6232
6233 // Expand node for constant pool load: small offset.
6234 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6235 effect(DEF dst, USE src, USE toc);
6236 ins_cost(MEMORY_REF_COST);
6237
6238 ins_num_consts(1);
6239
6240 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6241 size(4);
6242 ins_encode %{
6243 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6244 address float_address = __ float_constant($src$$constant);
6245 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6246 %}
6247 ins_pipe(pipe_class_memory);
6248 %}
6249
6250 // Expand node for constant pool load: large offset.
6251 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6252 effect(DEF dst, USE src, USE toc);
6253 ins_cost(MEMORY_REF_COST);
6254
6255 ins_num_consts(1);
6256
6257 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6258 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6259 "ADDIS $toc, $toc, -offset_hi"%}
6260 size(12);
6261 ins_encode %{
6262 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6263 FloatRegister Rdst = $dst$$FloatRegister;
6264 Register Rtoc = $toc$$Register;
6265 address float_address = __ float_constant($src$$constant);
6266 int offset = __ offset_to_method_toc(float_address);
6267 int hi = (offset + (1<<15))>>16;
6268 int lo = offset - hi * (1<<16);
6269
6270 __ addis(Rtoc, Rtoc, hi);
6271 __ lfs(Rdst, lo, Rtoc);
6272 __ addis(Rtoc, Rtoc, -hi);
6273 %}
6274 ins_pipe(pipe_class_memory);
6275 %}
6276
6277 // Adlc adds toc node MachConstantTableBase.
6278 instruct loadConF_Ex(regF dst, immF src) %{
6279 match(Set dst src);
6280 ins_cost(MEMORY_REF_COST);
6281
6282 // See loadConP.
6283 ins_cannot_rematerialize(true);
6284
6285 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6286 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6287 %}
6288
6289 // Expand node for constant pool load: small offset.
6290 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6291 effect(DEF dst, USE src, USE toc);
6292 ins_cost(MEMORY_REF_COST);
6293
6294 ins_num_consts(1);
6295
6296 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6297 size(4);
6298 ins_encode %{
6299 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6300 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6301 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6302 %}
6303 ins_pipe(pipe_class_memory);
6304 %}
6305
6306 // Expand node for constant pool load: large offset.
6307 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6308 effect(DEF dst, USE src, USE toc);
6309 ins_cost(MEMORY_REF_COST);
6310
6311 ins_num_consts(1);
6312
6313 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6314 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6315 "ADDIS $toc, $toc, -offset_hi" %}
6316 size(12);
6317 ins_encode %{
6318 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6319 FloatRegister Rdst = $dst$$FloatRegister;
6320 Register Rtoc = $toc$$Register;
6321 address float_address = __ double_constant($src$$constant);
6322 int offset = __ offset_to_method_toc(float_address);
6323 int hi = (offset + (1<<15))>>16;
6324 int lo = offset - hi * (1<<16);
6325
6326 __ addis(Rtoc, Rtoc, hi);
6327 __ lfd(Rdst, lo, Rtoc);
6328 __ addis(Rtoc, Rtoc, -hi);
6329 %}
6330 ins_pipe(pipe_class_memory);
6331 %}
6332
6333 // Adlc adds toc node MachConstantTableBase.
6334 instruct loadConD_Ex(regD dst, immD src) %{
6335 match(Set dst src);
6336 ins_cost(MEMORY_REF_COST);
6337
6338 // See loadConP.
6339 ins_cannot_rematerialize(true);
6340
6341 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6342 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6343 %}
6344
6345 // Prefetch instructions.
6346 // Must be safe to execute with invalid address (cannot fault).
6347
6348 // Special prefetch versions which use the dcbz instruction.
6349 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6350 match(PrefetchAllocation (AddP mem src));
6351 predicate(AllocatePrefetchStyle == 3);
6352 ins_cost(MEMORY_REF_COST);
6353
6354 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6355 size(4);
6356 ins_encode %{
6357 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6358 __ dcbz($src$$Register, $mem$$base$$Register);
6359 %}
6360 ins_pipe(pipe_class_memory);
6361 %}
6362
6363 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6364 match(PrefetchAllocation mem);
6365 predicate(AllocatePrefetchStyle == 3);
6366 ins_cost(MEMORY_REF_COST);
6367
6368 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6369 size(4);
6370 ins_encode %{
6371 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6372 __ dcbz($mem$$base$$Register);
6373 %}
6374 ins_pipe(pipe_class_memory);
6375 %}
6376
6377 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6378 match(PrefetchAllocation (AddP mem src));
6379 predicate(AllocatePrefetchStyle != 3);
6380 ins_cost(MEMORY_REF_COST);
6381
6382 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6383 size(4);
6384 ins_encode %{
6385 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6386 __ dcbtst($src$$Register, $mem$$base$$Register);
6387 %}
6388 ins_pipe(pipe_class_memory);
6389 %}
6390
6391 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6392 match(PrefetchAllocation mem);
6393 predicate(AllocatePrefetchStyle != 3);
6394 ins_cost(MEMORY_REF_COST);
6395
6396 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6397 size(4);
6398 ins_encode %{
6399 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6400 __ dcbtst($mem$$base$$Register);
6401 %}
6402 ins_pipe(pipe_class_memory);
6403 %}
6404
6405 //----------Store Instructions-------------------------------------------------
6406
6407 // Store Byte
6408 instruct storeB(memory mem, iRegIsrc src) %{
6409 match(Set mem (StoreB mem src));
6410 ins_cost(MEMORY_REF_COST);
6411
6412 format %{ "STB $src, $mem \t// byte" %}
6413 size(4);
6414 ins_encode %{
6415 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6416 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6417 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6418 %}
6419 ins_pipe(pipe_class_memory);
6420 %}
6421
6422 // Store Char/Short
6423 instruct storeC(memory mem, iRegIsrc src) %{
6424 match(Set mem (StoreC mem src));
6425 ins_cost(MEMORY_REF_COST);
6426
6427 format %{ "STH $src, $mem \t// short" %}
6428 size(4);
6429 ins_encode %{
6430 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6431 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6432 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6433 %}
6434 ins_pipe(pipe_class_memory);
6435 %}
6436
6437 // Store Integer
6438 instruct storeI(memory mem, iRegIsrc src) %{
6439 match(Set mem (StoreI mem src));
6440 ins_cost(MEMORY_REF_COST);
6441
6442 format %{ "STW $src, $mem" %}
6443 size(4);
6444 ins_encode( enc_stw(src, mem) );
6445 ins_pipe(pipe_class_memory);
6446 %}
6447
6448 // ConvL2I + StoreI.
6449 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6450 match(Set mem (StoreI mem (ConvL2I src)));
6451 ins_cost(MEMORY_REF_COST);
6452
6453 format %{ "STW l2i($src), $mem" %}
6454 size(4);
6455 ins_encode( enc_stw(src, mem) );
6456 ins_pipe(pipe_class_memory);
6457 %}
6458
6459 // Store Long
6460 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6461 match(Set mem (StoreL mem src));
6462 ins_cost(MEMORY_REF_COST);
6463
6464 format %{ "STD $src, $mem \t// long" %}
6465 size(4);
6466 ins_encode( enc_std(src, mem) );
6467 ins_pipe(pipe_class_memory);
6468 %}
6469
6470 // Store super word nodes.
6471
6472 // Store Aligned Packed Byte long register to memory
6473 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6474 predicate(n->as_StoreVector()->memory_size() == 8);
6475 match(Set mem (StoreVector mem src));
6476 ins_cost(MEMORY_REF_COST);
6477
6478 format %{ "STD $mem, $src \t// packed8B" %}
6479 size(4);
6480 ins_encode( enc_std(src, mem) );
6481 ins_pipe(pipe_class_memory);
6482 %}
6483
6484 // Store Compressed Oop
6485 instruct storeN(memory dst, iRegN_P2N src) %{
6486 match(Set dst (StoreN dst src));
6487 ins_cost(MEMORY_REF_COST);
6488
6489 format %{ "STW $src, $dst \t// compressed oop" %}
6490 size(4);
6491 ins_encode( enc_stw(src, dst) );
6492 ins_pipe(pipe_class_memory);
6493 %}
6494
6495 // Store Compressed KLass
6496 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6497 match(Set dst (StoreNKlass dst src));
6498 ins_cost(MEMORY_REF_COST);
6499
6500 format %{ "STW $src, $dst \t// compressed klass" %}
6501 size(4);
6502 ins_encode( enc_stw(src, dst) );
6503 ins_pipe(pipe_class_memory);
6504 %}
6505
6506 // Store Pointer
6507 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6508 match(Set dst (StoreP dst src));
6509 ins_cost(MEMORY_REF_COST);
6510
6511 format %{ "STD $src, $dst \t// ptr" %}
6512 size(4);
6513 ins_encode( enc_std(src, dst) );
6514 ins_pipe(pipe_class_memory);
6515 %}
6516
6517 // Store Float
6518 instruct storeF(memory mem, regF src) %{
6519 match(Set mem (StoreF mem src));
6520 ins_cost(MEMORY_REF_COST);
6521
6522 format %{ "STFS $src, $mem" %}
6523 size(4);
6524 ins_encode( enc_stfs(src, mem) );
6525 ins_pipe(pipe_class_memory);
6526 %}
6527
6528 // Store Double
6529 instruct storeD(memory mem, regD src) %{
6530 match(Set mem (StoreD mem src));
6531 ins_cost(MEMORY_REF_COST);
6532
6533 format %{ "STFD $src, $mem" %}
6534 size(4);
6535 ins_encode( enc_stfd(src, mem) );
6536 ins_pipe(pipe_class_memory);
6537 %}
6538
6539 //----------Store Instructions With Zeros--------------------------------------
6540
6541 // Card-mark for CMS garbage collection.
6542 // This cardmark does an optimization so that it must not always
6543 // do a releasing store. For this, it gets the address of
6544 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6545 // (Using releaseFieldAddr in the match rule is a hack.)
6546 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6547 match(Set mem (StoreCM mem releaseFieldAddr));
6548 effect(TEMP crx);
6549 predicate(false);
6550 ins_cost(MEMORY_REF_COST);
6551
6552 // See loadConP.
6553 ins_cannot_rematerialize(true);
6554
6555 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6556 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6557 ins_pipe(pipe_class_memory);
6558 %}
6559
6560 // Card-mark for CMS garbage collection.
6561 // This cardmark does an optimization so that it must not always
6562 // do a releasing store. For this, it needs the constant address of
6563 // CMSCollectorCardTableModRefBSExt::_requires_release.
6564 // This constant address is split off here by expand so we can use
6565 // adlc / matcher functionality to load it from the constant section.
6566 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6567 match(Set mem (StoreCM mem zero));
6568 predicate(UseConcMarkSweepGC);
6569
6570 expand %{
6571 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6572 iRegLdst releaseFieldAddress;
6573 flagsReg crx;
6574 loadConL_Ex(releaseFieldAddress, baseImm);
6575 storeCM_CMS(mem, releaseFieldAddress, crx);
6576 %}
6577 %}
6578
6579 instruct storeCM_G1(memory mem, immI_0 zero) %{
6580 match(Set mem (StoreCM mem zero));
6581 predicate(UseG1GC);
6582 ins_cost(MEMORY_REF_COST);
6583
6584 ins_cannot_rematerialize(true);
6585
6586 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6587 size(8);
6588 ins_encode %{
6589 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6590 __ li(R0, 0);
6591 //__ release(); // G1: oops are allowed to get visible after dirty marking
6592 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6593 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6594 %}
6595 ins_pipe(pipe_class_memory);
6596 %}
6597
6598 // Convert oop pointer into compressed form.
6599
6600 // Nodes for postalloc expand.
6601
6602 // Shift node for expand.
6603 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6604 // The match rule is needed to make it a 'MachTypeNode'!
6605 match(Set dst (EncodeP src));
6606 predicate(false);
6607
6608 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6609 size(4);
6610 ins_encode %{
6611 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6612 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6613 %}
6614 ins_pipe(pipe_class_default);
6615 %}
6616
6617 // Add node for expand.
6618 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6619 // The match rule is needed to make it a 'MachTypeNode'!
6620 match(Set dst (EncodeP src));
6621 predicate(false);
6622
6623 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6624 ins_encode %{
6625 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6626 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6627 %}
6628 ins_pipe(pipe_class_default);
6629 %}
6630
6631 // Conditional sub base.
6632 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6633 // The match rule is needed to make it a 'MachTypeNode'!
6634 match(Set dst (EncodeP (Binary crx src1)));
6635 predicate(false);
6636
6637 format %{ "BEQ $crx, done\n\t"
6638 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6639 "done:" %}
6640 ins_encode %{
6641 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6642 Label done;
6643 __ beq($crx$$CondRegister, done);
6644 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6645 __ bind(done);
6646 %}
6647 ins_pipe(pipe_class_default);
6648 %}
6649
6650 // Power 7 can use isel instruction
6651 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6652 // The match rule is needed to make it a 'MachTypeNode'!
6653 match(Set dst (EncodeP (Binary crx src1)));
6654 predicate(false);
6655
6656 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6657 size(4);
6658 ins_encode %{
6659 // This is a Power7 instruction for which no machine description exists.
6660 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6661 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6662 %}
6663 ins_pipe(pipe_class_default);
6664 %}
6665
6666 // Disjoint narrow oop base.
6667 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6668 match(Set dst (EncodeP src));
6669 predicate(Universe::narrow_oop_base_disjoint());
6670
6671 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6672 size(4);
6673 ins_encode %{
6674 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6675 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6676 %}
6677 ins_pipe(pipe_class_default);
6678 %}
6679
6680 // shift != 0, base != 0
6681 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6682 match(Set dst (EncodeP src));
6683 effect(TEMP crx);
6684 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6685 Universe::narrow_oop_shift() != 0 &&
6686 Universe::narrow_oop_base_overlaps());
6687
6688 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6689 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6690 %}
6691
6692 // shift != 0, base != 0
6693 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6694 match(Set dst (EncodeP src));
6695 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6696 Universe::narrow_oop_shift() != 0 &&
6697 Universe::narrow_oop_base_overlaps());
6698
6699 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6700 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6701 %}
6702
6703 // shift != 0, base == 0
6704 // TODO: This is the same as encodeP_shift. Merge!
6705 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6706 match(Set dst (EncodeP src));
6707 predicate(Universe::narrow_oop_shift() != 0 &&
6708 Universe::narrow_oop_base() ==0);
6709
6710 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6711 size(4);
6712 ins_encode %{
6713 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6714 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6715 %}
6716 ins_pipe(pipe_class_default);
6717 %}
6718
6719 // Compressed OOPs with narrow_oop_shift == 0.
6720 // shift == 0, base == 0
6721 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6722 match(Set dst (EncodeP src));
6723 predicate(Universe::narrow_oop_shift() == 0);
6724
6725 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6726 // variable size, 0 or 4.
6727 ins_encode %{
6728 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6729 __ mr_if_needed($dst$$Register, $src$$Register);
6730 %}
6731 ins_pipe(pipe_class_default);
6732 %}
6733
6734 // Decode nodes.
6735
6736 // Shift node for expand.
6737 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6738 // The match rule is needed to make it a 'MachTypeNode'!
6739 match(Set dst (DecodeN src));
6740 predicate(false);
6741
6742 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6743 size(4);
6744 ins_encode %{
6745 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6746 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6747 %}
6748 ins_pipe(pipe_class_default);
6749 %}
6750
6751 // Add node for expand.
6752 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6753 // The match rule is needed to make it a 'MachTypeNode'!
6754 match(Set dst (DecodeN src));
6755 predicate(false);
6756
6757 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %}
6758 ins_encode %{
6759 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6760 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6761 %}
6762 ins_pipe(pipe_class_default);
6763 %}
6764
6765 // conditianal add base for expand
6766 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6767 // The match rule is needed to make it a 'MachTypeNode'!
6768 // NOTICE that the rule is nonsense - we just have to make sure that:
6769 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6770 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6771 match(Set dst (DecodeN (Binary crx src)));
6772 predicate(false);
6773
6774 format %{ "BEQ $crx, done\n\t"
6775 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6776 "done:" %}
6777 ins_encode %{
6778 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6779 Label done;
6780 __ beq($crx$$CondRegister, done);
6781 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6782 __ bind(done);
6783 %}
6784 ins_pipe(pipe_class_default);
6785 %}
6786
6787 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6788 // The match rule is needed to make it a 'MachTypeNode'!
6789 // NOTICE that the rule is nonsense - we just have to make sure that:
6790 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6791 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6792 match(Set dst (DecodeN (Binary crx src1)));
6793 predicate(false);
6794
6795 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6796 size(4);
6797 ins_encode %{
6798 // This is a Power7 instruction for which no machine description exists.
6799 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6800 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6801 %}
6802 ins_pipe(pipe_class_default);
6803 %}
6804
6805 // shift != 0, base != 0
6806 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6807 match(Set dst (DecodeN src));
6808 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6809 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6810 Universe::narrow_oop_shift() != 0 &&
6811 Universe::narrow_oop_base() != 0);
6812 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6813 effect(TEMP crx);
6814
6815 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6816 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6817 %}
6818
6819 // shift != 0, base == 0
6820 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6821 match(Set dst (DecodeN src));
6822 predicate(Universe::narrow_oop_shift() != 0 &&
6823 Universe::narrow_oop_base() == 0);
6824
6825 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6826 size(4);
6827 ins_encode %{
6828 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6829 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6830 %}
6831 ins_pipe(pipe_class_default);
6832 %}
6833
6834 // Optimize DecodeN for disjoint base.
6835 // Shift narrow oop and or it into register that already contains the heap base.
6836 // Base == dst must hold, and is assured by construction in postaloc_expand.
6837 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6838 match(Set dst (DecodeN src));
6839 effect(TEMP base);
6840 predicate(false);
6841
6842 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6843 size(4);
6844 ins_encode %{
6845 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6846 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6847 %}
6848 ins_pipe(pipe_class_default);
6849 %}
6850
6851 // Optimize DecodeN for disjoint base.
6852 // This node requires only one cycle on the critical path.
6853 // We must postalloc_expand as we can not express use_def effects where
6854 // the used register is L and the def'ed register P.
6855 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6856 match(Set dst (DecodeN src));
6857 effect(TEMP_DEF dst);
6858 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6859 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6860 Universe::narrow_oop_base_disjoint());
6861 ins_cost(DEFAULT_COST);
6862
6863 format %{ "MOV $dst, heapbase \t\n"
6864 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6865 postalloc_expand %{
6866 loadBaseNode *n1 = new loadBaseNode();
6867 n1->add_req(NULL);
6868 n1->_opnds[0] = op_dst;
6869
6870 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6871 n2->add_req(n_region, n_src, n1);
6872 n2->_opnds[0] = op_dst;
6873 n2->_opnds[1] = op_src;
6874 n2->_opnds[2] = op_dst;
6875 n2->_bottom_type = _bottom_type;
6876
6877 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6878 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6879
6880 nodes->push(n1);
6881 nodes->push(n2);
6882 %}
6883 %}
6884
6885 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6886 match(Set dst (DecodeN src));
6887 effect(TEMP_DEF dst, TEMP crx);
6888 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6889 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6890 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6891 ins_cost(3 * DEFAULT_COST);
6892
6893 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %}
6894 postalloc_expand %{
6895 loadBaseNode *n1 = new loadBaseNode();
6896 n1->add_req(NULL);
6897 n1->_opnds[0] = op_dst;
6898
6899 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
6900 n_compare->add_req(n_region, n_src);
6901 n_compare->_opnds[0] = op_crx;
6902 n_compare->_opnds[1] = op_src;
6903 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6904
6905 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6906 n2->add_req(n_region, n_src, n1);
6907 n2->_opnds[0] = op_dst;
6908 n2->_opnds[1] = op_src;
6909 n2->_opnds[2] = op_dst;
6910 n2->_bottom_type = _bottom_type;
6911
6912 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6913 n_cond_set->add_req(n_region, n_compare, n2);
6914 n_cond_set->_opnds[0] = op_dst;
6915 n_cond_set->_opnds[1] = op_crx;
6916 n_cond_set->_opnds[2] = op_dst;
6917 n_cond_set->_bottom_type = _bottom_type;
6918
6919 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6920 ra_->set_oop(n_cond_set, true);
6921
6922 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6923 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6924 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6925 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6926
6927 nodes->push(n1);
6928 nodes->push(n_compare);
6929 nodes->push(n2);
6930 nodes->push(n_cond_set);
6931 %}
6932 %}
6933
6934 // src != 0, shift != 0, base != 0
6935 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6936 match(Set dst (DecodeN src));
6937 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6938 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6939 Universe::narrow_oop_shift() != 0 &&
6940 Universe::narrow_oop_base() != 0);
6941 ins_cost(2 * DEFAULT_COST);
6942
6943 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6944 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6945 %}
6946
6947 // Compressed OOPs with narrow_oop_shift == 0.
6948 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6949 match(Set dst (DecodeN src));
6950 predicate(Universe::narrow_oop_shift() == 0);
6951 ins_cost(DEFAULT_COST);
6952
6953 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6954 // variable size, 0 or 4.
6955 ins_encode %{
6956 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6957 __ mr_if_needed($dst$$Register, $src$$Register);
6958 %}
6959 ins_pipe(pipe_class_default);
6960 %}
6961
6962 // Convert compressed oop into int for vectors alignment masking.
6963 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6964 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6965 predicate(Universe::narrow_oop_shift() == 0);
6966 ins_cost(DEFAULT_COST);
6967
6968 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6969 // variable size, 0 or 4.
6970 ins_encode %{
6971 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6972 __ mr_if_needed($dst$$Register, $src$$Register);
6973 %}
6974 ins_pipe(pipe_class_default);
6975 %}
6976
6977 // Convert klass pointer into compressed form.
6978
6979 // Nodes for postalloc expand.
6980
6981 // Shift node for expand.
6982 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6983 // The match rule is needed to make it a 'MachTypeNode'!
6984 match(Set dst (EncodePKlass src));
6985 predicate(false);
6986
6987 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6988 size(4);
6989 ins_encode %{
6990 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6991 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6992 %}
6993 ins_pipe(pipe_class_default);
6994 %}
6995
6996 // Add node for expand.
6997 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6998 // The match rule is needed to make it a 'MachTypeNode'!
6999 match(Set dst (EncodePKlass (Binary base src)));
7000 predicate(false);
7001
7002 format %{ "SUB $dst, $base, $src \t// encode" %}
7003 size(4);
7004 ins_encode %{
7005 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7006 __ subf($dst$$Register, $base$$Register, $src$$Register);
7007 %}
7008 ins_pipe(pipe_class_default);
7009 %}
7010
7011 // Disjoint narrow oop base.
7012 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7013 match(Set dst (EncodePKlass src));
7014 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7015
7016 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
7017 size(4);
7018 ins_encode %{
7019 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7020 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7021 %}
7022 ins_pipe(pipe_class_default);
7023 %}
7024
7025 // shift != 0, base != 0
7026 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7027 match(Set dst (EncodePKlass (Binary base src)));
7028 predicate(false);
7029
7030 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7031 postalloc_expand %{
7032 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7033 n1->add_req(n_region, n_base, n_src);
7034 n1->_opnds[0] = op_dst;
7035 n1->_opnds[1] = op_base;
7036 n1->_opnds[2] = op_src;
7037 n1->_bottom_type = _bottom_type;
7038
7039 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7040 n2->add_req(n_region, n1);
7041 n2->_opnds[0] = op_dst;
7042 n2->_opnds[1] = op_dst;
7043 n2->_bottom_type = _bottom_type;
7044 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7045 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7046
7047 nodes->push(n1);
7048 nodes->push(n2);
7049 %}
7050 %}
7051
7052 // shift != 0, base != 0
7053 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7054 match(Set dst (EncodePKlass src));
7055 //predicate(Universe::narrow_klass_shift() != 0 &&
7056 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7057
7058 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7059 ins_cost(DEFAULT_COST*2); // Don't count constant.
7060 expand %{
7061 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7062 iRegLdst base;
7063 loadConL_Ex(base, baseImm);
7064 encodePKlass_not_null_Ex(dst, base, src);
7065 %}
7066 %}
7067
7068 // Decode nodes.
7069
7070 // Shift node for expand.
7071 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7072 // The match rule is needed to make it a 'MachTypeNode'!
7073 match(Set dst (DecodeNKlass src));
7074 predicate(false);
7075
7076 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7077 size(4);
7078 ins_encode %{
7079 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7080 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7081 %}
7082 ins_pipe(pipe_class_default);
7083 %}
7084
7085 // Add node for expand.
7086
7087 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7088 // The match rule is needed to make it a 'MachTypeNode'!
7089 match(Set dst (DecodeNKlass (Binary base src)));
7090 predicate(false);
7091
7092 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7093 size(4);
7094 ins_encode %{
7095 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7096 __ add($dst$$Register, $base$$Register, $src$$Register);
7097 %}
7098 ins_pipe(pipe_class_default);
7099 %}
7100
7101 // src != 0, shift != 0, base != 0
7102 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7103 match(Set dst (DecodeNKlass (Binary base src)));
7104 //effect(kill src); // We need a register for the immediate result after shifting.
7105 predicate(false);
7106
7107 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7108 postalloc_expand %{
7109 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7110 n1->add_req(n_region, n_base, n_src);
7111 n1->_opnds[0] = op_dst;
7112 n1->_opnds[1] = op_base;
7113 n1->_opnds[2] = op_src;
7114 n1->_bottom_type = _bottom_type;
7115
7116 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7117 n2->add_req(n_region, n1);
7118 n2->_opnds[0] = op_dst;
7119 n2->_opnds[1] = op_dst;
7120 n2->_bottom_type = _bottom_type;
7121
7122 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7123 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7124
7125 nodes->push(n1);
7126 nodes->push(n2);
7127 %}
7128 %}
7129
7130 // src != 0, shift != 0, base != 0
7131 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7132 match(Set dst (DecodeNKlass src));
7133 // predicate(Universe::narrow_klass_shift() != 0 &&
7134 // Universe::narrow_klass_base() != 0);
7135
7136 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7137
7138 ins_cost(DEFAULT_COST*2); // Don't count constant.
7139 expand %{
7140 // We add first, then we shift. Like this, we can get along with one register less.
7141 // But we have to load the base pre-shifted.
7142 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7143 iRegLdst base;
7144 loadConL_Ex(base, baseImm);
7145 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7146 %}
7147 %}
7148
7149 //----------MemBar Instructions-----------------------------------------------
7150 // Memory barrier flavors
7151
7152 instruct membar_acquire() %{
7153 match(LoadFence);
7154 ins_cost(4*MEMORY_REF_COST);
7155
7156 format %{ "MEMBAR-acquire" %}
7157 size(4);
7158 ins_encode %{
7159 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7160 __ acquire();
7161 %}
7162 ins_pipe(pipe_class_default);
7163 %}
7164
7165 instruct unnecessary_membar_acquire() %{
7166 match(MemBarAcquire);
7167 ins_cost(0);
7168
7169 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7170 size(0);
7171 ins_encode( /*empty*/ );
7172 ins_pipe(pipe_class_default);
7173 %}
7174
7175 instruct membar_acquire_lock() %{
7176 match(MemBarAcquireLock);
7177 ins_cost(0);
7178
7179 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7180 size(0);
7181 ins_encode( /*empty*/ );
7182 ins_pipe(pipe_class_default);
7183 %}
7184
7185 instruct membar_release() %{
7186 match(MemBarRelease);
7187 match(StoreFence);
7188 ins_cost(4*MEMORY_REF_COST);
7189
7190 format %{ "MEMBAR-release" %}
7191 size(4);
7192 ins_encode %{
7193 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7194 __ release();
7195 %}
7196 ins_pipe(pipe_class_default);
7197 %}
7198
7199 instruct membar_storestore() %{
7200 match(MemBarStoreStore);
7201 ins_cost(4*MEMORY_REF_COST);
7202
7203 format %{ "MEMBAR-store-store" %}
7204 size(4);
7205 ins_encode %{
7206 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7207 __ membar(Assembler::StoreStore);
7208 %}
7209 ins_pipe(pipe_class_default);
7210 %}
7211
7212 instruct membar_release_lock() %{
7213 match(MemBarReleaseLock);
7214 ins_cost(0);
7215
7216 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7217 size(0);
7218 ins_encode( /*empty*/ );
7219 ins_pipe(pipe_class_default);
7220 %}
7221
7222 instruct membar_volatile() %{
7223 match(MemBarVolatile);
7224 ins_cost(4*MEMORY_REF_COST);
7225
7226 format %{ "MEMBAR-volatile" %}
7227 size(4);
7228 ins_encode %{
7229 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7230 __ fence();
7231 %}
7232 ins_pipe(pipe_class_default);
7233 %}
7234
7235 // This optimization is wrong on PPC. The following pattern is not supported:
7236 // MemBarVolatile
7237 // ^ ^
7238 // | |
7239 // CtrlProj MemProj
7240 // ^ ^
7241 // | |
7242 // | Load
7243 // |
7244 // MemBarVolatile
7245 //
7246 // The first MemBarVolatile could get optimized out! According to
7247 // Vladimir, this pattern can not occur on Oracle platforms.
7248 // However, it does occur on PPC64 (because of membars in
7249 // inline_unsafe_load_store).
7250 //
7251 // Add this node again if we found a good solution for inline_unsafe_load_store().
7252 // Don't forget to look at the implementation of post_store_load_barrier again,
7253 // we did other fixes in that method.
7254 //instruct unnecessary_membar_volatile() %{
7255 // match(MemBarVolatile);
7256 // predicate(Matcher::post_store_load_barrier(n));
7257 // ins_cost(0);
7258 //
7259 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7260 // size(0);
7261 // ins_encode( /*empty*/ );
7262 // ins_pipe(pipe_class_default);
7263 //%}
7264
7265 instruct membar_CPUOrder() %{
7266 match(MemBarCPUOrder);
7267 ins_cost(0);
7268
7269 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7270 size(0);
7271 ins_encode( /*empty*/ );
7272 ins_pipe(pipe_class_default);
7273 %}
7274
7275 //----------Conditional Move---------------------------------------------------
7276
7277 // Cmove using isel.
7278 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7279 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7280 predicate(VM_Version::has_isel());
7281 ins_cost(DEFAULT_COST);
7282
7283 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7284 size(4);
7285 ins_encode %{
7286 // This is a Power7 instruction for which no machine description
7287 // exists. Anyways, the scheduler should be off on Power7.
7288 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7289 int cc = $cmp$$cmpcode;
7290 __ isel($dst$$Register, $crx$$CondRegister,
7291 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7292 %}
7293 ins_pipe(pipe_class_default);
7294 %}
7295
7296 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7297 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7298 predicate(!VM_Version::has_isel());
7299 ins_cost(DEFAULT_COST+BRANCH_COST);
7300
7301 ins_variable_size_depending_on_alignment(true);
7302
7303 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7304 // Worst case is branch + move + stop, no stop without scheduler
7305 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7306 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7307 ins_pipe(pipe_class_default);
7308 %}
7309
7310 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7311 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7312 ins_cost(DEFAULT_COST+BRANCH_COST);
7313
7314 ins_variable_size_depending_on_alignment(true);
7315
7316 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7317 // Worst case is branch + move + stop, no stop without scheduler
7318 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7319 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7320 ins_pipe(pipe_class_default);
7321 %}
7322
7323 // Cmove using isel.
7324 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7325 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7326 predicate(VM_Version::has_isel());
7327 ins_cost(DEFAULT_COST);
7328
7329 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7330 size(4);
7331 ins_encode %{
7332 // This is a Power7 instruction for which no machine description
7333 // exists. Anyways, the scheduler should be off on Power7.
7334 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7335 int cc = $cmp$$cmpcode;
7336 __ isel($dst$$Register, $crx$$CondRegister,
7337 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7338 %}
7339 ins_pipe(pipe_class_default);
7340 %}
7341
7342 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7343 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7344 predicate(!VM_Version::has_isel());
7345 ins_cost(DEFAULT_COST+BRANCH_COST);
7346
7347 ins_variable_size_depending_on_alignment(true);
7348
7349 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7350 // Worst case is branch + move + stop, no stop without scheduler.
7351 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7352 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7353 ins_pipe(pipe_class_default);
7354 %}
7355
7356 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7357 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7358 ins_cost(DEFAULT_COST+BRANCH_COST);
7359
7360 ins_variable_size_depending_on_alignment(true);
7361
7362 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7363 // Worst case is branch + move + stop, no stop without scheduler.
7364 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7365 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7366 ins_pipe(pipe_class_default);
7367 %}
7368
7369 // Cmove using isel.
7370 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7371 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7372 predicate(VM_Version::has_isel());
7373 ins_cost(DEFAULT_COST);
7374
7375 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7376 size(4);
7377 ins_encode %{
7378 // This is a Power7 instruction for which no machine description
7379 // exists. Anyways, the scheduler should be off on Power7.
7380 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7381 int cc = $cmp$$cmpcode;
7382 __ isel($dst$$Register, $crx$$CondRegister,
7383 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7384 %}
7385 ins_pipe(pipe_class_default);
7386 %}
7387
7388 // Conditional move for RegN. Only cmov(reg, reg).
7389 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7390 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7391 predicate(!VM_Version::has_isel());
7392 ins_cost(DEFAULT_COST+BRANCH_COST);
7393
7394 ins_variable_size_depending_on_alignment(true);
7395
7396 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7397 // Worst case is branch + move + stop, no stop without scheduler.
7398 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7399 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7400 ins_pipe(pipe_class_default);
7401 %}
7402
7403 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7404 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7405 ins_cost(DEFAULT_COST+BRANCH_COST);
7406
7407 ins_variable_size_depending_on_alignment(true);
7408
7409 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7410 // Worst case is branch + move + stop, no stop without scheduler.
7411 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7412 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7413 ins_pipe(pipe_class_default);
7414 %}
7415
7416 // Cmove using isel.
7417 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7418 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7419 predicate(VM_Version::has_isel());
7420 ins_cost(DEFAULT_COST);
7421
7422 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7423 size(4);
7424 ins_encode %{
7425 // This is a Power7 instruction for which no machine description
7426 // exists. Anyways, the scheduler should be off on Power7.
7427 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7428 int cc = $cmp$$cmpcode;
7429 __ isel($dst$$Register, $crx$$CondRegister,
7430 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7431 %}
7432 ins_pipe(pipe_class_default);
7433 %}
7434
7435 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7436 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7437 predicate(!VM_Version::has_isel());
7438 ins_cost(DEFAULT_COST+BRANCH_COST);
7439
7440 ins_variable_size_depending_on_alignment(true);
7441
7442 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7443 // Worst case is branch + move + stop, no stop without scheduler.
7444 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7445 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7446 ins_pipe(pipe_class_default);
7447 %}
7448
7449 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7450 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7451 ins_cost(DEFAULT_COST+BRANCH_COST);
7452
7453 ins_variable_size_depending_on_alignment(true);
7454
7455 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7456 // Worst case is branch + move + stop, no stop without scheduler.
7457 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7458 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7459 ins_pipe(pipe_class_default);
7460 %}
7461
7462 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7463 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7464 ins_cost(DEFAULT_COST+BRANCH_COST);
7465
7466 ins_variable_size_depending_on_alignment(true);
7467
7468 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7469 // Worst case is branch + move + stop, no stop without scheduler.
7470 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7471 ins_encode %{
7472 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7473 Label done;
7474 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7475 // Branch if not (cmp crx).
7476 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7477 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7478 // TODO PPC port __ endgroup_if_needed(_size == 12);
7479 __ bind(done);
7480 %}
7481 ins_pipe(pipe_class_default);
7482 %}
7483
7484 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7485 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7486 ins_cost(DEFAULT_COST+BRANCH_COST);
7487
7488 ins_variable_size_depending_on_alignment(true);
7489
7490 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7491 // Worst case is branch + move + stop, no stop without scheduler.
7492 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7493 ins_encode %{
7494 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7495 Label done;
7496 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7497 // Branch if not (cmp crx).
7498 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7499 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7500 // TODO PPC port __ endgroup_if_needed(_size == 12);
7501 __ bind(done);
7502 %}
7503 ins_pipe(pipe_class_default);
7504 %}
7505
7506 //----------Conditional_store--------------------------------------------------
7507 // Conditional-store of the updated heap-top.
7508 // Used during allocation of the shared heap.
7509 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7510
7511 // As compareAndSwapL, but return flag register instead of boolean value in
7512 // int register.
7513 // Used by sun/misc/AtomicLongCSImpl.java.
7514 // Mem_ptr must be a memory operand, else this node does not get
7515 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7516 // can be rematerialized which leads to errors.
7517 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7518 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7519 effect(TEMP cr0);
7520 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7521 ins_encode %{
7522 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7523 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7524 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7525 noreg, NULL, true);
7526 %}
7527 ins_pipe(pipe_class_default);
7528 %}
7529
7530 // As compareAndSwapP, but return flag register instead of boolean value in
7531 // int register.
7532 // This instruction is matched if UseTLAB is off.
7533 // Mem_ptr must be a memory operand, else this node does not get
7534 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7535 // can be rematerialized which leads to errors.
7536 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7537 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7538 ins_cost(2*MEMORY_REF_COST);
7539
7540 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7541 ins_encode %{
7542 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7543 __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7544 %}
7545 ins_pipe(pipe_class_memory);
7546 %}
7547
7548 // Implement LoadPLocked. Must be ordered against changes of the memory location
7549 // by storePConditional.
7550 // Don't know whether this is ever used.
7551 instruct loadPLocked(iRegPdst dst, memory mem) %{
7552 match(Set dst (LoadPLocked mem));
7553 ins_cost(2*MEMORY_REF_COST);
7554
7555 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %}
7556 size(4);
7557 ins_encode %{
7558 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7559 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7560 %}
7561 ins_pipe(pipe_class_memory);
7562 %}
7563
7564 //----------Compare-And-Swap---------------------------------------------------
7565
7566 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7567 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7568 // matched.
7569
7570 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7571 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7572 effect(TEMP cr0);
7573 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7574 // Variable size: instruction count smaller if regs are disjoint.
7575 ins_encode %{
7576 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7577 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7578 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7579 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7580 $res$$Register, true);
7581 %}
7582 ins_pipe(pipe_class_default);
7583 %}
7584
7585 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7586 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7587 effect(TEMP cr0);
7588 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7589 // Variable size: instruction count smaller if regs are disjoint.
7590 ins_encode %{
7591 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7592 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7593 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7594 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7595 $res$$Register, true);
7596 %}
7597 ins_pipe(pipe_class_default);
7598 %}
7599
7600 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7601 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7602 effect(TEMP cr0);
7603 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7604 // Variable size: instruction count smaller if regs are disjoint.
7605 ins_encode %{
7606 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7607 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7608 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7609 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7610 $res$$Register, NULL, true);
7611 %}
7612 ins_pipe(pipe_class_default);
7613 %}
7614
7615 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7616 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7617 effect(TEMP cr0);
7618 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7619 // Variable size: instruction count smaller if regs are disjoint.
7620 ins_encode %{
7621 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7622 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7623 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7624 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7625 $res$$Register, NULL, true);
7626 %}
7627 ins_pipe(pipe_class_default);
7628 %}
7629
7630 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7631 match(Set res (GetAndAddI mem_ptr src));
7632 effect(TEMP cr0);
7633 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7634 // Variable size: instruction count smaller if regs are disjoint.
7635 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7636 ins_pipe(pipe_class_default);
7637 %}
7638
7639 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7640 match(Set res (GetAndAddL mem_ptr src));
7641 effect(TEMP cr0);
7642 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7643 // Variable size: instruction count smaller if regs are disjoint.
7644 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7645 ins_pipe(pipe_class_default);
7646 %}
7647
7648 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7649 match(Set res (GetAndSetI mem_ptr src));
7650 effect(TEMP cr0);
7651 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7652 // Variable size: instruction count smaller if regs are disjoint.
7653 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7654 ins_pipe(pipe_class_default);
7655 %}
7656
7657 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7658 match(Set res (GetAndSetL mem_ptr src));
7659 effect(TEMP cr0);
7660 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7661 // Variable size: instruction count smaller if regs are disjoint.
7662 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7663 ins_pipe(pipe_class_default);
7664 %}
7665
7666 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7667 match(Set res (GetAndSetP mem_ptr src));
7668 effect(TEMP cr0);
7669 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7670 // Variable size: instruction count smaller if regs are disjoint.
7671 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7672 ins_pipe(pipe_class_default);
7673 %}
7674
7675 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7676 match(Set res (GetAndSetN mem_ptr src));
7677 effect(TEMP cr0);
7678 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7679 // Variable size: instruction count smaller if regs are disjoint.
7680 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7681 ins_pipe(pipe_class_default);
7682 %}
7683
7684 //----------Arithmetic Instructions--------------------------------------------
7685 // Addition Instructions
7686
7687 // Register Addition
7688 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7689 match(Set dst (AddI src1 src2));
7690 format %{ "ADD $dst, $src1, $src2" %}
7691 size(4);
7692 ins_encode %{
7693 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7694 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7695 %}
7696 ins_pipe(pipe_class_default);
7697 %}
7698
7699 // Expand does not work with above instruct. (??)
7700 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7701 // no match-rule
7702 effect(DEF dst, USE src1, USE src2);
7703 format %{ "ADD $dst, $src1, $src2" %}
7704 size(4);
7705 ins_encode %{
7706 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7707 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7708 %}
7709 ins_pipe(pipe_class_default);
7710 %}
7711
7712 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7713 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7714 ins_cost(DEFAULT_COST*3);
7715
7716 expand %{
7717 // FIXME: we should do this in the ideal world.
7718 iRegIdst tmp1;
7719 iRegIdst tmp2;
7720 addI_reg_reg(tmp1, src1, src2);
7721 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7722 addI_reg_reg(dst, tmp1, tmp2);
7723 %}
7724 %}
7725
7726 // Immediate Addition
7727 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7728 match(Set dst (AddI src1 src2));
7729 format %{ "ADDI $dst, $src1, $src2" %}
7730 size(4);
7731 ins_encode %{
7732 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7733 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7734 %}
7735 ins_pipe(pipe_class_default);
7736 %}
7737
7738 // Immediate Addition with 16-bit shifted operand
7739 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7740 match(Set dst (AddI src1 src2));
7741 format %{ "ADDIS $dst, $src1, $src2" %}
7742 size(4);
7743 ins_encode %{
7744 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7745 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7746 %}
7747 ins_pipe(pipe_class_default);
7748 %}
7749
7750 // Long Addition
7751 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7752 match(Set dst (AddL src1 src2));
7753 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7754 size(4);
7755 ins_encode %{
7756 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7757 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7758 %}
7759 ins_pipe(pipe_class_default);
7760 %}
7761
7762 // Expand does not work with above instruct. (??)
7763 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7764 // no match-rule
7765 effect(DEF dst, USE src1, USE src2);
7766 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7767 size(4);
7768 ins_encode %{
7769 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7770 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7771 %}
7772 ins_pipe(pipe_class_default);
7773 %}
7774
7775 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7776 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7777 ins_cost(DEFAULT_COST*3);
7778
7779 expand %{
7780 // FIXME: we should do this in the ideal world.
7781 iRegLdst tmp1;
7782 iRegLdst tmp2;
7783 addL_reg_reg(tmp1, src1, src2);
7784 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7785 addL_reg_reg(dst, tmp1, tmp2);
7786 %}
7787 %}
7788
7789 // AddL + ConvL2I.
7790 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7791 match(Set dst (ConvL2I (AddL src1 src2)));
7792
7793 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7794 size(4);
7795 ins_encode %{
7796 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7797 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7798 %}
7799 ins_pipe(pipe_class_default);
7800 %}
7801
7802 // No constant pool entries required.
7803 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7804 match(Set dst (AddL src1 src2));
7805
7806 format %{ "ADDI $dst, $src1, $src2" %}
7807 size(4);
7808 ins_encode %{
7809 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7810 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7811 %}
7812 ins_pipe(pipe_class_default);
7813 %}
7814
7815 // Long Immediate Addition with 16-bit shifted operand.
7816 // No constant pool entries required.
7817 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7818 match(Set dst (AddL src1 src2));
7819
7820 format %{ "ADDIS $dst, $src1, $src2" %}
7821 size(4);
7822 ins_encode %{
7823 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7824 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7825 %}
7826 ins_pipe(pipe_class_default);
7827 %}
7828
7829 // Pointer Register Addition
7830 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7831 match(Set dst (AddP src1 src2));
7832 format %{ "ADD $dst, $src1, $src2" %}
7833 size(4);
7834 ins_encode %{
7835 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7836 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7837 %}
7838 ins_pipe(pipe_class_default);
7839 %}
7840
7841 // Pointer Immediate Addition
7842 // No constant pool entries required.
7843 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7844 match(Set dst (AddP src1 src2));
7845
7846 format %{ "ADDI $dst, $src1, $src2" %}
7847 size(4);
7848 ins_encode %{
7849 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7850 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7851 %}
7852 ins_pipe(pipe_class_default);
7853 %}
7854
7855 // Pointer Immediate Addition with 16-bit shifted operand.
7856 // No constant pool entries required.
7857 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7858 match(Set dst (AddP src1 src2));
7859
7860 format %{ "ADDIS $dst, $src1, $src2" %}
7861 size(4);
7862 ins_encode %{
7863 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7864 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7865 %}
7866 ins_pipe(pipe_class_default);
7867 %}
7868
7869 //---------------------
7870 // Subtraction Instructions
7871
7872 // Register Subtraction
7873 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7874 match(Set dst (SubI src1 src2));
7875 format %{ "SUBF $dst, $src2, $src1" %}
7876 size(4);
7877 ins_encode %{
7878 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7879 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7880 %}
7881 ins_pipe(pipe_class_default);
7882 %}
7883
7884 // Immediate Subtraction
7885 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7886 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7887
7888 // SubI from constant (using subfic).
7889 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7890 match(Set dst (SubI src1 src2));
7891 format %{ "SUBI $dst, $src1, $src2" %}
7892
7893 size(4);
7894 ins_encode %{
7895 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7896 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7897 %}
7898 ins_pipe(pipe_class_default);
7899 %}
7900
7901 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7902 // positive integers and 0xF...F for negative ones.
7903 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7904 // no match-rule, false predicate
7905 effect(DEF dst, USE src);
7906 predicate(false);
7907
7908 format %{ "SRAWI $dst, $src, #31" %}
7909 size(4);
7910 ins_encode %{
7911 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7912 __ srawi($dst$$Register, $src$$Register, 0x1f);
7913 %}
7914 ins_pipe(pipe_class_default);
7915 %}
7916
7917 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7918 match(Set dst (AbsI src));
7919 ins_cost(DEFAULT_COST*3);
7920
7921 expand %{
7922 iRegIdst tmp1;
7923 iRegIdst tmp2;
7924 signmask32I_regI(tmp1, src);
7925 xorI_reg_reg(tmp2, tmp1, src);
7926 subI_reg_reg(dst, tmp2, tmp1);
7927 %}
7928 %}
7929
7930 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7931 match(Set dst (SubI zero src2));
7932 format %{ "NEG $dst, $src2" %}
7933 size(4);
7934 ins_encode %{
7935 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7936 __ neg($dst$$Register, $src2$$Register);
7937 %}
7938 ins_pipe(pipe_class_default);
7939 %}
7940
7941 // Long subtraction
7942 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7943 match(Set dst (SubL src1 src2));
7944 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7945 size(4);
7946 ins_encode %{
7947 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7948 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7949 %}
7950 ins_pipe(pipe_class_default);
7951 %}
7952
7953 // SubL + convL2I.
7954 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7955 match(Set dst (ConvL2I (SubL src1 src2)));
7956
7957 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7958 size(4);
7959 ins_encode %{
7960 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7961 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7962 %}
7963 ins_pipe(pipe_class_default);
7964 %}
7965
7966 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7967 // positive longs and 0xF...F for negative ones.
7968 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7969 // no match-rule, false predicate
7970 effect(DEF dst, USE src);
7971 predicate(false);
7972
7973 format %{ "SRADI $dst, $src, #63" %}
7974 size(4);
7975 ins_encode %{
7976 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7977 __ sradi($dst$$Register, $src$$Register, 0x3f);
7978 %}
7979 ins_pipe(pipe_class_default);
7980 %}
7981
7982 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7983 // positive longs and 0xF...F for negative ones.
7984 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7985 // no match-rule, false predicate
7986 effect(DEF dst, USE src);
7987 predicate(false);
7988
7989 format %{ "SRADI $dst, $src, #63" %}
7990 size(4);
7991 ins_encode %{
7992 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7993 __ sradi($dst$$Register, $src$$Register, 0x3f);
7994 %}
7995 ins_pipe(pipe_class_default);
7996 %}
7997
7998 // Long negation
7999 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8000 match(Set dst (SubL zero src2));
8001 format %{ "NEG $dst, $src2 \t// long" %}
8002 size(4);
8003 ins_encode %{
8004 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8005 __ neg($dst$$Register, $src2$$Register);
8006 %}
8007 ins_pipe(pipe_class_default);
8008 %}
8009
8010 // NegL + ConvL2I.
8011 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8012 match(Set dst (ConvL2I (SubL zero src2)));
8013
8014 format %{ "NEG $dst, $src2 \t// long + l2i" %}
8015 size(4);
8016 ins_encode %{
8017 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8018 __ neg($dst$$Register, $src2$$Register);
8019 %}
8020 ins_pipe(pipe_class_default);
8021 %}
8022
8023 // Multiplication Instructions
8024 // Integer Multiplication
8025
8026 // Register Multiplication
8027 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8028 match(Set dst (MulI src1 src2));
8029 ins_cost(DEFAULT_COST);
8030
8031 format %{ "MULLW $dst, $src1, $src2" %}
8032 size(4);
8033 ins_encode %{
8034 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8035 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8036 %}
8037 ins_pipe(pipe_class_default);
8038 %}
8039
8040 // Immediate Multiplication
8041 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8042 match(Set dst (MulI src1 src2));
8043 ins_cost(DEFAULT_COST);
8044
8045 format %{ "MULLI $dst, $src1, $src2" %}
8046 size(4);
8047 ins_encode %{
8048 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8049 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8050 %}
8051 ins_pipe(pipe_class_default);
8052 %}
8053
8054 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8055 match(Set dst (MulL src1 src2));
8056 ins_cost(DEFAULT_COST);
8057
8058 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8059 size(4);
8060 ins_encode %{
8061 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8062 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8063 %}
8064 ins_pipe(pipe_class_default);
8065 %}
8066
8067 // Multiply high for optimized long division by constant.
8068 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8069 match(Set dst (MulHiL src1 src2));
8070 ins_cost(DEFAULT_COST);
8071
8072 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8073 size(4);
8074 ins_encode %{
8075 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8076 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8077 %}
8078 ins_pipe(pipe_class_default);
8079 %}
8080
8081 // Immediate Multiplication
8082 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8083 match(Set dst (MulL src1 src2));
8084 ins_cost(DEFAULT_COST);
8085
8086 format %{ "MULLI $dst, $src1, $src2" %}
8087 size(4);
8088 ins_encode %{
8089 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8090 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8091 %}
8092 ins_pipe(pipe_class_default);
8093 %}
8094
8095 // Integer Division with Immediate -1: Negate.
8096 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8097 match(Set dst (DivI src1 src2));
8098 ins_cost(DEFAULT_COST);
8099
8100 format %{ "NEG $dst, $src1 \t// /-1" %}
8101 size(4);
8102 ins_encode %{
8103 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8104 __ neg($dst$$Register, $src1$$Register);
8105 %}
8106 ins_pipe(pipe_class_default);
8107 %}
8108
8109 // Integer Division with constant, but not -1.
8110 // We should be able to improve this by checking the type of src2.
8111 // It might well be that src2 is known to be positive.
8112 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8113 match(Set dst (DivI src1 src2));
8114 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8115 ins_cost(2*DEFAULT_COST);
8116
8117 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8118 size(4);
8119 ins_encode %{
8120 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8121 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8122 %}
8123 ins_pipe(pipe_class_default);
8124 %}
8125
8126 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8127 effect(USE_DEF dst, USE src1, USE crx);
8128 predicate(false);
8129
8130 ins_variable_size_depending_on_alignment(true);
8131
8132 format %{ "CMOVE $dst, neg($src1), $crx" %}
8133 // Worst case is branch + move + stop, no stop without scheduler.
8134 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8135 ins_encode %{
8136 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8137 Label done;
8138 __ bne($crx$$CondRegister, done);
8139 __ neg($dst$$Register, $src1$$Register);
8140 // TODO PPC port __ endgroup_if_needed(_size == 12);
8141 __ bind(done);
8142 %}
8143 ins_pipe(pipe_class_default);
8144 %}
8145
8146 // Integer Division with Registers not containing constants.
8147 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8148 match(Set dst (DivI src1 src2));
8149 ins_cost(10*DEFAULT_COST);
8150
8151 expand %{
8152 immI16 imm %{ (int)-1 %}
8153 flagsReg tmp1;
8154 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8155 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8156 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8157 %}
8158 %}
8159
8160 // Long Division with Immediate -1: Negate.
8161 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8162 match(Set dst (DivL src1 src2));
8163 ins_cost(DEFAULT_COST);
8164
8165 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8166 size(4);
8167 ins_encode %{
8168 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8169 __ neg($dst$$Register, $src1$$Register);
8170 %}
8171 ins_pipe(pipe_class_default);
8172 %}
8173
8174 // Long Division with constant, but not -1.
8175 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8176 match(Set dst (DivL src1 src2));
8177 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8178 ins_cost(2*DEFAULT_COST);
8179
8180 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8181 size(4);
8182 ins_encode %{
8183 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8184 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8185 %}
8186 ins_pipe(pipe_class_default);
8187 %}
8188
8189 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8190 effect(USE_DEF dst, USE src1, USE crx);
8191 predicate(false);
8192
8193 ins_variable_size_depending_on_alignment(true);
8194
8195 format %{ "CMOVE $dst, neg($src1), $crx" %}
8196 // Worst case is branch + move + stop, no stop without scheduler.
8197 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8198 ins_encode %{
8199 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8200 Label done;
8201 __ bne($crx$$CondRegister, done);
8202 __ neg($dst$$Register, $src1$$Register);
8203 // TODO PPC port __ endgroup_if_needed(_size == 12);
8204 __ bind(done);
8205 %}
8206 ins_pipe(pipe_class_default);
8207 %}
8208
8209 // Long Division with Registers not containing constants.
8210 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8211 match(Set dst (DivL src1 src2));
8212 ins_cost(10*DEFAULT_COST);
8213
8214 expand %{
8215 immL16 imm %{ (int)-1 %}
8216 flagsReg tmp1;
8217 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8218 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8219 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8220 %}
8221 %}
8222
8223 // Integer Remainder with registers.
8224 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8225 match(Set dst (ModI src1 src2));
8226 ins_cost(10*DEFAULT_COST);
8227
8228 expand %{
8229 immI16 imm %{ (int)-1 %}
8230 flagsReg tmp1;
8231 iRegIdst tmp2;
8232 iRegIdst tmp3;
8233 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8234 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8235 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8236 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8237 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8238 %}
8239 %}
8240
8241 // Long Remainder with registers
8242 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8243 match(Set dst (ModL src1 src2));
8244 ins_cost(10*DEFAULT_COST);
8245
8246 expand %{
8247 immL16 imm %{ (int)-1 %}
8248 flagsReg tmp1;
8249 iRegLdst tmp2;
8250 iRegLdst tmp3;
8251 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8252 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8253 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8254 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8255 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8256 %}
8257 %}
8258
8259 // Integer Shift Instructions
8260
8261 // Register Shift Left
8262
8263 // Clear all but the lowest #mask bits.
8264 // Used to normalize shift amounts in registers.
8265 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8266 // no match-rule, false predicate
8267 effect(DEF dst, USE src, USE mask);
8268 predicate(false);
8269
8270 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8271 size(4);
8272 ins_encode %{
8273 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8274 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8275 %}
8276 ins_pipe(pipe_class_default);
8277 %}
8278
8279 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8280 // no match-rule, false predicate
8281 effect(DEF dst, USE src1, USE src2);
8282 predicate(false);
8283
8284 format %{ "SLW $dst, $src1, $src2" %}
8285 size(4);
8286 ins_encode %{
8287 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8288 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8289 %}
8290 ins_pipe(pipe_class_default);
8291 %}
8292
8293 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8294 match(Set dst (LShiftI src1 src2));
8295 ins_cost(DEFAULT_COST*2);
8296 expand %{
8297 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8298 iRegIdst tmpI;
8299 maskI_reg_imm(tmpI, src2, mask);
8300 lShiftI_reg_reg(dst, src1, tmpI);
8301 %}
8302 %}
8303
8304 // Register Shift Left Immediate
8305 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8306 match(Set dst (LShiftI src1 src2));
8307
8308 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8309 size(4);
8310 ins_encode %{
8311 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8312 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8313 %}
8314 ins_pipe(pipe_class_default);
8315 %}
8316
8317 // AndI with negpow2-constant + LShiftI
8318 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8319 match(Set dst (LShiftI (AndI src1 src2) src3));
8320 predicate(UseRotateAndMaskInstructionsPPC64);
8321
8322 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8323 size(4);
8324 ins_encode %{
8325 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8326 long src2 = $src2$$constant;
8327 long src3 = $src3$$constant;
8328 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8329 if (maskbits >= 32) {
8330 __ li($dst$$Register, 0); // addi
8331 } else {
8332 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8333 }
8334 %}
8335 ins_pipe(pipe_class_default);
8336 %}
8337
8338 // RShiftI + AndI with negpow2-constant + LShiftI
8339 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8340 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8341 predicate(UseRotateAndMaskInstructionsPPC64);
8342
8343 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8344 size(4);
8345 ins_encode %{
8346 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8347 long src2 = $src2$$constant;
8348 long src3 = $src3$$constant;
8349 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8350 if (maskbits >= 32) {
8351 __ li($dst$$Register, 0); // addi
8352 } else {
8353 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8354 }
8355 %}
8356 ins_pipe(pipe_class_default);
8357 %}
8358
8359 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8360 // no match-rule, false predicate
8361 effect(DEF dst, USE src1, USE src2);
8362 predicate(false);
8363
8364 format %{ "SLD $dst, $src1, $src2" %}
8365 size(4);
8366 ins_encode %{
8367 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8368 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8369 %}
8370 ins_pipe(pipe_class_default);
8371 %}
8372
8373 // Register Shift Left
8374 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8375 match(Set dst (LShiftL src1 src2));
8376 ins_cost(DEFAULT_COST*2);
8377 expand %{
8378 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8379 iRegIdst tmpI;
8380 maskI_reg_imm(tmpI, src2, mask);
8381 lShiftL_regL_regI(dst, src1, tmpI);
8382 %}
8383 %}
8384
8385 // Register Shift Left Immediate
8386 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8387 match(Set dst (LShiftL src1 src2));
8388 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8389 size(4);
8390 ins_encode %{
8391 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8392 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8393 %}
8394 ins_pipe(pipe_class_default);
8395 %}
8396
8397 // If we shift more than 32 bits, we need not convert I2L.
8398 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8399 match(Set dst (LShiftL (ConvI2L src1) src2));
8400 ins_cost(DEFAULT_COST);
8401
8402 size(4);
8403 format %{ "SLDI $dst, i2l($src1), $src2" %}
8404 ins_encode %{
8405 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8406 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8407 %}
8408 ins_pipe(pipe_class_default);
8409 %}
8410
8411 // Shift a postivie int to the left.
8412 // Clrlsldi clears the upper 32 bits and shifts.
8413 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8414 match(Set dst (LShiftL (ConvI2L src1) src2));
8415 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8416
8417 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8418 size(4);
8419 ins_encode %{
8420 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8421 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8422 %}
8423 ins_pipe(pipe_class_default);
8424 %}
8425
8426 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8427 // no match-rule, false predicate
8428 effect(DEF dst, USE src1, USE src2);
8429 predicate(false);
8430
8431 format %{ "SRAW $dst, $src1, $src2" %}
8432 size(4);
8433 ins_encode %{
8434 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8435 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8436 %}
8437 ins_pipe(pipe_class_default);
8438 %}
8439
8440 // Register Arithmetic Shift Right
8441 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8442 match(Set dst (RShiftI src1 src2));
8443 ins_cost(DEFAULT_COST*2);
8444 expand %{
8445 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8446 iRegIdst tmpI;
8447 maskI_reg_imm(tmpI, src2, mask);
8448 arShiftI_reg_reg(dst, src1, tmpI);
8449 %}
8450 %}
8451
8452 // Register Arithmetic Shift Right Immediate
8453 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8454 match(Set dst (RShiftI src1 src2));
8455
8456 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8457 size(4);
8458 ins_encode %{
8459 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8460 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8461 %}
8462 ins_pipe(pipe_class_default);
8463 %}
8464
8465 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8466 // no match-rule, false predicate
8467 effect(DEF dst, USE src1, USE src2);
8468 predicate(false);
8469
8470 format %{ "SRAD $dst, $src1, $src2" %}
8471 size(4);
8472 ins_encode %{
8473 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8474 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8475 %}
8476 ins_pipe(pipe_class_default);
8477 %}
8478
8479 // Register Shift Right Arithmetic Long
8480 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8481 match(Set dst (RShiftL src1 src2));
8482 ins_cost(DEFAULT_COST*2);
8483
8484 expand %{
8485 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8486 iRegIdst tmpI;
8487 maskI_reg_imm(tmpI, src2, mask);
8488 arShiftL_regL_regI(dst, src1, tmpI);
8489 %}
8490 %}
8491
8492 // Register Shift Right Immediate
8493 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8494 match(Set dst (RShiftL src1 src2));
8495
8496 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8497 size(4);
8498 ins_encode %{
8499 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8500 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8501 %}
8502 ins_pipe(pipe_class_default);
8503 %}
8504
8505 // RShiftL + ConvL2I
8506 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8507 match(Set dst (ConvL2I (RShiftL src1 src2)));
8508
8509 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8510 size(4);
8511 ins_encode %{
8512 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8513 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8514 %}
8515 ins_pipe(pipe_class_default);
8516 %}
8517
8518 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8519 // no match-rule, false predicate
8520 effect(DEF dst, USE src1, USE src2);
8521 predicate(false);
8522
8523 format %{ "SRW $dst, $src1, $src2" %}
8524 size(4);
8525 ins_encode %{
8526 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8527 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8528 %}
8529 ins_pipe(pipe_class_default);
8530 %}
8531
8532 // Register Shift Right
8533 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8534 match(Set dst (URShiftI src1 src2));
8535 ins_cost(DEFAULT_COST*2);
8536
8537 expand %{
8538 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8539 iRegIdst tmpI;
8540 maskI_reg_imm(tmpI, src2, mask);
8541 urShiftI_reg_reg(dst, src1, tmpI);
8542 %}
8543 %}
8544
8545 // Register Shift Right Immediate
8546 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8547 match(Set dst (URShiftI src1 src2));
8548
8549 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8550 size(4);
8551 ins_encode %{
8552 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8553 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8554 %}
8555 ins_pipe(pipe_class_default);
8556 %}
8557
8558 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8559 // no match-rule, false predicate
8560 effect(DEF dst, USE src1, USE src2);
8561 predicate(false);
8562
8563 format %{ "SRD $dst, $src1, $src2" %}
8564 size(4);
8565 ins_encode %{
8566 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8567 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8568 %}
8569 ins_pipe(pipe_class_default);
8570 %}
8571
8572 // Register Shift Right
8573 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8574 match(Set dst (URShiftL src1 src2));
8575 ins_cost(DEFAULT_COST*2);
8576
8577 expand %{
8578 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8579 iRegIdst tmpI;
8580 maskI_reg_imm(tmpI, src2, mask);
8581 urShiftL_regL_regI(dst, src1, tmpI);
8582 %}
8583 %}
8584
8585 // Register Shift Right Immediate
8586 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8587 match(Set dst (URShiftL src1 src2));
8588
8589 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8590 size(4);
8591 ins_encode %{
8592 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8593 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8594 %}
8595 ins_pipe(pipe_class_default);
8596 %}
8597
8598 // URShiftL + ConvL2I.
8599 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8600 match(Set dst (ConvL2I (URShiftL src1 src2)));
8601
8602 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8603 size(4);
8604 ins_encode %{
8605 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8606 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8607 %}
8608 ins_pipe(pipe_class_default);
8609 %}
8610
8611 // Register Shift Right Immediate with a CastP2X
8612 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8613 match(Set dst (URShiftL (CastP2X src1) src2));
8614
8615 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8616 size(4);
8617 ins_encode %{
8618 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8619 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8620 %}
8621 ins_pipe(pipe_class_default);
8622 %}
8623
8624 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8625 match(Set dst (ConvL2I (ConvI2L src)));
8626
8627 format %{ "EXTSW $dst, $src \t// int->int" %}
8628 size(4);
8629 ins_encode %{
8630 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8631 __ extsw($dst$$Register, $src$$Register);
8632 %}
8633 ins_pipe(pipe_class_default);
8634 %}
8635
8636 //----------Rotate Instructions------------------------------------------------
8637
8638 // Rotate Left by 8-bit immediate
8639 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8640 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8641 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8642
8643 format %{ "ROTLWI $dst, $src, $lshift" %}
8644 size(4);
8645 ins_encode %{
8646 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8647 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8648 %}
8649 ins_pipe(pipe_class_default);
8650 %}
8651
8652 // Rotate Right by 8-bit immediate
8653 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8654 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8655 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8656
8657 format %{ "ROTRWI $dst, $rshift" %}
8658 size(4);
8659 ins_encode %{
8660 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8661 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8662 %}
8663 ins_pipe(pipe_class_default);
8664 %}
8665
8666 //----------Floating Point Arithmetic Instructions-----------------------------
8667
8668 // Add float single precision
8669 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8670 match(Set dst (AddF src1 src2));
8671
8672 format %{ "FADDS $dst, $src1, $src2" %}
8673 size(4);
8674 ins_encode %{
8675 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8676 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8677 %}
8678 ins_pipe(pipe_class_default);
8679 %}
8680
8681 // Add float double precision
8682 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8683 match(Set dst (AddD src1 src2));
8684
8685 format %{ "FADD $dst, $src1, $src2" %}
8686 size(4);
8687 ins_encode %{
8688 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8689 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8690 %}
8691 ins_pipe(pipe_class_default);
8692 %}
8693
8694 // Sub float single precision
8695 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8696 match(Set dst (SubF src1 src2));
8697
8698 format %{ "FSUBS $dst, $src1, $src2" %}
8699 size(4);
8700 ins_encode %{
8701 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8702 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8703 %}
8704 ins_pipe(pipe_class_default);
8705 %}
8706
8707 // Sub float double precision
8708 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8709 match(Set dst (SubD src1 src2));
8710 format %{ "FSUB $dst, $src1, $src2" %}
8711 size(4);
8712 ins_encode %{
8713 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8714 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8715 %}
8716 ins_pipe(pipe_class_default);
8717 %}
8718
8719 // Mul float single precision
8720 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8721 match(Set dst (MulF src1 src2));
8722 format %{ "FMULS $dst, $src1, $src2" %}
8723 size(4);
8724 ins_encode %{
8725 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8726 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8727 %}
8728 ins_pipe(pipe_class_default);
8729 %}
8730
8731 // Mul float double precision
8732 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8733 match(Set dst (MulD src1 src2));
8734 format %{ "FMUL $dst, $src1, $src2" %}
8735 size(4);
8736 ins_encode %{
8737 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8738 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8739 %}
8740 ins_pipe(pipe_class_default);
8741 %}
8742
8743 // Div float single precision
8744 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8745 match(Set dst (DivF src1 src2));
8746 format %{ "FDIVS $dst, $src1, $src2" %}
8747 size(4);
8748 ins_encode %{
8749 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8750 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8751 %}
8752 ins_pipe(pipe_class_default);
8753 %}
8754
8755 // Div float double precision
8756 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8757 match(Set dst (DivD src1 src2));
8758 format %{ "FDIV $dst, $src1, $src2" %}
8759 size(4);
8760 ins_encode %{
8761 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8762 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8763 %}
8764 ins_pipe(pipe_class_default);
8765 %}
8766
8767 // Absolute float single precision
8768 instruct absF_reg(regF dst, regF src) %{
8769 match(Set dst (AbsF src));
8770 format %{ "FABS $dst, $src \t// float" %}
8771 size(4);
8772 ins_encode %{
8773 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8774 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8775 %}
8776 ins_pipe(pipe_class_default);
8777 %}
8778
8779 // Absolute float double precision
8780 instruct absD_reg(regD dst, regD src) %{
8781 match(Set dst (AbsD src));
8782 format %{ "FABS $dst, $src \t// double" %}
8783 size(4);
8784 ins_encode %{
8785 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8786 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8787 %}
8788 ins_pipe(pipe_class_default);
8789 %}
8790
8791 instruct negF_reg(regF dst, regF src) %{
8792 match(Set dst (NegF src));
8793 format %{ "FNEG $dst, $src \t// float" %}
8794 size(4);
8795 ins_encode %{
8796 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8797 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8798 %}
8799 ins_pipe(pipe_class_default);
8800 %}
8801
8802 instruct negD_reg(regD dst, regD src) %{
8803 match(Set dst (NegD src));
8804 format %{ "FNEG $dst, $src \t// double" %}
8805 size(4);
8806 ins_encode %{
8807 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8808 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8809 %}
8810 ins_pipe(pipe_class_default);
8811 %}
8812
8813 // AbsF + NegF.
8814 instruct negF_absF_reg(regF dst, regF src) %{
8815 match(Set dst (NegF (AbsF src)));
8816 format %{ "FNABS $dst, $src \t// float" %}
8817 size(4);
8818 ins_encode %{
8819 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8820 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8821 %}
8822 ins_pipe(pipe_class_default);
8823 %}
8824
8825 // AbsD + NegD.
8826 instruct negD_absD_reg(regD dst, regD src) %{
8827 match(Set dst (NegD (AbsD src)));
8828 format %{ "FNABS $dst, $src \t// double" %}
8829 size(4);
8830 ins_encode %{
8831 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8832 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8833 %}
8834 ins_pipe(pipe_class_default);
8835 %}
8836
8837 // VM_Version::has_fsqrt() decides if this node will be used.
8838 // Sqrt float double precision
8839 instruct sqrtD_reg(regD dst, regD src) %{
8840 match(Set dst (SqrtD src));
8841 format %{ "FSQRT $dst, $src" %}
8842 size(4);
8843 ins_encode %{
8844 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8845 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8846 %}
8847 ins_pipe(pipe_class_default);
8848 %}
8849
8850 // Single-precision sqrt.
8851 instruct sqrtF_reg(regF dst, regF src) %{
8852 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8853 predicate(VM_Version::has_fsqrts());
8854 ins_cost(DEFAULT_COST);
8855
8856 format %{ "FSQRTS $dst, $src" %}
8857 size(4);
8858 ins_encode %{
8859 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8860 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8861 %}
8862 ins_pipe(pipe_class_default);
8863 %}
8864
8865 instruct roundDouble_nop(regD dst) %{
8866 match(Set dst (RoundDouble dst));
8867 ins_cost(0);
8868
8869 format %{ " -- \t// RoundDouble not needed - empty" %}
8870 size(0);
8871 // PPC results are already "rounded" (i.e., normal-format IEEE).
8872 ins_encode( /*empty*/ );
8873 ins_pipe(pipe_class_default);
8874 %}
8875
8876 instruct roundFloat_nop(regF dst) %{
8877 match(Set dst (RoundFloat dst));
8878 ins_cost(0);
8879
8880 format %{ " -- \t// RoundFloat not needed - empty" %}
8881 size(0);
8882 // PPC results are already "rounded" (i.e., normal-format IEEE).
8883 ins_encode( /*empty*/ );
8884 ins_pipe(pipe_class_default);
8885 %}
8886
8887 //----------Logical Instructions-----------------------------------------------
8888
8889 // And Instructions
8890
8891 // Register And
8892 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8893 match(Set dst (AndI src1 src2));
8894 format %{ "AND $dst, $src1, $src2" %}
8895 size(4);
8896 ins_encode %{
8897 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8898 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8899 %}
8900 ins_pipe(pipe_class_default);
8901 %}
8902
8903 // Immediate And
8904 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8905 match(Set dst (AndI src1 src2));
8906 effect(KILL cr0);
8907
8908 format %{ "ANDI $dst, $src1, $src2" %}
8909 size(4);
8910 ins_encode %{
8911 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8912 // FIXME: avoid andi_ ?
8913 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8914 %}
8915 ins_pipe(pipe_class_default);
8916 %}
8917
8918 // Immediate And where the immediate is a negative power of 2.
8919 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8920 match(Set dst (AndI src1 src2));
8921 format %{ "ANDWI $dst, $src1, $src2" %}
8922 size(4);
8923 ins_encode %{
8924 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8925 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8926 %}
8927 ins_pipe(pipe_class_default);
8928 %}
8929
8930 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8931 match(Set dst (AndI src1 src2));
8932 format %{ "ANDWI $dst, $src1, $src2" %}
8933 size(4);
8934 ins_encode %{
8935 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8936 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8937 %}
8938 ins_pipe(pipe_class_default);
8939 %}
8940
8941 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8942 match(Set dst (AndI src1 src2));
8943 predicate(UseRotateAndMaskInstructionsPPC64);
8944 format %{ "ANDWI $dst, $src1, $src2" %}
8945 size(4);
8946 ins_encode %{
8947 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8948 __ rlwinm($dst$$Register, $src1$$Register, 0,
8949 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8950 %}
8951 ins_pipe(pipe_class_default);
8952 %}
8953
8954 // Register And Long
8955 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8956 match(Set dst (AndL src1 src2));
8957 ins_cost(DEFAULT_COST);
8958
8959 format %{ "AND $dst, $src1, $src2 \t// long" %}
8960 size(4);
8961 ins_encode %{
8962 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8963 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8964 %}
8965 ins_pipe(pipe_class_default);
8966 %}
8967
8968 // Immediate And long
8969 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8970 match(Set dst (AndL src1 src2));
8971 effect(KILL cr0);
8972
8973 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8974 size(4);
8975 ins_encode %{
8976 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8977 // FIXME: avoid andi_ ?
8978 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8979 %}
8980 ins_pipe(pipe_class_default);
8981 %}
8982
8983 // Immediate And Long where the immediate is a negative power of 2.
8984 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8985 match(Set dst (AndL src1 src2));
8986 format %{ "ANDDI $dst, $src1, $src2" %}
8987 size(4);
8988 ins_encode %{
8989 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8990 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8991 %}
8992 ins_pipe(pipe_class_default);
8993 %}
8994
8995 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8996 match(Set dst (AndL src1 src2));
8997 format %{ "ANDDI $dst, $src1, $src2" %}
8998 size(4);
8999 ins_encode %{
9000 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9001 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9002 %}
9003 ins_pipe(pipe_class_default);
9004 %}
9005
9006 // AndL + ConvL2I.
9007 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9008 match(Set dst (ConvL2I (AndL src1 src2)));
9009 ins_cost(DEFAULT_COST);
9010
9011 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
9012 size(4);
9013 ins_encode %{
9014 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9015 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9016 %}
9017 ins_pipe(pipe_class_default);
9018 %}
9019
9020 // Or Instructions
9021
9022 // Register Or
9023 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9024 match(Set dst (OrI src1 src2));
9025 format %{ "OR $dst, $src1, $src2" %}
9026 size(4);
9027 ins_encode %{
9028 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9029 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9030 %}
9031 ins_pipe(pipe_class_default);
9032 %}
9033
9034 // Expand does not work with above instruct. (??)
9035 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9036 // no match-rule
9037 effect(DEF dst, USE src1, USE src2);
9038 format %{ "OR $dst, $src1, $src2" %}
9039 size(4);
9040 ins_encode %{
9041 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9042 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9043 %}
9044 ins_pipe(pipe_class_default);
9045 %}
9046
9047 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9048 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9049 ins_cost(DEFAULT_COST*3);
9050
9051 expand %{
9052 // FIXME: we should do this in the ideal world.
9053 iRegIdst tmp1;
9054 iRegIdst tmp2;
9055 orI_reg_reg(tmp1, src1, src2);
9056 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9057 orI_reg_reg(dst, tmp1, tmp2);
9058 %}
9059 %}
9060
9061 // Immediate Or
9062 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9063 match(Set dst (OrI src1 src2));
9064 format %{ "ORI $dst, $src1, $src2" %}
9065 size(4);
9066 ins_encode %{
9067 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9068 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9069 %}
9070 ins_pipe(pipe_class_default);
9071 %}
9072
9073 // Register Or Long
9074 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9075 match(Set dst (OrL src1 src2));
9076 ins_cost(DEFAULT_COST);
9077
9078 size(4);
9079 format %{ "OR $dst, $src1, $src2 \t// long" %}
9080 ins_encode %{
9081 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9082 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9083 %}
9084 ins_pipe(pipe_class_default);
9085 %}
9086
9087 // OrL + ConvL2I.
9088 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9089 match(Set dst (ConvL2I (OrL src1 src2)));
9090 ins_cost(DEFAULT_COST);
9091
9092 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9093 size(4);
9094 ins_encode %{
9095 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9096 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9097 %}
9098 ins_pipe(pipe_class_default);
9099 %}
9100
9101 // Immediate Or long
9102 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9103 match(Set dst (OrL src1 con));
9104 ins_cost(DEFAULT_COST);
9105
9106 format %{ "ORI $dst, $src1, $con \t// long" %}
9107 size(4);
9108 ins_encode %{
9109 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9110 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9111 %}
9112 ins_pipe(pipe_class_default);
9113 %}
9114
9115 // Xor Instructions
9116
9117 // Register Xor
9118 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9119 match(Set dst (XorI src1 src2));
9120 format %{ "XOR $dst, $src1, $src2" %}
9121 size(4);
9122 ins_encode %{
9123 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9124 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9125 %}
9126 ins_pipe(pipe_class_default);
9127 %}
9128
9129 // Expand does not work with above instruct. (??)
9130 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9131 // no match-rule
9132 effect(DEF dst, USE src1, USE src2);
9133 format %{ "XOR $dst, $src1, $src2" %}
9134 size(4);
9135 ins_encode %{
9136 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9137 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9138 %}
9139 ins_pipe(pipe_class_default);
9140 %}
9141
9142 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9143 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9144 ins_cost(DEFAULT_COST*3);
9145
9146 expand %{
9147 // FIXME: we should do this in the ideal world.
9148 iRegIdst tmp1;
9149 iRegIdst tmp2;
9150 xorI_reg_reg(tmp1, src1, src2);
9151 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9152 xorI_reg_reg(dst, tmp1, tmp2);
9153 %}
9154 %}
9155
9156 // Immediate Xor
9157 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9158 match(Set dst (XorI src1 src2));
9159 format %{ "XORI $dst, $src1, $src2" %}
9160 size(4);
9161 ins_encode %{
9162 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9163 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9164 %}
9165 ins_pipe(pipe_class_default);
9166 %}
9167
9168 // Register Xor Long
9169 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9170 match(Set dst (XorL src1 src2));
9171 ins_cost(DEFAULT_COST);
9172
9173 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9174 size(4);
9175 ins_encode %{
9176 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9177 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9178 %}
9179 ins_pipe(pipe_class_default);
9180 %}
9181
9182 // XorL + ConvL2I.
9183 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9184 match(Set dst (ConvL2I (XorL src1 src2)));
9185 ins_cost(DEFAULT_COST);
9186
9187 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9188 size(4);
9189 ins_encode %{
9190 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9191 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9192 %}
9193 ins_pipe(pipe_class_default);
9194 %}
9195
9196 // Immediate Xor Long
9197 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9198 match(Set dst (XorL src1 src2));
9199 ins_cost(DEFAULT_COST);
9200
9201 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9202 size(4);
9203 ins_encode %{
9204 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9205 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9206 %}
9207 ins_pipe(pipe_class_default);
9208 %}
9209
9210 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9211 match(Set dst (XorI src1 src2));
9212 ins_cost(DEFAULT_COST);
9213
9214 format %{ "NOT $dst, $src1 ($src2)" %}
9215 size(4);
9216 ins_encode %{
9217 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9218 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9219 %}
9220 ins_pipe(pipe_class_default);
9221 %}
9222
9223 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9224 match(Set dst (XorL src1 src2));
9225 ins_cost(DEFAULT_COST);
9226
9227 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9228 size(4);
9229 ins_encode %{
9230 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9231 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9232 %}
9233 ins_pipe(pipe_class_default);
9234 %}
9235
9236 // And-complement
9237 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9238 match(Set dst (AndI (XorI src1 src2) src3));
9239 ins_cost(DEFAULT_COST);
9240
9241 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9242 size(4);
9243 ins_encode( enc_andc(dst, src3, src1) );
9244 ins_pipe(pipe_class_default);
9245 %}
9246
9247 // And-complement
9248 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9249 // no match-rule, false predicate
9250 effect(DEF dst, USE src1, USE src2);
9251 predicate(false);
9252
9253 format %{ "ANDC $dst, $src1, $src2" %}
9254 size(4);
9255 ins_encode %{
9256 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9257 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9258 %}
9259 ins_pipe(pipe_class_default);
9260 %}
9261
9262 //----------Moves between int/long and float/double----------------------------
9263 //
9264 // The following rules move values from int/long registers/stack-locations
9265 // to float/double registers/stack-locations and vice versa, without doing any
9266 // conversions. These rules are used to implement the bit-conversion methods
9267 // of java.lang.Float etc., e.g.
9268 // int floatToIntBits(float value)
9269 // float intBitsToFloat(int bits)
9270 //
9271 // Notes on the implementation on ppc64:
9272 // We only provide rules which move between a register and a stack-location,
9273 // because we always have to go through memory when moving between a float
9274 // register and an integer register.
9275
9276 //---------- Chain stack slots between similar types --------
9277
9278 // These are needed so that the rules below can match.
9279
9280 // Load integer from stack slot
9281 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9282 match(Set dst src);
9283 ins_cost(MEMORY_REF_COST);
9284
9285 format %{ "LWZ $dst, $src" %}
9286 size(4);
9287 ins_encode( enc_lwz(dst, src) );
9288 ins_pipe(pipe_class_memory);
9289 %}
9290
9291 // Store integer to stack slot
9292 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9293 match(Set dst src);
9294 ins_cost(MEMORY_REF_COST);
9295
9296 format %{ "STW $src, $dst \t// stk" %}
9297 size(4);
9298 ins_encode( enc_stw(src, dst) ); // rs=rt
9299 ins_pipe(pipe_class_memory);
9300 %}
9301
9302 // Load long from stack slot
9303 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9304 match(Set dst src);
9305 ins_cost(MEMORY_REF_COST);
9306
9307 format %{ "LD $dst, $src \t// long" %}
9308 size(4);
9309 ins_encode( enc_ld(dst, src) );
9310 ins_pipe(pipe_class_memory);
9311 %}
9312
9313 // Store long to stack slot
9314 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9315 match(Set dst src);
9316 ins_cost(MEMORY_REF_COST);
9317
9318 format %{ "STD $src, $dst \t// long" %}
9319 size(4);
9320 ins_encode( enc_std(src, dst) ); // rs=rt
9321 ins_pipe(pipe_class_memory);
9322 %}
9323
9324 //----------Moves between int and float
9325
9326 // Move float value from float stack-location to integer register.
9327 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9328 match(Set dst (MoveF2I src));
9329 ins_cost(MEMORY_REF_COST);
9330
9331 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9332 size(4);
9333 ins_encode( enc_lwz(dst, src) );
9334 ins_pipe(pipe_class_memory);
9335 %}
9336
9337 // Move float value from float register to integer stack-location.
9338 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9339 match(Set dst (MoveF2I src));
9340 ins_cost(MEMORY_REF_COST);
9341
9342 format %{ "STFS $src, $dst \t// MoveF2I" %}
9343 size(4);
9344 ins_encode( enc_stfs(src, dst) );
9345 ins_pipe(pipe_class_memory);
9346 %}
9347
9348 // Move integer value from integer stack-location to float register.
9349 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9350 match(Set dst (MoveI2F src));
9351 ins_cost(MEMORY_REF_COST);
9352
9353 format %{ "LFS $dst, $src \t// MoveI2F" %}
9354 size(4);
9355 ins_encode %{
9356 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9357 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9358 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9359 %}
9360 ins_pipe(pipe_class_memory);
9361 %}
9362
9363 // Move integer value from integer register to float stack-location.
9364 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9365 match(Set dst (MoveI2F src));
9366 ins_cost(MEMORY_REF_COST);
9367
9368 format %{ "STW $src, $dst \t// MoveI2F" %}
9369 size(4);
9370 ins_encode( enc_stw(src, dst) );
9371 ins_pipe(pipe_class_memory);
9372 %}
9373
9374 //----------Moves between long and float
9375
9376 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9377 // no match-rule, false predicate
9378 effect(DEF dst, USE src);
9379 predicate(false);
9380
9381 format %{ "storeD $src, $dst \t// STACK" %}
9382 size(4);
9383 ins_encode( enc_stfd(src, dst) );
9384 ins_pipe(pipe_class_default);
9385 %}
9386
9387 //----------Moves between long and double
9388
9389 // Move double value from double stack-location to long register.
9390 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9391 match(Set dst (MoveD2L src));
9392 ins_cost(MEMORY_REF_COST);
9393 size(4);
9394 format %{ "LD $dst, $src \t// MoveD2L" %}
9395 ins_encode( enc_ld(dst, src) );
9396 ins_pipe(pipe_class_memory);
9397 %}
9398
9399 // Move double value from double register to long stack-location.
9400 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9401 match(Set dst (MoveD2L src));
9402 effect(DEF dst, USE src);
9403 ins_cost(MEMORY_REF_COST);
9404
9405 format %{ "STFD $src, $dst \t// MoveD2L" %}
9406 size(4);
9407 ins_encode( enc_stfd(src, dst) );
9408 ins_pipe(pipe_class_memory);
9409 %}
9410
9411 // Move long value from long stack-location to double register.
9412 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9413 match(Set dst (MoveL2D src));
9414 ins_cost(MEMORY_REF_COST);
9415
9416 format %{ "LFD $dst, $src \t// MoveL2D" %}
9417 size(4);
9418 ins_encode( enc_lfd(dst, src) );
9419 ins_pipe(pipe_class_memory);
9420 %}
9421
9422 // Move long value from long register to double stack-location.
9423 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9424 match(Set dst (MoveL2D src));
9425 ins_cost(MEMORY_REF_COST);
9426
9427 format %{ "STD $src, $dst \t// MoveL2D" %}
9428 size(4);
9429 ins_encode( enc_std(src, dst) );
9430 ins_pipe(pipe_class_memory);
9431 %}
9432
9433 //----------Register Move Instructions-----------------------------------------
9434
9435 // Replicate for Superword
9436
9437 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9438 predicate(false);
9439 effect(DEF dst, USE src);
9440
9441 format %{ "MR $dst, $src \t// replicate " %}
9442 // variable size, 0 or 4.
9443 ins_encode %{
9444 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9445 __ mr_if_needed($dst$$Register, $src$$Register);
9446 %}
9447 ins_pipe(pipe_class_default);
9448 %}
9449
9450 //----------Cast instructions (Java-level type cast)---------------------------
9451
9452 // Cast Long to Pointer for unsafe natives.
9453 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9454 match(Set dst (CastX2P src));
9455
9456 format %{ "MR $dst, $src \t// Long->Ptr" %}
9457 // variable size, 0 or 4.
9458 ins_encode %{
9459 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9460 __ mr_if_needed($dst$$Register, $src$$Register);
9461 %}
9462 ins_pipe(pipe_class_default);
9463 %}
9464
9465 // Cast Pointer to Long for unsafe natives.
9466 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9467 match(Set dst (CastP2X src));
9468
9469 format %{ "MR $dst, $src \t// Ptr->Long" %}
9470 // variable size, 0 or 4.
9471 ins_encode %{
9472 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9473 __ mr_if_needed($dst$$Register, $src$$Register);
9474 %}
9475 ins_pipe(pipe_class_default);
9476 %}
9477
9478 instruct castPP(iRegPdst dst) %{
9479 match(Set dst (CastPP dst));
9480 format %{ " -- \t// castPP of $dst" %}
9481 size(0);
9482 ins_encode( /*empty*/ );
9483 ins_pipe(pipe_class_default);
9484 %}
9485
9486 instruct castII(iRegIdst dst) %{
9487 match(Set dst (CastII dst));
9488 format %{ " -- \t// castII of $dst" %}
9489 size(0);
9490 ins_encode( /*empty*/ );
9491 ins_pipe(pipe_class_default);
9492 %}
9493
9494 instruct checkCastPP(iRegPdst dst) %{
9495 match(Set dst (CheckCastPP dst));
9496 format %{ " -- \t// checkcastPP of $dst" %}
9497 size(0);
9498 ins_encode( /*empty*/ );
9499 ins_pipe(pipe_class_default);
9500 %}
9501
9502 //----------Convert instructions-----------------------------------------------
9503
9504 // Convert to boolean.
9505
9506 // int_to_bool(src) : { 1 if src != 0
9507 // { 0 else
9508 //
9509 // strategy:
9510 // 1) Count leading zeros of 32 bit-value src,
9511 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9512 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9513 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9514
9515 // convI2Bool
9516 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9517 match(Set dst (Conv2B src));
9518 predicate(UseCountLeadingZerosInstructionsPPC64);
9519 ins_cost(DEFAULT_COST);
9520
9521 expand %{
9522 immI shiftAmount %{ 0x5 %}
9523 uimmI16 mask %{ 0x1 %}
9524 iRegIdst tmp1;
9525 iRegIdst tmp2;
9526 countLeadingZerosI(tmp1, src);
9527 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9528 xorI_reg_uimm16(dst, tmp2, mask);
9529 %}
9530 %}
9531
9532 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9533 match(Set dst (Conv2B src));
9534 effect(TEMP crx);
9535 predicate(!UseCountLeadingZerosInstructionsPPC64);
9536 ins_cost(DEFAULT_COST);
9537
9538 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9539 "LI $dst, #0\n\t"
9540 "BEQ $crx, done\n\t"
9541 "LI $dst, #1\n"
9542 "done:" %}
9543 size(16);
9544 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9545 ins_pipe(pipe_class_compare);
9546 %}
9547
9548 // ConvI2B + XorI
9549 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9550 match(Set dst (XorI (Conv2B src) mask));
9551 predicate(UseCountLeadingZerosInstructionsPPC64);
9552 ins_cost(DEFAULT_COST);
9553
9554 expand %{
9555 immI shiftAmount %{ 0x5 %}
9556 iRegIdst tmp1;
9557 countLeadingZerosI(tmp1, src);
9558 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9559 %}
9560 %}
9561
9562 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9563 match(Set dst (XorI (Conv2B src) mask));
9564 effect(TEMP crx);
9565 predicate(!UseCountLeadingZerosInstructionsPPC64);
9566 ins_cost(DEFAULT_COST);
9567
9568 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9569 "LI $dst, #1\n\t"
9570 "BEQ $crx, done\n\t"
9571 "LI $dst, #0\n"
9572 "done:" %}
9573 size(16);
9574 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9575 ins_pipe(pipe_class_compare);
9576 %}
9577
9578 // AndI 0b0..010..0 + ConvI2B
9579 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9580 match(Set dst (Conv2B (AndI src mask)));
9581 predicate(UseRotateAndMaskInstructionsPPC64);
9582 ins_cost(DEFAULT_COST);
9583
9584 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9585 size(4);
9586 ins_encode %{
9587 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9588 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9589 %}
9590 ins_pipe(pipe_class_default);
9591 %}
9592
9593 // Convert pointer to boolean.
9594 //
9595 // ptr_to_bool(src) : { 1 if src != 0
9596 // { 0 else
9597 //
9598 // strategy:
9599 // 1) Count leading zeros of 64 bit-value src,
9600 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9601 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9602 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9603
9604 // ConvP2B
9605 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9606 match(Set dst (Conv2B src));
9607 predicate(UseCountLeadingZerosInstructionsPPC64);
9608 ins_cost(DEFAULT_COST);
9609
9610 expand %{
9611 immI shiftAmount %{ 0x6 %}
9612 uimmI16 mask %{ 0x1 %}
9613 iRegIdst tmp1;
9614 iRegIdst tmp2;
9615 countLeadingZerosP(tmp1, src);
9616 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9617 xorI_reg_uimm16(dst, tmp2, mask);
9618 %}
9619 %}
9620
9621 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9622 match(Set dst (Conv2B src));
9623 effect(TEMP crx);
9624 predicate(!UseCountLeadingZerosInstructionsPPC64);
9625 ins_cost(DEFAULT_COST);
9626
9627 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9628 "LI $dst, #0\n\t"
9629 "BEQ $crx, done\n\t"
9630 "LI $dst, #1\n"
9631 "done:" %}
9632 size(16);
9633 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9634 ins_pipe(pipe_class_compare);
9635 %}
9636
9637 // ConvP2B + XorI
9638 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9639 match(Set dst (XorI (Conv2B src) mask));
9640 predicate(UseCountLeadingZerosInstructionsPPC64);
9641 ins_cost(DEFAULT_COST);
9642
9643 expand %{
9644 immI shiftAmount %{ 0x6 %}
9645 iRegIdst tmp1;
9646 countLeadingZerosP(tmp1, src);
9647 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9648 %}
9649 %}
9650
9651 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9652 match(Set dst (XorI (Conv2B src) mask));
9653 effect(TEMP crx);
9654 predicate(!UseCountLeadingZerosInstructionsPPC64);
9655 ins_cost(DEFAULT_COST);
9656
9657 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9658 "LI $dst, #1\n\t"
9659 "BEQ $crx, done\n\t"
9660 "LI $dst, #0\n"
9661 "done:" %}
9662 size(16);
9663 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9664 ins_pipe(pipe_class_compare);
9665 %}
9666
9667 // if src1 < src2, return -1 else return 0
9668 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9669 match(Set dst (CmpLTMask src1 src2));
9670 ins_cost(DEFAULT_COST*4);
9671
9672 expand %{
9673 iRegLdst src1s;
9674 iRegLdst src2s;
9675 iRegLdst diff;
9676 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9677 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9678 subL_reg_reg(diff, src1s, src2s);
9679 // Need to consider >=33 bit result, therefore we need signmaskL.
9680 signmask64I_regL(dst, diff);
9681 %}
9682 %}
9683
9684 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9685 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9686 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9687 size(4);
9688 ins_encode %{
9689 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9690 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9691 %}
9692 ins_pipe(pipe_class_default);
9693 %}
9694
9695 //----------Arithmetic Conversion Instructions---------------------------------
9696
9697 // Convert to Byte -- nop
9698 // Convert to Short -- nop
9699
9700 // Convert to Int
9701
9702 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9703 match(Set dst (RShiftI (LShiftI src amount) amount));
9704 format %{ "EXTSB $dst, $src \t// byte->int" %}
9705 size(4);
9706 ins_encode %{
9707 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9708 __ extsb($dst$$Register, $src$$Register);
9709 %}
9710 ins_pipe(pipe_class_default);
9711 %}
9712
9713 // LShiftI 16 + RShiftI 16 converts short to int.
9714 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9715 match(Set dst (RShiftI (LShiftI src amount) amount));
9716 format %{ "EXTSH $dst, $src \t// short->int" %}
9717 size(4);
9718 ins_encode %{
9719 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9720 __ extsh($dst$$Register, $src$$Register);
9721 %}
9722 ins_pipe(pipe_class_default);
9723 %}
9724
9725 // ConvL2I + ConvI2L: Sign extend int in long register.
9726 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9727 match(Set dst (ConvI2L (ConvL2I src)));
9728
9729 format %{ "EXTSW $dst, $src \t// long->long" %}
9730 size(4);
9731 ins_encode %{
9732 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9733 __ extsw($dst$$Register, $src$$Register);
9734 %}
9735 ins_pipe(pipe_class_default);
9736 %}
9737
9738 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9739 match(Set dst (ConvL2I src));
9740 format %{ "MR $dst, $src \t// long->int" %}
9741 // variable size, 0 or 4
9742 ins_encode %{
9743 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9744 __ mr_if_needed($dst$$Register, $src$$Register);
9745 %}
9746 ins_pipe(pipe_class_default);
9747 %}
9748
9749 instruct convD2IRaw_regD(regD dst, regD src) %{
9750 // no match-rule, false predicate
9751 effect(DEF dst, USE src);
9752 predicate(false);
9753
9754 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9755 size(4);
9756 ins_encode %{
9757 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9758 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9759 %}
9760 ins_pipe(pipe_class_default);
9761 %}
9762
9763 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9764 // no match-rule, false predicate
9765 effect(DEF dst, USE crx, USE src);
9766 predicate(false);
9767
9768 ins_variable_size_depending_on_alignment(true);
9769
9770 format %{ "cmovI $crx, $dst, $src" %}
9771 // Worst case is branch + move + stop, no stop without scheduler.
9772 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9773 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9774 ins_pipe(pipe_class_default);
9775 %}
9776
9777 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9778 // no match-rule, false predicate
9779 effect(DEF dst, USE crx, USE mem);
9780 predicate(false);
9781
9782 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9783 postalloc_expand %{
9784 //
9785 // replaces
9786 //
9787 // region dst crx mem
9788 // \ | | /
9789 // dst=cmovI_bso_stackSlotL_conLvalue0
9790 //
9791 // with
9792 //
9793 // region dst
9794 // \ /
9795 // dst=loadConI16(0)
9796 // |
9797 // ^ region dst crx mem
9798 // | \ | | /
9799 // dst=cmovI_bso_stackSlotL
9800 //
9801
9802 // Create new nodes.
9803 MachNode *m1 = new loadConI16Node();
9804 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9805
9806 // inputs for new nodes
9807 m1->add_req(n_region);
9808 m2->add_req(n_region, n_crx, n_mem);
9809
9810 // precedences for new nodes
9811 m2->add_prec(m1);
9812
9813 // operands for new nodes
9814 m1->_opnds[0] = op_dst;
9815 m1->_opnds[1] = new immI16Oper(0);
9816
9817 m2->_opnds[0] = op_dst;
9818 m2->_opnds[1] = op_crx;
9819 m2->_opnds[2] = op_mem;
9820
9821 // registers for new nodes
9822 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9823 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9824
9825 // Insert new nodes.
9826 nodes->push(m1);
9827 nodes->push(m2);
9828 %}
9829 %}
9830
9831 // Double to Int conversion, NaN is mapped to 0.
9832 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9833 match(Set dst (ConvD2I src));
9834 ins_cost(DEFAULT_COST);
9835
9836 expand %{
9837 regD tmpD;
9838 stackSlotL tmpS;
9839 flagsReg crx;
9840 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9841 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9842 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9843 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9844 %}
9845 %}
9846
9847 instruct convF2IRaw_regF(regF dst, regF src) %{
9848 // no match-rule, false predicate
9849 effect(DEF dst, USE src);
9850 predicate(false);
9851
9852 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9853 size(4);
9854 ins_encode %{
9855 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9856 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9857 %}
9858 ins_pipe(pipe_class_default);
9859 %}
9860
9861 // Float to Int conversion, NaN is mapped to 0.
9862 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9863 match(Set dst (ConvF2I src));
9864 ins_cost(DEFAULT_COST);
9865
9866 expand %{
9867 regF tmpF;
9868 stackSlotL tmpS;
9869 flagsReg crx;
9870 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9871 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9872 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9873 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9874 %}
9875 %}
9876
9877 // Convert to Long
9878
9879 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9880 match(Set dst (ConvI2L src));
9881 format %{ "EXTSW $dst, $src \t// int->long" %}
9882 size(4);
9883 ins_encode %{
9884 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9885 __ extsw($dst$$Register, $src$$Register);
9886 %}
9887 ins_pipe(pipe_class_default);
9888 %}
9889
9890 // Zero-extend: convert unsigned int to long (convUI2L).
9891 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9892 match(Set dst (AndL (ConvI2L src) mask));
9893 ins_cost(DEFAULT_COST);
9894
9895 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9896 size(4);
9897 ins_encode %{
9898 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9899 __ clrldi($dst$$Register, $src$$Register, 32);
9900 %}
9901 ins_pipe(pipe_class_default);
9902 %}
9903
9904 // Zero-extend: convert unsigned int to long in long register.
9905 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9906 match(Set dst (AndL src mask));
9907 ins_cost(DEFAULT_COST);
9908
9909 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9910 size(4);
9911 ins_encode %{
9912 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9913 __ clrldi($dst$$Register, $src$$Register, 32);
9914 %}
9915 ins_pipe(pipe_class_default);
9916 %}
9917
9918 instruct convF2LRaw_regF(regF dst, regF src) %{
9919 // no match-rule, false predicate
9920 effect(DEF dst, USE src);
9921 predicate(false);
9922
9923 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9924 size(4);
9925 ins_encode %{
9926 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9927 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9928 %}
9929 ins_pipe(pipe_class_default);
9930 %}
9931
9932 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9933 // no match-rule, false predicate
9934 effect(DEF dst, USE crx, USE src);
9935 predicate(false);
9936
9937 ins_variable_size_depending_on_alignment(true);
9938
9939 format %{ "cmovL $crx, $dst, $src" %}
9940 // Worst case is branch + move + stop, no stop without scheduler.
9941 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9942 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9943 ins_pipe(pipe_class_default);
9944 %}
9945
9946 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9947 // no match-rule, false predicate
9948 effect(DEF dst, USE crx, USE mem);
9949 predicate(false);
9950
9951 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9952 postalloc_expand %{
9953 //
9954 // replaces
9955 //
9956 // region dst crx mem
9957 // \ | | /
9958 // dst=cmovL_bso_stackSlotL_conLvalue0
9959 //
9960 // with
9961 //
9962 // region dst
9963 // \ /
9964 // dst=loadConL16(0)
9965 // |
9966 // ^ region dst crx mem
9967 // | \ | | /
9968 // dst=cmovL_bso_stackSlotL
9969 //
9970
9971 // Create new nodes.
9972 MachNode *m1 = new loadConL16Node();
9973 MachNode *m2 = new cmovL_bso_stackSlotLNode();
9974
9975 // inputs for new nodes
9976 m1->add_req(n_region);
9977 m2->add_req(n_region, n_crx, n_mem);
9978 m2->add_prec(m1);
9979
9980 // operands for new nodes
9981 m1->_opnds[0] = op_dst;
9982 m1->_opnds[1] = new immL16Oper(0);
9983 m2->_opnds[0] = op_dst;
9984 m2->_opnds[1] = op_crx;
9985 m2->_opnds[2] = op_mem;
9986
9987 // registers for new nodes
9988 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9989 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9990
9991 // Insert new nodes.
9992 nodes->push(m1);
9993 nodes->push(m2);
9994 %}
9995 %}
9996
9997 // Float to Long conversion, NaN is mapped to 0.
9998 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9999 match(Set dst (ConvF2L src));
10000 ins_cost(DEFAULT_COST);
10001
10002 expand %{
10003 regF tmpF;
10004 stackSlotL tmpS;
10005 flagsReg crx;
10006 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10007 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
10008 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
10009 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10010 %}
10011 %}
10012
10013 instruct convD2LRaw_regD(regD dst, regD src) %{
10014 // no match-rule, false predicate
10015 effect(DEF dst, USE src);
10016 predicate(false);
10017
10018 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10019 size(4);
10020 ins_encode %{
10021 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10022 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10023 %}
10024 ins_pipe(pipe_class_default);
10025 %}
10026
10027 // Double to Long conversion, NaN is mapped to 0.
10028 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10029 match(Set dst (ConvD2L src));
10030 ins_cost(DEFAULT_COST);
10031
10032 expand %{
10033 regD tmpD;
10034 stackSlotL tmpS;
10035 flagsReg crx;
10036 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10037 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10038 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10039 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10040 %}
10041 %}
10042
10043 // Convert to Float
10044
10045 // Placed here as needed in expand.
10046 instruct convL2DRaw_regD(regD dst, regD src) %{
10047 // no match-rule, false predicate
10048 effect(DEF dst, USE src);
10049 predicate(false);
10050
10051 format %{ "FCFID $dst, $src \t// convL2D" %}
10052 size(4);
10053 ins_encode %{
10054 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10055 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10056 %}
10057 ins_pipe(pipe_class_default);
10058 %}
10059
10060 // Placed here as needed in expand.
10061 instruct convD2F_reg(regF dst, regD src) %{
10062 match(Set dst (ConvD2F src));
10063 format %{ "FRSP $dst, $src \t// convD2F" %}
10064 size(4);
10065 ins_encode %{
10066 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10067 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10068 %}
10069 ins_pipe(pipe_class_default);
10070 %}
10071
10072 // Integer to Float conversion.
10073 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10074 match(Set dst (ConvI2F src));
10075 predicate(!VM_Version::has_fcfids());
10076 ins_cost(DEFAULT_COST);
10077
10078 expand %{
10079 iRegLdst tmpL;
10080 stackSlotL tmpS;
10081 regD tmpD;
10082 regD tmpD2;
10083 convI2L_reg(tmpL, src); // Sign-extension int to long.
10084 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10085 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10086 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10087 convD2F_reg(dst, tmpD2); // Convert double to float.
10088 %}
10089 %}
10090
10091 instruct convL2FRaw_regF(regF dst, regD src) %{
10092 // no match-rule, false predicate
10093 effect(DEF dst, USE src);
10094 predicate(false);
10095
10096 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10097 size(4);
10098 ins_encode %{
10099 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10100 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10101 %}
10102 ins_pipe(pipe_class_default);
10103 %}
10104
10105 // Integer to Float conversion. Special version for Power7.
10106 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10107 match(Set dst (ConvI2F src));
10108 predicate(VM_Version::has_fcfids());
10109 ins_cost(DEFAULT_COST);
10110
10111 expand %{
10112 iRegLdst tmpL;
10113 stackSlotL tmpS;
10114 regD tmpD;
10115 convI2L_reg(tmpL, src); // Sign-extension int to long.
10116 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10117 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10118 convL2FRaw_regF(dst, tmpD); // Convert to float.
10119 %}
10120 %}
10121
10122 // L2F to avoid runtime call.
10123 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10124 match(Set dst (ConvL2F src));
10125 predicate(VM_Version::has_fcfids());
10126 ins_cost(DEFAULT_COST);
10127
10128 expand %{
10129 stackSlotL tmpS;
10130 regD tmpD;
10131 regL_to_stkL(tmpS, src); // Store long to stack.
10132 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10133 convL2FRaw_regF(dst, tmpD); // Convert to float.
10134 %}
10135 %}
10136
10137 // Moved up as used in expand.
10138 //instruct convD2F_reg(regF dst, regD src) %{%}
10139
10140 // Convert to Double
10141
10142 // Integer to Double conversion.
10143 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10144 match(Set dst (ConvI2D src));
10145 ins_cost(DEFAULT_COST);
10146
10147 expand %{
10148 iRegLdst tmpL;
10149 stackSlotL tmpS;
10150 regD tmpD;
10151 convI2L_reg(tmpL, src); // Sign-extension int to long.
10152 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10153 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10154 convL2DRaw_regD(dst, tmpD); // Convert to double.
10155 %}
10156 %}
10157
10158 // Long to Double conversion
10159 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10160 match(Set dst (ConvL2D src));
10161 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10162
10163 expand %{
10164 regD tmpD;
10165 moveL2D_stack_reg(tmpD, src);
10166 convL2DRaw_regD(dst, tmpD);
10167 %}
10168 %}
10169
10170 instruct convF2D_reg(regD dst, regF src) %{
10171 match(Set dst (ConvF2D src));
10172 format %{ "FMR $dst, $src \t// float->double" %}
10173 // variable size, 0 or 4
10174 ins_encode %{
10175 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10176 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10177 %}
10178 ins_pipe(pipe_class_default);
10179 %}
10180
10181 //----------Control Flow Instructions------------------------------------------
10182 // Compare Instructions
10183
10184 // Compare Integers
10185 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10186 match(Set crx (CmpI src1 src2));
10187 size(4);
10188 format %{ "CMPW $crx, $src1, $src2" %}
10189 ins_encode %{
10190 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10191 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10192 %}
10193 ins_pipe(pipe_class_compare);
10194 %}
10195
10196 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10197 match(Set crx (CmpI src1 src2));
10198 format %{ "CMPWI $crx, $src1, $src2" %}
10199 size(4);
10200 ins_encode %{
10201 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10202 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10203 %}
10204 ins_pipe(pipe_class_compare);
10205 %}
10206
10207 // (src1 & src2) == 0?
10208 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10209 match(Set cr0 (CmpI (AndI src1 src2) zero));
10210 // r0 is killed
10211 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10212 size(4);
10213 ins_encode %{
10214 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10215 __ andi_(R0, $src1$$Register, $src2$$constant);
10216 %}
10217 ins_pipe(pipe_class_compare);
10218 %}
10219
10220 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10221 match(Set crx (CmpL src1 src2));
10222 format %{ "CMPD $crx, $src1, $src2" %}
10223 size(4);
10224 ins_encode %{
10225 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10226 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10227 %}
10228 ins_pipe(pipe_class_compare);
10229 %}
10230
10231 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10232 match(Set crx (CmpL src1 src2));
10233 format %{ "CMPDI $crx, $src1, $src2" %}
10234 size(4);
10235 ins_encode %{
10236 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10237 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10238 %}
10239 ins_pipe(pipe_class_compare);
10240 %}
10241
10242 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10243 match(Set cr0 (CmpL (AndL src1 src2) zero));
10244 // r0 is killed
10245 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10246 size(4);
10247 ins_encode %{
10248 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10249 __ and_(R0, $src1$$Register, $src2$$Register);
10250 %}
10251 ins_pipe(pipe_class_compare);
10252 %}
10253
10254 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10255 match(Set cr0 (CmpL (AndL src1 src2) zero));
10256 // r0 is killed
10257 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10258 size(4);
10259 ins_encode %{
10260 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10261 __ andi_(R0, $src1$$Register, $src2$$constant);
10262 %}
10263 ins_pipe(pipe_class_compare);
10264 %}
10265
10266 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10267 // no match-rule, false predicate
10268 effect(DEF dst, USE crx);
10269 predicate(false);
10270
10271 ins_variable_size_depending_on_alignment(true);
10272
10273 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10274 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10275 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10276 ins_encode %{
10277 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10278 Label done;
10279 // li(Rdst, 0); // equal -> 0
10280 __ beq($crx$$CondRegister, done);
10281 __ li($dst$$Register, 1); // greater -> +1
10282 __ bgt($crx$$CondRegister, done);
10283 __ li($dst$$Register, -1); // unordered or less -> -1
10284 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10285 __ bind(done);
10286 %}
10287 ins_pipe(pipe_class_compare);
10288 %}
10289
10290 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10291 // no match-rule, false predicate
10292 effect(DEF dst, USE crx);
10293 predicate(false);
10294
10295 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10296 postalloc_expand %{
10297 //
10298 // replaces
10299 //
10300 // region crx
10301 // \ |
10302 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10303 //
10304 // with
10305 //
10306 // region
10307 // \
10308 // dst=loadConI16(0)
10309 // |
10310 // ^ region crx
10311 // | \ |
10312 // dst=cmovI_conIvalueMinus1_conIvalue1
10313 //
10314
10315 // Create new nodes.
10316 MachNode *m1 = new loadConI16Node();
10317 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10318
10319 // inputs for new nodes
10320 m1->add_req(n_region);
10321 m2->add_req(n_region, n_crx);
10322 m2->add_prec(m1);
10323
10324 // operands for new nodes
10325 m1->_opnds[0] = op_dst;
10326 m1->_opnds[1] = new immI16Oper(0);
10327 m2->_opnds[0] = op_dst;
10328 m2->_opnds[1] = op_crx;
10329
10330 // registers for new nodes
10331 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10332 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10333
10334 // Insert new nodes.
10335 nodes->push(m1);
10336 nodes->push(m2);
10337 %}
10338 %}
10339
10340 // Manifest a CmpL3 result in an integer register. Very painful.
10341 // This is the test to avoid.
10342 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10343 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10344 match(Set dst (CmpL3 src1 src2));
10345 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10346
10347 expand %{
10348 flagsReg tmp1;
10349 cmpL_reg_reg(tmp1, src1, src2);
10350 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10351 %}
10352 %}
10353
10354 // Implicit range checks.
10355 // A range check in the ideal world has one of the following shapes:
10356 // - (If le (CmpU length index)), (IfTrue throw exception)
10357 // - (If lt (CmpU index length)), (IfFalse throw exception)
10358 //
10359 // Match range check 'If le (CmpU length index)'.
10360 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10361 match(If cmp (CmpU src_length index));
10362 effect(USE labl);
10363 predicate(TrapBasedRangeChecks &&
10364 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10365 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10366 (Matcher::branches_to_uncommon_trap(_leaf)));
10367
10368 ins_is_TrapBasedCheckNode(true);
10369
10370 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10371 size(4);
10372 ins_encode %{
10373 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10374 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10375 __ trap_range_check_le($src_length$$Register, $index$$constant);
10376 } else {
10377 // Both successors are uncommon traps, probability is 0.
10378 // Node got flipped during fixup flow.
10379 assert($cmp$$cmpcode == 0x9, "must be greater");
10380 __ trap_range_check_g($src_length$$Register, $index$$constant);
10381 }
10382 %}
10383 ins_pipe(pipe_class_trap);
10384 %}
10385
10386 // Match range check 'If lt (CmpU index length)'.
10387 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10388 match(If cmp (CmpU src_index src_length));
10389 effect(USE labl);
10390 predicate(TrapBasedRangeChecks &&
10391 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10392 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10393 (Matcher::branches_to_uncommon_trap(_leaf)));
10394
10395 ins_is_TrapBasedCheckNode(true);
10396
10397 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10398 size(4);
10399 ins_encode %{
10400 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10401 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10402 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10403 } else {
10404 // Both successors are uncommon traps, probability is 0.
10405 // Node got flipped during fixup flow.
10406 assert($cmp$$cmpcode == 0x8, "must be less");
10407 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10408 }
10409 %}
10410 ins_pipe(pipe_class_trap);
10411 %}
10412
10413 // Match range check 'If lt (CmpU index length)'.
10414 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10415 match(If cmp (CmpU src_index length));
10416 effect(USE labl);
10417 predicate(TrapBasedRangeChecks &&
10418 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10419 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10420 (Matcher::branches_to_uncommon_trap(_leaf)));
10421
10422 ins_is_TrapBasedCheckNode(true);
10423
10424 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10425 size(4);
10426 ins_encode %{
10427 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10428 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10429 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10430 } else {
10431 // Both successors are uncommon traps, probability is 0.
10432 // Node got flipped during fixup flow.
10433 assert($cmp$$cmpcode == 0x8, "must be less");
10434 __ trap_range_check_l($src_index$$Register, $length$$constant);
10435 }
10436 %}
10437 ins_pipe(pipe_class_trap);
10438 %}
10439
10440 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10441 match(Set crx (CmpU src1 src2));
10442 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10443 size(4);
10444 ins_encode %{
10445 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10446 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10447 %}
10448 ins_pipe(pipe_class_compare);
10449 %}
10450
10451 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10452 match(Set crx (CmpU src1 src2));
10453 size(4);
10454 format %{ "CMPLWI $crx, $src1, $src2" %}
10455 ins_encode %{
10456 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10457 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10458 %}
10459 ins_pipe(pipe_class_compare);
10460 %}
10461
10462 // Implicit zero checks (more implicit null checks).
10463 // No constant pool entries required.
10464 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10465 match(If cmp (CmpN value zero));
10466 effect(USE labl);
10467 predicate(TrapBasedNullChecks &&
10468 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10469 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10470 Matcher::branches_to_uncommon_trap(_leaf));
10471 ins_cost(1);
10472
10473 ins_is_TrapBasedCheckNode(true);
10474
10475 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10476 size(4);
10477 ins_encode %{
10478 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10479 if ($cmp$$cmpcode == 0xA) {
10480 __ trap_null_check($value$$Register);
10481 } else {
10482 // Both successors are uncommon traps, probability is 0.
10483 // Node got flipped during fixup flow.
10484 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10485 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10486 }
10487 %}
10488 ins_pipe(pipe_class_trap);
10489 %}
10490
10491 // Compare narrow oops.
10492 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10493 match(Set crx (CmpN src1 src2));
10494
10495 size(4);
10496 ins_cost(2);
10497 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10498 ins_encode %{
10499 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10500 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10501 %}
10502 ins_pipe(pipe_class_compare);
10503 %}
10504
10505 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10506 match(Set crx (CmpN src1 src2));
10507 // Make this more expensive than zeroCheckN_iReg_imm0.
10508 ins_cost(2);
10509
10510 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10511 size(4);
10512 ins_encode %{
10513 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10514 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10515 %}
10516 ins_pipe(pipe_class_compare);
10517 %}
10518
10519 // Implicit zero checks (more implicit null checks).
10520 // No constant pool entries required.
10521 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10522 match(If cmp (CmpP value zero));
10523 effect(USE labl);
10524 predicate(TrapBasedNullChecks &&
10525 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10526 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10527 Matcher::branches_to_uncommon_trap(_leaf));
10528 ins_cost(1); // Should not be cheaper than zeroCheckN.
10529
10530 ins_is_TrapBasedCheckNode(true);
10531
10532 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10533 size(4);
10534 ins_encode %{
10535 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10536 if ($cmp$$cmpcode == 0xA) {
10537 __ trap_null_check($value$$Register);
10538 } else {
10539 // Both successors are uncommon traps, probability is 0.
10540 // Node got flipped during fixup flow.
10541 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10542 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10543 }
10544 %}
10545 ins_pipe(pipe_class_trap);
10546 %}
10547
10548 // Compare Pointers
10549 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10550 match(Set crx (CmpP src1 src2));
10551 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10552 size(4);
10553 ins_encode %{
10554 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10555 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10556 %}
10557 ins_pipe(pipe_class_compare);
10558 %}
10559
10560 // Used in postalloc expand.
10561 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10562 // This match rule prevents reordering of node before a safepoint.
10563 // This only makes sense if this instructions is used exclusively
10564 // for the expansion of EncodeP!
10565 match(Set crx (CmpP src1 src2));
10566 predicate(false);
10567
10568 format %{ "CMPDI $crx, $src1, $src2" %}
10569 size(4);
10570 ins_encode %{
10571 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10572 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10573 %}
10574 ins_pipe(pipe_class_compare);
10575 %}
10576
10577 //----------Float Compares----------------------------------------------------
10578
10579 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10580 // Needs matchrule, see cmpDUnordered.
10581 match(Set crx (CmpF src1 src2));
10582 // no match-rule, false predicate
10583 predicate(false);
10584
10585 format %{ "cmpFUrd $crx, $src1, $src2" %}
10586 size(4);
10587 ins_encode %{
10588 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10589 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10590 %}
10591 ins_pipe(pipe_class_default);
10592 %}
10593
10594 instruct cmov_bns_less(flagsReg crx) %{
10595 // no match-rule, false predicate
10596 effect(DEF crx);
10597 predicate(false);
10598
10599 ins_variable_size_depending_on_alignment(true);
10600
10601 format %{ "cmov $crx" %}
10602 // Worst case is branch + move + stop, no stop without scheduler.
10603 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10604 ins_encode %{
10605 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10606 Label done;
10607 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10608 __ li(R0, 0);
10609 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10610 // TODO PPC port __ endgroup_if_needed(_size == 16);
10611 __ bind(done);
10612 %}
10613 ins_pipe(pipe_class_default);
10614 %}
10615
10616 // Compare floating, generate condition code.
10617 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10618 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10619 //
10620 // The following code sequence occurs a lot in mpegaudio:
10621 //
10622 // block BXX:
10623 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10624 // cmpFUrd CCR6, F11, F9
10625 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10626 // cmov CCR6
10627 // 8: instruct branchConSched:
10628 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10629 match(Set crx (CmpF src1 src2));
10630 ins_cost(DEFAULT_COST+BRANCH_COST);
10631
10632 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10633 postalloc_expand %{
10634 //
10635 // replaces
10636 //
10637 // region src1 src2
10638 // \ | |
10639 // crx=cmpF_reg_reg
10640 //
10641 // with
10642 //
10643 // region src1 src2
10644 // \ | |
10645 // crx=cmpFUnordered_reg_reg
10646 // |
10647 // ^ region
10648 // | \
10649 // crx=cmov_bns_less
10650 //
10651
10652 // Create new nodes.
10653 MachNode *m1 = new cmpFUnordered_reg_regNode();
10654 MachNode *m2 = new cmov_bns_lessNode();
10655
10656 // inputs for new nodes
10657 m1->add_req(n_region, n_src1, n_src2);
10658 m2->add_req(n_region);
10659 m2->add_prec(m1);
10660
10661 // operands for new nodes
10662 m1->_opnds[0] = op_crx;
10663 m1->_opnds[1] = op_src1;
10664 m1->_opnds[2] = op_src2;
10665 m2->_opnds[0] = op_crx;
10666
10667 // registers for new nodes
10668 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10669 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10670
10671 // Insert new nodes.
10672 nodes->push(m1);
10673 nodes->push(m2);
10674 %}
10675 %}
10676
10677 // Compare float, generate -1,0,1
10678 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10679 match(Set dst (CmpF3 src1 src2));
10680 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10681
10682 expand %{
10683 flagsReg tmp1;
10684 cmpFUnordered_reg_reg(tmp1, src1, src2);
10685 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10686 %}
10687 %}
10688
10689 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10690 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10691 // node right before the conditional move using it.
10692 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10693 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10694 // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10695 // conditional move was supposed to be spilled.
10696 match(Set crx (CmpD src1 src2));
10697 // False predicate, shall not be matched.
10698 predicate(false);
10699
10700 format %{ "cmpFUrd $crx, $src1, $src2" %}
10701 size(4);
10702 ins_encode %{
10703 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10704 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10705 %}
10706 ins_pipe(pipe_class_default);
10707 %}
10708
10709 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10710 match(Set crx (CmpD src1 src2));
10711 ins_cost(DEFAULT_COST+BRANCH_COST);
10712
10713 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10714 postalloc_expand %{
10715 //
10716 // replaces
10717 //
10718 // region src1 src2
10719 // \ | |
10720 // crx=cmpD_reg_reg
10721 //
10722 // with
10723 //
10724 // region src1 src2
10725 // \ | |
10726 // crx=cmpDUnordered_reg_reg
10727 // |
10728 // ^ region
10729 // | \
10730 // crx=cmov_bns_less
10731 //
10732
10733 // create new nodes
10734 MachNode *m1 = new cmpDUnordered_reg_regNode();
10735 MachNode *m2 = new cmov_bns_lessNode();
10736
10737 // inputs for new nodes
10738 m1->add_req(n_region, n_src1, n_src2);
10739 m2->add_req(n_region);
10740 m2->add_prec(m1);
10741
10742 // operands for new nodes
10743 m1->_opnds[0] = op_crx;
10744 m1->_opnds[1] = op_src1;
10745 m1->_opnds[2] = op_src2;
10746 m2->_opnds[0] = op_crx;
10747
10748 // registers for new nodes
10749 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10750 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10751
10752 // Insert new nodes.
10753 nodes->push(m1);
10754 nodes->push(m2);
10755 %}
10756 %}
10757
10758 // Compare double, generate -1,0,1
10759 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10760 match(Set dst (CmpD3 src1 src2));
10761 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10762
10763 expand %{
10764 flagsReg tmp1;
10765 cmpDUnordered_reg_reg(tmp1, src1, src2);
10766 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10767 %}
10768 %}
10769
10770 //----------Branches---------------------------------------------------------
10771 // Jump
10772
10773 // Direct Branch.
10774 instruct branch(label labl) %{
10775 match(Goto);
10776 effect(USE labl);
10777 ins_cost(BRANCH_COST);
10778
10779 format %{ "B $labl" %}
10780 size(4);
10781 ins_encode %{
10782 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10783 Label d; // dummy
10784 __ bind(d);
10785 Label* p = $labl$$label;
10786 // `p' is `NULL' when this encoding class is used only to
10787 // determine the size of the encoded instruction.
10788 Label& l = (NULL == p)? d : *(p);
10789 __ b(l);
10790 %}
10791 ins_pipe(pipe_class_default);
10792 %}
10793
10794 // Conditional Near Branch
10795 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10796 // Same match rule as `branchConFar'.
10797 match(If cmp crx);
10798 effect(USE lbl);
10799 ins_cost(BRANCH_COST);
10800
10801 // If set to 1 this indicates that the current instruction is a
10802 // short variant of a long branch. This avoids using this
10803 // instruction in first-pass matching. It will then only be used in
10804 // the `Shorten_branches' pass.
10805 ins_short_branch(1);
10806
10807 format %{ "B$cmp $crx, $lbl" %}
10808 size(4);
10809 ins_encode( enc_bc(crx, cmp, lbl) );
10810 ins_pipe(pipe_class_default);
10811 %}
10812
10813 // This is for cases when the ppc64 `bc' instruction does not
10814 // reach far enough. So we emit a far branch here, which is more
10815 // expensive.
10816 //
10817 // Conditional Far Branch
10818 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10819 // Same match rule as `branchCon'.
10820 match(If cmp crx);
10821 effect(USE crx, USE lbl);
10822 predicate(!false /* TODO: PPC port HB_Schedule*/);
10823 // Higher cost than `branchCon'.
10824 ins_cost(5*BRANCH_COST);
10825
10826 // This is not a short variant of a branch, but the long variant.
10827 ins_short_branch(0);
10828
10829 format %{ "B_FAR$cmp $crx, $lbl" %}
10830 size(8);
10831 ins_encode( enc_bc_far(crx, cmp, lbl) );
10832 ins_pipe(pipe_class_default);
10833 %}
10834
10835 // Conditional Branch used with Power6 scheduler (can be far or short).
10836 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10837 // Same match rule as `branchCon'.
10838 match(If cmp crx);
10839 effect(USE crx, USE lbl);
10840 predicate(false /* TODO: PPC port HB_Schedule*/);
10841 // Higher cost than `branchCon'.
10842 ins_cost(5*BRANCH_COST);
10843
10844 // Actually size doesn't depend on alignment but on shortening.
10845 ins_variable_size_depending_on_alignment(true);
10846 // long variant.
10847 ins_short_branch(0);
10848
10849 format %{ "B_FAR$cmp $crx, $lbl" %}
10850 size(8); // worst case
10851 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10852 ins_pipe(pipe_class_default);
10853 %}
10854
10855 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10856 match(CountedLoopEnd cmp crx);
10857 effect(USE labl);
10858 ins_cost(BRANCH_COST);
10859
10860 // short variant.
10861 ins_short_branch(1);
10862
10863 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10864 size(4);
10865 ins_encode( enc_bc(crx, cmp, labl) );
10866 ins_pipe(pipe_class_default);
10867 %}
10868
10869 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10870 match(CountedLoopEnd cmp crx);
10871 effect(USE labl);
10872 predicate(!false /* TODO: PPC port HB_Schedule */);
10873 ins_cost(BRANCH_COST);
10874
10875 // Long variant.
10876 ins_short_branch(0);
10877
10878 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10879 size(8);
10880 ins_encode( enc_bc_far(crx, cmp, labl) );
10881 ins_pipe(pipe_class_default);
10882 %}
10883
10884 // Conditional Branch used with Power6 scheduler (can be far or short).
10885 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10886 match(CountedLoopEnd cmp crx);
10887 effect(USE labl);
10888 predicate(false /* TODO: PPC port HB_Schedule */);
10889 // Higher cost than `branchCon'.
10890 ins_cost(5*BRANCH_COST);
10891
10892 // Actually size doesn't depend on alignment but on shortening.
10893 ins_variable_size_depending_on_alignment(true);
10894 // Long variant.
10895 ins_short_branch(0);
10896
10897 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10898 size(8); // worst case
10899 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10900 ins_pipe(pipe_class_default);
10901 %}
10902
10903 // ============================================================================
10904 // Java runtime operations, intrinsics and other complex operations.
10905
10906 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10907 // array for an instance of the superklass. Set a hidden internal cache on a
10908 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10909 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10910 //
10911 // GL TODO: Improve this.
10912 // - result should not be a TEMP
10913 // - Add match rule as on sparc avoiding additional Cmp.
10914 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10915 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10916 match(Set result (PartialSubtypeCheck subklass superklass));
10917 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10918 ins_cost(DEFAULT_COST*10);
10919
10920 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10921 ins_encode %{
10922 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10923 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10924 $tmp_klass$$Register, NULL, $result$$Register);
10925 %}
10926 ins_pipe(pipe_class_default);
10927 %}
10928
10929 // inlined locking and unlocking
10930
10931 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10932 match(Set crx (FastLock oop box));
10933 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10934 predicate(/*(!UseNewFastLockPPC64 || UseBiasedLocking) &&*/ !Compile::current()->use_rtm());
10935
10936 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10937 ins_encode %{
10938 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10939 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10940 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10941 UseBiasedLocking && !UseOptoBiasInlining); // SAPJVM MD 2014-11-06 UseOptoBiasInlining
10942 // If locking was successfull, crx should indicate 'EQ'.
10943 // The compiler generates a branch to the runtime call to
10944 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10945 %}
10946 ins_pipe(pipe_class_compare);
10947 %}
10948
10949 // Separate version for TM. Use bound register for box to enable USE_KILL.
10950 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10951 match(Set crx (FastLock oop box));
10952 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10953 predicate(Compile::current()->use_rtm());
10954
10955 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10956 ins_encode %{
10957 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10958 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10959 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10960 /*Biased Locking*/ false,
10961 _rtm_counters, _stack_rtm_counters,
10962 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10963 /*TM*/ true, ra_->C->profile_rtm());
10964 // If locking was successfull, crx should indicate 'EQ'.
10965 // The compiler generates a branch to the runtime call to
10966 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10967 %}
10968 ins_pipe(pipe_class_compare);
10969 %}
10970
10971 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10972 match(Set crx (FastUnlock oop box));
10973 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10974 predicate(!Compile::current()->use_rtm());
10975
10976 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10977 ins_encode %{
10978 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10979 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10980 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10981 UseBiasedLocking && !UseOptoBiasInlining,
10982 false);
10983 // If unlocking was successfull, crx should indicate 'EQ'.
10984 // The compiler generates a branch to the runtime call to
10985 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10986 %}
10987 ins_pipe(pipe_class_compare);
10988 %}
10989
10990 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10991 match(Set crx (FastUnlock oop box));
10992 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10993 predicate(Compile::current()->use_rtm());
10994
10995 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %}
10996 ins_encode %{
10997 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10998 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10999 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11000 /*Biased Locking*/ false, /*TM*/ true);
11001 // If unlocking was successfull, crx should indicate 'EQ'.
11002 // The compiler generates a branch to the runtime call to
11003 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11004 %}
11005 ins_pipe(pipe_class_compare);
11006 %}
11007
11008 // Align address.
11009 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11010 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11011
11012 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
11013 size(4);
11014 ins_encode %{
11015 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11016 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11017 %}
11018 ins_pipe(pipe_class_default);
11019 %}
11020
11021 // Array size computation.
11022 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11023 match(Set dst (SubL (CastP2X end) (CastP2X start)));
11024
11025 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
11026 size(4);
11027 ins_encode %{
11028 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11029 __ subf($dst$$Register, $start$$Register, $end$$Register);
11030 %}
11031 ins_pipe(pipe_class_default);
11032 %}
11033
11034 // Clear-array with dynamic array-size.
11035 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11036 match(Set dummy (ClearArray cnt base));
11037 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11038 ins_cost(MEMORY_REF_COST);
11039
11040 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11041
11042 format %{ "ClearArray $cnt, $base" %}
11043 ins_encode %{
11044 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11045 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11046 %}
11047 ins_pipe(pipe_class_default);
11048 %}
11049
11050 // String_IndexOf for needle of length 1.
11051 //
11052 // Match needle into immediate operands: no loadConP node needed. Saves one
11053 // register and two instructions over string_indexOf_imm1Node.
11054 //
11055 // Assumes register result differs from all input registers.
11056 //
11057 // Preserves registers haystack, haycnt
11058 // Kills registers tmp1, tmp2
11059 // Defines registers result
11060 //
11061 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11062 //
11063 // Unfortunately this does not match too often. In many situations the AddP is used
11064 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11065 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11066 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11067 iRegIdst tmp1, iRegIdst tmp2,
11068 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11069 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
11070 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11071
11072 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11073
11074 ins_cost(150);
11075 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11076 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11077
11078 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11079 ins_encode %{
11080 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11081 immPOper *needleOper = (immPOper *)$needleImm;
11082 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11083 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11084
11085 __ string_indexof_1($result$$Register,
11086 $haystack$$Register, $haycnt$$Register,
11087 R0, needle_values->char_at(0),
11088 $tmp1$$Register, $tmp2$$Register);
11089 %}
11090 ins_pipe(pipe_class_compare);
11091 %}
11092
11093 // String_IndexOf for needle of length 1.
11094 //
11095 // Special case requires less registers and emits less instructions.
11096 //
11097 // Assumes register result differs from all input registers.
11098 //
11099 // Preserves registers haystack, haycnt
11100 // Kills registers tmp1, tmp2, needle
11101 // Defines registers result
11102 //
11103 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11104 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11105 rscratch2RegP needle, immI_1 needlecntImm,
11106 iRegIdst tmp1, iRegIdst tmp2,
11107 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11108 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11109 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11110 TEMP tmp1, TEMP tmp2);
11111 // Required for EA: check if it is still a type_array.
11112 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11113 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11114 ins_cost(180);
11115
11116 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11117
11118 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11119 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11120 ins_encode %{
11121 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11122 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11123 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11124 guarantee(needle_values, "sanity");
11125 if (needle_values != NULL) {
11126 __ string_indexof_1($result$$Register,
11127 $haystack$$Register, $haycnt$$Register,
11128 R0, needle_values->char_at(0),
11129 $tmp1$$Register, $tmp2$$Register);
11130 } else {
11131 __ string_indexof_1($result$$Register,
11132 $haystack$$Register, $haycnt$$Register,
11133 $needle$$Register, 0,
11134 $tmp1$$Register, $tmp2$$Register);
11135 }
11136 %}
11137 ins_pipe(pipe_class_compare);
11138 %}
11139
11140 // String_IndexOf.
11141 //
11142 // Length of needle as immediate. This saves instruction loading constant needle
11143 // length.
11144 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11145 // completely or do it in vector instruction. This should save registers for
11146 // needlecnt and needle.
11147 //
11148 // Assumes register result differs from all input registers.
11149 // Overwrites haycnt, needlecnt.
11150 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11151 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11152 iRegPsrc needle, uimmI15 needlecntImm,
11153 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11154 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11155 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11156 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11157 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11158 // Required for EA: check if it is still a type_array.
11159 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11160 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11161 ins_cost(250);
11162
11163 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11164
11165 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11166 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11167 ins_encode %{
11168 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11169 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11170 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11171
11172 __ string_indexof($result$$Register,
11173 $haystack$$Register, $haycnt$$Register,
11174 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11175 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11176 %}
11177 ins_pipe(pipe_class_compare);
11178 %}
11179
11180 // StrIndexOf node.
11181 //
11182 // Assumes register result differs from all input registers.
11183 // Overwrites haycnt, needlecnt.
11184 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11185 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11186 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11187 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11188 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11189 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11190 TEMP_DEF result,
11191 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11192 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11193 ins_cost(300);
11194
11195 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11196
11197 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11198 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11199 ins_encode %{
11200 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11201 __ string_indexof($result$$Register,
11202 $haystack$$Register, $haycnt$$Register,
11203 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11204 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11205 %}
11206 ins_pipe(pipe_class_compare);
11207 %}
11208
11209 // String equals with immediate.
11210 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11211 iRegPdst tmp1, iRegPdst tmp2,
11212 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11213 match(Set result (StrEquals (Binary str1 str2) cntImm));
11214 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11215 KILL cr0, KILL cr6, KILL ctr);
11216 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11217 ins_cost(250);
11218
11219 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11220
11221 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11222 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11223 ins_encode %{
11224 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11225 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11226 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11227 %}
11228 ins_pipe(pipe_class_compare);
11229 %}
11230
11231 // String equals.
11232 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11233 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11234 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11235 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11236 match(Set result (StrEquals (Binary str1 str2) cnt));
11237 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11238 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11239 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11240 ins_cost(300);
11241
11242 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11243
11244 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11245 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11246 ins_encode %{
11247 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11248 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11249 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11250 %}
11251 ins_pipe(pipe_class_compare);
11252 %}
11253
11254 // String compare.
11255 // Char[] pointers are passed in.
11256 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11257 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11258 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11259 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11260 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11261 ins_cost(300);
11262
11263 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11264
11265 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11266 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11267 ins_encode %{
11268 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11269 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11270 $result$$Register, $tmp$$Register);
11271 %}
11272 ins_pipe(pipe_class_compare);
11273 %}
11274
11275 //---------- Min/Max Instructions ---------------------------------------------
11276
11277 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11278 match(Set dst (MinI src1 src2));
11279 ins_cost(DEFAULT_COST*6);
11280
11281 expand %{
11282 iRegLdst src1s;
11283 iRegLdst src2s;
11284 iRegLdst diff;
11285 iRegLdst sm;
11286 iRegLdst doz; // difference or zero
11287 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11288 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11289 subL_reg_reg(diff, src2s, src1s);
11290 // Need to consider >=33 bit result, therefore we need signmaskL.
11291 signmask64L_regL(sm, diff);
11292 andL_reg_reg(doz, diff, sm); // <=0
11293 addI_regL_regL(dst, doz, src1s);
11294 %}
11295 %}
11296
11297 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11298 match(Set dst (MaxI src1 src2));
11299 ins_cost(DEFAULT_COST*6);
11300
11301 expand %{
11302 iRegLdst src1s;
11303 iRegLdst src2s;
11304 iRegLdst diff;
11305 iRegLdst sm;
11306 iRegLdst doz; // difference or zero
11307 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11308 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11309 subL_reg_reg(diff, src2s, src1s);
11310 // Need to consider >=33 bit result, therefore we need signmaskL.
11311 signmask64L_regL(sm, diff);
11312 andcL_reg_reg(doz, diff, sm); // >=0
11313 addI_regL_regL(dst, doz, src1s);
11314 %}
11315 %}
11316
11317 //---------- Population Count Instructions ------------------------------------
11318
11319 // Popcnt for Power7.
11320 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11321 match(Set dst (PopCountI src));
11322 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11323 ins_cost(DEFAULT_COST);
11324
11325 format %{ "POPCNTW $dst, $src" %}
11326 size(4);
11327 ins_encode %{
11328 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11329 __ popcntw($dst$$Register, $src$$Register);
11330 %}
11331 ins_pipe(pipe_class_default);
11332 %}
11333
11334 // Popcnt for Power7.
11335 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11336 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11337 match(Set dst (PopCountL src));
11338 ins_cost(DEFAULT_COST);
11339
11340 format %{ "POPCNTD $dst, $src" %}
11341 size(4);
11342 ins_encode %{
11343 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11344 __ popcntd($dst$$Register, $src$$Register);
11345 %}
11346 ins_pipe(pipe_class_default);
11347 %}
11348
11349 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11350 match(Set dst (CountLeadingZerosI src));
11351 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11352 ins_cost(DEFAULT_COST);
11353
11354 format %{ "CNTLZW $dst, $src" %}
11355 size(4);
11356 ins_encode %{
11357 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11358 __ cntlzw($dst$$Register, $src$$Register);
11359 %}
11360 ins_pipe(pipe_class_default);
11361 %}
11362
11363 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11364 match(Set dst (CountLeadingZerosL src));
11365 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11366 ins_cost(DEFAULT_COST);
11367
11368 format %{ "CNTLZD $dst, $src" %}
11369 size(4);
11370 ins_encode %{
11371 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11372 __ cntlzd($dst$$Register, $src$$Register);
11373 %}
11374 ins_pipe(pipe_class_default);
11375 %}
11376
11377 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11378 // no match-rule, false predicate
11379 effect(DEF dst, USE src);
11380 predicate(false);
11381
11382 format %{ "CNTLZD $dst, $src" %}
11383 size(4);
11384 ins_encode %{
11385 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11386 __ cntlzd($dst$$Register, $src$$Register);
11387 %}
11388 ins_pipe(pipe_class_default);
11389 %}
11390
11391 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11392 match(Set dst (CountTrailingZerosI src));
11393 predicate(UseCountLeadingZerosInstructionsPPC64);
11394 ins_cost(DEFAULT_COST);
11395
11396 expand %{
11397 immI16 imm1 %{ (int)-1 %}
11398 immI16 imm2 %{ (int)32 %}
11399 immI_minus1 m1 %{ -1 %}
11400 iRegIdst tmpI1;
11401 iRegIdst tmpI2;
11402 iRegIdst tmpI3;
11403 addI_reg_imm16(tmpI1, src, imm1);
11404 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11405 countLeadingZerosI(tmpI3, tmpI2);
11406 subI_imm16_reg(dst, imm2, tmpI3);
11407 %}
11408 %}
11409
11410 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11411 match(Set dst (CountTrailingZerosL src));
11412 predicate(UseCountLeadingZerosInstructionsPPC64);
11413 ins_cost(DEFAULT_COST);
11414
11415 expand %{
11416 immL16 imm1 %{ (long)-1 %}
11417 immI16 imm2 %{ (int)64 %}
11418 iRegLdst tmpL1;
11419 iRegLdst tmpL2;
11420 iRegIdst tmpL3;
11421 addL_reg_imm16(tmpL1, src, imm1);
11422 andcL_reg_reg(tmpL2, tmpL1, src);
11423 countLeadingZerosL(tmpL3, tmpL2);
11424 subI_imm16_reg(dst, imm2, tmpL3);
11425 %}
11426 %}
11427
11428 // Expand nodes for byte_reverse_int.
11429 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11430 effect(DEF dst, USE src, USE pos, USE shift);
11431 predicate(false);
11432
11433 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11434 size(4);
11435 ins_encode %{
11436 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11437 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11438 %}
11439 ins_pipe(pipe_class_default);
11440 %}
11441
11442 // As insrwi_a, but with USE_DEF.
11443 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11444 effect(USE_DEF dst, USE src, USE pos, USE shift);
11445 predicate(false);
11446
11447 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11448 size(4);
11449 ins_encode %{
11450 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11451 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11452 %}
11453 ins_pipe(pipe_class_default);
11454 %}
11455
11456 // Just slightly faster than java implementation.
11457 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11458 match(Set dst (ReverseBytesI src));
11459 predicate(UseCountLeadingZerosInstructionsPPC64);
11460 ins_cost(DEFAULT_COST);
11461
11462 expand %{
11463 immI16 imm24 %{ (int) 24 %}
11464 immI16 imm16 %{ (int) 16 %}
11465 immI16 imm8 %{ (int) 8 %}
11466 immI16 imm4 %{ (int) 4 %}
11467 immI16 imm0 %{ (int) 0 %}
11468 iRegLdst tmpI1;
11469 iRegLdst tmpI2;
11470 iRegLdst tmpI3;
11471
11472 urShiftI_reg_imm(tmpI1, src, imm24);
11473 insrwi_a(dst, tmpI1, imm24, imm8);
11474 urShiftI_reg_imm(tmpI2, src, imm16);
11475 insrwi(dst, tmpI2, imm8, imm16);
11476 urShiftI_reg_imm(tmpI3, src, imm8);
11477 insrwi(dst, tmpI3, imm8, imm8);
11478 insrwi(dst, src, imm0, imm8);
11479 %}
11480 %}
11481
11482 //---------- Replicate Vector Instructions ------------------------------------
11483
11484 // Insrdi does replicate if src == dst.
11485 instruct repl32(iRegLdst dst) %{
11486 predicate(false);
11487 effect(USE_DEF dst);
11488
11489 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11490 size(4);
11491 ins_encode %{
11492 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11493 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11494 %}
11495 ins_pipe(pipe_class_default);
11496 %}
11497
11498 // Insrdi does replicate if src == dst.
11499 instruct repl48(iRegLdst dst) %{
11500 predicate(false);
11501 effect(USE_DEF dst);
11502
11503 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11504 size(4);
11505 ins_encode %{
11506 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11507 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11508 %}
11509 ins_pipe(pipe_class_default);
11510 %}
11511
11512 // Insrdi does replicate if src == dst.
11513 instruct repl56(iRegLdst dst) %{
11514 predicate(false);
11515 effect(USE_DEF dst);
11516
11517 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11518 size(4);
11519 ins_encode %{
11520 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11521 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11522 %}
11523 ins_pipe(pipe_class_default);
11524 %}
11525
11526 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11527 match(Set dst (ReplicateB src));
11528 predicate(n->as_Vector()->length() == 8);
11529 expand %{
11530 moveReg(dst, src);
11531 repl56(dst);
11532 repl48(dst);
11533 repl32(dst);
11534 %}
11535 %}
11536
11537 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11538 match(Set dst (ReplicateB zero));
11539 predicate(n->as_Vector()->length() == 8);
11540 format %{ "LI $dst, #0 \t// replicate8B" %}
11541 size(4);
11542 ins_encode %{
11543 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11544 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11545 %}
11546 ins_pipe(pipe_class_default);
11547 %}
11548
11549 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11550 match(Set dst (ReplicateB src));
11551 predicate(n->as_Vector()->length() == 8);
11552 format %{ "LI $dst, #-1 \t// replicate8B" %}
11553 size(4);
11554 ins_encode %{
11555 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11556 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11557 %}
11558 ins_pipe(pipe_class_default);
11559 %}
11560
11561 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11562 match(Set dst (ReplicateS src));
11563 predicate(n->as_Vector()->length() == 4);
11564 expand %{
11565 moveReg(dst, src);
11566 repl48(dst);
11567 repl32(dst);
11568 %}
11569 %}
11570
11571 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11572 match(Set dst (ReplicateS zero));
11573 predicate(n->as_Vector()->length() == 4);
11574 format %{ "LI $dst, #0 \t// replicate4C" %}
11575 size(4);
11576 ins_encode %{
11577 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11578 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11579 %}
11580 ins_pipe(pipe_class_default);
11581 %}
11582
11583 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11584 match(Set dst (ReplicateS src));
11585 predicate(n->as_Vector()->length() == 4);
11586 format %{ "LI $dst, -1 \t// replicate4C" %}
11587 size(4);
11588 ins_encode %{
11589 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11590 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11591 %}
11592 ins_pipe(pipe_class_default);
11593 %}
11594
11595 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11596 match(Set dst (ReplicateI src));
11597 predicate(n->as_Vector()->length() == 2);
11598 ins_cost(2 * DEFAULT_COST);
11599 expand %{
11600 moveReg(dst, src);
11601 repl32(dst);
11602 %}
11603 %}
11604
11605 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11606 match(Set dst (ReplicateI zero));
11607 predicate(n->as_Vector()->length() == 2);
11608 format %{ "LI $dst, #0 \t// replicate4C" %}
11609 size(4);
11610 ins_encode %{
11611 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11612 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11613 %}
11614 ins_pipe(pipe_class_default);
11615 %}
11616
11617 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11618 match(Set dst (ReplicateI src));
11619 predicate(n->as_Vector()->length() == 2);
11620 format %{ "LI $dst, -1 \t// replicate4C" %}
11621 size(4);
11622 ins_encode %{
11623 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11624 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11625 %}
11626 ins_pipe(pipe_class_default);
11627 %}
11628
11629 // Move float to int register via stack, replicate.
11630 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11631 match(Set dst (ReplicateF src));
11632 predicate(n->as_Vector()->length() == 2);
11633 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11634 expand %{
11635 stackSlotL tmpS;
11636 iRegIdst tmpI;
11637 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11638 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11639 moveReg(dst, tmpI); // Move int to long reg.
11640 repl32(dst); // Replicate bitpattern.
11641 %}
11642 %}
11643
11644 // Replicate scalar constant to packed float values in Double register
11645 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11646 match(Set dst (ReplicateF src));
11647 predicate(n->as_Vector()->length() == 2);
11648 ins_cost(5 * DEFAULT_COST);
11649
11650 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11651 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11652 %}
11653
11654 // Replicate scalar zero constant to packed float values in Double register
11655 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11656 match(Set dst (ReplicateF zero));
11657 predicate(n->as_Vector()->length() == 2);
11658
11659 format %{ "LI $dst, #0 \t// replicate2F" %}
11660 ins_encode %{
11661 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11662 __ li($dst$$Register, 0x0);
11663 %}
11664 ins_pipe(pipe_class_default);
11665 %}
11666
11667
11668 //----------Overflow Math Instructions-----------------------------------------
11669
11670 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
11671 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
11672 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
11673
11674 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11675 match(Set cr0 (OverflowAddL op1 op2));
11676
11677 format %{ "add_ $op1, $op2\t# overflow check long" %}
11678 ins_encode %{
11679 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11680 __ li(R0, 0);
11681 __ mtxer(R0); // clear XER.SO
11682 __ addo_(R0, $op1$$Register, $op2$$Register);
11683 %}
11684 ins_pipe(pipe_class_default);
11685 %}
11686
11687 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11688 match(Set cr0 (OverflowSubL op1 op2));
11689
11690 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %}
11691 ins_encode %{
11692 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11693 __ li(R0, 0);
11694 __ mtxer(R0); // clear XER.SO
11695 __ subfo_(R0, $op2$$Register, $op1$$Register);
11696 %}
11697 ins_pipe(pipe_class_default);
11698 %}
11699
11700 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
11701 match(Set cr0 (OverflowSubL zero op2));
11702
11703 format %{ "nego_ R0, $op2\t# overflow check long" %}
11704 ins_encode %{
11705 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11706 __ li(R0, 0);
11707 __ mtxer(R0); // clear XER.SO
11708 __ nego_(R0, $op2$$Register);
11709 %}
11710 ins_pipe(pipe_class_default);
11711 %}
11712
11713 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11714 match(Set cr0 (OverflowMulL op1 op2));
11715
11716 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
11717 ins_encode %{
11718 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11719 __ li(R0, 0);
11720 __ mtxer(R0); // clear XER.SO
11721 __ mulldo_(R0, $op1$$Register, $op2$$Register);
11722 %}
11723 ins_pipe(pipe_class_default);
11724 %}
11725
11726
11727 // ============================================================================
11728 // Safepoint Instruction
11729
11730 instruct safePoint_poll(iRegPdst poll) %{
11731 match(SafePoint poll);
11732 predicate(LoadPollAddressFromThread);
11733
11734 // It caused problems to add the effect that r0 is killed, but this
11735 // effect no longer needs to be mentioned, since r0 is not contained
11736 // in a reg_class.
11737
11738 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11739 size(4);
11740 ins_encode( enc_poll(0x0, poll) );
11741 ins_pipe(pipe_class_default);
11742 %}
11743
11744 // Safepoint without per-thread support. Load address of page to poll
11745 // as constant.
11746 // Rscratch2RegP is R12.
11747 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11748 // a seperate node so that the oop map is at the right location.
11749 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11750 match(SafePoint poll);
11751 predicate(!LoadPollAddressFromThread);
11752
11753 // It caused problems to add the effect that r0 is killed, but this
11754 // effect no longer needs to be mentioned, since r0 is not contained
11755 // in a reg_class.
11756
11757 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11758 ins_encode( enc_poll(0x0, poll) );
11759 ins_pipe(pipe_class_default);
11760 %}
11761
11762 // ============================================================================
11763 // Call Instructions
11764
11765 // Call Java Static Instruction
11766
11767 // Schedulable version of call static node.
11768 instruct CallStaticJavaDirect(method meth) %{
11769 match(CallStaticJava);
11770 effect(USE meth);
11771 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11772 ins_cost(CALL_COST);
11773
11774 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11775
11776 format %{ "CALL,static $meth \t// ==> " %}
11777 size(4);
11778 ins_encode( enc_java_static_call(meth) );
11779 ins_pipe(pipe_class_call);
11780 %}
11781
11782 // Schedulable version of call static node.
11783 instruct CallStaticJavaDirectHandle(method meth) %{
11784 match(CallStaticJava);
11785 effect(USE meth);
11786 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11787 ins_cost(CALL_COST);
11788
11789 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11790
11791 format %{ "CALL,static $meth \t// ==> " %}
11792 ins_encode( enc_java_handle_call(meth) );
11793 ins_pipe(pipe_class_call);
11794 %}
11795
11796 // Call Java Dynamic Instruction
11797
11798 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11799 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11800 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11801 // The call destination must still be placed in the constant pool.
11802 instruct CallDynamicJavaDirectSched(method meth) %{
11803 match(CallDynamicJava); // To get all the data fields we need ...
11804 effect(USE meth);
11805 predicate(false); // ... but never match.
11806
11807 ins_field_load_ic_hi_node(loadConL_hiNode*);
11808 ins_field_load_ic_node(loadConLNode*);
11809 ins_num_consts(1 /* 1 patchable constant: call destination */);
11810
11811 format %{ "BL \t// dynamic $meth ==> " %}
11812 size(4);
11813 ins_encode( enc_java_dynamic_call_sched(meth) );
11814 ins_pipe(pipe_class_call);
11815 %}
11816
11817 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11818 // We use postalloc expanded calls if we use inline caches
11819 // and do not update method data.
11820 //
11821 // This instruction has two constants: inline cache (IC) and call destination.
11822 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11823 // one constant.
11824 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11825 match(CallDynamicJava);
11826 effect(USE meth);
11827 predicate(UseInlineCaches);
11828 ins_cost(CALL_COST);
11829
11830 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11831
11832 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11833 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11834 %}
11835
11836 // Compound version of call dynamic java
11837 // We use postalloc expanded calls if we use inline caches
11838 // and do not update method data.
11839 instruct CallDynamicJavaDirect(method meth) %{
11840 match(CallDynamicJava);
11841 effect(USE meth);
11842 predicate(!UseInlineCaches);
11843 ins_cost(CALL_COST);
11844
11845 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11846 ins_num_consts(4);
11847
11848 format %{ "CALL,dynamic $meth \t// ==> " %}
11849 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11850 ins_pipe(pipe_class_call);
11851 %}
11852
11853 // Call Runtime Instruction
11854
11855 instruct CallRuntimeDirect(method meth) %{
11856 match(CallRuntime);
11857 effect(USE meth);
11858 ins_cost(CALL_COST);
11859
11860 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11861 // env for callee, C-toc.
11862 ins_num_consts(3);
11863
11864 format %{ "CALL,runtime" %}
11865 ins_encode( enc_java_to_runtime_call(meth) );
11866 ins_pipe(pipe_class_call);
11867 %}
11868
11869 // Call Leaf
11870
11871 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11872 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11873 effect(DEF dst, USE src);
11874
11875 ins_num_consts(1);
11876
11877 format %{ "MTCTR $src" %}
11878 size(4);
11879 ins_encode( enc_leaf_call_mtctr(src) );
11880 ins_pipe(pipe_class_default);
11881 %}
11882
11883 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11884 instruct CallLeafDirect(method meth) %{
11885 match(CallLeaf); // To get the data all the data fields we need ...
11886 effect(USE meth);
11887 predicate(false); // but never match.
11888
11889 format %{ "BCTRL \t// leaf call $meth ==> " %}
11890 size(4);
11891 ins_encode %{
11892 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11893 __ bctrl();
11894 %}
11895 ins_pipe(pipe_class_call);
11896 %}
11897
11898 // postalloc expand of CallLeafDirect.
11899 // Load adress to call from TOC, then bl to it.
11900 instruct CallLeafDirect_Ex(method meth) %{
11901 match(CallLeaf);
11902 effect(USE meth);
11903 ins_cost(CALL_COST);
11904
11905 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11906 // env for callee, C-toc.
11907 ins_num_consts(3);
11908
11909 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11910 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11911 %}
11912
11913 // Call runtime without safepoint - same as CallLeaf.
11914 // postalloc expand of CallLeafNoFPDirect.
11915 // Load adress to call from TOC, then bl to it.
11916 instruct CallLeafNoFPDirect_Ex(method meth) %{
11917 match(CallLeafNoFP);
11918 effect(USE meth);
11919 ins_cost(CALL_COST);
11920
11921 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11922 // env for callee, C-toc.
11923 ins_num_consts(3);
11924
11925 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11926 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11927 %}
11928
11929 // Tail Call; Jump from runtime stub to Java code.
11930 // Also known as an 'interprocedural jump'.
11931 // Target of jump will eventually return to caller.
11932 // TailJump below removes the return address.
11933 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11934 match(TailCall jump_target method_oop);
11935 ins_cost(CALL_COST);
11936
11937 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11938 "BCTR \t// tail call" %}
11939 size(8);
11940 ins_encode %{
11941 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11942 __ mtctr($jump_target$$Register);
11943 __ bctr();
11944 %}
11945 ins_pipe(pipe_class_call);
11946 %}
11947
11948 // Return Instruction
11949 instruct Ret() %{
11950 match(Return);
11951 format %{ "BLR \t// branch to link register" %}
11952 size(4);
11953 ins_encode %{
11954 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11955 // LR is restored in MachEpilogNode. Just do the RET here.
11956 __ blr();
11957 %}
11958 ins_pipe(pipe_class_default);
11959 %}
11960
11961 // Tail Jump; remove the return address; jump to target.
11962 // TailCall above leaves the return address around.
11963 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11964 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11965 // "restore" before this instruction (in Epilogue), we need to materialize it
11966 // in %i0.
11967 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11968 match(TailJump jump_target ex_oop);
11969 ins_cost(CALL_COST);
11970
11971 format %{ "LD R4_ARG2 = LR\n\t"
11972 "MTCTR $jump_target\n\t"
11973 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11974 size(12);
11975 ins_encode %{
11976 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11977 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11978 __ mtctr($jump_target$$Register);
11979 __ bctr();
11980 %}
11981 ins_pipe(pipe_class_call);
11982 %}
11983
11984 // Create exception oop: created by stack-crawling runtime code.
11985 // Created exception is now available to this handler, and is setup
11986 // just prior to jumping to this handler. No code emitted.
11987 instruct CreateException(rarg1RegP ex_oop) %{
11988 match(Set ex_oop (CreateEx));
11989 ins_cost(0);
11990
11991 format %{ " -- \t// exception oop; no code emitted" %}
11992 size(0);
11993 ins_encode( /*empty*/ );
11994 ins_pipe(pipe_class_default);
11995 %}
11996
11997 // Rethrow exception: The exception oop will come in the first
11998 // argument position. Then JUMP (not call) to the rethrow stub code.
11999 instruct RethrowException() %{
12000 match(Rethrow);
12001 ins_cost(CALL_COST);
12002
12003 format %{ "Jmp rethrow_stub" %}
12004 ins_encode %{
12005 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12006 cbuf.set_insts_mark();
12007 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12008 %}
12009 ins_pipe(pipe_class_call);
12010 %}
12011
12012 // Die now.
12013 instruct ShouldNotReachHere() %{
12014 match(Halt);
12015 ins_cost(CALL_COST);
12016
12017 format %{ "ShouldNotReachHere" %}
12018 size(4);
12019 ins_encode %{
12020 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12021 __ trap_should_not_reach_here();
12022 %}
12023 ins_pipe(pipe_class_default);
12024 %}
12025
12026 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
12027 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12028 // Get a DEF on threadRegP, no costs, no encoding, use
12029 // 'ins_should_rematerialize(true)' to avoid spilling.
12030 instruct tlsLoadP(threadRegP dst) %{
12031 match(Set dst (ThreadLocal));
12032 ins_cost(0);
12033
12034 ins_should_rematerialize(true);
12035
12036 format %{ " -- \t// $dst=Thread::current(), empty" %}
12037 size(0);
12038 ins_encode( /*empty*/ );
12039 ins_pipe(pipe_class_empty);
12040 %}
12041
12042 //---Some PPC specific nodes---------------------------------------------------
12043
12044 // Stop a group.
12045 instruct endGroup() %{
12046 ins_cost(0);
12047
12048 ins_is_nop(true);
12049
12050 format %{ "End Bundle (ori r1, r1, 0)" %}
12051 size(4);
12052 ins_encode %{
12053 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12054 __ endgroup();
12055 %}
12056 ins_pipe(pipe_class_default);
12057 %}
12058
12059 // Nop instructions
12060
12061 instruct fxNop() %{
12062 ins_cost(0);
12063
12064 ins_is_nop(true);
12065
12066 format %{ "fxNop" %}
12067 size(4);
12068 ins_encode %{
12069 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12070 __ nop();
12071 %}
12072 ins_pipe(pipe_class_default);
12073 %}
12074
12075 instruct fpNop0() %{
12076 ins_cost(0);
12077
12078 ins_is_nop(true);
12079
12080 format %{ "fpNop0" %}
12081 size(4);
12082 ins_encode %{
12083 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12084 __ fpnop0();
12085 %}
12086 ins_pipe(pipe_class_default);
12087 %}
12088
12089 instruct fpNop1() %{
12090 ins_cost(0);
12091
12092 ins_is_nop(true);
12093
12094 format %{ "fpNop1" %}
12095 size(4);
12096 ins_encode %{
12097 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12098 __ fpnop1();
12099 %}
12100 ins_pipe(pipe_class_default);
12101 %}
12102
12103 instruct brNop0() %{
12104 ins_cost(0);
12105 size(4);
12106 format %{ "brNop0" %}
12107 ins_encode %{
12108 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12109 __ brnop0();
12110 %}
12111 ins_is_nop(true);
12112 ins_pipe(pipe_class_default);
12113 %}
12114
12115 instruct brNop1() %{
12116 ins_cost(0);
12117
12118 ins_is_nop(true);
12119
12120 format %{ "brNop1" %}
12121 size(4);
12122 ins_encode %{
12123 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12124 __ brnop1();
12125 %}
12126 ins_pipe(pipe_class_default);
12127 %}
12128
12129 instruct brNop2() %{
12130 ins_cost(0);
12131
12132 ins_is_nop(true);
12133
12134 format %{ "brNop2" %}
12135 size(4);
12136 ins_encode %{
12137 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12138 __ brnop2();
12139 %}
12140 ins_pipe(pipe_class_default);
12141 %}
12142
12143 //----------PEEPHOLE RULES-----------------------------------------------------
12144 // These must follow all instruction definitions as they use the names
12145 // defined in the instructions definitions.
12146 //
12147 // peepmatch ( root_instr_name [preceeding_instruction]* );
12148 //
12149 // peepconstraint %{
12150 // (instruction_number.operand_name relational_op instruction_number.operand_name
12151 // [, ...] );
12152 // // instruction numbers are zero-based using left to right order in peepmatch
12153 //
12154 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12155 // // provide an instruction_number.operand_name for each operand that appears
12156 // // in the replacement instruction's match rule
12157 //
12158 // ---------VM FLAGS---------------------------------------------------------
12159 //
12160 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12161 //
12162 // Each peephole rule is given an identifying number starting with zero and
12163 // increasing by one in the order seen by the parser. An individual peephole
12164 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12165 // on the command-line.
12166 //
12167 // ---------CURRENT LIMITATIONS----------------------------------------------
12168 //
12169 // Only match adjacent instructions in same basic block
12170 // Only equality constraints
12171 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12172 // Only one replacement instruction
12173 //
12174 // ---------EXAMPLE----------------------------------------------------------
12175 //
12176 // // pertinent parts of existing instructions in architecture description
12177 // instruct movI(eRegI dst, eRegI src) %{
12178 // match(Set dst (CopyI src));
12179 // %}
12180 //
12181 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12182 // match(Set dst (AddI dst src));
12183 // effect(KILL cr);
12184 // %}
12185 //
12186 // // Change (inc mov) to lea
12187 // peephole %{
12188 // // increment preceeded by register-register move
12189 // peepmatch ( incI_eReg movI );
12190 // // require that the destination register of the increment
12191 // // match the destination register of the move
12192 // peepconstraint ( 0.dst == 1.dst );
12193 // // construct a replacement instruction that sets
12194 // // the destination to ( move's source register + one )
12195 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12196 // %}
12197 //
12198 // Implementation no longer uses movX instructions since
12199 // machine-independent system no longer uses CopyX nodes.
12200 //
12201 // peephole %{
12202 // peepmatch ( incI_eReg movI );
12203 // peepconstraint ( 0.dst == 1.dst );
12204 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12205 // %}
12206 //
12207 // peephole %{
12208 // peepmatch ( decI_eReg movI );
12209 // peepconstraint ( 0.dst == 1.dst );
12210 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12211 // %}
12212 //
12213 // peephole %{
12214 // peepmatch ( addI_eReg_imm movI );
12215 // peepconstraint ( 0.dst == 1.dst );
12216 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12217 // %}
12218 //
12219 // peephole %{
12220 // peepmatch ( addP_eReg_imm movP );
12221 // peepconstraint ( 0.dst == 1.dst );
12222 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12223 // %}
12224
12225 // // Change load of spilled value to only a spill
12226 // instruct storeI(memory mem, eRegI src) %{
12227 // match(Set mem (StoreI mem src));
12228 // %}
12229 //
12230 // instruct loadI(eRegI dst, memory mem) %{
12231 // match(Set dst (LoadI mem));
12232 // %}
12233 //
12234 peephole %{
12235 peepmatch ( loadI storeI );
12236 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12237 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12238 %}
12239
12240 peephole %{
12241 peepmatch ( loadL storeL );
12242 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12243 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12244 %}
12245
12246 peephole %{
12247 peepmatch ( loadP storeP );
12248 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12249 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12250 %}
12251
12252 //----------SMARTSPILL RULES---------------------------------------------------
12253 // These must follow all instruction definitions as they use the names
12254 // defined in the instructions definitions.