1 /*
2 * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2015 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP
27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP
28
29 #include "asm/register.hpp"
30
31 // Address is an abstraction used to represent a memory location
32 // as used in assembler instructions.
33 // PPC instructions grok either baseReg + indexReg or baseReg + disp.
34 // So far we do not use this as simplification by this class is low
35 // on PPC with its simple addressing mode. Use RegisterOrConstant to
36 // represent an offset.
37 class Address VALUE_OBJ_CLASS_SPEC {
38 };
39
40 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
41 private:
42 address _address;
43 RelocationHolder _rspec;
44
45 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
46 switch (rtype) {
47 case relocInfo::external_word_type:
48 return external_word_Relocation::spec(addr);
49 case relocInfo::internal_word_type:
50 return internal_word_Relocation::spec(addr);
51 case relocInfo::opt_virtual_call_type:
52 return opt_virtual_call_Relocation::spec();
53 case relocInfo::static_call_type:
54 return static_call_Relocation::spec();
55 case relocInfo::runtime_call_type:
56 return runtime_call_Relocation::spec();
57 case relocInfo::none:
58 return RelocationHolder();
59 default:
60 ShouldNotReachHere();
61 return RelocationHolder();
62 }
63 }
64
65 protected:
66 // creation
67 AddressLiteral() : _address(NULL), _rspec(NULL) {}
68
69 public:
70 AddressLiteral(address addr, RelocationHolder const& rspec)
71 : _address(addr),
72 _rspec(rspec) {}
73
74 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
75 : _address((address) addr),
76 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
77
78 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
79 : _address((address) addr),
80 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
81
82 intptr_t value() const { return (intptr_t) _address; }
83
84 const RelocationHolder& rspec() const { return _rspec; }
85 };
86
87 // Argument is an abstraction used to represent an outgoing
88 // actual argument or an incoming formal parameter, whether
89 // it resides in memory or in a register, in a manner consistent
90 // with the PPC Application Binary Interface, or ABI. This is
91 // often referred to as the native or C calling convention.
92
93 class Argument VALUE_OBJ_CLASS_SPEC {
94 private:
95 int _number; // The number of the argument.
96 public:
97 enum {
98 // Only 8 registers may contain integer parameters.
99 n_register_parameters = 8,
100 // Can have up to 8 floating registers.
101 n_float_register_parameters = 8,
102
103 // PPC C calling conventions.
104 // The first eight arguments are passed in int regs if they are int.
105 n_int_register_parameters_c = 8,
106 // The first thirteen float arguments are passed in float regs.
107 n_float_register_parameters_c = 13,
108 // Only the first 8 parameters are not placed on the stack. Aix disassembly
109 // shows that xlC places all float args after argument 8 on the stack AND
110 // in a register. This is not documented, but we follow this convention, too.
111 n_regs_not_on_stack_c = 8,
112 };
113 // creation
114 Argument(int number) : _number(number) {}
115
116 int number() const { return _number; }
117
118 // Locating register-based arguments:
119 bool is_register() const { return _number < n_register_parameters; }
120
121 Register as_register() const {
122 assert(is_register(), "must be a register argument");
123 return as_Register(number() + R3_ARG1->encoding());
124 }
125 };
126
127 #if !defined(ABI_ELFv2)
128 // A ppc64 function descriptor.
129 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC {
130 private:
131 address _entry;
132 address _toc;
133 address _env;
134
135 public:
136 inline address entry() const { return _entry; }
137 inline address toc() const { return _toc; }
138 inline address env() const { return _env; }
139
140 inline void set_entry(address entry) { _entry = entry; }
141 inline void set_toc( address toc) { _toc = toc; }
142 inline void set_env( address env) { _env = env; }
143
144 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
145 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); }
146 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); }
147
148 // Friend functions can be called without loading toc and env.
149 enum {
150 friend_toc = 0xcafe,
151 friend_env = 0xc0de
152 };
153
154 inline bool is_friend_function() const {
155 return (toc() == (address) friend_toc) && (env() == (address) friend_env);
156 }
157
158 // Constructor for stack-allocated instances.
159 FunctionDescriptor() {
160 _entry = (address) 0xbad;
161 _toc = (address) 0xbad;
162 _env = (address) 0xbad;
163 }
164 };
165 #endif
166
167 class Assembler : public AbstractAssembler {
168 protected:
169 // Displacement routines
170 static void print_instruction(int inst);
171 static int patched_branch(int dest_pos, int inst, int inst_pos);
172 static int branch_destination(int inst, int pos);
173
174 friend class AbstractAssembler;
175
176 // Code patchers need various routines like inv_wdisp()
177 friend class NativeInstruction;
178 friend class NativeGeneralJump;
179 friend class Relocation;
180
181 public:
182
183 enum shifts {
184 XO_21_29_SHIFT = 2,
185 XO_21_30_SHIFT = 1,
186 XO_27_29_SHIFT = 2,
187 XO_30_31_SHIFT = 0,
188 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15
189 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20
190 RS_SHIFT = 21u, // RS field in bits 21 -- 25
191 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31
192 };
193
194 enum opcdxos_masks {
195 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
196 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
197 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
198 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
199 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
200 // trap instructions
201 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
202 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT),
203 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
204 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
205 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
206 STD_OPCODE_MASK = LD_OPCODE_MASK,
207 STDU_OPCODE_MASK = STD_OPCODE_MASK,
208 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
209 STDUX_OPCODE_MASK = STDX_OPCODE_MASK,
210 STW_OPCODE_MASK = (63u << OPCODE_SHIFT),
211 STWU_OPCODE_MASK = STW_OPCODE_MASK,
212 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
213 STWUX_OPCODE_MASK = STWX_OPCODE_MASK,
214 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT),
215 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT),
216 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
217 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
218 };
219
220 enum opcdxos {
221 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1),
222 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1),
223 ADDI_OPCODE = (14u << OPCODE_SHIFT),
224 ADDIS_OPCODE = (15u << OPCODE_SHIFT),
225 ADDIC__OPCODE = (13u << OPCODE_SHIFT),
226 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1),
227 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1),
228 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1),
229 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1),
230 SUBFIC_OPCODE = (8u << OPCODE_SHIFT),
231 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
232 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
233 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
234 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
235 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
236 MULLI_OPCODE = (7u << OPCODE_SHIFT),
237 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1),
238 ANDI_OPCODE = (28u << OPCODE_SHIFT),
239 ANDIS_OPCODE = (29u << OPCODE_SHIFT),
240 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1),
241 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1),
242 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1),
243 ORI_OPCODE = (24u << OPCODE_SHIFT),
244 ORIS_OPCODE = (25u << OPCODE_SHIFT),
245 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1),
246 XORI_OPCODE = (26u << OPCODE_SHIFT),
247 XORIS_OPCODE = (27u << OPCODE_SHIFT),
248
249 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
250
251 RLWINM_OPCODE = (21u << OPCODE_SHIFT),
252 CLRRWI_OPCODE = RLWINM_OPCODE,
253 CLRLWI_OPCODE = RLWINM_OPCODE,
254
255 RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
256
257 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
258 SLWI_OPCODE = RLWINM_OPCODE,
259 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
260 SRWI_OPCODE = RLWINM_OPCODE,
261 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
262 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
263
264 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
265 CMPI_OPCODE = (11u << OPCODE_SHIFT),
266 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
267 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
268
269 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
270
271 // Special purpose registers
272 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
273 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
274
275 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
276 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
277
278 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
279 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
280
281 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
282 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
283
284 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
285 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
286
287 // Attention: Higher and lower half are inserted in reversed order.
288 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
289 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
290 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
291 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
292 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
293 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
294 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
295 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
296
297 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
298 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
299
300 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
301
302 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
303 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
304 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
305
306 // condition register logic instructions
307 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
308 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
309 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
310 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
311 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
312 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
313 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
314 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
315
316 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
317 BXX_OPCODE = (18u << OPCODE_SHIFT),
318 BCXX_OPCODE = (16u << OPCODE_SHIFT),
319
320 // CTR-related opcodes
321 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
322
323 LWZ_OPCODE = (32u << OPCODE_SHIFT),
324 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
325 LWZU_OPCODE = (33u << OPCODE_SHIFT),
326 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1),
327
328 LHA_OPCODE = (42u << OPCODE_SHIFT),
329 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
330 LHAU_OPCODE = (43u << OPCODE_SHIFT),
331
332 LHZ_OPCODE = (40u << OPCODE_SHIFT),
333 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
334 LHZU_OPCODE = (41u << OPCODE_SHIFT),
335 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1),
336
337 LBZ_OPCODE = (34u << OPCODE_SHIFT),
338 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
339 LBZU_OPCODE = (35u << OPCODE_SHIFT),
340
341 STW_OPCODE = (36u << OPCODE_SHIFT),
342 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
343 STWU_OPCODE = (37u << OPCODE_SHIFT),
344 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
345
346 STH_OPCODE = (44u << OPCODE_SHIFT),
347 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
348 STHU_OPCODE = (45u << OPCODE_SHIFT),
349
350 STB_OPCODE = (38u << OPCODE_SHIFT),
351 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
352 STBU_OPCODE = (39u << OPCODE_SHIFT),
353
354 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
355 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
356 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM
357
358 // 32 bit opcode encodings
359
360 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM
361 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
362
363 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM
364
365 // 64 bit opcode encodings
366
367 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
368 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
369 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM
370
371 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
372 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
373 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
374 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
375
376 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM
377 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
378 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
379 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
380
381 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
382
383 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
384 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
385 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
386
387 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
388 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
389 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
390 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
391
392 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
393 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
394 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
395
396
397 // opcodes only used for floating arithmetic
398 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
399 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
400 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
401 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
402 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
403 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
404 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
405 // on Power7. Do not use.
406 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
407 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
408 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
409 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
410 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
411 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
412 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
413 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1),
414 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1),
415 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1),
416 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1),
417 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1),
418 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1),
419
420 // PPC64-internal FPU conversion opcodes
421 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1),
422 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1),
423 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1),
424 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1),
425 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1),
426 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1),
427 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1),
428
429 // WARNING: using fmadd results in a non-compliant vm. Some floating
430 // point tck tests will fail.
431 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
432 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
433 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
434 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
435 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
436 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
437 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
438 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
439
440 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1),
441 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1),
442 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1),
443 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1),
444 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
445 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
446
447 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
448 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
449 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
450 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
451 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
452 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
453
454 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
455 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
456
457 // Vector instruction support for >= Power6
458 // Vector Storage Access
459 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
460 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
461 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
462 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
463 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
464 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
465 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
466 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
467 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
468 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
469 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
470 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
471
472 // Vector Permute and Formatting
473 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
474 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
475 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
476 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
477 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
478 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
479 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
480 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
481 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
482 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
483 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
484 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
485 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
486 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
487 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
488
489 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
490 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
491 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
492 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
493 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
494 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
495
496 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
497 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
498 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
499 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
500 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
501 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
502
503 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
504 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
505
506 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
507 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
508 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
509 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
510 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
511
512 // Vector Integer
513 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
514 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
515 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
516 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
517 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
518 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
519 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
520 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
521 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
522 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
523 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ),
524 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ),
525 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ),
526 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ),
527 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ),
528 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ),
529 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ),
530 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ),
531 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ),
532 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ),
533
534 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ),
535 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ),
536 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ),
537 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ),
538 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ),
539 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ),
540 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ),
541 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ),
542 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ),
543 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ),
544 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ),
545 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ),
546 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ),
547 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ),
548 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ),
549 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ),
550 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ),
551
552 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ),
553 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ),
554 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ),
555 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ),
556 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ),
557
558 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ),
559 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ),
560 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ),
561 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ),
562 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ),
563 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ),
564
565 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ),
566 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ),
567 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ),
568 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ),
569 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ),
570 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ),
571 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ),
572 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ),
573 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ),
574 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ),
575 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ),
576 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ),
577
578 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ),
579 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ),
580 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ),
581 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ),
582 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ),
583 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ),
584 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ),
585 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ),
586 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ),
587
588 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ),
589 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ),
590 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ),
591 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ),
592 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ),
593 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ),
594 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ),
595 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ),
596 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ),
597 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ),
598 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ),
599 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ),
600 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ),
601 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ),
602 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ),
603 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ),
604 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ),
605
606 // Vector Floating-Point
607 // not implemented yet
608
609 // Vector Status and Control
610 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
611 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
612
613 // AES (introduced with Power 8)
614 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
615 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
616 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
617 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
618 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
619
620 // SHA (introduced with Power 8)
621 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
622 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
623
624 // Vector Binary Polynomial Multiplication (introduced with Power 8)
625 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
626 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
627 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
628 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
629
630 // Vector Permute and Xor (introduced with Power 8)
631 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
632
633 // Transactional Memory instructions (introduced with Power 8)
634 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
635 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
636 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
637 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
638 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
639 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
640 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
641 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
642 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),
643
644 // Icache and dcache related instructions
645 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
646 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
647 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
648 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
649
650 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
651 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
652 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
653
654 // Instruction synchronization
655 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
656 // Memory barriers
657 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
658 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
659
660 // Trap instructions
661 TDI_OPCODE = (2u << OPCODE_SHIFT),
662 TWI_OPCODE = (3u << OPCODE_SHIFT),
663 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
664 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
665
666 // Atomics.
667 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
668 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
669 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
670 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
671
672 };
673
674 // Trap instructions TO bits
675 enum trap_to_bits {
676 // single bits
677 traptoLessThanSigned = 1 << 4, // 0, left end
678 traptoGreaterThanSigned = 1 << 3,
679 traptoEqual = 1 << 2,
680 traptoLessThanUnsigned = 1 << 1,
681 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
682
683 // compound ones
684 traptoUnconditional = (traptoLessThanSigned |
685 traptoGreaterThanSigned |
686 traptoEqual |
687 traptoLessThanUnsigned |
688 traptoGreaterThanUnsigned)
689 };
690
691 // Branch hints BH field
692 enum branch_hint_bh {
693 // bclr cases:
694 bhintbhBCLRisReturn = 0,
695 bhintbhBCLRisNotReturnButSame = 1,
696 bhintbhBCLRisNotPredictable = 3,
697
698 // bcctr cases:
699 bhintbhBCCTRisNotReturnButSame = 0,
700 bhintbhBCCTRisNotPredictable = 3
701 };
702
703 // Branch prediction hints AT field
704 enum branch_hint_at {
705 bhintatNoHint = 0, // at=00
706 bhintatIsNotTaken = 2, // at=10
707 bhintatIsTaken = 3 // at=11
708 };
709
710 // Branch prediction hints
711 enum branch_hint_concept {
712 // Use the same encoding as branch_hint_at to simply code.
713 bhintNoHint = bhintatNoHint,
714 bhintIsNotTaken = bhintatIsNotTaken,
715 bhintIsTaken = bhintatIsTaken
716 };
717
718 // Used in BO field of branch instruction.
719 enum branch_condition {
720 bcondCRbiIs0 = 4, // bo=001at
721 bcondCRbiIs1 = 12, // bo=011at
722 bcondAlways = 20 // bo=10100
723 };
724
725 // Branch condition with combined prediction hints.
726 enum branch_condition_with_hint {
727 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint,
728 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
729 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken,
730 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint,
731 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
732 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken,
733 };
734
735 // Elemental Memory Barriers (>=Power 8)
736 enum Elemental_Membar_mask_bits {
737 StoreStore = 1 << 0,
738 StoreLoad = 1 << 1,
739 LoadStore = 1 << 2,
740 LoadLoad = 1 << 3
741 };
742
743 // Branch prediction hints.
744 inline static int add_bhint_to_boint(const int bhint, const int boint) {
745 switch (boint) {
746 case bcondCRbiIs0:
747 case bcondCRbiIs1:
748 // branch_hint and branch_hint_at have same encodings
749 assert( (int)bhintNoHint == (int)bhintatNoHint
750 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
751 && (int)bhintIsTaken == (int)bhintatIsTaken,
752 "wrong encodings");
753 assert((bhint & 0x03) == bhint, "wrong encodings");
754 return (boint & ~0x03) | bhint;
755 case bcondAlways:
756 // no branch_hint
757 return boint;
758 default:
759 ShouldNotReachHere();
760 return 0;
761 }
762 }
763
764 // Extract bcond from boint.
765 inline static int inv_boint_bcond(const int boint) {
766 int r_bcond = boint & ~0x03;
767 assert(r_bcond == bcondCRbiIs0 ||
768 r_bcond == bcondCRbiIs1 ||
769 r_bcond == bcondAlways,
770 "bad branch condition");
771 return r_bcond;
772 }
773
774 // Extract bhint from boint.
775 inline static int inv_boint_bhint(const int boint) {
776 int r_bhint = boint & 0x03;
777 assert(r_bhint == bhintatNoHint ||
778 r_bhint == bhintatIsNotTaken ||
779 r_bhint == bhintatIsTaken,
780 "bad branch hint");
781 return r_bhint;
782 }
783
784 // Calculate opposite of given bcond.
785 inline static int opposite_bcond(const int bcond) {
786 switch (bcond) {
787 case bcondCRbiIs0:
788 return bcondCRbiIs1;
789 case bcondCRbiIs1:
790 return bcondCRbiIs0;
791 default:
792 ShouldNotReachHere();
793 return 0;
794 }
795 }
796
797 // Calculate opposite of given bhint.
798 inline static int opposite_bhint(const int bhint) {
799 switch (bhint) {
800 case bhintatNoHint:
801 return bhintatNoHint;
802 case bhintatIsNotTaken:
803 return bhintatIsTaken;
804 case bhintatIsTaken:
805 return bhintatIsNotTaken;
806 default:
807 ShouldNotReachHere();
808 return 0;
809 }
810 }
811
812 // PPC branch instructions
813 enum ppcops {
814 b_op = 18,
815 bc_op = 16,
816 bcr_op = 19
817 };
818
819 enum Condition {
820 negative = 0,
821 less = 0,
822 positive = 1,
823 greater = 1,
824 zero = 2,
825 equal = 2,
826 summary_overflow = 3,
827 };
828
829 public:
830 // Helper functions for groups of instructions
831
832 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
833
834 // instruction must start at passed address
835 static int instr_len(unsigned char *instr) { return BytesPerInstWord; }
836
837 // instruction must be left-justified in argument
838 static int instr_len(unsigned long instr) { return BytesPerInstWord; }
839
840 // longest instructions
841 static int instr_maxlen() { return BytesPerInstWord; }
842
843 // Test if x is within signed immediate range for nbits.
844 static bool is_simm(int x, unsigned int nbits) {
845 assert(0 < nbits && nbits < 32, "out of bounds");
846 const int min = -( ((int)1) << nbits-1 );
847 const int maxplus1 = ( ((int)1) << nbits-1 );
848 return min <= x && x < maxplus1;
849 }
850
851 static bool is_simm(jlong x, unsigned int nbits) {
852 assert(0 < nbits && nbits < 64, "out of bounds");
853 const jlong min = -( ((jlong)1) << nbits-1 );
854 const jlong maxplus1 = ( ((jlong)1) << nbits-1 );
855 return min <= x && x < maxplus1;
856 }
857
858 // Test if x is within unsigned immediate range for nbits
859 static bool is_uimm(int x, unsigned int nbits) {
860 assert(0 < nbits && nbits < 32, "out of bounds");
861 const int maxplus1 = ( ((int)1) << nbits );
862 return 0 <= x && x < maxplus1;
863 }
864
865 static bool is_uimm(jlong x, unsigned int nbits) {
866 assert(0 < nbits && nbits < 64, "out of bounds");
867 const jlong maxplus1 = ( ((jlong)1) << nbits );
868 return 0 <= x && x < maxplus1;
869 }
870
871 protected:
872 // helpers
873
874 // X is supposed to fit in a field "nbits" wide
875 // and be sign-extended. Check the range.
876 static void assert_signed_range(intptr_t x, int nbits) {
877 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
878 "value out of range");
879 }
880
881 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
882 assert((x & 3) == 0, "not word aligned");
883 assert_signed_range(x, nbits + 2);
884 }
885
886 static void assert_unsigned_const(int x, int nbits) {
887 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
888 }
889
890 static int fmask(juint hi_bit, juint lo_bit) {
891 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
892 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
893 }
894
895 // inverse of u_field
896 static int inv_u_field(int x, int hi_bit, int lo_bit) {
897 juint r = juint(x) >> lo_bit;
898 r &= fmask(hi_bit, lo_bit);
899 return int(r);
900 }
901
902 // signed version: extract from field and sign-extend
903 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
904 x = x << (31-hi_bit);
905 x = x >> (31-hi_bit+lo_bit);
906 return x;
907 }
908
909 static int u_field(int x, int hi_bit, int lo_bit) {
910 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
911 int r = x << lo_bit;
912 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
913 return r;
914 }
915
916 // Same as u_field for signed values
917 static int s_field(int x, int hi_bit, int lo_bit) {
918 int nbits = hi_bit - lo_bit + 1;
919 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
920 "value out of range");
921 x &= fmask(hi_bit, lo_bit);
922 int r = x << lo_bit;
923 return r;
924 }
925
926 // inv_op for ppc instructions
927 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
928
929 // Determine target address from li, bd field of branch instruction.
930 static intptr_t inv_li_field(int x) {
931 intptr_t r = inv_s_field_ppc(x, 25, 2);
932 r = (r << 2);
933 return r;
934 }
935 static intptr_t inv_bd_field(int x, intptr_t pos) {
936 intptr_t r = inv_s_field_ppc(x, 15, 2);
937 r = (r << 2) + pos;
938 return r;
939 }
940
941 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
942 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
943 // Extract instruction fields from instruction words.
944 public:
945 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); }
946 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); }
947 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); }
948 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
949 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); }
950 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
951 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
952 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; }
953 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); }
954 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); }
955 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); }
956 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); }
957 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
958 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }
959
960 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
961 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
962
963 // instruction fields
964 static int aa( int x) { return opp_u_field(x, 30, 30); }
965 static int ba( int x) { return opp_u_field(x, 15, 11); }
966 static int bb( int x) { return opp_u_field(x, 20, 16); }
967 static int bc( int x) { return opp_u_field(x, 25, 21); }
968 static int bd( int x) { return opp_s_field(x, 29, 16); }
969 static int bf( ConditionRegister cr) { return bf(cr->encoding()); }
970 static int bf( int x) { return opp_u_field(x, 8, 6); }
971 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); }
972 static int bfa( int x) { return opp_u_field(x, 13, 11); }
973 static int bh( int x) { return opp_u_field(x, 20, 19); }
974 static int bi( int x) { return opp_u_field(x, 15, 11); }
975 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
976 static int bo( int x) { return opp_u_field(x, 10, 6); }
977 static int bt( int x) { return opp_u_field(x, 10, 6); }
978 static int d1( int x) { return opp_s_field(x, 31, 16); }
979 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
980 static int eh( int x) { return opp_u_field(x, 31, 31); }
981 static int flm( int x) { return opp_u_field(x, 14, 7); }
982 static int fra( FloatRegister r) { return fra(r->encoding());}
983 static int frb( FloatRegister r) { return frb(r->encoding());}
984 static int frc( FloatRegister r) { return frc(r->encoding());}
985 static int frs( FloatRegister r) { return frs(r->encoding());}
986 static int frt( FloatRegister r) { return frt(r->encoding());}
987 static int fra( int x) { return opp_u_field(x, 15, 11); }
988 static int frb( int x) { return opp_u_field(x, 20, 16); }
989 static int frc( int x) { return opp_u_field(x, 25, 21); }
990 static int frs( int x) { return opp_u_field(x, 10, 6); }
991 static int frt( int x) { return opp_u_field(x, 10, 6); }
992 static int fxm( int x) { return opp_u_field(x, 19, 12); }
993 static int l10( int x) { return opp_u_field(x, 10, 10); }
994 static int l15( int x) { return opp_u_field(x, 15, 15); }
995 static int l910( int x) { return opp_u_field(x, 10, 9); }
996 static int e1215( int x) { return opp_u_field(x, 15, 12); }
997 static int lev( int x) { return opp_u_field(x, 26, 20); }
998 static int li( int x) { return opp_s_field(x, 29, 6); }
999 static int lk( int x) { return opp_u_field(x, 31, 31); }
1000 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
1001 static int me2630( int x) { return opp_u_field(x, 30, 26); }
1002 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1003 static int me2126( int x) { return mb2126(x); }
1004 static int nb( int x) { return opp_u_field(x, 20, 16); }
1005 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
1006 static int oe( int x) { return opp_u_field(x, 21, 21); }
1007 static int ra( Register r) { return ra(r->encoding()); }
1008 static int ra( int x) { return opp_u_field(x, 15, 11); }
1009 static int rb( Register r) { return rb(r->encoding()); }
1010 static int rb( int x) { return opp_u_field(x, 20, 16); }
1011 static int rc( int x) { return opp_u_field(x, 31, 31); }
1012 static int rs( Register r) { return rs(r->encoding()); }
1013 static int rs( int x) { return opp_u_field(x, 10, 6); }
1014 // we don't want to use R0 in memory accesses, because it has value `0' then
1015 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
1016 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); }
1017
1018 // register r is target
1019 static int rt( Register r) { return rs(r); }
1020 static int rt( int x) { return rs(x); }
1021 static int rta( Register r) { return ra(r); }
1022 static int rta0mem( Register r) { rta(r); return ra0mem(r); }
1023
1024 static int sh1620( int x) { return opp_u_field(x, 20, 16); }
1025 static int sh30( int x) { return opp_u_field(x, 30, 30); }
1026 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
1027 static int si( int x) { return opp_s_field(x, 31, 16); }
1028 static int spr( int x) { return opp_u_field(x, 20, 11); }
1029 static int sr( int x) { return opp_u_field(x, 15, 12); }
1030 static int tbr( int x) { return opp_u_field(x, 20, 11); }
1031 static int th( int x) { return opp_u_field(x, 10, 7); }
1032 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
1033 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
1034 static int to( int x) { return opp_u_field(x, 10, 6); }
1035 static int u( int x) { return opp_u_field(x, 19, 16); }
1036 static int ui( int x) { return opp_u_field(x, 31, 16); }
1037
1038 // Support vector instructions for >= Power6.
1039 static int vra( int x) { return opp_u_field(x, 15, 11); }
1040 static int vrb( int x) { return opp_u_field(x, 20, 16); }
1041 static int vrc( int x) { return opp_u_field(x, 25, 21); }
1042 static int vrs( int x) { return opp_u_field(x, 10, 6); }
1043 static int vrt( int x) { return opp_u_field(x, 10, 6); }
1044
1045 static int vra( VectorRegister r) { return vra(r->encoding());}
1046 static int vrb( VectorRegister r) { return vrb(r->encoding());}
1047 static int vrc( VectorRegister r) { return vrc(r->encoding());}
1048 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1049 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1050
1051 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1052 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1053 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1054 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1055
1056 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1057 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1058 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1059 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1060 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1061 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1062 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1063
1064 protected:
1065 // Compute relative address for branch.
1066 static intptr_t disp(intptr_t x, intptr_t off) {
1067 int xx = x - off;
1068 xx = xx >> 2;
1069 return xx;
1070 }
1071
1072 public:
1073 // signed immediate, in low bits, nbits long
1074 static int simm(int x, int nbits) {
1075 assert_signed_range(x, nbits);
1076 return x & ((1 << nbits) - 1);
1077 }
1078
1079 // unsigned immediate, in low bits, nbits long
1080 static int uimm(int x, int nbits) {
1081 assert_unsigned_const(x, nbits);
1082 return x & ((1 << nbits) - 1);
1083 }
1084
1085 static void set_imm(int* instr, short s) {
1086 // imm is always in the lower 16 bits of the instruction,
1087 // so this is endian-neutral. Same for the get_imm below.
1088 uint32_t w = *(uint32_t *)instr;
1089 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
1090 }
1091
1092 static int get_imm(address a, int instruction_number) {
1093 return (short)((int *)a)[instruction_number];
1094 }
1095
1096 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); }
1097 static inline int lo16_unsigned(int x) { return x & 0xffff; }
1098
1099 protected:
1100
1101 // Extract the top 32 bits in a 64 bit word.
1102 static int32_t hi32(int64_t x) {
1103 int32_t r = int32_t((uint64_t)x >> 32);
1104 return r;
1105 }
1106
1107 public:
1108
1109 static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1110 return ((addr + (a - 1)) & ~(a - 1));
1111 }
1112
1113 static inline bool is_aligned(unsigned int addr, unsigned int a) {
1114 return (0 == addr % a);
1115 }
1116
1117 void flush() {
1118 AbstractAssembler::flush();
1119 }
1120
1121 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
1122 inline void emit_data(int);
1123 inline void emit_data(int, RelocationHolder const&);
1124 inline void emit_data(int, relocInfo::relocType rtype);
1125
1126 // Emit an address.
1127 inline address emit_addr(const address addr = NULL);
1128
1129 #if !defined(ABI_ELFv2)
1130 // Emit a function descriptor with the specified entry point, TOC,
1131 // and ENV. If the entry point is NULL, the descriptor will point
1132 // just past the descriptor.
1133 // Use values from friend functions as defaults.
1134 inline address emit_fd(address entry = NULL,
1135 address toc = (address) FunctionDescriptor::friend_toc,
1136 address env = (address) FunctionDescriptor::friend_env);
1137 #endif
1138
1139 /////////////////////////////////////////////////////////////////////////////////////
1140 // PPC instructions
1141 /////////////////////////////////////////////////////////////////////////////////////
1142
1143 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1144 // immediates. The normal instruction encoders enforce that r0 is not
1145 // passed to them. Use either extended mnemonics encoders or the special ra0
1146 // versions.
1147
1148 // Issue an illegal instruction.
1149 inline void illtrap();
1150 static inline bool is_illtrap(int x);
1151
1152 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1153 inline void addi( Register d, Register a, int si16);
1154 inline void addis(Register d, Register a, int si16);
1155 private:
1156 inline void addi_r0ok( Register d, Register a, int si16);
1157 inline void addis_r0ok(Register d, Register a, int si16);
1158 public:
1159 inline void addic_( Register d, Register a, int si16);
1160 inline void subfic( Register d, Register a, int si16);
1161 inline void add( Register d, Register a, Register b);
1162 inline void add_( Register d, Register a, Register b);
1163 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec.
1164 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability.
1165 inline void subf_( Register d, Register a, Register b);
1166 inline void addc( Register d, Register a, Register b);
1167 inline void addc_( Register d, Register a, Register b);
1168 inline void subfc( Register d, Register a, Register b);
1169 inline void subfc_( Register d, Register a, Register b);
1170 inline void adde( Register d, Register a, Register b);
1171 inline void adde_( Register d, Register a, Register b);
1172 inline void subfe( Register d, Register a, Register b);
1173 inline void subfe_( Register d, Register a, Register b);
1174 inline void neg( Register d, Register a);
1175 inline void neg_( Register d, Register a);
1176 inline void mulli( Register d, Register a, int si16);
1177 inline void mulld( Register d, Register a, Register b);
1178 inline void mulld_( Register d, Register a, Register b);
1179 inline void mullw( Register d, Register a, Register b);
1180 inline void mullw_( Register d, Register a, Register b);
1181 inline void mulhw( Register d, Register a, Register b);
1182 inline void mulhw_( Register d, Register a, Register b);
1183 inline void mulhd( Register d, Register a, Register b);
1184 inline void mulhd_( Register d, Register a, Register b);
1185 inline void mulhdu( Register d, Register a, Register b);
1186 inline void mulhdu_(Register d, Register a, Register b);
1187 inline void divd( Register d, Register a, Register b);
1188 inline void divd_( Register d, Register a, Register b);
1189 inline void divw( Register d, Register a, Register b);
1190 inline void divw_( Register d, Register a, Register b);
1191
1192 // extended mnemonics
1193 inline void li( Register d, int si16);
1194 inline void lis( Register d, int si16);
1195 inline void addir(Register d, int si16, Register a);
1196
1197 static bool is_addi(int x) {
1198 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1199 }
1200 static bool is_addis(int x) {
1201 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1202 }
1203 static bool is_bxx(int x) {
1204 return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1205 }
1206 static bool is_b(int x) {
1207 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1208 }
1209 static bool is_bl(int x) {
1210 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1211 }
1212 static bool is_bcxx(int x) {
1213 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1214 }
1215 static bool is_bxx_or_bcxx(int x) {
1216 return is_bxx(x) || is_bcxx(x);
1217 }
1218 static bool is_bctrl(int x) {
1219 return x == 0x4e800421;
1220 }
1221 static bool is_bctr(int x) {
1222 return x == 0x4e800420;
1223 }
1224 static bool is_bclr(int x) {
1225 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1226 }
1227 static bool is_li(int x) {
1228 return is_addi(x) && inv_ra_field(x)==0;
1229 }
1230 static bool is_lis(int x) {
1231 return is_addis(x) && inv_ra_field(x)==0;
1232 }
1233 static bool is_mtctr(int x) {
1234 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1235 }
1236 static bool is_ld(int x) {
1237 return LD_OPCODE == (x & LD_OPCODE_MASK);
1238 }
1239 static bool is_std(int x) {
1240 return STD_OPCODE == (x & STD_OPCODE_MASK);
1241 }
1242 static bool is_stdu(int x) {
1243 return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1244 }
1245 static bool is_stdx(int x) {
1246 return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1247 }
1248 static bool is_stdux(int x) {
1249 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1250 }
1251 static bool is_stwx(int x) {
1252 return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1253 }
1254 static bool is_stwux(int x) {
1255 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1256 }
1257 static bool is_stw(int x) {
1258 return STW_OPCODE == (x & STW_OPCODE_MASK);
1259 }
1260 static bool is_stwu(int x) {
1261 return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1262 }
1263 static bool is_ori(int x) {
1264 return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1265 };
1266 static bool is_oris(int x) {
1267 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1268 };
1269 static bool is_rldicr(int x) {
1270 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1271 };
1272 static bool is_nop(int x) {
1273 return x == 0x60000000;
1274 }
1275 // endgroup opcode for Power6
1276 static bool is_endgroup(int x) {
1277 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1278 }
1279
1280
1281 private:
1282 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1283 inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1284 inline void cmp( ConditionRegister bf, int l, Register a, Register b);
1285 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1286 inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1287
1288 public:
1289 // extended mnemonics of Compare Instructions
1290 inline void cmpwi( ConditionRegister crx, Register a, int si16);
1291 inline void cmpdi( ConditionRegister crx, Register a, int si16);
1292 inline void cmpw( ConditionRegister crx, Register a, Register b);
1293 inline void cmpd( ConditionRegister crx, Register a, Register b);
1294 inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1295 inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1296 inline void cmplw( ConditionRegister crx, Register a, Register b);
1297 inline void cmpld( ConditionRegister crx, Register a, Register b);
1298
1299 inline void isel( Register d, Register a, Register b, int bc);
1300 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1301 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1302 // Set d = 0 if (cr.cc) equals 1, otherwise b.
1303 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1304
1305 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1306 void andi( Register a, Register s, int ui16); // optimized version
1307 inline void andi_( Register a, Register s, int ui16);
1308 inline void andis_( Register a, Register s, int ui16);
1309 inline void ori( Register a, Register s, int ui16);
1310 inline void oris( Register a, Register s, int ui16);
1311 inline void xori( Register a, Register s, int ui16);
1312 inline void xoris( Register a, Register s, int ui16);
1313 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
1314 inline void and_( Register a, Register s, Register b);
1315 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1316 // SMT-priority change instruction (see SMT instructions below).
1317 inline void or_unchecked(Register a, Register s, Register b);
1318 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
1319 inline void or_( Register a, Register s, Register b);
1320 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword
1321 inline void xor_( Register a, Register s, Register b);
1322 inline void nand( Register a, Register s, Register b);
1323 inline void nand_( Register a, Register s, Register b);
1324 inline void nor( Register a, Register s, Register b);
1325 inline void nor_( Register a, Register s, Register b);
1326 inline void andc( Register a, Register s, Register b);
1327 inline void andc_( Register a, Register s, Register b);
1328 inline void orc( Register a, Register s, Register b);
1329 inline void orc_( Register a, Register s, Register b);
1330 inline void extsb( Register a, Register s);
1331 inline void extsh( Register a, Register s);
1332 inline void extsw( Register a, Register s);
1333
1334 // extended mnemonics
1335 inline void nop();
1336 // NOP for FP and BR units (different versions to allow them to be in one group)
1337 inline void fpnop0();
1338 inline void fpnop1();
1339 inline void brnop0();
1340 inline void brnop1();
1341 inline void brnop2();
1342
1343 inline void mr( Register d, Register s);
1344 inline void ori_opt( Register d, int ui16);
1345 inline void oris_opt(Register d, int ui16);
1346
1347 // endgroup opcode for Power6
1348 inline void endgroup();
1349
1350 // count instructions
1351 inline void cntlzw( Register a, Register s);
1352 inline void cntlzw_( Register a, Register s);
1353 inline void cntlzd( Register a, Register s);
1354 inline void cntlzd_( Register a, Register s);
1355
1356 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1357 inline void sld( Register a, Register s, Register b);
1358 inline void sld_( Register a, Register s, Register b);
1359 inline void slw( Register a, Register s, Register b);
1360 inline void slw_( Register a, Register s, Register b);
1361 inline void srd( Register a, Register s, Register b);
1362 inline void srd_( Register a, Register s, Register b);
1363 inline void srw( Register a, Register s, Register b);
1364 inline void srw_( Register a, Register s, Register b);
1365 inline void srad( Register a, Register s, Register b);
1366 inline void srad_( Register a, Register s, Register b);
1367 inline void sraw( Register a, Register s, Register b);
1368 inline void sraw_( Register a, Register s, Register b);
1369 inline void sradi( Register a, Register s, int sh6);
1370 inline void sradi_( Register a, Register s, int sh6);
1371 inline void srawi( Register a, Register s, int sh5);
1372 inline void srawi_( Register a, Register s, int sh5);
1373
1374 // extended mnemonics for Shift Instructions
1375 inline void sldi( Register a, Register s, int sh6);
1376 inline void sldi_( Register a, Register s, int sh6);
1377 inline void slwi( Register a, Register s, int sh5);
1378 inline void slwi_( Register a, Register s, int sh5);
1379 inline void srdi( Register a, Register s, int sh6);
1380 inline void srdi_( Register a, Register s, int sh6);
1381 inline void srwi( Register a, Register s, int sh5);
1382 inline void srwi_( Register a, Register s, int sh5);
1383
1384 inline void clrrdi( Register a, Register s, int ui6);
1385 inline void clrrdi_( Register a, Register s, int ui6);
1386 inline void clrldi( Register a, Register s, int ui6);
1387 inline void clrldi_( Register a, Register s, int ui6);
1388 inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1389 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1390 inline void extrdi( Register a, Register s, int n, int b);
1391 // testbit with condition register
1392 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1393
1394 // rotate instructions
1395 inline void rotldi( Register a, Register s, int n);
1396 inline void rotrdi( Register a, Register s, int n);
1397 inline void rotlwi( Register a, Register s, int n);
1398 inline void rotrwi( Register a, Register s, int n);
1399
1400 // Rotate Instructions
1401 inline void rldic( Register a, Register s, int sh6, int mb6);
1402 inline void rldic_( Register a, Register s, int sh6, int mb6);
1403 inline void rldicr( Register a, Register s, int sh6, int mb6);
1404 inline void rldicr_( Register a, Register s, int sh6, int mb6);
1405 inline void rldicl( Register a, Register s, int sh6, int mb6);
1406 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1407 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1408 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1409 inline void rldimi( Register a, Register s, int sh6, int mb6);
1410 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1411 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1412 inline void insrdi( Register a, Register s, int n, int b);
1413 inline void insrwi( Register a, Register s, int n, int b);
1414
1415 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1416 // 4 bytes
1417 inline void lwzx( Register d, Register s1, Register s2);
1418 inline void lwz( Register d, int si16, Register s1);
1419 inline void lwzu( Register d, int si16, Register s1);
1420
1421 // 4 bytes
1422 inline void lwax( Register d, Register s1, Register s2);
1423 inline void lwa( Register d, int si16, Register s1);
1424
1425 // 4 bytes reversed
1426 inline void lwbrx( Register d, Register s1, Register s2);
1427
1428 // 2 bytes
1429 inline void lhzx( Register d, Register s1, Register s2);
1430 inline void lhz( Register d, int si16, Register s1);
1431 inline void lhzu( Register d, int si16, Register s1);
1432
1433 // 2 bytes reversed
1434 inline void lhbrx( Register d, Register s1, Register s2);
1435
1436 // 2 bytes
1437 inline void lhax( Register d, Register s1, Register s2);
1438 inline void lha( Register d, int si16, Register s1);
1439 inline void lhau( Register d, int si16, Register s1);
1440
1441 // 1 byte
1442 inline void lbzx( Register d, Register s1, Register s2);
1443 inline void lbz( Register d, int si16, Register s1);
1444 inline void lbzu( Register d, int si16, Register s1);
1445
1446 // 8 bytes
1447 inline void ldx( Register d, Register s1, Register s2);
1448 inline void ld( Register d, int si16, Register s1);
1449 inline void ldu( Register d, int si16, Register s1);
1450
1451 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
1452 inline void stwx( Register d, Register s1, Register s2);
1453 inline void stw( Register d, int si16, Register s1);
1454 inline void stwu( Register d, int si16, Register s1);
1455
1456 inline void sthx( Register d, Register s1, Register s2);
1457 inline void sth( Register d, int si16, Register s1);
1458 inline void sthu( Register d, int si16, Register s1);
1459
1460 inline void stbx( Register d, Register s1, Register s2);
1461 inline void stb( Register d, int si16, Register s1);
1462 inline void stbu( Register d, int si16, Register s1);
1463
1464 inline void stdx( Register d, Register s1, Register s2);
1465 inline void std( Register d, int si16, Register s1);
1466 inline void stdu( Register d, int si16, Register s1);
1467 inline void stdux(Register s, Register a, Register b);
1468
1469 // PPC 1, section 3.3.13 Move To/From System Register Instructions
1470 inline void mtlr( Register s1);
1471 inline void mflr( Register d);
1472 inline void mtctr(Register s1);
1473 inline void mfctr(Register d);
1474 inline void mtcrf(int fxm, Register s);
1475 inline void mfcr( Register d);
1476 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1477 inline void mtcr( Register s);
1478
1479 // Special purpose registers
1480 // Exception Register
1481 inline void mtxer(Register s1);
1482 inline void mfxer(Register d);
1483 // Vector Register Save Register
1484 inline void mtvrsave(Register s1);
1485 inline void mfvrsave(Register d);
1486 // Timebase
1487 inline void mftb(Register d);
1488 // Introduced with Power 8:
1489 // Data Stream Control Register
1490 inline void mtdscr(Register s1);
1491 inline void mfdscr(Register d );
1492 // Transactional Memory Registers
1493 inline void mftfhar(Register d);
1494 inline void mftfiar(Register d);
1495 inline void mftexasr(Register d);
1496 inline void mftexasru(Register d);
1497
1498 // TEXASR bit description
1499 enum transaction_failure_reason {
1500 // Upper half (TEXASRU):
1501 tm_failure_persistent = 7, // The failure is likely to recur on each execution.
1502 tm_disallowed = 8, // The instruction is not permitted.
1503 tm_nesting_of = 9, // The maximum transaction level was exceeded.
1504 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded.
1505 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state.
1506 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor.
1507 tm_trans_cf = 13, // A conflict occurred with another transaction.
1508 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation.
1509 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally.
1510 tm_tabort = 31, // Termination was caused by the execution of an abort instruction.
1511 // Lower half:
1512 tm_suspended = 32, // Failure was recorded in Suspended state.
1513 tm_failure_summary = 36, // Failure has been detected and recorded.
1514 tm_tfiar_exact = 37, // Value in the TFIAR is exact.
1515 tm_rot = 38, // Rollback-only transaction.
1516 };
1517
1518 // PPC 1, section 2.4.1 Branch Instructions
1519 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1520 inline void b( Label& L);
1521 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1522 inline void bl( Label& L);
1523 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1524 inline void bc( int boint, int biint, Label& L);
1525 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1526 inline void bcl(int boint, int biint, Label& L);
1527
1528 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1529 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1530 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1531 relocInfo::relocType rt = relocInfo::none);
1532 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1533 relocInfo::relocType rt = relocInfo::none);
1534
1535 // helper function for b, bcxx
1536 inline bool is_within_range_of_b(address a, address pc);
1537 inline bool is_within_range_of_bcxx(address a, address pc);
1538
1539 // get the destination of a bxx branch (b, bl, ba, bla)
1540 static inline address bxx_destination(address baddr);
1541 static inline address bxx_destination(int instr, address pc);
1542 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1543
1544 // extended mnemonics for branch instructions
1545 inline void blt(ConditionRegister crx, Label& L);
1546 inline void bgt(ConditionRegister crx, Label& L);
1547 inline void beq(ConditionRegister crx, Label& L);
1548 inline void bso(ConditionRegister crx, Label& L);
1549 inline void bge(ConditionRegister crx, Label& L);
1550 inline void ble(ConditionRegister crx, Label& L);
1551 inline void bne(ConditionRegister crx, Label& L);
1552 inline void bns(ConditionRegister crx, Label& L);
1553
1554 // Branch instructions with static prediction hints.
1555 inline void blt_predict_taken( ConditionRegister crx, Label& L);
1556 inline void bgt_predict_taken( ConditionRegister crx, Label& L);
1557 inline void beq_predict_taken( ConditionRegister crx, Label& L);
1558 inline void bso_predict_taken( ConditionRegister crx, Label& L);
1559 inline void bge_predict_taken( ConditionRegister crx, Label& L);
1560 inline void ble_predict_taken( ConditionRegister crx, Label& L);
1561 inline void bne_predict_taken( ConditionRegister crx, Label& L);
1562 inline void bns_predict_taken( ConditionRegister crx, Label& L);
1563 inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1564 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1565 inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1566 inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1567 inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1568 inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1569 inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1570 inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1571
1572 // for use in conjunction with testbitdi:
1573 inline void btrue( ConditionRegister crx, Label& L);
1574 inline void bfalse(ConditionRegister crx, Label& L);
1575
1576 inline void bltl(ConditionRegister crx, Label& L);
1577 inline void bgtl(ConditionRegister crx, Label& L);
1578 inline void beql(ConditionRegister crx, Label& L);
1579 inline void bsol(ConditionRegister crx, Label& L);
1580 inline void bgel(ConditionRegister crx, Label& L);
1581 inline void blel(ConditionRegister crx, Label& L);
1582 inline void bnel(ConditionRegister crx, Label& L);
1583 inline void bnsl(ConditionRegister crx, Label& L);
1584
1585 // extended mnemonics for Branch Instructions via LR
1586 // We use `blr' for returns.
1587 inline void blr(relocInfo::relocType rt = relocInfo::none);
1588
1589 // extended mnemonics for Branch Instructions with CTR
1590 // bdnz means `decrement CTR and jump to L if CTR is not zero'
1591 inline void bdnz(Label& L);
1592 // Decrement and branch if result is zero.
1593 inline void bdz(Label& L);
1594 // we use `bctr[l]' for jumps/calls in function descriptor glue
1595 // code, e.g. calls to runtime functions
1596 inline void bctr( relocInfo::relocType rt = relocInfo::none);
1597 inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1598 // conditional jumps/branches via CTR
1599 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1600 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1601 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1602 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1603
1604 // condition register logic instructions
1605 // NOTE: There's a preferred form: d and s2 should point into the same condition register.
1606 inline void crand( int d, int s1, int s2);
1607 inline void crnand(int d, int s1, int s2);
1608 inline void cror( int d, int s1, int s2);
1609 inline void crxor( int d, int s1, int s2);
1610 inline void crnor( int d, int s1, int s2);
1611 inline void creqv( int d, int s1, int s2);
1612 inline void crandc(int d, int s1, int s2);
1613 inline void crorc( int d, int s1, int s2);
1614
1615 // More convenient version.
1616 int condition_register_bit(ConditionRegister cr, Condition c) {
1617 return 4 * (int)(intptr_t)cr + c;
1618 }
1619 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1620 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1621 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1622 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1623 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1624 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1625 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1626 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1627
1628 // icache and dcache related instructions
1629 inline void icbi( Register s1, Register s2);
1630 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1631 inline void dcbz( Register s1, Register s2);
1632 inline void dcbst( Register s1, Register s2);
1633 inline void dcbf( Register s1, Register s2);
1634
1635 enum ct_cache_specification {
1636 ct_primary_cache = 0,
1637 ct_secondary_cache = 2
1638 };
1639 // dcache read hint
1640 inline void dcbt( Register s1, Register s2);
1641 inline void dcbtct( Register s1, Register s2, int ct);
1642 inline void dcbtds( Register s1, Register s2, int ds);
1643 // dcache write hint
1644 inline void dcbtst( Register s1, Register s2);
1645 inline void dcbtstct(Register s1, Register s2, int ct);
1646
1647 // machine barrier instructions:
1648 //
1649 // - sync two-way memory barrier, aka fence
1650 // - lwsync orders Store|Store,
1651 // Load|Store,
1652 // Load|Load,
1653 // but not Store|Load
1654 // - eieio orders memory accesses for device memory (only)
1655 // - isync invalidates speculatively executed instructions
1656 // From the Power ISA 2.06 documentation:
1657 // "[...] an isync instruction prevents the execution of
1658 // instructions following the isync until instructions
1659 // preceding the isync have completed, [...]"
1660 // From IBM's AIX assembler reference:
1661 // "The isync [...] instructions causes the processor to
1662 // refetch any instructions that might have been fetched
1663 // prior to the isync instruction. The instruction isync
1664 // causes the processor to wait for all previous instructions
1665 // to complete. Then any instructions already fetched are
1666 // discarded and instruction processing continues in the
1667 // environment established by the previous instructions."
1668 //
1669 // semantic barrier instructions:
1670 // (as defined in orderAccess.hpp)
1671 //
1672 // - release orders Store|Store, (maps to lwsync)
1673 // Load|Store
1674 // - acquire orders Load|Store, (maps to lwsync)
1675 // Load|Load
1676 // - fence orders Store|Store, (maps to sync)
1677 // Load|Store,
1678 // Load|Load,
1679 // Store|Load
1680 //
1681 private:
1682 inline void sync(int l);
1683 public:
1684 inline void sync();
1685 inline void lwsync();
1686 inline void ptesync();
1687 inline void eieio();
1688 inline void isync();
1689 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1690
1691 // atomics
1692 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1693 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1694 inline bool lxarx_hint_exclusive_access();
1695 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1696 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1697 inline void stwcx_( Register s, Register a, Register b);
1698 inline void stdcx_( Register s, Register a, Register b);
1699
1700 // Instructions for adjusting thread priority for simultaneous
1701 // multithreading (SMT) on Power5.
1702 private:
1703 inline void smt_prio_very_low();
1704 inline void smt_prio_medium_high();
1705 inline void smt_prio_high();
1706
1707 public:
1708 inline void smt_prio_low();
1709 inline void smt_prio_medium_low();
1710 inline void smt_prio_medium();
1711 // >= Power7
1712 inline void smt_yield();
1713 inline void smt_mdoio();
1714 inline void smt_mdoom();
1715
1716 // trap instructions
1717 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1718 // NOT FOR DIRECT USE!!
1719 protected:
1720 inline void tdi_unchecked(int tobits, Register a, int si16);
1721 inline void twi_unchecked(int tobits, Register a, int si16);
1722 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1723 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1724 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP
1725 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP
1726
1727 static bool is_tdi(int x, int tobits, int ra, int si16) {
1728 return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
1729 && (tobits == inv_to_field(x))
1730 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1731 && (si16 == inv_si_field(x));
1732 }
1733
1734 static bool is_twi(int x, int tobits, int ra, int si16) {
1735 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1736 && (tobits == inv_to_field(x))
1737 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1738 && (si16 == inv_si_field(x));
1739 }
1740
1741 static bool is_twi(int x, int tobits, int ra) {
1742 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1743 && (tobits == inv_to_field(x))
1744 && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
1745 }
1746
1747 static bool is_td(int x, int tobits, int ra, int rb) {
1748 return (TD_OPCODE == (x & TD_OPCODE_MASK))
1749 && (tobits == inv_to_field(x))
1750 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1751 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1752 }
1753
1754 static bool is_tw(int x, int tobits, int ra, int rb) {
1755 return (TW_OPCODE == (x & TW_OPCODE_MASK))
1756 && (tobits == inv_to_field(x))
1757 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1758 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1759 }
1760
1761 public:
1762 // PPC floating point instructions
1763 // PPC 1, section 4.6.2 Floating-Point Load Instructions
1764 inline void lfs( FloatRegister d, int si16, Register a);
1765 inline void lfsu( FloatRegister d, int si16, Register a);
1766 inline void lfsx( FloatRegister d, Register a, Register b);
1767 inline void lfd( FloatRegister d, int si16, Register a);
1768 inline void lfdu( FloatRegister d, int si16, Register a);
1769 inline void lfdx( FloatRegister d, Register a, Register b);
1770
1771 // PPC 1, section 4.6.3 Floating-Point Store Instructions
1772 inline void stfs( FloatRegister s, int si16, Register a);
1773 inline void stfsu( FloatRegister s, int si16, Register a);
1774 inline void stfsx( FloatRegister s, Register a, Register b);
1775 inline void stfd( FloatRegister s, int si16, Register a);
1776 inline void stfdu( FloatRegister s, int si16, Register a);
1777 inline void stfdx( FloatRegister s, Register a, Register b);
1778
1779 // PPC 1, section 4.6.4 Floating-Point Move Instructions
1780 inline void fmr( FloatRegister d, FloatRegister b);
1781 inline void fmr_( FloatRegister d, FloatRegister b);
1782
1783 // inline void mffgpr( FloatRegister d, Register b);
1784 // inline void mftgpr( Register d, FloatRegister b);
1785 inline void cmpb( Register a, Register s, Register b);
1786 inline void popcntb(Register a, Register s);
1787 inline void popcntw(Register a, Register s);
1788 inline void popcntd(Register a, Register s);
1789
1790 inline void fneg( FloatRegister d, FloatRegister b);
1791 inline void fneg_( FloatRegister d, FloatRegister b);
1792 inline void fabs( FloatRegister d, FloatRegister b);
1793 inline void fabs_( FloatRegister d, FloatRegister b);
1794 inline void fnabs( FloatRegister d, FloatRegister b);
1795 inline void fnabs_(FloatRegister d, FloatRegister b);
1796
1797 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
1798 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b);
1799 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
1800 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
1801 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
1802 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b);
1803 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
1804 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
1805 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
1806 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c);
1807 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
1808 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
1809 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
1810 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b);
1811 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
1812 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
1813 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
1814
1815 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
1816 inline void frsp( FloatRegister d, FloatRegister b);
1817 inline void fctid( FloatRegister d, FloatRegister b);
1818 inline void fctidz(FloatRegister d, FloatRegister b);
1819 inline void fctiw( FloatRegister d, FloatRegister b);
1820 inline void fctiwz(FloatRegister d, FloatRegister b);
1821 inline void fcfid( FloatRegister d, FloatRegister b);
1822 inline void fcfids(FloatRegister d, FloatRegister b);
1823
1824 // PPC 1, section 4.6.7 Floating-Point Compare Instructions
1825 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
1826
1827 inline void fsqrt( FloatRegister d, FloatRegister b);
1828 inline void fsqrts(FloatRegister d, FloatRegister b);
1829
1830 // Vector instructions for >= Power6.
1831 inline void lvebx( VectorRegister d, Register s1, Register s2);
1832 inline void lvehx( VectorRegister d, Register s1, Register s2);
1833 inline void lvewx( VectorRegister d, Register s1, Register s2);
1834 inline void lvx( VectorRegister d, Register s1, Register s2);
1835 inline void lvxl( VectorRegister d, Register s1, Register s2);
1836 inline void stvebx( VectorRegister d, Register s1, Register s2);
1837 inline void stvehx( VectorRegister d, Register s1, Register s2);
1838 inline void stvewx( VectorRegister d, Register s1, Register s2);
1839 inline void stvx( VectorRegister d, Register s1, Register s2);
1840 inline void stvxl( VectorRegister d, Register s1, Register s2);
1841 inline void lvsl( VectorRegister d, Register s1, Register s2);
1842 inline void lvsr( VectorRegister d, Register s1, Register s2);
1843 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b);
1844 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b);
1845 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b);
1846 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b);
1847 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b);
1848 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b);
1849 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b);
1850 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b);
1851 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
1852 inline void vupkhpx( VectorRegister d, VectorRegister b);
1853 inline void vupkhsb( VectorRegister d, VectorRegister b);
1854 inline void vupkhsh( VectorRegister d, VectorRegister b);
1855 inline void vupklpx( VectorRegister d, VectorRegister b);
1856 inline void vupklsb( VectorRegister d, VectorRegister b);
1857 inline void vupklsh( VectorRegister d, VectorRegister b);
1858 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
1859 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
1860 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
1861 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
1862 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
1863 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
1864 inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
1865 inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
1866 inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
1867 inline void vspltisb( VectorRegister d, int si5);
1868 inline void vspltish( VectorRegister d, int si5);
1869 inline void vspltisw( VectorRegister d, int si5);
1870 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1871 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1872 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
1873 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4);
1874 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
1875 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
1876 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
1877 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1878 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
1879 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1880 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
1881 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
1882 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
1883 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
1884 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
1885 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
1886 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
1887 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1888 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
1889 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1890 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b);
1891 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b);
1892 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b);
1893 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b);
1894 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b);
1895 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b);
1896 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b);
1897 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b);
1898 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b);
1899 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b);
1900 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b);
1901 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b);
1902 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b);
1903 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b);
1904 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b);
1905 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1906 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
1907 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1908 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1909 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1910 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1911 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1912 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1913 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1914 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b);
1915 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
1916 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
1917 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
1918 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
1919 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b);
1920 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b);
1921 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b);
1922 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b);
1923 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b);
1924 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b);
1925 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b);
1926 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b);
1927 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b);
1928 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b);
1929 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b);
1930 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b);
1931 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b);
1932 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b);
1933 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b);
1934 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b);
1935 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b);
1936 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b);
1937 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
1938 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
1939 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
1940 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
1941 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
1942 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
1943 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
1944 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
1945 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
1946 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
1947 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
1948 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
1949 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
1950 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
1951 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
1952 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
1953 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
1954 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
1955 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b);
1956 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
1957 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
1958 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
1959 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
1960 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
1961 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
1962 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
1963 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
1964 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
1965 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
1966 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
1967 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
1968 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
1969 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
1970 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
1971 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1972 // Vector Floating-Point not implemented yet
1973 inline void mtvscr( VectorRegister b);
1974 inline void mfvscr( VectorRegister d);
1975
1976 // AES (introduced with Power 8)
1977 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
1978 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
1979 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
1980 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
1981 inline void vsbox( VectorRegister d, VectorRegister a);
1982
1983 // SHA (introduced with Power 8)
1984 // Not yet implemented.
1985
1986 // Vector Binary Polynomial Multiplication (introduced with Power 8)
1987 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
1988 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
1989 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
1990 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
1991
1992 // Vector Permute and Xor (introduced with Power 8)
1993 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1994
1995 // Transactional Memory instructions (introduced with Power 8)
1996 inline void tbegin_(); // R=0
1997 inline void tbeginrot_(); // R=1 Rollback-Only Transaction
1998 inline void tend_(); // A=0
1999 inline void tendall_(); // A=1
2000 inline void tabort_();
2001 inline void tabort_(Register a);
2002 inline void tabortwc_(int t, Register a, Register b);
2003 inline void tabortwci_(int t, Register a, int si);
2004 inline void tabortdc_(int t, Register a, Register b);
2005 inline void tabortdci_(int t, Register a, int si);
2006 inline void tsuspend_(); // tsr with L=0
2007 inline void tresume_(); // tsr with L=1
2008 inline void tcheck(int f);
2009
2010 static bool is_tbegin(int x) {
2011 return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1));
2012 }
2013
2014 // The following encoders use r0 as second operand. These instructions
2015 // read r0 as '0'.
2016 inline void lwzx( Register d, Register s2);
2017 inline void lwz( Register d, int si16);
2018 inline void lwax( Register d, Register s2);
2019 inline void lwa( Register d, int si16);
2020 inline void lwbrx(Register d, Register s2);
2021 inline void lhzx( Register d, Register s2);
2022 inline void lhz( Register d, int si16);
2023 inline void lhax( Register d, Register s2);
2024 inline void lha( Register d, int si16);
2025 inline void lhbrx(Register d, Register s2);
2026 inline void lbzx( Register d, Register s2);
2027 inline void lbz( Register d, int si16);
2028 inline void ldx( Register d, Register s2);
2029 inline void ld( Register d, int si16);
2030 inline void stwx( Register d, Register s2);
2031 inline void stw( Register d, int si16);
2032 inline void sthx( Register d, Register s2);
2033 inline void sth( Register d, int si16);
2034 inline void stbx( Register d, Register s2);
2035 inline void stb( Register d, int si16);
2036 inline void stdx( Register d, Register s2);
2037 inline void std( Register d, int si16);
2038
2039 // PPC 2, section 3.2.1 Instruction Cache Instructions
2040 inline void icbi( Register s2);
2041 // PPC 2, section 3.2.2 Data Cache Instructions
2042 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
2043 inline void dcbz( Register s2);
2044 inline void dcbst( Register s2);
2045 inline void dcbf( Register s2);
2046 // dcache read hint
2047 inline void dcbt( Register s2);
2048 inline void dcbtct( Register s2, int ct);
2049 inline void dcbtds( Register s2, int ds);
2050 // dcache write hint
2051 inline void dcbtst( Register s2);
2052 inline void dcbtstct(Register s2, int ct);
2053
2054 // Atomics: use ra0mem to disallow R0 as base.
2055 inline void lwarx_unchecked(Register d, Register b, int eh1);
2056 inline void ldarx_unchecked(Register d, Register b, int eh1);
2057 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2058 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2059 inline void stwcx_(Register s, Register b);
2060 inline void stdcx_(Register s, Register b);
2061 inline void lfs( FloatRegister d, int si16);
2062 inline void lfsx( FloatRegister d, Register b);
2063 inline void lfd( FloatRegister d, int si16);
2064 inline void lfdx( FloatRegister d, Register b);
2065 inline void stfs( FloatRegister s, int si16);
2066 inline void stfsx( FloatRegister s, Register b);
2067 inline void stfd( FloatRegister s, int si16);
2068 inline void stfdx( FloatRegister s, Register b);
2069 inline void lvebx( VectorRegister d, Register s2);
2070 inline void lvehx( VectorRegister d, Register s2);
2071 inline void lvewx( VectorRegister d, Register s2);
2072 inline void lvx( VectorRegister d, Register s2);
2073 inline void lvxl( VectorRegister d, Register s2);
2074 inline void stvebx(VectorRegister d, Register s2);
2075 inline void stvehx(VectorRegister d, Register s2);
2076 inline void stvewx(VectorRegister d, Register s2);
2077 inline void stvx( VectorRegister d, Register s2);
2078 inline void stvxl( VectorRegister d, Register s2);
2079 inline void lvsl( VectorRegister d, Register s2);
2080 inline void lvsr( VectorRegister d, Register s2);
2081
2082 // RegisterOrConstant versions.
2083 // These emitters choose between the versions using two registers and
2084 // those with register and immediate, depending on the content of roc.
2085 // If the constant is not encodable as immediate, instructions to
2086 // load the constant are emitted beforehand. Store instructions need a
2087 // tmp reg if the constant is not encodable as immediate.
2088 // Size unpredictable.
2089 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg);
2090 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2091 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2092 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2093 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2094 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2095 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2096 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2097 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2098 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2099 void add( Register d, RegisterOrConstant roc, Register s1);
2100 void subf(Register d, RegisterOrConstant roc, Register s1);
2101 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
2102
2103
2104 // Emit several instructions to load a 64 bit constant. This issues a fixed
2105 // instruction pattern so that the constant can be patched later on.
2106 enum {
2107 load_const_size = 5 * BytesPerInstWord
2108 };
2109 void load_const(Register d, long a, Register tmp = noreg);
2110 inline void load_const(Register d, void* a, Register tmp = noreg);
2111 inline void load_const(Register d, Label& L, Register tmp = noreg);
2112 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
2113
2114 // Load a 64 bit constant, optimized, not identifyable.
2115 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
2116 // 16 bit immediate offset. This is useful if the offset can be encoded in
2117 // a succeeding instruction.
2118 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false);
2119 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
2120 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
2121 }
2122
2123 // Creation
2124 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2125 #ifdef CHECK_DELAY
2126 delay_state = no_delay;
2127 #endif
2128 }
2129
2130 // Testing
2131 #ifndef PRODUCT
2132 void test_asm();
2133 #endif
2134 };
2135
2136
2137 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP