1 /*
2 * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2015 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP
27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP
28
29 #include "asm/register.hpp"
30
31 // Address is an abstraction used to represent a memory location
32 // as used in assembler instructions.
33 // PPC instructions grok either baseReg + indexReg or baseReg + disp.
34 // So far we do not use this as simplification by this class is low
35 // on PPC with its simple addressing mode. Use RegisterOrConstant to
36 // represent an offset.
37 class Address VALUE_OBJ_CLASS_SPEC {
38 };
39
40 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
41 private:
42 address _address;
43 RelocationHolder _rspec;
44
45 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
46 switch (rtype) {
47 case relocInfo::external_word_type:
48 return external_word_Relocation::spec(addr);
49 case relocInfo::internal_word_type:
50 return internal_word_Relocation::spec(addr);
51 case relocInfo::opt_virtual_call_type:
52 return opt_virtual_call_Relocation::spec();
53 case relocInfo::static_call_type:
54 return static_call_Relocation::spec();
55 case relocInfo::runtime_call_type:
56 return runtime_call_Relocation::spec();
57 case relocInfo::none:
58 return RelocationHolder();
59 default:
60 ShouldNotReachHere();
61 return RelocationHolder();
62 }
63 }
64
65 protected:
66 // creation
67 AddressLiteral() : _address(NULL), _rspec(NULL) {}
68
69 public:
70 AddressLiteral(address addr, RelocationHolder const& rspec)
71 : _address(addr),
72 _rspec(rspec) {}
73
74 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
75 : _address((address) addr),
76 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
77
78 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
79 : _address((address) addr),
80 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
81
82 intptr_t value() const { return (intptr_t) _address; }
83
84 const RelocationHolder& rspec() const { return _rspec; }
85 };
86
87 // Argument is an abstraction used to represent an outgoing
88 // actual argument or an incoming formal parameter, whether
89 // it resides in memory or in a register, in a manner consistent
90 // with the PPC Application Binary Interface, or ABI. This is
91 // often referred to as the native or C calling convention.
92
93 class Argument VALUE_OBJ_CLASS_SPEC {
94 private:
95 int _number; // The number of the argument.
96 public:
97 enum {
98 // Only 8 registers may contain integer parameters.
99 n_register_parameters = 8,
100 // Can have up to 8 floating registers.
101 n_float_register_parameters = 8,
102
103 // PPC C calling conventions.
104 // The first eight arguments are passed in int regs if they are int.
105 n_int_register_parameters_c = 8,
106 // The first thirteen float arguments are passed in float regs.
107 n_float_register_parameters_c = 13,
108 // Only the first 8 parameters are not placed on the stack. Aix disassembly
109 // shows that xlC places all float args after argument 8 on the stack AND
110 // in a register. This is not documented, but we follow this convention, too.
111 n_regs_not_on_stack_c = 8,
112 };
113 // creation
114 Argument(int number) : _number(number) {}
115
116 int number() const { return _number; }
117
118 // Locating register-based arguments:
119 bool is_register() const { return _number < n_register_parameters; }
120
121 Register as_register() const {
122 assert(is_register(), "must be a register argument");
123 return as_Register(number() + R3_ARG1->encoding());
124 }
125 };
126
127 #if !defined(ABI_ELFv2)
128 // A ppc64 function descriptor.
129 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC {
130 private:
131 address _entry;
132 address _toc;
133 address _env;
134
135 public:
136 inline address entry() const { return _entry; }
137 inline address toc() const { return _toc; }
138 inline address env() const { return _env; }
139
140 inline void set_entry(address entry) { _entry = entry; }
141 inline void set_toc( address toc) { _toc = toc; }
142 inline void set_env( address env) { _env = env; }
143
144 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
145 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); }
146 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); }
147
148 // Friend functions can be called without loading toc and env.
149 enum {
150 friend_toc = 0xcafe,
151 friend_env = 0xc0de
152 };
153
154 inline bool is_friend_function() const {
155 return (toc() == (address) friend_toc) && (env() == (address) friend_env);
156 }
157
158 // Constructor for stack-allocated instances.
159 FunctionDescriptor() {
160 _entry = (address) 0xbad;
161 _toc = (address) 0xbad;
162 _env = (address) 0xbad;
163 }
164 };
165 #endif
166
167 class Assembler : public AbstractAssembler {
168 protected:
169 // Displacement routines
170 static void print_instruction(int inst);
171 static int patched_branch(int dest_pos, int inst, int inst_pos);
172 static int branch_destination(int inst, int pos);
173
174 friend class AbstractAssembler;
175
176 // Code patchers need various routines like inv_wdisp()
177 friend class NativeInstruction;
178 friend class NativeGeneralJump;
179 friend class Relocation;
180
181 public:
182
183 enum shifts {
184 XO_21_29_SHIFT = 2,
185 XO_21_30_SHIFT = 1,
186 XO_27_29_SHIFT = 2,
187 XO_30_31_SHIFT = 0,
188 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15
189 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20
190 RS_SHIFT = 21u, // RS field in bits 21 -- 25
191 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31
192 };
193
194 enum opcdxos_masks {
195 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
196 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
197 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
198 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
199 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
200 // trap instructions
201 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
202 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT),
203 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
204 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
205 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
206 STD_OPCODE_MASK = LD_OPCODE_MASK,
207 STDU_OPCODE_MASK = STD_OPCODE_MASK,
208 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
209 STDUX_OPCODE_MASK = STDX_OPCODE_MASK,
210 STW_OPCODE_MASK = (63u << OPCODE_SHIFT),
211 STWU_OPCODE_MASK = STW_OPCODE_MASK,
212 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
213 STWUX_OPCODE_MASK = STWX_OPCODE_MASK,
214 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT),
215 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT),
216 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
217 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
218 };
219
220 enum opcdxos {
221 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1),
222 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1),
223 ADDI_OPCODE = (14u << OPCODE_SHIFT),
224 ADDIS_OPCODE = (15u << OPCODE_SHIFT),
225 ADDIC__OPCODE = (13u << OPCODE_SHIFT),
226 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1),
227 ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1),
228 ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1),
229 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1),
230 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1),
231 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1),
232 SUBFIC_OPCODE = (8u << OPCODE_SHIFT),
233 SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1),
234 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
235 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
236 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
237 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
238 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
239 MULLI_OPCODE = (7u << OPCODE_SHIFT),
240 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1),
241 ANDI_OPCODE = (28u << OPCODE_SHIFT),
242 ANDIS_OPCODE = (29u << OPCODE_SHIFT),
243 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1),
244 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1),
245 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1),
246 ORI_OPCODE = (24u << OPCODE_SHIFT),
247 ORIS_OPCODE = (25u << OPCODE_SHIFT),
248 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1),
249 XORI_OPCODE = (26u << OPCODE_SHIFT),
250 XORIS_OPCODE = (27u << OPCODE_SHIFT),
251
252 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
253
254 RLWINM_OPCODE = (21u << OPCODE_SHIFT),
255 CLRRWI_OPCODE = RLWINM_OPCODE,
256 CLRLWI_OPCODE = RLWINM_OPCODE,
257
258 RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
259
260 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
261 SLWI_OPCODE = RLWINM_OPCODE,
262 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
263 SRWI_OPCODE = RLWINM_OPCODE,
264 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
265 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
266
267 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
268 CMPI_OPCODE = (11u << OPCODE_SHIFT),
269 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
270 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
271
272 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
273
274 // Special purpose registers
275 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
276 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
277
278 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
279 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
280
281 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
282 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
283
284 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
285 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
286
287 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
288 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
289
290 // Attention: Higher and lower half are inserted in reversed order.
291 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
292 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
293 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
294 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
295 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
296 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
297 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
298 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
299
300 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
301 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
302
303 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
304
305 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
306 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
307 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
308
309 // condition register logic instructions
310 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
311 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
312 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
313 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
314 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
315 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
316 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
317 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
318
319 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
320 BXX_OPCODE = (18u << OPCODE_SHIFT),
321 BCXX_OPCODE = (16u << OPCODE_SHIFT),
322
323 // CTR-related opcodes
324 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
325
326 LWZ_OPCODE = (32u << OPCODE_SHIFT),
327 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
328 LWZU_OPCODE = (33u << OPCODE_SHIFT),
329 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1),
330
331 LHA_OPCODE = (42u << OPCODE_SHIFT),
332 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
333 LHAU_OPCODE = (43u << OPCODE_SHIFT),
334
335 LHZ_OPCODE = (40u << OPCODE_SHIFT),
336 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
337 LHZU_OPCODE = (41u << OPCODE_SHIFT),
338 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1),
339
340 LBZ_OPCODE = (34u << OPCODE_SHIFT),
341 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
342 LBZU_OPCODE = (35u << OPCODE_SHIFT),
343
344 STW_OPCODE = (36u << OPCODE_SHIFT),
345 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
346 STWU_OPCODE = (37u << OPCODE_SHIFT),
347 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
348
349 STH_OPCODE = (44u << OPCODE_SHIFT),
350 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
351 STHU_OPCODE = (45u << OPCODE_SHIFT),
352
353 STB_OPCODE = (38u << OPCODE_SHIFT),
354 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
355 STBU_OPCODE = (39u << OPCODE_SHIFT),
356
357 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
358 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
359 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM
360
361 // 32 bit opcode encodings
362
363 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM
364 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
365
366 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM
367
368 // 64 bit opcode encodings
369
370 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
371 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
372 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM
373
374 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
375 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
376 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
377 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
378
379 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM
380 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
381 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
382 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
383
384 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
385
386 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
387 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
388 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
389
390 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
391 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
392 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
393 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
394
395 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
396 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
397 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
398
399
400 // opcodes only used for floating arithmetic
401 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
402 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
403 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
404 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
405 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
406 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
407 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
408 // on Power7. Do not use.
409 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
410 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
411 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
412 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
413 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
414 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
415 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
416 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1),
417 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1),
418 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1),
419 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1),
420 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1),
421 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1),
422
423 // PPC64-internal FPU conversion opcodes
424 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1),
425 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1),
426 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1),
427 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1),
428 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1),
429 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1),
430 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1),
431
432 // WARNING: using fmadd results in a non-compliant vm. Some floating
433 // point tck tests will fail.
434 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
435 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
436 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
437 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
438 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
439 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
440 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
441 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
442
443 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1),
444 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1),
445 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1),
446 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1),
447 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
448 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
449
450 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
451 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
452 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
453 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
454 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
455 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
456
457 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
458 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
459
460 // Vector instruction support for >= Power6
461 // Vector Storage Access
462 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
463 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
464 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
465 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
466 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
467 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
468 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
469 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
470 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
471 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
472 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
473 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
474
475 // Vector Permute and Formatting
476 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
477 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
478 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
479 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
480 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
481 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
482 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
483 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
484 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
485 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
486 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
487 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
488 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
489 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
490 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
491
492 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
493 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
494 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
495 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
496 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
497 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
498
499 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
500 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
501 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
502 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
503 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
504 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
505
506 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
507 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
508
509 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
510 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
511 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
512 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
513 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
514
515 // Vector Integer
516 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
517 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
518 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
519 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
520 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
521 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
522 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
523 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
524 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
525 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
526 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ),
527 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ),
528 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ),
529 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ),
530 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ),
531 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ),
532 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ),
533 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ),
534 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ),
535 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ),
536
537 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ),
538 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ),
539 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ),
540 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ),
541 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ),
542 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ),
543 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ),
544 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ),
545 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ),
546 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ),
547 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ),
548 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ),
549 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ),
550 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ),
551 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ),
552 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ),
553 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ),
554
555 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ),
556 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ),
557 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ),
558 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ),
559 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ),
560
561 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ),
562 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ),
563 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ),
564 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ),
565 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ),
566 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ),
567
568 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ),
569 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ),
570 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ),
571 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ),
572 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ),
573 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ),
574 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ),
575 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ),
576 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ),
577 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ),
578 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ),
579 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ),
580
581 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ),
582 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ),
583 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ),
584 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ),
585 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ),
586 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ),
587 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ),
588 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ),
589 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ),
590
591 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ),
592 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ),
593 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ),
594 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ),
595 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ),
596 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ),
597 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ),
598 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ),
599 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ),
600 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ),
601 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ),
602 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ),
603 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ),
604 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ),
605 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ),
606 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ),
607 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ),
608
609 // Vector Floating-Point
610 // not implemented yet
611
612 // Vector Status and Control
613 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
614 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
615
616 // AES (introduced with Power 8)
617 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
618 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
619 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
620 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
621 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
622
623 // SHA (introduced with Power 8)
624 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
625 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
626
627 // Vector Binary Polynomial Multiplication (introduced with Power 8)
628 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
629 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
630 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
631 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
632
633 // Vector Permute and Xor (introduced with Power 8)
634 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
635
636 // Transactional Memory instructions (introduced with Power 8)
637 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
638 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
639 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
640 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
641 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
642 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
643 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
644 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
645 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),
646
647 // Icache and dcache related instructions
648 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
649 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
650 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
651 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
652
653 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
654 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
655 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
656
657 // Instruction synchronization
658 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
659 // Memory barriers
660 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
661 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
662
663 // Wait instructions for polling.
664 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1),
665
666 // Trap instructions
667 TDI_OPCODE = (2u << OPCODE_SHIFT),
668 TWI_OPCODE = (3u << OPCODE_SHIFT),
669 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
670 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
671
672 // Atomics.
673 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
674 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
675 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
676 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
677 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
678 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
679
680 };
681
682 // Trap instructions TO bits
683 enum trap_to_bits {
684 // single bits
685 traptoLessThanSigned = 1 << 4, // 0, left end
686 traptoGreaterThanSigned = 1 << 3,
687 traptoEqual = 1 << 2,
688 traptoLessThanUnsigned = 1 << 1,
689 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
690
691 // compound ones
692 traptoUnconditional = (traptoLessThanSigned |
693 traptoGreaterThanSigned |
694 traptoEqual |
695 traptoLessThanUnsigned |
696 traptoGreaterThanUnsigned)
697 };
698
699 // Branch hints BH field
700 enum branch_hint_bh {
701 // bclr cases:
702 bhintbhBCLRisReturn = 0,
703 bhintbhBCLRisNotReturnButSame = 1,
704 bhintbhBCLRisNotPredictable = 3,
705
706 // bcctr cases:
707 bhintbhBCCTRisNotReturnButSame = 0,
708 bhintbhBCCTRisNotPredictable = 3
709 };
710
711 // Branch prediction hints AT field
712 enum branch_hint_at {
713 bhintatNoHint = 0, // at=00
714 bhintatIsNotTaken = 2, // at=10
715 bhintatIsTaken = 3 // at=11
716 };
717
718 // Branch prediction hints
719 enum branch_hint_concept {
720 // Use the same encoding as branch_hint_at to simply code.
721 bhintNoHint = bhintatNoHint,
722 bhintIsNotTaken = bhintatIsNotTaken,
723 bhintIsTaken = bhintatIsTaken
724 };
725
726 // Used in BO field of branch instruction.
727 enum branch_condition {
728 bcondCRbiIs0 = 4, // bo=001at
729 bcondCRbiIs1 = 12, // bo=011at
730 bcondAlways = 20 // bo=10100
731 };
732
733 // Branch condition with combined prediction hints.
734 enum branch_condition_with_hint {
735 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint,
736 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
737 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken,
738 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint,
739 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
740 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken,
741 };
742
743 // Elemental Memory Barriers (>=Power 8)
744 enum Elemental_Membar_mask_bits {
745 StoreStore = 1 << 0,
746 StoreLoad = 1 << 1,
747 LoadStore = 1 << 2,
748 LoadLoad = 1 << 3
749 };
750
751 // Branch prediction hints.
752 inline static int add_bhint_to_boint(const int bhint, const int boint) {
753 switch (boint) {
754 case bcondCRbiIs0:
755 case bcondCRbiIs1:
756 // branch_hint and branch_hint_at have same encodings
757 assert( (int)bhintNoHint == (int)bhintatNoHint
758 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
759 && (int)bhintIsTaken == (int)bhintatIsTaken,
760 "wrong encodings");
761 assert((bhint & 0x03) == bhint, "wrong encodings");
762 return (boint & ~0x03) | bhint;
763 case bcondAlways:
764 // no branch_hint
765 return boint;
766 default:
767 ShouldNotReachHere();
768 return 0;
769 }
770 }
771
772 // Extract bcond from boint.
773 inline static int inv_boint_bcond(const int boint) {
774 int r_bcond = boint & ~0x03;
775 assert(r_bcond == bcondCRbiIs0 ||
776 r_bcond == bcondCRbiIs1 ||
777 r_bcond == bcondAlways,
778 "bad branch condition");
779 return r_bcond;
780 }
781
782 // Extract bhint from boint.
783 inline static int inv_boint_bhint(const int boint) {
784 int r_bhint = boint & 0x03;
785 assert(r_bhint == bhintatNoHint ||
786 r_bhint == bhintatIsNotTaken ||
787 r_bhint == bhintatIsTaken,
788 "bad branch hint");
789 return r_bhint;
790 }
791
792 // Calculate opposite of given bcond.
793 inline static int opposite_bcond(const int bcond) {
794 switch (bcond) {
795 case bcondCRbiIs0:
796 return bcondCRbiIs1;
797 case bcondCRbiIs1:
798 return bcondCRbiIs0;
799 default:
800 ShouldNotReachHere();
801 return 0;
802 }
803 }
804
805 // Calculate opposite of given bhint.
806 inline static int opposite_bhint(const int bhint) {
807 switch (bhint) {
808 case bhintatNoHint:
809 return bhintatNoHint;
810 case bhintatIsNotTaken:
811 return bhintatIsTaken;
812 case bhintatIsTaken:
813 return bhintatIsNotTaken;
814 default:
815 ShouldNotReachHere();
816 return 0;
817 }
818 }
819
820 // PPC branch instructions
821 enum ppcops {
822 b_op = 18,
823 bc_op = 16,
824 bcr_op = 19
825 };
826
827 enum Condition {
828 negative = 0,
829 less = 0,
830 positive = 1,
831 greater = 1,
832 zero = 2,
833 equal = 2,
834 summary_overflow = 3,
835 };
836
837 public:
838 // Helper functions for groups of instructions
839
840 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
841
842 // instruction must start at passed address
843 static int instr_len(unsigned char *instr) { return BytesPerInstWord; }
844
845 // instruction must be left-justified in argument
846 static int instr_len(unsigned long instr) { return BytesPerInstWord; }
847
848 // longest instructions
849 static int instr_maxlen() { return BytesPerInstWord; }
850
851 // Test if x is within signed immediate range for nbits.
852 static bool is_simm(int x, unsigned int nbits) {
853 assert(0 < nbits && nbits < 32, "out of bounds");
854 const int min = -( ((int)1) << nbits-1 );
855 const int maxplus1 = ( ((int)1) << nbits-1 );
856 return min <= x && x < maxplus1;
857 }
858
859 static bool is_simm(jlong x, unsigned int nbits) {
860 assert(0 < nbits && nbits < 64, "out of bounds");
861 const jlong min = -( ((jlong)1) << nbits-1 );
862 const jlong maxplus1 = ( ((jlong)1) << nbits-1 );
863 return min <= x && x < maxplus1;
864 }
865
866 // Test if x is within unsigned immediate range for nbits
867 static bool is_uimm(int x, unsigned int nbits) {
868 assert(0 < nbits && nbits < 32, "out of bounds");
869 const int maxplus1 = ( ((int)1) << nbits );
870 return 0 <= x && x < maxplus1;
871 }
872
873 static bool is_uimm(jlong x, unsigned int nbits) {
874 assert(0 < nbits && nbits < 64, "out of bounds");
875 const jlong maxplus1 = ( ((jlong)1) << nbits );
876 return 0 <= x && x < maxplus1;
877 }
878
879 protected:
880 // helpers
881
882 // X is supposed to fit in a field "nbits" wide
883 // and be sign-extended. Check the range.
884 static void assert_signed_range(intptr_t x, int nbits) {
885 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
886 "value out of range");
887 }
888
889 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
890 assert((x & 3) == 0, "not word aligned");
891 assert_signed_range(x, nbits + 2);
892 }
893
894 static void assert_unsigned_const(int x, int nbits) {
895 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
896 }
897
898 static int fmask(juint hi_bit, juint lo_bit) {
899 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
900 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
901 }
902
903 // inverse of u_field
904 static int inv_u_field(int x, int hi_bit, int lo_bit) {
905 juint r = juint(x) >> lo_bit;
906 r &= fmask(hi_bit, lo_bit);
907 return int(r);
908 }
909
910 // signed version: extract from field and sign-extend
911 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
912 x = x << (31-hi_bit);
913 x = x >> (31-hi_bit+lo_bit);
914 return x;
915 }
916
917 static int u_field(int x, int hi_bit, int lo_bit) {
918 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
919 int r = x << lo_bit;
920 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
921 return r;
922 }
923
924 // Same as u_field for signed values
925 static int s_field(int x, int hi_bit, int lo_bit) {
926 int nbits = hi_bit - lo_bit + 1;
927 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
928 "value out of range");
929 x &= fmask(hi_bit, lo_bit);
930 int r = x << lo_bit;
931 return r;
932 }
933
934 // inv_op for ppc instructions
935 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
936
937 // Determine target address from li, bd field of branch instruction.
938 static intptr_t inv_li_field(int x) {
939 intptr_t r = inv_s_field_ppc(x, 25, 2);
940 r = (r << 2);
941 return r;
942 }
943 static intptr_t inv_bd_field(int x, intptr_t pos) {
944 intptr_t r = inv_s_field_ppc(x, 15, 2);
945 r = (r << 2) + pos;
946 return r;
947 }
948
949 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
950 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
951 // Extract instruction fields from instruction words.
952 public:
953 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); }
954 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); }
955 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); }
956 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
957 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); }
958 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
959 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
960 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; }
961 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); }
962 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); }
963 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); }
964 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); }
965 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
966 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }
967
968 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
969 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
970
971 // instruction fields
972 static int aa( int x) { return opp_u_field(x, 30, 30); }
973 static int ba( int x) { return opp_u_field(x, 15, 11); }
974 static int bb( int x) { return opp_u_field(x, 20, 16); }
975 static int bc( int x) { return opp_u_field(x, 25, 21); }
976 static int bd( int x) { return opp_s_field(x, 29, 16); }
977 static int bf( ConditionRegister cr) { return bf(cr->encoding()); }
978 static int bf( int x) { return opp_u_field(x, 8, 6); }
979 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); }
980 static int bfa( int x) { return opp_u_field(x, 13, 11); }
981 static int bh( int x) { return opp_u_field(x, 20, 19); }
982 static int bi( int x) { return opp_u_field(x, 15, 11); }
983 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
984 static int bo( int x) { return opp_u_field(x, 10, 6); }
985 static int bt( int x) { return opp_u_field(x, 10, 6); }
986 static int d1( int x) { return opp_s_field(x, 31, 16); }
987 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
988 static int eh( int x) { return opp_u_field(x, 31, 31); }
989 static int flm( int x) { return opp_u_field(x, 14, 7); }
990 static int fra( FloatRegister r) { return fra(r->encoding());}
991 static int frb( FloatRegister r) { return frb(r->encoding());}
992 static int frc( FloatRegister r) { return frc(r->encoding());}
993 static int frs( FloatRegister r) { return frs(r->encoding());}
994 static int frt( FloatRegister r) { return frt(r->encoding());}
995 static int fra( int x) { return opp_u_field(x, 15, 11); }
996 static int frb( int x) { return opp_u_field(x, 20, 16); }
997 static int frc( int x) { return opp_u_field(x, 25, 21); }
998 static int frs( int x) { return opp_u_field(x, 10, 6); }
999 static int frt( int x) { return opp_u_field(x, 10, 6); }
1000 static int fxm( int x) { return opp_u_field(x, 19, 12); }
1001 static int l10( int x) { return opp_u_field(x, 10, 10); }
1002 static int l15( int x) { return opp_u_field(x, 15, 15); }
1003 static int l910( int x) { return opp_u_field(x, 10, 9); }
1004 static int e1215( int x) { return opp_u_field(x, 15, 12); }
1005 static int lev( int x) { return opp_u_field(x, 26, 20); }
1006 static int li( int x) { return opp_s_field(x, 29, 6); }
1007 static int lk( int x) { return opp_u_field(x, 31, 31); }
1008 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
1009 static int me2630( int x) { return opp_u_field(x, 30, 26); }
1010 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1011 static int me2126( int x) { return mb2126(x); }
1012 static int nb( int x) { return opp_u_field(x, 20, 16); }
1013 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
1014 static int oe( int x) { return opp_u_field(x, 21, 21); }
1015 static int ra( Register r) { return ra(r->encoding()); }
1016 static int ra( int x) { return opp_u_field(x, 15, 11); }
1017 static int rb( Register r) { return rb(r->encoding()); }
1018 static int rb( int x) { return opp_u_field(x, 20, 16); }
1019 static int rc( int x) { return opp_u_field(x, 31, 31); }
1020 static int rs( Register r) { return rs(r->encoding()); }
1021 static int rs( int x) { return opp_u_field(x, 10, 6); }
1022 // we don't want to use R0 in memory accesses, because it has value `0' then
1023 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
1024 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); }
1025
1026 // register r is target
1027 static int rt( Register r) { return rs(r); }
1028 static int rt( int x) { return rs(x); }
1029 static int rta( Register r) { return ra(r); }
1030 static int rta0mem( Register r) { rta(r); return ra0mem(r); }
1031
1032 static int sh1620( int x) { return opp_u_field(x, 20, 16); }
1033 static int sh30( int x) { return opp_u_field(x, 30, 30); }
1034 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
1035 static int si( int x) { return opp_s_field(x, 31, 16); }
1036 static int spr( int x) { return opp_u_field(x, 20, 11); }
1037 static int sr( int x) { return opp_u_field(x, 15, 12); }
1038 static int tbr( int x) { return opp_u_field(x, 20, 11); }
1039 static int th( int x) { return opp_u_field(x, 10, 7); }
1040 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
1041 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
1042 static int to( int x) { return opp_u_field(x, 10, 6); }
1043 static int u( int x) { return opp_u_field(x, 19, 16); }
1044 static int ui( int x) { return opp_u_field(x, 31, 16); }
1045
1046 // Support vector instructions for >= Power6.
1047 static int vra( int x) { return opp_u_field(x, 15, 11); }
1048 static int vrb( int x) { return opp_u_field(x, 20, 16); }
1049 static int vrc( int x) { return opp_u_field(x, 25, 21); }
1050 static int vrs( int x) { return opp_u_field(x, 10, 6); }
1051 static int vrt( int x) { return opp_u_field(x, 10, 6); }
1052
1053 static int vra( VectorRegister r) { return vra(r->encoding());}
1054 static int vrb( VectorRegister r) { return vrb(r->encoding());}
1055 static int vrc( VectorRegister r) { return vrc(r->encoding());}
1056 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1057 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1058
1059 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1060 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1061 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1062 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1063
1064 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1065 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1066 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1067 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1068 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1069 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1070 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1071
1072 protected:
1073 // Compute relative address for branch.
1074 static intptr_t disp(intptr_t x, intptr_t off) {
1075 int xx = x - off;
1076 xx = xx >> 2;
1077 return xx;
1078 }
1079
1080 public:
1081 // signed immediate, in low bits, nbits long
1082 static int simm(int x, int nbits) {
1083 assert_signed_range(x, nbits);
1084 return x & ((1 << nbits) - 1);
1085 }
1086
1087 // unsigned immediate, in low bits, nbits long
1088 static int uimm(int x, int nbits) {
1089 assert_unsigned_const(x, nbits);
1090 return x & ((1 << nbits) - 1);
1091 }
1092
1093 static void set_imm(int* instr, short s) {
1094 // imm is always in the lower 16 bits of the instruction,
1095 // so this is endian-neutral. Same for the get_imm below.
1096 uint32_t w = *(uint32_t *)instr;
1097 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
1098 }
1099
1100 static int get_imm(address a, int instruction_number) {
1101 return (short)((int *)a)[instruction_number];
1102 }
1103
1104 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); }
1105 static inline int lo16_unsigned(int x) { return x & 0xffff; }
1106
1107 protected:
1108
1109 // Extract the top 32 bits in a 64 bit word.
1110 static int32_t hi32(int64_t x) {
1111 int32_t r = int32_t((uint64_t)x >> 32);
1112 return r;
1113 }
1114
1115 public:
1116
1117 static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1118 return ((addr + (a - 1)) & ~(a - 1));
1119 }
1120
1121 static inline bool is_aligned(unsigned int addr, unsigned int a) {
1122 return (0 == addr % a);
1123 }
1124
1125 void flush() {
1126 AbstractAssembler::flush();
1127 }
1128
1129 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
1130 inline void emit_data(int);
1131 inline void emit_data(int, RelocationHolder const&);
1132 inline void emit_data(int, relocInfo::relocType rtype);
1133
1134 // Emit an address.
1135 inline address emit_addr(const address addr = NULL);
1136
1137 #if !defined(ABI_ELFv2)
1138 // Emit a function descriptor with the specified entry point, TOC,
1139 // and ENV. If the entry point is NULL, the descriptor will point
1140 // just past the descriptor.
1141 // Use values from friend functions as defaults.
1142 inline address emit_fd(address entry = NULL,
1143 address toc = (address) FunctionDescriptor::friend_toc,
1144 address env = (address) FunctionDescriptor::friend_env);
1145 #endif
1146
1147 /////////////////////////////////////////////////////////////////////////////////////
1148 // PPC instructions
1149 /////////////////////////////////////////////////////////////////////////////////////
1150
1151 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1152 // immediates. The normal instruction encoders enforce that r0 is not
1153 // passed to them. Use either extended mnemonics encoders or the special ra0
1154 // versions.
1155
1156 // Issue an illegal instruction.
1157 inline void illtrap();
1158 static inline bool is_illtrap(int x);
1159
1160 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1161 inline void addi( Register d, Register a, int si16);
1162 inline void addis(Register d, Register a, int si16);
1163 private:
1164 inline void addi_r0ok( Register d, Register a, int si16);
1165 inline void addis_r0ok(Register d, Register a, int si16);
1166 public:
1167 inline void addic_( Register d, Register a, int si16);
1168 inline void subfic( Register d, Register a, int si16);
1169 inline void add( Register d, Register a, Register b);
1170 inline void add_( Register d, Register a, Register b);
1171 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec.
1172 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability.
1173 inline void subf_( Register d, Register a, Register b);
1174 inline void addc( Register d, Register a, Register b);
1175 inline void addc_( Register d, Register a, Register b);
1176 inline void subfc( Register d, Register a, Register b);
1177 inline void subfc_( Register d, Register a, Register b);
1178 inline void adde( Register d, Register a, Register b);
1179 inline void adde_( Register d, Register a, Register b);
1180 inline void subfe( Register d, Register a, Register b);
1181 inline void subfe_( Register d, Register a, Register b);
1182 inline void addme( Register d, Register a);
1183 inline void addme_( Register d, Register a);
1184 inline void subfme( Register d, Register a);
1185 inline void subfme_(Register d, Register a);
1186 inline void addze( Register d, Register a);
1187 inline void addze_( Register d, Register a);
1188 inline void subfze( Register d, Register a);
1189 inline void subfze_(Register d, Register a);
1190 inline void neg( Register d, Register a);
1191 inline void neg_( Register d, Register a);
1192 inline void mulli( Register d, Register a, int si16);
1193 inline void mulld( Register d, Register a, Register b);
1194 inline void mulld_( Register d, Register a, Register b);
1195 inline void mullw( Register d, Register a, Register b);
1196 inline void mullw_( Register d, Register a, Register b);
1197 inline void mulhw( Register d, Register a, Register b);
1198 inline void mulhw_( Register d, Register a, Register b);
1199 inline void mulhd( Register d, Register a, Register b);
1200 inline void mulhd_( Register d, Register a, Register b);
1201 inline void mulhdu( Register d, Register a, Register b);
1202 inline void mulhdu_(Register d, Register a, Register b);
1203 inline void divd( Register d, Register a, Register b);
1204 inline void divd_( Register d, Register a, Register b);
1205 inline void divw( Register d, Register a, Register b);
1206 inline void divw_( Register d, Register a, Register b);
1207
1208 // Fixed-Point Arithmetic Instructions with Overflow detection
1209 inline void addo( Register d, Register a, Register b);
1210 inline void addo_( Register d, Register a, Register b);
1211 inline void subfo( Register d, Register a, Register b);
1212 inline void subfo_( Register d, Register a, Register b);
1213 inline void addco( Register d, Register a, Register b);
1214 inline void addco_( Register d, Register a, Register b);
1215 inline void subfco( Register d, Register a, Register b);
1216 inline void subfco_( Register d, Register a, Register b);
1217 inline void addeo( Register d, Register a, Register b);
1218 inline void addeo_( Register d, Register a, Register b);
1219 inline void subfeo( Register d, Register a, Register b);
1220 inline void subfeo_( Register d, Register a, Register b);
1221 inline void addmeo( Register d, Register a);
1222 inline void addmeo_( Register d, Register a);
1223 inline void subfmeo( Register d, Register a);
1224 inline void subfmeo_(Register d, Register a);
1225 inline void addzeo( Register d, Register a);
1226 inline void addzeo_( Register d, Register a);
1227 inline void subfzeo( Register d, Register a);
1228 inline void subfzeo_(Register d, Register a);
1229 inline void nego( Register d, Register a);
1230 inline void nego_( Register d, Register a);
1231 inline void mulldo( Register d, Register a, Register b);
1232 inline void mulldo_( Register d, Register a, Register b);
1233 inline void mullwo( Register d, Register a, Register b);
1234 inline void mullwo_( Register d, Register a, Register b);
1235 inline void divdo( Register d, Register a, Register b);
1236 inline void divdo_( Register d, Register a, Register b);
1237 inline void divwo( Register d, Register a, Register b);
1238 inline void divwo_( Register d, Register a, Register b);
1239
1240 // extended mnemonics
1241 inline void li( Register d, int si16);
1242 inline void lis( Register d, int si16);
1243 inline void addir(Register d, int si16, Register a);
1244
1245 static bool is_addi(int x) {
1246 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1247 }
1248 static bool is_addis(int x) {
1249 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1250 }
1251 static bool is_bxx(int x) {
1252 return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1253 }
1254 static bool is_b(int x) {
1255 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1256 }
1257 static bool is_bl(int x) {
1258 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1259 }
1260 static bool is_bcxx(int x) {
1261 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1262 }
1263 static bool is_bxx_or_bcxx(int x) {
1264 return is_bxx(x) || is_bcxx(x);
1265 }
1266 static bool is_bctrl(int x) {
1267 return x == 0x4e800421;
1268 }
1269 static bool is_bctr(int x) {
1270 return x == 0x4e800420;
1271 }
1272 static bool is_bclr(int x) {
1273 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1274 }
1275 static bool is_li(int x) {
1276 return is_addi(x) && inv_ra_field(x)==0;
1277 }
1278 static bool is_lis(int x) {
1279 return is_addis(x) && inv_ra_field(x)==0;
1280 }
1281 static bool is_mtctr(int x) {
1282 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1283 }
1284 static bool is_ld(int x) {
1285 return LD_OPCODE == (x & LD_OPCODE_MASK);
1286 }
1287 static bool is_std(int x) {
1288 return STD_OPCODE == (x & STD_OPCODE_MASK);
1289 }
1290 static bool is_stdu(int x) {
1291 return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1292 }
1293 static bool is_stdx(int x) {
1294 return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1295 }
1296 static bool is_stdux(int x) {
1297 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1298 }
1299 static bool is_stwx(int x) {
1300 return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1301 }
1302 static bool is_stwux(int x) {
1303 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1304 }
1305 static bool is_stw(int x) {
1306 return STW_OPCODE == (x & STW_OPCODE_MASK);
1307 }
1308 static bool is_stwu(int x) {
1309 return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1310 }
1311 static bool is_ori(int x) {
1312 return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1313 };
1314 static bool is_oris(int x) {
1315 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1316 };
1317 static bool is_rldicr(int x) {
1318 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1319 };
1320 static bool is_nop(int x) {
1321 return x == 0x60000000;
1322 }
1323 // endgroup opcode for Power6
1324 static bool is_endgroup(int x) {
1325 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1326 }
1327
1328
1329 private:
1330 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1331 inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1332 inline void cmp( ConditionRegister bf, int l, Register a, Register b);
1333 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1334 inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1335
1336 public:
1337 // extended mnemonics of Compare Instructions
1338 inline void cmpwi( ConditionRegister crx, Register a, int si16);
1339 inline void cmpdi( ConditionRegister crx, Register a, int si16);
1340 inline void cmpw( ConditionRegister crx, Register a, Register b);
1341 inline void cmpd( ConditionRegister crx, Register a, Register b);
1342 inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1343 inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1344 inline void cmplw( ConditionRegister crx, Register a, Register b);
1345 inline void cmpld( ConditionRegister crx, Register a, Register b);
1346
1347 inline void isel( Register d, Register a, Register b, int bc);
1348 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1349 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1350 // Set d = 0 if (cr.cc) equals 1, otherwise b.
1351 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1352
1353 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1354 void andi( Register a, Register s, long ui16); // optimized version
1355 inline void andi_( Register a, Register s, int ui16);
1356 inline void andis_( Register a, Register s, int ui16);
1357 inline void ori( Register a, Register s, int ui16);
1358 inline void oris( Register a, Register s, int ui16);
1359 inline void xori( Register a, Register s, int ui16);
1360 inline void xoris( Register a, Register s, int ui16);
1361 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
1362 inline void and_( Register a, Register s, Register b);
1363 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1364 // SMT-priority change instruction (see SMT instructions below).
1365 inline void or_unchecked(Register a, Register s, Register b);
1366 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
1367 inline void or_( Register a, Register s, Register b);
1368 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword
1369 inline void xor_( Register a, Register s, Register b);
1370 inline void nand( Register a, Register s, Register b);
1371 inline void nand_( Register a, Register s, Register b);
1372 inline void nor( Register a, Register s, Register b);
1373 inline void nor_( Register a, Register s, Register b);
1374 inline void andc( Register a, Register s, Register b);
1375 inline void andc_( Register a, Register s, Register b);
1376 inline void orc( Register a, Register s, Register b);
1377 inline void orc_( Register a, Register s, Register b);
1378 inline void extsb( Register a, Register s);
1379 inline void extsh( Register a, Register s);
1380 inline void extsw( Register a, Register s);
1381
1382 // extended mnemonics
1383 inline void nop();
1384 // NOP for FP and BR units (different versions to allow them to be in one group)
1385 inline void fpnop0();
1386 inline void fpnop1();
1387 inline void brnop0();
1388 inline void brnop1();
1389 inline void brnop2();
1390
1391 inline void mr( Register d, Register s);
1392 inline void ori_opt( Register d, int ui16);
1393 inline void oris_opt(Register d, int ui16);
1394
1395 // endgroup opcode for Power6
1396 inline void endgroup();
1397
1398 // count instructions
1399 inline void cntlzw( Register a, Register s);
1400 inline void cntlzw_( Register a, Register s);
1401 inline void cntlzd( Register a, Register s);
1402 inline void cntlzd_( Register a, Register s);
1403
1404 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1405 inline void sld( Register a, Register s, Register b);
1406 inline void sld_( Register a, Register s, Register b);
1407 inline void slw( Register a, Register s, Register b);
1408 inline void slw_( Register a, Register s, Register b);
1409 inline void srd( Register a, Register s, Register b);
1410 inline void srd_( Register a, Register s, Register b);
1411 inline void srw( Register a, Register s, Register b);
1412 inline void srw_( Register a, Register s, Register b);
1413 inline void srad( Register a, Register s, Register b);
1414 inline void srad_( Register a, Register s, Register b);
1415 inline void sraw( Register a, Register s, Register b);
1416 inline void sraw_( Register a, Register s, Register b);
1417 inline void sradi( Register a, Register s, int sh6);
1418 inline void sradi_( Register a, Register s, int sh6);
1419 inline void srawi( Register a, Register s, int sh5);
1420 inline void srawi_( Register a, Register s, int sh5);
1421
1422 // extended mnemonics for Shift Instructions
1423 inline void sldi( Register a, Register s, int sh6);
1424 inline void sldi_( Register a, Register s, int sh6);
1425 inline void slwi( Register a, Register s, int sh5);
1426 inline void slwi_( Register a, Register s, int sh5);
1427 inline void srdi( Register a, Register s, int sh6);
1428 inline void srdi_( Register a, Register s, int sh6);
1429 inline void srwi( Register a, Register s, int sh5);
1430 inline void srwi_( Register a, Register s, int sh5);
1431
1432 inline void clrrdi( Register a, Register s, int ui6);
1433 inline void clrrdi_( Register a, Register s, int ui6);
1434 inline void clrldi( Register a, Register s, int ui6);
1435 inline void clrldi_( Register a, Register s, int ui6);
1436 inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1437 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1438 inline void extrdi( Register a, Register s, int n, int b);
1439 // testbit with condition register
1440 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1441
1442 // rotate instructions
1443 inline void rotldi( Register a, Register s, int n);
1444 inline void rotrdi( Register a, Register s, int n);
1445 inline void rotlwi( Register a, Register s, int n);
1446 inline void rotrwi( Register a, Register s, int n);
1447
1448 // Rotate Instructions
1449 inline void rldic( Register a, Register s, int sh6, int mb6);
1450 inline void rldic_( Register a, Register s, int sh6, int mb6);
1451 inline void rldicr( Register a, Register s, int sh6, int mb6);
1452 inline void rldicr_( Register a, Register s, int sh6, int mb6);
1453 inline void rldicl( Register a, Register s, int sh6, int mb6);
1454 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1455 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1456 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1457 inline void rldimi( Register a, Register s, int sh6, int mb6);
1458 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1459 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1460 inline void insrdi( Register a, Register s, int n, int b);
1461 inline void insrwi( Register a, Register s, int n, int b);
1462
1463 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1464 // 4 bytes
1465 inline void lwzx( Register d, Register s1, Register s2);
1466 inline void lwz( Register d, int si16, Register s1);
1467 inline void lwzu( Register d, int si16, Register s1);
1468
1469 // 4 bytes
1470 inline void lwax( Register d, Register s1, Register s2);
1471 inline void lwa( Register d, int si16, Register s1);
1472
1473 // 4 bytes reversed
1474 inline void lwbrx( Register d, Register s1, Register s2);
1475
1476 // 2 bytes
1477 inline void lhzx( Register d, Register s1, Register s2);
1478 inline void lhz( Register d, int si16, Register s1);
1479 inline void lhzu( Register d, int si16, Register s1);
1480
1481 // 2 bytes reversed
1482 inline void lhbrx( Register d, Register s1, Register s2);
1483
1484 // 2 bytes
1485 inline void lhax( Register d, Register s1, Register s2);
1486 inline void lha( Register d, int si16, Register s1);
1487 inline void lhau( Register d, int si16, Register s1);
1488
1489 // 1 byte
1490 inline void lbzx( Register d, Register s1, Register s2);
1491 inline void lbz( Register d, int si16, Register s1);
1492 inline void lbzu( Register d, int si16, Register s1);
1493
1494 // 8 bytes
1495 inline void ldx( Register d, Register s1, Register s2);
1496 inline void ld( Register d, int si16, Register s1);
1497 inline void ldu( Register d, int si16, Register s1);
1498
1499 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
1500 inline void stwx( Register d, Register s1, Register s2);
1501 inline void stw( Register d, int si16, Register s1);
1502 inline void stwu( Register d, int si16, Register s1);
1503
1504 inline void sthx( Register d, Register s1, Register s2);
1505 inline void sth( Register d, int si16, Register s1);
1506 inline void sthu( Register d, int si16, Register s1);
1507
1508 inline void stbx( Register d, Register s1, Register s2);
1509 inline void stb( Register d, int si16, Register s1);
1510 inline void stbu( Register d, int si16, Register s1);
1511
1512 inline void stdx( Register d, Register s1, Register s2);
1513 inline void std( Register d, int si16, Register s1);
1514 inline void stdu( Register d, int si16, Register s1);
1515 inline void stdux(Register s, Register a, Register b);
1516
1517 // PPC 1, section 3.3.13 Move To/From System Register Instructions
1518 inline void mtlr( Register s1);
1519 inline void mflr( Register d);
1520 inline void mtctr(Register s1);
1521 inline void mfctr(Register d);
1522 inline void mtcrf(int fxm, Register s);
1523 inline void mfcr( Register d);
1524 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1525 inline void mtcr( Register s);
1526
1527 // Special purpose registers
1528 // Exception Register
1529 inline void mtxer(Register s1);
1530 inline void mfxer(Register d);
1531 // Vector Register Save Register
1532 inline void mtvrsave(Register s1);
1533 inline void mfvrsave(Register d);
1534 // Timebase
1535 inline void mftb(Register d);
1536 // Introduced with Power 8:
1537 // Data Stream Control Register
1538 inline void mtdscr(Register s1);
1539 inline void mfdscr(Register d );
1540 // Transactional Memory Registers
1541 inline void mftfhar(Register d);
1542 inline void mftfiar(Register d);
1543 inline void mftexasr(Register d);
1544 inline void mftexasru(Register d);
1545
1546 // TEXASR bit description
1547 enum transaction_failure_reason {
1548 // Upper half (TEXASRU):
1549 tm_failure_persistent = 7, // The failure is likely to recur on each execution.
1550 tm_disallowed = 8, // The instruction is not permitted.
1551 tm_nesting_of = 9, // The maximum transaction level was exceeded.
1552 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded.
1553 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state.
1554 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor.
1555 tm_trans_cf = 13, // A conflict occurred with another transaction.
1556 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation.
1557 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally.
1558 tm_tabort = 31, // Termination was caused by the execution of an abort instruction.
1559 // Lower half:
1560 tm_suspended = 32, // Failure was recorded in Suspended state.
1561 tm_failure_summary = 36, // Failure has been detected and recorded.
1562 tm_tfiar_exact = 37, // Value in the TFIAR is exact.
1563 tm_rot = 38, // Rollback-only transaction.
1564 };
1565
1566 // PPC 1, section 2.4.1 Branch Instructions
1567 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1568 inline void b( Label& L);
1569 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1570 inline void bl( Label& L);
1571 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1572 inline void bc( int boint, int biint, Label& L);
1573 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1574 inline void bcl(int boint, int biint, Label& L);
1575
1576 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1577 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1578 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1579 relocInfo::relocType rt = relocInfo::none);
1580 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1581 relocInfo::relocType rt = relocInfo::none);
1582
1583 // helper function for b, bcxx
1584 inline bool is_within_range_of_b(address a, address pc);
1585 inline bool is_within_range_of_bcxx(address a, address pc);
1586
1587 // get the destination of a bxx branch (b, bl, ba, bla)
1588 static inline address bxx_destination(address baddr);
1589 static inline address bxx_destination(int instr, address pc);
1590 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1591
1592 // extended mnemonics for branch instructions
1593 inline void blt(ConditionRegister crx, Label& L);
1594 inline void bgt(ConditionRegister crx, Label& L);
1595 inline void beq(ConditionRegister crx, Label& L);
1596 inline void bso(ConditionRegister crx, Label& L);
1597 inline void bge(ConditionRegister crx, Label& L);
1598 inline void ble(ConditionRegister crx, Label& L);
1599 inline void bne(ConditionRegister crx, Label& L);
1600 inline void bns(ConditionRegister crx, Label& L);
1601
1602 // Branch instructions with static prediction hints.
1603 inline void blt_predict_taken( ConditionRegister crx, Label& L);
1604 inline void bgt_predict_taken( ConditionRegister crx, Label& L);
1605 inline void beq_predict_taken( ConditionRegister crx, Label& L);
1606 inline void bso_predict_taken( ConditionRegister crx, Label& L);
1607 inline void bge_predict_taken( ConditionRegister crx, Label& L);
1608 inline void ble_predict_taken( ConditionRegister crx, Label& L);
1609 inline void bne_predict_taken( ConditionRegister crx, Label& L);
1610 inline void bns_predict_taken( ConditionRegister crx, Label& L);
1611 inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1612 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1613 inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1614 inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1615 inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1616 inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1617 inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1618 inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1619
1620 // for use in conjunction with testbitdi:
1621 inline void btrue( ConditionRegister crx, Label& L);
1622 inline void bfalse(ConditionRegister crx, Label& L);
1623
1624 inline void bltl(ConditionRegister crx, Label& L);
1625 inline void bgtl(ConditionRegister crx, Label& L);
1626 inline void beql(ConditionRegister crx, Label& L);
1627 inline void bsol(ConditionRegister crx, Label& L);
1628 inline void bgel(ConditionRegister crx, Label& L);
1629 inline void blel(ConditionRegister crx, Label& L);
1630 inline void bnel(ConditionRegister crx, Label& L);
1631 inline void bnsl(ConditionRegister crx, Label& L);
1632
1633 // extended mnemonics for Branch Instructions via LR
1634 // We use `blr' for returns.
1635 inline void blr(relocInfo::relocType rt = relocInfo::none);
1636
1637 // extended mnemonics for Branch Instructions with CTR
1638 // bdnz means `decrement CTR and jump to L if CTR is not zero'
1639 inline void bdnz(Label& L);
1640 // Decrement and branch if result is zero.
1641 inline void bdz(Label& L);
1642 // we use `bctr[l]' for jumps/calls in function descriptor glue
1643 // code, e.g. calls to runtime functions
1644 inline void bctr( relocInfo::relocType rt = relocInfo::none);
1645 inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1646 // conditional jumps/branches via CTR
1647 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1648 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1649 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1650 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1651
1652 // condition register logic instructions
1653 // NOTE: There's a preferred form: d and s2 should point into the same condition register.
1654 inline void crand( int d, int s1, int s2);
1655 inline void crnand(int d, int s1, int s2);
1656 inline void cror( int d, int s1, int s2);
1657 inline void crxor( int d, int s1, int s2);
1658 inline void crnor( int d, int s1, int s2);
1659 inline void creqv( int d, int s1, int s2);
1660 inline void crandc(int d, int s1, int s2);
1661 inline void crorc( int d, int s1, int s2);
1662
1663 // More convenient version.
1664 int condition_register_bit(ConditionRegister cr, Condition c) {
1665 return 4 * (int)(intptr_t)cr + c;
1666 }
1667 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1668 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1669 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1670 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1671 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1672 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1673 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1674 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1675
1676 // icache and dcache related instructions
1677 inline void icbi( Register s1, Register s2);
1678 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1679 inline void dcbz( Register s1, Register s2);
1680 inline void dcbst( Register s1, Register s2);
1681 inline void dcbf( Register s1, Register s2);
1682
1683 enum ct_cache_specification {
1684 ct_primary_cache = 0,
1685 ct_secondary_cache = 2
1686 };
1687 // dcache read hint
1688 inline void dcbt( Register s1, Register s2);
1689 inline void dcbtct( Register s1, Register s2, int ct);
1690 inline void dcbtds( Register s1, Register s2, int ds);
1691 // dcache write hint
1692 inline void dcbtst( Register s1, Register s2);
1693 inline void dcbtstct(Register s1, Register s2, int ct);
1694
1695 // machine barrier instructions:
1696 //
1697 // - sync two-way memory barrier, aka fence
1698 // - lwsync orders Store|Store,
1699 // Load|Store,
1700 // Load|Load,
1701 // but not Store|Load
1702 // - eieio orders memory accesses for device memory (only)
1703 // - isync invalidates speculatively executed instructions
1704 // From the Power ISA 2.06 documentation:
1705 // "[...] an isync instruction prevents the execution of
1706 // instructions following the isync until instructions
1707 // preceding the isync have completed, [...]"
1708 // From IBM's AIX assembler reference:
1709 // "The isync [...] instructions causes the processor to
1710 // refetch any instructions that might have been fetched
1711 // prior to the isync instruction. The instruction isync
1712 // causes the processor to wait for all previous instructions
1713 // to complete. Then any instructions already fetched are
1714 // discarded and instruction processing continues in the
1715 // environment established by the previous instructions."
1716 //
1717 // semantic barrier instructions:
1718 // (as defined in orderAccess.hpp)
1719 //
1720 // - release orders Store|Store, (maps to lwsync)
1721 // Load|Store
1722 // - acquire orders Load|Store, (maps to lwsync)
1723 // Load|Load
1724 // - fence orders Store|Store, (maps to sync)
1725 // Load|Store,
1726 // Load|Load,
1727 // Store|Load
1728 //
1729 private:
1730 inline void sync(int l);
1731 public:
1732 inline void sync();
1733 inline void lwsync();
1734 inline void ptesync();
1735 inline void eieio();
1736 inline void isync();
1737 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1738
1739 // Wait instructions for polling. Attention: May result in SIGILL.
1740 inline void wait();
1741 inline void waitrsv(); // >=Power7
1742
1743 // atomics
1744 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1745 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1746 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1747 inline bool lxarx_hint_exclusive_access();
1748 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1749 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1750 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1751 inline void stwcx_( Register s, Register a, Register b);
1752 inline void stdcx_( Register s, Register a, Register b);
1753 inline void stqcx_( Register s, Register a, Register b);
1754
1755 // Instructions for adjusting thread priority for simultaneous
1756 // multithreading (SMT) on Power5.
1757 private:
1758 inline void smt_prio_very_low();
1759 inline void smt_prio_medium_high();
1760 inline void smt_prio_high();
1761
1762 public:
1763 inline void smt_prio_low();
1764 inline void smt_prio_medium_low();
1765 inline void smt_prio_medium();
1766 // >= Power7
1767 inline void smt_yield();
1768 inline void smt_mdoio();
1769 inline void smt_mdoom();
1770
1771 // trap instructions
1772 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1773 // NOT FOR DIRECT USE!!
1774 protected:
1775 inline void tdi_unchecked(int tobits, Register a, int si16);
1776 inline void twi_unchecked(int tobits, Register a, int si16);
1777 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1778 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1779 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP
1780 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP
1781
1782 static bool is_tdi(int x, int tobits, int ra, int si16) {
1783 return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
1784 && (tobits == inv_to_field(x))
1785 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1786 && (si16 == inv_si_field(x));
1787 }
1788
1789 static bool is_twi(int x, int tobits, int ra, int si16) {
1790 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1791 && (tobits == inv_to_field(x))
1792 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1793 && (si16 == inv_si_field(x));
1794 }
1795
1796 static bool is_twi(int x, int tobits, int ra) {
1797 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1798 && (tobits == inv_to_field(x))
1799 && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
1800 }
1801
1802 static bool is_td(int x, int tobits, int ra, int rb) {
1803 return (TD_OPCODE == (x & TD_OPCODE_MASK))
1804 && (tobits == inv_to_field(x))
1805 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1806 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1807 }
1808
1809 static bool is_tw(int x, int tobits, int ra, int rb) {
1810 return (TW_OPCODE == (x & TW_OPCODE_MASK))
1811 && (tobits == inv_to_field(x))
1812 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1813 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1814 }
1815
1816 public:
1817 // PPC floating point instructions
1818 // PPC 1, section 4.6.2 Floating-Point Load Instructions
1819 inline void lfs( FloatRegister d, int si16, Register a);
1820 inline void lfsu( FloatRegister d, int si16, Register a);
1821 inline void lfsx( FloatRegister d, Register a, Register b);
1822 inline void lfd( FloatRegister d, int si16, Register a);
1823 inline void lfdu( FloatRegister d, int si16, Register a);
1824 inline void lfdx( FloatRegister d, Register a, Register b);
1825
1826 // PPC 1, section 4.6.3 Floating-Point Store Instructions
1827 inline void stfs( FloatRegister s, int si16, Register a);
1828 inline void stfsu( FloatRegister s, int si16, Register a);
1829 inline void stfsx( FloatRegister s, Register a, Register b);
1830 inline void stfd( FloatRegister s, int si16, Register a);
1831 inline void stfdu( FloatRegister s, int si16, Register a);
1832 inline void stfdx( FloatRegister s, Register a, Register b);
1833
1834 // PPC 1, section 4.6.4 Floating-Point Move Instructions
1835 inline void fmr( FloatRegister d, FloatRegister b);
1836 inline void fmr_( FloatRegister d, FloatRegister b);
1837
1838 // inline void mffgpr( FloatRegister d, Register b);
1839 // inline void mftgpr( Register d, FloatRegister b);
1840 inline void cmpb( Register a, Register s, Register b);
1841 inline void popcntb(Register a, Register s);
1842 inline void popcntw(Register a, Register s);
1843 inline void popcntd(Register a, Register s);
1844
1845 inline void fneg( FloatRegister d, FloatRegister b);
1846 inline void fneg_( FloatRegister d, FloatRegister b);
1847 inline void fabs( FloatRegister d, FloatRegister b);
1848 inline void fabs_( FloatRegister d, FloatRegister b);
1849 inline void fnabs( FloatRegister d, FloatRegister b);
1850 inline void fnabs_(FloatRegister d, FloatRegister b);
1851
1852 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
1853 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b);
1854 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
1855 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
1856 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
1857 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b);
1858 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
1859 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
1860 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
1861 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c);
1862 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
1863 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
1864 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
1865 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b);
1866 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
1867 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
1868 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
1869
1870 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
1871 inline void frsp( FloatRegister d, FloatRegister b);
1872 inline void fctid( FloatRegister d, FloatRegister b);
1873 inline void fctidz(FloatRegister d, FloatRegister b);
1874 inline void fctiw( FloatRegister d, FloatRegister b);
1875 inline void fctiwz(FloatRegister d, FloatRegister b);
1876 inline void fcfid( FloatRegister d, FloatRegister b);
1877 inline void fcfids(FloatRegister d, FloatRegister b);
1878
1879 // PPC 1, section 4.6.7 Floating-Point Compare Instructions
1880 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
1881
1882 inline void fsqrt( FloatRegister d, FloatRegister b);
1883 inline void fsqrts(FloatRegister d, FloatRegister b);
1884
1885 // Vector instructions for >= Power6.
1886 inline void lvebx( VectorRegister d, Register s1, Register s2);
1887 inline void lvehx( VectorRegister d, Register s1, Register s2);
1888 inline void lvewx( VectorRegister d, Register s1, Register s2);
1889 inline void lvx( VectorRegister d, Register s1, Register s2);
1890 inline void lvxl( VectorRegister d, Register s1, Register s2);
1891 inline void stvebx( VectorRegister d, Register s1, Register s2);
1892 inline void stvehx( VectorRegister d, Register s1, Register s2);
1893 inline void stvewx( VectorRegister d, Register s1, Register s2);
1894 inline void stvx( VectorRegister d, Register s1, Register s2);
1895 inline void stvxl( VectorRegister d, Register s1, Register s2);
1896 inline void lvsl( VectorRegister d, Register s1, Register s2);
1897 inline void lvsr( VectorRegister d, Register s1, Register s2);
1898 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b);
1899 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b);
1900 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b);
1901 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b);
1902 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b);
1903 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b);
1904 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b);
1905 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b);
1906 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
1907 inline void vupkhpx( VectorRegister d, VectorRegister b);
1908 inline void vupkhsb( VectorRegister d, VectorRegister b);
1909 inline void vupkhsh( VectorRegister d, VectorRegister b);
1910 inline void vupklpx( VectorRegister d, VectorRegister b);
1911 inline void vupklsb( VectorRegister d, VectorRegister b);
1912 inline void vupklsh( VectorRegister d, VectorRegister b);
1913 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
1914 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
1915 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
1916 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
1917 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
1918 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
1919 inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
1920 inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
1921 inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
1922 inline void vspltisb( VectorRegister d, int si5);
1923 inline void vspltish( VectorRegister d, int si5);
1924 inline void vspltisw( VectorRegister d, int si5);
1925 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1926 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1927 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
1928 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4);
1929 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
1930 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
1931 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
1932 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1933 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
1934 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1935 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
1936 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
1937 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
1938 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
1939 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
1940 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
1941 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
1942 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1943 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
1944 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1945 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b);
1946 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b);
1947 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b);
1948 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b);
1949 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b);
1950 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b);
1951 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b);
1952 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b);
1953 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b);
1954 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b);
1955 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b);
1956 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b);
1957 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b);
1958 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b);
1959 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b);
1960 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1961 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
1962 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1963 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1964 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1965 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1966 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1967 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1968 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1969 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b);
1970 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
1971 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
1972 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
1973 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
1974 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b);
1975 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b);
1976 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b);
1977 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b);
1978 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b);
1979 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b);
1980 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b);
1981 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b);
1982 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b);
1983 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b);
1984 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b);
1985 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b);
1986 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b);
1987 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b);
1988 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b);
1989 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b);
1990 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b);
1991 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b);
1992 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
1993 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
1994 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
1995 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
1996 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
1997 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
1998 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
1999 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
2000 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
2001 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
2002 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
2003 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
2004 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
2005 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
2006 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
2007 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
2008 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
2009 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
2010 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b);
2011 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
2012 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
2013 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
2014 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
2015 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
2016 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
2017 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
2018 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2019 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2020 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2021 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2022 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2023 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2024 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2025 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2026 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2027 // Vector Floating-Point not implemented yet
2028 inline void mtvscr( VectorRegister b);
2029 inline void mfvscr( VectorRegister d);
2030
2031 // AES (introduced with Power 8)
2032 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2033 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2034 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2035 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2036 inline void vsbox( VectorRegister d, VectorRegister a);
2037
2038 // SHA (introduced with Power 8)
2039 // Not yet implemented.
2040
2041 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2042 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2043 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2044 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2045 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2046
2047 // Vector Permute and Xor (introduced with Power 8)
2048 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2049
2050 // Transactional Memory instructions (introduced with Power 8)
2051 inline void tbegin_(); // R=0
2052 inline void tbeginrot_(); // R=1 Rollback-Only Transaction
2053 inline void tend_(); // A=0
2054 inline void tendall_(); // A=1
2055 inline void tabort_();
2056 inline void tabort_(Register a);
2057 inline void tabortwc_(int t, Register a, Register b);
2058 inline void tabortwci_(int t, Register a, int si);
2059 inline void tabortdc_(int t, Register a, Register b);
2060 inline void tabortdci_(int t, Register a, int si);
2061 inline void tsuspend_(); // tsr with L=0
2062 inline void tresume_(); // tsr with L=1
2063 inline void tcheck(int f);
2064
2065 static bool is_tbegin(int x) {
2066 return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1));
2067 }
2068
2069 // The following encoders use r0 as second operand. These instructions
2070 // read r0 as '0'.
2071 inline void lwzx( Register d, Register s2);
2072 inline void lwz( Register d, int si16);
2073 inline void lwax( Register d, Register s2);
2074 inline void lwa( Register d, int si16);
2075 inline void lwbrx(Register d, Register s2);
2076 inline void lhzx( Register d, Register s2);
2077 inline void lhz( Register d, int si16);
2078 inline void lhax( Register d, Register s2);
2079 inline void lha( Register d, int si16);
2080 inline void lhbrx(Register d, Register s2);
2081 inline void lbzx( Register d, Register s2);
2082 inline void lbz( Register d, int si16);
2083 inline void ldx( Register d, Register s2);
2084 inline void ld( Register d, int si16);
2085 inline void stwx( Register d, Register s2);
2086 inline void stw( Register d, int si16);
2087 inline void sthx( Register d, Register s2);
2088 inline void sth( Register d, int si16);
2089 inline void stbx( Register d, Register s2);
2090 inline void stb( Register d, int si16);
2091 inline void stdx( Register d, Register s2);
2092 inline void std( Register d, int si16);
2093
2094 // PPC 2, section 3.2.1 Instruction Cache Instructions
2095 inline void icbi( Register s2);
2096 // PPC 2, section 3.2.2 Data Cache Instructions
2097 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
2098 inline void dcbz( Register s2);
2099 inline void dcbst( Register s2);
2100 inline void dcbf( Register s2);
2101 // dcache read hint
2102 inline void dcbt( Register s2);
2103 inline void dcbtct( Register s2, int ct);
2104 inline void dcbtds( Register s2, int ds);
2105 // dcache write hint
2106 inline void dcbtst( Register s2);
2107 inline void dcbtstct(Register s2, int ct);
2108
2109 // Atomics: use ra0mem to disallow R0 as base.
2110 inline void lwarx_unchecked(Register d, Register b, int eh1);
2111 inline void ldarx_unchecked(Register d, Register b, int eh1);
2112 inline void lqarx_unchecked(Register d, Register b, int eh1);
2113 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2114 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2115 inline void lqarx( Register d, Register b, bool hint_exclusive_access);
2116 inline void stwcx_(Register s, Register b);
2117 inline void stdcx_(Register s, Register b);
2118 inline void stqcx_(Register s, Register b);
2119 inline void lfs( FloatRegister d, int si16);
2120 inline void lfsx( FloatRegister d, Register b);
2121 inline void lfd( FloatRegister d, int si16);
2122 inline void lfdx( FloatRegister d, Register b);
2123 inline void stfs( FloatRegister s, int si16);
2124 inline void stfsx( FloatRegister s, Register b);
2125 inline void stfd( FloatRegister s, int si16);
2126 inline void stfdx( FloatRegister s, Register b);
2127 inline void lvebx( VectorRegister d, Register s2);
2128 inline void lvehx( VectorRegister d, Register s2);
2129 inline void lvewx( VectorRegister d, Register s2);
2130 inline void lvx( VectorRegister d, Register s2);
2131 inline void lvxl( VectorRegister d, Register s2);
2132 inline void stvebx(VectorRegister d, Register s2);
2133 inline void stvehx(VectorRegister d, Register s2);
2134 inline void stvewx(VectorRegister d, Register s2);
2135 inline void stvx( VectorRegister d, Register s2);
2136 inline void stvxl( VectorRegister d, Register s2);
2137 inline void lvsl( VectorRegister d, Register s2);
2138 inline void lvsr( VectorRegister d, Register s2);
2139
2140 // RegisterOrConstant versions.
2141 // These emitters choose between the versions using two registers and
2142 // those with register and immediate, depending on the content of roc.
2143 // If the constant is not encodable as immediate, instructions to
2144 // load the constant are emitted beforehand. Store instructions need a
2145 // tmp reg if the constant is not encodable as immediate.
2146 // Size unpredictable.
2147 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg);
2148 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2149 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2150 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2151 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2152 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2153 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2154 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2155 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2156 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2157 void add( Register d, RegisterOrConstant roc, Register s1);
2158 void subf(Register d, RegisterOrConstant roc, Register s1);
2159 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
2160
2161
2162 // Emit several instructions to load a 64 bit constant. This issues a fixed
2163 // instruction pattern so that the constant can be patched later on.
2164 enum {
2165 load_const_size = 5 * BytesPerInstWord
2166 };
2167 void load_const(Register d, long a, Register tmp = noreg);
2168 inline void load_const(Register d, void* a, Register tmp = noreg);
2169 inline void load_const(Register d, Label& L, Register tmp = noreg);
2170 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
2171
2172 // Load a 64 bit constant, optimized, not identifyable.
2173 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
2174 // 16 bit immediate offset. This is useful if the offset can be encoded in
2175 // a succeeding instruction.
2176 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false);
2177 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
2178 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
2179 }
2180
2181 // If return_simm16_rest, the return value needs to get added afterwards.
2182 int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false);
2183 inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
2184 return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
2185 }
2186
2187 // If return_simm16_rest, the return value needs to get added afterwards.
2188 inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) {
2189 return add_const_optimized(d, s, -x, tmp, return_simm16_rest);
2190 }
2191 inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
2192 return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
2193 }
2194
2195 // Creation
2196 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2197 #ifdef CHECK_DELAY
2198 delay_state = no_delay;
2199 #endif
2200 }
2201
2202 // Testing
2203 #ifndef PRODUCT
2204 void test_asm();
2205 #endif
2206 };
2207
2208
2209 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP