1 //
2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2015 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
900
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
906
907 source %{
908
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
925
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
937
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
954
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
961
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
976
977 return false;
978 }
979
980 #define __ _masm.
981
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
984
985 // ****************************************************************************
986
987 // REQUIRED FUNCTIONALITY
988
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
992
993 // PPC port: Removed use of lazy constant construct.
994
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
999
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1005
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1016
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1024
1025 //=============================================================================
1026
1027 // condition code conversions
1028
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1032
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1036
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1040
1041 //=============================================================================
1042
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1046
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1050
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1054
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1058
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1062
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1066
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1071
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1075
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1079
1080 //=============================================================================
1081
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1087
1088 //=============================================================================
1089
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1095
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1101
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1105
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1109
1110 //=============================================================================
1111
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1116
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1121
1122 //=============================================================================
1123
1124 %} // interrupt source
1125
1126 source_hpp %{ // Header information of the source block.
1127
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1131
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1133
1134 class CallStubImpl {
1135
1136 public:
1137
1138 // Emit call stub, compiled java to interpreter.
1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1140
1141 // Size of call trampoline stub.
1142 // This doesn't need to be accurate to the byte, but it
1143 // must be larger than or equal to the real size of the stub.
1144 static uint size_call_trampoline() {
1145 return trampoline_stub_size;
1146 }
1147
1148 // number of relocations needed by a call trampoline stub
1149 static uint reloc_call_trampoline() {
1150 return 5;
1151 }
1152
1153 };
1154
1155 %} // end source_hpp
1156
1157 source %{
1158
1159 // Emit a trampoline stub for a call to a target which is too far away.
1160 //
1161 // code sequences:
1162 //
1163 // call-site:
1164 // branch-and-link to <destination> or <trampoline stub>
1165 //
1166 // Related trampoline stub for this call-site in the stub section:
1167 // load the call target from the constant pool
1168 // branch via CTR (LR/link still points to the call-site above)
1169
1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1171 // Start the stub.
1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1173 if (stub == NULL) {
1174 Compile::current()->env()->record_out_of_memory_failure();
1175 return;
1176 }
1177
1178 // For java_to_interp stubs we use R11_scratch1 as scratch register
1179 // and in call trampoline stubs we use R12_scratch2. This way we
1180 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1181 Register reg_scratch = R12_scratch2;
1182
1183 // Create a trampoline stub relocation which relates this trampoline stub
1184 // with the call instruction at insts_call_instruction_offset in the
1185 // instructions code-section.
1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1187 const int stub_start_offset = __ offset();
1188
1189 // Now, create the trampoline stub's code:
1190 // - load the TOC
1191 // - load the call target from the constant pool
1192 // - call
1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1195 __ mtctr(reg_scratch);
1196 __ bctr();
1197
1198 const address stub_start_addr = __ addr_at(stub_start_offset);
1199
1200 // FIXME: Assert that the trampoline stub can be identified and patched.
1201
1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1204 "encoded offset into the constant pool must match");
1205 // Trampoline_stub_size should be good.
1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1208
1209 // End the stub.
1210 __ end_a_stub();
1211 }
1212
1213 //=============================================================================
1214
1215 // Emit an inline branch-and-link call and a related trampoline stub.
1216 //
1217 // code sequences:
1218 //
1219 // call-site:
1220 // branch-and-link to <destination> or <trampoline stub>
1221 //
1222 // Related trampoline stub for this call-site in the stub section:
1223 // load the call target from the constant pool
1224 // branch via CTR (LR/link still points to the call-site above)
1225 //
1226
1227 typedef struct {
1228 int insts_call_instruction_offset;
1229 int ret_addr_offset;
1230 } EmitCallOffsets;
1231
1232 // Emit a branch-and-link instruction that branches to a trampoline.
1233 // - Remember the offset of the branch-and-link instruction.
1234 // - Add a relocation at the branch-and-link instruction.
1235 // - Emit a branch-and-link.
1236 // - Remember the return pc offset.
1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1238 EmitCallOffsets offsets = { -1, -1 };
1239 const int start_offset = __ offset();
1240 offsets.insts_call_instruction_offset = __ offset();
1241
1242 // No entry point given, use the current pc.
1243 if (entry_point == NULL) entry_point = __ pc();
1244
1245 if (!Compile::current()->in_scratch_emit_size()) {
1246 // Put the entry point as a constant into the constant pool.
1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1249
1250 // Emit the trampoline stub which will be related to the branch-and-link below.
1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1252 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full.
1253 __ relocate(rtype);
1254 }
1255
1256 // Note: At this point we do not have the address of the trampoline
1257 // stub, and the entry point might be too far away for bl, so __ pc()
1258 // serves as dummy and the bl will be patched later.
1259 __ bl((address) __ pc());
1260
1261 offsets.ret_addr_offset = __ offset() - start_offset;
1262
1263 return offsets;
1264 }
1265
1266 //=============================================================================
1267
1268 // Factory for creating loadConL* nodes for large/small constant pool.
1269
1270 static inline jlong replicate_immF(float con) {
1271 // Replicate float con 2 times and pack into vector.
1272 int val = *((int*)&con);
1273 jlong lval = val;
1274 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1275 return lval;
1276 }
1277
1278 //=============================================================================
1279
1280 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1281 int Compile::ConstantTable::calculate_table_base_offset() const {
1282 return 0; // absolute addressing, no offset
1283 }
1284
1285 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1286 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1287 iRegPdstOper *op_dst = new iRegPdstOper();
1288 MachNode *m1 = new loadToc_hiNode();
1289 MachNode *m2 = new loadToc_loNode();
1290
1291 m1->add_req(NULL);
1292 m2->add_req(NULL, m1);
1293 m1->_opnds[0] = op_dst;
1294 m2->_opnds[0] = op_dst;
1295 m2->_opnds[1] = op_dst;
1296 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1297 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1298 nodes->push(m1);
1299 nodes->push(m2);
1300 }
1301
1302 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1303 // Is postalloc expanded.
1304 ShouldNotReachHere();
1305 }
1306
1307 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1308 return 0;
1309 }
1310
1311 #ifndef PRODUCT
1312 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1313 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1314 }
1315 #endif
1316
1317 //=============================================================================
1318
1319 #ifndef PRODUCT
1320 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1321 Compile* C = ra_->C;
1322 const long framesize = C->frame_slots() << LogBytesPerInt;
1323
1324 st->print("PROLOG\n\t");
1325 if (C->need_stack_bang(framesize)) {
1326 st->print("stack_overflow_check\n\t");
1327 }
1328
1329 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1330 st->print("save return pc\n\t");
1331 st->print("push frame %ld\n\t", -framesize);
1332 }
1333 }
1334 #endif
1335
1336 // Macro used instead of the common __ to emulate the pipes of PPC.
1337 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1338 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1339 // still no scheduling of this code is possible, the micro scheduler is aware of the
1340 // code and can update its internal data. The following mechanism is used to achieve this:
1341 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1342 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1343 #if 0 // TODO: PPC port
1344 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1345 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1346 _masm.
1347 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1348 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1349 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1350 C->hb_scheduling()->_pdScheduling->advance_offset
1351 #else
1352 #define ___(op) if (UsePower6SchedulerPPC64) \
1353 Unimplemented(); \
1354 _masm.
1355 #define ___stop if (UsePower6SchedulerPPC64) \
1356 Unimplemented()
1357 #define ___advance if (UsePower6SchedulerPPC64) \
1358 Unimplemented()
1359 #endif
1360
1361 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1362 Compile* C = ra_->C;
1363 MacroAssembler _masm(&cbuf);
1364
1365 const long framesize = C->frame_size_in_bytes();
1366 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1367
1368 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1369
1370 const Register return_pc = R20; // Must match return_addr() in frame section.
1371 const Register callers_sp = R21;
1372 const Register push_frame_temp = R22;
1373 const Register toc_temp = R23;
1374 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1375
1376 if (method_is_frameless) {
1377 // Add nop at beginning of all frameless methods to prevent any
1378 // oop instructions from getting overwritten by make_not_entrant
1379 // (patching attempt would fail).
1380 ___(nop) nop();
1381 } else {
1382 // Get return pc.
1383 ___(mflr) mflr(return_pc);
1384 }
1385
1386 // Calls to C2R adapters often do not accept exceptional returns.
1387 // We require that their callers must bang for them. But be
1388 // careful, because some VM calls (such as call site linkage) can
1389 // use several kilobytes of stack. But the stack safety zone should
1390 // account for that. See bugs 4446381, 4468289, 4497237.
1391
1392 int bangsize = C->bang_size_in_bytes();
1393 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1394 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1395 // Unfortunately we cannot use the function provided in
1396 // assembler.cpp as we have to emulate the pipes. So I had to
1397 // insert the code of generate_stack_overflow_check(), see
1398 // assembler.cpp for some illuminative comments.
1399 const int page_size = os::vm_page_size();
1400 int bang_end = StackShadowPages * page_size;
1401
1402 // This is how far the previous frame's stack banging extended.
1403 const int bang_end_safe = bang_end;
1404
1405 if (bangsize > page_size) {
1406 bang_end += bangsize;
1407 }
1408
1409 int bang_offset = bang_end_safe;
1410
1411 while (bang_offset <= bang_end) {
1412 // Need at least one stack bang at end of shadow zone.
1413
1414 // Again I had to copy code, this time from assembler_ppc.cpp,
1415 // bang_stack_with_offset - see there for comments.
1416
1417 // Stack grows down, caller passes positive offset.
1418 assert(bang_offset > 0, "must bang with positive offset");
1419
1420 long stdoffset = -bang_offset;
1421
1422 if (Assembler::is_simm(stdoffset, 16)) {
1423 // Signed 16 bit offset, a simple std is ok.
1424 if (UseLoadInstructionsForStackBangingPPC64) {
1425 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1426 } else {
1427 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1428 }
1429 } else if (Assembler::is_simm(stdoffset, 31)) {
1430 // Use largeoffset calculations for addis & ld/std.
1431 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1432 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1433
1434 Register tmp = R11;
1435 ___(addis) addis(tmp, R1_SP, hi);
1436 if (UseLoadInstructionsForStackBangingPPC64) {
1437 ___(ld) ld(R0, lo, tmp);
1438 } else {
1439 ___(std) std(R0, lo, tmp);
1440 }
1441 } else {
1442 ShouldNotReachHere();
1443 }
1444
1445 bang_offset += page_size;
1446 }
1447 // R11 trashed
1448 } // C->need_stack_bang(framesize) && UseStackBanging
1449
1450 unsigned int bytes = (unsigned int)framesize;
1451 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1452 ciMethod *currMethod = C->method();
1453
1454 // Optimized version for most common case.
1455 if (UsePower6SchedulerPPC64 &&
1456 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1457 !(false /* ConstantsALot TODO: PPC port*/)) {
1458 ___(or) mr(callers_sp, R1_SP);
1459 ___(std) std(return_pc, _abi(lr), R1_SP);
1460 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1461 return;
1462 }
1463
1464 if (!method_is_frameless) {
1465 // Get callers sp.
1466 ___(or) mr(callers_sp, R1_SP);
1467
1468 // Push method's frame, modifies SP.
1469 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1470 // The ABI is already accounted for in 'framesize' via the
1471 // 'out_preserve' area.
1472 Register tmp = push_frame_temp;
1473 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1474 if (Assembler::is_simm(-offset, 16)) {
1475 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1476 } else {
1477 long x = -offset;
1478 // Had to insert load_const(tmp, -offset).
1479 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1480 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1481 ___(rldicr) sldi(tmp, tmp, 32);
1482 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1483 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1484
1485 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1486 }
1487 }
1488 #if 0 // TODO: PPC port
1489 // For testing large constant pools, emit a lot of constants to constant pool.
1490 // "Randomize" const_size.
1491 if (ConstantsALot) {
1492 const int num_consts = const_size();
1493 for (int i = 0; i < num_consts; i++) {
1494 __ long_constant(0xB0B5B00BBABE);
1495 }
1496 }
1497 #endif
1498 if (!method_is_frameless) {
1499 // Save return pc.
1500 ___(std) std(return_pc, _abi(lr), callers_sp);
1501 }
1502 }
1503 #undef ___
1504 #undef ___stop
1505 #undef ___advance
1506
1507 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1508 // Variable size. determine dynamically.
1509 return MachNode::size(ra_);
1510 }
1511
1512 int MachPrologNode::reloc() const {
1513 // Return number of relocatable values contained in this instruction.
1514 return 1; // 1 reloc entry for load_const(toc).
1515 }
1516
1517 //=============================================================================
1518
1519 #ifndef PRODUCT
1520 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1521 Compile* C = ra_->C;
1522
1523 st->print("EPILOG\n\t");
1524 st->print("restore return pc\n\t");
1525 st->print("pop frame\n\t");
1526
1527 if (do_polling() && C->is_method_compilation()) {
1528 st->print("touch polling page\n\t");
1529 }
1530 }
1531 #endif
1532
1533 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1534 Compile* C = ra_->C;
1535 MacroAssembler _masm(&cbuf);
1536
1537 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1538 assert(framesize >= 0, "negative frame-size?");
1539
1540 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1541 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1542 const Register return_pc = R11;
1543 const Register polling_page = R12;
1544
1545 if (!method_is_frameless) {
1546 // Restore return pc relative to callers' sp.
1547 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1548 }
1549
1550 if (method_needs_polling) {
1551 if (LoadPollAddressFromThread) {
1552 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1553 Unimplemented();
1554 } else {
1555 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1556 }
1557 }
1558
1559 if (!method_is_frameless) {
1560 // Move return pc to LR.
1561 __ mtlr(return_pc);
1562 // Pop frame (fixed frame-size).
1563 __ addi(R1_SP, R1_SP, (int)framesize);
1564 }
1565
1566 if (method_needs_polling) {
1567 // We need to mark the code position where the load from the safepoint
1568 // polling page was emitted as relocInfo::poll_return_type here.
1569 __ relocate(relocInfo::poll_return_type);
1570 __ load_from_polling_page(polling_page);
1571 }
1572 }
1573
1574 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1575 // Variable size. Determine dynamically.
1576 return MachNode::size(ra_);
1577 }
1578
1579 int MachEpilogNode::reloc() const {
1580 // Return number of relocatable values contained in this instruction.
1581 return 1; // 1 for load_from_polling_page.
1582 }
1583
1584 const Pipeline * MachEpilogNode::pipeline() const {
1585 return MachNode::pipeline_class();
1586 }
1587
1588 // This method seems to be obsolete. It is declared in machnode.hpp
1589 // and defined in all *.ad files, but it is never called. Should we
1590 // get rid of it?
1591 int MachEpilogNode::safepoint_offset() const {
1592 assert(do_polling(), "no return for this epilog node");
1593 return 0;
1594 }
1595
1596 #if 0 // TODO: PPC port
1597 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1598 MacroAssembler _masm(&cbuf);
1599 if (LoadPollAddressFromThread) {
1600 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1601 } else {
1602 _masm.nop();
1603 }
1604 }
1605
1606 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1607 if (LoadPollAddressFromThread) {
1608 return 4;
1609 } else {
1610 return 4;
1611 }
1612 }
1613
1614 #ifndef PRODUCT
1615 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1616 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1617 }
1618 #endif
1619
1620 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1621 return RSCRATCH1_BITS64_REG_mask();
1622 }
1623 #endif // PPC port
1624
1625 // =============================================================================
1626
1627 // Figure out which register class each belongs in: rc_int, rc_float or
1628 // rc_stack.
1629 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1630
1631 static enum RC rc_class(OptoReg::Name reg) {
1632 // Return the register class for the given register. The given register
1633 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1634 // enumeration in adGlobals_ppc.hpp.
1635
1636 if (reg == OptoReg::Bad) return rc_bad;
1637
1638 // We have 64 integer register halves, starting at index 0.
1639 if (reg < 64) return rc_int;
1640
1641 // We have 64 floating-point register halves, starting at index 64.
1642 if (reg < 64+64) return rc_float;
1643
1644 // Between float regs & stack are the flags regs.
1645 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1646
1647 return rc_stack;
1648 }
1649
1650 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1651 bool do_print, Compile* C, outputStream *st) {
1652
1653 assert(opcode == Assembler::LD_OPCODE ||
1654 opcode == Assembler::STD_OPCODE ||
1655 opcode == Assembler::LWZ_OPCODE ||
1656 opcode == Assembler::STW_OPCODE ||
1657 opcode == Assembler::LFD_OPCODE ||
1658 opcode == Assembler::STFD_OPCODE ||
1659 opcode == Assembler::LFS_OPCODE ||
1660 opcode == Assembler::STFS_OPCODE,
1661 "opcode not supported");
1662
1663 if (cbuf) {
1664 int d =
1665 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1666 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1667 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1668 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1669 }
1670 #ifndef PRODUCT
1671 else if (do_print) {
1672 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1673 op_str,
1674 Matcher::regName[reg],
1675 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1676 }
1677 #endif
1678 return 4; // size
1679 }
1680
1681 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1682 Compile* C = ra_->C;
1683
1684 // Get registers to move.
1685 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1686 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1687 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1688 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1689
1690 enum RC src_hi_rc = rc_class(src_hi);
1691 enum RC src_lo_rc = rc_class(src_lo);
1692 enum RC dst_hi_rc = rc_class(dst_hi);
1693 enum RC dst_lo_rc = rc_class(dst_lo);
1694
1695 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1696 if (src_hi != OptoReg::Bad)
1697 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1698 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1699 "expected aligned-adjacent pairs");
1700 // Generate spill code!
1701 int size = 0;
1702
1703 if (src_lo == dst_lo && src_hi == dst_hi)
1704 return size; // Self copy, no move.
1705
1706 // --------------------------------------
1707 // Memory->Memory Spill. Use R0 to hold the value.
1708 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1709 int src_offset = ra_->reg2offset(src_lo);
1710 int dst_offset = ra_->reg2offset(dst_lo);
1711 if (src_hi != OptoReg::Bad) {
1712 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1713 "expected same type of move for high parts");
1714 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1715 if (!cbuf && !do_size) st->print("\n\t");
1716 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1717 } else {
1718 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1719 if (!cbuf && !do_size) st->print("\n\t");
1720 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1721 }
1722 return size;
1723 }
1724
1725 // --------------------------------------
1726 // Check for float->int copy; requires a trip through memory.
1727 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1728 Unimplemented();
1729 }
1730
1731 // --------------------------------------
1732 // Check for integer reg-reg copy.
1733 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1734 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1735 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1736 size = (Rsrc != Rdst) ? 4 : 0;
1737
1738 if (cbuf) {
1739 MacroAssembler _masm(cbuf);
1740 if (size) {
1741 __ mr(Rdst, Rsrc);
1742 }
1743 }
1744 #ifndef PRODUCT
1745 else if (!do_size) {
1746 if (size) {
1747 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1748 } else {
1749 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1750 }
1751 }
1752 #endif
1753 return size;
1754 }
1755
1756 // Check for integer store.
1757 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1758 int dst_offset = ra_->reg2offset(dst_lo);
1759 if (src_hi != OptoReg::Bad) {
1760 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1761 "expected same type of move for high parts");
1762 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1763 } else {
1764 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1765 }
1766 return size;
1767 }
1768
1769 // Check for integer load.
1770 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1771 int src_offset = ra_->reg2offset(src_lo);
1772 if (src_hi != OptoReg::Bad) {
1773 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1774 "expected same type of move for high parts");
1775 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1776 } else {
1777 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1778 }
1779 return size;
1780 }
1781
1782 // Check for float reg-reg copy.
1783 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1784 if (cbuf) {
1785 MacroAssembler _masm(cbuf);
1786 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1787 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1788 __ fmr(Rdst, Rsrc);
1789 }
1790 #ifndef PRODUCT
1791 else if (!do_size) {
1792 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1793 }
1794 #endif
1795 return 4;
1796 }
1797
1798 // Check for float store.
1799 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1800 int dst_offset = ra_->reg2offset(dst_lo);
1801 if (src_hi != OptoReg::Bad) {
1802 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1803 "expected same type of move for high parts");
1804 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1805 } else {
1806 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1807 }
1808 return size;
1809 }
1810
1811 // Check for float load.
1812 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1813 int src_offset = ra_->reg2offset(src_lo);
1814 if (src_hi != OptoReg::Bad) {
1815 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1816 "expected same type of move for high parts");
1817 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1818 } else {
1819 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1820 }
1821 return size;
1822 }
1823
1824 // --------------------------------------------------------------------
1825 // Check for hi bits still needing moving. Only happens for misaligned
1826 // arguments to native calls.
1827 if (src_hi == dst_hi)
1828 return size; // Self copy; no move.
1829
1830 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1831 ShouldNotReachHere(); // Unimplemented
1832 return 0;
1833 }
1834
1835 #ifndef PRODUCT
1836 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1837 if (!ra_)
1838 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1839 else
1840 implementation(NULL, ra_, false, st);
1841 }
1842 #endif
1843
1844 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1845 implementation(&cbuf, ra_, false, NULL);
1846 }
1847
1848 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1849 return implementation(NULL, ra_, true, NULL);
1850 }
1851
1852 #if 0 // TODO: PPC port
1853 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1854 #ifndef PRODUCT
1855 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1856 #endif
1857 assert(ra_->node_regs_max_index() != 0, "");
1858
1859 // Get registers to move.
1860 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1861 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1862 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1863 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1864
1865 enum RC src_lo_rc = rc_class(src_lo);
1866 enum RC dst_lo_rc = rc_class(dst_lo);
1867
1868 if (src_lo == dst_lo && src_hi == dst_hi)
1869 return ppc64Opcode_none; // Self copy, no move.
1870
1871 // --------------------------------------
1872 // Memory->Memory Spill. Use R0 to hold the value.
1873 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1874 return ppc64Opcode_compound;
1875 }
1876
1877 // --------------------------------------
1878 // Check for float->int copy; requires a trip through memory.
1879 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1880 Unimplemented();
1881 }
1882
1883 // --------------------------------------
1884 // Check for integer reg-reg copy.
1885 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1886 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1887 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1888 if (Rsrc == Rdst) {
1889 return ppc64Opcode_none;
1890 } else {
1891 return ppc64Opcode_or;
1892 }
1893 }
1894
1895 // Check for integer store.
1896 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1897 if (src_hi != OptoReg::Bad) {
1898 return ppc64Opcode_std;
1899 } else {
1900 return ppc64Opcode_stw;
1901 }
1902 }
1903
1904 // Check for integer load.
1905 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1906 if (src_hi != OptoReg::Bad) {
1907 return ppc64Opcode_ld;
1908 } else {
1909 return ppc64Opcode_lwz;
1910 }
1911 }
1912
1913 // Check for float reg-reg copy.
1914 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1915 return ppc64Opcode_fmr;
1916 }
1917
1918 // Check for float store.
1919 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1920 if (src_hi != OptoReg::Bad) {
1921 return ppc64Opcode_stfd;
1922 } else {
1923 return ppc64Opcode_stfs;
1924 }
1925 }
1926
1927 // Check for float load.
1928 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1929 if (src_hi != OptoReg::Bad) {
1930 return ppc64Opcode_lfd;
1931 } else {
1932 return ppc64Opcode_lfs;
1933 }
1934 }
1935
1936 // --------------------------------------------------------------------
1937 // Check for hi bits still needing moving. Only happens for misaligned
1938 // arguments to native calls.
1939 if (src_hi == dst_hi) {
1940 return ppc64Opcode_none; // Self copy; no move.
1941 }
1942
1943 ShouldNotReachHere();
1944 return ppc64Opcode_undefined;
1945 }
1946 #endif // PPC port
1947
1948 #ifndef PRODUCT
1949 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1950 st->print("NOP \t// %d nops to pad for loops.", _count);
1951 }
1952 #endif
1953
1954 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1955 MacroAssembler _masm(&cbuf);
1956 // _count contains the number of nops needed for padding.
1957 for (int i = 0; i < _count; i++) {
1958 __ nop();
1959 }
1960 }
1961
1962 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1963 return _count * 4;
1964 }
1965
1966 #ifndef PRODUCT
1967 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1968 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1969 char reg_str[128];
1970 ra_->dump_register(this, reg_str);
1971 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1972 }
1973 #endif
1974
1975 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1976 MacroAssembler _masm(&cbuf);
1977
1978 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1979 int reg = ra_->get_encode(this);
1980
1981 if (Assembler::is_simm(offset, 16)) {
1982 __ addi(as_Register(reg), R1, offset);
1983 } else {
1984 ShouldNotReachHere();
1985 }
1986 }
1987
1988 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1989 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1990 return 4;
1991 }
1992
1993 #ifndef PRODUCT
1994 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1995 st->print_cr("---- MachUEPNode ----");
1996 st->print_cr("...");
1997 }
1998 #endif
1999
2000 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2001 // This is the unverified entry point.
2002 MacroAssembler _masm(&cbuf);
2003
2004 // Inline_cache contains a klass.
2005 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2006 Register receiver_klass = R12_scratch2; // tmp
2007
2008 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2009 assert(R11_scratch1 == R11, "need prologue scratch register");
2010
2011 // Check for NULL argument if we don't have implicit null checks.
2012 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2013 if (TrapBasedNullChecks) {
2014 __ trap_null_check(R3_ARG1);
2015 } else {
2016 Label valid;
2017 __ cmpdi(CCR0, R3_ARG1, 0);
2018 __ bne_predict_taken(CCR0, valid);
2019 // We have a null argument, branch to ic_miss_stub.
2020 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2021 relocInfo::runtime_call_type);
2022 __ bind(valid);
2023 }
2024 }
2025 // Assume argument is not NULL, load klass from receiver.
2026 __ load_klass(receiver_klass, R3_ARG1);
2027
2028 if (TrapBasedICMissChecks) {
2029 __ trap_ic_miss_check(receiver_klass, ic_klass);
2030 } else {
2031 Label valid;
2032 __ cmpd(CCR0, receiver_klass, ic_klass);
2033 __ beq_predict_taken(CCR0, valid);
2034 // We have an unexpected klass, branch to ic_miss_stub.
2035 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2036 relocInfo::runtime_call_type);
2037 __ bind(valid);
2038 }
2039
2040 // Argument is valid and klass is as expected, continue.
2041 }
2042
2043 #if 0 // TODO: PPC port
2044 // Optimize UEP code on z (save a load_const() call in main path).
2045 int MachUEPNode::ep_offset() {
2046 return 0;
2047 }
2048 #endif
2049
2050 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2051 // Variable size. Determine dynamically.
2052 return MachNode::size(ra_);
2053 }
2054
2055 //=============================================================================
2056
2057 %} // interrupt source
2058
2059 source_hpp %{ // Header information of the source block.
2060
2061 class HandlerImpl {
2062
2063 public:
2064
2065 static int emit_exception_handler(CodeBuffer &cbuf);
2066 static int emit_deopt_handler(CodeBuffer& cbuf);
2067
2068 static uint size_exception_handler() {
2069 // The exception_handler is a b64_patchable.
2070 return MacroAssembler::b64_patchable_size;
2071 }
2072
2073 static uint size_deopt_handler() {
2074 // The deopt_handler is a bl64_patchable.
2075 return MacroAssembler::bl64_patchable_size;
2076 }
2077
2078 };
2079
2080 %} // end source_hpp
2081
2082 source %{
2083
2084 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2085 MacroAssembler _masm(&cbuf);
2086
2087 address base = __ start_a_stub(size_exception_handler());
2088 if (base == NULL) return 0; // CodeBuffer::expand failed
2089
2090 int offset = __ offset();
2091 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2092 relocInfo::runtime_call_type);
2093 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2094 __ end_a_stub();
2095
2096 return offset;
2097 }
2098
2099 // The deopt_handler is like the exception handler, but it calls to
2100 // the deoptimization blob instead of jumping to the exception blob.
2101 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2102 MacroAssembler _masm(&cbuf);
2103
2104 address base = __ start_a_stub(size_deopt_handler());
2105 if (base == NULL) return 0; // CodeBuffer::expand failed
2106
2107 int offset = __ offset();
2108 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2109 relocInfo::runtime_call_type);
2110 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2111 __ end_a_stub();
2112
2113 return offset;
2114 }
2115
2116 //=============================================================================
2117
2118 // Use a frame slots bias for frameless methods if accessing the stack.
2119 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2120 if (as_Register(reg_enc) == R1_SP) {
2121 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2122 }
2123 return 0;
2124 }
2125
2126 const bool Matcher::match_rule_supported(int opcode) {
2127 if (!has_match_rule(opcode))
2128 return false;
2129
2130 switch (opcode) {
2131 case Op_SqrtD:
2132 return VM_Version::has_fsqrt();
2133 case Op_CountLeadingZerosI:
2134 case Op_CountLeadingZerosL:
2135 case Op_CountTrailingZerosI:
2136 case Op_CountTrailingZerosL:
2137 if (!UseCountLeadingZerosInstructionsPPC64)
2138 return false;
2139 break;
2140
2141 case Op_PopCountI:
2142 case Op_PopCountL:
2143 return (UsePopCountInstruction && VM_Version::has_popcntw());
2144
2145 case Op_StrComp:
2146 return SpecialStringCompareTo;
2147 case Op_StrEquals:
2148 return SpecialStringEquals;
2149 case Op_StrIndexOf:
2150 return SpecialStringIndexOf;
2151 }
2152
2153 return true; // Per default match rules are supported.
2154 }
2155
2156 int Matcher::regnum_to_fpu_offset(int regnum) {
2157 // No user for this method?
2158 Unimplemented();
2159 return 999;
2160 }
2161
2162 const bool Matcher::convL2FSupported(void) {
2163 // fcfids can do the conversion (>= Power7).
2164 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2165 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2166 }
2167
2168 // Vector width in bytes.
2169 const int Matcher::vector_width_in_bytes(BasicType bt) {
2170 assert(MaxVectorSize == 8, "");
2171 return 8;
2172 }
2173
2174 // Vector ideal reg.
2175 const int Matcher::vector_ideal_reg(int size) {
2176 assert(MaxVectorSize == 8 && size == 8, "");
2177 return Op_RegL;
2178 }
2179
2180 const int Matcher::vector_shift_count_ideal_reg(int size) {
2181 fatal("vector shift is not supported");
2182 return Node::NotAMachineReg;
2183 }
2184
2185 // Limits on vector size (number of elements) loaded into vector.
2186 const int Matcher::max_vector_size(const BasicType bt) {
2187 assert(is_java_primitive(bt), "only primitive type vectors");
2188 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2189 }
2190
2191 const int Matcher::min_vector_size(const BasicType bt) {
2192 return max_vector_size(bt); // Same as max.
2193 }
2194
2195 // PPC doesn't support misaligned vectors store/load.
2196 const bool Matcher::misaligned_vectors_ok() {
2197 return false;
2198 }
2199
2200 // PPC AES support not yet implemented
2201 const bool Matcher::pass_original_key_for_aes() {
2202 return false;
2203 }
2204
2205 // RETURNS: whether this branch offset is short enough that a short
2206 // branch can be used.
2207 //
2208 // If the platform does not provide any short branch variants, then
2209 // this method should return `false' for offset 0.
2210 //
2211 // `Compile::Fill_buffer' will decide on basis of this information
2212 // whether to do the pass `Compile::Shorten_branches' at all.
2213 //
2214 // And `Compile::Shorten_branches' will decide on basis of this
2215 // information whether to replace particular branch sites by short
2216 // ones.
2217 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2218 // Is the offset within the range of a ppc64 pc relative branch?
2219 bool b;
2220
2221 const int safety_zone = 3 * BytesPerInstWord;
2222 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2223 29 - 16 + 1 + 2);
2224 return b;
2225 }
2226
2227 const bool Matcher::isSimpleConstant64(jlong value) {
2228 // Probably always true, even if a temp register is required.
2229 return true;
2230 }
2231 /* TODO: PPC port
2232 // Make a new machine dependent decode node (with its operands).
2233 MachTypeNode *Matcher::make_decode_node() {
2234 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2235 "This method is only implemented for unscaled cOops mode so far");
2236 MachTypeNode *decode = new decodeN_unscaledNode();
2237 decode->set_opnd_array(0, new iRegPdstOper());
2238 decode->set_opnd_array(1, new iRegNsrcOper());
2239 return decode;
2240 }
2241 */
2242 // Threshold size for cleararray.
2243 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2244
2245 // false => size gets scaled to BytesPerLong, ok.
2246 const bool Matcher::init_array_count_is_in_bytes = false;
2247
2248 // Use conditional move (CMOVL) on Power7.
2249 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2250
2251 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2252 // fsel doesn't accept a condition register as input, so this would be slightly different.
2253 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2254
2255 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2256 const bool Matcher::require_postalloc_expand = true;
2257
2258 // Should the Matcher clone shifts on addressing modes, expecting them to
2259 // be subsumed into complex addressing expressions or compute them into
2260 // registers? True for Intel but false for most RISCs.
2261 const bool Matcher::clone_shift_expressions = false;
2262
2263 // Do we need to mask the count passed to shift instructions or does
2264 // the cpu only look at the lower 5/6 bits anyway?
2265 // Off, as masks are generated in expand rules where required.
2266 // Constant shift counts are handled in Ideal phase.
2267 const bool Matcher::need_masked_shift_count = false;
2268
2269 // This affects two different things:
2270 // - how Decode nodes are matched
2271 // - how ImplicitNullCheck opportunities are recognized
2272 // If true, the matcher will try to remove all Decodes and match them
2273 // (as operands) into nodes. NullChecks are not prepared to deal with
2274 // Decodes by final_graph_reshaping().
2275 // If false, final_graph_reshaping() forces the decode behind the Cmp
2276 // for a NullCheck. The matcher matches the Decode node into a register.
2277 // Implicit_null_check optimization moves the Decode along with the
2278 // memory operation back up before the NullCheck.
2279 bool Matcher::narrow_oop_use_complex_address() {
2280 // TODO: PPC port if (MatchDecodeNodes) return true;
2281 return false;
2282 }
2283
2284 bool Matcher::narrow_klass_use_complex_address() {
2285 NOT_LP64(ShouldNotCallThis());
2286 assert(UseCompressedClassPointers, "only for compressed klass code");
2287 // TODO: PPC port if (MatchDecodeNodes) return true;
2288 return false;
2289 }
2290
2291 // Is it better to copy float constants, or load them directly from memory?
2292 // Intel can load a float constant from a direct address, requiring no
2293 // extra registers. Most RISCs will have to materialize an address into a
2294 // register first, so they would do better to copy the constant from stack.
2295 const bool Matcher::rematerialize_float_constants = false;
2296
2297 // If CPU can load and store mis-aligned doubles directly then no fixup is
2298 // needed. Else we split the double into 2 integer pieces and move it
2299 // piece-by-piece. Only happens when passing doubles into C code as the
2300 // Java calling convention forces doubles to be aligned.
2301 const bool Matcher::misaligned_doubles_ok = true;
2302
2303 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2304 Unimplemented();
2305 }
2306
2307 // Advertise here if the CPU requires explicit rounding operations
2308 // to implement the UseStrictFP mode.
2309 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2310
2311 // Do floats take an entire double register or just half?
2312 //
2313 // A float occupies a ppc64 double register. For the allocator, a
2314 // ppc64 double register appears as a pair of float registers.
2315 bool Matcher::float_in_double() { return true; }
2316
2317 // Do ints take an entire long register or just half?
2318 // The relevant question is how the int is callee-saved:
2319 // the whole long is written but de-opt'ing will have to extract
2320 // the relevant 32 bits.
2321 const bool Matcher::int_in_long = true;
2322
2323 // Constants for c2c and c calling conventions.
2324
2325 const MachRegisterNumbers iarg_reg[8] = {
2326 R3_num, R4_num, R5_num, R6_num,
2327 R7_num, R8_num, R9_num, R10_num
2328 };
2329
2330 const MachRegisterNumbers farg_reg[13] = {
2331 F1_num, F2_num, F3_num, F4_num,
2332 F5_num, F6_num, F7_num, F8_num,
2333 F9_num, F10_num, F11_num, F12_num,
2334 F13_num
2335 };
2336
2337 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2338
2339 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2340
2341 // Return whether or not this register is ever used as an argument. This
2342 // function is used on startup to build the trampoline stubs in generateOptoStub.
2343 // Registers not mentioned will be killed by the VM call in the trampoline, and
2344 // arguments in those registers not be available to the callee.
2345 bool Matcher::can_be_java_arg(int reg) {
2346 // We return true for all registers contained in iarg_reg[] and
2347 // farg_reg[] and their virtual halves.
2348 // We must include the virtual halves in order to get STDs and LDs
2349 // instead of STWs and LWs in the trampoline stubs.
2350
2351 if ( reg == R3_num || reg == R3_H_num
2352 || reg == R4_num || reg == R4_H_num
2353 || reg == R5_num || reg == R5_H_num
2354 || reg == R6_num || reg == R6_H_num
2355 || reg == R7_num || reg == R7_H_num
2356 || reg == R8_num || reg == R8_H_num
2357 || reg == R9_num || reg == R9_H_num
2358 || reg == R10_num || reg == R10_H_num)
2359 return true;
2360
2361 if ( reg == F1_num || reg == F1_H_num
2362 || reg == F2_num || reg == F2_H_num
2363 || reg == F3_num || reg == F3_H_num
2364 || reg == F4_num || reg == F4_H_num
2365 || reg == F5_num || reg == F5_H_num
2366 || reg == F6_num || reg == F6_H_num
2367 || reg == F7_num || reg == F7_H_num
2368 || reg == F8_num || reg == F8_H_num
2369 || reg == F9_num || reg == F9_H_num
2370 || reg == F10_num || reg == F10_H_num
2371 || reg == F11_num || reg == F11_H_num
2372 || reg == F12_num || reg == F12_H_num
2373 || reg == F13_num || reg == F13_H_num)
2374 return true;
2375
2376 return false;
2377 }
2378
2379 bool Matcher::is_spillable_arg(int reg) {
2380 return can_be_java_arg(reg);
2381 }
2382
2383 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2384 return false;
2385 }
2386
2387 // Register for DIVI projection of divmodI.
2388 RegMask Matcher::divI_proj_mask() {
2389 ShouldNotReachHere();
2390 return RegMask();
2391 }
2392
2393 // Register for MODI projection of divmodI.
2394 RegMask Matcher::modI_proj_mask() {
2395 ShouldNotReachHere();
2396 return RegMask();
2397 }
2398
2399 // Register for DIVL projection of divmodL.
2400 RegMask Matcher::divL_proj_mask() {
2401 ShouldNotReachHere();
2402 return RegMask();
2403 }
2404
2405 // Register for MODL projection of divmodL.
2406 RegMask Matcher::modL_proj_mask() {
2407 ShouldNotReachHere();
2408 return RegMask();
2409 }
2410
2411 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2412 return RegMask();
2413 }
2414
2415 %}
2416
2417 //----------ENCODING BLOCK-----------------------------------------------------
2418 // This block specifies the encoding classes used by the compiler to output
2419 // byte streams. Encoding classes are parameterized macros used by
2420 // Machine Instruction Nodes in order to generate the bit encoding of the
2421 // instruction. Operands specify their base encoding interface with the
2422 // interface keyword. There are currently supported four interfaces,
2423 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2424 // operand to generate a function which returns its register number when
2425 // queried. CONST_INTER causes an operand to generate a function which
2426 // returns the value of the constant when queried. MEMORY_INTER causes an
2427 // operand to generate four functions which return the Base Register, the
2428 // Index Register, the Scale Value, and the Offset Value of the operand when
2429 // queried. COND_INTER causes an operand to generate six functions which
2430 // return the encoding code (ie - encoding bits for the instruction)
2431 // associated with each basic boolean condition for a conditional instruction.
2432 //
2433 // Instructions specify two basic values for encoding. Again, a function
2434 // is available to check if the constant displacement is an oop. They use the
2435 // ins_encode keyword to specify their encoding classes (which must be
2436 // a sequence of enc_class names, and their parameters, specified in
2437 // the encoding block), and they use the
2438 // opcode keyword to specify, in order, their primary, secondary, and
2439 // tertiary opcode. Only the opcode sections which a particular instruction
2440 // needs for encoding need to be specified.
2441 encode %{
2442 enc_class enc_unimplemented %{
2443 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2444 MacroAssembler _masm(&cbuf);
2445 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2446 %}
2447
2448 enc_class enc_untested %{
2449 #ifdef ASSERT
2450 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2451 MacroAssembler _masm(&cbuf);
2452 __ untested("Untested mach node encoding in AD file.");
2453 #else
2454 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2455 #endif
2456 %}
2457
2458 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2459 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2460 MacroAssembler _masm(&cbuf);
2461 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2462 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2463 %}
2464
2465 // Load acquire.
2466 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2467 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2468 MacroAssembler _masm(&cbuf);
2469 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2470 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2471 __ twi_0($dst$$Register);
2472 __ isync();
2473 %}
2474
2475 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2476 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2477
2478 MacroAssembler _masm(&cbuf);
2479 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2480 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2481 %}
2482
2483 // Load acquire.
2484 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2485 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2486
2487 MacroAssembler _masm(&cbuf);
2488 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2489 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2490 __ twi_0($dst$$Register);
2491 __ isync();
2492 %}
2493
2494 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2495 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2496
2497 MacroAssembler _masm(&cbuf);
2498 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2499 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2500 %}
2501
2502 // Load acquire.
2503 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2504 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2505
2506 MacroAssembler _masm(&cbuf);
2507 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2508 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2509 __ twi_0($dst$$Register);
2510 __ isync();
2511 %}
2512
2513 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2514 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2515 MacroAssembler _masm(&cbuf);
2516 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2517 // Operand 'ds' requires 4-alignment.
2518 assert((Idisp & 0x3) == 0, "unaligned offset");
2519 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2520 %}
2521
2522 // Load acquire.
2523 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2524 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2525 MacroAssembler _masm(&cbuf);
2526 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2527 // Operand 'ds' requires 4-alignment.
2528 assert((Idisp & 0x3) == 0, "unaligned offset");
2529 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2530 __ twi_0($dst$$Register);
2531 __ isync();
2532 %}
2533
2534 enc_class enc_lfd(RegF dst, memory mem) %{
2535 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2536 MacroAssembler _masm(&cbuf);
2537 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2538 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2539 %}
2540
2541 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2542 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2543
2544 MacroAssembler _masm(&cbuf);
2545 int toc_offset = 0;
2546
2547 if (!ra_->C->in_scratch_emit_size()) {
2548 address const_toc_addr;
2549 // Create a non-oop constant, no relocation needed.
2550 // If it is an IC, it has a virtual_call_Relocation.
2551 const_toc_addr = __ long_constant((jlong)$src$$constant);
2552
2553 // Get the constant's TOC offset.
2554 toc_offset = __ offset_to_method_toc(const_toc_addr);
2555
2556 // Keep the current instruction offset in mind.
2557 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2558 }
2559
2560 __ ld($dst$$Register, toc_offset, $toc$$Register);
2561 %}
2562
2563 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2564 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2565
2566 MacroAssembler _masm(&cbuf);
2567
2568 if (!ra_->C->in_scratch_emit_size()) {
2569 address const_toc_addr;
2570 // Create a non-oop constant, no relocation needed.
2571 // If it is an IC, it has a virtual_call_Relocation.
2572 const_toc_addr = __ long_constant((jlong)$src$$constant);
2573
2574 // Get the constant's TOC offset.
2575 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2576 // Store the toc offset of the constant.
2577 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2578
2579 // Also keep the current instruction offset in mind.
2580 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2581 }
2582
2583 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2584 %}
2585
2586 %} // encode
2587
2588 source %{
2589
2590 typedef struct {
2591 loadConL_hiNode *_large_hi;
2592 loadConL_loNode *_large_lo;
2593 loadConLNode *_small;
2594 MachNode *_last;
2595 } loadConLNodesTuple;
2596
2597 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2598 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2599 loadConLNodesTuple nodes;
2600
2601 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2602 if (large_constant_pool) {
2603 // Create new nodes.
2604 loadConL_hiNode *m1 = new loadConL_hiNode();
2605 loadConL_loNode *m2 = new loadConL_loNode();
2606
2607 // inputs for new nodes
2608 m1->add_req(NULL, toc);
2609 m2->add_req(NULL, m1);
2610
2611 // operands for new nodes
2612 m1->_opnds[0] = new iRegLdstOper(); // dst
2613 m1->_opnds[1] = immSrc; // src
2614 m1->_opnds[2] = new iRegPdstOper(); // toc
2615 m2->_opnds[0] = new iRegLdstOper(); // dst
2616 m2->_opnds[1] = immSrc; // src
2617 m2->_opnds[2] = new iRegLdstOper(); // base
2618
2619 // Initialize ins_attrib TOC fields.
2620 m1->_const_toc_offset = -1;
2621 m2->_const_toc_offset_hi_node = m1;
2622
2623 // Initialize ins_attrib instruction offset.
2624 m1->_cbuf_insts_offset = -1;
2625
2626 // register allocation for new nodes
2627 ra_->set_pair(m1->_idx, reg_second, reg_first);
2628 ra_->set_pair(m2->_idx, reg_second, reg_first);
2629
2630 // Create result.
2631 nodes._large_hi = m1;
2632 nodes._large_lo = m2;
2633 nodes._small = NULL;
2634 nodes._last = nodes._large_lo;
2635 assert(m2->bottom_type()->isa_long(), "must be long");
2636 } else {
2637 loadConLNode *m2 = new loadConLNode();
2638
2639 // inputs for new nodes
2640 m2->add_req(NULL, toc);
2641
2642 // operands for new nodes
2643 m2->_opnds[0] = new iRegLdstOper(); // dst
2644 m2->_opnds[1] = immSrc; // src
2645 m2->_opnds[2] = new iRegPdstOper(); // toc
2646
2647 // Initialize ins_attrib instruction offset.
2648 m2->_cbuf_insts_offset = -1;
2649
2650 // register allocation for new nodes
2651 ra_->set_pair(m2->_idx, reg_second, reg_first);
2652
2653 // Create result.
2654 nodes._large_hi = NULL;
2655 nodes._large_lo = NULL;
2656 nodes._small = m2;
2657 nodes._last = nodes._small;
2658 assert(m2->bottom_type()->isa_long(), "must be long");
2659 }
2660
2661 return nodes;
2662 }
2663
2664 %} // source
2665
2666 encode %{
2667 // Postalloc expand emitter for loading a long constant from the method's TOC.
2668 // Enc_class needed as consttanttablebase is not supported by postalloc
2669 // expand.
2670 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2671 // Create new nodes.
2672 loadConLNodesTuple loadConLNodes =
2673 loadConLNodesTuple_create(ra_, n_toc, op_src,
2674 ra_->get_reg_second(this), ra_->get_reg_first(this));
2675
2676 // Push new nodes.
2677 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2678 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2679
2680 // some asserts
2681 assert(nodes->length() >= 1, "must have created at least 1 node");
2682 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2683 %}
2684
2685 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2686 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2687
2688 MacroAssembler _masm(&cbuf);
2689 int toc_offset = 0;
2690
2691 if (!ra_->C->in_scratch_emit_size()) {
2692 intptr_t val = $src$$constant;
2693 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2694 address const_toc_addr;
2695 if (constant_reloc == relocInfo::oop_type) {
2696 // Create an oop constant and a corresponding relocation.
2697 AddressLiteral a = __ allocate_oop_address((jobject)val);
2698 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2699 __ relocate(a.rspec());
2700 } else if (constant_reloc == relocInfo::metadata_type) {
2701 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2702 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2703 __ relocate(a.rspec());
2704 } else {
2705 // Create a non-oop constant, no relocation needed.
2706 const_toc_addr = __ long_constant((jlong)$src$$constant);
2707 }
2708
2709 // Get the constant's TOC offset.
2710 toc_offset = __ offset_to_method_toc(const_toc_addr);
2711 }
2712
2713 __ ld($dst$$Register, toc_offset, $toc$$Register);
2714 %}
2715
2716 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2717 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2718
2719 MacroAssembler _masm(&cbuf);
2720 if (!ra_->C->in_scratch_emit_size()) {
2721 intptr_t val = $src$$constant;
2722 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2723 address const_toc_addr;
2724 if (constant_reloc == relocInfo::oop_type) {
2725 // Create an oop constant and a corresponding relocation.
2726 AddressLiteral a = __ allocate_oop_address((jobject)val);
2727 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2728 __ relocate(a.rspec());
2729 } else if (constant_reloc == relocInfo::metadata_type) {
2730 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2731 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2732 __ relocate(a.rspec());
2733 } else { // non-oop pointers, e.g. card mark base, heap top
2734 // Create a non-oop constant, no relocation needed.
2735 const_toc_addr = __ long_constant((jlong)$src$$constant);
2736 }
2737
2738 // Get the constant's TOC offset.
2739 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2740 // Store the toc offset of the constant.
2741 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2742 }
2743
2744 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2745 %}
2746
2747 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2748 // Enc_class needed as consttanttablebase is not supported by postalloc
2749 // expand.
2750 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2751 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2752 if (large_constant_pool) {
2753 // Create new nodes.
2754 loadConP_hiNode *m1 = new loadConP_hiNode();
2755 loadConP_loNode *m2 = new loadConP_loNode();
2756
2757 // inputs for new nodes
2758 m1->add_req(NULL, n_toc);
2759 m2->add_req(NULL, m1);
2760
2761 // operands for new nodes
2762 m1->_opnds[0] = new iRegPdstOper(); // dst
2763 m1->_opnds[1] = op_src; // src
2764 m1->_opnds[2] = new iRegPdstOper(); // toc
2765 m2->_opnds[0] = new iRegPdstOper(); // dst
2766 m2->_opnds[1] = op_src; // src
2767 m2->_opnds[2] = new iRegLdstOper(); // base
2768
2769 // Initialize ins_attrib TOC fields.
2770 m1->_const_toc_offset = -1;
2771 m2->_const_toc_offset_hi_node = m1;
2772
2773 // Register allocation for new nodes.
2774 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2775 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2776
2777 nodes->push(m1);
2778 nodes->push(m2);
2779 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2780 } else {
2781 loadConPNode *m2 = new loadConPNode();
2782
2783 // inputs for new nodes
2784 m2->add_req(NULL, n_toc);
2785
2786 // operands for new nodes
2787 m2->_opnds[0] = new iRegPdstOper(); // dst
2788 m2->_opnds[1] = op_src; // src
2789 m2->_opnds[2] = new iRegPdstOper(); // toc
2790
2791 // Register allocation for new nodes.
2792 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2793
2794 nodes->push(m2);
2795 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2796 }
2797 %}
2798
2799 // Enc_class needed as consttanttablebase is not supported by postalloc
2800 // expand.
2801 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2802 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2803
2804 MachNode *m2;
2805 if (large_constant_pool) {
2806 m2 = new loadConFCompNode();
2807 } else {
2808 m2 = new loadConFNode();
2809 }
2810 // inputs for new nodes
2811 m2->add_req(NULL, n_toc);
2812
2813 // operands for new nodes
2814 m2->_opnds[0] = op_dst;
2815 m2->_opnds[1] = op_src;
2816 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2817
2818 // register allocation for new nodes
2819 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2820 nodes->push(m2);
2821 %}
2822
2823 // Enc_class needed as consttanttablebase is not supported by postalloc
2824 // expand.
2825 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2826 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2827
2828 MachNode *m2;
2829 if (large_constant_pool) {
2830 m2 = new loadConDCompNode();
2831 } else {
2832 m2 = new loadConDNode();
2833 }
2834 // inputs for new nodes
2835 m2->add_req(NULL, n_toc);
2836
2837 // operands for new nodes
2838 m2->_opnds[0] = op_dst;
2839 m2->_opnds[1] = op_src;
2840 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2841
2842 // register allocation for new nodes
2843 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2844 nodes->push(m2);
2845 %}
2846
2847 enc_class enc_stw(iRegIsrc src, memory mem) %{
2848 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2849 MacroAssembler _masm(&cbuf);
2850 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2851 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2852 %}
2853
2854 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2855 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2856 MacroAssembler _masm(&cbuf);
2857 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2858 // Operand 'ds' requires 4-alignment.
2859 assert((Idisp & 0x3) == 0, "unaligned offset");
2860 __ std($src$$Register, Idisp, $mem$$base$$Register);
2861 %}
2862
2863 enc_class enc_stfs(RegF src, memory mem) %{
2864 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2865 MacroAssembler _masm(&cbuf);
2866 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2867 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2868 %}
2869
2870 enc_class enc_stfd(RegF src, memory mem) %{
2871 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2872 MacroAssembler _masm(&cbuf);
2873 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2874 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2875 %}
2876
2877 // Use release_store for card-marking to ensure that previous
2878 // oop-stores are visible before the card-mark change.
2879 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2880 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2881 // FIXME: Implement this as a cmove and use a fixed condition code
2882 // register which is written on every transition to compiled code,
2883 // e.g. in call-stub and when returning from runtime stubs.
2884 //
2885 // Proposed code sequence for the cmove implementation:
2886 //
2887 // Label skip_release;
2888 // __ beq(CCRfixed, skip_release);
2889 // __ release();
2890 // __ bind(skip_release);
2891 // __ stb(card mark);
2892
2893 MacroAssembler _masm(&cbuf);
2894 Label skip_storestore;
2895
2896 #if 0 // TODO: PPC port
2897 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2898 // StoreStore barrier conditionally.
2899 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2900 __ cmpwi(CCR0, R0, 0);
2901 __ beq_predict_taken(CCR0, skip_storestore);
2902 #endif
2903 __ li(R0, 0);
2904 __ membar(Assembler::StoreStore);
2905 #if 0 // TODO: PPC port
2906 __ bind(skip_storestore);
2907 #endif
2908
2909 // Do the store.
2910 if ($mem$$index == 0) {
2911 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2912 } else {
2913 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2914 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2915 }
2916 %}
2917
2918 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2919
2920 if (VM_Version::has_isel()) {
2921 // use isel instruction with Power 7
2922 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2923 encodeP_subNode *n_sub_base = new encodeP_subNode();
2924 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2925 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2926
2927 n_compare->add_req(n_region, n_src);
2928 n_compare->_opnds[0] = op_crx;
2929 n_compare->_opnds[1] = op_src;
2930 n_compare->_opnds[2] = new immL16Oper(0);
2931
2932 n_sub_base->add_req(n_region, n_src);
2933 n_sub_base->_opnds[0] = op_dst;
2934 n_sub_base->_opnds[1] = op_src;
2935 n_sub_base->_bottom_type = _bottom_type;
2936
2937 n_shift->add_req(n_region, n_sub_base);
2938 n_shift->_opnds[0] = op_dst;
2939 n_shift->_opnds[1] = op_dst;
2940 n_shift->_bottom_type = _bottom_type;
2941
2942 n_cond_set->add_req(n_region, n_compare, n_shift);
2943 n_cond_set->_opnds[0] = op_dst;
2944 n_cond_set->_opnds[1] = op_crx;
2945 n_cond_set->_opnds[2] = op_dst;
2946 n_cond_set->_bottom_type = _bottom_type;
2947
2948 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2949 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2950 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2951 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2952
2953 nodes->push(n_compare);
2954 nodes->push(n_sub_base);
2955 nodes->push(n_shift);
2956 nodes->push(n_cond_set);
2957
2958 } else {
2959 // before Power 7
2960 moveRegNode *n_move = new moveRegNode();
2961 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2962 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2963 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2964
2965 n_move->add_req(n_region, n_src);
2966 n_move->_opnds[0] = op_dst;
2967 n_move->_opnds[1] = op_src;
2968 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2969
2970 n_compare->add_req(n_region, n_src);
2971 n_compare->add_prec(n_move);
2972
2973 n_compare->_opnds[0] = op_crx;
2974 n_compare->_opnds[1] = op_src;
2975 n_compare->_opnds[2] = new immL16Oper(0);
2976
2977 n_sub_base->add_req(n_region, n_compare, n_src);
2978 n_sub_base->_opnds[0] = op_dst;
2979 n_sub_base->_opnds[1] = op_crx;
2980 n_sub_base->_opnds[2] = op_src;
2981 n_sub_base->_bottom_type = _bottom_type;
2982
2983 n_shift->add_req(n_region, n_sub_base);
2984 n_shift->_opnds[0] = op_dst;
2985 n_shift->_opnds[1] = op_dst;
2986 n_shift->_bottom_type = _bottom_type;
2987
2988 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2989 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2990 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2991 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2992
2993 nodes->push(n_move);
2994 nodes->push(n_compare);
2995 nodes->push(n_sub_base);
2996 nodes->push(n_shift);
2997 }
2998
2999 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3000 %}
3001
3002 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3003
3004 encodeP_subNode *n1 = new encodeP_subNode();
3005 n1->add_req(n_region, n_src);
3006 n1->_opnds[0] = op_dst;
3007 n1->_opnds[1] = op_src;
3008 n1->_bottom_type = _bottom_type;
3009
3010 encodeP_shiftNode *n2 = new encodeP_shiftNode();
3011 n2->add_req(n_region, n1);
3012 n2->_opnds[0] = op_dst;
3013 n2->_opnds[1] = op_dst;
3014 n2->_bottom_type = _bottom_type;
3015 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3016 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017
3018 nodes->push(n1);
3019 nodes->push(n2);
3020 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3021 %}
3022
3023 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3024 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
3025 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
3026
3027 n_compare->add_req(n_region, n_src);
3028 n_compare->_opnds[0] = op_crx;
3029 n_compare->_opnds[1] = op_src;
3030 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
3031
3032 n_shift->add_req(n_region, n_src);
3033 n_shift->_opnds[0] = op_dst;
3034 n_shift->_opnds[1] = op_src;
3035 n_shift->_bottom_type = _bottom_type;
3036
3037 if (VM_Version::has_isel()) {
3038 // use isel instruction with Power 7
3039
3040 decodeN_addNode *n_add_base = new decodeN_addNode();
3041 n_add_base->add_req(n_region, n_shift);
3042 n_add_base->_opnds[0] = op_dst;
3043 n_add_base->_opnds[1] = op_dst;
3044 n_add_base->_bottom_type = _bottom_type;
3045
3046 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
3047 n_cond_set->add_req(n_region, n_compare, n_add_base);
3048 n_cond_set->_opnds[0] = op_dst;
3049 n_cond_set->_opnds[1] = op_crx;
3050 n_cond_set->_opnds[2] = op_dst;
3051 n_cond_set->_bottom_type = _bottom_type;
3052
3053 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3054 ra_->set_oop(n_cond_set, true);
3055
3056 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3057 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3058 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3059 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3060
3061 nodes->push(n_compare);
3062 nodes->push(n_shift);
3063 nodes->push(n_add_base);
3064 nodes->push(n_cond_set);
3065
3066 } else {
3067 // before Power 7
3068 cond_add_baseNode *n_add_base = new cond_add_baseNode();
3069
3070 n_add_base->add_req(n_region, n_compare, n_shift);
3071 n_add_base->_opnds[0] = op_dst;
3072 n_add_base->_opnds[1] = op_crx;
3073 n_add_base->_opnds[2] = op_dst;
3074 n_add_base->_bottom_type = _bottom_type;
3075
3076 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3077 ra_->set_oop(n_add_base, true);
3078
3079 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3080 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3081 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3082
3083 nodes->push(n_compare);
3084 nodes->push(n_shift);
3085 nodes->push(n_add_base);
3086 }
3087 %}
3088
3089 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3090 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3091 n1->add_req(n_region, n_src);
3092 n1->_opnds[0] = op_dst;
3093 n1->_opnds[1] = op_src;
3094 n1->_bottom_type = _bottom_type;
3095
3096 decodeN_addNode *n2 = new decodeN_addNode();
3097 n2->add_req(n_region, n1);
3098 n2->_opnds[0] = op_dst;
3099 n2->_opnds[1] = op_dst;
3100 n2->_bottom_type = _bottom_type;
3101 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3102 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3103
3104 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3105 ra_->set_oop(n2, true);
3106
3107 nodes->push(n1);
3108 nodes->push(n2);
3109 %}
3110
3111 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3112 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3113
3114 MacroAssembler _masm(&cbuf);
3115 int cc = $cmp$$cmpcode;
3116 int flags_reg = $crx$$reg;
3117 Label done;
3118 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3119 // Branch if not (cmp crx).
3120 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3121 __ mr($dst$$Register, $src$$Register);
3122 // TODO PPC port __ endgroup_if_needed(_size == 12);
3123 __ bind(done);
3124 %}
3125
3126 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3127 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3128
3129 MacroAssembler _masm(&cbuf);
3130 Label done;
3131 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3132 // Branch if not (cmp crx).
3133 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3134 __ li($dst$$Register, $src$$constant);
3135 // TODO PPC port __ endgroup_if_needed(_size == 12);
3136 __ bind(done);
3137 %}
3138
3139 // New atomics.
3140 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3141 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3142
3143 MacroAssembler _masm(&cbuf);
3144 Register Rtmp = R0;
3145 Register Rres = $res$$Register;
3146 Register Rsrc = $src$$Register;
3147 Register Rptr = $mem_ptr$$Register;
3148 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3149 Register Rold = RegCollision ? Rtmp : Rres;
3150
3151 Label Lretry;
3152 __ bind(Lretry);
3153 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3154 __ add(Rtmp, Rsrc, Rold);
3155 __ stwcx_(Rtmp, Rptr);
3156 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3157 __ bne_predict_not_taken(CCR0, Lretry);
3158 } else {
3159 __ bne( CCR0, Lretry);
3160 }
3161 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3162 __ fence();
3163 %}
3164
3165 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3166 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3167
3168 MacroAssembler _masm(&cbuf);
3169 Register Rtmp = R0;
3170 Register Rres = $res$$Register;
3171 Register Rsrc = $src$$Register;
3172 Register Rptr = $mem_ptr$$Register;
3173 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3174 Register Rold = RegCollision ? Rtmp : Rres;
3175
3176 Label Lretry;
3177 __ bind(Lretry);
3178 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3179 __ add(Rtmp, Rsrc, Rold);
3180 __ stdcx_(Rtmp, Rptr);
3181 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3182 __ bne_predict_not_taken(CCR0, Lretry);
3183 } else {
3184 __ bne( CCR0, Lretry);
3185 }
3186 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3187 __ fence();
3188 %}
3189
3190 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3191 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3192
3193 MacroAssembler _masm(&cbuf);
3194 Register Rtmp = R0;
3195 Register Rres = $res$$Register;
3196 Register Rsrc = $src$$Register;
3197 Register Rptr = $mem_ptr$$Register;
3198 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3199 Register Rold = RegCollision ? Rtmp : Rres;
3200
3201 Label Lretry;
3202 __ bind(Lretry);
3203 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3204 __ stwcx_(Rsrc, Rptr);
3205 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3206 __ bne_predict_not_taken(CCR0, Lretry);
3207 } else {
3208 __ bne( CCR0, Lretry);
3209 }
3210 if (RegCollision) __ mr(Rres, Rtmp);
3211 __ fence();
3212 %}
3213
3214 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3215 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3216
3217 MacroAssembler _masm(&cbuf);
3218 Register Rtmp = R0;
3219 Register Rres = $res$$Register;
3220 Register Rsrc = $src$$Register;
3221 Register Rptr = $mem_ptr$$Register;
3222 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3223 Register Rold = RegCollision ? Rtmp : Rres;
3224
3225 Label Lretry;
3226 __ bind(Lretry);
3227 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3228 __ stdcx_(Rsrc, Rptr);
3229 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3230 __ bne_predict_not_taken(CCR0, Lretry);
3231 } else {
3232 __ bne( CCR0, Lretry);
3233 }
3234 if (RegCollision) __ mr(Rres, Rtmp);
3235 __ fence();
3236 %}
3237
3238 // This enc_class is needed so that scheduler gets proper
3239 // input mapping for latency computation.
3240 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3241 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3242 MacroAssembler _masm(&cbuf);
3243 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3244 %}
3245
3246 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3247 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3248
3249 MacroAssembler _masm(&cbuf);
3250
3251 Label done;
3252 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3253 __ li($dst$$Register, $zero$$constant);
3254 __ beq($crx$$CondRegister, done);
3255 __ li($dst$$Register, $notzero$$constant);
3256 __ bind(done);
3257 %}
3258
3259 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3260 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3261
3262 MacroAssembler _masm(&cbuf);
3263
3264 Label done;
3265 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3266 __ li($dst$$Register, $zero$$constant);
3267 __ beq($crx$$CondRegister, done);
3268 __ li($dst$$Register, $notzero$$constant);
3269 __ bind(done);
3270 %}
3271
3272 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3273 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3274
3275 MacroAssembler _masm(&cbuf);
3276 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3277 Label done;
3278 __ bso($crx$$CondRegister, done);
3279 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3280 // TODO PPC port __ endgroup_if_needed(_size == 12);
3281 __ bind(done);
3282 %}
3283
3284 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3285 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3286
3287 MacroAssembler _masm(&cbuf);
3288 Label d; // dummy
3289 __ bind(d);
3290 Label* p = ($lbl$$label);
3291 // `p' is `NULL' when this encoding class is used only to
3292 // determine the size of the encoded instruction.
3293 Label& l = (NULL == p)? d : *(p);
3294 int cc = $cmp$$cmpcode;
3295 int flags_reg = $crx$$reg;
3296 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3297 int bhint = Assembler::bhintNoHint;
3298
3299 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3300 if (_prob <= PROB_NEVER) {
3301 bhint = Assembler::bhintIsNotTaken;
3302 } else if (_prob >= PROB_ALWAYS) {
3303 bhint = Assembler::bhintIsTaken;
3304 }
3305 }
3306
3307 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3308 cc_to_biint(cc, flags_reg),
3309 l);
3310 %}
3311
3312 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3313 // The scheduler doesn't know about branch shortening, so we set the opcode
3314 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3315 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3316
3317 MacroAssembler _masm(&cbuf);
3318 Label d; // dummy
3319 __ bind(d);
3320 Label* p = ($lbl$$label);
3321 // `p' is `NULL' when this encoding class is used only to
3322 // determine the size of the encoded instruction.
3323 Label& l = (NULL == p)? d : *(p);
3324 int cc = $cmp$$cmpcode;
3325 int flags_reg = $crx$$reg;
3326 int bhint = Assembler::bhintNoHint;
3327
3328 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3329 if (_prob <= PROB_NEVER) {
3330 bhint = Assembler::bhintIsNotTaken;
3331 } else if (_prob >= PROB_ALWAYS) {
3332 bhint = Assembler::bhintIsTaken;
3333 }
3334 }
3335
3336 // Tell the conditional far branch to optimize itself when being relocated.
3337 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3338 cc_to_biint(cc, flags_reg),
3339 l,
3340 MacroAssembler::bc_far_optimize_on_relocate);
3341 %}
3342
3343 // Branch used with Power6 scheduling (can be shortened without changing the node).
3344 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3345 // The scheduler doesn't know about branch shortening, so we set the opcode
3346 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3347 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3348
3349 MacroAssembler _masm(&cbuf);
3350 Label d; // dummy
3351 __ bind(d);
3352 Label* p = ($lbl$$label);
3353 // `p' is `NULL' when this encoding class is used only to
3354 // determine the size of the encoded instruction.
3355 Label& l = (NULL == p)? d : *(p);
3356 int cc = $cmp$$cmpcode;
3357 int flags_reg = $crx$$reg;
3358 int bhint = Assembler::bhintNoHint;
3359
3360 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3361 if (_prob <= PROB_NEVER) {
3362 bhint = Assembler::bhintIsNotTaken;
3363 } else if (_prob >= PROB_ALWAYS) {
3364 bhint = Assembler::bhintIsTaken;
3365 }
3366 }
3367
3368 #if 0 // TODO: PPC port
3369 if (_size == 8) {
3370 // Tell the conditional far branch to optimize itself when being relocated.
3371 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3372 cc_to_biint(cc, flags_reg),
3373 l,
3374 MacroAssembler::bc_far_optimize_on_relocate);
3375 } else {
3376 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3377 cc_to_biint(cc, flags_reg),
3378 l);
3379 }
3380 #endif
3381 Unimplemented();
3382 %}
3383
3384 // Postalloc expand emitter for loading a replicatef float constant from
3385 // the method's TOC.
3386 // Enc_class needed as consttanttablebase is not supported by postalloc
3387 // expand.
3388 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3389 // Create new nodes.
3390
3391 // Make an operand with the bit pattern to load as float.
3392 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3393
3394 loadConLNodesTuple loadConLNodes =
3395 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3396 ra_->get_reg_second(this), ra_->get_reg_first(this));
3397
3398 // Push new nodes.
3399 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3400 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3401
3402 assert(nodes->length() >= 1, "must have created at least 1 node");
3403 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3404 %}
3405
3406 // This enc_class is needed so that scheduler gets proper
3407 // input mapping for latency computation.
3408 enc_class enc_poll(immI dst, iRegLdst poll) %{
3409 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3410 // Fake operand dst needed for PPC scheduler.
3411 assert($dst$$constant == 0x0, "dst must be 0x0");
3412
3413 MacroAssembler _masm(&cbuf);
3414 // Mark the code position where the load from the safepoint
3415 // polling page was emitted as relocInfo::poll_type.
3416 __ relocate(relocInfo::poll_type);
3417 __ load_from_polling_page($poll$$Register);
3418 %}
3419
3420 // A Java static call or a runtime call.
3421 //
3422 // Branch-and-link relative to a trampoline.
3423 // The trampoline loads the target address and does a long branch to there.
3424 // In case we call java, the trampoline branches to a interpreter_stub
3425 // which loads the inline cache and the real call target from the constant pool.
3426 //
3427 // This basically looks like this:
3428 //
3429 // >>>> consts -+ -+
3430 // | |- offset1
3431 // [call target1] | <-+
3432 // [IC cache] |- offset2
3433 // [call target2] <--+
3434 //
3435 // <<<< consts
3436 // >>>> insts
3437 //
3438 // bl offset16 -+ -+ ??? // How many bits available?
3439 // | |
3440 // <<<< insts | |
3441 // >>>> stubs | |
3442 // | |- trampoline_stub_Reloc
3443 // trampoline stub: | <-+
3444 // r2 = toc |
3445 // r2 = [r2 + offset1] | // Load call target1 from const section
3446 // mtctr r2 |
3447 // bctr |- static_stub_Reloc
3448 // comp_to_interp_stub: <---+
3449 // r1 = toc
3450 // ICreg = [r1 + IC_offset] // Load IC from const section
3451 // r1 = [r1 + offset2] // Load call target2 from const section
3452 // mtctr r1
3453 // bctr
3454 //
3455 // <<<< stubs
3456 //
3457 // The call instruction in the code either
3458 // - Branches directly to a compiled method if the offset is encodable in instruction.
3459 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3460 // - Branches to the compiled_to_interp stub if the target is interpreted.
3461 //
3462 // Further there are three relocations from the loads to the constants in
3463 // the constant section.
3464 //
3465 // Usage of r1 and r2 in the stubs allows to distinguish them.
3466 enc_class enc_java_static_call(method meth) %{
3467 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3468
3469 MacroAssembler _masm(&cbuf);
3470 address entry_point = (address)$meth$$method;
3471
3472 if (!_method) {
3473 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3474 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3475 } else {
3476 // Remember the offset not the address.
3477 const int start_offset = __ offset();
3478 // The trampoline stub.
3479 if (!Compile::current()->in_scratch_emit_size()) {
3480 // No entry point given, use the current pc.
3481 // Make sure branch fits into
3482 if (entry_point == 0) entry_point = __ pc();
3483
3484 // Put the entry point as a constant into the constant pool.
3485 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3486 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3487
3488 // Emit the trampoline stub which will be related to the branch-and-link below.
3489 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3490 if (Compile::current()->env()->failing()) { return; } // Code cache may be full.
3491 __ relocate(_optimized_virtual ?
3492 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3493 }
3494
3495 // The real call.
3496 // Note: At this point we do not have the address of the trampoline
3497 // stub, and the entry point might be too far away for bl, so __ pc()
3498 // serves as dummy and the bl will be patched later.
3499 cbuf.set_insts_mark();
3500 __ bl(__ pc()); // Emits a relocation.
3501
3502 // The stub for call to interpreter.
3503 CompiledStaticCall::emit_to_interp_stub(cbuf);
3504 }
3505 %}
3506
3507 // Emit a method handle call.
3508 //
3509 // Method handle calls from compiled to compiled are going thru a
3510 // c2i -> i2c adapter, extending the frame for their arguments. The
3511 // caller however, returns directly to the compiled callee, that has
3512 // to cope with the extended frame. We restore the original frame by
3513 // loading the callers sp and adding the calculated framesize.
3514 enc_class enc_java_handle_call(method meth) %{
3515 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3516
3517 MacroAssembler _masm(&cbuf);
3518 address entry_point = (address)$meth$$method;
3519
3520 // Remember the offset not the address.
3521 const int start_offset = __ offset();
3522 // The trampoline stub.
3523 if (!ra_->C->in_scratch_emit_size()) {
3524 // No entry point given, use the current pc.
3525 // Make sure branch fits into
3526 if (entry_point == 0) entry_point = __ pc();
3527
3528 // Put the entry point as a constant into the constant pool.
3529 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3530 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3531
3532 // Emit the trampoline stub which will be related to the branch-and-link below.
3533 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3534 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3535 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3536 __ relocate(relocInfo::opt_virtual_call_type);
3537 }
3538
3539 // The real call.
3540 // Note: At this point we do not have the address of the trampoline
3541 // stub, and the entry point might be too far away for bl, so __ pc()
3542 // serves as dummy and the bl will be patched later.
3543 cbuf.set_insts_mark();
3544 __ bl(__ pc()); // Emits a relocation.
3545
3546 assert(_method, "execute next statement conditionally");
3547 // The stub for call to interpreter.
3548 CompiledStaticCall::emit_to_interp_stub(cbuf);
3549
3550 // Restore original sp.
3551 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3552 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3553 unsigned int bytes = (unsigned int)framesize;
3554 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3555 if (Assembler::is_simm(-offset, 16)) {
3556 __ addi(R1_SP, R11_scratch1, -offset);
3557 } else {
3558 __ load_const_optimized(R12_scratch2, -offset);
3559 __ add(R1_SP, R11_scratch1, R12_scratch2);
3560 }
3561 #ifdef ASSERT
3562 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3563 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3564 __ asm_assert_eq("backlink changed", 0x8000);
3565 #endif
3566 // If fails should store backlink before unextending.
3567
3568 if (ra_->C->env()->failing()) {
3569 return;
3570 }
3571 %}
3572
3573 // Second node of expanded dynamic call - the call.
3574 enc_class enc_java_dynamic_call_sched(method meth) %{
3575 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3576
3577 MacroAssembler _masm(&cbuf);
3578
3579 if (!ra_->C->in_scratch_emit_size()) {
3580 // Create a call trampoline stub for the given method.
3581 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3582 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3583 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3584 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3585 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3586
3587 // Build relocation at call site with ic position as data.
3588 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3589 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3590 "must have one, but can't have both");
3591 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3592 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3593 "must contain instruction offset");
3594 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3595 ? _load_ic_hi_node->_cbuf_insts_offset
3596 : _load_ic_node->_cbuf_insts_offset;
3597 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3598 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3599 "should be load from TOC");
3600
3601 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3602 }
3603
3604 // At this point I do not have the address of the trampoline stub,
3605 // and the entry point might be too far away for bl. Pc() serves
3606 // as dummy and bl will be patched later.
3607 __ bl((address) __ pc());
3608 %}
3609
3610 // postalloc expand emitter for virtual calls.
3611 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3612
3613 // Create the nodes for loading the IC from the TOC.
3614 loadConLNodesTuple loadConLNodes_IC =
3615 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3616 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3617
3618 // Create the call node.
3619 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3620 call->_method_handle_invoke = _method_handle_invoke;
3621 call->_vtable_index = _vtable_index;
3622 call->_method = _method;
3623 call->_bci = _bci;
3624 call->_optimized_virtual = _optimized_virtual;
3625 call->_tf = _tf;
3626 call->_entry_point = _entry_point;
3627 call->_cnt = _cnt;
3628 call->_argsize = _argsize;
3629 call->_oop_map = _oop_map;
3630 call->_jvms = _jvms;
3631 call->_jvmadj = _jvmadj;
3632 call->_in_rms = _in_rms;
3633 call->_nesting = _nesting;
3634
3635 // New call needs all inputs of old call.
3636 // Req...
3637 for (uint i = 0; i < req(); ++i) {
3638 // The expanded node does not need toc any more.
3639 // Add the inline cache constant here instead. This expresses the
3640 // register of the inline cache must be live at the call.
3641 // Else we would have to adapt JVMState by -1.
3642 if (i == mach_constant_base_node_input()) {
3643 call->add_req(loadConLNodes_IC._last);
3644 } else {
3645 call->add_req(in(i));
3646 }
3647 }
3648 // ...as well as prec
3649 for (uint i = req(); i < len(); ++i) {
3650 call->add_prec(in(i));
3651 }
3652
3653 // Remember nodes loading the inline cache into r19.
3654 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3655 call->_load_ic_node = loadConLNodes_IC._small;
3656
3657 // Operands for new nodes.
3658 call->_opnds[0] = _opnds[0];
3659 call->_opnds[1] = _opnds[1];
3660
3661 // Only the inline cache is associated with a register.
3662 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3663
3664 // Push new nodes.
3665 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3666 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3667 nodes->push(call);
3668 %}
3669
3670 // Compound version of call dynamic
3671 // Toc is only passed so that it can be used in ins_encode statement.
3672 // In the code we have to use $constanttablebase.
3673 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3674 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3675 MacroAssembler _masm(&cbuf);
3676 int start_offset = __ offset();
3677
3678 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3679 #if 0
3680 int vtable_index = this->_vtable_index;
3681 if (_vtable_index < 0) {
3682 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3683 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3684 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3685
3686 // Virtual call relocation will point to ic load.
3687 address virtual_call_meta_addr = __ pc();
3688 // Load a clear inline cache.
3689 AddressLiteral empty_ic((address) Universe::non_oop_word());
3690 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3691 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3692 // to determine who we intended to call.
3693 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3694 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3695 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3696 "Fix constant in ret_addr_offset()");
3697 } else {
3698 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3699 // Go thru the vtable. Get receiver klass. Receiver already
3700 // checked for non-null. If we'll go thru a C2I adapter, the
3701 // interpreter expects method in R19_method.
3702
3703 __ load_klass(R11_scratch1, R3);
3704
3705 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3706 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3707 __ li(R19_method, v_off);
3708 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3709 // NOTE: for vtable dispatches, the vtable entry will never be
3710 // null. However it may very well end up in handle_wrong_method
3711 // if the method is abstract for the particular class.
3712 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3713 // Call target. Either compiled code or C2I adapter.
3714 __ mtctr(R11_scratch1);
3715 __ bctrl();
3716 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3717 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3718 }
3719 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3720 "Fix constant in ret_addr_offset()");
3721 }
3722 #endif
3723 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3724 %}
3725
3726 // a runtime call
3727 enc_class enc_java_to_runtime_call (method meth) %{
3728 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3729
3730 MacroAssembler _masm(&cbuf);
3731 const address start_pc = __ pc();
3732
3733 #if defined(ABI_ELFv2)
3734 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3735 __ call_c(entry, relocInfo::runtime_call_type);
3736 #else
3737 // The function we're going to call.
3738 FunctionDescriptor fdtemp;
3739 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3740
3741 Register Rtoc = R12_scratch2;
3742 // Calculate the method's TOC.
3743 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3744 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3745 // pool entries; call_c_using_toc will optimize the call.
3746 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3747 #endif
3748
3749 // Check the ret_addr_offset.
3750 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3751 "Fix constant in ret_addr_offset()");
3752 %}
3753
3754 // Move to ctr for leaf call.
3755 // This enc_class is needed so that scheduler gets proper
3756 // input mapping for latency computation.
3757 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3758 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3759 MacroAssembler _masm(&cbuf);
3760 __ mtctr($src$$Register);
3761 %}
3762
3763 // Postalloc expand emitter for runtime leaf calls.
3764 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3765 loadConLNodesTuple loadConLNodes_Entry;
3766 #if defined(ABI_ELFv2)
3767 jlong entry_address = (jlong) this->entry_point();
3768 assert(entry_address, "need address here");
3769 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3770 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3771 #else
3772 // Get the struct that describes the function we are about to call.
3773 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3774 assert(fd, "need fd here");
3775 jlong entry_address = (jlong) fd->entry();
3776 // new nodes
3777 loadConLNodesTuple loadConLNodes_Env;
3778 loadConLNodesTuple loadConLNodes_Toc;
3779
3780 // Create nodes and operands for loading the entry point.
3781 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3782 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3783
3784
3785 // Create nodes and operands for loading the env pointer.
3786 if (fd->env() != NULL) {
3787 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3788 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3789 } else {
3790 loadConLNodes_Env._large_hi = NULL;
3791 loadConLNodes_Env._large_lo = NULL;
3792 loadConLNodes_Env._small = NULL;
3793 loadConLNodes_Env._last = new loadConL16Node();
3794 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3795 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3796 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3797 }
3798
3799 // Create nodes and operands for loading the Toc point.
3800 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3801 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3802 #endif // ABI_ELFv2
3803 // mtctr node
3804 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3805
3806 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3807 mtctr->add_req(0, loadConLNodes_Entry._last);
3808
3809 mtctr->_opnds[0] = new iRegLdstOper();
3810 mtctr->_opnds[1] = new iRegLdstOper();
3811
3812 // call node
3813 MachCallLeafNode *call = new CallLeafDirectNode();
3814
3815 call->_opnds[0] = _opnds[0];
3816 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3817
3818 // Make the new call node look like the old one.
3819 call->_name = _name;
3820 call->_tf = _tf;
3821 call->_entry_point = _entry_point;
3822 call->_cnt = _cnt;
3823 call->_argsize = _argsize;
3824 call->_oop_map = _oop_map;
3825 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3826 call->_jvms = NULL;
3827 call->_jvmadj = _jvmadj;
3828 call->_in_rms = _in_rms;
3829 call->_nesting = _nesting;
3830
3831
3832 // New call needs all inputs of old call.
3833 // Req...
3834 for (uint i = 0; i < req(); ++i) {
3835 if (i != mach_constant_base_node_input()) {
3836 call->add_req(in(i));
3837 }
3838 }
3839
3840 // These must be reqired edges, as the registers are live up to
3841 // the call. Else the constants are handled as kills.
3842 call->add_req(mtctr);
3843 #if !defined(ABI_ELFv2)
3844 call->add_req(loadConLNodes_Env._last);
3845 call->add_req(loadConLNodes_Toc._last);
3846 #endif
3847
3848 // ...as well as prec
3849 for (uint i = req(); i < len(); ++i) {
3850 call->add_prec(in(i));
3851 }
3852
3853 // registers
3854 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3855
3856 // Insert the new nodes.
3857 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3858 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3859 #if !defined(ABI_ELFv2)
3860 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3861 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3862 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3863 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3864 #endif
3865 nodes->push(mtctr);
3866 nodes->push(call);
3867 %}
3868 %}
3869
3870 //----------FRAME--------------------------------------------------------------
3871 // Definition of frame structure and management information.
3872
3873 frame %{
3874 // What direction does stack grow in (assumed to be same for native & Java).
3875 stack_direction(TOWARDS_LOW);
3876
3877 // These two registers define part of the calling convention between
3878 // compiled code and the interpreter.
3879
3880 // Inline Cache Register or method for I2C.
3881 inline_cache_reg(R19); // R19_method
3882
3883 // Method Oop Register when calling interpreter.
3884 interpreter_method_oop_reg(R19); // R19_method
3885
3886 // Optional: name the operand used by cisc-spilling to access
3887 // [stack_pointer + offset].
3888 cisc_spilling_operand_name(indOffset);
3889
3890 // Number of stack slots consumed by a Monitor enter.
3891 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3892
3893 // Compiled code's Frame Pointer.
3894 frame_pointer(R1); // R1_SP
3895
3896 // Interpreter stores its frame pointer in a register which is
3897 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3898 // interpreted java to compiled java.
3899 //
3900 // R14_state holds pointer to caller's cInterpreter.
3901 interpreter_frame_pointer(R14); // R14_state
3902
3903 stack_alignment(frame::alignment_in_bytes);
3904
3905 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3906
3907 // Number of outgoing stack slots killed above the
3908 // out_preserve_stack_slots for calls to C. Supports the var-args
3909 // backing area for register parms.
3910 //
3911 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3912
3913 // The after-PROLOG location of the return address. Location of
3914 // return address specifies a type (REG or STACK) and a number
3915 // representing the register number (i.e. - use a register name) or
3916 // stack slot.
3917 //
3918 // A: Link register is stored in stack slot ...
3919 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3920 // J: Therefore, we make sure that the link register is also in R11_scratch1
3921 // at the end of the prolog.
3922 // B: We use R20, now.
3923 //return_addr(REG R20);
3924
3925 // G: After reading the comments made by all the luminaries on their
3926 // failure to tell the compiler where the return address really is,
3927 // I hardly dare to try myself. However, I'm convinced it's in slot
3928 // 4 what apparently works and saves us some spills.
3929 return_addr(STACK 4);
3930
3931 // This is the body of the function
3932 //
3933 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3934 // uint length, // length of array
3935 // bool is_outgoing)
3936 //
3937 // The `sig' array is to be updated. sig[j] represents the location
3938 // of the j-th argument, either a register or a stack slot.
3939
3940 // Comment taken from i486.ad:
3941 // Body of function which returns an integer array locating
3942 // arguments either in registers or in stack slots. Passed an array
3943 // of ideal registers called "sig" and a "length" count. Stack-slot
3944 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3945 // arguments for a CALLEE. Incoming stack arguments are
3946 // automatically biased by the preserve_stack_slots field above.
3947 calling_convention %{
3948 // No difference between ingoing/outgoing. Just pass false.
3949 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3950 %}
3951
3952 // Comment taken from i486.ad:
3953 // Body of function which returns an integer array locating
3954 // arguments either in registers or in stack slots. Passed an array
3955 // of ideal registers called "sig" and a "length" count. Stack-slot
3956 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3957 // arguments for a CALLEE. Incoming stack arguments are
3958 // automatically biased by the preserve_stack_slots field above.
3959 c_calling_convention %{
3960 // This is obviously always outgoing.
3961 // C argument in register AND stack slot.
3962 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3963 %}
3964
3965 // Location of native (C/C++) and interpreter return values. This
3966 // is specified to be the same as Java. In the 32-bit VM, long
3967 // values are actually returned from native calls in O0:O1 and
3968 // returned to the interpreter in I0:I1. The copying to and from
3969 // the register pairs is done by the appropriate call and epilog
3970 // opcodes. This simplifies the register allocator.
3971 c_return_value %{
3972 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3973 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3974 "only return normal values");
3975 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3976 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3977 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3978 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3979 %}
3980
3981 // Location of compiled Java return values. Same as C
3982 return_value %{
3983 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3984 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3985 "only return normal values");
3986 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3987 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3988 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3989 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3990 %}
3991 %}
3992
3993
3994 //----------ATTRIBUTES---------------------------------------------------------
3995
3996 //----------Operand Attributes-------------------------------------------------
3997 op_attrib op_cost(1); // Required cost attribute.
3998
3999 //----------Instruction Attributes---------------------------------------------
4000
4001 // Cost attribute. required.
4002 ins_attrib ins_cost(DEFAULT_COST);
4003
4004 // Is this instruction a non-matching short branch variant of some
4005 // long branch? Not required.
4006 ins_attrib ins_short_branch(0);
4007
4008 ins_attrib ins_is_TrapBasedCheckNode(true);
4009
4010 // Number of constants.
4011 // This instruction uses the given number of constants
4012 // (optional attribute).
4013 // This is needed to determine in time whether the constant pool will
4014 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4015 // is determined. It's also used to compute the constant pool size
4016 // in Output().
4017 ins_attrib ins_num_consts(0);
4018
4019 // Required alignment attribute (must be a power of 2) specifies the
4020 // alignment that some part of the instruction (not necessarily the
4021 // start) requires. If > 1, a compute_padding() function must be
4022 // provided for the instruction.
4023 ins_attrib ins_alignment(1);
4024
4025 // Enforce/prohibit rematerializations.
4026 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4027 // then rematerialization of that instruction is prohibited and the
4028 // instruction's value will be spilled if necessary.
4029 // Causes that MachNode::rematerialize() returns false.
4030 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4031 // then rematerialization should be enforced and a copy of the instruction
4032 // should be inserted if possible; rematerialization is not guaranteed.
4033 // Note: this may result in rematerializations in front of every use.
4034 // Causes that MachNode::rematerialize() can return true.
4035 // (optional attribute)
4036 ins_attrib ins_cannot_rematerialize(false);
4037 ins_attrib ins_should_rematerialize(false);
4038
4039 // Instruction has variable size depending on alignment.
4040 ins_attrib ins_variable_size_depending_on_alignment(false);
4041
4042 // Instruction is a nop.
4043 ins_attrib ins_is_nop(false);
4044
4045 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4046 ins_attrib ins_use_mach_if_fast_lock_node(false);
4047
4048 // Field for the toc offset of a constant.
4049 //
4050 // This is needed if the toc offset is not encodable as an immediate in
4051 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4052 // added to the toc, and from this a load with immediate is performed.
4053 // With postalloc expand, we get two nodes that require the same offset
4054 // but which don't know about each other. The offset is only known
4055 // when the constant is added to the constant pool during emitting.
4056 // It is generated in the 'hi'-node adding the upper bits, and saved
4057 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4058 // the offset from there when it gets encoded.
4059 ins_attrib ins_field_const_toc_offset(0);
4060 ins_attrib ins_field_const_toc_offset_hi_node(0);
4061
4062 // A field that can hold the instructions offset in the code buffer.
4063 // Set in the nodes emitter.
4064 ins_attrib ins_field_cbuf_insts_offset(-1);
4065
4066 // Fields for referencing a call's load-IC-node.
4067 // If the toc offset can not be encoded as an immediate in a load, we
4068 // use two nodes.
4069 ins_attrib ins_field_load_ic_hi_node(0);
4070 ins_attrib ins_field_load_ic_node(0);
4071
4072 //----------OPERANDS-----------------------------------------------------------
4073 // Operand definitions must precede instruction definitions for correct
4074 // parsing in the ADLC because operands constitute user defined types
4075 // which are used in instruction definitions.
4076 //
4077 // Formats are generated automatically for constants and base registers.
4078
4079 //----------Simple Operands----------------------------------------------------
4080 // Immediate Operands
4081
4082 // Integer Immediate: 32-bit
4083 operand immI() %{
4084 match(ConI);
4085 op_cost(40);
4086 format %{ %}
4087 interface(CONST_INTER);
4088 %}
4089
4090 operand immI8() %{
4091 predicate(Assembler::is_simm(n->get_int(), 8));
4092 op_cost(0);
4093 match(ConI);
4094 format %{ %}
4095 interface(CONST_INTER);
4096 %}
4097
4098 // Integer Immediate: 16-bit
4099 operand immI16() %{
4100 predicate(Assembler::is_simm(n->get_int(), 16));
4101 op_cost(0);
4102 match(ConI);
4103 format %{ %}
4104 interface(CONST_INTER);
4105 %}
4106
4107 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4108 operand immIhi16() %{
4109 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4110 match(ConI);
4111 op_cost(0);
4112 format %{ %}
4113 interface(CONST_INTER);
4114 %}
4115
4116 operand immInegpow2() %{
4117 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4118 match(ConI);
4119 op_cost(0);
4120 format %{ %}
4121 interface(CONST_INTER);
4122 %}
4123
4124 operand immIpow2minus1() %{
4125 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4126 match(ConI);
4127 op_cost(0);
4128 format %{ %}
4129 interface(CONST_INTER);
4130 %}
4131
4132 operand immIpowerOf2() %{
4133 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4134 match(ConI);
4135 op_cost(0);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4139
4140 // Unsigned Integer Immediate: the values 0-31
4141 operand uimmI5() %{
4142 predicate(Assembler::is_uimm(n->get_int(), 5));
4143 match(ConI);
4144 op_cost(0);
4145 format %{ %}
4146 interface(CONST_INTER);
4147 %}
4148
4149 // Unsigned Integer Immediate: 6-bit
4150 operand uimmI6() %{
4151 predicate(Assembler::is_uimm(n->get_int(), 6));
4152 match(ConI);
4153 op_cost(0);
4154 format %{ %}
4155 interface(CONST_INTER);
4156 %}
4157
4158 // Unsigned Integer Immediate: 6-bit int, greater than 32
4159 operand uimmI6_ge32() %{
4160 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4161 match(ConI);
4162 op_cost(0);
4163 format %{ %}
4164 interface(CONST_INTER);
4165 %}
4166
4167 // Unsigned Integer Immediate: 15-bit
4168 operand uimmI15() %{
4169 predicate(Assembler::is_uimm(n->get_int(), 15));
4170 match(ConI);
4171 op_cost(0);
4172 format %{ %}
4173 interface(CONST_INTER);
4174 %}
4175
4176 // Unsigned Integer Immediate: 16-bit
4177 operand uimmI16() %{
4178 predicate(Assembler::is_uimm(n->get_int(), 16));
4179 match(ConI);
4180 op_cost(0);
4181 format %{ %}
4182 interface(CONST_INTER);
4183 %}
4184
4185 // constant 'int 0'.
4186 operand immI_0() %{
4187 predicate(n->get_int() == 0);
4188 match(ConI);
4189 op_cost(0);
4190 format %{ %}
4191 interface(CONST_INTER);
4192 %}
4193
4194 // constant 'int 1'.
4195 operand immI_1() %{
4196 predicate(n->get_int() == 1);
4197 match(ConI);
4198 op_cost(0);
4199 format %{ %}
4200 interface(CONST_INTER);
4201 %}
4202
4203 // constant 'int -1'.
4204 operand immI_minus1() %{
4205 predicate(n->get_int() == -1);
4206 match(ConI);
4207 op_cost(0);
4208 format %{ %}
4209 interface(CONST_INTER);
4210 %}
4211
4212 // int value 16.
4213 operand immI_16() %{
4214 predicate(n->get_int() == 16);
4215 match(ConI);
4216 op_cost(0);
4217 format %{ %}
4218 interface(CONST_INTER);
4219 %}
4220
4221 // int value 24.
4222 operand immI_24() %{
4223 predicate(n->get_int() == 24);
4224 match(ConI);
4225 op_cost(0);
4226 format %{ %}
4227 interface(CONST_INTER);
4228 %}
4229
4230 // Compressed oops constants
4231 // Pointer Immediate
4232 operand immN() %{
4233 match(ConN);
4234
4235 op_cost(10);
4236 format %{ %}
4237 interface(CONST_INTER);
4238 %}
4239
4240 // NULL Pointer Immediate
4241 operand immN_0() %{
4242 predicate(n->get_narrowcon() == 0);
4243 match(ConN);
4244
4245 op_cost(0);
4246 format %{ %}
4247 interface(CONST_INTER);
4248 %}
4249
4250 // Compressed klass constants
4251 operand immNKlass() %{
4252 match(ConNKlass);
4253
4254 op_cost(0);
4255 format %{ %}
4256 interface(CONST_INTER);
4257 %}
4258
4259 // This operand can be used to avoid matching of an instruct
4260 // with chain rule.
4261 operand immNKlass_NM() %{
4262 match(ConNKlass);
4263 predicate(false);
4264 op_cost(0);
4265 format %{ %}
4266 interface(CONST_INTER);
4267 %}
4268
4269 // Pointer Immediate: 64-bit
4270 operand immP() %{
4271 match(ConP);
4272 op_cost(0);
4273 format %{ %}
4274 interface(CONST_INTER);
4275 %}
4276
4277 // Operand to avoid match of loadConP.
4278 // This operand can be used to avoid matching of an instruct
4279 // with chain rule.
4280 operand immP_NM() %{
4281 match(ConP);
4282 predicate(false);
4283 op_cost(0);
4284 format %{ %}
4285 interface(CONST_INTER);
4286 %}
4287
4288 // costant 'pointer 0'.
4289 operand immP_0() %{
4290 predicate(n->get_ptr() == 0);
4291 match(ConP);
4292 op_cost(0);
4293 format %{ %}
4294 interface(CONST_INTER);
4295 %}
4296
4297 // pointer 0x0 or 0x1
4298 operand immP_0or1() %{
4299 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4300 match(ConP);
4301 op_cost(0);
4302 format %{ %}
4303 interface(CONST_INTER);
4304 %}
4305
4306 operand immL() %{
4307 match(ConL);
4308 op_cost(40);
4309 format %{ %}
4310 interface(CONST_INTER);
4311 %}
4312
4313 // Long Immediate: 16-bit
4314 operand immL16() %{
4315 predicate(Assembler::is_simm(n->get_long(), 16));
4316 match(ConL);
4317 op_cost(0);
4318 format %{ %}
4319 interface(CONST_INTER);
4320 %}
4321
4322 // Long Immediate: 16-bit, 4-aligned
4323 operand immL16Alg4() %{
4324 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4325 match(ConL);
4326 op_cost(0);
4327 format %{ %}
4328 interface(CONST_INTER);
4329 %}
4330
4331 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4332 operand immL32hi16() %{
4333 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4334 match(ConL);
4335 op_cost(0);
4336 format %{ %}
4337 interface(CONST_INTER);
4338 %}
4339
4340 // Long Immediate: 32-bit
4341 operand immL32() %{
4342 predicate(Assembler::is_simm(n->get_long(), 32));
4343 match(ConL);
4344 op_cost(0);
4345 format %{ %}
4346 interface(CONST_INTER);
4347 %}
4348
4349 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4350 operand immLhighest16() %{
4351 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4352 match(ConL);
4353 op_cost(0);
4354 format %{ %}
4355 interface(CONST_INTER);
4356 %}
4357
4358 operand immLnegpow2() %{
4359 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4360 match(ConL);
4361 op_cost(0);
4362 format %{ %}
4363 interface(CONST_INTER);
4364 %}
4365
4366 operand immLpow2minus1() %{
4367 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4368 (n->get_long() != (jlong)0xffffffffffffffffL));
4369 match(ConL);
4370 op_cost(0);
4371 format %{ %}
4372 interface(CONST_INTER);
4373 %}
4374
4375 // constant 'long 0'.
4376 operand immL_0() %{
4377 predicate(n->get_long() == 0L);
4378 match(ConL);
4379 op_cost(0);
4380 format %{ %}
4381 interface(CONST_INTER);
4382 %}
4383
4384 // constat ' long -1'.
4385 operand immL_minus1() %{
4386 predicate(n->get_long() == -1L);
4387 match(ConL);
4388 op_cost(0);
4389 format %{ %}
4390 interface(CONST_INTER);
4391 %}
4392
4393 // Long Immediate: low 32-bit mask
4394 operand immL_32bits() %{
4395 predicate(n->get_long() == 0xFFFFFFFFL);
4396 match(ConL);
4397 op_cost(0);
4398 format %{ %}
4399 interface(CONST_INTER);
4400 %}
4401
4402 // Unsigned Long Immediate: 16-bit
4403 operand uimmL16() %{
4404 predicate(Assembler::is_uimm(n->get_long(), 16));
4405 match(ConL);
4406 op_cost(0);
4407 format %{ %}
4408 interface(CONST_INTER);
4409 %}
4410
4411 // Float Immediate
4412 operand immF() %{
4413 match(ConF);
4414 op_cost(40);
4415 format %{ %}
4416 interface(CONST_INTER);
4417 %}
4418
4419 // Float Immediate: +0.0f.
4420 operand immF_0() %{
4421 predicate(jint_cast(n->getf()) == 0);
4422 match(ConF);
4423
4424 op_cost(0);
4425 format %{ %}
4426 interface(CONST_INTER);
4427 %}
4428
4429 // Double Immediate
4430 operand immD() %{
4431 match(ConD);
4432 op_cost(40);
4433 format %{ %}
4434 interface(CONST_INTER);
4435 %}
4436
4437 // Integer Register Operands
4438 // Integer Destination Register
4439 // See definition of reg_class bits32_reg_rw.
4440 operand iRegIdst() %{
4441 constraint(ALLOC_IN_RC(bits32_reg_rw));
4442 match(RegI);
4443 match(rscratch1RegI);
4444 match(rscratch2RegI);
4445 match(rarg1RegI);
4446 match(rarg2RegI);
4447 match(rarg3RegI);
4448 match(rarg4RegI);
4449 format %{ %}
4450 interface(REG_INTER);
4451 %}
4452
4453 // Integer Source Register
4454 // See definition of reg_class bits32_reg_ro.
4455 operand iRegIsrc() %{
4456 constraint(ALLOC_IN_RC(bits32_reg_ro));
4457 match(RegI);
4458 match(rscratch1RegI);
4459 match(rscratch2RegI);
4460 match(rarg1RegI);
4461 match(rarg2RegI);
4462 match(rarg3RegI);
4463 match(rarg4RegI);
4464 format %{ %}
4465 interface(REG_INTER);
4466 %}
4467
4468 operand rscratch1RegI() %{
4469 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4470 match(iRegIdst);
4471 format %{ %}
4472 interface(REG_INTER);
4473 %}
4474
4475 operand rscratch2RegI() %{
4476 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4477 match(iRegIdst);
4478 format %{ %}
4479 interface(REG_INTER);
4480 %}
4481
4482 operand rarg1RegI() %{
4483 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4484 match(iRegIdst);
4485 format %{ %}
4486 interface(REG_INTER);
4487 %}
4488
4489 operand rarg2RegI() %{
4490 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4491 match(iRegIdst);
4492 format %{ %}
4493 interface(REG_INTER);
4494 %}
4495
4496 operand rarg3RegI() %{
4497 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4498 match(iRegIdst);
4499 format %{ %}
4500 interface(REG_INTER);
4501 %}
4502
4503 operand rarg4RegI() %{
4504 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4505 match(iRegIdst);
4506 format %{ %}
4507 interface(REG_INTER);
4508 %}
4509
4510 operand rarg1RegL() %{
4511 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4512 match(iRegLdst);
4513 format %{ %}
4514 interface(REG_INTER);
4515 %}
4516
4517 operand rarg2RegL() %{
4518 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4519 match(iRegLdst);
4520 format %{ %}
4521 interface(REG_INTER);
4522 %}
4523
4524 operand rarg3RegL() %{
4525 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4526 match(iRegLdst);
4527 format %{ %}
4528 interface(REG_INTER);
4529 %}
4530
4531 operand rarg4RegL() %{
4532 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4533 match(iRegLdst);
4534 format %{ %}
4535 interface(REG_INTER);
4536 %}
4537
4538 // Pointer Destination Register
4539 // See definition of reg_class bits64_reg_rw.
4540 operand iRegPdst() %{
4541 constraint(ALLOC_IN_RC(bits64_reg_rw));
4542 match(RegP);
4543 match(rscratch1RegP);
4544 match(rscratch2RegP);
4545 match(rarg1RegP);
4546 match(rarg2RegP);
4547 match(rarg3RegP);
4548 match(rarg4RegP);
4549 format %{ %}
4550 interface(REG_INTER);
4551 %}
4552
4553 // Pointer Destination Register
4554 // Operand not using r11 and r12 (killed in epilog).
4555 operand iRegPdstNoScratch() %{
4556 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4557 match(RegP);
4558 match(rarg1RegP);
4559 match(rarg2RegP);
4560 match(rarg3RegP);
4561 match(rarg4RegP);
4562 format %{ %}
4563 interface(REG_INTER);
4564 %}
4565
4566 // Pointer Source Register
4567 // See definition of reg_class bits64_reg_ro.
4568 operand iRegPsrc() %{
4569 constraint(ALLOC_IN_RC(bits64_reg_ro));
4570 match(RegP);
4571 match(iRegPdst);
4572 match(rscratch1RegP);
4573 match(rscratch2RegP);
4574 match(rarg1RegP);
4575 match(rarg2RegP);
4576 match(rarg3RegP);
4577 match(rarg4RegP);
4578 match(threadRegP);
4579 format %{ %}
4580 interface(REG_INTER);
4581 %}
4582
4583 // Thread operand.
4584 operand threadRegP() %{
4585 constraint(ALLOC_IN_RC(thread_bits64_reg));
4586 match(iRegPdst);
4587 format %{ "R16" %}
4588 interface(REG_INTER);
4589 %}
4590
4591 operand rscratch1RegP() %{
4592 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4593 match(iRegPdst);
4594 format %{ "R11" %}
4595 interface(REG_INTER);
4596 %}
4597
4598 operand rscratch2RegP() %{
4599 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4600 match(iRegPdst);
4601 format %{ %}
4602 interface(REG_INTER);
4603 %}
4604
4605 operand rarg1RegP() %{
4606 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4607 match(iRegPdst);
4608 format %{ %}
4609 interface(REG_INTER);
4610 %}
4611
4612 operand rarg2RegP() %{
4613 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4614 match(iRegPdst);
4615 format %{ %}
4616 interface(REG_INTER);
4617 %}
4618
4619 operand rarg3RegP() %{
4620 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4621 match(iRegPdst);
4622 format %{ %}
4623 interface(REG_INTER);
4624 %}
4625
4626 operand rarg4RegP() %{
4627 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4628 match(iRegPdst);
4629 format %{ %}
4630 interface(REG_INTER);
4631 %}
4632
4633 operand iRegNsrc() %{
4634 constraint(ALLOC_IN_RC(bits32_reg_ro));
4635 match(RegN);
4636 match(iRegNdst);
4637
4638 format %{ %}
4639 interface(REG_INTER);
4640 %}
4641
4642 operand iRegNdst() %{
4643 constraint(ALLOC_IN_RC(bits32_reg_rw));
4644 match(RegN);
4645
4646 format %{ %}
4647 interface(REG_INTER);
4648 %}
4649
4650 // Long Destination Register
4651 // See definition of reg_class bits64_reg_rw.
4652 operand iRegLdst() %{
4653 constraint(ALLOC_IN_RC(bits64_reg_rw));
4654 match(RegL);
4655 match(rscratch1RegL);
4656 match(rscratch2RegL);
4657 format %{ %}
4658 interface(REG_INTER);
4659 %}
4660
4661 // Long Source Register
4662 // See definition of reg_class bits64_reg_ro.
4663 operand iRegLsrc() %{
4664 constraint(ALLOC_IN_RC(bits64_reg_ro));
4665 match(RegL);
4666 match(iRegLdst);
4667 match(rscratch1RegL);
4668 match(rscratch2RegL);
4669 format %{ %}
4670 interface(REG_INTER);
4671 %}
4672
4673 // Special operand for ConvL2I.
4674 operand iRegL2Isrc(iRegLsrc reg) %{
4675 constraint(ALLOC_IN_RC(bits64_reg_ro));
4676 match(ConvL2I reg);
4677 format %{ "ConvL2I($reg)" %}
4678 interface(REG_INTER)
4679 %}
4680
4681 operand rscratch1RegL() %{
4682 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4683 match(RegL);
4684 format %{ %}
4685 interface(REG_INTER);
4686 %}
4687
4688 operand rscratch2RegL() %{
4689 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4690 match(RegL);
4691 format %{ %}
4692 interface(REG_INTER);
4693 %}
4694
4695 // Condition Code Flag Registers
4696 operand flagsReg() %{
4697 constraint(ALLOC_IN_RC(int_flags));
4698 match(RegFlags);
4699 format %{ %}
4700 interface(REG_INTER);
4701 %}
4702
4703 // Condition Code Flag Register CR0
4704 operand flagsRegCR0() %{
4705 constraint(ALLOC_IN_RC(int_flags_CR0));
4706 match(RegFlags);
4707 format %{ "CR0" %}
4708 interface(REG_INTER);
4709 %}
4710
4711 operand flagsRegCR1() %{
4712 constraint(ALLOC_IN_RC(int_flags_CR1));
4713 match(RegFlags);
4714 format %{ "CR1" %}
4715 interface(REG_INTER);
4716 %}
4717
4718 operand flagsRegCR6() %{
4719 constraint(ALLOC_IN_RC(int_flags_CR6));
4720 match(RegFlags);
4721 format %{ "CR6" %}
4722 interface(REG_INTER);
4723 %}
4724
4725 operand regCTR() %{
4726 constraint(ALLOC_IN_RC(ctr_reg));
4727 // RegFlags should work. Introducing a RegSpecial type would cause a
4728 // lot of changes.
4729 match(RegFlags);
4730 format %{"SR_CTR" %}
4731 interface(REG_INTER);
4732 %}
4733
4734 operand regD() %{
4735 constraint(ALLOC_IN_RC(dbl_reg));
4736 match(RegD);
4737 format %{ %}
4738 interface(REG_INTER);
4739 %}
4740
4741 operand regF() %{
4742 constraint(ALLOC_IN_RC(flt_reg));
4743 match(RegF);
4744 format %{ %}
4745 interface(REG_INTER);
4746 %}
4747
4748 // Special Registers
4749
4750 // Method Register
4751 operand inline_cache_regP(iRegPdst reg) %{
4752 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4753 match(reg);
4754 format %{ %}
4755 interface(REG_INTER);
4756 %}
4757
4758 operand compiler_method_oop_regP(iRegPdst reg) %{
4759 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4760 match(reg);
4761 format %{ %}
4762 interface(REG_INTER);
4763 %}
4764
4765 operand interpreter_method_oop_regP(iRegPdst reg) %{
4766 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4767 match(reg);
4768 format %{ %}
4769 interface(REG_INTER);
4770 %}
4771
4772 // Operands to remove register moves in unscaled mode.
4773 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4774 operand iRegP2N(iRegPsrc reg) %{
4775 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4776 constraint(ALLOC_IN_RC(bits64_reg_ro));
4777 match(EncodeP reg);
4778 format %{ "$reg" %}
4779 interface(REG_INTER)
4780 %}
4781
4782 operand iRegN2P(iRegNsrc reg) %{
4783 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4784 constraint(ALLOC_IN_RC(bits32_reg_ro));
4785 match(DecodeN reg);
4786 match(DecodeNKlass reg);
4787 format %{ "$reg" %}
4788 interface(REG_INTER)
4789 %}
4790
4791 //----------Complex Operands---------------------------------------------------
4792 // Indirect Memory Reference
4793 operand indirect(iRegPsrc reg) %{
4794 constraint(ALLOC_IN_RC(bits64_reg_ro));
4795 match(reg);
4796 op_cost(100);
4797 format %{ "[$reg]" %}
4798 interface(MEMORY_INTER) %{
4799 base($reg);
4800 index(0x0);
4801 scale(0x0);
4802 disp(0x0);
4803 %}
4804 %}
4805
4806 // Indirect with Offset
4807 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4808 constraint(ALLOC_IN_RC(bits64_reg_ro));
4809 match(AddP reg offset);
4810 op_cost(100);
4811 format %{ "[$reg + $offset]" %}
4812 interface(MEMORY_INTER) %{
4813 base($reg);
4814 index(0x0);
4815 scale(0x0);
4816 disp($offset);
4817 %}
4818 %}
4819
4820 // Indirect with 4-aligned Offset
4821 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4822 constraint(ALLOC_IN_RC(bits64_reg_ro));
4823 match(AddP reg offset);
4824 op_cost(100);
4825 format %{ "[$reg + $offset]" %}
4826 interface(MEMORY_INTER) %{
4827 base($reg);
4828 index(0x0);
4829 scale(0x0);
4830 disp($offset);
4831 %}
4832 %}
4833
4834 //----------Complex Operands for Compressed OOPs-------------------------------
4835 // Compressed OOPs with narrow_oop_shift == 0.
4836
4837 // Indirect Memory Reference, compressed OOP
4838 operand indirectNarrow(iRegNsrc reg) %{
4839 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4840 constraint(ALLOC_IN_RC(bits64_reg_ro));
4841 match(DecodeN reg);
4842 match(DecodeNKlass reg);
4843 op_cost(100);
4844 format %{ "[$reg]" %}
4845 interface(MEMORY_INTER) %{
4846 base($reg);
4847 index(0x0);
4848 scale(0x0);
4849 disp(0x0);
4850 %}
4851 %}
4852
4853 // Indirect with Offset, compressed OOP
4854 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4855 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4856 constraint(ALLOC_IN_RC(bits64_reg_ro));
4857 match(AddP (DecodeN reg) offset);
4858 match(AddP (DecodeNKlass reg) offset);
4859 op_cost(100);
4860 format %{ "[$reg + $offset]" %}
4861 interface(MEMORY_INTER) %{
4862 base($reg);
4863 index(0x0);
4864 scale(0x0);
4865 disp($offset);
4866 %}
4867 %}
4868
4869 // Indirect with 4-aligned Offset, compressed OOP
4870 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4871 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4872 constraint(ALLOC_IN_RC(bits64_reg_ro));
4873 match(AddP (DecodeN reg) offset);
4874 match(AddP (DecodeNKlass reg) offset);
4875 op_cost(100);
4876 format %{ "[$reg + $offset]" %}
4877 interface(MEMORY_INTER) %{
4878 base($reg);
4879 index(0x0);
4880 scale(0x0);
4881 disp($offset);
4882 %}
4883 %}
4884
4885 //----------Special Memory Operands--------------------------------------------
4886 // Stack Slot Operand
4887 //
4888 // This operand is used for loading and storing temporary values on
4889 // the stack where a match requires a value to flow through memory.
4890 operand stackSlotI(sRegI reg) %{
4891 constraint(ALLOC_IN_RC(stack_slots));
4892 op_cost(100);
4893 //match(RegI);
4894 format %{ "[sp+$reg]" %}
4895 interface(MEMORY_INTER) %{
4896 base(0x1); // R1_SP
4897 index(0x0);
4898 scale(0x0);
4899 disp($reg); // Stack Offset
4900 %}
4901 %}
4902
4903 operand stackSlotL(sRegL reg) %{
4904 constraint(ALLOC_IN_RC(stack_slots));
4905 op_cost(100);
4906 //match(RegL);
4907 format %{ "[sp+$reg]" %}
4908 interface(MEMORY_INTER) %{
4909 base(0x1); // R1_SP
4910 index(0x0);
4911 scale(0x0);
4912 disp($reg); // Stack Offset
4913 %}
4914 %}
4915
4916 operand stackSlotP(sRegP reg) %{
4917 constraint(ALLOC_IN_RC(stack_slots));
4918 op_cost(100);
4919 //match(RegP);
4920 format %{ "[sp+$reg]" %}
4921 interface(MEMORY_INTER) %{
4922 base(0x1); // R1_SP
4923 index(0x0);
4924 scale(0x0);
4925 disp($reg); // Stack Offset
4926 %}
4927 %}
4928
4929 operand stackSlotF(sRegF reg) %{
4930 constraint(ALLOC_IN_RC(stack_slots));
4931 op_cost(100);
4932 //match(RegF);
4933 format %{ "[sp+$reg]" %}
4934 interface(MEMORY_INTER) %{
4935 base(0x1); // R1_SP
4936 index(0x0);
4937 scale(0x0);
4938 disp($reg); // Stack Offset
4939 %}
4940 %}
4941
4942 operand stackSlotD(sRegD reg) %{
4943 constraint(ALLOC_IN_RC(stack_slots));
4944 op_cost(100);
4945 //match(RegD);
4946 format %{ "[sp+$reg]" %}
4947 interface(MEMORY_INTER) %{
4948 base(0x1); // R1_SP
4949 index(0x0);
4950 scale(0x0);
4951 disp($reg); // Stack Offset
4952 %}
4953 %}
4954
4955 // Operands for expressing Control Flow
4956 // NOTE: Label is a predefined operand which should not be redefined in
4957 // the AD file. It is generically handled within the ADLC.
4958
4959 //----------Conditional Branch Operands----------------------------------------
4960 // Comparison Op
4961 //
4962 // This is the operation of the comparison, and is limited to the
4963 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4964 // (!=).
4965 //
4966 // Other attributes of the comparison, such as unsignedness, are specified
4967 // by the comparison instruction that sets a condition code flags register.
4968 // That result is represented by a flags operand whose subtype is appropriate
4969 // to the unsignedness (etc.) of the comparison.
4970 //
4971 // Later, the instruction which matches both the Comparison Op (a Bool) and
4972 // the flags (produced by the Cmp) specifies the coding of the comparison op
4973 // by matching a specific subtype of Bool operand below.
4974
4975 // When used for floating point comparisons: unordered same as less.
4976 operand cmpOp() %{
4977 match(Bool);
4978 format %{ "" %}
4979 interface(COND_INTER) %{
4980 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4981 // BO & BI
4982 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4983 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4984 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4985 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4986 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4987 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4988 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4989 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4990 %}
4991 %}
4992
4993 //----------OPERAND CLASSES----------------------------------------------------
4994 // Operand Classes are groups of operands that are used to simplify
4995 // instruction definitions by not requiring the AD writer to specify
4996 // seperate instructions for every form of operand when the
4997 // instruction accepts multiple operand types with the same basic
4998 // encoding and format. The classic case of this is memory operands.
4999 // Indirect is not included since its use is limited to Compare & Swap.
5000
5001 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
5002 // Memory operand where offsets are 4-aligned. Required for ld, std.
5003 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
5004 opclass indirectMemory(indirect, indirectNarrow);
5005
5006 // Special opclass for I and ConvL2I.
5007 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5008
5009 // Operand classes to match encode and decode. iRegN_P2N is only used
5010 // for storeN. I have never seen an encode node elsewhere.
5011 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5012 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5013
5014 //----------PIPELINE-----------------------------------------------------------
5015
5016 pipeline %{
5017
5018 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5019 // J. Res. & Dev., No. 1, Jan. 2002.
5020
5021 //----------ATTRIBUTES---------------------------------------------------------
5022 attributes %{
5023
5024 // Power4 instructions are of fixed length.
5025 fixed_size_instructions;
5026
5027 // TODO: if `bundle' means number of instructions fetched
5028 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5029 // max instructions issued per cycle, this is 5.
5030 max_instructions_per_bundle = 8;
5031
5032 // A Power4 instruction is 4 bytes long.
5033 instruction_unit_size = 4;
5034
5035 // The Power4 processor fetches 64 bytes...
5036 instruction_fetch_unit_size = 64;
5037
5038 // ...in one line
5039 instruction_fetch_units = 1
5040
5041 // Unused, list one so that array generated by adlc is not empty.
5042 // Aix compiler chokes if _nop_count = 0.
5043 nops(fxNop);
5044 %}
5045
5046 //----------RESOURCES----------------------------------------------------------
5047 // Resources are the functional units available to the machine
5048 resources(
5049 PPC_BR, // branch unit
5050 PPC_CR, // condition unit
5051 PPC_FX1, // integer arithmetic unit 1
5052 PPC_FX2, // integer arithmetic unit 2
5053 PPC_LDST1, // load/store unit 1
5054 PPC_LDST2, // load/store unit 2
5055 PPC_FP1, // float arithmetic unit 1
5056 PPC_FP2, // float arithmetic unit 2
5057 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5058 PPC_FX = PPC_FX1 | PPC_FX2,
5059 PPC_FP = PPC_FP1 | PPC_FP2
5060 );
5061
5062 //----------PIPELINE DESCRIPTION-----------------------------------------------
5063 // Pipeline Description specifies the stages in the machine's pipeline
5064 pipe_desc(
5065 // Power4 longest pipeline path
5066 PPC_IF, // instruction fetch
5067 PPC_IC,
5068 //PPC_BP, // branch prediction
5069 PPC_D0, // decode
5070 PPC_D1, // decode
5071 PPC_D2, // decode
5072 PPC_D3, // decode
5073 PPC_Xfer1,
5074 PPC_GD, // group definition
5075 PPC_MP, // map
5076 PPC_ISS, // issue
5077 PPC_RF, // resource fetch
5078 PPC_EX1, // execute (all units)
5079 PPC_EX2, // execute (FP, LDST)
5080 PPC_EX3, // execute (FP, LDST)
5081 PPC_EX4, // execute (FP)
5082 PPC_EX5, // execute (FP)
5083 PPC_EX6, // execute (FP)
5084 PPC_WB, // write back
5085 PPC_Xfer2,
5086 PPC_CP
5087 );
5088
5089 //----------PIPELINE CLASSES---------------------------------------------------
5090 // Pipeline Classes describe the stages in which input and output are
5091 // referenced by the hardware pipeline.
5092
5093 // Simple pipeline classes.
5094
5095 // Default pipeline class.
5096 pipe_class pipe_class_default() %{
5097 single_instruction;
5098 fixed_latency(2);
5099 %}
5100
5101 // Pipeline class for empty instructions.
5102 pipe_class pipe_class_empty() %{
5103 single_instruction;
5104 fixed_latency(0);
5105 %}
5106
5107 // Pipeline class for compares.
5108 pipe_class pipe_class_compare() %{
5109 single_instruction;
5110 fixed_latency(16);
5111 %}
5112
5113 // Pipeline class for traps.
5114 pipe_class pipe_class_trap() %{
5115 single_instruction;
5116 fixed_latency(100);
5117 %}
5118
5119 // Pipeline class for memory operations.
5120 pipe_class pipe_class_memory() %{
5121 single_instruction;
5122 fixed_latency(16);
5123 %}
5124
5125 // Pipeline class for call.
5126 pipe_class pipe_class_call() %{
5127 single_instruction;
5128 fixed_latency(100);
5129 %}
5130
5131 // Define the class for the Nop node.
5132 define %{
5133 MachNop = pipe_class_default;
5134 %}
5135
5136 %}
5137
5138 //----------INSTRUCTIONS-------------------------------------------------------
5139
5140 // Naming of instructions:
5141 // opA_operB / opA_operB_operC:
5142 // Operation 'op' with one or two source operands 'oper'. Result
5143 // type is A, source operand types are B and C.
5144 // Iff A == B == C, B and C are left out.
5145 //
5146 // The instructions are ordered according to the following scheme:
5147 // - loads
5148 // - load constants
5149 // - prefetch
5150 // - store
5151 // - encode/decode
5152 // - membar
5153 // - conditional moves
5154 // - compare & swap
5155 // - arithmetic and logic operations
5156 // * int: Add, Sub, Mul, Div, Mod
5157 // * int: lShift, arShift, urShift, rot
5158 // * float: Add, Sub, Mul, Div
5159 // * and, or, xor ...
5160 // - register moves: float <-> int, reg <-> stack, repl
5161 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5162 // - conv (low level type cast requiring bit changes (sign extend etc)
5163 // - compares, range & zero checks.
5164 // - branches
5165 // - complex operations, intrinsics, min, max, replicate
5166 // - lock
5167 // - Calls
5168 //
5169 // If there are similar instructions with different types they are sorted:
5170 // int before float
5171 // small before big
5172 // signed before unsigned
5173 // e.g., loadS before loadUS before loadI before loadF.
5174
5175
5176 //----------Load/Store Instructions--------------------------------------------
5177
5178 //----------Load Instructions--------------------------------------------------
5179
5180 // Converts byte to int.
5181 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5182 // reuses the 'amount' operand, but adlc expects that operand specification
5183 // and operands in match rule are equivalent.
5184 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5185 effect(DEF dst, USE src);
5186 format %{ "EXTSB $dst, $src \t// byte->int" %}
5187 size(4);
5188 ins_encode %{
5189 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5190 __ extsb($dst$$Register, $src$$Register);
5191 %}
5192 ins_pipe(pipe_class_default);
5193 %}
5194
5195 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5196 // match-rule, false predicate
5197 match(Set dst (LoadB mem));
5198 predicate(false);
5199
5200 format %{ "LBZ $dst, $mem" %}
5201 size(4);
5202 ins_encode( enc_lbz(dst, mem) );
5203 ins_pipe(pipe_class_memory);
5204 %}
5205
5206 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5207 // match-rule, false predicate
5208 match(Set dst (LoadB mem));
5209 predicate(false);
5210
5211 format %{ "LBZ $dst, $mem\n\t"
5212 "TWI $dst\n\t"
5213 "ISYNC" %}
5214 size(12);
5215 ins_encode( enc_lbz_ac(dst, mem) );
5216 ins_pipe(pipe_class_memory);
5217 %}
5218
5219 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5220 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5221 match(Set dst (LoadB mem));
5222 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5223 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5224 expand %{
5225 iRegIdst tmp;
5226 loadUB_indirect(tmp, mem);
5227 convB2I_reg_2(dst, tmp);
5228 %}
5229 %}
5230
5231 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5232 match(Set dst (LoadB mem));
5233 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5234 expand %{
5235 iRegIdst tmp;
5236 loadUB_indirect_ac(tmp, mem);
5237 convB2I_reg_2(dst, tmp);
5238 %}
5239 %}
5240
5241 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5242 // match-rule, false predicate
5243 match(Set dst (LoadB mem));
5244 predicate(false);
5245
5246 format %{ "LBZ $dst, $mem" %}
5247 size(4);
5248 ins_encode( enc_lbz(dst, mem) );
5249 ins_pipe(pipe_class_memory);
5250 %}
5251
5252 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5253 // match-rule, false predicate
5254 match(Set dst (LoadB mem));
5255 predicate(false);
5256
5257 format %{ "LBZ $dst, $mem\n\t"
5258 "TWI $dst\n\t"
5259 "ISYNC" %}
5260 size(12);
5261 ins_encode( enc_lbz_ac(dst, mem) );
5262 ins_pipe(pipe_class_memory);
5263 %}
5264
5265 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5266 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5267 match(Set dst (LoadB mem));
5268 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5269 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5270
5271 expand %{
5272 iRegIdst tmp;
5273 loadUB_indOffset16(tmp, mem);
5274 convB2I_reg_2(dst, tmp);
5275 %}
5276 %}
5277
5278 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5279 match(Set dst (LoadB mem));
5280 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5281
5282 expand %{
5283 iRegIdst tmp;
5284 loadUB_indOffset16_ac(tmp, mem);
5285 convB2I_reg_2(dst, tmp);
5286 %}
5287 %}
5288
5289 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5290 instruct loadUB(iRegIdst dst, memory mem) %{
5291 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5292 match(Set dst (LoadUB mem));
5293 ins_cost(MEMORY_REF_COST);
5294
5295 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5296 size(4);
5297 ins_encode( enc_lbz(dst, mem) );
5298 ins_pipe(pipe_class_memory);
5299 %}
5300
5301 // Load Unsigned Byte (8bit UNsigned) acquire.
5302 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5303 match(Set dst (LoadUB mem));
5304 ins_cost(3*MEMORY_REF_COST);
5305
5306 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5307 "TWI $dst\n\t"
5308 "ISYNC" %}
5309 size(12);
5310 ins_encode( enc_lbz_ac(dst, mem) );
5311 ins_pipe(pipe_class_memory);
5312 %}
5313
5314 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5315 instruct loadUB2L(iRegLdst dst, memory mem) %{
5316 match(Set dst (ConvI2L (LoadUB mem)));
5317 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5318 ins_cost(MEMORY_REF_COST);
5319
5320 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5321 size(4);
5322 ins_encode( enc_lbz(dst, mem) );
5323 ins_pipe(pipe_class_memory);
5324 %}
5325
5326 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5327 match(Set dst (ConvI2L (LoadUB mem)));
5328 ins_cost(3*MEMORY_REF_COST);
5329
5330 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5331 "TWI $dst\n\t"
5332 "ISYNC" %}
5333 size(12);
5334 ins_encode( enc_lbz_ac(dst, mem) );
5335 ins_pipe(pipe_class_memory);
5336 %}
5337
5338 // Load Short (16bit signed)
5339 instruct loadS(iRegIdst dst, memory mem) %{
5340 match(Set dst (LoadS mem));
5341 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5342 ins_cost(MEMORY_REF_COST);
5343
5344 format %{ "LHA $dst, $mem" %}
5345 size(4);
5346 ins_encode %{
5347 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5348 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5349 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5350 %}
5351 ins_pipe(pipe_class_memory);
5352 %}
5353
5354 // Load Short (16bit signed) acquire.
5355 instruct loadS_ac(iRegIdst dst, memory mem) %{
5356 match(Set dst (LoadS mem));
5357 ins_cost(3*MEMORY_REF_COST);
5358
5359 format %{ "LHA $dst, $mem\t acquire\n\t"
5360 "TWI $dst\n\t"
5361 "ISYNC" %}
5362 size(12);
5363 ins_encode %{
5364 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5365 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5366 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5367 __ twi_0($dst$$Register);
5368 __ isync();
5369 %}
5370 ins_pipe(pipe_class_memory);
5371 %}
5372
5373 // Load Char (16bit unsigned)
5374 instruct loadUS(iRegIdst dst, memory mem) %{
5375 match(Set dst (LoadUS mem));
5376 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5377 ins_cost(MEMORY_REF_COST);
5378
5379 format %{ "LHZ $dst, $mem" %}
5380 size(4);
5381 ins_encode( enc_lhz(dst, mem) );
5382 ins_pipe(pipe_class_memory);
5383 %}
5384
5385 // Load Char (16bit unsigned) acquire.
5386 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5387 match(Set dst (LoadUS mem));
5388 ins_cost(3*MEMORY_REF_COST);
5389
5390 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5391 "TWI $dst\n\t"
5392 "ISYNC" %}
5393 size(12);
5394 ins_encode( enc_lhz_ac(dst, mem) );
5395 ins_pipe(pipe_class_memory);
5396 %}
5397
5398 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5399 instruct loadUS2L(iRegLdst dst, memory mem) %{
5400 match(Set dst (ConvI2L (LoadUS mem)));
5401 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5402 ins_cost(MEMORY_REF_COST);
5403
5404 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5405 size(4);
5406 ins_encode( enc_lhz(dst, mem) );
5407 ins_pipe(pipe_class_memory);
5408 %}
5409
5410 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5411 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5412 match(Set dst (ConvI2L (LoadUS mem)));
5413 ins_cost(3*MEMORY_REF_COST);
5414
5415 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5416 "TWI $dst\n\t"
5417 "ISYNC" %}
5418 size(12);
5419 ins_encode( enc_lhz_ac(dst, mem) );
5420 ins_pipe(pipe_class_memory);
5421 %}
5422
5423 // Load Integer.
5424 instruct loadI(iRegIdst dst, memory mem) %{
5425 match(Set dst (LoadI mem));
5426 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5427 ins_cost(MEMORY_REF_COST);
5428
5429 format %{ "LWZ $dst, $mem" %}
5430 size(4);
5431 ins_encode( enc_lwz(dst, mem) );
5432 ins_pipe(pipe_class_memory);
5433 %}
5434
5435 // Load Integer acquire.
5436 instruct loadI_ac(iRegIdst dst, memory mem) %{
5437 match(Set dst (LoadI mem));
5438 ins_cost(3*MEMORY_REF_COST);
5439
5440 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5441 "TWI $dst\n\t"
5442 "ISYNC" %}
5443 size(12);
5444 ins_encode( enc_lwz_ac(dst, mem) );
5445 ins_pipe(pipe_class_memory);
5446 %}
5447
5448 // Match loading integer and casting it to unsigned int in
5449 // long register.
5450 // LoadI + ConvI2L + AndL 0xffffffff.
5451 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5452 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5453 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5454 ins_cost(MEMORY_REF_COST);
5455
5456 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5457 size(4);
5458 ins_encode( enc_lwz(dst, mem) );
5459 ins_pipe(pipe_class_memory);
5460 %}
5461
5462 // Match loading integer and casting it to long.
5463 instruct loadI2L(iRegLdst dst, memory mem) %{
5464 match(Set dst (ConvI2L (LoadI mem)));
5465 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5466 ins_cost(MEMORY_REF_COST);
5467
5468 format %{ "LWA $dst, $mem \t// loadI2L" %}
5469 size(4);
5470 ins_encode %{
5471 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5472 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5473 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5474 %}
5475 ins_pipe(pipe_class_memory);
5476 %}
5477
5478 // Match loading integer and casting it to long - acquire.
5479 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5480 match(Set dst (ConvI2L (LoadI mem)));
5481 ins_cost(3*MEMORY_REF_COST);
5482
5483 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5484 "TWI $dst\n\t"
5485 "ISYNC" %}
5486 size(12);
5487 ins_encode %{
5488 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5489 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5490 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5491 __ twi_0($dst$$Register);
5492 __ isync();
5493 %}
5494 ins_pipe(pipe_class_memory);
5495 %}
5496
5497 // Load Long - aligned
5498 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5499 match(Set dst (LoadL mem));
5500 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5501 ins_cost(MEMORY_REF_COST);
5502
5503 format %{ "LD $dst, $mem \t// long" %}
5504 size(4);
5505 ins_encode( enc_ld(dst, mem) );
5506 ins_pipe(pipe_class_memory);
5507 %}
5508
5509 // Load Long - aligned acquire.
5510 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5511 match(Set dst (LoadL mem));
5512 ins_cost(3*MEMORY_REF_COST);
5513
5514 format %{ "LD $dst, $mem \t// long acquire\n\t"
5515 "TWI $dst\n\t"
5516 "ISYNC" %}
5517 size(12);
5518 ins_encode( enc_ld_ac(dst, mem) );
5519 ins_pipe(pipe_class_memory);
5520 %}
5521
5522 // Load Long - UNaligned
5523 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5524 match(Set dst (LoadL_unaligned mem));
5525 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5526 ins_cost(MEMORY_REF_COST);
5527
5528 format %{ "LD $dst, $mem \t// unaligned long" %}
5529 size(4);
5530 ins_encode( enc_ld(dst, mem) );
5531 ins_pipe(pipe_class_memory);
5532 %}
5533
5534 // Load nodes for superwords
5535
5536 // Load Aligned Packed Byte
5537 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5538 predicate(n->as_LoadVector()->memory_size() == 8);
5539 match(Set dst (LoadVector mem));
5540 ins_cost(MEMORY_REF_COST);
5541
5542 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5543 size(4);
5544 ins_encode( enc_ld(dst, mem) );
5545 ins_pipe(pipe_class_memory);
5546 %}
5547
5548 // Load Range, range = array length (=jint)
5549 instruct loadRange(iRegIdst dst, memory mem) %{
5550 match(Set dst (LoadRange mem));
5551 ins_cost(MEMORY_REF_COST);
5552
5553 format %{ "LWZ $dst, $mem \t// range" %}
5554 size(4);
5555 ins_encode( enc_lwz(dst, mem) );
5556 ins_pipe(pipe_class_memory);
5557 %}
5558
5559 // Load Compressed Pointer
5560 instruct loadN(iRegNdst dst, memory mem) %{
5561 match(Set dst (LoadN mem));
5562 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5563 ins_cost(MEMORY_REF_COST);
5564
5565 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5566 size(4);
5567 ins_encode( enc_lwz(dst, mem) );
5568 ins_pipe(pipe_class_memory);
5569 %}
5570
5571 // Load Compressed Pointer acquire.
5572 instruct loadN_ac(iRegNdst dst, memory mem) %{
5573 match(Set dst (LoadN mem));
5574 ins_cost(3*MEMORY_REF_COST);
5575
5576 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5577 "TWI $dst\n\t"
5578 "ISYNC" %}
5579 size(12);
5580 ins_encode( enc_lwz_ac(dst, mem) );
5581 ins_pipe(pipe_class_memory);
5582 %}
5583
5584 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5585 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5586 match(Set dst (DecodeN (LoadN mem)));
5587 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5588 ins_cost(MEMORY_REF_COST);
5589
5590 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5591 size(4);
5592 ins_encode( enc_lwz(dst, mem) );
5593 ins_pipe(pipe_class_memory);
5594 %}
5595
5596 // Load Pointer
5597 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5598 match(Set dst (LoadP mem));
5599 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5600 ins_cost(MEMORY_REF_COST);
5601
5602 format %{ "LD $dst, $mem \t// ptr" %}
5603 size(4);
5604 ins_encode( enc_ld(dst, mem) );
5605 ins_pipe(pipe_class_memory);
5606 %}
5607
5608 // Load Pointer acquire.
5609 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5610 match(Set dst (LoadP mem));
5611 ins_cost(3*MEMORY_REF_COST);
5612
5613 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5614 "TWI $dst\n\t"
5615 "ISYNC" %}
5616 size(12);
5617 ins_encode( enc_ld_ac(dst, mem) );
5618 ins_pipe(pipe_class_memory);
5619 %}
5620
5621 // LoadP + CastP2L
5622 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5623 match(Set dst (CastP2X (LoadP mem)));
5624 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5625 ins_cost(MEMORY_REF_COST);
5626
5627 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5628 size(4);
5629 ins_encode( enc_ld(dst, mem) );
5630 ins_pipe(pipe_class_memory);
5631 %}
5632
5633 // Load compressed klass pointer.
5634 instruct loadNKlass(iRegNdst dst, memory mem) %{
5635 match(Set dst (LoadNKlass mem));
5636 ins_cost(MEMORY_REF_COST);
5637
5638 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5639 size(4);
5640 ins_encode( enc_lwz(dst, mem) );
5641 ins_pipe(pipe_class_memory);
5642 %}
5643
5644 // Load Klass Pointer
5645 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5646 match(Set dst (LoadKlass mem));
5647 ins_cost(MEMORY_REF_COST);
5648
5649 format %{ "LD $dst, $mem \t// klass ptr" %}
5650 size(4);
5651 ins_encode( enc_ld(dst, mem) );
5652 ins_pipe(pipe_class_memory);
5653 %}
5654
5655 // Load Float
5656 instruct loadF(regF dst, memory mem) %{
5657 match(Set dst (LoadF mem));
5658 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5659 ins_cost(MEMORY_REF_COST);
5660
5661 format %{ "LFS $dst, $mem" %}
5662 size(4);
5663 ins_encode %{
5664 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5665 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5666 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5667 %}
5668 ins_pipe(pipe_class_memory);
5669 %}
5670
5671 // Load Float acquire.
5672 instruct loadF_ac(regF dst, memory mem) %{
5673 match(Set dst (LoadF mem));
5674 ins_cost(3*MEMORY_REF_COST);
5675
5676 format %{ "LFS $dst, $mem \t// acquire\n\t"
5677 "FCMPU cr0, $dst, $dst\n\t"
5678 "BNE cr0, next\n"
5679 "next:\n\t"
5680 "ISYNC" %}
5681 size(16);
5682 ins_encode %{
5683 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5684 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5685 Label next;
5686 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5687 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5688 __ bne(CCR0, next);
5689 __ bind(next);
5690 __ isync();
5691 %}
5692 ins_pipe(pipe_class_memory);
5693 %}
5694
5695 // Load Double - aligned
5696 instruct loadD(regD dst, memory mem) %{
5697 match(Set dst (LoadD mem));
5698 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5699 ins_cost(MEMORY_REF_COST);
5700
5701 format %{ "LFD $dst, $mem" %}
5702 size(4);
5703 ins_encode( enc_lfd(dst, mem) );
5704 ins_pipe(pipe_class_memory);
5705 %}
5706
5707 // Load Double - aligned acquire.
5708 instruct loadD_ac(regD dst, memory mem) %{
5709 match(Set dst (LoadD mem));
5710 ins_cost(3*MEMORY_REF_COST);
5711
5712 format %{ "LFD $dst, $mem \t// acquire\n\t"
5713 "FCMPU cr0, $dst, $dst\n\t"
5714 "BNE cr0, next\n"
5715 "next:\n\t"
5716 "ISYNC" %}
5717 size(16);
5718 ins_encode %{
5719 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5720 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5721 Label next;
5722 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5723 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5724 __ bne(CCR0, next);
5725 __ bind(next);
5726 __ isync();
5727 %}
5728 ins_pipe(pipe_class_memory);
5729 %}
5730
5731 // Load Double - UNaligned
5732 instruct loadD_unaligned(regD dst, memory mem) %{
5733 match(Set dst (LoadD_unaligned mem));
5734 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5735 ins_cost(MEMORY_REF_COST);
5736
5737 format %{ "LFD $dst, $mem" %}
5738 size(4);
5739 ins_encode( enc_lfd(dst, mem) );
5740 ins_pipe(pipe_class_memory);
5741 %}
5742
5743 //----------Constants--------------------------------------------------------
5744
5745 // Load MachConstantTableBase: add hi offset to global toc.
5746 // TODO: Handle hidden register r29 in bundler!
5747 instruct loadToc_hi(iRegLdst dst) %{
5748 effect(DEF dst);
5749 ins_cost(DEFAULT_COST);
5750
5751 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5752 size(4);
5753 ins_encode %{
5754 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5755 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5756 %}
5757 ins_pipe(pipe_class_default);
5758 %}
5759
5760 // Load MachConstantTableBase: add lo offset to global toc.
5761 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5762 effect(DEF dst, USE src);
5763 ins_cost(DEFAULT_COST);
5764
5765 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5766 size(4);
5767 ins_encode %{
5768 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5769 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5770 %}
5771 ins_pipe(pipe_class_default);
5772 %}
5773
5774 // Load 16-bit integer constant 0xssss????
5775 instruct loadConI16(iRegIdst dst, immI16 src) %{
5776 match(Set dst src);
5777
5778 format %{ "LI $dst, $src" %}
5779 size(4);
5780 ins_encode %{
5781 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5782 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5783 %}
5784 ins_pipe(pipe_class_default);
5785 %}
5786
5787 // Load integer constant 0x????0000
5788 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5789 match(Set dst src);
5790 ins_cost(DEFAULT_COST);
5791
5792 format %{ "LIS $dst, $src.hi" %}
5793 size(4);
5794 ins_encode %{
5795 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5796 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5797 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5798 %}
5799 ins_pipe(pipe_class_default);
5800 %}
5801
5802 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5803 // and sign extended), this adds the low 16 bits.
5804 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5805 // no match-rule, false predicate
5806 effect(DEF dst, USE src1, USE src2);
5807 predicate(false);
5808
5809 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5810 size(4);
5811 ins_encode %{
5812 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5813 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5814 %}
5815 ins_pipe(pipe_class_default);
5816 %}
5817
5818 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5819 match(Set dst src);
5820 ins_cost(DEFAULT_COST*2);
5821
5822 expand %{
5823 // Would like to use $src$$constant.
5824 immI16 srcLo %{ _opnds[1]->constant() %}
5825 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5826 immIhi16 srcHi %{ _opnds[1]->constant() %}
5827 iRegIdst tmpI;
5828 loadConIhi16(tmpI, srcHi);
5829 loadConI32_lo16(dst, tmpI, srcLo);
5830 %}
5831 %}
5832
5833 // No constant pool entries required.
5834 instruct loadConL16(iRegLdst dst, immL16 src) %{
5835 match(Set dst src);
5836
5837 format %{ "LI $dst, $src \t// long" %}
5838 size(4);
5839 ins_encode %{
5840 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5841 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5842 %}
5843 ins_pipe(pipe_class_default);
5844 %}
5845
5846 // Load long constant 0xssssssss????0000
5847 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5848 match(Set dst src);
5849 ins_cost(DEFAULT_COST);
5850
5851 format %{ "LIS $dst, $src.hi \t// long" %}
5852 size(4);
5853 ins_encode %{
5854 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5855 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5856 %}
5857 ins_pipe(pipe_class_default);
5858 %}
5859
5860 // To load a 32 bit constant: merge lower 16 bits into already loaded
5861 // high 16 bits.
5862 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5863 // no match-rule, false predicate
5864 effect(DEF dst, USE src1, USE src2);
5865 predicate(false);
5866
5867 format %{ "ORI $dst, $src1, $src2.lo" %}
5868 size(4);
5869 ins_encode %{
5870 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5871 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5872 %}
5873 ins_pipe(pipe_class_default);
5874 %}
5875
5876 // Load 32-bit long constant
5877 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5878 match(Set dst src);
5879 ins_cost(DEFAULT_COST*2);
5880
5881 expand %{
5882 // Would like to use $src$$constant.
5883 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5884 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5885 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5886 iRegLdst tmpL;
5887 loadConL32hi16(tmpL, srcHi);
5888 loadConL32_lo16(dst, tmpL, srcLo);
5889 %}
5890 %}
5891
5892 // Load long constant 0x????000000000000.
5893 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5894 match(Set dst src);
5895 ins_cost(DEFAULT_COST);
5896
5897 expand %{
5898 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5899 immI shift32 %{ 32 %}
5900 iRegLdst tmpL;
5901 loadConL32hi16(tmpL, srcHi);
5902 lshiftL_regL_immI(dst, tmpL, shift32);
5903 %}
5904 %}
5905
5906 // Expand node for constant pool load: small offset.
5907 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5908 effect(DEF dst, USE src, USE toc);
5909 ins_cost(MEMORY_REF_COST);
5910
5911 ins_num_consts(1);
5912 // Needed so that CallDynamicJavaDirect can compute the address of this
5913 // instruction for relocation.
5914 ins_field_cbuf_insts_offset(int);
5915
5916 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5917 size(4);
5918 ins_encode( enc_load_long_constL(dst, src, toc) );
5919 ins_pipe(pipe_class_memory);
5920 %}
5921
5922 // Expand node for constant pool load: large offset.
5923 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5924 effect(DEF dst, USE src, USE toc);
5925 predicate(false);
5926
5927 ins_num_consts(1);
5928 ins_field_const_toc_offset(int);
5929 // Needed so that CallDynamicJavaDirect can compute the address of this
5930 // instruction for relocation.
5931 ins_field_cbuf_insts_offset(int);
5932
5933 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5934 size(4);
5935 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5936 ins_pipe(pipe_class_default);
5937 %}
5938
5939 // Expand node for constant pool load: large offset.
5940 // No constant pool entries required.
5941 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5942 effect(DEF dst, USE src, USE base);
5943 predicate(false);
5944
5945 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5946
5947 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5948 size(4);
5949 ins_encode %{
5950 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5951 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5952 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5953 %}
5954 ins_pipe(pipe_class_memory);
5955 %}
5956
5957 // Load long constant from constant table. Expand in case of
5958 // offset > 16 bit is needed.
5959 // Adlc adds toc node MachConstantTableBase.
5960 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5961 match(Set dst src);
5962 ins_cost(MEMORY_REF_COST);
5963
5964 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5965 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5966 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5967 %}
5968
5969 // Load NULL as compressed oop.
5970 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5971 match(Set dst src);
5972 ins_cost(DEFAULT_COST);
5973
5974 format %{ "LI $dst, $src \t// compressed ptr" %}
5975 size(4);
5976 ins_encode %{
5977 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5978 __ li($dst$$Register, 0);
5979 %}
5980 ins_pipe(pipe_class_default);
5981 %}
5982
5983 // Load hi part of compressed oop constant.
5984 instruct loadConN_hi(iRegNdst dst, immN src) %{
5985 effect(DEF dst, USE src);
5986 ins_cost(DEFAULT_COST);
5987
5988 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5989 size(4);
5990 ins_encode %{
5991 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5992 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5993 %}
5994 ins_pipe(pipe_class_default);
5995 %}
5996
5997 // Add lo part of compressed oop constant to already loaded hi part.
5998 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5999 effect(DEF dst, USE src1, USE src2);
6000 ins_cost(DEFAULT_COST);
6001
6002 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6003 size(4);
6004 ins_encode %{
6005 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6006 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6007 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6008 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6009 __ relocate(rspec, 1);
6010 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6011 %}
6012 ins_pipe(pipe_class_default);
6013 %}
6014
6015 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6016 // leaving the upper 32 bits with sign-extension bits.
6017 // This clears these bits: dst = src & 0xFFFFFFFF.
6018 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6019 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6020 effect(DEF dst, USE src);
6021 predicate(false);
6022
6023 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6024 size(4);
6025 ins_encode %{
6026 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6027 __ clrldi($dst$$Register, $src$$Register, 0x20);
6028 %}
6029 ins_pipe(pipe_class_default);
6030 %}
6031
6032 // Optimize DecodeN for disjoint base.
6033 // Load base of compressed oops into a register
6034 instruct loadBase(iRegLdst dst) %{
6035 effect(DEF dst);
6036
6037 format %{ "MR $dst, r30_heapbase" %}
6038 size(4);
6039 ins_encode %{
6040 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6041 __ mr($dst$$Register, R30);
6042 %}
6043 ins_pipe(pipe_class_default);
6044 %}
6045
6046 // Loading ConN must be postalloc expanded so that edges between
6047 // the nodes are safe. They may not interfere with a safepoint.
6048 // GL TODO: This needs three instructions: better put this into the constant pool.
6049 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6050 match(Set dst src);
6051 ins_cost(DEFAULT_COST*2);
6052
6053 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6054 postalloc_expand %{
6055 MachNode *m1 = new loadConN_hiNode();
6056 MachNode *m2 = new loadConN_loNode();
6057 MachNode *m3 = new clearMs32bNode();
6058 m1->add_req(NULL);
6059 m2->add_req(NULL, m1);
6060 m3->add_req(NULL, m2);
6061 m1->_opnds[0] = op_dst;
6062 m1->_opnds[1] = op_src;
6063 m2->_opnds[0] = op_dst;
6064 m2->_opnds[1] = op_dst;
6065 m2->_opnds[2] = op_src;
6066 m3->_opnds[0] = op_dst;
6067 m3->_opnds[1] = op_dst;
6068 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6069 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6070 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6071 nodes->push(m1);
6072 nodes->push(m2);
6073 nodes->push(m3);
6074 %}
6075 %}
6076
6077 // We have seen a safepoint between the hi and lo parts, and this node was handled
6078 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6079 // not a narrow oop.
6080 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6081 match(Set dst src);
6082 effect(DEF dst, USE src);
6083 ins_cost(DEFAULT_COST);
6084
6085 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6086 size(4);
6087 ins_encode %{
6088 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6089 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6090 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6091 %}
6092 ins_pipe(pipe_class_default);
6093 %}
6094
6095 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6096 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6097 match(Set dst src1);
6098 effect(TEMP src2);
6099 ins_cost(DEFAULT_COST);
6100
6101 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6102 size(4);
6103 ins_encode %{
6104 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6105 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6106 %}
6107 ins_pipe(pipe_class_default);
6108 %}
6109
6110 // This needs a match rule so that build_oop_map knows this is
6111 // not a narrow oop.
6112 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6113 match(Set dst src1);
6114 effect(TEMP src2);
6115 ins_cost(DEFAULT_COST);
6116
6117 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6118 size(4);
6119 ins_encode %{
6120 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6121 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6122 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6123 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6124 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6125
6126 __ relocate(rspec, 1);
6127 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6128 %}
6129 ins_pipe(pipe_class_default);
6130 %}
6131
6132 // Loading ConNKlass must be postalloc expanded so that edges between
6133 // the nodes are safe. They may not interfere with a safepoint.
6134 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6135 match(Set dst src);
6136 ins_cost(DEFAULT_COST*2);
6137
6138 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6139 postalloc_expand %{
6140 // Load high bits into register. Sign extended.
6141 MachNode *m1 = new loadConNKlass_hiNode();
6142 m1->add_req(NULL);
6143 m1->_opnds[0] = op_dst;
6144 m1->_opnds[1] = op_src;
6145 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6146 nodes->push(m1);
6147
6148 MachNode *m2 = m1;
6149 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6150 // Value might be 1-extended. Mask out these bits.
6151 m2 = new loadConNKlass_maskNode();
6152 m2->add_req(NULL, m1);
6153 m2->_opnds[0] = op_dst;
6154 m2->_opnds[1] = op_src;
6155 m2->_opnds[2] = op_dst;
6156 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6157 nodes->push(m2);
6158 }
6159
6160 MachNode *m3 = new loadConNKlass_loNode();
6161 m3->add_req(NULL, m2);
6162 m3->_opnds[0] = op_dst;
6163 m3->_opnds[1] = op_src;
6164 m3->_opnds[2] = op_dst;
6165 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6166 nodes->push(m3);
6167 %}
6168 %}
6169
6170 // 0x1 is used in object initialization (initial object header).
6171 // No constant pool entries required.
6172 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6173 match(Set dst src);
6174
6175 format %{ "LI $dst, $src \t// ptr" %}
6176 size(4);
6177 ins_encode %{
6178 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6179 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6180 %}
6181 ins_pipe(pipe_class_default);
6182 %}
6183
6184 // Expand node for constant pool load: small offset.
6185 // The match rule is needed to generate the correct bottom_type(),
6186 // however this node should never match. The use of predicate is not
6187 // possible since ADLC forbids predicates for chain rules. The higher
6188 // costs do not prevent matching in this case. For that reason the
6189 // operand immP_NM with predicate(false) is used.
6190 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6191 match(Set dst src);
6192 effect(TEMP toc);
6193
6194 ins_num_consts(1);
6195
6196 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6197 size(4);
6198 ins_encode( enc_load_long_constP(dst, src, toc) );
6199 ins_pipe(pipe_class_memory);
6200 %}
6201
6202 // Expand node for constant pool load: large offset.
6203 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6204 effect(DEF dst, USE src, USE toc);
6205 predicate(false);
6206
6207 ins_num_consts(1);
6208 ins_field_const_toc_offset(int);
6209
6210 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6211 size(4);
6212 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6213 ins_pipe(pipe_class_default);
6214 %}
6215
6216 // Expand node for constant pool load: large offset.
6217 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6218 match(Set dst src);
6219 effect(TEMP base);
6220
6221 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6222
6223 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6224 size(4);
6225 ins_encode %{
6226 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6227 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6228 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6229 %}
6230 ins_pipe(pipe_class_memory);
6231 %}
6232
6233 // Load pointer constant from constant table. Expand in case an
6234 // offset > 16 bit is needed.
6235 // Adlc adds toc node MachConstantTableBase.
6236 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6237 match(Set dst src);
6238 ins_cost(MEMORY_REF_COST);
6239
6240 // This rule does not use "expand" because then
6241 // the result type is not known to be an Oop. An ADLC
6242 // enhancement will be needed to make that work - not worth it!
6243
6244 // If this instruction rematerializes, it prolongs the live range
6245 // of the toc node, causing illegal graphs.
6246 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6247 ins_cannot_rematerialize(true);
6248
6249 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6250 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6251 %}
6252
6253 // Expand node for constant pool load: small offset.
6254 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6255 effect(DEF dst, USE src, USE toc);
6256 ins_cost(MEMORY_REF_COST);
6257
6258 ins_num_consts(1);
6259
6260 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6261 size(4);
6262 ins_encode %{
6263 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6264 address float_address = __ float_constant($src$$constant);
6265 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6266 %}
6267 ins_pipe(pipe_class_memory);
6268 %}
6269
6270 // Expand node for constant pool load: large offset.
6271 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6272 effect(DEF dst, USE src, USE toc);
6273 ins_cost(MEMORY_REF_COST);
6274
6275 ins_num_consts(1);
6276
6277 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6278 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6279 "ADDIS $toc, $toc, -offset_hi"%}
6280 size(12);
6281 ins_encode %{
6282 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6283 FloatRegister Rdst = $dst$$FloatRegister;
6284 Register Rtoc = $toc$$Register;
6285 address float_address = __ float_constant($src$$constant);
6286 int offset = __ offset_to_method_toc(float_address);
6287 int hi = (offset + (1<<15))>>16;
6288 int lo = offset - hi * (1<<16);
6289
6290 __ addis(Rtoc, Rtoc, hi);
6291 __ lfs(Rdst, lo, Rtoc);
6292 __ addis(Rtoc, Rtoc, -hi);
6293 %}
6294 ins_pipe(pipe_class_memory);
6295 %}
6296
6297 // Adlc adds toc node MachConstantTableBase.
6298 instruct loadConF_Ex(regF dst, immF src) %{
6299 match(Set dst src);
6300 ins_cost(MEMORY_REF_COST);
6301
6302 // See loadConP.
6303 ins_cannot_rematerialize(true);
6304
6305 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6306 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6307 %}
6308
6309 // Expand node for constant pool load: small offset.
6310 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6311 effect(DEF dst, USE src, USE toc);
6312 ins_cost(MEMORY_REF_COST);
6313
6314 ins_num_consts(1);
6315
6316 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6317 size(4);
6318 ins_encode %{
6319 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6320 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6321 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6322 %}
6323 ins_pipe(pipe_class_memory);
6324 %}
6325
6326 // Expand node for constant pool load: large offset.
6327 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6328 effect(DEF dst, USE src, USE toc);
6329 ins_cost(MEMORY_REF_COST);
6330
6331 ins_num_consts(1);
6332
6333 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6334 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6335 "ADDIS $toc, $toc, -offset_hi" %}
6336 size(12);
6337 ins_encode %{
6338 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6339 FloatRegister Rdst = $dst$$FloatRegister;
6340 Register Rtoc = $toc$$Register;
6341 address float_address = __ double_constant($src$$constant);
6342 int offset = __ offset_to_method_toc(float_address);
6343 int hi = (offset + (1<<15))>>16;
6344 int lo = offset - hi * (1<<16);
6345
6346 __ addis(Rtoc, Rtoc, hi);
6347 __ lfd(Rdst, lo, Rtoc);
6348 __ addis(Rtoc, Rtoc, -hi);
6349 %}
6350 ins_pipe(pipe_class_memory);
6351 %}
6352
6353 // Adlc adds toc node MachConstantTableBase.
6354 instruct loadConD_Ex(regD dst, immD src) %{
6355 match(Set dst src);
6356 ins_cost(MEMORY_REF_COST);
6357
6358 // See loadConP.
6359 ins_cannot_rematerialize(true);
6360
6361 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6362 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6363 %}
6364
6365 // Prefetch instructions.
6366 // Must be safe to execute with invalid address (cannot fault).
6367
6368 // Special prefetch versions which use the dcbz instruction.
6369 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6370 match(PrefetchAllocation (AddP mem src));
6371 predicate(AllocatePrefetchStyle == 3);
6372 ins_cost(MEMORY_REF_COST);
6373
6374 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6375 size(4);
6376 ins_encode %{
6377 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6378 __ dcbz($src$$Register, $mem$$base$$Register);
6379 %}
6380 ins_pipe(pipe_class_memory);
6381 %}
6382
6383 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6384 match(PrefetchAllocation mem);
6385 predicate(AllocatePrefetchStyle == 3);
6386 ins_cost(MEMORY_REF_COST);
6387
6388 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6389 size(4);
6390 ins_encode %{
6391 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6392 __ dcbz($mem$$base$$Register);
6393 %}
6394 ins_pipe(pipe_class_memory);
6395 %}
6396
6397 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6398 match(PrefetchAllocation (AddP mem src));
6399 predicate(AllocatePrefetchStyle != 3);
6400 ins_cost(MEMORY_REF_COST);
6401
6402 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6403 size(4);
6404 ins_encode %{
6405 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6406 __ dcbtst($src$$Register, $mem$$base$$Register);
6407 %}
6408 ins_pipe(pipe_class_memory);
6409 %}
6410
6411 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6412 match(PrefetchAllocation mem);
6413 predicate(AllocatePrefetchStyle != 3);
6414 ins_cost(MEMORY_REF_COST);
6415
6416 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6417 size(4);
6418 ins_encode %{
6419 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6420 __ dcbtst($mem$$base$$Register);
6421 %}
6422 ins_pipe(pipe_class_memory);
6423 %}
6424
6425 //----------Store Instructions-------------------------------------------------
6426
6427 // Store Byte
6428 instruct storeB(memory mem, iRegIsrc src) %{
6429 match(Set mem (StoreB mem src));
6430 ins_cost(MEMORY_REF_COST);
6431
6432 format %{ "STB $src, $mem \t// byte" %}
6433 size(4);
6434 ins_encode %{
6435 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6436 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6437 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6438 %}
6439 ins_pipe(pipe_class_memory);
6440 %}
6441
6442 // Store Char/Short
6443 instruct storeC(memory mem, iRegIsrc src) %{
6444 match(Set mem (StoreC mem src));
6445 ins_cost(MEMORY_REF_COST);
6446
6447 format %{ "STH $src, $mem \t// short" %}
6448 size(4);
6449 ins_encode %{
6450 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6451 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6452 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6453 %}
6454 ins_pipe(pipe_class_memory);
6455 %}
6456
6457 // Store Integer
6458 instruct storeI(memory mem, iRegIsrc src) %{
6459 match(Set mem (StoreI mem src));
6460 ins_cost(MEMORY_REF_COST);
6461
6462 format %{ "STW $src, $mem" %}
6463 size(4);
6464 ins_encode( enc_stw(src, mem) );
6465 ins_pipe(pipe_class_memory);
6466 %}
6467
6468 // ConvL2I + StoreI.
6469 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6470 match(Set mem (StoreI mem (ConvL2I src)));
6471 ins_cost(MEMORY_REF_COST);
6472
6473 format %{ "STW l2i($src), $mem" %}
6474 size(4);
6475 ins_encode( enc_stw(src, mem) );
6476 ins_pipe(pipe_class_memory);
6477 %}
6478
6479 // Store Long
6480 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6481 match(Set mem (StoreL mem src));
6482 ins_cost(MEMORY_REF_COST);
6483
6484 format %{ "STD $src, $mem \t// long" %}
6485 size(4);
6486 ins_encode( enc_std(src, mem) );
6487 ins_pipe(pipe_class_memory);
6488 %}
6489
6490 // Store super word nodes.
6491
6492 // Store Aligned Packed Byte long register to memory
6493 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6494 predicate(n->as_StoreVector()->memory_size() == 8);
6495 match(Set mem (StoreVector mem src));
6496 ins_cost(MEMORY_REF_COST);
6497
6498 format %{ "STD $mem, $src \t// packed8B" %}
6499 size(4);
6500 ins_encode( enc_std(src, mem) );
6501 ins_pipe(pipe_class_memory);
6502 %}
6503
6504 // Store Compressed Oop
6505 instruct storeN(memory dst, iRegN_P2N src) %{
6506 match(Set dst (StoreN dst src));
6507 ins_cost(MEMORY_REF_COST);
6508
6509 format %{ "STW $src, $dst \t// compressed oop" %}
6510 size(4);
6511 ins_encode( enc_stw(src, dst) );
6512 ins_pipe(pipe_class_memory);
6513 %}
6514
6515 // Store Compressed KLass
6516 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6517 match(Set dst (StoreNKlass dst src));
6518 ins_cost(MEMORY_REF_COST);
6519
6520 format %{ "STW $src, $dst \t// compressed klass" %}
6521 size(4);
6522 ins_encode( enc_stw(src, dst) );
6523 ins_pipe(pipe_class_memory);
6524 %}
6525
6526 // Store Pointer
6527 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6528 match(Set dst (StoreP dst src));
6529 ins_cost(MEMORY_REF_COST);
6530
6531 format %{ "STD $src, $dst \t// ptr" %}
6532 size(4);
6533 ins_encode( enc_std(src, dst) );
6534 ins_pipe(pipe_class_memory);
6535 %}
6536
6537 // Store Float
6538 instruct storeF(memory mem, regF src) %{
6539 match(Set mem (StoreF mem src));
6540 ins_cost(MEMORY_REF_COST);
6541
6542 format %{ "STFS $src, $mem" %}
6543 size(4);
6544 ins_encode( enc_stfs(src, mem) );
6545 ins_pipe(pipe_class_memory);
6546 %}
6547
6548 // Store Double
6549 instruct storeD(memory mem, regD src) %{
6550 match(Set mem (StoreD mem src));
6551 ins_cost(MEMORY_REF_COST);
6552
6553 format %{ "STFD $src, $mem" %}
6554 size(4);
6555 ins_encode( enc_stfd(src, mem) );
6556 ins_pipe(pipe_class_memory);
6557 %}
6558
6559 //----------Store Instructions With Zeros--------------------------------------
6560
6561 // Card-mark for CMS garbage collection.
6562 // This cardmark does an optimization so that it must not always
6563 // do a releasing store. For this, it gets the address of
6564 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6565 // (Using releaseFieldAddr in the match rule is a hack.)
6566 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6567 match(Set mem (StoreCM mem releaseFieldAddr));
6568 predicate(false);
6569 ins_cost(MEMORY_REF_COST);
6570
6571 // See loadConP.
6572 ins_cannot_rematerialize(true);
6573
6574 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6575 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6576 ins_pipe(pipe_class_memory);
6577 %}
6578
6579 // Card-mark for CMS garbage collection.
6580 // This cardmark does an optimization so that it must not always
6581 // do a releasing store. For this, it needs the constant address of
6582 // CMSCollectorCardTableModRefBSExt::_requires_release.
6583 // This constant address is split off here by expand so we can use
6584 // adlc / matcher functionality to load it from the constant section.
6585 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6586 match(Set mem (StoreCM mem zero));
6587 predicate(UseConcMarkSweepGC);
6588
6589 expand %{
6590 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6591 iRegLdst releaseFieldAddress;
6592 loadConL_Ex(releaseFieldAddress, baseImm);
6593 storeCM_CMS(mem, releaseFieldAddress);
6594 %}
6595 %}
6596
6597 instruct storeCM_G1(memory mem, immI_0 zero) %{
6598 match(Set mem (StoreCM mem zero));
6599 predicate(UseG1GC);
6600 ins_cost(MEMORY_REF_COST);
6601
6602 ins_cannot_rematerialize(true);
6603
6604 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6605 size(8);
6606 ins_encode %{
6607 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6608 __ li(R0, 0);
6609 //__ release(); // G1: oops are allowed to get visible after dirty marking
6610 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6611 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6612 %}
6613 ins_pipe(pipe_class_memory);
6614 %}
6615
6616 // Convert oop pointer into compressed form.
6617
6618 // Nodes for postalloc expand.
6619
6620 // Shift node for expand.
6621 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6622 // The match rule is needed to make it a 'MachTypeNode'!
6623 match(Set dst (EncodeP src));
6624 predicate(false);
6625
6626 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6627 size(4);
6628 ins_encode %{
6629 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6630 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6631 %}
6632 ins_pipe(pipe_class_default);
6633 %}
6634
6635 // Add node for expand.
6636 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6637 // The match rule is needed to make it a 'MachTypeNode'!
6638 match(Set dst (EncodeP src));
6639 predicate(false);
6640
6641 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6642 size(4);
6643 ins_encode %{
6644 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6645 __ subf($dst$$Register, R30, $src$$Register);
6646 %}
6647 ins_pipe(pipe_class_default);
6648 %}
6649
6650 // Conditional sub base.
6651 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6652 // The match rule is needed to make it a 'MachTypeNode'!
6653 match(Set dst (EncodeP (Binary crx src1)));
6654 predicate(false);
6655
6656 ins_variable_size_depending_on_alignment(true);
6657
6658 format %{ "BEQ $crx, done\n\t"
6659 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6660 "done:" %}
6661 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6662 ins_encode %{
6663 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6664 Label done;
6665 __ beq($crx$$CondRegister, done);
6666 __ subf($dst$$Register, R30, $src1$$Register);
6667 // TODO PPC port __ endgroup_if_needed(_size == 12);
6668 __ bind(done);
6669 %}
6670 ins_pipe(pipe_class_default);
6671 %}
6672
6673 // Power 7 can use isel instruction
6674 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6675 // The match rule is needed to make it a 'MachTypeNode'!
6676 match(Set dst (EncodeP (Binary crx src1)));
6677 predicate(false);
6678
6679 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6680 size(4);
6681 ins_encode %{
6682 // This is a Power7 instruction for which no machine description exists.
6683 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6684 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6685 %}
6686 ins_pipe(pipe_class_default);
6687 %}
6688
6689 // Disjoint narrow oop base.
6690 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6691 match(Set dst (EncodeP src));
6692 predicate(Universe::narrow_oop_base_disjoint());
6693
6694 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6695 size(4);
6696 ins_encode %{
6697 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6698 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6699 %}
6700 ins_pipe(pipe_class_default);
6701 %}
6702
6703 // shift != 0, base != 0
6704 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6705 match(Set dst (EncodeP src));
6706 effect(TEMP crx);
6707 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6708 Universe::narrow_oop_shift() != 0 &&
6709 Universe::narrow_oop_base_overlaps());
6710
6711 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6712 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6713 %}
6714
6715 // shift != 0, base != 0
6716 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6717 match(Set dst (EncodeP src));
6718 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6719 Universe::narrow_oop_shift() != 0 &&
6720 Universe::narrow_oop_base_overlaps());
6721
6722 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6723 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6724 %}
6725
6726 // shift != 0, base == 0
6727 // TODO: This is the same as encodeP_shift. Merge!
6728 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6729 match(Set dst (EncodeP src));
6730 predicate(Universe::narrow_oop_shift() != 0 &&
6731 Universe::narrow_oop_base() ==0);
6732
6733 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6734 size(4);
6735 ins_encode %{
6736 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6737 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6738 %}
6739 ins_pipe(pipe_class_default);
6740 %}
6741
6742 // Compressed OOPs with narrow_oop_shift == 0.
6743 // shift == 0, base == 0
6744 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6745 match(Set dst (EncodeP src));
6746 predicate(Universe::narrow_oop_shift() == 0);
6747
6748 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6749 // variable size, 0 or 4.
6750 ins_encode %{
6751 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6752 __ mr_if_needed($dst$$Register, $src$$Register);
6753 %}
6754 ins_pipe(pipe_class_default);
6755 %}
6756
6757 // Decode nodes.
6758
6759 // Shift node for expand.
6760 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6761 // The match rule is needed to make it a 'MachTypeNode'!
6762 match(Set dst (DecodeN src));
6763 predicate(false);
6764
6765 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6766 size(4);
6767 ins_encode %{
6768 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6769 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6770 %}
6771 ins_pipe(pipe_class_default);
6772 %}
6773
6774 // Add node for expand.
6775 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6776 // The match rule is needed to make it a 'MachTypeNode'!
6777 match(Set dst (DecodeN src));
6778 predicate(false);
6779
6780 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6781 size(4);
6782 ins_encode %{
6783 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6784 __ add($dst$$Register, $src$$Register, R30);
6785 %}
6786 ins_pipe(pipe_class_default);
6787 %}
6788
6789 // conditianal add base for expand
6790 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6791 // The match rule is needed to make it a 'MachTypeNode'!
6792 // NOTICE that the rule is nonsense - we just have to make sure that:
6793 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6794 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6795 match(Set dst (DecodeN (Binary crx src1)));
6796 predicate(false);
6797
6798 ins_variable_size_depending_on_alignment(true);
6799
6800 format %{ "BEQ $crx, done\n\t"
6801 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6802 "done:" %}
6803 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6804 ins_encode %{
6805 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6806 Label done;
6807 __ beq($crx$$CondRegister, done);
6808 __ add($dst$$Register, $src1$$Register, R30);
6809 // TODO PPC port __ endgroup_if_needed(_size == 12);
6810 __ bind(done);
6811 %}
6812 ins_pipe(pipe_class_default);
6813 %}
6814
6815 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6816 // The match rule is needed to make it a 'MachTypeNode'!
6817 // NOTICE that the rule is nonsense - we just have to make sure that:
6818 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6819 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6820 match(Set dst (DecodeN (Binary crx src1)));
6821 predicate(false);
6822
6823 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6824 size(4);
6825 ins_encode %{
6826 // This is a Power7 instruction for which no machine description exists.
6827 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6828 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6829 %}
6830 ins_pipe(pipe_class_default);
6831 %}
6832
6833 // shift != 0, base != 0
6834 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6835 match(Set dst (DecodeN src));
6836 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6837 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6838 Universe::narrow_oop_shift() != 0 &&
6839 Universe::narrow_oop_base() != 0);
6840 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6841 effect(TEMP crx);
6842
6843 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6844 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6845 %}
6846
6847 // shift != 0, base == 0
6848 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6849 match(Set dst (DecodeN src));
6850 predicate(Universe::narrow_oop_shift() != 0 &&
6851 Universe::narrow_oop_base() == 0);
6852
6853 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6854 size(4);
6855 ins_encode %{
6856 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6857 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6858 %}
6859 ins_pipe(pipe_class_default);
6860 %}
6861
6862 // Optimize DecodeN for disjoint base.
6863 // Shift narrow oop and or it into register that already contains the heap base.
6864 // Base == dst must hold, and is assured by construction in postaloc_expand.
6865 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6866 match(Set dst (DecodeN src));
6867 effect(TEMP base);
6868 predicate(false);
6869
6870 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6871 size(4);
6872 ins_encode %{
6873 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6874 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6875 %}
6876 ins_pipe(pipe_class_default);
6877 %}
6878
6879 // Optimize DecodeN for disjoint base.
6880 // This node requires only one cycle on the critical path.
6881 // We must postalloc_expand as we can not express use_def effects where
6882 // the used register is L and the def'ed register P.
6883 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6884 match(Set dst (DecodeN src));
6885 effect(TEMP_DEF dst);
6886 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6887 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6888 Universe::narrow_oop_base_disjoint());
6889 ins_cost(DEFAULT_COST);
6890
6891 format %{ "MOV $dst, R30 \t\n"
6892 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6893 postalloc_expand %{
6894 loadBaseNode *n1 = new loadBaseNode();
6895 n1->add_req(NULL);
6896 n1->_opnds[0] = op_dst;
6897
6898 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6899 n2->add_req(n_region, n_src, n1);
6900 n2->_opnds[0] = op_dst;
6901 n2->_opnds[1] = op_src;
6902 n2->_opnds[2] = op_dst;
6903 n2->_bottom_type = _bottom_type;
6904
6905 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6906 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6907
6908 nodes->push(n1);
6909 nodes->push(n2);
6910 %}
6911 %}
6912
6913 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6914 match(Set dst (DecodeN src));
6915 effect(TEMP_DEF dst, TEMP crx);
6916 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6917 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6918 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6919 ins_cost(3 * DEFAULT_COST);
6920
6921 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %}
6922 postalloc_expand %{
6923 loadBaseNode *n1 = new loadBaseNode();
6924 n1->add_req(NULL);
6925 n1->_opnds[0] = op_dst;
6926
6927 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
6928 n_compare->add_req(n_region, n_src);
6929 n_compare->_opnds[0] = op_crx;
6930 n_compare->_opnds[1] = op_src;
6931 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6932
6933 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6934 n2->add_req(n_region, n_src, n1);
6935 n2->_opnds[0] = op_dst;
6936 n2->_opnds[1] = op_src;
6937 n2->_opnds[2] = op_dst;
6938 n2->_bottom_type = _bottom_type;
6939
6940 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6941 n_cond_set->add_req(n_region, n_compare, n2);
6942 n_cond_set->_opnds[0] = op_dst;
6943 n_cond_set->_opnds[1] = op_crx;
6944 n_cond_set->_opnds[2] = op_dst;
6945 n_cond_set->_bottom_type = _bottom_type;
6946
6947 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6948 ra_->set_oop(n_cond_set, true);
6949
6950 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6951 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6952 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6953 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6954
6955 nodes->push(n1);
6956 nodes->push(n_compare);
6957 nodes->push(n2);
6958 nodes->push(n_cond_set);
6959 %}
6960 %}
6961
6962 // src != 0, shift != 0, base != 0
6963 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6964 match(Set dst (DecodeN src));
6965 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6966 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6967 Universe::narrow_oop_shift() != 0 &&
6968 Universe::narrow_oop_base() != 0);
6969 ins_cost(2 * DEFAULT_COST);
6970
6971 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6972 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6973 %}
6974
6975 // Compressed OOPs with narrow_oop_shift == 0.
6976 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6977 match(Set dst (DecodeN src));
6978 predicate(Universe::narrow_oop_shift() == 0);
6979 ins_cost(DEFAULT_COST);
6980
6981 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6982 // variable size, 0 or 4.
6983 ins_encode %{
6984 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6985 __ mr_if_needed($dst$$Register, $src$$Register);
6986 %}
6987 ins_pipe(pipe_class_default);
6988 %}
6989
6990 // Convert compressed oop into int for vectors alignment masking.
6991 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6992 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6993 predicate(Universe::narrow_oop_shift() == 0);
6994 ins_cost(DEFAULT_COST);
6995
6996 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6997 // variable size, 0 or 4.
6998 ins_encode %{
6999 // TODO: PPC port $archOpcode(ppc64Opcode_or);
7000 __ mr_if_needed($dst$$Register, $src$$Register);
7001 %}
7002 ins_pipe(pipe_class_default);
7003 %}
7004
7005 // Convert klass pointer into compressed form.
7006
7007 // Nodes for postalloc expand.
7008
7009 // Shift node for expand.
7010 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
7011 // The match rule is needed to make it a 'MachTypeNode'!
7012 match(Set dst (EncodePKlass src));
7013 predicate(false);
7014
7015 format %{ "SRDI $dst, $src, 3 \t// encode" %}
7016 size(4);
7017 ins_encode %{
7018 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7019 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7020 %}
7021 ins_pipe(pipe_class_default);
7022 %}
7023
7024 // Add node for expand.
7025 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7026 // The match rule is needed to make it a 'MachTypeNode'!
7027 match(Set dst (EncodePKlass (Binary base src)));
7028 predicate(false);
7029
7030 format %{ "SUB $dst, $base, $src \t// encode" %}
7031 size(4);
7032 ins_encode %{
7033 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7034 __ subf($dst$$Register, $base$$Register, $src$$Register);
7035 %}
7036 ins_pipe(pipe_class_default);
7037 %}
7038
7039 // Disjoint narrow oop base.
7040 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7041 match(Set dst (EncodePKlass src));
7042 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7043
7044 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
7045 size(4);
7046 ins_encode %{
7047 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7048 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7049 %}
7050 ins_pipe(pipe_class_default);
7051 %}
7052
7053 // shift != 0, base != 0
7054 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7055 match(Set dst (EncodePKlass (Binary base src)));
7056 predicate(false);
7057
7058 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7059 postalloc_expand %{
7060 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7061 n1->add_req(n_region, n_base, n_src);
7062 n1->_opnds[0] = op_dst;
7063 n1->_opnds[1] = op_base;
7064 n1->_opnds[2] = op_src;
7065 n1->_bottom_type = _bottom_type;
7066
7067 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7068 n2->add_req(n_region, n1);
7069 n2->_opnds[0] = op_dst;
7070 n2->_opnds[1] = op_dst;
7071 n2->_bottom_type = _bottom_type;
7072 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7073 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7074
7075 nodes->push(n1);
7076 nodes->push(n2);
7077 %}
7078 %}
7079
7080 // shift != 0, base != 0
7081 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7082 match(Set dst (EncodePKlass src));
7083 //predicate(Universe::narrow_klass_shift() != 0 &&
7084 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7085
7086 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7087 ins_cost(DEFAULT_COST*2); // Don't count constant.
7088 expand %{
7089 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7090 iRegLdst base;
7091 loadConL_Ex(base, baseImm);
7092 encodePKlass_not_null_Ex(dst, base, src);
7093 %}
7094 %}
7095
7096 // Decode nodes.
7097
7098 // Shift node for expand.
7099 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7100 // The match rule is needed to make it a 'MachTypeNode'!
7101 match(Set dst (DecodeNKlass src));
7102 predicate(false);
7103
7104 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7105 size(4);
7106 ins_encode %{
7107 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7108 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7109 %}
7110 ins_pipe(pipe_class_default);
7111 %}
7112
7113 // Add node for expand.
7114
7115 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7116 // The match rule is needed to make it a 'MachTypeNode'!
7117 match(Set dst (DecodeNKlass (Binary base src)));
7118 predicate(false);
7119
7120 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7121 size(4);
7122 ins_encode %{
7123 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7124 __ add($dst$$Register, $base$$Register, $src$$Register);
7125 %}
7126 ins_pipe(pipe_class_default);
7127 %}
7128
7129 // src != 0, shift != 0, base != 0
7130 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7131 match(Set dst (DecodeNKlass (Binary base src)));
7132 //effect(kill src); // We need a register for the immediate result after shifting.
7133 predicate(false);
7134
7135 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7136 postalloc_expand %{
7137 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7138 n1->add_req(n_region, n_base, n_src);
7139 n1->_opnds[0] = op_dst;
7140 n1->_opnds[1] = op_base;
7141 n1->_opnds[2] = op_src;
7142 n1->_bottom_type = _bottom_type;
7143
7144 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7145 n2->add_req(n_region, n1);
7146 n2->_opnds[0] = op_dst;
7147 n2->_opnds[1] = op_dst;
7148 n2->_bottom_type = _bottom_type;
7149
7150 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7151 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7152
7153 nodes->push(n1);
7154 nodes->push(n2);
7155 %}
7156 %}
7157
7158 // src != 0, shift != 0, base != 0
7159 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7160 match(Set dst (DecodeNKlass src));
7161 // predicate(Universe::narrow_klass_shift() != 0 &&
7162 // Universe::narrow_klass_base() != 0);
7163
7164 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7165
7166 ins_cost(DEFAULT_COST*2); // Don't count constant.
7167 expand %{
7168 // We add first, then we shift. Like this, we can get along with one register less.
7169 // But we have to load the base pre-shifted.
7170 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7171 iRegLdst base;
7172 loadConL_Ex(base, baseImm);
7173 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7174 %}
7175 %}
7176
7177 //----------MemBar Instructions-----------------------------------------------
7178 // Memory barrier flavors
7179
7180 instruct membar_acquire() %{
7181 match(LoadFence);
7182 ins_cost(4*MEMORY_REF_COST);
7183
7184 format %{ "MEMBAR-acquire" %}
7185 size(4);
7186 ins_encode %{
7187 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7188 __ acquire();
7189 %}
7190 ins_pipe(pipe_class_default);
7191 %}
7192
7193 instruct unnecessary_membar_acquire() %{
7194 match(MemBarAcquire);
7195 ins_cost(0);
7196
7197 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7198 size(0);
7199 ins_encode( /*empty*/ );
7200 ins_pipe(pipe_class_default);
7201 %}
7202
7203 instruct membar_acquire_lock() %{
7204 match(MemBarAcquireLock);
7205 ins_cost(0);
7206
7207 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7208 size(0);
7209 ins_encode( /*empty*/ );
7210 ins_pipe(pipe_class_default);
7211 %}
7212
7213 instruct membar_release() %{
7214 match(MemBarRelease);
7215 match(StoreFence);
7216 ins_cost(4*MEMORY_REF_COST);
7217
7218 format %{ "MEMBAR-release" %}
7219 size(4);
7220 ins_encode %{
7221 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7222 __ release();
7223 %}
7224 ins_pipe(pipe_class_default);
7225 %}
7226
7227 instruct membar_storestore() %{
7228 match(MemBarStoreStore);
7229 ins_cost(4*MEMORY_REF_COST);
7230
7231 format %{ "MEMBAR-store-store" %}
7232 size(4);
7233 ins_encode %{
7234 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7235 __ membar(Assembler::StoreStore);
7236 %}
7237 ins_pipe(pipe_class_default);
7238 %}
7239
7240 instruct membar_release_lock() %{
7241 match(MemBarReleaseLock);
7242 ins_cost(0);
7243
7244 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7245 size(0);
7246 ins_encode( /*empty*/ );
7247 ins_pipe(pipe_class_default);
7248 %}
7249
7250 instruct membar_volatile() %{
7251 match(MemBarVolatile);
7252 ins_cost(4*MEMORY_REF_COST);
7253
7254 format %{ "MEMBAR-volatile" %}
7255 size(4);
7256 ins_encode %{
7257 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7258 __ fence();
7259 %}
7260 ins_pipe(pipe_class_default);
7261 %}
7262
7263 // This optimization is wrong on PPC. The following pattern is not supported:
7264 // MemBarVolatile
7265 // ^ ^
7266 // | |
7267 // CtrlProj MemProj
7268 // ^ ^
7269 // | |
7270 // | Load
7271 // |
7272 // MemBarVolatile
7273 //
7274 // The first MemBarVolatile could get optimized out! According to
7275 // Vladimir, this pattern can not occur on Oracle platforms.
7276 // However, it does occur on PPC64 (because of membars in
7277 // inline_unsafe_load_store).
7278 //
7279 // Add this node again if we found a good solution for inline_unsafe_load_store().
7280 // Don't forget to look at the implementation of post_store_load_barrier again,
7281 // we did other fixes in that method.
7282 //instruct unnecessary_membar_volatile() %{
7283 // match(MemBarVolatile);
7284 // predicate(Matcher::post_store_load_barrier(n));
7285 // ins_cost(0);
7286 //
7287 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7288 // size(0);
7289 // ins_encode( /*empty*/ );
7290 // ins_pipe(pipe_class_default);
7291 //%}
7292
7293 instruct membar_CPUOrder() %{
7294 match(MemBarCPUOrder);
7295 ins_cost(0);
7296
7297 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7298 size(0);
7299 ins_encode( /*empty*/ );
7300 ins_pipe(pipe_class_default);
7301 %}
7302
7303 //----------Conditional Move---------------------------------------------------
7304
7305 // Cmove using isel.
7306 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7307 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7308 predicate(VM_Version::has_isel());
7309 ins_cost(DEFAULT_COST);
7310
7311 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7312 size(4);
7313 ins_encode %{
7314 // This is a Power7 instruction for which no machine description
7315 // exists. Anyways, the scheduler should be off on Power7.
7316 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7317 int cc = $cmp$$cmpcode;
7318 __ isel($dst$$Register, $crx$$CondRegister,
7319 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7320 %}
7321 ins_pipe(pipe_class_default);
7322 %}
7323
7324 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7325 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7326 predicate(!VM_Version::has_isel());
7327 ins_cost(DEFAULT_COST+BRANCH_COST);
7328
7329 ins_variable_size_depending_on_alignment(true);
7330
7331 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7332 // Worst case is branch + move + stop, no stop without scheduler
7333 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7334 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7335 ins_pipe(pipe_class_default);
7336 %}
7337
7338 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7339 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7340 ins_cost(DEFAULT_COST+BRANCH_COST);
7341
7342 ins_variable_size_depending_on_alignment(true);
7343
7344 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7345 // Worst case is branch + move + stop, no stop without scheduler
7346 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7347 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7348 ins_pipe(pipe_class_default);
7349 %}
7350
7351 // Cmove using isel.
7352 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7353 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7354 predicate(VM_Version::has_isel());
7355 ins_cost(DEFAULT_COST);
7356
7357 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7358 size(4);
7359 ins_encode %{
7360 // This is a Power7 instruction for which no machine description
7361 // exists. Anyways, the scheduler should be off on Power7.
7362 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7363 int cc = $cmp$$cmpcode;
7364 __ isel($dst$$Register, $crx$$CondRegister,
7365 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7366 %}
7367 ins_pipe(pipe_class_default);
7368 %}
7369
7370 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7371 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7372 predicate(!VM_Version::has_isel());
7373 ins_cost(DEFAULT_COST+BRANCH_COST);
7374
7375 ins_variable_size_depending_on_alignment(true);
7376
7377 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7378 // Worst case is branch + move + stop, no stop without scheduler.
7379 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7380 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7381 ins_pipe(pipe_class_default);
7382 %}
7383
7384 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7385 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7386 ins_cost(DEFAULT_COST+BRANCH_COST);
7387
7388 ins_variable_size_depending_on_alignment(true);
7389
7390 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7391 // Worst case is branch + move + stop, no stop without scheduler.
7392 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7393 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7394 ins_pipe(pipe_class_default);
7395 %}
7396
7397 // Cmove using isel.
7398 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7399 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7400 predicate(VM_Version::has_isel());
7401 ins_cost(DEFAULT_COST);
7402
7403 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7404 size(4);
7405 ins_encode %{
7406 // This is a Power7 instruction for which no machine description
7407 // exists. Anyways, the scheduler should be off on Power7.
7408 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7409 int cc = $cmp$$cmpcode;
7410 __ isel($dst$$Register, $crx$$CondRegister,
7411 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7412 %}
7413 ins_pipe(pipe_class_default);
7414 %}
7415
7416 // Conditional move for RegN. Only cmov(reg, reg).
7417 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7418 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7419 predicate(!VM_Version::has_isel());
7420 ins_cost(DEFAULT_COST+BRANCH_COST);
7421
7422 ins_variable_size_depending_on_alignment(true);
7423
7424 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7425 // Worst case is branch + move + stop, no stop without scheduler.
7426 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7427 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7428 ins_pipe(pipe_class_default);
7429 %}
7430
7431 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7432 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7433 ins_cost(DEFAULT_COST+BRANCH_COST);
7434
7435 ins_variable_size_depending_on_alignment(true);
7436
7437 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7438 // Worst case is branch + move + stop, no stop without scheduler.
7439 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7440 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7441 ins_pipe(pipe_class_default);
7442 %}
7443
7444 // Cmove using isel.
7445 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7446 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7447 predicate(VM_Version::has_isel());
7448 ins_cost(DEFAULT_COST);
7449
7450 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7451 size(4);
7452 ins_encode %{
7453 // This is a Power7 instruction for which no machine description
7454 // exists. Anyways, the scheduler should be off on Power7.
7455 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7456 int cc = $cmp$$cmpcode;
7457 __ isel($dst$$Register, $crx$$CondRegister,
7458 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7459 %}
7460 ins_pipe(pipe_class_default);
7461 %}
7462
7463 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7464 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7465 predicate(!VM_Version::has_isel());
7466 ins_cost(DEFAULT_COST+BRANCH_COST);
7467
7468 ins_variable_size_depending_on_alignment(true);
7469
7470 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7471 // Worst case is branch + move + stop, no stop without scheduler.
7472 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7473 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7474 ins_pipe(pipe_class_default);
7475 %}
7476
7477 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7478 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7479 ins_cost(DEFAULT_COST+BRANCH_COST);
7480
7481 ins_variable_size_depending_on_alignment(true);
7482
7483 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7484 // Worst case is branch + move + stop, no stop without scheduler.
7485 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7486 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7487 ins_pipe(pipe_class_default);
7488 %}
7489
7490 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7491 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7492 ins_cost(DEFAULT_COST+BRANCH_COST);
7493
7494 ins_variable_size_depending_on_alignment(true);
7495
7496 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7497 // Worst case is branch + move + stop, no stop without scheduler.
7498 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7499 ins_encode %{
7500 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7501 Label done;
7502 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7503 // Branch if not (cmp crx).
7504 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7505 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7506 // TODO PPC port __ endgroup_if_needed(_size == 12);
7507 __ bind(done);
7508 %}
7509 ins_pipe(pipe_class_default);
7510 %}
7511
7512 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7513 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7514 ins_cost(DEFAULT_COST+BRANCH_COST);
7515
7516 ins_variable_size_depending_on_alignment(true);
7517
7518 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7519 // Worst case is branch + move + stop, no stop without scheduler.
7520 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7521 ins_encode %{
7522 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7523 Label done;
7524 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7525 // Branch if not (cmp crx).
7526 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7527 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7528 // TODO PPC port __ endgroup_if_needed(_size == 12);
7529 __ bind(done);
7530 %}
7531 ins_pipe(pipe_class_default);
7532 %}
7533
7534 //----------Conditional_store--------------------------------------------------
7535 // Conditional-store of the updated heap-top.
7536 // Used during allocation of the shared heap.
7537 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7538
7539 // As compareAndSwapL, but return flag register instead of boolean value in
7540 // int register.
7541 // Used by sun/misc/AtomicLongCSImpl.java.
7542 // Mem_ptr must be a memory operand, else this node does not get
7543 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7544 // can be rematerialized which leads to errors.
7545 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7546 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7547 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7548 ins_encode %{
7549 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7550 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7551 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7552 noreg, NULL, true);
7553 %}
7554 ins_pipe(pipe_class_default);
7555 %}
7556
7557 // As compareAndSwapP, but return flag register instead of boolean value in
7558 // int register.
7559 // This instruction is matched if UseTLAB is off.
7560 // Mem_ptr must be a memory operand, else this node does not get
7561 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7562 // can be rematerialized which leads to errors.
7563 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7564 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7565 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7566 ins_encode %{
7567 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7568 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7569 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7570 noreg, NULL, true);
7571 %}
7572 ins_pipe(pipe_class_default);
7573 %}
7574
7575 // Implement LoadPLocked. Must be ordered against changes of the memory location
7576 // by storePConditional.
7577 // Don't know whether this is ever used.
7578 instruct loadPLocked(iRegPdst dst, memory mem) %{
7579 match(Set dst (LoadPLocked mem));
7580 ins_cost(MEMORY_REF_COST);
7581
7582 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7583 "TWI $dst\n\t"
7584 "ISYNC" %}
7585 size(12);
7586 ins_encode( enc_ld_ac(dst, mem) );
7587 ins_pipe(pipe_class_memory);
7588 %}
7589
7590 //----------Compare-And-Swap---------------------------------------------------
7591
7592 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7593 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7594 // matched.
7595
7596 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7597 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7598 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7599 // Variable size: instruction count smaller if regs are disjoint.
7600 ins_encode %{
7601 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7602 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7603 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7604 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7605 $res$$Register, true);
7606 %}
7607 ins_pipe(pipe_class_default);
7608 %}
7609
7610 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7611 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7612 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7613 // Variable size: instruction count smaller if regs are disjoint.
7614 ins_encode %{
7615 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7616 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7617 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7618 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7619 $res$$Register, true);
7620 %}
7621 ins_pipe(pipe_class_default);
7622 %}
7623
7624 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7625 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7626 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7627 // Variable size: instruction count smaller if regs are disjoint.
7628 ins_encode %{
7629 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7630 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7631 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7632 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7633 $res$$Register, NULL, true);
7634 %}
7635 ins_pipe(pipe_class_default);
7636 %}
7637
7638 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7639 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7640 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7641 // Variable size: instruction count smaller if regs are disjoint.
7642 ins_encode %{
7643 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7644 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7645 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7646 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7647 $res$$Register, NULL, true);
7648 %}
7649 ins_pipe(pipe_class_default);
7650 %}
7651
7652 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7653 match(Set res (GetAndAddI mem_ptr src));
7654 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7655 // Variable size: instruction count smaller if regs are disjoint.
7656 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7657 ins_pipe(pipe_class_default);
7658 %}
7659
7660 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7661 match(Set res (GetAndAddL mem_ptr src));
7662 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7663 // Variable size: instruction count smaller if regs are disjoint.
7664 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7665 ins_pipe(pipe_class_default);
7666 %}
7667
7668 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7669 match(Set res (GetAndSetI mem_ptr src));
7670 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7671 // Variable size: instruction count smaller if regs are disjoint.
7672 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7673 ins_pipe(pipe_class_default);
7674 %}
7675
7676 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7677 match(Set res (GetAndSetL mem_ptr src));
7678 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7679 // Variable size: instruction count smaller if regs are disjoint.
7680 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7681 ins_pipe(pipe_class_default);
7682 %}
7683
7684 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7685 match(Set res (GetAndSetP mem_ptr src));
7686 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7687 // Variable size: instruction count smaller if regs are disjoint.
7688 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7689 ins_pipe(pipe_class_default);
7690 %}
7691
7692 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7693 match(Set res (GetAndSetN mem_ptr src));
7694 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7695 // Variable size: instruction count smaller if regs are disjoint.
7696 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7697 ins_pipe(pipe_class_default);
7698 %}
7699
7700 //----------Arithmetic Instructions--------------------------------------------
7701 // Addition Instructions
7702
7703 // Register Addition
7704 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7705 match(Set dst (AddI src1 src2));
7706 format %{ "ADD $dst, $src1, $src2" %}
7707 size(4);
7708 ins_encode %{
7709 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7710 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7711 %}
7712 ins_pipe(pipe_class_default);
7713 %}
7714
7715 // Expand does not work with above instruct. (??)
7716 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7717 // no match-rule
7718 effect(DEF dst, USE src1, USE src2);
7719 format %{ "ADD $dst, $src1, $src2" %}
7720 size(4);
7721 ins_encode %{
7722 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7723 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7724 %}
7725 ins_pipe(pipe_class_default);
7726 %}
7727
7728 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7729 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7730 ins_cost(DEFAULT_COST*3);
7731
7732 expand %{
7733 // FIXME: we should do this in the ideal world.
7734 iRegIdst tmp1;
7735 iRegIdst tmp2;
7736 addI_reg_reg(tmp1, src1, src2);
7737 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7738 addI_reg_reg(dst, tmp1, tmp2);
7739 %}
7740 %}
7741
7742 // Immediate Addition
7743 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7744 match(Set dst (AddI src1 src2));
7745 format %{ "ADDI $dst, $src1, $src2" %}
7746 size(4);
7747 ins_encode %{
7748 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7749 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7750 %}
7751 ins_pipe(pipe_class_default);
7752 %}
7753
7754 // Immediate Addition with 16-bit shifted operand
7755 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7756 match(Set dst (AddI src1 src2));
7757 format %{ "ADDIS $dst, $src1, $src2" %}
7758 size(4);
7759 ins_encode %{
7760 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7761 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7762 %}
7763 ins_pipe(pipe_class_default);
7764 %}
7765
7766 // Long Addition
7767 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7768 match(Set dst (AddL src1 src2));
7769 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7770 size(4);
7771 ins_encode %{
7772 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7773 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7774 %}
7775 ins_pipe(pipe_class_default);
7776 %}
7777
7778 // Expand does not work with above instruct. (??)
7779 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7780 // no match-rule
7781 effect(DEF dst, USE src1, USE src2);
7782 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7783 size(4);
7784 ins_encode %{
7785 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7786 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7787 %}
7788 ins_pipe(pipe_class_default);
7789 %}
7790
7791 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7792 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7793 ins_cost(DEFAULT_COST*3);
7794
7795 expand %{
7796 // FIXME: we should do this in the ideal world.
7797 iRegLdst tmp1;
7798 iRegLdst tmp2;
7799 addL_reg_reg(tmp1, src1, src2);
7800 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7801 addL_reg_reg(dst, tmp1, tmp2);
7802 %}
7803 %}
7804
7805 // AddL + ConvL2I.
7806 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7807 match(Set dst (ConvL2I (AddL src1 src2)));
7808
7809 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7810 size(4);
7811 ins_encode %{
7812 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7813 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7814 %}
7815 ins_pipe(pipe_class_default);
7816 %}
7817
7818 // No constant pool entries required.
7819 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7820 match(Set dst (AddL src1 src2));
7821
7822 format %{ "ADDI $dst, $src1, $src2" %}
7823 size(4);
7824 ins_encode %{
7825 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7826 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7827 %}
7828 ins_pipe(pipe_class_default);
7829 %}
7830
7831 // Long Immediate Addition with 16-bit shifted operand.
7832 // No constant pool entries required.
7833 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7834 match(Set dst (AddL src1 src2));
7835
7836 format %{ "ADDIS $dst, $src1, $src2" %}
7837 size(4);
7838 ins_encode %{
7839 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7840 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7841 %}
7842 ins_pipe(pipe_class_default);
7843 %}
7844
7845 // Pointer Register Addition
7846 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7847 match(Set dst (AddP src1 src2));
7848 format %{ "ADD $dst, $src1, $src2" %}
7849 size(4);
7850 ins_encode %{
7851 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7852 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7853 %}
7854 ins_pipe(pipe_class_default);
7855 %}
7856
7857 // Pointer Immediate Addition
7858 // No constant pool entries required.
7859 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7860 match(Set dst (AddP src1 src2));
7861
7862 format %{ "ADDI $dst, $src1, $src2" %}
7863 size(4);
7864 ins_encode %{
7865 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7866 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7867 %}
7868 ins_pipe(pipe_class_default);
7869 %}
7870
7871 // Pointer Immediate Addition with 16-bit shifted operand.
7872 // No constant pool entries required.
7873 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7874 match(Set dst (AddP src1 src2));
7875
7876 format %{ "ADDIS $dst, $src1, $src2" %}
7877 size(4);
7878 ins_encode %{
7879 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7880 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7881 %}
7882 ins_pipe(pipe_class_default);
7883 %}
7884
7885 //---------------------
7886 // Subtraction Instructions
7887
7888 // Register Subtraction
7889 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7890 match(Set dst (SubI src1 src2));
7891 format %{ "SUBF $dst, $src2, $src1" %}
7892 size(4);
7893 ins_encode %{
7894 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7895 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7896 %}
7897 ins_pipe(pipe_class_default);
7898 %}
7899
7900 // Immediate Subtraction
7901 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7902 // so this rule seems to be unused.
7903 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7904 match(Set dst (SubI src1 src2));
7905 format %{ "SUBI $dst, $src1, $src2" %}
7906 size(4);
7907 ins_encode %{
7908 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7909 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7910 %}
7911 ins_pipe(pipe_class_default);
7912 %}
7913
7914 // SubI from constant (using subfic).
7915 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7916 match(Set dst (SubI src1 src2));
7917 format %{ "SUBI $dst, $src1, $src2" %}
7918
7919 size(4);
7920 ins_encode %{
7921 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7922 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7923 %}
7924 ins_pipe(pipe_class_default);
7925 %}
7926
7927 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7928 // positive integers and 0xF...F for negative ones.
7929 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7930 // no match-rule, false predicate
7931 effect(DEF dst, USE src);
7932 predicate(false);
7933
7934 format %{ "SRAWI $dst, $src, #31" %}
7935 size(4);
7936 ins_encode %{
7937 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7938 __ srawi($dst$$Register, $src$$Register, 0x1f);
7939 %}
7940 ins_pipe(pipe_class_default);
7941 %}
7942
7943 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7944 match(Set dst (AbsI src));
7945 ins_cost(DEFAULT_COST*3);
7946
7947 expand %{
7948 iRegIdst tmp1;
7949 iRegIdst tmp2;
7950 signmask32I_regI(tmp1, src);
7951 xorI_reg_reg(tmp2, tmp1, src);
7952 subI_reg_reg(dst, tmp2, tmp1);
7953 %}
7954 %}
7955
7956 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7957 match(Set dst (SubI zero src2));
7958 format %{ "NEG $dst, $src2" %}
7959 size(4);
7960 ins_encode %{
7961 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7962 __ neg($dst$$Register, $src2$$Register);
7963 %}
7964 ins_pipe(pipe_class_default);
7965 %}
7966
7967 // Long subtraction
7968 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7969 match(Set dst (SubL src1 src2));
7970 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7971 size(4);
7972 ins_encode %{
7973 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7974 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7975 %}
7976 ins_pipe(pipe_class_default);
7977 %}
7978
7979 // SubL + convL2I.
7980 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7981 match(Set dst (ConvL2I (SubL src1 src2)));
7982
7983 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7984 size(4);
7985 ins_encode %{
7986 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7987 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7988 %}
7989 ins_pipe(pipe_class_default);
7990 %}
7991
7992 // Immediate Subtraction
7993 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7994 // so this rule seems to be unused.
7995 // No constant pool entries required.
7996 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7997 match(Set dst (SubL src1 src2));
7998
7999 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
8000 size(4);
8001 ins_encode %{
8002 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8003 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
8004 %}
8005 ins_pipe(pipe_class_default);
8006 %}
8007
8008 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8009 // positive longs and 0xF...F for negative ones.
8010 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
8011 // no match-rule, false predicate
8012 effect(DEF dst, USE src);
8013 predicate(false);
8014
8015 format %{ "SRADI $dst, $src, #63" %}
8016 size(4);
8017 ins_encode %{
8018 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8019 __ sradi($dst$$Register, $src$$Register, 0x3f);
8020 %}
8021 ins_pipe(pipe_class_default);
8022 %}
8023
8024 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8025 // positive longs and 0xF...F for negative ones.
8026 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8027 // no match-rule, false predicate
8028 effect(DEF dst, USE src);
8029 predicate(false);
8030
8031 format %{ "SRADI $dst, $src, #63" %}
8032 size(4);
8033 ins_encode %{
8034 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8035 __ sradi($dst$$Register, $src$$Register, 0x3f);
8036 %}
8037 ins_pipe(pipe_class_default);
8038 %}
8039
8040 // Long negation
8041 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8042 match(Set dst (SubL zero src2));
8043 format %{ "NEG $dst, $src2 \t// long" %}
8044 size(4);
8045 ins_encode %{
8046 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8047 __ neg($dst$$Register, $src2$$Register);
8048 %}
8049 ins_pipe(pipe_class_default);
8050 %}
8051
8052 // NegL + ConvL2I.
8053 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8054 match(Set dst (ConvL2I (SubL zero src2)));
8055
8056 format %{ "NEG $dst, $src2 \t// long + l2i" %}
8057 size(4);
8058 ins_encode %{
8059 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8060 __ neg($dst$$Register, $src2$$Register);
8061 %}
8062 ins_pipe(pipe_class_default);
8063 %}
8064
8065 // Multiplication Instructions
8066 // Integer Multiplication
8067
8068 // Register Multiplication
8069 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8070 match(Set dst (MulI src1 src2));
8071 ins_cost(DEFAULT_COST);
8072
8073 format %{ "MULLW $dst, $src1, $src2" %}
8074 size(4);
8075 ins_encode %{
8076 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8077 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8078 %}
8079 ins_pipe(pipe_class_default);
8080 %}
8081
8082 // Immediate Multiplication
8083 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8084 match(Set dst (MulI src1 src2));
8085 ins_cost(DEFAULT_COST);
8086
8087 format %{ "MULLI $dst, $src1, $src2" %}
8088 size(4);
8089 ins_encode %{
8090 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8091 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8092 %}
8093 ins_pipe(pipe_class_default);
8094 %}
8095
8096 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8097 match(Set dst (MulL src1 src2));
8098 ins_cost(DEFAULT_COST);
8099
8100 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8101 size(4);
8102 ins_encode %{
8103 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8104 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8105 %}
8106 ins_pipe(pipe_class_default);
8107 %}
8108
8109 // Multiply high for optimized long division by constant.
8110 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8111 match(Set dst (MulHiL src1 src2));
8112 ins_cost(DEFAULT_COST);
8113
8114 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8115 size(4);
8116 ins_encode %{
8117 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8118 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8119 %}
8120 ins_pipe(pipe_class_default);
8121 %}
8122
8123 // Immediate Multiplication
8124 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8125 match(Set dst (MulL src1 src2));
8126 ins_cost(DEFAULT_COST);
8127
8128 format %{ "MULLI $dst, $src1, $src2" %}
8129 size(4);
8130 ins_encode %{
8131 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8132 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8133 %}
8134 ins_pipe(pipe_class_default);
8135 %}
8136
8137 // Integer Division with Immediate -1: Negate.
8138 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8139 match(Set dst (DivI src1 src2));
8140 ins_cost(DEFAULT_COST);
8141
8142 format %{ "NEG $dst, $src1 \t// /-1" %}
8143 size(4);
8144 ins_encode %{
8145 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8146 __ neg($dst$$Register, $src1$$Register);
8147 %}
8148 ins_pipe(pipe_class_default);
8149 %}
8150
8151 // Integer Division with constant, but not -1.
8152 // We should be able to improve this by checking the type of src2.
8153 // It might well be that src2 is known to be positive.
8154 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8155 match(Set dst (DivI src1 src2));
8156 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8157 ins_cost(2*DEFAULT_COST);
8158
8159 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8160 size(4);
8161 ins_encode %{
8162 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8163 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8164 %}
8165 ins_pipe(pipe_class_default);
8166 %}
8167
8168 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8169 effect(USE_DEF dst, USE src1, USE crx);
8170 predicate(false);
8171
8172 ins_variable_size_depending_on_alignment(true);
8173
8174 format %{ "CMOVE $dst, neg($src1), $crx" %}
8175 // Worst case is branch + move + stop, no stop without scheduler.
8176 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8177 ins_encode %{
8178 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8179 Label done;
8180 __ bne($crx$$CondRegister, done);
8181 __ neg($dst$$Register, $src1$$Register);
8182 // TODO PPC port __ endgroup_if_needed(_size == 12);
8183 __ bind(done);
8184 %}
8185 ins_pipe(pipe_class_default);
8186 %}
8187
8188 // Integer Division with Registers not containing constants.
8189 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8190 match(Set dst (DivI src1 src2));
8191 ins_cost(10*DEFAULT_COST);
8192
8193 expand %{
8194 immI16 imm %{ (int)-1 %}
8195 flagsReg tmp1;
8196 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8197 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8198 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8199 %}
8200 %}
8201
8202 // Long Division with Immediate -1: Negate.
8203 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8204 match(Set dst (DivL src1 src2));
8205 ins_cost(DEFAULT_COST);
8206
8207 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8208 size(4);
8209 ins_encode %{
8210 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8211 __ neg($dst$$Register, $src1$$Register);
8212 %}
8213 ins_pipe(pipe_class_default);
8214 %}
8215
8216 // Long Division with constant, but not -1.
8217 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8218 match(Set dst (DivL src1 src2));
8219 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8220 ins_cost(2*DEFAULT_COST);
8221
8222 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8223 size(4);
8224 ins_encode %{
8225 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8226 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8227 %}
8228 ins_pipe(pipe_class_default);
8229 %}
8230
8231 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8232 effect(USE_DEF dst, USE src1, USE crx);
8233 predicate(false);
8234
8235 ins_variable_size_depending_on_alignment(true);
8236
8237 format %{ "CMOVE $dst, neg($src1), $crx" %}
8238 // Worst case is branch + move + stop, no stop without scheduler.
8239 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8240 ins_encode %{
8241 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8242 Label done;
8243 __ bne($crx$$CondRegister, done);
8244 __ neg($dst$$Register, $src1$$Register);
8245 // TODO PPC port __ endgroup_if_needed(_size == 12);
8246 __ bind(done);
8247 %}
8248 ins_pipe(pipe_class_default);
8249 %}
8250
8251 // Long Division with Registers not containing constants.
8252 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8253 match(Set dst (DivL src1 src2));
8254 ins_cost(10*DEFAULT_COST);
8255
8256 expand %{
8257 immL16 imm %{ (int)-1 %}
8258 flagsReg tmp1;
8259 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8260 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8261 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8262 %}
8263 %}
8264
8265 // Integer Remainder with registers.
8266 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8267 match(Set dst (ModI src1 src2));
8268 ins_cost(10*DEFAULT_COST);
8269
8270 expand %{
8271 immI16 imm %{ (int)-1 %}
8272 flagsReg tmp1;
8273 iRegIdst tmp2;
8274 iRegIdst tmp3;
8275 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8276 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8277 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8278 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8279 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8280 %}
8281 %}
8282
8283 // Long Remainder with registers
8284 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8285 match(Set dst (ModL src1 src2));
8286 ins_cost(10*DEFAULT_COST);
8287
8288 expand %{
8289 immL16 imm %{ (int)-1 %}
8290 flagsReg tmp1;
8291 iRegLdst tmp2;
8292 iRegLdst tmp3;
8293 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8294 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8295 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8296 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8297 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8298 %}
8299 %}
8300
8301 // Integer Shift Instructions
8302
8303 // Register Shift Left
8304
8305 // Clear all but the lowest #mask bits.
8306 // Used to normalize shift amounts in registers.
8307 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8308 // no match-rule, false predicate
8309 effect(DEF dst, USE src, USE mask);
8310 predicate(false);
8311
8312 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8313 size(4);
8314 ins_encode %{
8315 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8316 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8317 %}
8318 ins_pipe(pipe_class_default);
8319 %}
8320
8321 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8322 // no match-rule, false predicate
8323 effect(DEF dst, USE src1, USE src2);
8324 predicate(false);
8325
8326 format %{ "SLW $dst, $src1, $src2" %}
8327 size(4);
8328 ins_encode %{
8329 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8330 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8331 %}
8332 ins_pipe(pipe_class_default);
8333 %}
8334
8335 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8336 match(Set dst (LShiftI src1 src2));
8337 ins_cost(DEFAULT_COST*2);
8338 expand %{
8339 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8340 iRegIdst tmpI;
8341 maskI_reg_imm(tmpI, src2, mask);
8342 lShiftI_reg_reg(dst, src1, tmpI);
8343 %}
8344 %}
8345
8346 // Register Shift Left Immediate
8347 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8348 match(Set dst (LShiftI src1 src2));
8349
8350 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8351 size(4);
8352 ins_encode %{
8353 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8354 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8355 %}
8356 ins_pipe(pipe_class_default);
8357 %}
8358
8359 // AndI with negpow2-constant + LShiftI
8360 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8361 match(Set dst (LShiftI (AndI src1 src2) src3));
8362 predicate(UseRotateAndMaskInstructionsPPC64);
8363
8364 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8365 size(4);
8366 ins_encode %{
8367 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8368 long src2 = $src2$$constant;
8369 long src3 = $src3$$constant;
8370 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8371 if (maskbits >= 32) {
8372 __ li($dst$$Register, 0); // addi
8373 } else {
8374 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8375 }
8376 %}
8377 ins_pipe(pipe_class_default);
8378 %}
8379
8380 // RShiftI + AndI with negpow2-constant + LShiftI
8381 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8382 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8383 predicate(UseRotateAndMaskInstructionsPPC64);
8384
8385 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8386 size(4);
8387 ins_encode %{
8388 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8389 long src2 = $src2$$constant;
8390 long src3 = $src3$$constant;
8391 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8392 if (maskbits >= 32) {
8393 __ li($dst$$Register, 0); // addi
8394 } else {
8395 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8396 }
8397 %}
8398 ins_pipe(pipe_class_default);
8399 %}
8400
8401 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8402 // no match-rule, false predicate
8403 effect(DEF dst, USE src1, USE src2);
8404 predicate(false);
8405
8406 format %{ "SLD $dst, $src1, $src2" %}
8407 size(4);
8408 ins_encode %{
8409 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8410 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8411 %}
8412 ins_pipe(pipe_class_default);
8413 %}
8414
8415 // Register Shift Left
8416 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8417 match(Set dst (LShiftL src1 src2));
8418 ins_cost(DEFAULT_COST*2);
8419 expand %{
8420 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8421 iRegIdst tmpI;
8422 maskI_reg_imm(tmpI, src2, mask);
8423 lShiftL_regL_regI(dst, src1, tmpI);
8424 %}
8425 %}
8426
8427 // Register Shift Left Immediate
8428 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8429 match(Set dst (LShiftL src1 src2));
8430 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8431 size(4);
8432 ins_encode %{
8433 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8434 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8435 %}
8436 ins_pipe(pipe_class_default);
8437 %}
8438
8439 // If we shift more than 32 bits, we need not convert I2L.
8440 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8441 match(Set dst (LShiftL (ConvI2L src1) src2));
8442 ins_cost(DEFAULT_COST);
8443
8444 size(4);
8445 format %{ "SLDI $dst, i2l($src1), $src2" %}
8446 ins_encode %{
8447 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8448 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8449 %}
8450 ins_pipe(pipe_class_default);
8451 %}
8452
8453 // Shift a postivie int to the left.
8454 // Clrlsldi clears the upper 32 bits and shifts.
8455 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8456 match(Set dst (LShiftL (ConvI2L src1) src2));
8457 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8458
8459 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8460 size(4);
8461 ins_encode %{
8462 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8463 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8464 %}
8465 ins_pipe(pipe_class_default);
8466 %}
8467
8468 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8469 // no match-rule, false predicate
8470 effect(DEF dst, USE src1, USE src2);
8471 predicate(false);
8472
8473 format %{ "SRAW $dst, $src1, $src2" %}
8474 size(4);
8475 ins_encode %{
8476 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8477 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8478 %}
8479 ins_pipe(pipe_class_default);
8480 %}
8481
8482 // Register Arithmetic Shift Right
8483 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8484 match(Set dst (RShiftI src1 src2));
8485 ins_cost(DEFAULT_COST*2);
8486 expand %{
8487 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8488 iRegIdst tmpI;
8489 maskI_reg_imm(tmpI, src2, mask);
8490 arShiftI_reg_reg(dst, src1, tmpI);
8491 %}
8492 %}
8493
8494 // Register Arithmetic Shift Right Immediate
8495 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8496 match(Set dst (RShiftI src1 src2));
8497
8498 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8499 size(4);
8500 ins_encode %{
8501 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8502 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8503 %}
8504 ins_pipe(pipe_class_default);
8505 %}
8506
8507 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8508 // no match-rule, false predicate
8509 effect(DEF dst, USE src1, USE src2);
8510 predicate(false);
8511
8512 format %{ "SRAD $dst, $src1, $src2" %}
8513 size(4);
8514 ins_encode %{
8515 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8516 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8517 %}
8518 ins_pipe(pipe_class_default);
8519 %}
8520
8521 // Register Shift Right Arithmetic Long
8522 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8523 match(Set dst (RShiftL src1 src2));
8524 ins_cost(DEFAULT_COST*2);
8525
8526 expand %{
8527 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8528 iRegIdst tmpI;
8529 maskI_reg_imm(tmpI, src2, mask);
8530 arShiftL_regL_regI(dst, src1, tmpI);
8531 %}
8532 %}
8533
8534 // Register Shift Right Immediate
8535 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8536 match(Set dst (RShiftL src1 src2));
8537
8538 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8539 size(4);
8540 ins_encode %{
8541 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8542 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8543 %}
8544 ins_pipe(pipe_class_default);
8545 %}
8546
8547 // RShiftL + ConvL2I
8548 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8549 match(Set dst (ConvL2I (RShiftL src1 src2)));
8550
8551 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8552 size(4);
8553 ins_encode %{
8554 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8555 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8556 %}
8557 ins_pipe(pipe_class_default);
8558 %}
8559
8560 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8561 // no match-rule, false predicate
8562 effect(DEF dst, USE src1, USE src2);
8563 predicate(false);
8564
8565 format %{ "SRW $dst, $src1, $src2" %}
8566 size(4);
8567 ins_encode %{
8568 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8569 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8570 %}
8571 ins_pipe(pipe_class_default);
8572 %}
8573
8574 // Register Shift Right
8575 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8576 match(Set dst (URShiftI src1 src2));
8577 ins_cost(DEFAULT_COST*2);
8578
8579 expand %{
8580 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8581 iRegIdst tmpI;
8582 maskI_reg_imm(tmpI, src2, mask);
8583 urShiftI_reg_reg(dst, src1, tmpI);
8584 %}
8585 %}
8586
8587 // Register Shift Right Immediate
8588 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8589 match(Set dst (URShiftI src1 src2));
8590
8591 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8592 size(4);
8593 ins_encode %{
8594 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8595 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8596 %}
8597 ins_pipe(pipe_class_default);
8598 %}
8599
8600 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8601 // no match-rule, false predicate
8602 effect(DEF dst, USE src1, USE src2);
8603 predicate(false);
8604
8605 format %{ "SRD $dst, $src1, $src2" %}
8606 size(4);
8607 ins_encode %{
8608 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8609 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8610 %}
8611 ins_pipe(pipe_class_default);
8612 %}
8613
8614 // Register Shift Right
8615 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8616 match(Set dst (URShiftL src1 src2));
8617 ins_cost(DEFAULT_COST*2);
8618
8619 expand %{
8620 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8621 iRegIdst tmpI;
8622 maskI_reg_imm(tmpI, src2, mask);
8623 urShiftL_regL_regI(dst, src1, tmpI);
8624 %}
8625 %}
8626
8627 // Register Shift Right Immediate
8628 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8629 match(Set dst (URShiftL src1 src2));
8630
8631 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8632 size(4);
8633 ins_encode %{
8634 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8635 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8636 %}
8637 ins_pipe(pipe_class_default);
8638 %}
8639
8640 // URShiftL + ConvL2I.
8641 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8642 match(Set dst (ConvL2I (URShiftL src1 src2)));
8643
8644 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8645 size(4);
8646 ins_encode %{
8647 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8648 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8649 %}
8650 ins_pipe(pipe_class_default);
8651 %}
8652
8653 // Register Shift Right Immediate with a CastP2X
8654 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8655 match(Set dst (URShiftL (CastP2X src1) src2));
8656
8657 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8658 size(4);
8659 ins_encode %{
8660 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8661 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8662 %}
8663 ins_pipe(pipe_class_default);
8664 %}
8665
8666 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8667 match(Set dst (ConvL2I (ConvI2L src)));
8668
8669 format %{ "EXTSW $dst, $src \t// int->int" %}
8670 size(4);
8671 ins_encode %{
8672 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8673 __ extsw($dst$$Register, $src$$Register);
8674 %}
8675 ins_pipe(pipe_class_default);
8676 %}
8677
8678 //----------Rotate Instructions------------------------------------------------
8679
8680 // Rotate Left by 8-bit immediate
8681 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8682 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8683 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8684
8685 format %{ "ROTLWI $dst, $src, $lshift" %}
8686 size(4);
8687 ins_encode %{
8688 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8689 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8690 %}
8691 ins_pipe(pipe_class_default);
8692 %}
8693
8694 // Rotate Right by 8-bit immediate
8695 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8696 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8697 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8698
8699 format %{ "ROTRWI $dst, $rshift" %}
8700 size(4);
8701 ins_encode %{
8702 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8703 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8704 %}
8705 ins_pipe(pipe_class_default);
8706 %}
8707
8708 //----------Floating Point Arithmetic Instructions-----------------------------
8709
8710 // Add float single precision
8711 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8712 match(Set dst (AddF src1 src2));
8713
8714 format %{ "FADDS $dst, $src1, $src2" %}
8715 size(4);
8716 ins_encode %{
8717 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8718 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8719 %}
8720 ins_pipe(pipe_class_default);
8721 %}
8722
8723 // Add float double precision
8724 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8725 match(Set dst (AddD src1 src2));
8726
8727 format %{ "FADD $dst, $src1, $src2" %}
8728 size(4);
8729 ins_encode %{
8730 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8731 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8732 %}
8733 ins_pipe(pipe_class_default);
8734 %}
8735
8736 // Sub float single precision
8737 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8738 match(Set dst (SubF src1 src2));
8739
8740 format %{ "FSUBS $dst, $src1, $src2" %}
8741 size(4);
8742 ins_encode %{
8743 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8744 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8745 %}
8746 ins_pipe(pipe_class_default);
8747 %}
8748
8749 // Sub float double precision
8750 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8751 match(Set dst (SubD src1 src2));
8752 format %{ "FSUB $dst, $src1, $src2" %}
8753 size(4);
8754 ins_encode %{
8755 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8756 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8757 %}
8758 ins_pipe(pipe_class_default);
8759 %}
8760
8761 // Mul float single precision
8762 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8763 match(Set dst (MulF src1 src2));
8764 format %{ "FMULS $dst, $src1, $src2" %}
8765 size(4);
8766 ins_encode %{
8767 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8768 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8769 %}
8770 ins_pipe(pipe_class_default);
8771 %}
8772
8773 // Mul float double precision
8774 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8775 match(Set dst (MulD src1 src2));
8776 format %{ "FMUL $dst, $src1, $src2" %}
8777 size(4);
8778 ins_encode %{
8779 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8780 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8781 %}
8782 ins_pipe(pipe_class_default);
8783 %}
8784
8785 // Div float single precision
8786 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8787 match(Set dst (DivF src1 src2));
8788 format %{ "FDIVS $dst, $src1, $src2" %}
8789 size(4);
8790 ins_encode %{
8791 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8792 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8793 %}
8794 ins_pipe(pipe_class_default);
8795 %}
8796
8797 // Div float double precision
8798 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8799 match(Set dst (DivD src1 src2));
8800 format %{ "FDIV $dst, $src1, $src2" %}
8801 size(4);
8802 ins_encode %{
8803 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8804 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8805 %}
8806 ins_pipe(pipe_class_default);
8807 %}
8808
8809 // Absolute float single precision
8810 instruct absF_reg(regF dst, regF src) %{
8811 match(Set dst (AbsF src));
8812 format %{ "FABS $dst, $src \t// float" %}
8813 size(4);
8814 ins_encode %{
8815 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8816 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8817 %}
8818 ins_pipe(pipe_class_default);
8819 %}
8820
8821 // Absolute float double precision
8822 instruct absD_reg(regD dst, regD src) %{
8823 match(Set dst (AbsD src));
8824 format %{ "FABS $dst, $src \t// double" %}
8825 size(4);
8826 ins_encode %{
8827 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8828 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8829 %}
8830 ins_pipe(pipe_class_default);
8831 %}
8832
8833 instruct negF_reg(regF dst, regF src) %{
8834 match(Set dst (NegF src));
8835 format %{ "FNEG $dst, $src \t// float" %}
8836 size(4);
8837 ins_encode %{
8838 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8839 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8840 %}
8841 ins_pipe(pipe_class_default);
8842 %}
8843
8844 instruct negD_reg(regD dst, regD src) %{
8845 match(Set dst (NegD src));
8846 format %{ "FNEG $dst, $src \t// double" %}
8847 size(4);
8848 ins_encode %{
8849 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8850 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8851 %}
8852 ins_pipe(pipe_class_default);
8853 %}
8854
8855 // AbsF + NegF.
8856 instruct negF_absF_reg(regF dst, regF src) %{
8857 match(Set dst (NegF (AbsF src)));
8858 format %{ "FNABS $dst, $src \t// float" %}
8859 size(4);
8860 ins_encode %{
8861 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8862 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8863 %}
8864 ins_pipe(pipe_class_default);
8865 %}
8866
8867 // AbsD + NegD.
8868 instruct negD_absD_reg(regD dst, regD src) %{
8869 match(Set dst (NegD (AbsD src)));
8870 format %{ "FNABS $dst, $src \t// double" %}
8871 size(4);
8872 ins_encode %{
8873 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8874 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8875 %}
8876 ins_pipe(pipe_class_default);
8877 %}
8878
8879 // VM_Version::has_fsqrt() decides if this node will be used.
8880 // Sqrt float double precision
8881 instruct sqrtD_reg(regD dst, regD src) %{
8882 match(Set dst (SqrtD src));
8883 format %{ "FSQRT $dst, $src" %}
8884 size(4);
8885 ins_encode %{
8886 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8887 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8888 %}
8889 ins_pipe(pipe_class_default);
8890 %}
8891
8892 // Single-precision sqrt.
8893 instruct sqrtF_reg(regF dst, regF src) %{
8894 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8895 predicate(VM_Version::has_fsqrts());
8896 ins_cost(DEFAULT_COST);
8897
8898 format %{ "FSQRTS $dst, $src" %}
8899 size(4);
8900 ins_encode %{
8901 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8902 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8903 %}
8904 ins_pipe(pipe_class_default);
8905 %}
8906
8907 instruct roundDouble_nop(regD dst) %{
8908 match(Set dst (RoundDouble dst));
8909 ins_cost(0);
8910
8911 format %{ " -- \t// RoundDouble not needed - empty" %}
8912 size(0);
8913 // PPC results are already "rounded" (i.e., normal-format IEEE).
8914 ins_encode( /*empty*/ );
8915 ins_pipe(pipe_class_default);
8916 %}
8917
8918 instruct roundFloat_nop(regF dst) %{
8919 match(Set dst (RoundFloat dst));
8920 ins_cost(0);
8921
8922 format %{ " -- \t// RoundFloat not needed - empty" %}
8923 size(0);
8924 // PPC results are already "rounded" (i.e., normal-format IEEE).
8925 ins_encode( /*empty*/ );
8926 ins_pipe(pipe_class_default);
8927 %}
8928
8929 //----------Logical Instructions-----------------------------------------------
8930
8931 // And Instructions
8932
8933 // Register And
8934 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8935 match(Set dst (AndI src1 src2));
8936 format %{ "AND $dst, $src1, $src2" %}
8937 size(4);
8938 ins_encode %{
8939 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8940 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8941 %}
8942 ins_pipe(pipe_class_default);
8943 %}
8944
8945 // Immediate And
8946 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8947 match(Set dst (AndI src1 src2));
8948 effect(KILL cr0);
8949
8950 format %{ "ANDI $dst, $src1, $src2" %}
8951 size(4);
8952 ins_encode %{
8953 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8954 // FIXME: avoid andi_ ?
8955 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8956 %}
8957 ins_pipe(pipe_class_default);
8958 %}
8959
8960 // Immediate And where the immediate is a negative power of 2.
8961 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8962 match(Set dst (AndI src1 src2));
8963 format %{ "ANDWI $dst, $src1, $src2" %}
8964 size(4);
8965 ins_encode %{
8966 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8967 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8968 %}
8969 ins_pipe(pipe_class_default);
8970 %}
8971
8972 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8973 match(Set dst (AndI src1 src2));
8974 format %{ "ANDWI $dst, $src1, $src2" %}
8975 size(4);
8976 ins_encode %{
8977 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8978 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8979 %}
8980 ins_pipe(pipe_class_default);
8981 %}
8982
8983 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8984 match(Set dst (AndI src1 src2));
8985 predicate(UseRotateAndMaskInstructionsPPC64);
8986 format %{ "ANDWI $dst, $src1, $src2" %}
8987 size(4);
8988 ins_encode %{
8989 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8990 __ rlwinm($dst$$Register, $src1$$Register, 0,
8991 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8992 %}
8993 ins_pipe(pipe_class_default);
8994 %}
8995
8996 // Register And Long
8997 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8998 match(Set dst (AndL src1 src2));
8999 ins_cost(DEFAULT_COST);
9000
9001 format %{ "AND $dst, $src1, $src2 \t// long" %}
9002 size(4);
9003 ins_encode %{
9004 // TODO: PPC port $archOpcode(ppc64Opcode_and);
9005 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9006 %}
9007 ins_pipe(pipe_class_default);
9008 %}
9009
9010 // Immediate And long
9011 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
9012 match(Set dst (AndL src1 src2));
9013 effect(KILL cr0);
9014 ins_cost(DEFAULT_COST);
9015
9016 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
9017 size(4);
9018 ins_encode %{
9019 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9020 // FIXME: avoid andi_ ?
9021 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9022 %}
9023 ins_pipe(pipe_class_default);
9024 %}
9025
9026 // Immediate And Long where the immediate is a negative power of 2.
9027 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
9028 match(Set dst (AndL src1 src2));
9029 format %{ "ANDDI $dst, $src1, $src2" %}
9030 size(4);
9031 ins_encode %{
9032 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9033 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9034 %}
9035 ins_pipe(pipe_class_default);
9036 %}
9037
9038 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9039 match(Set dst (AndL src1 src2));
9040 format %{ "ANDDI $dst, $src1, $src2" %}
9041 size(4);
9042 ins_encode %{
9043 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9044 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9045 %}
9046 ins_pipe(pipe_class_default);
9047 %}
9048
9049 // AndL + ConvL2I.
9050 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9051 match(Set dst (ConvL2I (AndL src1 src2)));
9052 ins_cost(DEFAULT_COST);
9053
9054 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
9055 size(4);
9056 ins_encode %{
9057 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9058 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9059 %}
9060 ins_pipe(pipe_class_default);
9061 %}
9062
9063 // Or Instructions
9064
9065 // Register Or
9066 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9067 match(Set dst (OrI src1 src2));
9068 format %{ "OR $dst, $src1, $src2" %}
9069 size(4);
9070 ins_encode %{
9071 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9072 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9073 %}
9074 ins_pipe(pipe_class_default);
9075 %}
9076
9077 // Expand does not work with above instruct. (??)
9078 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9079 // no match-rule
9080 effect(DEF dst, USE src1, USE src2);
9081 format %{ "OR $dst, $src1, $src2" %}
9082 size(4);
9083 ins_encode %{
9084 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9085 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9086 %}
9087 ins_pipe(pipe_class_default);
9088 %}
9089
9090 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9091 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9092 ins_cost(DEFAULT_COST*3);
9093
9094 expand %{
9095 // FIXME: we should do this in the ideal world.
9096 iRegIdst tmp1;
9097 iRegIdst tmp2;
9098 orI_reg_reg(tmp1, src1, src2);
9099 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9100 orI_reg_reg(dst, tmp1, tmp2);
9101 %}
9102 %}
9103
9104 // Immediate Or
9105 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9106 match(Set dst (OrI src1 src2));
9107 format %{ "ORI $dst, $src1, $src2" %}
9108 size(4);
9109 ins_encode %{
9110 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9111 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9112 %}
9113 ins_pipe(pipe_class_default);
9114 %}
9115
9116 // Register Or Long
9117 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9118 match(Set dst (OrL src1 src2));
9119 ins_cost(DEFAULT_COST);
9120
9121 size(4);
9122 format %{ "OR $dst, $src1, $src2 \t// long" %}
9123 ins_encode %{
9124 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9125 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9126 %}
9127 ins_pipe(pipe_class_default);
9128 %}
9129
9130 // OrL + ConvL2I.
9131 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9132 match(Set dst (ConvL2I (OrL src1 src2)));
9133 ins_cost(DEFAULT_COST);
9134
9135 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9136 size(4);
9137 ins_encode %{
9138 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9139 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9140 %}
9141 ins_pipe(pipe_class_default);
9142 %}
9143
9144 // Immediate Or long
9145 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9146 match(Set dst (OrL src1 con));
9147 ins_cost(DEFAULT_COST);
9148
9149 format %{ "ORI $dst, $src1, $con \t// long" %}
9150 size(4);
9151 ins_encode %{
9152 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9153 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9154 %}
9155 ins_pipe(pipe_class_default);
9156 %}
9157
9158 // Xor Instructions
9159
9160 // Register Xor
9161 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9162 match(Set dst (XorI src1 src2));
9163 format %{ "XOR $dst, $src1, $src2" %}
9164 size(4);
9165 ins_encode %{
9166 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9167 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9168 %}
9169 ins_pipe(pipe_class_default);
9170 %}
9171
9172 // Expand does not work with above instruct. (??)
9173 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9174 // no match-rule
9175 effect(DEF dst, USE src1, USE src2);
9176 format %{ "XOR $dst, $src1, $src2" %}
9177 size(4);
9178 ins_encode %{
9179 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9180 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9181 %}
9182 ins_pipe(pipe_class_default);
9183 %}
9184
9185 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9186 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9187 ins_cost(DEFAULT_COST*3);
9188
9189 expand %{
9190 // FIXME: we should do this in the ideal world.
9191 iRegIdst tmp1;
9192 iRegIdst tmp2;
9193 xorI_reg_reg(tmp1, src1, src2);
9194 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9195 xorI_reg_reg(dst, tmp1, tmp2);
9196 %}
9197 %}
9198
9199 // Immediate Xor
9200 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9201 match(Set dst (XorI src1 src2));
9202 format %{ "XORI $dst, $src1, $src2" %}
9203 size(4);
9204 ins_encode %{
9205 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9206 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9207 %}
9208 ins_pipe(pipe_class_default);
9209 %}
9210
9211 // Register Xor Long
9212 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9213 match(Set dst (XorL src1 src2));
9214 ins_cost(DEFAULT_COST);
9215
9216 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9217 size(4);
9218 ins_encode %{
9219 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9220 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9221 %}
9222 ins_pipe(pipe_class_default);
9223 %}
9224
9225 // XorL + ConvL2I.
9226 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9227 match(Set dst (ConvL2I (XorL src1 src2)));
9228 ins_cost(DEFAULT_COST);
9229
9230 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9231 size(4);
9232 ins_encode %{
9233 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9234 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9235 %}
9236 ins_pipe(pipe_class_default);
9237 %}
9238
9239 // Immediate Xor Long
9240 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9241 match(Set dst (XorL src1 src2));
9242 ins_cost(DEFAULT_COST);
9243
9244 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9245 size(4);
9246 ins_encode %{
9247 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9248 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9249 %}
9250 ins_pipe(pipe_class_default);
9251 %}
9252
9253 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9254 match(Set dst (XorI src1 src2));
9255 ins_cost(DEFAULT_COST);
9256
9257 format %{ "NOT $dst, $src1 ($src2)" %}
9258 size(4);
9259 ins_encode %{
9260 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9261 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9262 %}
9263 ins_pipe(pipe_class_default);
9264 %}
9265
9266 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9267 match(Set dst (XorL src1 src2));
9268 ins_cost(DEFAULT_COST);
9269
9270 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9271 size(4);
9272 ins_encode %{
9273 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9274 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9275 %}
9276 ins_pipe(pipe_class_default);
9277 %}
9278
9279 // And-complement
9280 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9281 match(Set dst (AndI (XorI src1 src2) src3));
9282 ins_cost(DEFAULT_COST);
9283
9284 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9285 size(4);
9286 ins_encode( enc_andc(dst, src3, src1) );
9287 ins_pipe(pipe_class_default);
9288 %}
9289
9290 // And-complement
9291 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9292 // no match-rule, false predicate
9293 effect(DEF dst, USE src1, USE src2);
9294 predicate(false);
9295
9296 format %{ "ANDC $dst, $src1, $src2" %}
9297 size(4);
9298 ins_encode %{
9299 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9300 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9301 %}
9302 ins_pipe(pipe_class_default);
9303 %}
9304
9305 //----------Moves between int/long and float/double----------------------------
9306 //
9307 // The following rules move values from int/long registers/stack-locations
9308 // to float/double registers/stack-locations and vice versa, without doing any
9309 // conversions. These rules are used to implement the bit-conversion methods
9310 // of java.lang.Float etc., e.g.
9311 // int floatToIntBits(float value)
9312 // float intBitsToFloat(int bits)
9313 //
9314 // Notes on the implementation on ppc64:
9315 // We only provide rules which move between a register and a stack-location,
9316 // because we always have to go through memory when moving between a float
9317 // register and an integer register.
9318
9319 //---------- Chain stack slots between similar types --------
9320
9321 // These are needed so that the rules below can match.
9322
9323 // Load integer from stack slot
9324 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9325 match(Set dst src);
9326 ins_cost(MEMORY_REF_COST);
9327
9328 format %{ "LWZ $dst, $src" %}
9329 size(4);
9330 ins_encode( enc_lwz(dst, src) );
9331 ins_pipe(pipe_class_memory);
9332 %}
9333
9334 // Store integer to stack slot
9335 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9336 match(Set dst src);
9337 ins_cost(MEMORY_REF_COST);
9338
9339 format %{ "STW $src, $dst \t// stk" %}
9340 size(4);
9341 ins_encode( enc_stw(src, dst) ); // rs=rt
9342 ins_pipe(pipe_class_memory);
9343 %}
9344
9345 // Load long from stack slot
9346 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9347 match(Set dst src);
9348 ins_cost(MEMORY_REF_COST);
9349
9350 format %{ "LD $dst, $src \t// long" %}
9351 size(4);
9352 ins_encode( enc_ld(dst, src) );
9353 ins_pipe(pipe_class_memory);
9354 %}
9355
9356 // Store long to stack slot
9357 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9358 match(Set dst src);
9359 ins_cost(MEMORY_REF_COST);
9360
9361 format %{ "STD $src, $dst \t// long" %}
9362 size(4);
9363 ins_encode( enc_std(src, dst) ); // rs=rt
9364 ins_pipe(pipe_class_memory);
9365 %}
9366
9367 //----------Moves between int and float
9368
9369 // Move float value from float stack-location to integer register.
9370 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9371 match(Set dst (MoveF2I src));
9372 ins_cost(MEMORY_REF_COST);
9373
9374 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9375 size(4);
9376 ins_encode( enc_lwz(dst, src) );
9377 ins_pipe(pipe_class_memory);
9378 %}
9379
9380 // Move float value from float register to integer stack-location.
9381 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9382 match(Set dst (MoveF2I src));
9383 ins_cost(MEMORY_REF_COST);
9384
9385 format %{ "STFS $src, $dst \t// MoveF2I" %}
9386 size(4);
9387 ins_encode( enc_stfs(src, dst) );
9388 ins_pipe(pipe_class_memory);
9389 %}
9390
9391 // Move integer value from integer stack-location to float register.
9392 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9393 match(Set dst (MoveI2F src));
9394 ins_cost(MEMORY_REF_COST);
9395
9396 format %{ "LFS $dst, $src \t// MoveI2F" %}
9397 size(4);
9398 ins_encode %{
9399 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9400 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9401 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9402 %}
9403 ins_pipe(pipe_class_memory);
9404 %}
9405
9406 // Move integer value from integer register to float stack-location.
9407 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9408 match(Set dst (MoveI2F src));
9409 ins_cost(MEMORY_REF_COST);
9410
9411 format %{ "STW $src, $dst \t// MoveI2F" %}
9412 size(4);
9413 ins_encode( enc_stw(src, dst) );
9414 ins_pipe(pipe_class_memory);
9415 %}
9416
9417 //----------Moves between long and float
9418
9419 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9420 // no match-rule, false predicate
9421 effect(DEF dst, USE src);
9422 predicate(false);
9423
9424 format %{ "storeD $src, $dst \t// STACK" %}
9425 size(4);
9426 ins_encode( enc_stfd(src, dst) );
9427 ins_pipe(pipe_class_default);
9428 %}
9429
9430 //----------Moves between long and double
9431
9432 // Move double value from double stack-location to long register.
9433 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9434 match(Set dst (MoveD2L src));
9435 ins_cost(MEMORY_REF_COST);
9436 size(4);
9437 format %{ "LD $dst, $src \t// MoveD2L" %}
9438 ins_encode( enc_ld(dst, src) );
9439 ins_pipe(pipe_class_memory);
9440 %}
9441
9442 // Move double value from double register to long stack-location.
9443 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9444 match(Set dst (MoveD2L src));
9445 effect(DEF dst, USE src);
9446 ins_cost(MEMORY_REF_COST);
9447
9448 format %{ "STFD $src, $dst \t// MoveD2L" %}
9449 size(4);
9450 ins_encode( enc_stfd(src, dst) );
9451 ins_pipe(pipe_class_memory);
9452 %}
9453
9454 // Move long value from long stack-location to double register.
9455 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9456 match(Set dst (MoveL2D src));
9457 ins_cost(MEMORY_REF_COST);
9458
9459 format %{ "LFD $dst, $src \t// MoveL2D" %}
9460 size(4);
9461 ins_encode( enc_lfd(dst, src) );
9462 ins_pipe(pipe_class_memory);
9463 %}
9464
9465 // Move long value from long register to double stack-location.
9466 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9467 match(Set dst (MoveL2D src));
9468 ins_cost(MEMORY_REF_COST);
9469
9470 format %{ "STD $src, $dst \t// MoveL2D" %}
9471 size(4);
9472 ins_encode( enc_std(src, dst) );
9473 ins_pipe(pipe_class_memory);
9474 %}
9475
9476 //----------Register Move Instructions-----------------------------------------
9477
9478 // Replicate for Superword
9479
9480 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9481 predicate(false);
9482 effect(DEF dst, USE src);
9483
9484 format %{ "MR $dst, $src \t// replicate " %}
9485 // variable size, 0 or 4.
9486 ins_encode %{
9487 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9488 __ mr_if_needed($dst$$Register, $src$$Register);
9489 %}
9490 ins_pipe(pipe_class_default);
9491 %}
9492
9493 //----------Cast instructions (Java-level type cast)---------------------------
9494
9495 // Cast Long to Pointer for unsafe natives.
9496 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9497 match(Set dst (CastX2P src));
9498
9499 format %{ "MR $dst, $src \t// Long->Ptr" %}
9500 // variable size, 0 or 4.
9501 ins_encode %{
9502 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9503 __ mr_if_needed($dst$$Register, $src$$Register);
9504 %}
9505 ins_pipe(pipe_class_default);
9506 %}
9507
9508 // Cast Pointer to Long for unsafe natives.
9509 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9510 match(Set dst (CastP2X src));
9511
9512 format %{ "MR $dst, $src \t// Ptr->Long" %}
9513 // variable size, 0 or 4.
9514 ins_encode %{
9515 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9516 __ mr_if_needed($dst$$Register, $src$$Register);
9517 %}
9518 ins_pipe(pipe_class_default);
9519 %}
9520
9521 instruct castPP(iRegPdst dst) %{
9522 match(Set dst (CastPP dst));
9523 format %{ " -- \t// castPP of $dst" %}
9524 size(0);
9525 ins_encode( /*empty*/ );
9526 ins_pipe(pipe_class_default);
9527 %}
9528
9529 instruct castII(iRegIdst dst) %{
9530 match(Set dst (CastII dst));
9531 format %{ " -- \t// castII of $dst" %}
9532 size(0);
9533 ins_encode( /*empty*/ );
9534 ins_pipe(pipe_class_default);
9535 %}
9536
9537 instruct checkCastPP(iRegPdst dst) %{
9538 match(Set dst (CheckCastPP dst));
9539 format %{ " -- \t// checkcastPP of $dst" %}
9540 size(0);
9541 ins_encode( /*empty*/ );
9542 ins_pipe(pipe_class_default);
9543 %}
9544
9545 //----------Convert instructions-----------------------------------------------
9546
9547 // Convert to boolean.
9548
9549 // int_to_bool(src) : { 1 if src != 0
9550 // { 0 else
9551 //
9552 // strategy:
9553 // 1) Count leading zeros of 32 bit-value src,
9554 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9555 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9556 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9557
9558 // convI2Bool
9559 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9560 match(Set dst (Conv2B src));
9561 predicate(UseCountLeadingZerosInstructionsPPC64);
9562 ins_cost(DEFAULT_COST);
9563
9564 expand %{
9565 immI shiftAmount %{ 0x5 %}
9566 uimmI16 mask %{ 0x1 %}
9567 iRegIdst tmp1;
9568 iRegIdst tmp2;
9569 countLeadingZerosI(tmp1, src);
9570 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9571 xorI_reg_uimm16(dst, tmp2, mask);
9572 %}
9573 %}
9574
9575 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9576 match(Set dst (Conv2B src));
9577 effect(TEMP crx);
9578 predicate(!UseCountLeadingZerosInstructionsPPC64);
9579 ins_cost(DEFAULT_COST);
9580
9581 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9582 "LI $dst, #0\n\t"
9583 "BEQ $crx, done\n\t"
9584 "LI $dst, #1\n"
9585 "done:" %}
9586 size(16);
9587 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9588 ins_pipe(pipe_class_compare);
9589 %}
9590
9591 // ConvI2B + XorI
9592 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9593 match(Set dst (XorI (Conv2B src) mask));
9594 predicate(UseCountLeadingZerosInstructionsPPC64);
9595 ins_cost(DEFAULT_COST);
9596
9597 expand %{
9598 immI shiftAmount %{ 0x5 %}
9599 iRegIdst tmp1;
9600 countLeadingZerosI(tmp1, src);
9601 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9602 %}
9603 %}
9604
9605 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9606 match(Set dst (XorI (Conv2B src) mask));
9607 effect(TEMP crx);
9608 predicate(!UseCountLeadingZerosInstructionsPPC64);
9609 ins_cost(DEFAULT_COST);
9610
9611 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9612 "LI $dst, #1\n\t"
9613 "BEQ $crx, done\n\t"
9614 "LI $dst, #0\n"
9615 "done:" %}
9616 size(16);
9617 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9618 ins_pipe(pipe_class_compare);
9619 %}
9620
9621 // AndI 0b0..010..0 + ConvI2B
9622 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9623 match(Set dst (Conv2B (AndI src mask)));
9624 predicate(UseRotateAndMaskInstructionsPPC64);
9625 ins_cost(DEFAULT_COST);
9626
9627 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9628 size(4);
9629 ins_encode %{
9630 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9631 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9632 %}
9633 ins_pipe(pipe_class_default);
9634 %}
9635
9636 // Convert pointer to boolean.
9637 //
9638 // ptr_to_bool(src) : { 1 if src != 0
9639 // { 0 else
9640 //
9641 // strategy:
9642 // 1) Count leading zeros of 64 bit-value src,
9643 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9644 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9645 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9646
9647 // ConvP2B
9648 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9649 match(Set dst (Conv2B src));
9650 predicate(UseCountLeadingZerosInstructionsPPC64);
9651 ins_cost(DEFAULT_COST);
9652
9653 expand %{
9654 immI shiftAmount %{ 0x6 %}
9655 uimmI16 mask %{ 0x1 %}
9656 iRegIdst tmp1;
9657 iRegIdst tmp2;
9658 countLeadingZerosP(tmp1, src);
9659 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9660 xorI_reg_uimm16(dst, tmp2, mask);
9661 %}
9662 %}
9663
9664 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9665 match(Set dst (Conv2B src));
9666 effect(TEMP crx);
9667 predicate(!UseCountLeadingZerosInstructionsPPC64);
9668 ins_cost(DEFAULT_COST);
9669
9670 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9671 "LI $dst, #0\n\t"
9672 "BEQ $crx, done\n\t"
9673 "LI $dst, #1\n"
9674 "done:" %}
9675 size(16);
9676 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9677 ins_pipe(pipe_class_compare);
9678 %}
9679
9680 // ConvP2B + XorI
9681 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9682 match(Set dst (XorI (Conv2B src) mask));
9683 predicate(UseCountLeadingZerosInstructionsPPC64);
9684 ins_cost(DEFAULT_COST);
9685
9686 expand %{
9687 immI shiftAmount %{ 0x6 %}
9688 iRegIdst tmp1;
9689 countLeadingZerosP(tmp1, src);
9690 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9691 %}
9692 %}
9693
9694 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9695 match(Set dst (XorI (Conv2B src) mask));
9696 effect(TEMP crx);
9697 predicate(!UseCountLeadingZerosInstructionsPPC64);
9698 ins_cost(DEFAULT_COST);
9699
9700 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9701 "LI $dst, #1\n\t"
9702 "BEQ $crx, done\n\t"
9703 "LI $dst, #0\n"
9704 "done:" %}
9705 size(16);
9706 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9707 ins_pipe(pipe_class_compare);
9708 %}
9709
9710 // if src1 < src2, return -1 else return 0
9711 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9712 match(Set dst (CmpLTMask src1 src2));
9713 ins_cost(DEFAULT_COST*4);
9714
9715 expand %{
9716 iRegLdst src1s;
9717 iRegLdst src2s;
9718 iRegLdst diff;
9719 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9720 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9721 subL_reg_reg(diff, src1s, src2s);
9722 // Need to consider >=33 bit result, therefore we need signmaskL.
9723 signmask64I_regL(dst, diff);
9724 %}
9725 %}
9726
9727 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9728 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9729 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9730 size(4);
9731 ins_encode %{
9732 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9733 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9734 %}
9735 ins_pipe(pipe_class_default);
9736 %}
9737
9738 //----------Arithmetic Conversion Instructions---------------------------------
9739
9740 // Convert to Byte -- nop
9741 // Convert to Short -- nop
9742
9743 // Convert to Int
9744
9745 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9746 match(Set dst (RShiftI (LShiftI src amount) amount));
9747 format %{ "EXTSB $dst, $src \t// byte->int" %}
9748 size(4);
9749 ins_encode %{
9750 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9751 __ extsb($dst$$Register, $src$$Register);
9752 %}
9753 ins_pipe(pipe_class_default);
9754 %}
9755
9756 // LShiftI 16 + RShiftI 16 converts short to int.
9757 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9758 match(Set dst (RShiftI (LShiftI src amount) amount));
9759 format %{ "EXTSH $dst, $src \t// short->int" %}
9760 size(4);
9761 ins_encode %{
9762 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9763 __ extsh($dst$$Register, $src$$Register);
9764 %}
9765 ins_pipe(pipe_class_default);
9766 %}
9767
9768 // ConvL2I + ConvI2L: Sign extend int in long register.
9769 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9770 match(Set dst (ConvI2L (ConvL2I src)));
9771
9772 format %{ "EXTSW $dst, $src \t// long->long" %}
9773 size(4);
9774 ins_encode %{
9775 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9776 __ extsw($dst$$Register, $src$$Register);
9777 %}
9778 ins_pipe(pipe_class_default);
9779 %}
9780
9781 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9782 match(Set dst (ConvL2I src));
9783 format %{ "MR $dst, $src \t// long->int" %}
9784 // variable size, 0 or 4
9785 ins_encode %{
9786 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9787 __ mr_if_needed($dst$$Register, $src$$Register);
9788 %}
9789 ins_pipe(pipe_class_default);
9790 %}
9791
9792 instruct convD2IRaw_regD(regD dst, regD src) %{
9793 // no match-rule, false predicate
9794 effect(DEF dst, USE src);
9795 predicate(false);
9796
9797 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9798 size(4);
9799 ins_encode %{
9800 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9801 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9802 %}
9803 ins_pipe(pipe_class_default);
9804 %}
9805
9806 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9807 // no match-rule, false predicate
9808 effect(DEF dst, USE crx, USE src);
9809 predicate(false);
9810
9811 ins_variable_size_depending_on_alignment(true);
9812
9813 format %{ "cmovI $crx, $dst, $src" %}
9814 // Worst case is branch + move + stop, no stop without scheduler.
9815 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9816 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9817 ins_pipe(pipe_class_default);
9818 %}
9819
9820 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9821 // no match-rule, false predicate
9822 effect(DEF dst, USE crx, USE mem);
9823 predicate(false);
9824
9825 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9826 postalloc_expand %{
9827 //
9828 // replaces
9829 //
9830 // region dst crx mem
9831 // \ | | /
9832 // dst=cmovI_bso_stackSlotL_conLvalue0
9833 //
9834 // with
9835 //
9836 // region dst
9837 // \ /
9838 // dst=loadConI16(0)
9839 // |
9840 // ^ region dst crx mem
9841 // | \ | | /
9842 // dst=cmovI_bso_stackSlotL
9843 //
9844
9845 // Create new nodes.
9846 MachNode *m1 = new loadConI16Node();
9847 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9848
9849 // inputs for new nodes
9850 m1->add_req(n_region);
9851 m2->add_req(n_region, n_crx, n_mem);
9852
9853 // precedences for new nodes
9854 m2->add_prec(m1);
9855
9856 // operands for new nodes
9857 m1->_opnds[0] = op_dst;
9858 m1->_opnds[1] = new immI16Oper(0);
9859
9860 m2->_opnds[0] = op_dst;
9861 m2->_opnds[1] = op_crx;
9862 m2->_opnds[2] = op_mem;
9863
9864 // registers for new nodes
9865 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9866 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9867
9868 // Insert new nodes.
9869 nodes->push(m1);
9870 nodes->push(m2);
9871 %}
9872 %}
9873
9874 // Double to Int conversion, NaN is mapped to 0.
9875 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9876 match(Set dst (ConvD2I src));
9877 ins_cost(DEFAULT_COST);
9878
9879 expand %{
9880 regD tmpD;
9881 stackSlotL tmpS;
9882 flagsReg crx;
9883 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9884 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9885 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9886 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9887 %}
9888 %}
9889
9890 instruct convF2IRaw_regF(regF dst, regF src) %{
9891 // no match-rule, false predicate
9892 effect(DEF dst, USE src);
9893 predicate(false);
9894
9895 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9896 size(4);
9897 ins_encode %{
9898 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9899 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9900 %}
9901 ins_pipe(pipe_class_default);
9902 %}
9903
9904 // Float to Int conversion, NaN is mapped to 0.
9905 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9906 match(Set dst (ConvF2I src));
9907 ins_cost(DEFAULT_COST);
9908
9909 expand %{
9910 regF tmpF;
9911 stackSlotL tmpS;
9912 flagsReg crx;
9913 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9914 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9915 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9916 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9917 %}
9918 %}
9919
9920 // Convert to Long
9921
9922 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9923 match(Set dst (ConvI2L src));
9924 format %{ "EXTSW $dst, $src \t// int->long" %}
9925 size(4);
9926 ins_encode %{
9927 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9928 __ extsw($dst$$Register, $src$$Register);
9929 %}
9930 ins_pipe(pipe_class_default);
9931 %}
9932
9933 // Zero-extend: convert unsigned int to long (convUI2L).
9934 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9935 match(Set dst (AndL (ConvI2L src) mask));
9936 ins_cost(DEFAULT_COST);
9937
9938 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9939 size(4);
9940 ins_encode %{
9941 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9942 __ clrldi($dst$$Register, $src$$Register, 32);
9943 %}
9944 ins_pipe(pipe_class_default);
9945 %}
9946
9947 // Zero-extend: convert unsigned int to long in long register.
9948 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9949 match(Set dst (AndL src mask));
9950 ins_cost(DEFAULT_COST);
9951
9952 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9953 size(4);
9954 ins_encode %{
9955 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9956 __ clrldi($dst$$Register, $src$$Register, 32);
9957 %}
9958 ins_pipe(pipe_class_default);
9959 %}
9960
9961 instruct convF2LRaw_regF(regF dst, regF src) %{
9962 // no match-rule, false predicate
9963 effect(DEF dst, USE src);
9964 predicate(false);
9965
9966 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9967 size(4);
9968 ins_encode %{
9969 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9970 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9971 %}
9972 ins_pipe(pipe_class_default);
9973 %}
9974
9975 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9976 // no match-rule, false predicate
9977 effect(DEF dst, USE crx, USE src);
9978 predicate(false);
9979
9980 ins_variable_size_depending_on_alignment(true);
9981
9982 format %{ "cmovL $crx, $dst, $src" %}
9983 // Worst case is branch + move + stop, no stop without scheduler.
9984 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9985 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9986 ins_pipe(pipe_class_default);
9987 %}
9988
9989 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9990 // no match-rule, false predicate
9991 effect(DEF dst, USE crx, USE mem);
9992 predicate(false);
9993
9994 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9995 postalloc_expand %{
9996 //
9997 // replaces
9998 //
9999 // region dst crx mem
10000 // \ | | /
10001 // dst=cmovL_bso_stackSlotL_conLvalue0
10002 //
10003 // with
10004 //
10005 // region dst
10006 // \ /
10007 // dst=loadConL16(0)
10008 // |
10009 // ^ region dst crx mem
10010 // | \ | | /
10011 // dst=cmovL_bso_stackSlotL
10012 //
10013
10014 // Create new nodes.
10015 MachNode *m1 = new loadConL16Node();
10016 MachNode *m2 = new cmovL_bso_stackSlotLNode();
10017
10018 // inputs for new nodes
10019 m1->add_req(n_region);
10020 m2->add_req(n_region, n_crx, n_mem);
10021 m2->add_prec(m1);
10022
10023 // operands for new nodes
10024 m1->_opnds[0] = op_dst;
10025 m1->_opnds[1] = new immL16Oper(0);
10026 m2->_opnds[0] = op_dst;
10027 m2->_opnds[1] = op_crx;
10028 m2->_opnds[2] = op_mem;
10029
10030 // registers for new nodes
10031 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10032 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10033
10034 // Insert new nodes.
10035 nodes->push(m1);
10036 nodes->push(m2);
10037 %}
10038 %}
10039
10040 // Float to Long conversion, NaN is mapped to 0.
10041 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10042 match(Set dst (ConvF2L src));
10043 ins_cost(DEFAULT_COST);
10044
10045 expand %{
10046 regF tmpF;
10047 stackSlotL tmpS;
10048 flagsReg crx;
10049 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10050 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
10051 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
10052 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10053 %}
10054 %}
10055
10056 instruct convD2LRaw_regD(regD dst, regD src) %{
10057 // no match-rule, false predicate
10058 effect(DEF dst, USE src);
10059 predicate(false);
10060
10061 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10062 size(4);
10063 ins_encode %{
10064 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10065 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10066 %}
10067 ins_pipe(pipe_class_default);
10068 %}
10069
10070 // Double to Long conversion, NaN is mapped to 0.
10071 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10072 match(Set dst (ConvD2L src));
10073 ins_cost(DEFAULT_COST);
10074
10075 expand %{
10076 regD tmpD;
10077 stackSlotL tmpS;
10078 flagsReg crx;
10079 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10080 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10081 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10082 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10083 %}
10084 %}
10085
10086 // Convert to Float
10087
10088 // Placed here as needed in expand.
10089 instruct convL2DRaw_regD(regD dst, regD src) %{
10090 // no match-rule, false predicate
10091 effect(DEF dst, USE src);
10092 predicate(false);
10093
10094 format %{ "FCFID $dst, $src \t// convL2D" %}
10095 size(4);
10096 ins_encode %{
10097 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10098 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10099 %}
10100 ins_pipe(pipe_class_default);
10101 %}
10102
10103 // Placed here as needed in expand.
10104 instruct convD2F_reg(regF dst, regD src) %{
10105 match(Set dst (ConvD2F src));
10106 format %{ "FRSP $dst, $src \t// convD2F" %}
10107 size(4);
10108 ins_encode %{
10109 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10110 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10111 %}
10112 ins_pipe(pipe_class_default);
10113 %}
10114
10115 // Integer to Float conversion.
10116 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10117 match(Set dst (ConvI2F src));
10118 predicate(!VM_Version::has_fcfids());
10119 ins_cost(DEFAULT_COST);
10120
10121 expand %{
10122 iRegLdst tmpL;
10123 stackSlotL tmpS;
10124 regD tmpD;
10125 regD tmpD2;
10126 convI2L_reg(tmpL, src); // Sign-extension int to long.
10127 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10128 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10129 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10130 convD2F_reg(dst, tmpD2); // Convert double to float.
10131 %}
10132 %}
10133
10134 instruct convL2FRaw_regF(regF dst, regD src) %{
10135 // no match-rule, false predicate
10136 effect(DEF dst, USE src);
10137 predicate(false);
10138
10139 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10140 size(4);
10141 ins_encode %{
10142 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10143 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10144 %}
10145 ins_pipe(pipe_class_default);
10146 %}
10147
10148 // Integer to Float conversion. Special version for Power7.
10149 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10150 match(Set dst (ConvI2F src));
10151 predicate(VM_Version::has_fcfids());
10152 ins_cost(DEFAULT_COST);
10153
10154 expand %{
10155 iRegLdst tmpL;
10156 stackSlotL tmpS;
10157 regD tmpD;
10158 convI2L_reg(tmpL, src); // Sign-extension int to long.
10159 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10160 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10161 convL2FRaw_regF(dst, tmpD); // Convert to float.
10162 %}
10163 %}
10164
10165 // L2F to avoid runtime call.
10166 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10167 match(Set dst (ConvL2F src));
10168 predicate(VM_Version::has_fcfids());
10169 ins_cost(DEFAULT_COST);
10170
10171 expand %{
10172 stackSlotL tmpS;
10173 regD tmpD;
10174 regL_to_stkL(tmpS, src); // Store long to stack.
10175 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10176 convL2FRaw_regF(dst, tmpD); // Convert to float.
10177 %}
10178 %}
10179
10180 // Moved up as used in expand.
10181 //instruct convD2F_reg(regF dst, regD src) %{%}
10182
10183 // Convert to Double
10184
10185 // Integer to Double conversion.
10186 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10187 match(Set dst (ConvI2D src));
10188 ins_cost(DEFAULT_COST);
10189
10190 expand %{
10191 iRegLdst tmpL;
10192 stackSlotL tmpS;
10193 regD tmpD;
10194 convI2L_reg(tmpL, src); // Sign-extension int to long.
10195 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10196 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10197 convL2DRaw_regD(dst, tmpD); // Convert to double.
10198 %}
10199 %}
10200
10201 // Long to Double conversion
10202 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10203 match(Set dst (ConvL2D src));
10204 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10205
10206 expand %{
10207 regD tmpD;
10208 moveL2D_stack_reg(tmpD, src);
10209 convL2DRaw_regD(dst, tmpD);
10210 %}
10211 %}
10212
10213 instruct convF2D_reg(regD dst, regF src) %{
10214 match(Set dst (ConvF2D src));
10215 format %{ "FMR $dst, $src \t// float->double" %}
10216 // variable size, 0 or 4
10217 ins_encode %{
10218 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10219 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10220 %}
10221 ins_pipe(pipe_class_default);
10222 %}
10223
10224 //----------Control Flow Instructions------------------------------------------
10225 // Compare Instructions
10226
10227 // Compare Integers
10228 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10229 match(Set crx (CmpI src1 src2));
10230 size(4);
10231 format %{ "CMPW $crx, $src1, $src2" %}
10232 ins_encode %{
10233 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10234 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10235 %}
10236 ins_pipe(pipe_class_compare);
10237 %}
10238
10239 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10240 match(Set crx (CmpI src1 src2));
10241 format %{ "CMPWI $crx, $src1, $src2" %}
10242 size(4);
10243 ins_encode %{
10244 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10245 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10246 %}
10247 ins_pipe(pipe_class_compare);
10248 %}
10249
10250 // (src1 & src2) == 0?
10251 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10252 match(Set cr0 (CmpI (AndI src1 src2) zero));
10253 // r0 is killed
10254 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10255 size(4);
10256 ins_encode %{
10257 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10258 // FIXME: avoid andi_ ?
10259 __ andi_(R0, $src1$$Register, $src2$$constant);
10260 %}
10261 ins_pipe(pipe_class_compare);
10262 %}
10263
10264 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10265 match(Set crx (CmpL src1 src2));
10266 format %{ "CMPD $crx, $src1, $src2" %}
10267 size(4);
10268 ins_encode %{
10269 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10270 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10271 %}
10272 ins_pipe(pipe_class_compare);
10273 %}
10274
10275 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10276 match(Set crx (CmpL src1 src2));
10277 format %{ "CMPDI $crx, $src1, $src2" %}
10278 size(4);
10279 ins_encode %{
10280 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10281 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10282 %}
10283 ins_pipe(pipe_class_compare);
10284 %}
10285
10286 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10287 match(Set cr0 (CmpL (AndL src1 src2) zero));
10288 // r0 is killed
10289 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10290 size(4);
10291 ins_encode %{
10292 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10293 __ and_(R0, $src1$$Register, $src2$$Register);
10294 %}
10295 ins_pipe(pipe_class_compare);
10296 %}
10297
10298 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10299 match(Set cr0 (CmpL (AndL src1 src2) zero));
10300 // r0 is killed
10301 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10302 size(4);
10303 ins_encode %{
10304 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10305 // FIXME: avoid andi_ ?
10306 __ andi_(R0, $src1$$Register, $src2$$constant);
10307 %}
10308 ins_pipe(pipe_class_compare);
10309 %}
10310
10311 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10312 // no match-rule, false predicate
10313 effect(DEF dst, USE crx);
10314 predicate(false);
10315
10316 ins_variable_size_depending_on_alignment(true);
10317
10318 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10319 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10320 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10321 ins_encode %{
10322 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10323 Label done;
10324 // li(Rdst, 0); // equal -> 0
10325 __ beq($crx$$CondRegister, done);
10326 __ li($dst$$Register, 1); // greater -> +1
10327 __ bgt($crx$$CondRegister, done);
10328 __ li($dst$$Register, -1); // unordered or less -> -1
10329 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10330 __ bind(done);
10331 %}
10332 ins_pipe(pipe_class_compare);
10333 %}
10334
10335 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10336 // no match-rule, false predicate
10337 effect(DEF dst, USE crx);
10338 predicate(false);
10339
10340 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10341 postalloc_expand %{
10342 //
10343 // replaces
10344 //
10345 // region crx
10346 // \ |
10347 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10348 //
10349 // with
10350 //
10351 // region
10352 // \
10353 // dst=loadConI16(0)
10354 // |
10355 // ^ region crx
10356 // | \ |
10357 // dst=cmovI_conIvalueMinus1_conIvalue1
10358 //
10359
10360 // Create new nodes.
10361 MachNode *m1 = new loadConI16Node();
10362 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10363
10364 // inputs for new nodes
10365 m1->add_req(n_region);
10366 m2->add_req(n_region, n_crx);
10367 m2->add_prec(m1);
10368
10369 // operands for new nodes
10370 m1->_opnds[0] = op_dst;
10371 m1->_opnds[1] = new immI16Oper(0);
10372 m2->_opnds[0] = op_dst;
10373 m2->_opnds[1] = op_crx;
10374
10375 // registers for new nodes
10376 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10377 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10378
10379 // Insert new nodes.
10380 nodes->push(m1);
10381 nodes->push(m2);
10382 %}
10383 %}
10384
10385 // Manifest a CmpL3 result in an integer register. Very painful.
10386 // This is the test to avoid.
10387 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10388 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10389 match(Set dst (CmpL3 src1 src2));
10390 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10391
10392 expand %{
10393 flagsReg tmp1;
10394 cmpL_reg_reg(tmp1, src1, src2);
10395 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10396 %}
10397 %}
10398
10399 // Implicit range checks.
10400 // A range check in the ideal world has one of the following shapes:
10401 // - (If le (CmpU length index)), (IfTrue throw exception)
10402 // - (If lt (CmpU index length)), (IfFalse throw exception)
10403 //
10404 // Match range check 'If le (CmpU length index)'.
10405 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10406 match(If cmp (CmpU src_length index));
10407 effect(USE labl);
10408 predicate(TrapBasedRangeChecks &&
10409 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10410 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10411 (Matcher::branches_to_uncommon_trap(_leaf)));
10412
10413 ins_is_TrapBasedCheckNode(true);
10414
10415 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10416 size(4);
10417 ins_encode %{
10418 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10419 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10420 __ trap_range_check_le($src_length$$Register, $index$$constant);
10421 } else {
10422 // Both successors are uncommon traps, probability is 0.
10423 // Node got flipped during fixup flow.
10424 assert($cmp$$cmpcode == 0x9, "must be greater");
10425 __ trap_range_check_g($src_length$$Register, $index$$constant);
10426 }
10427 %}
10428 ins_pipe(pipe_class_trap);
10429 %}
10430
10431 // Match range check 'If lt (CmpU index length)'.
10432 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10433 match(If cmp (CmpU src_index src_length));
10434 effect(USE labl);
10435 predicate(TrapBasedRangeChecks &&
10436 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10437 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10438 (Matcher::branches_to_uncommon_trap(_leaf)));
10439
10440 ins_is_TrapBasedCheckNode(true);
10441
10442 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10443 size(4);
10444 ins_encode %{
10445 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10446 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10447 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10448 } else {
10449 // Both successors are uncommon traps, probability is 0.
10450 // Node got flipped during fixup flow.
10451 assert($cmp$$cmpcode == 0x8, "must be less");
10452 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10453 }
10454 %}
10455 ins_pipe(pipe_class_trap);
10456 %}
10457
10458 // Match range check 'If lt (CmpU index length)'.
10459 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10460 match(If cmp (CmpU src_index length));
10461 effect(USE labl);
10462 predicate(TrapBasedRangeChecks &&
10463 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10464 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10465 (Matcher::branches_to_uncommon_trap(_leaf)));
10466
10467 ins_is_TrapBasedCheckNode(true);
10468
10469 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10470 size(4);
10471 ins_encode %{
10472 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10473 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10474 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10475 } else {
10476 // Both successors are uncommon traps, probability is 0.
10477 // Node got flipped during fixup flow.
10478 assert($cmp$$cmpcode == 0x8, "must be less");
10479 __ trap_range_check_l($src_index$$Register, $length$$constant);
10480 }
10481 %}
10482 ins_pipe(pipe_class_trap);
10483 %}
10484
10485 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10486 match(Set crx (CmpU src1 src2));
10487 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10488 size(4);
10489 ins_encode %{
10490 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10491 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10492 %}
10493 ins_pipe(pipe_class_compare);
10494 %}
10495
10496 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10497 match(Set crx (CmpU src1 src2));
10498 size(4);
10499 format %{ "CMPLWI $crx, $src1, $src2" %}
10500 ins_encode %{
10501 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10502 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10503 %}
10504 ins_pipe(pipe_class_compare);
10505 %}
10506
10507 // Implicit zero checks (more implicit null checks).
10508 // No constant pool entries required.
10509 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10510 match(If cmp (CmpN value zero));
10511 effect(USE labl);
10512 predicate(TrapBasedNullChecks &&
10513 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10514 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10515 Matcher::branches_to_uncommon_trap(_leaf));
10516 ins_cost(1);
10517
10518 ins_is_TrapBasedCheckNode(true);
10519
10520 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10521 size(4);
10522 ins_encode %{
10523 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10524 if ($cmp$$cmpcode == 0xA) {
10525 __ trap_null_check($value$$Register);
10526 } else {
10527 // Both successors are uncommon traps, probability is 0.
10528 // Node got flipped during fixup flow.
10529 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10530 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10531 }
10532 %}
10533 ins_pipe(pipe_class_trap);
10534 %}
10535
10536 // Compare narrow oops.
10537 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10538 match(Set crx (CmpN src1 src2));
10539
10540 size(4);
10541 ins_cost(2);
10542 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10543 ins_encode %{
10544 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10545 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10546 %}
10547 ins_pipe(pipe_class_compare);
10548 %}
10549
10550 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10551 match(Set crx (CmpN src1 src2));
10552 // Make this more expensive than zeroCheckN_iReg_imm0.
10553 ins_cost(2);
10554
10555 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10556 size(4);
10557 ins_encode %{
10558 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10559 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10560 %}
10561 ins_pipe(pipe_class_compare);
10562 %}
10563
10564 // Implicit zero checks (more implicit null checks).
10565 // No constant pool entries required.
10566 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10567 match(If cmp (CmpP value zero));
10568 effect(USE labl);
10569 predicate(TrapBasedNullChecks &&
10570 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10571 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10572 Matcher::branches_to_uncommon_trap(_leaf));
10573 ins_cost(1); // Should not be cheaper than zeroCheckN.
10574
10575 ins_is_TrapBasedCheckNode(true);
10576
10577 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10578 size(4);
10579 ins_encode %{
10580 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10581 if ($cmp$$cmpcode == 0xA) {
10582 __ trap_null_check($value$$Register);
10583 } else {
10584 // Both successors are uncommon traps, probability is 0.
10585 // Node got flipped during fixup flow.
10586 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10587 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10588 }
10589 %}
10590 ins_pipe(pipe_class_trap);
10591 %}
10592
10593 // Compare Pointers
10594 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10595 match(Set crx (CmpP src1 src2));
10596 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10597 size(4);
10598 ins_encode %{
10599 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10600 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10601 %}
10602 ins_pipe(pipe_class_compare);
10603 %}
10604
10605 // Used in postalloc expand.
10606 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10607 // This match rule prevents reordering of node before a safepoint.
10608 // This only makes sense if this instructions is used exclusively
10609 // for the expansion of EncodeP!
10610 match(Set crx (CmpP src1 src2));
10611 predicate(false);
10612
10613 format %{ "CMPDI $crx, $src1, $src2" %}
10614 size(4);
10615 ins_encode %{
10616 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10617 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10618 %}
10619 ins_pipe(pipe_class_compare);
10620 %}
10621
10622 //----------Float Compares----------------------------------------------------
10623
10624 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10625 // no match-rule, false predicate
10626 effect(DEF crx, USE src1, USE src2);
10627 predicate(false);
10628
10629 format %{ "cmpFUrd $crx, $src1, $src2" %}
10630 size(4);
10631 ins_encode %{
10632 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10633 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10634 %}
10635 ins_pipe(pipe_class_default);
10636 %}
10637
10638 instruct cmov_bns_less(flagsReg crx) %{
10639 // no match-rule, false predicate
10640 effect(DEF crx);
10641 predicate(false);
10642
10643 ins_variable_size_depending_on_alignment(true);
10644
10645 format %{ "cmov $crx" %}
10646 // Worst case is branch + move + stop, no stop without scheduler.
10647 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10648 ins_encode %{
10649 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10650 Label done;
10651 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10652 __ li(R0, 0);
10653 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10654 // TODO PPC port __ endgroup_if_needed(_size == 16);
10655 __ bind(done);
10656 %}
10657 ins_pipe(pipe_class_default);
10658 %}
10659
10660 // Compare floating, generate condition code.
10661 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10662 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10663 //
10664 // The following code sequence occurs a lot in mpegaudio:
10665 //
10666 // block BXX:
10667 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10668 // cmpFUrd CCR6, F11, F9
10669 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10670 // cmov CCR6
10671 // 8: instruct branchConSched:
10672 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10673 match(Set crx (CmpF src1 src2));
10674 ins_cost(DEFAULT_COST+BRANCH_COST);
10675
10676 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10677 postalloc_expand %{
10678 //
10679 // replaces
10680 //
10681 // region src1 src2
10682 // \ | |
10683 // crx=cmpF_reg_reg
10684 //
10685 // with
10686 //
10687 // region src1 src2
10688 // \ | |
10689 // crx=cmpFUnordered_reg_reg
10690 // |
10691 // ^ region
10692 // | \
10693 // crx=cmov_bns_less
10694 //
10695
10696 // Create new nodes.
10697 MachNode *m1 = new cmpFUnordered_reg_regNode();
10698 MachNode *m2 = new cmov_bns_lessNode();
10699
10700 // inputs for new nodes
10701 m1->add_req(n_region, n_src1, n_src2);
10702 m2->add_req(n_region);
10703 m2->add_prec(m1);
10704
10705 // operands for new nodes
10706 m1->_opnds[0] = op_crx;
10707 m1->_opnds[1] = op_src1;
10708 m1->_opnds[2] = op_src2;
10709 m2->_opnds[0] = op_crx;
10710
10711 // registers for new nodes
10712 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10713 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10714
10715 // Insert new nodes.
10716 nodes->push(m1);
10717 nodes->push(m2);
10718 %}
10719 %}
10720
10721 // Compare float, generate -1,0,1
10722 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10723 match(Set dst (CmpF3 src1 src2));
10724 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10725
10726 expand %{
10727 flagsReg tmp1;
10728 cmpFUnordered_reg_reg(tmp1, src1, src2);
10729 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10730 %}
10731 %}
10732
10733 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10734 // no match-rule, false predicate
10735 effect(DEF crx, USE src1, USE src2);
10736 predicate(false);
10737
10738 format %{ "cmpFUrd $crx, $src1, $src2" %}
10739 size(4);
10740 ins_encode %{
10741 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10742 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10743 %}
10744 ins_pipe(pipe_class_default);
10745 %}
10746
10747 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10748 match(Set crx (CmpD src1 src2));
10749 ins_cost(DEFAULT_COST+BRANCH_COST);
10750
10751 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10752 postalloc_expand %{
10753 //
10754 // replaces
10755 //
10756 // region src1 src2
10757 // \ | |
10758 // crx=cmpD_reg_reg
10759 //
10760 // with
10761 //
10762 // region src1 src2
10763 // \ | |
10764 // crx=cmpDUnordered_reg_reg
10765 // |
10766 // ^ region
10767 // | \
10768 // crx=cmov_bns_less
10769 //
10770
10771 // create new nodes
10772 MachNode *m1 = new cmpDUnordered_reg_regNode();
10773 MachNode *m2 = new cmov_bns_lessNode();
10774
10775 // inputs for new nodes
10776 m1->add_req(n_region, n_src1, n_src2);
10777 m2->add_req(n_region);
10778 m2->add_prec(m1);
10779
10780 // operands for new nodes
10781 m1->_opnds[0] = op_crx;
10782 m1->_opnds[1] = op_src1;
10783 m1->_opnds[2] = op_src2;
10784 m2->_opnds[0] = op_crx;
10785
10786 // registers for new nodes
10787 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10788 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10789
10790 // Insert new nodes.
10791 nodes->push(m1);
10792 nodes->push(m2);
10793 %}
10794 %}
10795
10796 // Compare double, generate -1,0,1
10797 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10798 match(Set dst (CmpD3 src1 src2));
10799 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10800
10801 expand %{
10802 flagsReg tmp1;
10803 cmpDUnordered_reg_reg(tmp1, src1, src2);
10804 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10805 %}
10806 %}
10807
10808 //----------Branches---------------------------------------------------------
10809 // Jump
10810
10811 // Direct Branch.
10812 instruct branch(label labl) %{
10813 match(Goto);
10814 effect(USE labl);
10815 ins_cost(BRANCH_COST);
10816
10817 format %{ "B $labl" %}
10818 size(4);
10819 ins_encode %{
10820 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10821 Label d; // dummy
10822 __ bind(d);
10823 Label* p = $labl$$label;
10824 // `p' is `NULL' when this encoding class is used only to
10825 // determine the size of the encoded instruction.
10826 Label& l = (NULL == p)? d : *(p);
10827 __ b(l);
10828 %}
10829 ins_pipe(pipe_class_default);
10830 %}
10831
10832 // Conditional Near Branch
10833 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10834 // Same match rule as `branchConFar'.
10835 match(If cmp crx);
10836 effect(USE lbl);
10837 ins_cost(BRANCH_COST);
10838
10839 // If set to 1 this indicates that the current instruction is a
10840 // short variant of a long branch. This avoids using this
10841 // instruction in first-pass matching. It will then only be used in
10842 // the `Shorten_branches' pass.
10843 ins_short_branch(1);
10844
10845 format %{ "B$cmp $crx, $lbl" %}
10846 size(4);
10847 ins_encode( enc_bc(crx, cmp, lbl) );
10848 ins_pipe(pipe_class_default);
10849 %}
10850
10851 // This is for cases when the ppc64 `bc' instruction does not
10852 // reach far enough. So we emit a far branch here, which is more
10853 // expensive.
10854 //
10855 // Conditional Far Branch
10856 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10857 // Same match rule as `branchCon'.
10858 match(If cmp crx);
10859 effect(USE crx, USE lbl);
10860 predicate(!false /* TODO: PPC port HB_Schedule*/);
10861 // Higher cost than `branchCon'.
10862 ins_cost(5*BRANCH_COST);
10863
10864 // This is not a short variant of a branch, but the long variant.
10865 ins_short_branch(0);
10866
10867 format %{ "B_FAR$cmp $crx, $lbl" %}
10868 size(8);
10869 ins_encode( enc_bc_far(crx, cmp, lbl) );
10870 ins_pipe(pipe_class_default);
10871 %}
10872
10873 // Conditional Branch used with Power6 scheduler (can be far or short).
10874 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10875 // Same match rule as `branchCon'.
10876 match(If cmp crx);
10877 effect(USE crx, USE lbl);
10878 predicate(false /* TODO: PPC port HB_Schedule*/);
10879 // Higher cost than `branchCon'.
10880 ins_cost(5*BRANCH_COST);
10881
10882 // Actually size doesn't depend on alignment but on shortening.
10883 ins_variable_size_depending_on_alignment(true);
10884 // long variant.
10885 ins_short_branch(0);
10886
10887 format %{ "B_FAR$cmp $crx, $lbl" %}
10888 size(8); // worst case
10889 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10890 ins_pipe(pipe_class_default);
10891 %}
10892
10893 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10894 match(CountedLoopEnd cmp crx);
10895 effect(USE labl);
10896 ins_cost(BRANCH_COST);
10897
10898 // short variant.
10899 ins_short_branch(1);
10900
10901 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10902 size(4);
10903 ins_encode( enc_bc(crx, cmp, labl) );
10904 ins_pipe(pipe_class_default);
10905 %}
10906
10907 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10908 match(CountedLoopEnd cmp crx);
10909 effect(USE labl);
10910 predicate(!false /* TODO: PPC port HB_Schedule */);
10911 ins_cost(BRANCH_COST);
10912
10913 // Long variant.
10914 ins_short_branch(0);
10915
10916 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10917 size(8);
10918 ins_encode( enc_bc_far(crx, cmp, labl) );
10919 ins_pipe(pipe_class_default);
10920 %}
10921
10922 // Conditional Branch used with Power6 scheduler (can be far or short).
10923 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10924 match(CountedLoopEnd cmp crx);
10925 effect(USE labl);
10926 predicate(false /* TODO: PPC port HB_Schedule */);
10927 // Higher cost than `branchCon'.
10928 ins_cost(5*BRANCH_COST);
10929
10930 // Actually size doesn't depend on alignment but on shortening.
10931 ins_variable_size_depending_on_alignment(true);
10932 // Long variant.
10933 ins_short_branch(0);
10934
10935 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10936 size(8); // worst case
10937 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10938 ins_pipe(pipe_class_default);
10939 %}
10940
10941 // ============================================================================
10942 // Java runtime operations, intrinsics and other complex operations.
10943
10944 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10945 // array for an instance of the superklass. Set a hidden internal cache on a
10946 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10947 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10948 //
10949 // GL TODO: Improve this.
10950 // - result should not be a TEMP
10951 // - Add match rule as on sparc avoiding additional Cmp.
10952 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10953 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10954 match(Set result (PartialSubtypeCheck subklass superklass));
10955 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10956 ins_cost(DEFAULT_COST*10);
10957
10958 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10959 ins_encode %{
10960 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10961 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10962 $tmp_klass$$Register, NULL, $result$$Register);
10963 %}
10964 ins_pipe(pipe_class_default);
10965 %}
10966
10967 // inlined locking and unlocking
10968
10969 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10970 match(Set crx (FastLock oop box));
10971 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10972 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10973
10974 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10975 ins_encode %{
10976 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10977 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10978 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10979 // If locking was successfull, crx should indicate 'EQ'.
10980 // The compiler generates a branch to the runtime call to
10981 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10982 %}
10983 ins_pipe(pipe_class_compare);
10984 %}
10985
10986 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10987 match(Set crx (FastUnlock oop box));
10988 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10989
10990 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10991 ins_encode %{
10992 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10993 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10994 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10995 // If unlocking was successfull, crx should indicate 'EQ'.
10996 // The compiler generates a branch to the runtime call to
10997 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10998 %}
10999 ins_pipe(pipe_class_compare);
11000 %}
11001
11002 // Align address.
11003 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11004 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11005
11006 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
11007 size(4);
11008 ins_encode %{
11009 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11010 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11011 %}
11012 ins_pipe(pipe_class_default);
11013 %}
11014
11015 // Array size computation.
11016 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11017 match(Set dst (SubL (CastP2X end) (CastP2X start)));
11018
11019 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
11020 size(4);
11021 ins_encode %{
11022 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11023 __ subf($dst$$Register, $start$$Register, $end$$Register);
11024 %}
11025 ins_pipe(pipe_class_default);
11026 %}
11027
11028 // Clear-array with dynamic array-size.
11029 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11030 match(Set dummy (ClearArray cnt base));
11031 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11032 ins_cost(MEMORY_REF_COST);
11033
11034 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11035
11036 format %{ "ClearArray $cnt, $base" %}
11037 ins_encode %{
11038 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11039 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11040 %}
11041 ins_pipe(pipe_class_default);
11042 %}
11043
11044 // String_IndexOf for needle of length 1.
11045 //
11046 // Match needle into immediate operands: no loadConP node needed. Saves one
11047 // register and two instructions over string_indexOf_imm1Node.
11048 //
11049 // Assumes register result differs from all input registers.
11050 //
11051 // Preserves registers haystack, haycnt
11052 // Kills registers tmp1, tmp2
11053 // Defines registers result
11054 //
11055 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11056 //
11057 // Unfortunately this does not match too often. In many situations the AddP is used
11058 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11059 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11060 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11061 iRegIdst tmp1, iRegIdst tmp2,
11062 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11063 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
11064 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11065
11066 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11067
11068 ins_cost(150);
11069 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11070 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11071
11072 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11073 ins_encode %{
11074 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11075 immPOper *needleOper = (immPOper *)$needleImm;
11076 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11077 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11078
11079 __ string_indexof_1($result$$Register,
11080 $haystack$$Register, $haycnt$$Register,
11081 R0, needle_values->char_at(0),
11082 $tmp1$$Register, $tmp2$$Register);
11083 %}
11084 ins_pipe(pipe_class_compare);
11085 %}
11086
11087 // String_IndexOf for needle of length 1.
11088 //
11089 // Special case requires less registers and emits less instructions.
11090 //
11091 // Assumes register result differs from all input registers.
11092 //
11093 // Preserves registers haystack, haycnt
11094 // Kills registers tmp1, tmp2, needle
11095 // Defines registers result
11096 //
11097 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11098 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11099 rscratch2RegP needle, immI_1 needlecntImm,
11100 iRegIdst tmp1, iRegIdst tmp2,
11101 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11102 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11103 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11104 TEMP tmp1, TEMP tmp2);
11105 // Required for EA: check if it is still a type_array.
11106 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11107 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11108 ins_cost(180);
11109
11110 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11111
11112 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11113 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11114 ins_encode %{
11115 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11116 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11117 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11118 guarantee(needle_values, "sanity");
11119 if (needle_values != NULL) {
11120 __ string_indexof_1($result$$Register,
11121 $haystack$$Register, $haycnt$$Register,
11122 R0, needle_values->char_at(0),
11123 $tmp1$$Register, $tmp2$$Register);
11124 } else {
11125 __ string_indexof_1($result$$Register,
11126 $haystack$$Register, $haycnt$$Register,
11127 $needle$$Register, 0,
11128 $tmp1$$Register, $tmp2$$Register);
11129 }
11130 %}
11131 ins_pipe(pipe_class_compare);
11132 %}
11133
11134 // String_IndexOf.
11135 //
11136 // Length of needle as immediate. This saves instruction loading constant needle
11137 // length.
11138 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11139 // completely or do it in vector instruction. This should save registers for
11140 // needlecnt and needle.
11141 //
11142 // Assumes register result differs from all input registers.
11143 // Overwrites haycnt, needlecnt.
11144 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11145 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11146 iRegPsrc needle, uimmI15 needlecntImm,
11147 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11148 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11149 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11150 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11151 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11152 // Required for EA: check if it is still a type_array.
11153 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11154 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11155 ins_cost(250);
11156
11157 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11158
11159 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11160 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11161 ins_encode %{
11162 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11163 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11164 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11165
11166 __ string_indexof($result$$Register,
11167 $haystack$$Register, $haycnt$$Register,
11168 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11169 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11170 %}
11171 ins_pipe(pipe_class_compare);
11172 %}
11173
11174 // StrIndexOf node.
11175 //
11176 // Assumes register result differs from all input registers.
11177 // Overwrites haycnt, needlecnt.
11178 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11179 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11180 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11181 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11182 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11183 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11184 TEMP_DEF result,
11185 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11186 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11187 ins_cost(300);
11188
11189 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11190
11191 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11192 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11193 ins_encode %{
11194 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11195 __ string_indexof($result$$Register,
11196 $haystack$$Register, $haycnt$$Register,
11197 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11198 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11199 %}
11200 ins_pipe(pipe_class_compare);
11201 %}
11202
11203 // String equals with immediate.
11204 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11205 iRegPdst tmp1, iRegPdst tmp2,
11206 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11207 match(Set result (StrEquals (Binary str1 str2) cntImm));
11208 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11209 KILL cr0, KILL cr6, KILL ctr);
11210 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11211 ins_cost(250);
11212
11213 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11214
11215 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11216 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11217 ins_encode %{
11218 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11219 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11220 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11221 %}
11222 ins_pipe(pipe_class_compare);
11223 %}
11224
11225 // String equals.
11226 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11227 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11228 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11229 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11230 match(Set result (StrEquals (Binary str1 str2) cnt));
11231 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11232 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11233 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11234 ins_cost(300);
11235
11236 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11237
11238 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11239 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11240 ins_encode %{
11241 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11242 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11243 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11244 %}
11245 ins_pipe(pipe_class_compare);
11246 %}
11247
11248 // String compare.
11249 // Char[] pointers are passed in.
11250 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11251 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11252 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11253 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11254 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11255 ins_cost(300);
11256
11257 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11258
11259 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11260 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11261 ins_encode %{
11262 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11263 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11264 $result$$Register, $tmp$$Register);
11265 %}
11266 ins_pipe(pipe_class_compare);
11267 %}
11268
11269 //---------- Min/Max Instructions ---------------------------------------------
11270
11271 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11272 match(Set dst (MinI src1 src2));
11273 ins_cost(DEFAULT_COST*6);
11274
11275 expand %{
11276 iRegLdst src1s;
11277 iRegLdst src2s;
11278 iRegLdst diff;
11279 iRegLdst sm;
11280 iRegLdst doz; // difference or zero
11281 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11282 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11283 subL_reg_reg(diff, src2s, src1s);
11284 // Need to consider >=33 bit result, therefore we need signmaskL.
11285 signmask64L_regL(sm, diff);
11286 andL_reg_reg(doz, diff, sm); // <=0
11287 addI_regL_regL(dst, doz, src1s);
11288 %}
11289 %}
11290
11291 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11292 match(Set dst (MaxI src1 src2));
11293 ins_cost(DEFAULT_COST*6);
11294
11295 expand %{
11296 iRegLdst src1s;
11297 iRegLdst src2s;
11298 iRegLdst diff;
11299 iRegLdst sm;
11300 iRegLdst doz; // difference or zero
11301 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11302 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11303 subL_reg_reg(diff, src2s, src1s);
11304 // Need to consider >=33 bit result, therefore we need signmaskL.
11305 signmask64L_regL(sm, diff);
11306 andcL_reg_reg(doz, diff, sm); // >=0
11307 addI_regL_regL(dst, doz, src1s);
11308 %}
11309 %}
11310
11311 //---------- Population Count Instructions ------------------------------------
11312
11313 // Popcnt for Power7.
11314 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11315 match(Set dst (PopCountI src));
11316 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11317 ins_cost(DEFAULT_COST);
11318
11319 format %{ "POPCNTW $dst, $src" %}
11320 size(4);
11321 ins_encode %{
11322 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11323 __ popcntw($dst$$Register, $src$$Register);
11324 %}
11325 ins_pipe(pipe_class_default);
11326 %}
11327
11328 // Popcnt for Power7.
11329 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11330 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11331 match(Set dst (PopCountL src));
11332 ins_cost(DEFAULT_COST);
11333
11334 format %{ "POPCNTD $dst, $src" %}
11335 size(4);
11336 ins_encode %{
11337 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11338 __ popcntd($dst$$Register, $src$$Register);
11339 %}
11340 ins_pipe(pipe_class_default);
11341 %}
11342
11343 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11344 match(Set dst (CountLeadingZerosI src));
11345 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11346 ins_cost(DEFAULT_COST);
11347
11348 format %{ "CNTLZW $dst, $src" %}
11349 size(4);
11350 ins_encode %{
11351 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11352 __ cntlzw($dst$$Register, $src$$Register);
11353 %}
11354 ins_pipe(pipe_class_default);
11355 %}
11356
11357 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11358 match(Set dst (CountLeadingZerosL src));
11359 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11360 ins_cost(DEFAULT_COST);
11361
11362 format %{ "CNTLZD $dst, $src" %}
11363 size(4);
11364 ins_encode %{
11365 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11366 __ cntlzd($dst$$Register, $src$$Register);
11367 %}
11368 ins_pipe(pipe_class_default);
11369 %}
11370
11371 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11372 // no match-rule, false predicate
11373 effect(DEF dst, USE src);
11374 predicate(false);
11375
11376 format %{ "CNTLZD $dst, $src" %}
11377 size(4);
11378 ins_encode %{
11379 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11380 __ cntlzd($dst$$Register, $src$$Register);
11381 %}
11382 ins_pipe(pipe_class_default);
11383 %}
11384
11385 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11386 match(Set dst (CountTrailingZerosI src));
11387 predicate(UseCountLeadingZerosInstructionsPPC64);
11388 ins_cost(DEFAULT_COST);
11389
11390 expand %{
11391 immI16 imm1 %{ (int)-1 %}
11392 immI16 imm2 %{ (int)32 %}
11393 immI_minus1 m1 %{ -1 %}
11394 iRegIdst tmpI1;
11395 iRegIdst tmpI2;
11396 iRegIdst tmpI3;
11397 addI_reg_imm16(tmpI1, src, imm1);
11398 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11399 countLeadingZerosI(tmpI3, tmpI2);
11400 subI_imm16_reg(dst, imm2, tmpI3);
11401 %}
11402 %}
11403
11404 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11405 match(Set dst (CountTrailingZerosL src));
11406 predicate(UseCountLeadingZerosInstructionsPPC64);
11407 ins_cost(DEFAULT_COST);
11408
11409 expand %{
11410 immL16 imm1 %{ (long)-1 %}
11411 immI16 imm2 %{ (int)64 %}
11412 iRegLdst tmpL1;
11413 iRegLdst tmpL2;
11414 iRegIdst tmpL3;
11415 addL_reg_imm16(tmpL1, src, imm1);
11416 andcL_reg_reg(tmpL2, tmpL1, src);
11417 countLeadingZerosL(tmpL3, tmpL2);
11418 subI_imm16_reg(dst, imm2, tmpL3);
11419 %}
11420 %}
11421
11422 // Expand nodes for byte_reverse_int.
11423 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11424 effect(DEF dst, USE src, USE pos, USE shift);
11425 predicate(false);
11426
11427 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11428 size(4);
11429 ins_encode %{
11430 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11431 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11432 %}
11433 ins_pipe(pipe_class_default);
11434 %}
11435
11436 // As insrwi_a, but with USE_DEF.
11437 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11438 effect(USE_DEF dst, USE src, USE pos, USE shift);
11439 predicate(false);
11440
11441 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11442 size(4);
11443 ins_encode %{
11444 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11445 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11446 %}
11447 ins_pipe(pipe_class_default);
11448 %}
11449
11450 // Just slightly faster than java implementation.
11451 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11452 match(Set dst (ReverseBytesI src));
11453 predicate(UseCountLeadingZerosInstructionsPPC64);
11454 ins_cost(DEFAULT_COST);
11455
11456 expand %{
11457 immI16 imm24 %{ (int) 24 %}
11458 immI16 imm16 %{ (int) 16 %}
11459 immI16 imm8 %{ (int) 8 %}
11460 immI16 imm4 %{ (int) 4 %}
11461 immI16 imm0 %{ (int) 0 %}
11462 iRegLdst tmpI1;
11463 iRegLdst tmpI2;
11464 iRegLdst tmpI3;
11465
11466 urShiftI_reg_imm(tmpI1, src, imm24);
11467 insrwi_a(dst, tmpI1, imm24, imm8);
11468 urShiftI_reg_imm(tmpI2, src, imm16);
11469 insrwi(dst, tmpI2, imm8, imm16);
11470 urShiftI_reg_imm(tmpI3, src, imm8);
11471 insrwi(dst, tmpI3, imm8, imm8);
11472 insrwi(dst, src, imm0, imm8);
11473 %}
11474 %}
11475
11476 //---------- Replicate Vector Instructions ------------------------------------
11477
11478 // Insrdi does replicate if src == dst.
11479 instruct repl32(iRegLdst dst) %{
11480 predicate(false);
11481 effect(USE_DEF dst);
11482
11483 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11484 size(4);
11485 ins_encode %{
11486 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11487 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11488 %}
11489 ins_pipe(pipe_class_default);
11490 %}
11491
11492 // Insrdi does replicate if src == dst.
11493 instruct repl48(iRegLdst dst) %{
11494 predicate(false);
11495 effect(USE_DEF dst);
11496
11497 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11498 size(4);
11499 ins_encode %{
11500 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11501 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11502 %}
11503 ins_pipe(pipe_class_default);
11504 %}
11505
11506 // Insrdi does replicate if src == dst.
11507 instruct repl56(iRegLdst dst) %{
11508 predicate(false);
11509 effect(USE_DEF dst);
11510
11511 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11512 size(4);
11513 ins_encode %{
11514 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11515 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11516 %}
11517 ins_pipe(pipe_class_default);
11518 %}
11519
11520 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11521 match(Set dst (ReplicateB src));
11522 predicate(n->as_Vector()->length() == 8);
11523 expand %{
11524 moveReg(dst, src);
11525 repl56(dst);
11526 repl48(dst);
11527 repl32(dst);
11528 %}
11529 %}
11530
11531 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11532 match(Set dst (ReplicateB zero));
11533 predicate(n->as_Vector()->length() == 8);
11534 format %{ "LI $dst, #0 \t// replicate8B" %}
11535 size(4);
11536 ins_encode %{
11537 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11538 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11539 %}
11540 ins_pipe(pipe_class_default);
11541 %}
11542
11543 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11544 match(Set dst (ReplicateB src));
11545 predicate(n->as_Vector()->length() == 8);
11546 format %{ "LI $dst, #-1 \t// replicate8B" %}
11547 size(4);
11548 ins_encode %{
11549 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11550 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11551 %}
11552 ins_pipe(pipe_class_default);
11553 %}
11554
11555 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11556 match(Set dst (ReplicateS src));
11557 predicate(n->as_Vector()->length() == 4);
11558 expand %{
11559 moveReg(dst, src);
11560 repl48(dst);
11561 repl32(dst);
11562 %}
11563 %}
11564
11565 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11566 match(Set dst (ReplicateS zero));
11567 predicate(n->as_Vector()->length() == 4);
11568 format %{ "LI $dst, #0 \t// replicate4C" %}
11569 size(4);
11570 ins_encode %{
11571 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11572 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11573 %}
11574 ins_pipe(pipe_class_default);
11575 %}
11576
11577 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11578 match(Set dst (ReplicateS src));
11579 predicate(n->as_Vector()->length() == 4);
11580 format %{ "LI $dst, -1 \t// replicate4C" %}
11581 size(4);
11582 ins_encode %{
11583 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11584 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11585 %}
11586 ins_pipe(pipe_class_default);
11587 %}
11588
11589 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11590 match(Set dst (ReplicateI src));
11591 predicate(n->as_Vector()->length() == 2);
11592 ins_cost(2 * DEFAULT_COST);
11593 expand %{
11594 moveReg(dst, src);
11595 repl32(dst);
11596 %}
11597 %}
11598
11599 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11600 match(Set dst (ReplicateI zero));
11601 predicate(n->as_Vector()->length() == 2);
11602 format %{ "LI $dst, #0 \t// replicate4C" %}
11603 size(4);
11604 ins_encode %{
11605 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11606 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11607 %}
11608 ins_pipe(pipe_class_default);
11609 %}
11610
11611 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11612 match(Set dst (ReplicateI src));
11613 predicate(n->as_Vector()->length() == 2);
11614 format %{ "LI $dst, -1 \t// replicate4C" %}
11615 size(4);
11616 ins_encode %{
11617 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11618 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11619 %}
11620 ins_pipe(pipe_class_default);
11621 %}
11622
11623 // Move float to int register via stack, replicate.
11624 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11625 match(Set dst (ReplicateF src));
11626 predicate(n->as_Vector()->length() == 2);
11627 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11628 expand %{
11629 stackSlotL tmpS;
11630 iRegIdst tmpI;
11631 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11632 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11633 moveReg(dst, tmpI); // Move int to long reg.
11634 repl32(dst); // Replicate bitpattern.
11635 %}
11636 %}
11637
11638 // Replicate scalar constant to packed float values in Double register
11639 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11640 match(Set dst (ReplicateF src));
11641 predicate(n->as_Vector()->length() == 2);
11642 ins_cost(5 * DEFAULT_COST);
11643
11644 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11645 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11646 %}
11647
11648 // Replicate scalar zero constant to packed float values in Double register
11649 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11650 match(Set dst (ReplicateF zero));
11651 predicate(n->as_Vector()->length() == 2);
11652
11653 format %{ "LI $dst, #0 \t// replicate2F" %}
11654 ins_encode %{
11655 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11656 __ li($dst$$Register, 0x0);
11657 %}
11658 ins_pipe(pipe_class_default);
11659 %}
11660
11661 // ============================================================================
11662 // Safepoint Instruction
11663
11664 instruct safePoint_poll(iRegPdst poll) %{
11665 match(SafePoint poll);
11666 predicate(LoadPollAddressFromThread);
11667
11668 // It caused problems to add the effect that r0 is killed, but this
11669 // effect no longer needs to be mentioned, since r0 is not contained
11670 // in a reg_class.
11671
11672 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11673 size(4);
11674 ins_encode( enc_poll(0x0, poll) );
11675 ins_pipe(pipe_class_default);
11676 %}
11677
11678 // Safepoint without per-thread support. Load address of page to poll
11679 // as constant.
11680 // Rscratch2RegP is R12.
11681 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11682 // a seperate node so that the oop map is at the right location.
11683 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11684 match(SafePoint poll);
11685 predicate(!LoadPollAddressFromThread);
11686
11687 // It caused problems to add the effect that r0 is killed, but this
11688 // effect no longer needs to be mentioned, since r0 is not contained
11689 // in a reg_class.
11690
11691 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11692 ins_encode( enc_poll(0x0, poll) );
11693 ins_pipe(pipe_class_default);
11694 %}
11695
11696 // ============================================================================
11697 // Call Instructions
11698
11699 // Call Java Static Instruction
11700
11701 // Schedulable version of call static node.
11702 instruct CallStaticJavaDirect(method meth) %{
11703 match(CallStaticJava);
11704 effect(USE meth);
11705 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11706 ins_cost(CALL_COST);
11707
11708 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11709
11710 format %{ "CALL,static $meth \t// ==> " %}
11711 size(4);
11712 ins_encode( enc_java_static_call(meth) );
11713 ins_pipe(pipe_class_call);
11714 %}
11715
11716 // Schedulable version of call static node.
11717 instruct CallStaticJavaDirectHandle(method meth) %{
11718 match(CallStaticJava);
11719 effect(USE meth);
11720 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11721 ins_cost(CALL_COST);
11722
11723 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11724
11725 format %{ "CALL,static $meth \t// ==> " %}
11726 ins_encode( enc_java_handle_call(meth) );
11727 ins_pipe(pipe_class_call);
11728 %}
11729
11730 // Call Java Dynamic Instruction
11731
11732 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11733 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11734 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11735 // The call destination must still be placed in the constant pool.
11736 instruct CallDynamicJavaDirectSched(method meth) %{
11737 match(CallDynamicJava); // To get all the data fields we need ...
11738 effect(USE meth);
11739 predicate(false); // ... but never match.
11740
11741 ins_field_load_ic_hi_node(loadConL_hiNode*);
11742 ins_field_load_ic_node(loadConLNode*);
11743 ins_num_consts(1 /* 1 patchable constant: call destination */);
11744
11745 format %{ "BL \t// dynamic $meth ==> " %}
11746 size(4);
11747 ins_encode( enc_java_dynamic_call_sched(meth) );
11748 ins_pipe(pipe_class_call);
11749 %}
11750
11751 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11752 // We use postalloc expanded calls if we use inline caches
11753 // and do not update method data.
11754 //
11755 // This instruction has two constants: inline cache (IC) and call destination.
11756 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11757 // one constant.
11758 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11759 match(CallDynamicJava);
11760 effect(USE meth);
11761 predicate(UseInlineCaches);
11762 ins_cost(CALL_COST);
11763
11764 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11765
11766 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11767 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11768 %}
11769
11770 // Compound version of call dynamic java
11771 // We use postalloc expanded calls if we use inline caches
11772 // and do not update method data.
11773 instruct CallDynamicJavaDirect(method meth) %{
11774 match(CallDynamicJava);
11775 effect(USE meth);
11776 predicate(!UseInlineCaches);
11777 ins_cost(CALL_COST);
11778
11779 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11780 ins_num_consts(4);
11781
11782 format %{ "CALL,dynamic $meth \t// ==> " %}
11783 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11784 ins_pipe(pipe_class_call);
11785 %}
11786
11787 // Call Runtime Instruction
11788
11789 instruct CallRuntimeDirect(method meth) %{
11790 match(CallRuntime);
11791 effect(USE meth);
11792 ins_cost(CALL_COST);
11793
11794 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11795 // env for callee, C-toc.
11796 ins_num_consts(3);
11797
11798 format %{ "CALL,runtime" %}
11799 ins_encode( enc_java_to_runtime_call(meth) );
11800 ins_pipe(pipe_class_call);
11801 %}
11802
11803 // Call Leaf
11804
11805 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11806 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11807 effect(DEF dst, USE src);
11808
11809 ins_num_consts(1);
11810
11811 format %{ "MTCTR $src" %}
11812 size(4);
11813 ins_encode( enc_leaf_call_mtctr(src) );
11814 ins_pipe(pipe_class_default);
11815 %}
11816
11817 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11818 instruct CallLeafDirect(method meth) %{
11819 match(CallLeaf); // To get the data all the data fields we need ...
11820 effect(USE meth);
11821 predicate(false); // but never match.
11822
11823 format %{ "BCTRL \t// leaf call $meth ==> " %}
11824 size(4);
11825 ins_encode %{
11826 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11827 __ bctrl();
11828 %}
11829 ins_pipe(pipe_class_call);
11830 %}
11831
11832 // postalloc expand of CallLeafDirect.
11833 // Load adress to call from TOC, then bl to it.
11834 instruct CallLeafDirect_Ex(method meth) %{
11835 match(CallLeaf);
11836 effect(USE meth);
11837 ins_cost(CALL_COST);
11838
11839 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11840 // env for callee, C-toc.
11841 ins_num_consts(3);
11842
11843 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11844 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11845 %}
11846
11847 // Call runtime without safepoint - same as CallLeaf.
11848 // postalloc expand of CallLeafNoFPDirect.
11849 // Load adress to call from TOC, then bl to it.
11850 instruct CallLeafNoFPDirect_Ex(method meth) %{
11851 match(CallLeafNoFP);
11852 effect(USE meth);
11853 ins_cost(CALL_COST);
11854
11855 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11856 // env for callee, C-toc.
11857 ins_num_consts(3);
11858
11859 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11860 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11861 %}
11862
11863 // Tail Call; Jump from runtime stub to Java code.
11864 // Also known as an 'interprocedural jump'.
11865 // Target of jump will eventually return to caller.
11866 // TailJump below removes the return address.
11867 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11868 match(TailCall jump_target method_oop);
11869 ins_cost(CALL_COST);
11870
11871 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11872 "BCTR \t// tail call" %}
11873 size(8);
11874 ins_encode %{
11875 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11876 __ mtctr($jump_target$$Register);
11877 __ bctr();
11878 %}
11879 ins_pipe(pipe_class_call);
11880 %}
11881
11882 // Return Instruction
11883 instruct Ret() %{
11884 match(Return);
11885 format %{ "BLR \t// branch to link register" %}
11886 size(4);
11887 ins_encode %{
11888 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11889 // LR is restored in MachEpilogNode. Just do the RET here.
11890 __ blr();
11891 %}
11892 ins_pipe(pipe_class_default);
11893 %}
11894
11895 // Tail Jump; remove the return address; jump to target.
11896 // TailCall above leaves the return address around.
11897 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11898 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11899 // "restore" before this instruction (in Epilogue), we need to materialize it
11900 // in %i0.
11901 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11902 match(TailJump jump_target ex_oop);
11903 ins_cost(CALL_COST);
11904
11905 format %{ "LD R4_ARG2 = LR\n\t"
11906 "MTCTR $jump_target\n\t"
11907 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11908 size(12);
11909 ins_encode %{
11910 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11911 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11912 __ mtctr($jump_target$$Register);
11913 __ bctr();
11914 %}
11915 ins_pipe(pipe_class_call);
11916 %}
11917
11918 // Create exception oop: created by stack-crawling runtime code.
11919 // Created exception is now available to this handler, and is setup
11920 // just prior to jumping to this handler. No code emitted.
11921 instruct CreateException(rarg1RegP ex_oop) %{
11922 match(Set ex_oop (CreateEx));
11923 ins_cost(0);
11924
11925 format %{ " -- \t// exception oop; no code emitted" %}
11926 size(0);
11927 ins_encode( /*empty*/ );
11928 ins_pipe(pipe_class_default);
11929 %}
11930
11931 // Rethrow exception: The exception oop will come in the first
11932 // argument position. Then JUMP (not call) to the rethrow stub code.
11933 instruct RethrowException() %{
11934 match(Rethrow);
11935 ins_cost(CALL_COST);
11936
11937 format %{ "Jmp rethrow_stub" %}
11938 ins_encode %{
11939 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11940 cbuf.set_insts_mark();
11941 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11942 %}
11943 ins_pipe(pipe_class_call);
11944 %}
11945
11946 // Die now.
11947 instruct ShouldNotReachHere() %{
11948 match(Halt);
11949 ins_cost(CALL_COST);
11950
11951 format %{ "ShouldNotReachHere" %}
11952 size(4);
11953 ins_encode %{
11954 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11955 __ trap_should_not_reach_here();
11956 %}
11957 ins_pipe(pipe_class_default);
11958 %}
11959
11960 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11961 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11962 // Get a DEF on threadRegP, no costs, no encoding, use
11963 // 'ins_should_rematerialize(true)' to avoid spilling.
11964 instruct tlsLoadP(threadRegP dst) %{
11965 match(Set dst (ThreadLocal));
11966 ins_cost(0);
11967
11968 ins_should_rematerialize(true);
11969
11970 format %{ " -- \t// $dst=Thread::current(), empty" %}
11971 size(0);
11972 ins_encode( /*empty*/ );
11973 ins_pipe(pipe_class_empty);
11974 %}
11975
11976 //---Some PPC specific nodes---------------------------------------------------
11977
11978 // Stop a group.
11979 instruct endGroup() %{
11980 ins_cost(0);
11981
11982 ins_is_nop(true);
11983
11984 format %{ "End Bundle (ori r1, r1, 0)" %}
11985 size(4);
11986 ins_encode %{
11987 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11988 __ endgroup();
11989 %}
11990 ins_pipe(pipe_class_default);
11991 %}
11992
11993 // Nop instructions
11994
11995 instruct fxNop() %{
11996 ins_cost(0);
11997
11998 ins_is_nop(true);
11999
12000 format %{ "fxNop" %}
12001 size(4);
12002 ins_encode %{
12003 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12004 __ nop();
12005 %}
12006 ins_pipe(pipe_class_default);
12007 %}
12008
12009 instruct fpNop0() %{
12010 ins_cost(0);
12011
12012 ins_is_nop(true);
12013
12014 format %{ "fpNop0" %}
12015 size(4);
12016 ins_encode %{
12017 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12018 __ fpnop0();
12019 %}
12020 ins_pipe(pipe_class_default);
12021 %}
12022
12023 instruct fpNop1() %{
12024 ins_cost(0);
12025
12026 ins_is_nop(true);
12027
12028 format %{ "fpNop1" %}
12029 size(4);
12030 ins_encode %{
12031 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12032 __ fpnop1();
12033 %}
12034 ins_pipe(pipe_class_default);
12035 %}
12036
12037 instruct brNop0() %{
12038 ins_cost(0);
12039 size(4);
12040 format %{ "brNop0" %}
12041 ins_encode %{
12042 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12043 __ brnop0();
12044 %}
12045 ins_is_nop(true);
12046 ins_pipe(pipe_class_default);
12047 %}
12048
12049 instruct brNop1() %{
12050 ins_cost(0);
12051
12052 ins_is_nop(true);
12053
12054 format %{ "brNop1" %}
12055 size(4);
12056 ins_encode %{
12057 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12058 __ brnop1();
12059 %}
12060 ins_pipe(pipe_class_default);
12061 %}
12062
12063 instruct brNop2() %{
12064 ins_cost(0);
12065
12066 ins_is_nop(true);
12067
12068 format %{ "brNop2" %}
12069 size(4);
12070 ins_encode %{
12071 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12072 __ brnop2();
12073 %}
12074 ins_pipe(pipe_class_default);
12075 %}
12076
12077 //----------PEEPHOLE RULES-----------------------------------------------------
12078 // These must follow all instruction definitions as they use the names
12079 // defined in the instructions definitions.
12080 //
12081 // peepmatch ( root_instr_name [preceeding_instruction]* );
12082 //
12083 // peepconstraint %{
12084 // (instruction_number.operand_name relational_op instruction_number.operand_name
12085 // [, ...] );
12086 // // instruction numbers are zero-based using left to right order in peepmatch
12087 //
12088 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12089 // // provide an instruction_number.operand_name for each operand that appears
12090 // // in the replacement instruction's match rule
12091 //
12092 // ---------VM FLAGS---------------------------------------------------------
12093 //
12094 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12095 //
12096 // Each peephole rule is given an identifying number starting with zero and
12097 // increasing by one in the order seen by the parser. An individual peephole
12098 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12099 // on the command-line.
12100 //
12101 // ---------CURRENT LIMITATIONS----------------------------------------------
12102 //
12103 // Only match adjacent instructions in same basic block
12104 // Only equality constraints
12105 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12106 // Only one replacement instruction
12107 //
12108 // ---------EXAMPLE----------------------------------------------------------
12109 //
12110 // // pertinent parts of existing instructions in architecture description
12111 // instruct movI(eRegI dst, eRegI src) %{
12112 // match(Set dst (CopyI src));
12113 // %}
12114 //
12115 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12116 // match(Set dst (AddI dst src));
12117 // effect(KILL cr);
12118 // %}
12119 //
12120 // // Change (inc mov) to lea
12121 // peephole %{
12122 // // increment preceeded by register-register move
12123 // peepmatch ( incI_eReg movI );
12124 // // require that the destination register of the increment
12125 // // match the destination register of the move
12126 // peepconstraint ( 0.dst == 1.dst );
12127 // // construct a replacement instruction that sets
12128 // // the destination to ( move's source register + one )
12129 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12130 // %}
12131 //
12132 // Implementation no longer uses movX instructions since
12133 // machine-independent system no longer uses CopyX nodes.
12134 //
12135 // peephole %{
12136 // peepmatch ( incI_eReg movI );
12137 // peepconstraint ( 0.dst == 1.dst );
12138 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12139 // %}
12140 //
12141 // peephole %{
12142 // peepmatch ( decI_eReg movI );
12143 // peepconstraint ( 0.dst == 1.dst );
12144 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12145 // %}
12146 //
12147 // peephole %{
12148 // peepmatch ( addI_eReg_imm movI );
12149 // peepconstraint ( 0.dst == 1.dst );
12150 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12151 // %}
12152 //
12153 // peephole %{
12154 // peepmatch ( addP_eReg_imm movP );
12155 // peepconstraint ( 0.dst == 1.dst );
12156 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12157 // %}
12158
12159 // // Change load of spilled value to only a spill
12160 // instruct storeI(memory mem, eRegI src) %{
12161 // match(Set mem (StoreI mem src));
12162 // %}
12163 //
12164 // instruct loadI(eRegI dst, memory mem) %{
12165 // match(Set dst (LoadI mem));
12166 // %}
12167 //
12168 peephole %{
12169 peepmatch ( loadI storeI );
12170 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12171 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12172 %}
12173
12174 peephole %{
12175 peepmatch ( loadL storeL );
12176 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12177 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12178 %}
12179
12180 peephole %{
12181 peepmatch ( loadP storeP );
12182 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12183 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12184 %}
12185
12186 //----------SMARTSPILL RULES---------------------------------------------------
12187 // These must follow all instruction definitions as they use the names
12188 // defined in the instructions definitions.