1 //
2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2015 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29,*/ // global TOC
451 R30,
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29,*/
488 R30,
489 R31
490 );
491
492 reg_class rscratch1_bits32_reg(R11);
493 reg_class rscratch2_bits32_reg(R12);
494 reg_class rarg1_bits32_reg(R3);
495 reg_class rarg2_bits32_reg(R4);
496 reg_class rarg3_bits32_reg(R5);
497 reg_class rarg4_bits32_reg(R6);
498
499 // ----------------------------
500 // 64 Bit Register Classes
501 // ----------------------------
502 // 64-bit build means 64-bit pointers means hi/lo pairs
503
504 reg_class rscratch1_bits64_reg(R11_H, R11);
505 reg_class rscratch2_bits64_reg(R12_H, R12);
506 reg_class rarg1_bits64_reg(R3_H, R3);
507 reg_class rarg2_bits64_reg(R4_H, R4);
508 reg_class rarg3_bits64_reg(R5_H, R5);
509 reg_class rarg4_bits64_reg(R6_H, R6);
510 // Thread register, 'written' by tlsLoadP, see there.
511 reg_class thread_bits64_reg(R16_H, R16);
512
513 reg_class r19_bits64_reg(R19_H, R19);
514
515 // 64 bit registers that can be read and written i.e. these registers
516 // can be dest (or src) of normal instructions.
517 reg_class bits64_reg_rw(
518 /*R0_H, R0*/ // R0
519 /*R1_H, R1*/ // SP
520 R2_H, R2, // TOC
521 R3_H, R3,
522 R4_H, R4,
523 R5_H, R5,
524 R6_H, R6,
525 R7_H, R7,
526 R8_H, R8,
527 R9_H, R9,
528 R10_H, R10,
529 R11_H, R11,
530 R12_H, R12,
531 /*R13_H, R13*/ // system thread id
532 R14_H, R14,
533 R15_H, R15,
534 /*R16_H, R16*/ // R16_thread
535 R17_H, R17,
536 R18_H, R18,
537 R19_H, R19,
538 R20_H, R20,
539 R21_H, R21,
540 R22_H, R22,
541 R23_H, R23,
542 R24_H, R24,
543 R25_H, R25,
544 R26_H, R26,
545 R27_H, R27,
546 R28_H, R28,
547 /*R29_H, R29,*/
548 R30_H, R30,
549 R31_H, R31
550 );
551
552 // 64 bit registers used excluding r2, r11 and r12
553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
554 // r2, r11 and r12 internally.
555 reg_class bits64_reg_leaf_call(
556 /*R0_H, R0*/ // R0
557 /*R1_H, R1*/ // SP
558 /*R2_H, R2*/ // TOC
559 R3_H, R3,
560 R4_H, R4,
561 R5_H, R5,
562 R6_H, R6,
563 R7_H, R7,
564 R8_H, R8,
565 R9_H, R9,
566 R10_H, R10,
567 /*R11_H, R11*/
568 /*R12_H, R12*/
569 /*R13_H, R13*/ // system thread id
570 R14_H, R14,
571 R15_H, R15,
572 /*R16_H, R16*/ // R16_thread
573 R17_H, R17,
574 R18_H, R18,
575 R19_H, R19,
576 R20_H, R20,
577 R21_H, R21,
578 R22_H, R22,
579 R23_H, R23,
580 R24_H, R24,
581 R25_H, R25,
582 R26_H, R26,
583 R27_H, R27,
584 R28_H, R28,
585 /*R29_H, R29,*/
586 R30_H, R30,
587 R31_H, R31
588 );
589
590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
591 // which uses r19 as inline cache internally and expanded LeafCall which uses
592 // r2, r11 and r12 internally.
593 reg_class bits64_constant_table_base(
594 /*R0_H, R0*/ // R0
595 /*R1_H, R1*/ // SP
596 /*R2_H, R2*/ // TOC
597 R3_H, R3,
598 R4_H, R4,
599 R5_H, R5,
600 R6_H, R6,
601 R7_H, R7,
602 R8_H, R8,
603 R9_H, R9,
604 R10_H, R10,
605 /*R11_H, R11*/
606 /*R12_H, R12*/
607 /*R13_H, R13*/ // system thread id
608 R14_H, R14,
609 R15_H, R15,
610 /*R16_H, R16*/ // R16_thread
611 R17_H, R17,
612 R18_H, R18,
613 /*R19_H, R19*/
614 R20_H, R20,
615 R21_H, R21,
616 R22_H, R22,
617 R23_H, R23,
618 R24_H, R24,
619 R25_H, R25,
620 R26_H, R26,
621 R27_H, R27,
622 R28_H, R28,
623 /*R29_H, R29,*/
624 R30_H, R30,
625 R31_H, R31
626 );
627
628 // 64 bit registers that can only be read i.e. these registers can
629 // only be src of all instructions.
630 reg_class bits64_reg_ro(
631 /*R0_H, R0*/ // R0
632 R1_H, R1,
633 R2_H, R2, // TOC
634 R3_H, R3,
635 R4_H, R4,
636 R5_H, R5,
637 R6_H, R6,
638 R7_H, R7,
639 R8_H, R8,
640 R9_H, R9,
641 R10_H, R10,
642 R11_H, R11,
643 R12_H, R12,
644 /*R13_H, R13*/ // system thread id
645 R14_H, R14,
646 R15_H, R15,
647 R16_H, R16, // R16_thread
648 R17_H, R17,
649 R18_H, R18,
650 R19_H, R19,
651 R20_H, R20,
652 R21_H, R21,
653 R22_H, R22,
654 R23_H, R23,
655 R24_H, R24,
656 R25_H, R25,
657 R26_H, R26,
658 R27_H, R27,
659 R28_H, R28,
660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
661 R30_H, R30,
662 R31_H, R31
663 );
664
665
666 // ----------------------------
667 // Special Class for Condition Code Flags Register
668
669 reg_class int_flags(
670 /*CCR0*/ // scratch
671 /*CCR1*/ // scratch
672 /*CCR2*/ // nv!
673 /*CCR3*/ // nv!
674 /*CCR4*/ // nv!
675 CCR5,
676 CCR6,
677 CCR7
678 );
679
680 reg_class int_flags_ro(
681 CCR0,
682 CCR1,
683 CCR2,
684 CCR3,
685 CCR4,
686 CCR5,
687 CCR6,
688 CCR7
689 );
690
691 reg_class int_flags_CR0(CCR0);
692 reg_class int_flags_CR1(CCR1);
693 reg_class int_flags_CR6(CCR6);
694 reg_class ctr_reg(SR_CTR);
695
696 // ----------------------------
697 // Float Register Classes
698 // ----------------------------
699
700 reg_class flt_reg(
701 /*F0*/ // scratch
702 F1,
703 F2,
704 F3,
705 F4,
706 F5,
707 F6,
708 F7,
709 F8,
710 F9,
711 F10,
712 F11,
713 F12,
714 F13,
715 F14, // nv!
716 F15, // nv!
717 F16, // nv!
718 F17, // nv!
719 F18, // nv!
720 F19, // nv!
721 F20, // nv!
722 F21, // nv!
723 F22, // nv!
724 F23, // nv!
725 F24, // nv!
726 F25, // nv!
727 F26, // nv!
728 F27, // nv!
729 F28, // nv!
730 F29, // nv!
731 F30, // nv!
732 F31 // nv!
733 );
734
735 // Double precision float registers have virtual `high halves' that
736 // are needed by the allocator.
737 reg_class dbl_reg(
738 /*F0, F0_H*/ // scratch
739 F1, F1_H,
740 F2, F2_H,
741 F3, F3_H,
742 F4, F4_H,
743 F5, F5_H,
744 F6, F6_H,
745 F7, F7_H,
746 F8, F8_H,
747 F9, F9_H,
748 F10, F10_H,
749 F11, F11_H,
750 F12, F12_H,
751 F13, F13_H,
752 F14, F14_H, // nv!
753 F15, F15_H, // nv!
754 F16, F16_H, // nv!
755 F17, F17_H, // nv!
756 F18, F18_H, // nv!
757 F19, F19_H, // nv!
758 F20, F20_H, // nv!
759 F21, F21_H, // nv!
760 F22, F22_H, // nv!
761 F23, F23_H, // nv!
762 F24, F24_H, // nv!
763 F25, F25_H, // nv!
764 F26, F26_H, // nv!
765 F27, F27_H, // nv!
766 F28, F28_H, // nv!
767 F29, F29_H, // nv!
768 F30, F30_H, // nv!
769 F31, F31_H // nv!
770 );
771
772 %}
773
774 //----------DEFINITION BLOCK---------------------------------------------------
775 // Define name --> value mappings to inform the ADLC of an integer valued name
776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
777 // Format:
778 // int_def <name> ( <int_value>, <expression>);
779 // Generated Code in ad_<arch>.hpp
780 // #define <name> (<expression>)
781 // // value == <int_value>
782 // Generated code in ad_<arch>.cpp adlc_verification()
783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
784 //
785 definitions %{
786 // The default cost (of an ALU instruction).
787 int_def DEFAULT_COST_LOW ( 30, 30);
788 int_def DEFAULT_COST ( 100, 100);
789 int_def HUGE_COST (1000000, 1000000);
790
791 // Memory refs
792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
794
795 // Branches are even more expensive.
796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
797 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
798 %}
799
800
801 //----------SOURCE BLOCK-------------------------------------------------------
802 // This is a block of C++ code which provides values, functions, and
803 // definitions necessary in the rest of the architecture description.
804 source_hpp %{
805 // Header information of the source block.
806 // Method declarations/definitions which are used outside
807 // the ad-scope can conveniently be defined here.
808 //
809 // To keep related declarations/definitions/uses close together,
810 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
811
812 // Returns true if Node n is followed by a MemBar node that
813 // will do an acquire. If so, this node must not do the acquire
814 // operation.
815 bool followed_by_acquire(const Node *n);
816 %}
817
818 source %{
819
820 // Optimize load-acquire.
821 //
822 // Check if acquire is unnecessary due to following operation that does
823 // acquire anyways.
824 // Walk the pattern:
825 //
826 // n: Load.acq
827 // |
828 // MemBarAcquire
829 // | |
830 // Proj(ctrl) Proj(mem)
831 // | |
832 // MemBarRelease/Volatile
833 //
834 bool followed_by_acquire(const Node *load) {
835 assert(load->is_Load(), "So far implemented only for loads.");
836
837 // Find MemBarAcquire.
838 const Node *mba = NULL;
839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
840 const Node *out = load->fast_out(i);
841 if (out->Opcode() == Op_MemBarAcquire) {
842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
843 mba = out;
844 break;
845 }
846 }
847 if (!mba) return false;
848
849 // Find following MemBar node.
850 //
851 // The following node must be reachable by control AND memory
852 // edge to assure no other operations are in between the two nodes.
853 //
854 // So first get the Proj node, mem_proj, to use it to iterate forward.
855 Node *mem_proj = NULL;
856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
858 assert(mem_proj->is_Proj(), "only projections here");
859 ProjNode *proj = mem_proj->as_Proj();
860 if (proj->_con == TypeFunc::Memory &&
861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
862 break;
863 }
864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
865
866 // Search MemBar behind Proj. If there are other memory operations
867 // behind the Proj we lost.
868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
869 Node *x = mem_proj->fast_out(j);
870 // Proj might have an edge to a store or load node which precedes the membar.
871 if (x->is_Mem()) return false;
872
873 // On PPC64 release and volatile are implemented by an instruction
874 // that also has acquire semantics. I.e. there is no need for an
875 // acquire before these.
876 int xop = x->Opcode();
877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
878 // Make sure we're not missing Call/Phi/MergeMem by checking
879 // control edges. The control edge must directly lead back
880 // to the MemBarAcquire
881 Node *ctrl_proj = x->in(0);
882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
883 return true;
884 }
885 }
886 }
887
888 return false;
889 }
890
891 #define __ _masm.
892
893 // Tertiary op of a LoadP or StoreP encoding.
894 #define REGP_OP true
895
896 // ****************************************************************************
897
898 // REQUIRED FUNCTIONALITY
899
900 // !!!!! Special hack to get all type of calls to specify the byte offset
901 // from the start of the call to the point where the return address
902 // will point.
903
904 // PPC port: Removed use of lazy constant construct.
905
906 int MachCallStaticJavaNode::ret_addr_offset() {
907 // It's only a single branch-and-link instruction.
908 return 4;
909 }
910
911 int MachCallDynamicJavaNode::ret_addr_offset() {
912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
913 // postalloc expanded calls if we use inline caches and do not update method data.
914 if (UseInlineCaches)
915 return 4;
916
917 int vtable_index = this->_vtable_index;
918 if (vtable_index < 0) {
919 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
921 return 12;
922 } else {
923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
924 return 24;
925 }
926 }
927
928 int MachCallRuntimeNode::ret_addr_offset() {
929 #if defined(ABI_ELFv2)
930 return 28;
931 #else
932 return 40;
933 #endif
934 }
935
936 //=============================================================================
937
938 // condition code conversions
939
940 static int cc_to_boint(int cc) {
941 return Assembler::bcondCRbiIs0 | (cc & 8);
942 }
943
944 static int cc_to_inverse_boint(int cc) {
945 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
946 }
947
948 static int cc_to_biint(int cc, int flags_reg) {
949 return (flags_reg << 2) | (cc & 3);
950 }
951
952 //=============================================================================
953
954 // Compute padding required for nodes which need alignment. The padding
955 // is the number of bytes (not instructions) which will be inserted before
956 // the instruction. The padding must match the size of a NOP instruction.
957
958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
959 return (3*4-current_offset)&31;
960 }
961
962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
963 return (2*4-current_offset)&31;
964 }
965
966 int string_indexOf_immNode::compute_padding(int current_offset) const {
967 return (3*4-current_offset)&31;
968 }
969
970 int string_indexOfNode::compute_padding(int current_offset) const {
971 return (1*4-current_offset)&31;
972 }
973
974 int string_compareNode::compute_padding(int current_offset) const {
975 return (4*4-current_offset)&31;
976 }
977
978 int string_equals_immNode::compute_padding(int current_offset) const {
979 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
980 return (2*4-current_offset)&31;
981 }
982
983 int string_equalsNode::compute_padding(int current_offset) const {
984 return (7*4-current_offset)&31;
985 }
986
987 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
988 return (2*4-current_offset)&31;
989 }
990
991 //=============================================================================
992
993 // Indicate if the safepoint node needs the polling page as an input.
994 bool SafePointNode::needs_polling_address_input() {
995 // The address is loaded from thread by a seperate node.
996 return true;
997 }
998
999 //=============================================================================
1000
1001 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1002 void emit_break(CodeBuffer &cbuf) {
1003 MacroAssembler _masm(&cbuf);
1004 __ illtrap();
1005 }
1006
1007 #ifndef PRODUCT
1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1009 st->print("BREAKPOINT");
1010 }
1011 #endif
1012
1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1014 emit_break(cbuf);
1015 }
1016
1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1018 return MachNode::size(ra_);
1019 }
1020
1021 //=============================================================================
1022
1023 void emit_nop(CodeBuffer &cbuf) {
1024 MacroAssembler _masm(&cbuf);
1025 __ nop();
1026 }
1027
1028 static inline void emit_long(CodeBuffer &cbuf, int value) {
1029 *((int*)(cbuf.insts_end())) = value;
1030 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1031 }
1032
1033 //=============================================================================
1034
1035 %} // interrupt source
1036
1037 source_hpp %{ // Header information of the source block.
1038
1039 //--------------------------------------------------------------
1040 //---< Used for optimization in Compile::Shorten_branches >---
1041 //--------------------------------------------------------------
1042
1043 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1044
1045 class CallStubImpl {
1046
1047 public:
1048
1049 // Emit call stub, compiled java to interpreter.
1050 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1051
1052 // Size of call trampoline stub.
1053 // This doesn't need to be accurate to the byte, but it
1054 // must be larger than or equal to the real size of the stub.
1055 static uint size_call_trampoline() {
1056 return trampoline_stub_size;
1057 }
1058
1059 // number of relocations needed by a call trampoline stub
1060 static uint reloc_call_trampoline() {
1061 return 5;
1062 }
1063
1064 };
1065
1066 %} // end source_hpp
1067
1068 source %{
1069
1070 // Emit a trampoline stub for a call to a target which is too far away.
1071 //
1072 // code sequences:
1073 //
1074 // call-site:
1075 // branch-and-link to <destination> or <trampoline stub>
1076 //
1077 // Related trampoline stub for this call-site in the stub section:
1078 // load the call target from the constant pool
1079 // branch via CTR (LR/link still points to the call-site above)
1080
1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1082 // Start the stub.
1083 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1084 if (stub == NULL) {
1085 Compile::current()->env()->record_out_of_memory_failure();
1086 return;
1087 }
1088
1089 // For java_to_interp stubs we use R11_scratch1 as scratch register
1090 // and in call trampoline stubs we use R12_scratch2. This way we
1091 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1092 Register reg_scratch = R12_scratch2;
1093
1094 // Create a trampoline stub relocation which relates this trampoline stub
1095 // with the call instruction at insts_call_instruction_offset in the
1096 // instructions code-section.
1097 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1098 const int stub_start_offset = __ offset();
1099
1100 // Now, create the trampoline stub's code:
1101 // - load the TOC
1102 // - load the call target from the constant pool
1103 // - call
1104 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1105 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1106 __ mtctr(reg_scratch);
1107 __ bctr();
1108
1109 const address stub_start_addr = __ addr_at(stub_start_offset);
1110
1111 // FIXME: Assert that the trampoline stub can be identified and patched.
1112
1113 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1114 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1115 "encoded offset into the constant pool must match");
1116 // Trampoline_stub_size should be good.
1117 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1118 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1119
1120 // End the stub.
1121 __ end_a_stub();
1122 }
1123
1124 //=============================================================================
1125
1126 // Emit an inline branch-and-link call and a related trampoline stub.
1127 //
1128 // code sequences:
1129 //
1130 // call-site:
1131 // branch-and-link to <destination> or <trampoline stub>
1132 //
1133 // Related trampoline stub for this call-site in the stub section:
1134 // load the call target from the constant pool
1135 // branch via CTR (LR/link still points to the call-site above)
1136 //
1137
1138 typedef struct {
1139 int insts_call_instruction_offset;
1140 int ret_addr_offset;
1141 } EmitCallOffsets;
1142
1143 // Emit a branch-and-link instruction that branches to a trampoline.
1144 // - Remember the offset of the branch-and-link instruction.
1145 // - Add a relocation at the branch-and-link instruction.
1146 // - Emit a branch-and-link.
1147 // - Remember the return pc offset.
1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1149 EmitCallOffsets offsets = { -1, -1 };
1150 const int start_offset = __ offset();
1151 offsets.insts_call_instruction_offset = __ offset();
1152
1153 // No entry point given, use the current pc.
1154 if (entry_point == NULL) entry_point = __ pc();
1155
1156 if (!Compile::current()->in_scratch_emit_size()) {
1157 // Put the entry point as a constant into the constant pool.
1158 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1159 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1160
1161 // Emit the trampoline stub which will be related to the branch-and-link below.
1162 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1163 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full.
1164 __ relocate(rtype);
1165 }
1166
1167 // Note: At this point we do not have the address of the trampoline
1168 // stub, and the entry point might be too far away for bl, so __ pc()
1169 // serves as dummy and the bl will be patched later.
1170 __ bl((address) __ pc());
1171
1172 offsets.ret_addr_offset = __ offset() - start_offset;
1173
1174 return offsets;
1175 }
1176
1177 //=============================================================================
1178
1179 // Factory for creating loadConL* nodes for large/small constant pool.
1180
1181 static inline jlong replicate_immF(float con) {
1182 // Replicate float con 2 times and pack into vector.
1183 int val = *((int*)&con);
1184 jlong lval = val;
1185 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1186 return lval;
1187 }
1188
1189 //=============================================================================
1190
1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1192 int Compile::ConstantTable::calculate_table_base_offset() const {
1193 return 0; // absolute addressing, no offset
1194 }
1195
1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1198 iRegPdstOper *op_dst = new iRegPdstOper();
1199 MachNode *m1 = new loadToc_hiNode();
1200 MachNode *m2 = new loadToc_loNode();
1201
1202 m1->add_req(NULL);
1203 m2->add_req(NULL, m1);
1204 m1->_opnds[0] = op_dst;
1205 m2->_opnds[0] = op_dst;
1206 m2->_opnds[1] = op_dst;
1207 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1208 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1209 nodes->push(m1);
1210 nodes->push(m2);
1211 }
1212
1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1214 // Is postalloc expanded.
1215 ShouldNotReachHere();
1216 }
1217
1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1219 return 0;
1220 }
1221
1222 #ifndef PRODUCT
1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1224 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1225 }
1226 #endif
1227
1228 //=============================================================================
1229
1230 #ifndef PRODUCT
1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1232 Compile* C = ra_->C;
1233 const long framesize = C->frame_slots() << LogBytesPerInt;
1234
1235 st->print("PROLOG\n\t");
1236 if (C->need_stack_bang(framesize)) {
1237 st->print("stack_overflow_check\n\t");
1238 }
1239
1240 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1241 st->print("save return pc\n\t");
1242 st->print("push frame %ld\n\t", -framesize);
1243 }
1244 }
1245 #endif
1246
1247 // Macro used instead of the common __ to emulate the pipes of PPC.
1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1250 // still no scheduling of this code is possible, the micro scheduler is aware of the
1251 // code and can update its internal data. The following mechanism is used to achieve this:
1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1254 #if 0 // TODO: PPC port
1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1256 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1257 _masm.
1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1259 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1261 C->hb_scheduling()->_pdScheduling->advance_offset
1262 #else
1263 #define ___(op) if (UsePower6SchedulerPPC64) \
1264 Unimplemented(); \
1265 _masm.
1266 #define ___stop if (UsePower6SchedulerPPC64) \
1267 Unimplemented()
1268 #define ___advance if (UsePower6SchedulerPPC64) \
1269 Unimplemented()
1270 #endif
1271
1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273 Compile* C = ra_->C;
1274 MacroAssembler _masm(&cbuf);
1275
1276 const long framesize = C->frame_size_in_bytes();
1277 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1278
1279 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1280
1281 const Register return_pc = R20; // Must match return_addr() in frame section.
1282 const Register callers_sp = R21;
1283 const Register push_frame_temp = R22;
1284 const Register toc_temp = R23;
1285 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1286
1287 if (method_is_frameless) {
1288 // Add nop at beginning of all frameless methods to prevent any
1289 // oop instructions from getting overwritten by make_not_entrant
1290 // (patching attempt would fail).
1291 ___(nop) nop();
1292 } else {
1293 // Get return pc.
1294 ___(mflr) mflr(return_pc);
1295 }
1296
1297 // Calls to C2R adapters often do not accept exceptional returns.
1298 // We require that their callers must bang for them. But be
1299 // careful, because some VM calls (such as call site linkage) can
1300 // use several kilobytes of stack. But the stack safety zone should
1301 // account for that. See bugs 4446381, 4468289, 4497237.
1302
1303 int bangsize = C->bang_size_in_bytes();
1304 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1305 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1306 // Unfortunately we cannot use the function provided in
1307 // assembler.cpp as we have to emulate the pipes. So I had to
1308 // insert the code of generate_stack_overflow_check(), see
1309 // assembler.cpp for some illuminative comments.
1310 const int page_size = os::vm_page_size();
1311 int bang_end = StackShadowPages * page_size;
1312
1313 // This is how far the previous frame's stack banging extended.
1314 const int bang_end_safe = bang_end;
1315
1316 if (bangsize > page_size) {
1317 bang_end += bangsize;
1318 }
1319
1320 int bang_offset = bang_end_safe;
1321
1322 while (bang_offset <= bang_end) {
1323 // Need at least one stack bang at end of shadow zone.
1324
1325 // Again I had to copy code, this time from assembler_ppc.cpp,
1326 // bang_stack_with_offset - see there for comments.
1327
1328 // Stack grows down, caller passes positive offset.
1329 assert(bang_offset > 0, "must bang with positive offset");
1330
1331 long stdoffset = -bang_offset;
1332
1333 if (Assembler::is_simm(stdoffset, 16)) {
1334 // Signed 16 bit offset, a simple std is ok.
1335 if (UseLoadInstructionsForStackBangingPPC64) {
1336 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1337 } else {
1338 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1339 }
1340 } else if (Assembler::is_simm(stdoffset, 31)) {
1341 // Use largeoffset calculations for addis & ld/std.
1342 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1343 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1344
1345 Register tmp = R11;
1346 ___(addis) addis(tmp, R1_SP, hi);
1347 if (UseLoadInstructionsForStackBangingPPC64) {
1348 ___(ld) ld(R0, lo, tmp);
1349 } else {
1350 ___(std) std(R0, lo, tmp);
1351 }
1352 } else {
1353 ShouldNotReachHere();
1354 }
1355
1356 bang_offset += page_size;
1357 }
1358 // R11 trashed
1359 } // C->need_stack_bang(framesize) && UseStackBanging
1360
1361 unsigned int bytes = (unsigned int)framesize;
1362 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1363 ciMethod *currMethod = C->method();
1364
1365 // Optimized version for most common case.
1366 if (UsePower6SchedulerPPC64 &&
1367 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1368 !(false /* ConstantsALot TODO: PPC port*/)) {
1369 ___(or) mr(callers_sp, R1_SP);
1370 ___(std) std(return_pc, _abi(lr), R1_SP);
1371 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1372 return;
1373 }
1374
1375 if (!method_is_frameless) {
1376 // Get callers sp.
1377 ___(or) mr(callers_sp, R1_SP);
1378
1379 // Push method's frame, modifies SP.
1380 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1381 // The ABI is already accounted for in 'framesize' via the
1382 // 'out_preserve' area.
1383 Register tmp = push_frame_temp;
1384 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1385 if (Assembler::is_simm(-offset, 16)) {
1386 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1387 } else {
1388 long x = -offset;
1389 // Had to insert load_const(tmp, -offset).
1390 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1391 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1392 ___(rldicr) sldi(tmp, tmp, 32);
1393 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1394 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1395
1396 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1397 }
1398 }
1399 #if 0 // TODO: PPC port
1400 // For testing large constant pools, emit a lot of constants to constant pool.
1401 // "Randomize" const_size.
1402 if (ConstantsALot) {
1403 const int num_consts = const_size();
1404 for (int i = 0; i < num_consts; i++) {
1405 __ long_constant(0xB0B5B00BBABE);
1406 }
1407 }
1408 #endif
1409 if (!method_is_frameless) {
1410 // Save return pc.
1411 ___(std) std(return_pc, _abi(lr), callers_sp);
1412 }
1413 }
1414 #undef ___
1415 #undef ___stop
1416 #undef ___advance
1417
1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1419 // Variable size. determine dynamically.
1420 return MachNode::size(ra_);
1421 }
1422
1423 int MachPrologNode::reloc() const {
1424 // Return number of relocatable values contained in this instruction.
1425 return 1; // 1 reloc entry for load_const(toc).
1426 }
1427
1428 //=============================================================================
1429
1430 #ifndef PRODUCT
1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1432 Compile* C = ra_->C;
1433
1434 st->print("EPILOG\n\t");
1435 st->print("restore return pc\n\t");
1436 st->print("pop frame\n\t");
1437
1438 if (do_polling() && C->is_method_compilation()) {
1439 st->print("touch polling page\n\t");
1440 }
1441 }
1442 #endif
1443
1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445 Compile* C = ra_->C;
1446 MacroAssembler _masm(&cbuf);
1447
1448 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1449 assert(framesize >= 0, "negative frame-size?");
1450
1451 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1452 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1453 const Register return_pc = R11;
1454 const Register polling_page = R12;
1455
1456 if (!method_is_frameless) {
1457 // Restore return pc relative to callers' sp.
1458 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1459 }
1460
1461 if (method_needs_polling) {
1462 if (LoadPollAddressFromThread) {
1463 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1464 Unimplemented();
1465 } else {
1466 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1467 }
1468 }
1469
1470 if (!method_is_frameless) {
1471 // Move return pc to LR.
1472 __ mtlr(return_pc);
1473 // Pop frame (fixed frame-size).
1474 __ addi(R1_SP, R1_SP, (int)framesize);
1475 }
1476
1477 if (method_needs_polling) {
1478 // We need to mark the code position where the load from the safepoint
1479 // polling page was emitted as relocInfo::poll_return_type here.
1480 __ relocate(relocInfo::poll_return_type);
1481 __ load_from_polling_page(polling_page);
1482 }
1483 }
1484
1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1486 // Variable size. Determine dynamically.
1487 return MachNode::size(ra_);
1488 }
1489
1490 int MachEpilogNode::reloc() const {
1491 // Return number of relocatable values contained in this instruction.
1492 return 1; // 1 for load_from_polling_page.
1493 }
1494
1495 const Pipeline * MachEpilogNode::pipeline() const {
1496 return MachNode::pipeline_class();
1497 }
1498
1499 // This method seems to be obsolete. It is declared in machnode.hpp
1500 // and defined in all *.ad files, but it is never called. Should we
1501 // get rid of it?
1502 int MachEpilogNode::safepoint_offset() const {
1503 assert(do_polling(), "no return for this epilog node");
1504 return 0;
1505 }
1506
1507 #if 0 // TODO: PPC port
1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1509 MacroAssembler _masm(&cbuf);
1510 if (LoadPollAddressFromThread) {
1511 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1512 } else {
1513 _masm.nop();
1514 }
1515 }
1516
1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1518 if (LoadPollAddressFromThread) {
1519 return 4;
1520 } else {
1521 return 4;
1522 }
1523 }
1524
1525 #ifndef PRODUCT
1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1527 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1528 }
1529 #endif
1530
1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1532 return RSCRATCH1_BITS64_REG_mask();
1533 }
1534 #endif // PPC port
1535
1536 // =============================================================================
1537
1538 // Figure out which register class each belongs in: rc_int, rc_float or
1539 // rc_stack.
1540 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1541
1542 static enum RC rc_class(OptoReg::Name reg) {
1543 // Return the register class for the given register. The given register
1544 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1545 // enumeration in adGlobals_ppc.hpp.
1546
1547 if (reg == OptoReg::Bad) return rc_bad;
1548
1549 // We have 64 integer register halves, starting at index 0.
1550 if (reg < 64) return rc_int;
1551
1552 // We have 64 floating-point register halves, starting at index 64.
1553 if (reg < 64+64) return rc_float;
1554
1555 // Between float regs & stack are the flags regs.
1556 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1557
1558 return rc_stack;
1559 }
1560
1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1562 bool do_print, Compile* C, outputStream *st) {
1563
1564 assert(opcode == Assembler::LD_OPCODE ||
1565 opcode == Assembler::STD_OPCODE ||
1566 opcode == Assembler::LWZ_OPCODE ||
1567 opcode == Assembler::STW_OPCODE ||
1568 opcode == Assembler::LFD_OPCODE ||
1569 opcode == Assembler::STFD_OPCODE ||
1570 opcode == Assembler::LFS_OPCODE ||
1571 opcode == Assembler::STFS_OPCODE,
1572 "opcode not supported");
1573
1574 if (cbuf) {
1575 int d =
1576 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1577 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1578 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1579 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1580 }
1581 #ifndef PRODUCT
1582 else if (do_print) {
1583 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1584 op_str,
1585 Matcher::regName[reg],
1586 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1587 }
1588 #endif
1589 return 4; // size
1590 }
1591
1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1593 Compile* C = ra_->C;
1594
1595 // Get registers to move.
1596 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1597 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1598 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1599 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1600
1601 enum RC src_hi_rc = rc_class(src_hi);
1602 enum RC src_lo_rc = rc_class(src_lo);
1603 enum RC dst_hi_rc = rc_class(dst_hi);
1604 enum RC dst_lo_rc = rc_class(dst_lo);
1605
1606 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1607 if (src_hi != OptoReg::Bad)
1608 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1609 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1610 "expected aligned-adjacent pairs");
1611 // Generate spill code!
1612 int size = 0;
1613
1614 if (src_lo == dst_lo && src_hi == dst_hi)
1615 return size; // Self copy, no move.
1616
1617 // --------------------------------------
1618 // Memory->Memory Spill. Use R0 to hold the value.
1619 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1620 int src_offset = ra_->reg2offset(src_lo);
1621 int dst_offset = ra_->reg2offset(dst_lo);
1622 if (src_hi != OptoReg::Bad) {
1623 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1624 "expected same type of move for high parts");
1625 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1626 if (!cbuf && !do_size) st->print("\n\t");
1627 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1628 } else {
1629 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1630 if (!cbuf && !do_size) st->print("\n\t");
1631 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1632 }
1633 return size;
1634 }
1635
1636 // --------------------------------------
1637 // Check for float->int copy; requires a trip through memory.
1638 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1639 Unimplemented();
1640 }
1641
1642 // --------------------------------------
1643 // Check for integer reg-reg copy.
1644 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1645 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1646 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1647 size = (Rsrc != Rdst) ? 4 : 0;
1648
1649 if (cbuf) {
1650 MacroAssembler _masm(cbuf);
1651 if (size) {
1652 __ mr(Rdst, Rsrc);
1653 }
1654 }
1655 #ifndef PRODUCT
1656 else if (!do_size) {
1657 if (size) {
1658 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1659 } else {
1660 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1661 }
1662 }
1663 #endif
1664 return size;
1665 }
1666
1667 // Check for integer store.
1668 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1669 int dst_offset = ra_->reg2offset(dst_lo);
1670 if (src_hi != OptoReg::Bad) {
1671 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1672 "expected same type of move for high parts");
1673 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1674 } else {
1675 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1676 }
1677 return size;
1678 }
1679
1680 // Check for integer load.
1681 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1682 int src_offset = ra_->reg2offset(src_lo);
1683 if (src_hi != OptoReg::Bad) {
1684 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1685 "expected same type of move for high parts");
1686 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1687 } else {
1688 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1689 }
1690 return size;
1691 }
1692
1693 // Check for float reg-reg copy.
1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1695 if (cbuf) {
1696 MacroAssembler _masm(cbuf);
1697 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1698 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1699 __ fmr(Rdst, Rsrc);
1700 }
1701 #ifndef PRODUCT
1702 else if (!do_size) {
1703 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1704 }
1705 #endif
1706 return 4;
1707 }
1708
1709 // Check for float store.
1710 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1711 int dst_offset = ra_->reg2offset(dst_lo);
1712 if (src_hi != OptoReg::Bad) {
1713 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1714 "expected same type of move for high parts");
1715 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1716 } else {
1717 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1718 }
1719 return size;
1720 }
1721
1722 // Check for float load.
1723 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1724 int src_offset = ra_->reg2offset(src_lo);
1725 if (src_hi != OptoReg::Bad) {
1726 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1727 "expected same type of move for high parts");
1728 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1729 } else {
1730 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1731 }
1732 return size;
1733 }
1734
1735 // --------------------------------------------------------------------
1736 // Check for hi bits still needing moving. Only happens for misaligned
1737 // arguments to native calls.
1738 if (src_hi == dst_hi)
1739 return size; // Self copy; no move.
1740
1741 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1742 ShouldNotReachHere(); // Unimplemented
1743 return 0;
1744 }
1745
1746 #ifndef PRODUCT
1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748 if (!ra_)
1749 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1750 else
1751 implementation(NULL, ra_, false, st);
1752 }
1753 #endif
1754
1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1756 implementation(&cbuf, ra_, false, NULL);
1757 }
1758
1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1760 return implementation(NULL, ra_, true, NULL);
1761 }
1762
1763 #if 0 // TODO: PPC port
1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1765 #ifndef PRODUCT
1766 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1767 #endif
1768 assert(ra_->node_regs_max_index() != 0, "");
1769
1770 // Get registers to move.
1771 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1772 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1773 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1774 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1775
1776 enum RC src_lo_rc = rc_class(src_lo);
1777 enum RC dst_lo_rc = rc_class(dst_lo);
1778
1779 if (src_lo == dst_lo && src_hi == dst_hi)
1780 return ppc64Opcode_none; // Self copy, no move.
1781
1782 // --------------------------------------
1783 // Memory->Memory Spill. Use R0 to hold the value.
1784 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1785 return ppc64Opcode_compound;
1786 }
1787
1788 // --------------------------------------
1789 // Check for float->int copy; requires a trip through memory.
1790 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1791 Unimplemented();
1792 }
1793
1794 // --------------------------------------
1795 // Check for integer reg-reg copy.
1796 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1797 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1798 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1799 if (Rsrc == Rdst) {
1800 return ppc64Opcode_none;
1801 } else {
1802 return ppc64Opcode_or;
1803 }
1804 }
1805
1806 // Check for integer store.
1807 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1808 if (src_hi != OptoReg::Bad) {
1809 return ppc64Opcode_std;
1810 } else {
1811 return ppc64Opcode_stw;
1812 }
1813 }
1814
1815 // Check for integer load.
1816 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1817 if (src_hi != OptoReg::Bad) {
1818 return ppc64Opcode_ld;
1819 } else {
1820 return ppc64Opcode_lwz;
1821 }
1822 }
1823
1824 // Check for float reg-reg copy.
1825 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1826 return ppc64Opcode_fmr;
1827 }
1828
1829 // Check for float store.
1830 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1831 if (src_hi != OptoReg::Bad) {
1832 return ppc64Opcode_stfd;
1833 } else {
1834 return ppc64Opcode_stfs;
1835 }
1836 }
1837
1838 // Check for float load.
1839 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1840 if (src_hi != OptoReg::Bad) {
1841 return ppc64Opcode_lfd;
1842 } else {
1843 return ppc64Opcode_lfs;
1844 }
1845 }
1846
1847 // --------------------------------------------------------------------
1848 // Check for hi bits still needing moving. Only happens for misaligned
1849 // arguments to native calls.
1850 if (src_hi == dst_hi) {
1851 return ppc64Opcode_none; // Self copy; no move.
1852 }
1853
1854 ShouldNotReachHere();
1855 return ppc64Opcode_undefined;
1856 }
1857 #endif // PPC port
1858
1859 #ifndef PRODUCT
1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1861 st->print("NOP \t// %d nops to pad for loops.", _count);
1862 }
1863 #endif
1864
1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1866 MacroAssembler _masm(&cbuf);
1867 // _count contains the number of nops needed for padding.
1868 for (int i = 0; i < _count; i++) {
1869 __ nop();
1870 }
1871 }
1872
1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1874 return _count * 4;
1875 }
1876
1877 #ifndef PRODUCT
1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1879 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1880 char reg_str[128];
1881 ra_->dump_register(this, reg_str);
1882 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1883 }
1884 #endif
1885
1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1887 MacroAssembler _masm(&cbuf);
1888
1889 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1890 int reg = ra_->get_encode(this);
1891
1892 if (Assembler::is_simm(offset, 16)) {
1893 __ addi(as_Register(reg), R1, offset);
1894 } else {
1895 ShouldNotReachHere();
1896 }
1897 }
1898
1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1900 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1901 return 4;
1902 }
1903
1904 #ifndef PRODUCT
1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1906 st->print_cr("---- MachUEPNode ----");
1907 st->print_cr("...");
1908 }
1909 #endif
1910
1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1912 // This is the unverified entry point.
1913 MacroAssembler _masm(&cbuf);
1914
1915 // Inline_cache contains a klass.
1916 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1917 Register receiver_klass = R12_scratch2; // tmp
1918
1919 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1920 assert(R11_scratch1 == R11, "need prologue scratch register");
1921
1922 // Check for NULL argument if we don't have implicit null checks.
1923 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1924 if (TrapBasedNullChecks) {
1925 __ trap_null_check(R3_ARG1);
1926 } else {
1927 Label valid;
1928 __ cmpdi(CCR0, R3_ARG1, 0);
1929 __ bne_predict_taken(CCR0, valid);
1930 // We have a null argument, branch to ic_miss_stub.
1931 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1932 relocInfo::runtime_call_type);
1933 __ bind(valid);
1934 }
1935 }
1936 // Assume argument is not NULL, load klass from receiver.
1937 __ load_klass(receiver_klass, R3_ARG1);
1938
1939 if (TrapBasedICMissChecks) {
1940 __ trap_ic_miss_check(receiver_klass, ic_klass);
1941 } else {
1942 Label valid;
1943 __ cmpd(CCR0, receiver_klass, ic_klass);
1944 __ beq_predict_taken(CCR0, valid);
1945 // We have an unexpected klass, branch to ic_miss_stub.
1946 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1947 relocInfo::runtime_call_type);
1948 __ bind(valid);
1949 }
1950
1951 // Argument is valid and klass is as expected, continue.
1952 }
1953
1954 #if 0 // TODO: PPC port
1955 // Optimize UEP code on z (save a load_const() call in main path).
1956 int MachUEPNode::ep_offset() {
1957 return 0;
1958 }
1959 #endif
1960
1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1962 // Variable size. Determine dynamically.
1963 return MachNode::size(ra_);
1964 }
1965
1966 //=============================================================================
1967
1968 %} // interrupt source
1969
1970 source_hpp %{ // Header information of the source block.
1971
1972 class HandlerImpl {
1973
1974 public:
1975
1976 static int emit_exception_handler(CodeBuffer &cbuf);
1977 static int emit_deopt_handler(CodeBuffer& cbuf);
1978
1979 static uint size_exception_handler() {
1980 // The exception_handler is a b64_patchable.
1981 return MacroAssembler::b64_patchable_size;
1982 }
1983
1984 static uint size_deopt_handler() {
1985 // The deopt_handler is a bl64_patchable.
1986 return MacroAssembler::bl64_patchable_size;
1987 }
1988
1989 };
1990
1991 %} // end source_hpp
1992
1993 source %{
1994
1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1996 MacroAssembler _masm(&cbuf);
1997
1998 address base = __ start_a_stub(size_exception_handler());
1999 if (base == NULL) return 0; // CodeBuffer::expand failed
2000
2001 int offset = __ offset();
2002 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2003 relocInfo::runtime_call_type);
2004 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2005 __ end_a_stub();
2006
2007 return offset;
2008 }
2009
2010 // The deopt_handler is like the exception handler, but it calls to
2011 // the deoptimization blob instead of jumping to the exception blob.
2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2013 MacroAssembler _masm(&cbuf);
2014
2015 address base = __ start_a_stub(size_deopt_handler());
2016 if (base == NULL) return 0; // CodeBuffer::expand failed
2017
2018 int offset = __ offset();
2019 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2020 relocInfo::runtime_call_type);
2021 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2022 __ end_a_stub();
2023
2024 return offset;
2025 }
2026
2027 //=============================================================================
2028
2029 // Use a frame slots bias for frameless methods if accessing the stack.
2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2031 if (as_Register(reg_enc) == R1_SP) {
2032 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2033 }
2034 return 0;
2035 }
2036
2037 const bool Matcher::match_rule_supported(int opcode) {
2038 if (!has_match_rule(opcode))
2039 return false;
2040
2041 switch (opcode) {
2042 case Op_SqrtD:
2043 return VM_Version::has_fsqrt();
2044 case Op_CountLeadingZerosI:
2045 case Op_CountLeadingZerosL:
2046 case Op_CountTrailingZerosI:
2047 case Op_CountTrailingZerosL:
2048 if (!UseCountLeadingZerosInstructionsPPC64)
2049 return false;
2050 break;
2051
2052 case Op_PopCountI:
2053 case Op_PopCountL:
2054 return (UsePopCountInstruction && VM_Version::has_popcntw());
2055
2056 case Op_StrComp:
2057 return SpecialStringCompareTo;
2058 case Op_StrEquals:
2059 return SpecialStringEquals;
2060 case Op_StrIndexOf:
2061 return SpecialStringIndexOf;
2062 }
2063
2064 return true; // Per default match rules are supported.
2065 }
2066
2067 int Matcher::regnum_to_fpu_offset(int regnum) {
2068 // No user for this method?
2069 Unimplemented();
2070 return 999;
2071 }
2072
2073 const bool Matcher::convL2FSupported(void) {
2074 // fcfids can do the conversion (>= Power7).
2075 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2076 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2077 }
2078
2079 // Vector width in bytes.
2080 const int Matcher::vector_width_in_bytes(BasicType bt) {
2081 assert(MaxVectorSize == 8, "");
2082 return 8;
2083 }
2084
2085 // Vector ideal reg.
2086 const int Matcher::vector_ideal_reg(int size) {
2087 assert(MaxVectorSize == 8 && size == 8, "");
2088 return Op_RegL;
2089 }
2090
2091 const int Matcher::vector_shift_count_ideal_reg(int size) {
2092 fatal("vector shift is not supported");
2093 return Node::NotAMachineReg;
2094 }
2095
2096 // Limits on vector size (number of elements) loaded into vector.
2097 const int Matcher::max_vector_size(const BasicType bt) {
2098 assert(is_java_primitive(bt), "only primitive type vectors");
2099 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2100 }
2101
2102 const int Matcher::min_vector_size(const BasicType bt) {
2103 return max_vector_size(bt); // Same as max.
2104 }
2105
2106 // PPC doesn't support misaligned vectors store/load.
2107 const bool Matcher::misaligned_vectors_ok() {
2108 return false;
2109 }
2110
2111 // PPC AES support not yet implemented
2112 const bool Matcher::pass_original_key_for_aes() {
2113 return false;
2114 }
2115
2116 // RETURNS: whether this branch offset is short enough that a short
2117 // branch can be used.
2118 //
2119 // If the platform does not provide any short branch variants, then
2120 // this method should return `false' for offset 0.
2121 //
2122 // `Compile::Fill_buffer' will decide on basis of this information
2123 // whether to do the pass `Compile::Shorten_branches' at all.
2124 //
2125 // And `Compile::Shorten_branches' will decide on basis of this
2126 // information whether to replace particular branch sites by short
2127 // ones.
2128 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2129 // Is the offset within the range of a ppc64 pc relative branch?
2130 bool b;
2131
2132 const int safety_zone = 3 * BytesPerInstWord;
2133 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2134 29 - 16 + 1 + 2);
2135 return b;
2136 }
2137
2138 const bool Matcher::isSimpleConstant64(jlong value) {
2139 // Probably always true, even if a temp register is required.
2140 return true;
2141 }
2142 /* TODO: PPC port
2143 // Make a new machine dependent decode node (with its operands).
2144 MachTypeNode *Matcher::make_decode_node() {
2145 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2146 "This method is only implemented for unscaled cOops mode so far");
2147 MachTypeNode *decode = new decodeN_unscaledNode();
2148 decode->set_opnd_array(0, new iRegPdstOper());
2149 decode->set_opnd_array(1, new iRegNsrcOper());
2150 return decode;
2151 }
2152 */
2153 // Threshold size for cleararray.
2154 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2155
2156 // false => size gets scaled to BytesPerLong, ok.
2157 const bool Matcher::init_array_count_is_in_bytes = false;
2158
2159 // Use conditional move (CMOVL) on Power7.
2160 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2161
2162 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2163 // fsel doesn't accept a condition register as input, so this would be slightly different.
2164 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2165
2166 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2167 const bool Matcher::require_postalloc_expand = true;
2168
2169 // Should the Matcher clone shifts on addressing modes, expecting them to
2170 // be subsumed into complex addressing expressions or compute them into
2171 // registers? True for Intel but false for most RISCs.
2172 const bool Matcher::clone_shift_expressions = false;
2173
2174 // Do we need to mask the count passed to shift instructions or does
2175 // the cpu only look at the lower 5/6 bits anyway?
2176 // PowerPC requires masked shift counts.
2177 const bool Matcher::need_masked_shift_count = true;
2178
2179 // This affects two different things:
2180 // - how Decode nodes are matched
2181 // - how ImplicitNullCheck opportunities are recognized
2182 // If true, the matcher will try to remove all Decodes and match them
2183 // (as operands) into nodes. NullChecks are not prepared to deal with
2184 // Decodes by final_graph_reshaping().
2185 // If false, final_graph_reshaping() forces the decode behind the Cmp
2186 // for a NullCheck. The matcher matches the Decode node into a register.
2187 // Implicit_null_check optimization moves the Decode along with the
2188 // memory operation back up before the NullCheck.
2189 bool Matcher::narrow_oop_use_complex_address() {
2190 // TODO: PPC port if (MatchDecodeNodes) return true;
2191 return false;
2192 }
2193
2194 bool Matcher::narrow_klass_use_complex_address() {
2195 NOT_LP64(ShouldNotCallThis());
2196 assert(UseCompressedClassPointers, "only for compressed klass code");
2197 // TODO: PPC port if (MatchDecodeNodes) return true;
2198 return false;
2199 }
2200
2201 // Is it better to copy float constants, or load them directly from memory?
2202 // Intel can load a float constant from a direct address, requiring no
2203 // extra registers. Most RISCs will have to materialize an address into a
2204 // register first, so they would do better to copy the constant from stack.
2205 const bool Matcher::rematerialize_float_constants = false;
2206
2207 // If CPU can load and store mis-aligned doubles directly then no fixup is
2208 // needed. Else we split the double into 2 integer pieces and move it
2209 // piece-by-piece. Only happens when passing doubles into C code as the
2210 // Java calling convention forces doubles to be aligned.
2211 const bool Matcher::misaligned_doubles_ok = true;
2212
2213 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2214 Unimplemented();
2215 }
2216
2217 // Advertise here if the CPU requires explicit rounding operations
2218 // to implement the UseStrictFP mode.
2219 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2220
2221 // Do floats take an entire double register or just half?
2222 //
2223 // A float occupies a ppc64 double register. For the allocator, a
2224 // ppc64 double register appears as a pair of float registers.
2225 bool Matcher::float_in_double() { return true; }
2226
2227 // Do ints take an entire long register or just half?
2228 // The relevant question is how the int is callee-saved:
2229 // the whole long is written but de-opt'ing will have to extract
2230 // the relevant 32 bits.
2231 const bool Matcher::int_in_long = true;
2232
2233 // Constants for c2c and c calling conventions.
2234
2235 const MachRegisterNumbers iarg_reg[8] = {
2236 R3_num, R4_num, R5_num, R6_num,
2237 R7_num, R8_num, R9_num, R10_num
2238 };
2239
2240 const MachRegisterNumbers farg_reg[13] = {
2241 F1_num, F2_num, F3_num, F4_num,
2242 F5_num, F6_num, F7_num, F8_num,
2243 F9_num, F10_num, F11_num, F12_num,
2244 F13_num
2245 };
2246
2247 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2248
2249 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2250
2251 // Return whether or not this register is ever used as an argument. This
2252 // function is used on startup to build the trampoline stubs in generateOptoStub.
2253 // Registers not mentioned will be killed by the VM call in the trampoline, and
2254 // arguments in those registers not be available to the callee.
2255 bool Matcher::can_be_java_arg(int reg) {
2256 // We return true for all registers contained in iarg_reg[] and
2257 // farg_reg[] and their virtual halves.
2258 // We must include the virtual halves in order to get STDs and LDs
2259 // instead of STWs and LWs in the trampoline stubs.
2260
2261 if ( reg == R3_num || reg == R3_H_num
2262 || reg == R4_num || reg == R4_H_num
2263 || reg == R5_num || reg == R5_H_num
2264 || reg == R6_num || reg == R6_H_num
2265 || reg == R7_num || reg == R7_H_num
2266 || reg == R8_num || reg == R8_H_num
2267 || reg == R9_num || reg == R9_H_num
2268 || reg == R10_num || reg == R10_H_num)
2269 return true;
2270
2271 if ( reg == F1_num || reg == F1_H_num
2272 || reg == F2_num || reg == F2_H_num
2273 || reg == F3_num || reg == F3_H_num
2274 || reg == F4_num || reg == F4_H_num
2275 || reg == F5_num || reg == F5_H_num
2276 || reg == F6_num || reg == F6_H_num
2277 || reg == F7_num || reg == F7_H_num
2278 || reg == F8_num || reg == F8_H_num
2279 || reg == F9_num || reg == F9_H_num
2280 || reg == F10_num || reg == F10_H_num
2281 || reg == F11_num || reg == F11_H_num
2282 || reg == F12_num || reg == F12_H_num
2283 || reg == F13_num || reg == F13_H_num)
2284 return true;
2285
2286 return false;
2287 }
2288
2289 bool Matcher::is_spillable_arg(int reg) {
2290 return can_be_java_arg(reg);
2291 }
2292
2293 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2294 return false;
2295 }
2296
2297 // Register for DIVI projection of divmodI.
2298 RegMask Matcher::divI_proj_mask() {
2299 ShouldNotReachHere();
2300 return RegMask();
2301 }
2302
2303 // Register for MODI projection of divmodI.
2304 RegMask Matcher::modI_proj_mask() {
2305 ShouldNotReachHere();
2306 return RegMask();
2307 }
2308
2309 // Register for DIVL projection of divmodL.
2310 RegMask Matcher::divL_proj_mask() {
2311 ShouldNotReachHere();
2312 return RegMask();
2313 }
2314
2315 // Register for MODL projection of divmodL.
2316 RegMask Matcher::modL_proj_mask() {
2317 ShouldNotReachHere();
2318 return RegMask();
2319 }
2320
2321 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2322 return RegMask();
2323 }
2324
2325 %}
2326
2327 //----------ENCODING BLOCK-----------------------------------------------------
2328 // This block specifies the encoding classes used by the compiler to output
2329 // byte streams. Encoding classes are parameterized macros used by
2330 // Machine Instruction Nodes in order to generate the bit encoding of the
2331 // instruction. Operands specify their base encoding interface with the
2332 // interface keyword. There are currently supported four interfaces,
2333 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2334 // operand to generate a function which returns its register number when
2335 // queried. CONST_INTER causes an operand to generate a function which
2336 // returns the value of the constant when queried. MEMORY_INTER causes an
2337 // operand to generate four functions which return the Base Register, the
2338 // Index Register, the Scale Value, and the Offset Value of the operand when
2339 // queried. COND_INTER causes an operand to generate six functions which
2340 // return the encoding code (ie - encoding bits for the instruction)
2341 // associated with each basic boolean condition for a conditional instruction.
2342 //
2343 // Instructions specify two basic values for encoding. Again, a function
2344 // is available to check if the constant displacement is an oop. They use the
2345 // ins_encode keyword to specify their encoding classes (which must be
2346 // a sequence of enc_class names, and their parameters, specified in
2347 // the encoding block), and they use the
2348 // opcode keyword to specify, in order, their primary, secondary, and
2349 // tertiary opcode. Only the opcode sections which a particular instruction
2350 // needs for encoding need to be specified.
2351 encode %{
2352 enc_class enc_unimplemented %{
2353 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2354 MacroAssembler _masm(&cbuf);
2355 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2356 %}
2357
2358 enc_class enc_untested %{
2359 #ifdef ASSERT
2360 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2361 MacroAssembler _masm(&cbuf);
2362 __ untested("Untested mach node encoding in AD file.");
2363 #else
2364 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2365 #endif
2366 %}
2367
2368 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2369 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2370 MacroAssembler _masm(&cbuf);
2371 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2372 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2373 %}
2374
2375 // Load acquire.
2376 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2377 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2378 MacroAssembler _masm(&cbuf);
2379 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2380 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2381 __ twi_0($dst$$Register);
2382 __ isync();
2383 %}
2384
2385 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2386 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2387
2388 MacroAssembler _masm(&cbuf);
2389 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2390 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2391 %}
2392
2393 // Load acquire.
2394 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2395 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2396
2397 MacroAssembler _masm(&cbuf);
2398 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2399 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2400 __ twi_0($dst$$Register);
2401 __ isync();
2402 %}
2403
2404 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2405 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2406
2407 MacroAssembler _masm(&cbuf);
2408 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2409 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2410 %}
2411
2412 // Load acquire.
2413 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2414 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2415
2416 MacroAssembler _masm(&cbuf);
2417 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2418 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2419 __ twi_0($dst$$Register);
2420 __ isync();
2421 %}
2422
2423 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2424 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2425 MacroAssembler _masm(&cbuf);
2426 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2427 // Operand 'ds' requires 4-alignment.
2428 assert((Idisp & 0x3) == 0, "unaligned offset");
2429 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2430 %}
2431
2432 // Load acquire.
2433 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2434 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2435 MacroAssembler _masm(&cbuf);
2436 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2437 // Operand 'ds' requires 4-alignment.
2438 assert((Idisp & 0x3) == 0, "unaligned offset");
2439 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2440 __ twi_0($dst$$Register);
2441 __ isync();
2442 %}
2443
2444 enc_class enc_lfd(RegF dst, memory mem) %{
2445 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2446 MacroAssembler _masm(&cbuf);
2447 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2448 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2449 %}
2450
2451 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2452 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2453
2454 MacroAssembler _masm(&cbuf);
2455 int toc_offset = 0;
2456
2457 if (!ra_->C->in_scratch_emit_size()) {
2458 address const_toc_addr;
2459 // Create a non-oop constant, no relocation needed.
2460 // If it is an IC, it has a virtual_call_Relocation.
2461 const_toc_addr = __ long_constant((jlong)$src$$constant);
2462
2463 // Get the constant's TOC offset.
2464 toc_offset = __ offset_to_method_toc(const_toc_addr);
2465
2466 // Keep the current instruction offset in mind.
2467 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2468 }
2469
2470 __ ld($dst$$Register, toc_offset, $toc$$Register);
2471 %}
2472
2473 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2474 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2475
2476 MacroAssembler _masm(&cbuf);
2477
2478 if (!ra_->C->in_scratch_emit_size()) {
2479 address const_toc_addr;
2480 // Create a non-oop constant, no relocation needed.
2481 // If it is an IC, it has a virtual_call_Relocation.
2482 const_toc_addr = __ long_constant((jlong)$src$$constant);
2483
2484 // Get the constant's TOC offset.
2485 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2486 // Store the toc offset of the constant.
2487 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2488
2489 // Also keep the current instruction offset in mind.
2490 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2491 }
2492
2493 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2494 %}
2495
2496 %} // encode
2497
2498 source %{
2499
2500 typedef struct {
2501 loadConL_hiNode *_large_hi;
2502 loadConL_loNode *_large_lo;
2503 loadConLNode *_small;
2504 MachNode *_last;
2505 } loadConLNodesTuple;
2506
2507 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2508 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2509 loadConLNodesTuple nodes;
2510
2511 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2512 if (large_constant_pool) {
2513 // Create new nodes.
2514 loadConL_hiNode *m1 = new loadConL_hiNode();
2515 loadConL_loNode *m2 = new loadConL_loNode();
2516
2517 // inputs for new nodes
2518 m1->add_req(NULL, toc);
2519 m2->add_req(NULL, m1);
2520
2521 // operands for new nodes
2522 m1->_opnds[0] = new iRegLdstOper(); // dst
2523 m1->_opnds[1] = immSrc; // src
2524 m1->_opnds[2] = new iRegPdstOper(); // toc
2525 m2->_opnds[0] = new iRegLdstOper(); // dst
2526 m2->_opnds[1] = immSrc; // src
2527 m2->_opnds[2] = new iRegLdstOper(); // base
2528
2529 // Initialize ins_attrib TOC fields.
2530 m1->_const_toc_offset = -1;
2531 m2->_const_toc_offset_hi_node = m1;
2532
2533 // Initialize ins_attrib instruction offset.
2534 m1->_cbuf_insts_offset = -1;
2535
2536 // register allocation for new nodes
2537 ra_->set_pair(m1->_idx, reg_second, reg_first);
2538 ra_->set_pair(m2->_idx, reg_second, reg_first);
2539
2540 // Create result.
2541 nodes._large_hi = m1;
2542 nodes._large_lo = m2;
2543 nodes._small = NULL;
2544 nodes._last = nodes._large_lo;
2545 assert(m2->bottom_type()->isa_long(), "must be long");
2546 } else {
2547 loadConLNode *m2 = new loadConLNode();
2548
2549 // inputs for new nodes
2550 m2->add_req(NULL, toc);
2551
2552 // operands for new nodes
2553 m2->_opnds[0] = new iRegLdstOper(); // dst
2554 m2->_opnds[1] = immSrc; // src
2555 m2->_opnds[2] = new iRegPdstOper(); // toc
2556
2557 // Initialize ins_attrib instruction offset.
2558 m2->_cbuf_insts_offset = -1;
2559
2560 // register allocation for new nodes
2561 ra_->set_pair(m2->_idx, reg_second, reg_first);
2562
2563 // Create result.
2564 nodes._large_hi = NULL;
2565 nodes._large_lo = NULL;
2566 nodes._small = m2;
2567 nodes._last = nodes._small;
2568 assert(m2->bottom_type()->isa_long(), "must be long");
2569 }
2570
2571 return nodes;
2572 }
2573
2574 %} // source
2575
2576 encode %{
2577 // Postalloc expand emitter for loading a long constant from the method's TOC.
2578 // Enc_class needed as consttanttablebase is not supported by postalloc
2579 // expand.
2580 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2581 // Create new nodes.
2582 loadConLNodesTuple loadConLNodes =
2583 loadConLNodesTuple_create(ra_, n_toc, op_src,
2584 ra_->get_reg_second(this), ra_->get_reg_first(this));
2585
2586 // Push new nodes.
2587 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2588 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2589
2590 // some asserts
2591 assert(nodes->length() >= 1, "must have created at least 1 node");
2592 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2593 %}
2594
2595 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2596 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2597
2598 MacroAssembler _masm(&cbuf);
2599 int toc_offset = 0;
2600
2601 if (!ra_->C->in_scratch_emit_size()) {
2602 intptr_t val = $src$$constant;
2603 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2604 address const_toc_addr;
2605 if (constant_reloc == relocInfo::oop_type) {
2606 // Create an oop constant and a corresponding relocation.
2607 AddressLiteral a = __ allocate_oop_address((jobject)val);
2608 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2609 __ relocate(a.rspec());
2610 } else if (constant_reloc == relocInfo::metadata_type) {
2611 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2612 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2613 __ relocate(a.rspec());
2614 } else {
2615 // Create a non-oop constant, no relocation needed.
2616 const_toc_addr = __ long_constant((jlong)$src$$constant);
2617 }
2618
2619 // Get the constant's TOC offset.
2620 toc_offset = __ offset_to_method_toc(const_toc_addr);
2621 }
2622
2623 __ ld($dst$$Register, toc_offset, $toc$$Register);
2624 %}
2625
2626 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2627 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2628
2629 MacroAssembler _masm(&cbuf);
2630 if (!ra_->C->in_scratch_emit_size()) {
2631 intptr_t val = $src$$constant;
2632 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2633 address const_toc_addr;
2634 if (constant_reloc == relocInfo::oop_type) {
2635 // Create an oop constant and a corresponding relocation.
2636 AddressLiteral a = __ allocate_oop_address((jobject)val);
2637 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2638 __ relocate(a.rspec());
2639 } else if (constant_reloc == relocInfo::metadata_type) {
2640 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2641 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2642 __ relocate(a.rspec());
2643 } else { // non-oop pointers, e.g. card mark base, heap top
2644 // Create a non-oop constant, no relocation needed.
2645 const_toc_addr = __ long_constant((jlong)$src$$constant);
2646 }
2647
2648 // Get the constant's TOC offset.
2649 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2650 // Store the toc offset of the constant.
2651 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2652 }
2653
2654 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2655 %}
2656
2657 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2658 // Enc_class needed as consttanttablebase is not supported by postalloc
2659 // expand.
2660 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2661 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2662 if (large_constant_pool) {
2663 // Create new nodes.
2664 loadConP_hiNode *m1 = new loadConP_hiNode();
2665 loadConP_loNode *m2 = new loadConP_loNode();
2666
2667 // inputs for new nodes
2668 m1->add_req(NULL, n_toc);
2669 m2->add_req(NULL, m1);
2670
2671 // operands for new nodes
2672 m1->_opnds[0] = new iRegPdstOper(); // dst
2673 m1->_opnds[1] = op_src; // src
2674 m1->_opnds[2] = new iRegPdstOper(); // toc
2675 m2->_opnds[0] = new iRegPdstOper(); // dst
2676 m2->_opnds[1] = op_src; // src
2677 m2->_opnds[2] = new iRegLdstOper(); // base
2678
2679 // Initialize ins_attrib TOC fields.
2680 m1->_const_toc_offset = -1;
2681 m2->_const_toc_offset_hi_node = m1;
2682
2683 // Register allocation for new nodes.
2684 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2685 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2686
2687 nodes->push(m1);
2688 nodes->push(m2);
2689 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2690 } else {
2691 loadConPNode *m2 = new loadConPNode();
2692
2693 // inputs for new nodes
2694 m2->add_req(NULL, n_toc);
2695
2696 // operands for new nodes
2697 m2->_opnds[0] = new iRegPdstOper(); // dst
2698 m2->_opnds[1] = op_src; // src
2699 m2->_opnds[2] = new iRegPdstOper(); // toc
2700
2701 // Register allocation for new nodes.
2702 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2703
2704 nodes->push(m2);
2705 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2706 }
2707 %}
2708
2709 // Enc_class needed as consttanttablebase is not supported by postalloc
2710 // expand.
2711 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2712 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2713
2714 MachNode *m2;
2715 if (large_constant_pool) {
2716 m2 = new loadConFCompNode();
2717 } else {
2718 m2 = new loadConFNode();
2719 }
2720 // inputs for new nodes
2721 m2->add_req(NULL, n_toc);
2722
2723 // operands for new nodes
2724 m2->_opnds[0] = op_dst;
2725 m2->_opnds[1] = op_src;
2726 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2727
2728 // register allocation for new nodes
2729 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2730 nodes->push(m2);
2731 %}
2732
2733 // Enc_class needed as consttanttablebase is not supported by postalloc
2734 // expand.
2735 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2736 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2737
2738 MachNode *m2;
2739 if (large_constant_pool) {
2740 m2 = new loadConDCompNode();
2741 } else {
2742 m2 = new loadConDNode();
2743 }
2744 // inputs for new nodes
2745 m2->add_req(NULL, n_toc);
2746
2747 // operands for new nodes
2748 m2->_opnds[0] = op_dst;
2749 m2->_opnds[1] = op_src;
2750 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2751
2752 // register allocation for new nodes
2753 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2754 nodes->push(m2);
2755 %}
2756
2757 enc_class enc_stw(iRegIsrc src, memory mem) %{
2758 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2759 MacroAssembler _masm(&cbuf);
2760 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2761 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2762 %}
2763
2764 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2765 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2766 MacroAssembler _masm(&cbuf);
2767 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2768 // Operand 'ds' requires 4-alignment.
2769 assert((Idisp & 0x3) == 0, "unaligned offset");
2770 __ std($src$$Register, Idisp, $mem$$base$$Register);
2771 %}
2772
2773 enc_class enc_stfs(RegF src, memory mem) %{
2774 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2775 MacroAssembler _masm(&cbuf);
2776 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2777 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2778 %}
2779
2780 enc_class enc_stfd(RegF src, memory mem) %{
2781 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2782 MacroAssembler _masm(&cbuf);
2783 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2784 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2785 %}
2786
2787 // Use release_store for card-marking to ensure that previous
2788 // oop-stores are visible before the card-mark change.
2789 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2790 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2791 // FIXME: Implement this as a cmove and use a fixed condition code
2792 // register which is written on every transition to compiled code,
2793 // e.g. in call-stub and when returning from runtime stubs.
2794 //
2795 // Proposed code sequence for the cmove implementation:
2796 //
2797 // Label skip_release;
2798 // __ beq(CCRfixed, skip_release);
2799 // __ release();
2800 // __ bind(skip_release);
2801 // __ stb(card mark);
2802
2803 MacroAssembler _masm(&cbuf);
2804 Label skip_storestore;
2805
2806 #if 0 // TODO: PPC port
2807 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2808 // StoreStore barrier conditionally.
2809 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2810 __ cmpwi($crx$$CondRegister, R0, 0);
2811 __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2812 #endif
2813 __ li(R0, 0);
2814 __ membar(Assembler::StoreStore);
2815 #if 0 // TODO: PPC port
2816 __ bind(skip_storestore);
2817 #endif
2818
2819 // Do the store.
2820 if ($mem$$index == 0) {
2821 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2822 } else {
2823 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2824 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2825 }
2826 %}
2827
2828 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2829
2830 if (VM_Version::has_isel()) {
2831 // use isel instruction with Power 7
2832 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2833 encodeP_subNode *n_sub_base = new encodeP_subNode();
2834 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2835 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2836
2837 n_compare->add_req(n_region, n_src);
2838 n_compare->_opnds[0] = op_crx;
2839 n_compare->_opnds[1] = op_src;
2840 n_compare->_opnds[2] = new immL16Oper(0);
2841
2842 n_sub_base->add_req(n_region, n_src);
2843 n_sub_base->_opnds[0] = op_dst;
2844 n_sub_base->_opnds[1] = op_src;
2845 n_sub_base->_bottom_type = _bottom_type;
2846
2847 n_shift->add_req(n_region, n_sub_base);
2848 n_shift->_opnds[0] = op_dst;
2849 n_shift->_opnds[1] = op_dst;
2850 n_shift->_bottom_type = _bottom_type;
2851
2852 n_cond_set->add_req(n_region, n_compare, n_shift);
2853 n_cond_set->_opnds[0] = op_dst;
2854 n_cond_set->_opnds[1] = op_crx;
2855 n_cond_set->_opnds[2] = op_dst;
2856 n_cond_set->_bottom_type = _bottom_type;
2857
2858 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2859 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2860 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2861 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2862
2863 nodes->push(n_compare);
2864 nodes->push(n_sub_base);
2865 nodes->push(n_shift);
2866 nodes->push(n_cond_set);
2867
2868 } else {
2869 // before Power 7
2870 moveRegNode *n_move = new moveRegNode();
2871 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2872 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2873 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2874
2875 n_move->add_req(n_region, n_src);
2876 n_move->_opnds[0] = op_dst;
2877 n_move->_opnds[1] = op_src;
2878 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2879
2880 n_compare->add_req(n_region, n_src);
2881 n_compare->add_prec(n_move);
2882
2883 n_compare->_opnds[0] = op_crx;
2884 n_compare->_opnds[1] = op_src;
2885 n_compare->_opnds[2] = new immL16Oper(0);
2886
2887 n_sub_base->add_req(n_region, n_compare, n_src);
2888 n_sub_base->_opnds[0] = op_dst;
2889 n_sub_base->_opnds[1] = op_crx;
2890 n_sub_base->_opnds[2] = op_src;
2891 n_sub_base->_bottom_type = _bottom_type;
2892
2893 n_shift->add_req(n_region, n_sub_base);
2894 n_shift->_opnds[0] = op_dst;
2895 n_shift->_opnds[1] = op_dst;
2896 n_shift->_bottom_type = _bottom_type;
2897
2898 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2899 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2900 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2901 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2902
2903 nodes->push(n_move);
2904 nodes->push(n_compare);
2905 nodes->push(n_sub_base);
2906 nodes->push(n_shift);
2907 }
2908
2909 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2910 %}
2911
2912 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2913
2914 encodeP_subNode *n1 = new encodeP_subNode();
2915 n1->add_req(n_region, n_src);
2916 n1->_opnds[0] = op_dst;
2917 n1->_opnds[1] = op_src;
2918 n1->_bottom_type = _bottom_type;
2919
2920 encodeP_shiftNode *n2 = new encodeP_shiftNode();
2921 n2->add_req(n_region, n1);
2922 n2->_opnds[0] = op_dst;
2923 n2->_opnds[1] = op_dst;
2924 n2->_bottom_type = _bottom_type;
2925 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2926 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2927
2928 nodes->push(n1);
2929 nodes->push(n2);
2930 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2931 %}
2932
2933 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2934 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
2935 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
2936
2937 n_compare->add_req(n_region, n_src);
2938 n_compare->_opnds[0] = op_crx;
2939 n_compare->_opnds[1] = op_src;
2940 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2941
2942 n_shift->add_req(n_region, n_src);
2943 n_shift->_opnds[0] = op_dst;
2944 n_shift->_opnds[1] = op_src;
2945 n_shift->_bottom_type = _bottom_type;
2946
2947 if (VM_Version::has_isel()) {
2948 // use isel instruction with Power 7
2949
2950 decodeN_addNode *n_add_base = new decodeN_addNode();
2951 n_add_base->add_req(n_region, n_shift);
2952 n_add_base->_opnds[0] = op_dst;
2953 n_add_base->_opnds[1] = op_dst;
2954 n_add_base->_bottom_type = _bottom_type;
2955
2956 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2957 n_cond_set->add_req(n_region, n_compare, n_add_base);
2958 n_cond_set->_opnds[0] = op_dst;
2959 n_cond_set->_opnds[1] = op_crx;
2960 n_cond_set->_opnds[2] = op_dst;
2961 n_cond_set->_bottom_type = _bottom_type;
2962
2963 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2964 ra_->set_oop(n_cond_set, true);
2965
2966 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2967 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2968 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2969 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2970
2971 nodes->push(n_compare);
2972 nodes->push(n_shift);
2973 nodes->push(n_add_base);
2974 nodes->push(n_cond_set);
2975
2976 } else {
2977 // before Power 7
2978 cond_add_baseNode *n_add_base = new cond_add_baseNode();
2979
2980 n_add_base->add_req(n_region, n_compare, n_shift);
2981 n_add_base->_opnds[0] = op_dst;
2982 n_add_base->_opnds[1] = op_crx;
2983 n_add_base->_opnds[2] = op_dst;
2984 n_add_base->_bottom_type = _bottom_type;
2985
2986 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2987 ra_->set_oop(n_add_base, true);
2988
2989 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2990 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2991 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2992
2993 nodes->push(n_compare);
2994 nodes->push(n_shift);
2995 nodes->push(n_add_base);
2996 }
2997 %}
2998
2999 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3000 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3001 n1->add_req(n_region, n_src);
3002 n1->_opnds[0] = op_dst;
3003 n1->_opnds[1] = op_src;
3004 n1->_bottom_type = _bottom_type;
3005
3006 decodeN_addNode *n2 = new decodeN_addNode();
3007 n2->add_req(n_region, n1);
3008 n2->_opnds[0] = op_dst;
3009 n2->_opnds[1] = op_dst;
3010 n2->_bottom_type = _bottom_type;
3011 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3012 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3013
3014 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3015 ra_->set_oop(n2, true);
3016
3017 nodes->push(n1);
3018 nodes->push(n2);
3019 %}
3020
3021 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3022 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3023
3024 MacroAssembler _masm(&cbuf);
3025 int cc = $cmp$$cmpcode;
3026 int flags_reg = $crx$$reg;
3027 Label done;
3028 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3029 // Branch if not (cmp crx).
3030 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3031 __ mr($dst$$Register, $src$$Register);
3032 // TODO PPC port __ endgroup_if_needed(_size == 12);
3033 __ bind(done);
3034 %}
3035
3036 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3037 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3038
3039 MacroAssembler _masm(&cbuf);
3040 Label done;
3041 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3042 // Branch if not (cmp crx).
3043 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3044 __ li($dst$$Register, $src$$constant);
3045 // TODO PPC port __ endgroup_if_needed(_size == 12);
3046 __ bind(done);
3047 %}
3048
3049 // New atomics.
3050 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3051 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3052
3053 MacroAssembler _masm(&cbuf);
3054 Register Rtmp = R0;
3055 Register Rres = $res$$Register;
3056 Register Rsrc = $src$$Register;
3057 Register Rptr = $mem_ptr$$Register;
3058 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3059 Register Rold = RegCollision ? Rtmp : Rres;
3060
3061 Label Lretry;
3062 __ bind(Lretry);
3063 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3064 __ add(Rtmp, Rsrc, Rold);
3065 __ stwcx_(Rtmp, Rptr);
3066 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3067 __ bne_predict_not_taken(CCR0, Lretry);
3068 } else {
3069 __ bne( CCR0, Lretry);
3070 }
3071 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3072 __ fence();
3073 %}
3074
3075 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3076 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3077
3078 MacroAssembler _masm(&cbuf);
3079 Register Rtmp = R0;
3080 Register Rres = $res$$Register;
3081 Register Rsrc = $src$$Register;
3082 Register Rptr = $mem_ptr$$Register;
3083 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3084 Register Rold = RegCollision ? Rtmp : Rres;
3085
3086 Label Lretry;
3087 __ bind(Lretry);
3088 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3089 __ add(Rtmp, Rsrc, Rold);
3090 __ stdcx_(Rtmp, Rptr);
3091 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3092 __ bne_predict_not_taken(CCR0, Lretry);
3093 } else {
3094 __ bne( CCR0, Lretry);
3095 }
3096 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3097 __ fence();
3098 %}
3099
3100 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3101 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3102
3103 MacroAssembler _masm(&cbuf);
3104 Register Rtmp = R0;
3105 Register Rres = $res$$Register;
3106 Register Rsrc = $src$$Register;
3107 Register Rptr = $mem_ptr$$Register;
3108 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3109 Register Rold = RegCollision ? Rtmp : Rres;
3110
3111 Label Lretry;
3112 __ bind(Lretry);
3113 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3114 __ stwcx_(Rsrc, Rptr);
3115 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3116 __ bne_predict_not_taken(CCR0, Lretry);
3117 } else {
3118 __ bne( CCR0, Lretry);
3119 }
3120 if (RegCollision) __ mr(Rres, Rtmp);
3121 __ fence();
3122 %}
3123
3124 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3125 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3126
3127 MacroAssembler _masm(&cbuf);
3128 Register Rtmp = R0;
3129 Register Rres = $res$$Register;
3130 Register Rsrc = $src$$Register;
3131 Register Rptr = $mem_ptr$$Register;
3132 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3133 Register Rold = RegCollision ? Rtmp : Rres;
3134
3135 Label Lretry;
3136 __ bind(Lretry);
3137 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3138 __ stdcx_(Rsrc, Rptr);
3139 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3140 __ bne_predict_not_taken(CCR0, Lretry);
3141 } else {
3142 __ bne( CCR0, Lretry);
3143 }
3144 if (RegCollision) __ mr(Rres, Rtmp);
3145 __ fence();
3146 %}
3147
3148 // This enc_class is needed so that scheduler gets proper
3149 // input mapping for latency computation.
3150 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3151 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3152 MacroAssembler _masm(&cbuf);
3153 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3154 %}
3155
3156 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3157 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3158
3159 MacroAssembler _masm(&cbuf);
3160
3161 Label done;
3162 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3163 __ li($dst$$Register, $zero$$constant);
3164 __ beq($crx$$CondRegister, done);
3165 __ li($dst$$Register, $notzero$$constant);
3166 __ bind(done);
3167 %}
3168
3169 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3170 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3171
3172 MacroAssembler _masm(&cbuf);
3173
3174 Label done;
3175 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3176 __ li($dst$$Register, $zero$$constant);
3177 __ beq($crx$$CondRegister, done);
3178 __ li($dst$$Register, $notzero$$constant);
3179 __ bind(done);
3180 %}
3181
3182 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3183 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3184
3185 MacroAssembler _masm(&cbuf);
3186 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3187 Label done;
3188 __ bso($crx$$CondRegister, done);
3189 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3190 // TODO PPC port __ endgroup_if_needed(_size == 12);
3191 __ bind(done);
3192 %}
3193
3194 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3195 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3196
3197 MacroAssembler _masm(&cbuf);
3198 Label d; // dummy
3199 __ bind(d);
3200 Label* p = ($lbl$$label);
3201 // `p' is `NULL' when this encoding class is used only to
3202 // determine the size of the encoded instruction.
3203 Label& l = (NULL == p)? d : *(p);
3204 int cc = $cmp$$cmpcode;
3205 int flags_reg = $crx$$reg;
3206 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3207 int bhint = Assembler::bhintNoHint;
3208
3209 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3210 if (_prob <= PROB_NEVER) {
3211 bhint = Assembler::bhintIsNotTaken;
3212 } else if (_prob >= PROB_ALWAYS) {
3213 bhint = Assembler::bhintIsTaken;
3214 }
3215 }
3216
3217 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3218 cc_to_biint(cc, flags_reg),
3219 l);
3220 %}
3221
3222 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3223 // The scheduler doesn't know about branch shortening, so we set the opcode
3224 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3225 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3226
3227 MacroAssembler _masm(&cbuf);
3228 Label d; // dummy
3229 __ bind(d);
3230 Label* p = ($lbl$$label);
3231 // `p' is `NULL' when this encoding class is used only to
3232 // determine the size of the encoded instruction.
3233 Label& l = (NULL == p)? d : *(p);
3234 int cc = $cmp$$cmpcode;
3235 int flags_reg = $crx$$reg;
3236 int bhint = Assembler::bhintNoHint;
3237
3238 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3239 if (_prob <= PROB_NEVER) {
3240 bhint = Assembler::bhintIsNotTaken;
3241 } else if (_prob >= PROB_ALWAYS) {
3242 bhint = Assembler::bhintIsTaken;
3243 }
3244 }
3245
3246 // Tell the conditional far branch to optimize itself when being relocated.
3247 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3248 cc_to_biint(cc, flags_reg),
3249 l,
3250 MacroAssembler::bc_far_optimize_on_relocate);
3251 %}
3252
3253 // Branch used with Power6 scheduling (can be shortened without changing the node).
3254 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3255 // The scheduler doesn't know about branch shortening, so we set the opcode
3256 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3257 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3258
3259 MacroAssembler _masm(&cbuf);
3260 Label d; // dummy
3261 __ bind(d);
3262 Label* p = ($lbl$$label);
3263 // `p' is `NULL' when this encoding class is used only to
3264 // determine the size of the encoded instruction.
3265 Label& l = (NULL == p)? d : *(p);
3266 int cc = $cmp$$cmpcode;
3267 int flags_reg = $crx$$reg;
3268 int bhint = Assembler::bhintNoHint;
3269
3270 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3271 if (_prob <= PROB_NEVER) {
3272 bhint = Assembler::bhintIsNotTaken;
3273 } else if (_prob >= PROB_ALWAYS) {
3274 bhint = Assembler::bhintIsTaken;
3275 }
3276 }
3277
3278 #if 0 // TODO: PPC port
3279 if (_size == 8) {
3280 // Tell the conditional far branch to optimize itself when being relocated.
3281 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3282 cc_to_biint(cc, flags_reg),
3283 l,
3284 MacroAssembler::bc_far_optimize_on_relocate);
3285 } else {
3286 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3287 cc_to_biint(cc, flags_reg),
3288 l);
3289 }
3290 #endif
3291 Unimplemented();
3292 %}
3293
3294 // Postalloc expand emitter for loading a replicatef float constant from
3295 // the method's TOC.
3296 // Enc_class needed as consttanttablebase is not supported by postalloc
3297 // expand.
3298 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3299 // Create new nodes.
3300
3301 // Make an operand with the bit pattern to load as float.
3302 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3303
3304 loadConLNodesTuple loadConLNodes =
3305 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3306 ra_->get_reg_second(this), ra_->get_reg_first(this));
3307
3308 // Push new nodes.
3309 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3310 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3311
3312 assert(nodes->length() >= 1, "must have created at least 1 node");
3313 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3314 %}
3315
3316 // This enc_class is needed so that scheduler gets proper
3317 // input mapping for latency computation.
3318 enc_class enc_poll(immI dst, iRegLdst poll) %{
3319 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3320 // Fake operand dst needed for PPC scheduler.
3321 assert($dst$$constant == 0x0, "dst must be 0x0");
3322
3323 MacroAssembler _masm(&cbuf);
3324 // Mark the code position where the load from the safepoint
3325 // polling page was emitted as relocInfo::poll_type.
3326 __ relocate(relocInfo::poll_type);
3327 __ load_from_polling_page($poll$$Register);
3328 %}
3329
3330 // A Java static call or a runtime call.
3331 //
3332 // Branch-and-link relative to a trampoline.
3333 // The trampoline loads the target address and does a long branch to there.
3334 // In case we call java, the trampoline branches to a interpreter_stub
3335 // which loads the inline cache and the real call target from the constant pool.
3336 //
3337 // This basically looks like this:
3338 //
3339 // >>>> consts -+ -+
3340 // | |- offset1
3341 // [call target1] | <-+
3342 // [IC cache] |- offset2
3343 // [call target2] <--+
3344 //
3345 // <<<< consts
3346 // >>>> insts
3347 //
3348 // bl offset16 -+ -+ ??? // How many bits available?
3349 // | |
3350 // <<<< insts | |
3351 // >>>> stubs | |
3352 // | |- trampoline_stub_Reloc
3353 // trampoline stub: | <-+
3354 // r2 = toc |
3355 // r2 = [r2 + offset1] | // Load call target1 from const section
3356 // mtctr r2 |
3357 // bctr |- static_stub_Reloc
3358 // comp_to_interp_stub: <---+
3359 // r1 = toc
3360 // ICreg = [r1 + IC_offset] // Load IC from const section
3361 // r1 = [r1 + offset2] // Load call target2 from const section
3362 // mtctr r1
3363 // bctr
3364 //
3365 // <<<< stubs
3366 //
3367 // The call instruction in the code either
3368 // - Branches directly to a compiled method if the offset is encodable in instruction.
3369 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3370 // - Branches to the compiled_to_interp stub if the target is interpreted.
3371 //
3372 // Further there are three relocations from the loads to the constants in
3373 // the constant section.
3374 //
3375 // Usage of r1 and r2 in the stubs allows to distinguish them.
3376 enc_class enc_java_static_call(method meth) %{
3377 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3378
3379 MacroAssembler _masm(&cbuf);
3380 address entry_point = (address)$meth$$method;
3381
3382 if (!_method) {
3383 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3384 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3385 } else {
3386 // Remember the offset not the address.
3387 const int start_offset = __ offset();
3388 // The trampoline stub.
3389 if (!Compile::current()->in_scratch_emit_size()) {
3390 // No entry point given, use the current pc.
3391 // Make sure branch fits into
3392 if (entry_point == 0) entry_point = __ pc();
3393
3394 // Put the entry point as a constant into the constant pool.
3395 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3396 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3397
3398 // Emit the trampoline stub which will be related to the branch-and-link below.
3399 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3400 if (Compile::current()->env()->failing()) { return; } // Code cache may be full.
3401 __ relocate(_optimized_virtual ?
3402 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3403 }
3404
3405 // The real call.
3406 // Note: At this point we do not have the address of the trampoline
3407 // stub, and the entry point might be too far away for bl, so __ pc()
3408 // serves as dummy and the bl will be patched later.
3409 cbuf.set_insts_mark();
3410 __ bl(__ pc()); // Emits a relocation.
3411
3412 // The stub for call to interpreter.
3413 CompiledStaticCall::emit_to_interp_stub(cbuf);
3414 }
3415 %}
3416
3417 // Emit a method handle call.
3418 //
3419 // Method handle calls from compiled to compiled are going thru a
3420 // c2i -> i2c adapter, extending the frame for their arguments. The
3421 // caller however, returns directly to the compiled callee, that has
3422 // to cope with the extended frame. We restore the original frame by
3423 // loading the callers sp and adding the calculated framesize.
3424 enc_class enc_java_handle_call(method meth) %{
3425 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3426
3427 MacroAssembler _masm(&cbuf);
3428 address entry_point = (address)$meth$$method;
3429
3430 // Remember the offset not the address.
3431 const int start_offset = __ offset();
3432 // The trampoline stub.
3433 if (!ra_->C->in_scratch_emit_size()) {
3434 // No entry point given, use the current pc.
3435 // Make sure branch fits into
3436 if (entry_point == 0) entry_point = __ pc();
3437
3438 // Put the entry point as a constant into the constant pool.
3439 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3440 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3441
3442 // Emit the trampoline stub which will be related to the branch-and-link below.
3443 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3444 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3445 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3446 __ relocate(relocInfo::opt_virtual_call_type);
3447 }
3448
3449 // The real call.
3450 // Note: At this point we do not have the address of the trampoline
3451 // stub, and the entry point might be too far away for bl, so __ pc()
3452 // serves as dummy and the bl will be patched later.
3453 cbuf.set_insts_mark();
3454 __ bl(__ pc()); // Emits a relocation.
3455
3456 assert(_method, "execute next statement conditionally");
3457 // The stub for call to interpreter.
3458 CompiledStaticCall::emit_to_interp_stub(cbuf);
3459
3460 // Restore original sp.
3461 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3462 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3463 unsigned int bytes = (unsigned int)framesize;
3464 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3465 if (Assembler::is_simm(-offset, 16)) {
3466 __ addi(R1_SP, R11_scratch1, -offset);
3467 } else {
3468 __ load_const_optimized(R12_scratch2, -offset);
3469 __ add(R1_SP, R11_scratch1, R12_scratch2);
3470 }
3471 #ifdef ASSERT
3472 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3473 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3474 __ asm_assert_eq("backlink changed", 0x8000);
3475 #endif
3476 // If fails should store backlink before unextending.
3477
3478 if (ra_->C->env()->failing()) {
3479 return;
3480 }
3481 %}
3482
3483 // Second node of expanded dynamic call - the call.
3484 enc_class enc_java_dynamic_call_sched(method meth) %{
3485 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3486
3487 MacroAssembler _masm(&cbuf);
3488
3489 if (!ra_->C->in_scratch_emit_size()) {
3490 // Create a call trampoline stub for the given method.
3491 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3492 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3493 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3494 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3495 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3496
3497 // Build relocation at call site with ic position as data.
3498 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3499 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3500 "must have one, but can't have both");
3501 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3502 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3503 "must contain instruction offset");
3504 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3505 ? _load_ic_hi_node->_cbuf_insts_offset
3506 : _load_ic_node->_cbuf_insts_offset;
3507 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3508 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3509 "should be load from TOC");
3510
3511 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3512 }
3513
3514 // At this point I do not have the address of the trampoline stub,
3515 // and the entry point might be too far away for bl. Pc() serves
3516 // as dummy and bl will be patched later.
3517 __ bl((address) __ pc());
3518 %}
3519
3520 // postalloc expand emitter for virtual calls.
3521 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3522
3523 // Create the nodes for loading the IC from the TOC.
3524 loadConLNodesTuple loadConLNodes_IC =
3525 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3526 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3527
3528 // Create the call node.
3529 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3530 call->_method_handle_invoke = _method_handle_invoke;
3531 call->_vtable_index = _vtable_index;
3532 call->_method = _method;
3533 call->_bci = _bci;
3534 call->_optimized_virtual = _optimized_virtual;
3535 call->_tf = _tf;
3536 call->_entry_point = _entry_point;
3537 call->_cnt = _cnt;
3538 call->_argsize = _argsize;
3539 call->_oop_map = _oop_map;
3540 call->_jvms = _jvms;
3541 call->_jvmadj = _jvmadj;
3542 call->_in_rms = _in_rms;
3543 call->_nesting = _nesting;
3544
3545 // New call needs all inputs of old call.
3546 // Req...
3547 for (uint i = 0; i < req(); ++i) {
3548 // The expanded node does not need toc any more.
3549 // Add the inline cache constant here instead. This expresses the
3550 // register of the inline cache must be live at the call.
3551 // Else we would have to adapt JVMState by -1.
3552 if (i == mach_constant_base_node_input()) {
3553 call->add_req(loadConLNodes_IC._last);
3554 } else {
3555 call->add_req(in(i));
3556 }
3557 }
3558 // ...as well as prec
3559 for (uint i = req(); i < len(); ++i) {
3560 call->add_prec(in(i));
3561 }
3562
3563 // Remember nodes loading the inline cache into r19.
3564 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3565 call->_load_ic_node = loadConLNodes_IC._small;
3566
3567 // Operands for new nodes.
3568 call->_opnds[0] = _opnds[0];
3569 call->_opnds[1] = _opnds[1];
3570
3571 // Only the inline cache is associated with a register.
3572 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3573
3574 // Push new nodes.
3575 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3576 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3577 nodes->push(call);
3578 %}
3579
3580 // Compound version of call dynamic
3581 // Toc is only passed so that it can be used in ins_encode statement.
3582 // In the code we have to use $constanttablebase.
3583 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3584 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3585 MacroAssembler _masm(&cbuf);
3586 int start_offset = __ offset();
3587
3588 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3589 #if 0
3590 int vtable_index = this->_vtable_index;
3591 if (_vtable_index < 0) {
3592 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3593 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3594 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3595
3596 // Virtual call relocation will point to ic load.
3597 address virtual_call_meta_addr = __ pc();
3598 // Load a clear inline cache.
3599 AddressLiteral empty_ic((address) Universe::non_oop_word());
3600 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3601 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3602 // to determine who we intended to call.
3603 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3604 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3605 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3606 "Fix constant in ret_addr_offset()");
3607 } else {
3608 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3609 // Go thru the vtable. Get receiver klass. Receiver already
3610 // checked for non-null. If we'll go thru a C2I adapter, the
3611 // interpreter expects method in R19_method.
3612
3613 __ load_klass(R11_scratch1, R3);
3614
3615 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3616 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3617 __ li(R19_method, v_off);
3618 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3619 // NOTE: for vtable dispatches, the vtable entry will never be
3620 // null. However it may very well end up in handle_wrong_method
3621 // if the method is abstract for the particular class.
3622 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3623 // Call target. Either compiled code or C2I adapter.
3624 __ mtctr(R11_scratch1);
3625 __ bctrl();
3626 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3627 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3628 }
3629 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3630 "Fix constant in ret_addr_offset()");
3631 }
3632 #endif
3633 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3634 %}
3635
3636 // a runtime call
3637 enc_class enc_java_to_runtime_call (method meth) %{
3638 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3639
3640 MacroAssembler _masm(&cbuf);
3641 const address start_pc = __ pc();
3642
3643 #if defined(ABI_ELFv2)
3644 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3645 __ call_c(entry, relocInfo::runtime_call_type);
3646 #else
3647 // The function we're going to call.
3648 FunctionDescriptor fdtemp;
3649 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3650
3651 Register Rtoc = R12_scratch2;
3652 // Calculate the method's TOC.
3653 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3654 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3655 // pool entries; call_c_using_toc will optimize the call.
3656 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3657 #endif
3658
3659 // Check the ret_addr_offset.
3660 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3661 "Fix constant in ret_addr_offset()");
3662 %}
3663
3664 // Move to ctr for leaf call.
3665 // This enc_class is needed so that scheduler gets proper
3666 // input mapping for latency computation.
3667 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3668 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3669 MacroAssembler _masm(&cbuf);
3670 __ mtctr($src$$Register);
3671 %}
3672
3673 // Postalloc expand emitter for runtime leaf calls.
3674 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3675 loadConLNodesTuple loadConLNodes_Entry;
3676 #if defined(ABI_ELFv2)
3677 jlong entry_address = (jlong) this->entry_point();
3678 assert(entry_address, "need address here");
3679 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3680 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3681 #else
3682 // Get the struct that describes the function we are about to call.
3683 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3684 assert(fd, "need fd here");
3685 jlong entry_address = (jlong) fd->entry();
3686 // new nodes
3687 loadConLNodesTuple loadConLNodes_Env;
3688 loadConLNodesTuple loadConLNodes_Toc;
3689
3690 // Create nodes and operands for loading the entry point.
3691 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3692 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3693
3694
3695 // Create nodes and operands for loading the env pointer.
3696 if (fd->env() != NULL) {
3697 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3698 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3699 } else {
3700 loadConLNodes_Env._large_hi = NULL;
3701 loadConLNodes_Env._large_lo = NULL;
3702 loadConLNodes_Env._small = NULL;
3703 loadConLNodes_Env._last = new loadConL16Node();
3704 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3705 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3706 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3707 }
3708
3709 // Create nodes and operands for loading the Toc point.
3710 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3711 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3712 #endif // ABI_ELFv2
3713 // mtctr node
3714 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3715
3716 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3717 mtctr->add_req(0, loadConLNodes_Entry._last);
3718
3719 mtctr->_opnds[0] = new iRegLdstOper();
3720 mtctr->_opnds[1] = new iRegLdstOper();
3721
3722 // call node
3723 MachCallLeafNode *call = new CallLeafDirectNode();
3724
3725 call->_opnds[0] = _opnds[0];
3726 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3727
3728 // Make the new call node look like the old one.
3729 call->_name = _name;
3730 call->_tf = _tf;
3731 call->_entry_point = _entry_point;
3732 call->_cnt = _cnt;
3733 call->_argsize = _argsize;
3734 call->_oop_map = _oop_map;
3735 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3736 call->_jvms = NULL;
3737 call->_jvmadj = _jvmadj;
3738 call->_in_rms = _in_rms;
3739 call->_nesting = _nesting;
3740
3741
3742 // New call needs all inputs of old call.
3743 // Req...
3744 for (uint i = 0; i < req(); ++i) {
3745 if (i != mach_constant_base_node_input()) {
3746 call->add_req(in(i));
3747 }
3748 }
3749
3750 // These must be reqired edges, as the registers are live up to
3751 // the call. Else the constants are handled as kills.
3752 call->add_req(mtctr);
3753 #if !defined(ABI_ELFv2)
3754 call->add_req(loadConLNodes_Env._last);
3755 call->add_req(loadConLNodes_Toc._last);
3756 #endif
3757
3758 // ...as well as prec
3759 for (uint i = req(); i < len(); ++i) {
3760 call->add_prec(in(i));
3761 }
3762
3763 // registers
3764 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3765
3766 // Insert the new nodes.
3767 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3768 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3769 #if !defined(ABI_ELFv2)
3770 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3771 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3772 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3773 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3774 #endif
3775 nodes->push(mtctr);
3776 nodes->push(call);
3777 %}
3778 %}
3779
3780 //----------FRAME--------------------------------------------------------------
3781 // Definition of frame structure and management information.
3782
3783 frame %{
3784 // What direction does stack grow in (assumed to be same for native & Java).
3785 stack_direction(TOWARDS_LOW);
3786
3787 // These two registers define part of the calling convention between
3788 // compiled code and the interpreter.
3789
3790 // Inline Cache Register or method for I2C.
3791 inline_cache_reg(R19); // R19_method
3792
3793 // Method Oop Register when calling interpreter.
3794 interpreter_method_oop_reg(R19); // R19_method
3795
3796 // Optional: name the operand used by cisc-spilling to access
3797 // [stack_pointer + offset].
3798 cisc_spilling_operand_name(indOffset);
3799
3800 // Number of stack slots consumed by a Monitor enter.
3801 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3802
3803 // Compiled code's Frame Pointer.
3804 frame_pointer(R1); // R1_SP
3805
3806 // Interpreter stores its frame pointer in a register which is
3807 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3808 // interpreted java to compiled java.
3809 //
3810 // R14_state holds pointer to caller's cInterpreter.
3811 interpreter_frame_pointer(R14); // R14_state
3812
3813 stack_alignment(frame::alignment_in_bytes);
3814
3815 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3816
3817 // Number of outgoing stack slots killed above the
3818 // out_preserve_stack_slots for calls to C. Supports the var-args
3819 // backing area for register parms.
3820 //
3821 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3822
3823 // The after-PROLOG location of the return address. Location of
3824 // return address specifies a type (REG or STACK) and a number
3825 // representing the register number (i.e. - use a register name) or
3826 // stack slot.
3827 //
3828 // A: Link register is stored in stack slot ...
3829 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3830 // J: Therefore, we make sure that the link register is also in R11_scratch1
3831 // at the end of the prolog.
3832 // B: We use R20, now.
3833 //return_addr(REG R20);
3834
3835 // G: After reading the comments made by all the luminaries on their
3836 // failure to tell the compiler where the return address really is,
3837 // I hardly dare to try myself. However, I'm convinced it's in slot
3838 // 4 what apparently works and saves us some spills.
3839 return_addr(STACK 4);
3840
3841 // This is the body of the function
3842 //
3843 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3844 // uint length, // length of array
3845 // bool is_outgoing)
3846 //
3847 // The `sig' array is to be updated. sig[j] represents the location
3848 // of the j-th argument, either a register or a stack slot.
3849
3850 // Comment taken from i486.ad:
3851 // Body of function which returns an integer array locating
3852 // arguments either in registers or in stack slots. Passed an array
3853 // of ideal registers called "sig" and a "length" count. Stack-slot
3854 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3855 // arguments for a CALLEE. Incoming stack arguments are
3856 // automatically biased by the preserve_stack_slots field above.
3857 calling_convention %{
3858 // No difference between ingoing/outgoing. Just pass false.
3859 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3860 %}
3861
3862 // Comment taken from i486.ad:
3863 // Body of function which returns an integer array locating
3864 // arguments either in registers or in stack slots. Passed an array
3865 // of ideal registers called "sig" and a "length" count. Stack-slot
3866 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3867 // arguments for a CALLEE. Incoming stack arguments are
3868 // automatically biased by the preserve_stack_slots field above.
3869 c_calling_convention %{
3870 // This is obviously always outgoing.
3871 // C argument in register AND stack slot.
3872 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3873 %}
3874
3875 // Location of native (C/C++) and interpreter return values. This
3876 // is specified to be the same as Java. In the 32-bit VM, long
3877 // values are actually returned from native calls in O0:O1 and
3878 // returned to the interpreter in I0:I1. The copying to and from
3879 // the register pairs is done by the appropriate call and epilog
3880 // opcodes. This simplifies the register allocator.
3881 c_return_value %{
3882 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3883 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3884 "only return normal values");
3885 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3886 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3887 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3888 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3889 %}
3890
3891 // Location of compiled Java return values. Same as C
3892 return_value %{
3893 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3894 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3895 "only return normal values");
3896 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3897 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3898 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3899 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3900 %}
3901 %}
3902
3903
3904 //----------ATTRIBUTES---------------------------------------------------------
3905
3906 //----------Operand Attributes-------------------------------------------------
3907 op_attrib op_cost(1); // Required cost attribute.
3908
3909 //----------Instruction Attributes---------------------------------------------
3910
3911 // Cost attribute. required.
3912 ins_attrib ins_cost(DEFAULT_COST);
3913
3914 // Is this instruction a non-matching short branch variant of some
3915 // long branch? Not required.
3916 ins_attrib ins_short_branch(0);
3917
3918 ins_attrib ins_is_TrapBasedCheckNode(true);
3919
3920 // Number of constants.
3921 // This instruction uses the given number of constants
3922 // (optional attribute).
3923 // This is needed to determine in time whether the constant pool will
3924 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3925 // is determined. It's also used to compute the constant pool size
3926 // in Output().
3927 ins_attrib ins_num_consts(0);
3928
3929 // Required alignment attribute (must be a power of 2) specifies the
3930 // alignment that some part of the instruction (not necessarily the
3931 // start) requires. If > 1, a compute_padding() function must be
3932 // provided for the instruction.
3933 ins_attrib ins_alignment(1);
3934
3935 // Enforce/prohibit rematerializations.
3936 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3937 // then rematerialization of that instruction is prohibited and the
3938 // instruction's value will be spilled if necessary.
3939 // Causes that MachNode::rematerialize() returns false.
3940 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3941 // then rematerialization should be enforced and a copy of the instruction
3942 // should be inserted if possible; rematerialization is not guaranteed.
3943 // Note: this may result in rematerializations in front of every use.
3944 // Causes that MachNode::rematerialize() can return true.
3945 // (optional attribute)
3946 ins_attrib ins_cannot_rematerialize(false);
3947 ins_attrib ins_should_rematerialize(false);
3948
3949 // Instruction has variable size depending on alignment.
3950 ins_attrib ins_variable_size_depending_on_alignment(false);
3951
3952 // Instruction is a nop.
3953 ins_attrib ins_is_nop(false);
3954
3955 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3956 ins_attrib ins_use_mach_if_fast_lock_node(false);
3957
3958 // Field for the toc offset of a constant.
3959 //
3960 // This is needed if the toc offset is not encodable as an immediate in
3961 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3962 // added to the toc, and from this a load with immediate is performed.
3963 // With postalloc expand, we get two nodes that require the same offset
3964 // but which don't know about each other. The offset is only known
3965 // when the constant is added to the constant pool during emitting.
3966 // It is generated in the 'hi'-node adding the upper bits, and saved
3967 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3968 // the offset from there when it gets encoded.
3969 ins_attrib ins_field_const_toc_offset(0);
3970 ins_attrib ins_field_const_toc_offset_hi_node(0);
3971
3972 // A field that can hold the instructions offset in the code buffer.
3973 // Set in the nodes emitter.
3974 ins_attrib ins_field_cbuf_insts_offset(-1);
3975
3976 // Fields for referencing a call's load-IC-node.
3977 // If the toc offset can not be encoded as an immediate in a load, we
3978 // use two nodes.
3979 ins_attrib ins_field_load_ic_hi_node(0);
3980 ins_attrib ins_field_load_ic_node(0);
3981
3982 //----------OPERANDS-----------------------------------------------------------
3983 // Operand definitions must precede instruction definitions for correct
3984 // parsing in the ADLC because operands constitute user defined types
3985 // which are used in instruction definitions.
3986 //
3987 // Formats are generated automatically for constants and base registers.
3988
3989 //----------Simple Operands----------------------------------------------------
3990 // Immediate Operands
3991
3992 // Integer Immediate: 32-bit
3993 operand immI() %{
3994 match(ConI);
3995 op_cost(40);
3996 format %{ %}
3997 interface(CONST_INTER);
3998 %}
3999
4000 operand immI8() %{
4001 predicate(Assembler::is_simm(n->get_int(), 8));
4002 op_cost(0);
4003 match(ConI);
4004 format %{ %}
4005 interface(CONST_INTER);
4006 %}
4007
4008 // Integer Immediate: 16-bit
4009 operand immI16() %{
4010 predicate(Assembler::is_simm(n->get_int(), 16));
4011 op_cost(0);
4012 match(ConI);
4013 format %{ %}
4014 interface(CONST_INTER);
4015 %}
4016
4017 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4018 operand immIhi16() %{
4019 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4020 match(ConI);
4021 op_cost(0);
4022 format %{ %}
4023 interface(CONST_INTER);
4024 %}
4025
4026 operand immInegpow2() %{
4027 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4028 match(ConI);
4029 op_cost(0);
4030 format %{ %}
4031 interface(CONST_INTER);
4032 %}
4033
4034 operand immIpow2minus1() %{
4035 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4036 match(ConI);
4037 op_cost(0);
4038 format %{ %}
4039 interface(CONST_INTER);
4040 %}
4041
4042 operand immIpowerOf2() %{
4043 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4044 match(ConI);
4045 op_cost(0);
4046 format %{ %}
4047 interface(CONST_INTER);
4048 %}
4049
4050 // Unsigned Integer Immediate: the values 0-31
4051 operand uimmI5() %{
4052 predicate(Assembler::is_uimm(n->get_int(), 5));
4053 match(ConI);
4054 op_cost(0);
4055 format %{ %}
4056 interface(CONST_INTER);
4057 %}
4058
4059 // Unsigned Integer Immediate: 6-bit
4060 operand uimmI6() %{
4061 predicate(Assembler::is_uimm(n->get_int(), 6));
4062 match(ConI);
4063 op_cost(0);
4064 format %{ %}
4065 interface(CONST_INTER);
4066 %}
4067
4068 // Unsigned Integer Immediate: 6-bit int, greater than 32
4069 operand uimmI6_ge32() %{
4070 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4071 match(ConI);
4072 op_cost(0);
4073 format %{ %}
4074 interface(CONST_INTER);
4075 %}
4076
4077 // Unsigned Integer Immediate: 15-bit
4078 operand uimmI15() %{
4079 predicate(Assembler::is_uimm(n->get_int(), 15));
4080 match(ConI);
4081 op_cost(0);
4082 format %{ %}
4083 interface(CONST_INTER);
4084 %}
4085
4086 // Unsigned Integer Immediate: 16-bit
4087 operand uimmI16() %{
4088 predicate(Assembler::is_uimm(n->get_int(), 16));
4089 match(ConI);
4090 op_cost(0);
4091 format %{ %}
4092 interface(CONST_INTER);
4093 %}
4094
4095 // constant 'int 0'.
4096 operand immI_0() %{
4097 predicate(n->get_int() == 0);
4098 match(ConI);
4099 op_cost(0);
4100 format %{ %}
4101 interface(CONST_INTER);
4102 %}
4103
4104 // constant 'int 1'.
4105 operand immI_1() %{
4106 predicate(n->get_int() == 1);
4107 match(ConI);
4108 op_cost(0);
4109 format %{ %}
4110 interface(CONST_INTER);
4111 %}
4112
4113 // constant 'int -1'.
4114 operand immI_minus1() %{
4115 predicate(n->get_int() == -1);
4116 match(ConI);
4117 op_cost(0);
4118 format %{ %}
4119 interface(CONST_INTER);
4120 %}
4121
4122 // int value 16.
4123 operand immI_16() %{
4124 predicate(n->get_int() == 16);
4125 match(ConI);
4126 op_cost(0);
4127 format %{ %}
4128 interface(CONST_INTER);
4129 %}
4130
4131 // int value 24.
4132 operand immI_24() %{
4133 predicate(n->get_int() == 24);
4134 match(ConI);
4135 op_cost(0);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4139
4140 // Compressed oops constants
4141 // Pointer Immediate
4142 operand immN() %{
4143 match(ConN);
4144
4145 op_cost(10);
4146 format %{ %}
4147 interface(CONST_INTER);
4148 %}
4149
4150 // NULL Pointer Immediate
4151 operand immN_0() %{
4152 predicate(n->get_narrowcon() == 0);
4153 match(ConN);
4154
4155 op_cost(0);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4159
4160 // Compressed klass constants
4161 operand immNKlass() %{
4162 match(ConNKlass);
4163
4164 op_cost(0);
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4168
4169 // This operand can be used to avoid matching of an instruct
4170 // with chain rule.
4171 operand immNKlass_NM() %{
4172 match(ConNKlass);
4173 predicate(false);
4174 op_cost(0);
4175 format %{ %}
4176 interface(CONST_INTER);
4177 %}
4178
4179 // Pointer Immediate: 64-bit
4180 operand immP() %{
4181 match(ConP);
4182 op_cost(0);
4183 format %{ %}
4184 interface(CONST_INTER);
4185 %}
4186
4187 // Operand to avoid match of loadConP.
4188 // This operand can be used to avoid matching of an instruct
4189 // with chain rule.
4190 operand immP_NM() %{
4191 match(ConP);
4192 predicate(false);
4193 op_cost(0);
4194 format %{ %}
4195 interface(CONST_INTER);
4196 %}
4197
4198 // costant 'pointer 0'.
4199 operand immP_0() %{
4200 predicate(n->get_ptr() == 0);
4201 match(ConP);
4202 op_cost(0);
4203 format %{ %}
4204 interface(CONST_INTER);
4205 %}
4206
4207 // pointer 0x0 or 0x1
4208 operand immP_0or1() %{
4209 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4210 match(ConP);
4211 op_cost(0);
4212 format %{ %}
4213 interface(CONST_INTER);
4214 %}
4215
4216 operand immL() %{
4217 match(ConL);
4218 op_cost(40);
4219 format %{ %}
4220 interface(CONST_INTER);
4221 %}
4222
4223 // Long Immediate: 16-bit
4224 operand immL16() %{
4225 predicate(Assembler::is_simm(n->get_long(), 16));
4226 match(ConL);
4227 op_cost(0);
4228 format %{ %}
4229 interface(CONST_INTER);
4230 %}
4231
4232 // Long Immediate: 16-bit, 4-aligned
4233 operand immL16Alg4() %{
4234 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4235 match(ConL);
4236 op_cost(0);
4237 format %{ %}
4238 interface(CONST_INTER);
4239 %}
4240
4241 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4242 operand immL32hi16() %{
4243 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4244 match(ConL);
4245 op_cost(0);
4246 format %{ %}
4247 interface(CONST_INTER);
4248 %}
4249
4250 // Long Immediate: 32-bit
4251 operand immL32() %{
4252 predicate(Assembler::is_simm(n->get_long(), 32));
4253 match(ConL);
4254 op_cost(0);
4255 format %{ %}
4256 interface(CONST_INTER);
4257 %}
4258
4259 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4260 operand immLhighest16() %{
4261 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4262 match(ConL);
4263 op_cost(0);
4264 format %{ %}
4265 interface(CONST_INTER);
4266 %}
4267
4268 operand immLnegpow2() %{
4269 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4270 match(ConL);
4271 op_cost(0);
4272 format %{ %}
4273 interface(CONST_INTER);
4274 %}
4275
4276 operand immLpow2minus1() %{
4277 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4278 (n->get_long() != (jlong)0xffffffffffffffffL));
4279 match(ConL);
4280 op_cost(0);
4281 format %{ %}
4282 interface(CONST_INTER);
4283 %}
4284
4285 // constant 'long 0'.
4286 operand immL_0() %{
4287 predicate(n->get_long() == 0L);
4288 match(ConL);
4289 op_cost(0);
4290 format %{ %}
4291 interface(CONST_INTER);
4292 %}
4293
4294 // constat ' long -1'.
4295 operand immL_minus1() %{
4296 predicate(n->get_long() == -1L);
4297 match(ConL);
4298 op_cost(0);
4299 format %{ %}
4300 interface(CONST_INTER);
4301 %}
4302
4303 // Long Immediate: low 32-bit mask
4304 operand immL_32bits() %{
4305 predicate(n->get_long() == 0xFFFFFFFFL);
4306 match(ConL);
4307 op_cost(0);
4308 format %{ %}
4309 interface(CONST_INTER);
4310 %}
4311
4312 // Unsigned Long Immediate: 16-bit
4313 operand uimmL16() %{
4314 predicate(Assembler::is_uimm(n->get_long(), 16));
4315 match(ConL);
4316 op_cost(0);
4317 format %{ %}
4318 interface(CONST_INTER);
4319 %}
4320
4321 // Float Immediate
4322 operand immF() %{
4323 match(ConF);
4324 op_cost(40);
4325 format %{ %}
4326 interface(CONST_INTER);
4327 %}
4328
4329 // Float Immediate: +0.0f.
4330 operand immF_0() %{
4331 predicate(jint_cast(n->getf()) == 0);
4332 match(ConF);
4333
4334 op_cost(0);
4335 format %{ %}
4336 interface(CONST_INTER);
4337 %}
4338
4339 // Double Immediate
4340 operand immD() %{
4341 match(ConD);
4342 op_cost(40);
4343 format %{ %}
4344 interface(CONST_INTER);
4345 %}
4346
4347 // Integer Register Operands
4348 // Integer Destination Register
4349 // See definition of reg_class bits32_reg_rw.
4350 operand iRegIdst() %{
4351 constraint(ALLOC_IN_RC(bits32_reg_rw));
4352 match(RegI);
4353 match(rscratch1RegI);
4354 match(rscratch2RegI);
4355 match(rarg1RegI);
4356 match(rarg2RegI);
4357 match(rarg3RegI);
4358 match(rarg4RegI);
4359 format %{ %}
4360 interface(REG_INTER);
4361 %}
4362
4363 // Integer Source Register
4364 // See definition of reg_class bits32_reg_ro.
4365 operand iRegIsrc() %{
4366 constraint(ALLOC_IN_RC(bits32_reg_ro));
4367 match(RegI);
4368 match(rscratch1RegI);
4369 match(rscratch2RegI);
4370 match(rarg1RegI);
4371 match(rarg2RegI);
4372 match(rarg3RegI);
4373 match(rarg4RegI);
4374 format %{ %}
4375 interface(REG_INTER);
4376 %}
4377
4378 operand rscratch1RegI() %{
4379 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4380 match(iRegIdst);
4381 format %{ %}
4382 interface(REG_INTER);
4383 %}
4384
4385 operand rscratch2RegI() %{
4386 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4387 match(iRegIdst);
4388 format %{ %}
4389 interface(REG_INTER);
4390 %}
4391
4392 operand rarg1RegI() %{
4393 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4394 match(iRegIdst);
4395 format %{ %}
4396 interface(REG_INTER);
4397 %}
4398
4399 operand rarg2RegI() %{
4400 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4401 match(iRegIdst);
4402 format %{ %}
4403 interface(REG_INTER);
4404 %}
4405
4406 operand rarg3RegI() %{
4407 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4408 match(iRegIdst);
4409 format %{ %}
4410 interface(REG_INTER);
4411 %}
4412
4413 operand rarg4RegI() %{
4414 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4415 match(iRegIdst);
4416 format %{ %}
4417 interface(REG_INTER);
4418 %}
4419
4420 operand rarg1RegL() %{
4421 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4422 match(iRegLdst);
4423 format %{ %}
4424 interface(REG_INTER);
4425 %}
4426
4427 operand rarg2RegL() %{
4428 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4429 match(iRegLdst);
4430 format %{ %}
4431 interface(REG_INTER);
4432 %}
4433
4434 operand rarg3RegL() %{
4435 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4436 match(iRegLdst);
4437 format %{ %}
4438 interface(REG_INTER);
4439 %}
4440
4441 operand rarg4RegL() %{
4442 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4443 match(iRegLdst);
4444 format %{ %}
4445 interface(REG_INTER);
4446 %}
4447
4448 // Pointer Destination Register
4449 // See definition of reg_class bits64_reg_rw.
4450 operand iRegPdst() %{
4451 constraint(ALLOC_IN_RC(bits64_reg_rw));
4452 match(RegP);
4453 match(rscratch1RegP);
4454 match(rscratch2RegP);
4455 match(rarg1RegP);
4456 match(rarg2RegP);
4457 match(rarg3RegP);
4458 match(rarg4RegP);
4459 format %{ %}
4460 interface(REG_INTER);
4461 %}
4462
4463 // Pointer Destination Register
4464 // Operand not using r11 and r12 (killed in epilog).
4465 operand iRegPdstNoScratch() %{
4466 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4467 match(RegP);
4468 match(rarg1RegP);
4469 match(rarg2RegP);
4470 match(rarg3RegP);
4471 match(rarg4RegP);
4472 format %{ %}
4473 interface(REG_INTER);
4474 %}
4475
4476 // Pointer Source Register
4477 // See definition of reg_class bits64_reg_ro.
4478 operand iRegPsrc() %{
4479 constraint(ALLOC_IN_RC(bits64_reg_ro));
4480 match(RegP);
4481 match(iRegPdst);
4482 match(rscratch1RegP);
4483 match(rscratch2RegP);
4484 match(rarg1RegP);
4485 match(rarg2RegP);
4486 match(rarg3RegP);
4487 match(rarg4RegP);
4488 match(threadRegP);
4489 format %{ %}
4490 interface(REG_INTER);
4491 %}
4492
4493 // Thread operand.
4494 operand threadRegP() %{
4495 constraint(ALLOC_IN_RC(thread_bits64_reg));
4496 match(iRegPdst);
4497 format %{ "R16" %}
4498 interface(REG_INTER);
4499 %}
4500
4501 operand rscratch1RegP() %{
4502 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4503 match(iRegPdst);
4504 format %{ "R11" %}
4505 interface(REG_INTER);
4506 %}
4507
4508 operand rscratch2RegP() %{
4509 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4510 match(iRegPdst);
4511 format %{ %}
4512 interface(REG_INTER);
4513 %}
4514
4515 operand rarg1RegP() %{
4516 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4517 match(iRegPdst);
4518 format %{ %}
4519 interface(REG_INTER);
4520 %}
4521
4522 operand rarg2RegP() %{
4523 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4524 match(iRegPdst);
4525 format %{ %}
4526 interface(REG_INTER);
4527 %}
4528
4529 operand rarg3RegP() %{
4530 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4531 match(iRegPdst);
4532 format %{ %}
4533 interface(REG_INTER);
4534 %}
4535
4536 operand rarg4RegP() %{
4537 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4538 match(iRegPdst);
4539 format %{ %}
4540 interface(REG_INTER);
4541 %}
4542
4543 operand iRegNsrc() %{
4544 constraint(ALLOC_IN_RC(bits32_reg_ro));
4545 match(RegN);
4546 match(iRegNdst);
4547
4548 format %{ %}
4549 interface(REG_INTER);
4550 %}
4551
4552 operand iRegNdst() %{
4553 constraint(ALLOC_IN_RC(bits32_reg_rw));
4554 match(RegN);
4555
4556 format %{ %}
4557 interface(REG_INTER);
4558 %}
4559
4560 // Long Destination Register
4561 // See definition of reg_class bits64_reg_rw.
4562 operand iRegLdst() %{
4563 constraint(ALLOC_IN_RC(bits64_reg_rw));
4564 match(RegL);
4565 match(rscratch1RegL);
4566 match(rscratch2RegL);
4567 format %{ %}
4568 interface(REG_INTER);
4569 %}
4570
4571 // Long Source Register
4572 // See definition of reg_class bits64_reg_ro.
4573 operand iRegLsrc() %{
4574 constraint(ALLOC_IN_RC(bits64_reg_ro));
4575 match(RegL);
4576 match(iRegLdst);
4577 match(rscratch1RegL);
4578 match(rscratch2RegL);
4579 format %{ %}
4580 interface(REG_INTER);
4581 %}
4582
4583 // Special operand for ConvL2I.
4584 operand iRegL2Isrc(iRegLsrc reg) %{
4585 constraint(ALLOC_IN_RC(bits64_reg_ro));
4586 match(ConvL2I reg);
4587 format %{ "ConvL2I($reg)" %}
4588 interface(REG_INTER)
4589 %}
4590
4591 operand rscratch1RegL() %{
4592 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4593 match(RegL);
4594 format %{ %}
4595 interface(REG_INTER);
4596 %}
4597
4598 operand rscratch2RegL() %{
4599 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4600 match(RegL);
4601 format %{ %}
4602 interface(REG_INTER);
4603 %}
4604
4605 // Condition Code Flag Registers
4606 operand flagsReg() %{
4607 constraint(ALLOC_IN_RC(int_flags));
4608 match(RegFlags);
4609 format %{ %}
4610 interface(REG_INTER);
4611 %}
4612
4613 operand flagsRegSrc() %{
4614 constraint(ALLOC_IN_RC(int_flags_ro));
4615 match(RegFlags);
4616 match(flagsReg);
4617 match(flagsRegCR0);
4618 format %{ %}
4619 interface(REG_INTER);
4620 %}
4621
4622 // Condition Code Flag Register CR0
4623 operand flagsRegCR0() %{
4624 constraint(ALLOC_IN_RC(int_flags_CR0));
4625 match(RegFlags);
4626 format %{ "CR0" %}
4627 interface(REG_INTER);
4628 %}
4629
4630 operand flagsRegCR1() %{
4631 constraint(ALLOC_IN_RC(int_flags_CR1));
4632 match(RegFlags);
4633 format %{ "CR1" %}
4634 interface(REG_INTER);
4635 %}
4636
4637 operand flagsRegCR6() %{
4638 constraint(ALLOC_IN_RC(int_flags_CR6));
4639 match(RegFlags);
4640 format %{ "CR6" %}
4641 interface(REG_INTER);
4642 %}
4643
4644 operand regCTR() %{
4645 constraint(ALLOC_IN_RC(ctr_reg));
4646 // RegFlags should work. Introducing a RegSpecial type would cause a
4647 // lot of changes.
4648 match(RegFlags);
4649 format %{"SR_CTR" %}
4650 interface(REG_INTER);
4651 %}
4652
4653 operand regD() %{
4654 constraint(ALLOC_IN_RC(dbl_reg));
4655 match(RegD);
4656 format %{ %}
4657 interface(REG_INTER);
4658 %}
4659
4660 operand regF() %{
4661 constraint(ALLOC_IN_RC(flt_reg));
4662 match(RegF);
4663 format %{ %}
4664 interface(REG_INTER);
4665 %}
4666
4667 // Special Registers
4668
4669 // Method Register
4670 operand inline_cache_regP(iRegPdst reg) %{
4671 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4672 match(reg);
4673 format %{ %}
4674 interface(REG_INTER);
4675 %}
4676
4677 operand compiler_method_oop_regP(iRegPdst reg) %{
4678 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4679 match(reg);
4680 format %{ %}
4681 interface(REG_INTER);
4682 %}
4683
4684 operand interpreter_method_oop_regP(iRegPdst reg) %{
4685 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4686 match(reg);
4687 format %{ %}
4688 interface(REG_INTER);
4689 %}
4690
4691 // Operands to remove register moves in unscaled mode.
4692 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4693 operand iRegP2N(iRegPsrc reg) %{
4694 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4695 constraint(ALLOC_IN_RC(bits64_reg_ro));
4696 match(EncodeP reg);
4697 format %{ "$reg" %}
4698 interface(REG_INTER)
4699 %}
4700
4701 operand iRegN2P(iRegNsrc reg) %{
4702 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4703 constraint(ALLOC_IN_RC(bits32_reg_ro));
4704 match(DecodeN reg);
4705 format %{ "$reg" %}
4706 interface(REG_INTER)
4707 %}
4708
4709 operand iRegN2P_klass(iRegNsrc reg) %{
4710 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4711 constraint(ALLOC_IN_RC(bits32_reg_ro));
4712 match(DecodeNKlass reg);
4713 format %{ "$reg" %}
4714 interface(REG_INTER)
4715 %}
4716
4717 //----------Complex Operands---------------------------------------------------
4718 // Indirect Memory Reference
4719 operand indirect(iRegPsrc reg) %{
4720 constraint(ALLOC_IN_RC(bits64_reg_ro));
4721 match(reg);
4722 op_cost(100);
4723 format %{ "[$reg]" %}
4724 interface(MEMORY_INTER) %{
4725 base($reg);
4726 index(0x0);
4727 scale(0x0);
4728 disp(0x0);
4729 %}
4730 %}
4731
4732 // Indirect with Offset
4733 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4734 constraint(ALLOC_IN_RC(bits64_reg_ro));
4735 match(AddP reg offset);
4736 op_cost(100);
4737 format %{ "[$reg + $offset]" %}
4738 interface(MEMORY_INTER) %{
4739 base($reg);
4740 index(0x0);
4741 scale(0x0);
4742 disp($offset);
4743 %}
4744 %}
4745
4746 // Indirect with 4-aligned Offset
4747 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4748 constraint(ALLOC_IN_RC(bits64_reg_ro));
4749 match(AddP reg offset);
4750 op_cost(100);
4751 format %{ "[$reg + $offset]" %}
4752 interface(MEMORY_INTER) %{
4753 base($reg);
4754 index(0x0);
4755 scale(0x0);
4756 disp($offset);
4757 %}
4758 %}
4759
4760 //----------Complex Operands for Compressed OOPs-------------------------------
4761 // Compressed OOPs with narrow_oop_shift == 0.
4762
4763 // Indirect Memory Reference, compressed OOP
4764 operand indirectNarrow(iRegNsrc reg) %{
4765 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4766 constraint(ALLOC_IN_RC(bits64_reg_ro));
4767 match(DecodeN reg);
4768 op_cost(100);
4769 format %{ "[$reg]" %}
4770 interface(MEMORY_INTER) %{
4771 base($reg);
4772 index(0x0);
4773 scale(0x0);
4774 disp(0x0);
4775 %}
4776 %}
4777
4778 operand indirectNarrow_klass(iRegNsrc reg) %{
4779 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4780 constraint(ALLOC_IN_RC(bits64_reg_ro));
4781 match(DecodeNKlass reg);
4782 op_cost(100);
4783 format %{ "[$reg]" %}
4784 interface(MEMORY_INTER) %{
4785 base($reg);
4786 index(0x0);
4787 scale(0x0);
4788 disp(0x0);
4789 %}
4790 %}
4791
4792 // Indirect with Offset, compressed OOP
4793 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4794 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4795 constraint(ALLOC_IN_RC(bits64_reg_ro));
4796 match(AddP (DecodeN reg) offset);
4797 op_cost(100);
4798 format %{ "[$reg + $offset]" %}
4799 interface(MEMORY_INTER) %{
4800 base($reg);
4801 index(0x0);
4802 scale(0x0);
4803 disp($offset);
4804 %}
4805 %}
4806
4807 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4808 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4809 constraint(ALLOC_IN_RC(bits64_reg_ro));
4810 match(AddP (DecodeNKlass reg) offset);
4811 op_cost(100);
4812 format %{ "[$reg + $offset]" %}
4813 interface(MEMORY_INTER) %{
4814 base($reg);
4815 index(0x0);
4816 scale(0x0);
4817 disp($offset);
4818 %}
4819 %}
4820
4821 // Indirect with 4-aligned Offset, compressed OOP
4822 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4823 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4824 constraint(ALLOC_IN_RC(bits64_reg_ro));
4825 match(AddP (DecodeN reg) offset);
4826 op_cost(100);
4827 format %{ "[$reg + $offset]" %}
4828 interface(MEMORY_INTER) %{
4829 base($reg);
4830 index(0x0);
4831 scale(0x0);
4832 disp($offset);
4833 %}
4834 %}
4835
4836 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4837 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4838 constraint(ALLOC_IN_RC(bits64_reg_ro));
4839 match(AddP (DecodeNKlass reg) offset);
4840 op_cost(100);
4841 format %{ "[$reg + $offset]" %}
4842 interface(MEMORY_INTER) %{
4843 base($reg);
4844 index(0x0);
4845 scale(0x0);
4846 disp($offset);
4847 %}
4848 %}
4849
4850 //----------Special Memory Operands--------------------------------------------
4851 // Stack Slot Operand
4852 //
4853 // This operand is used for loading and storing temporary values on
4854 // the stack where a match requires a value to flow through memory.
4855 operand stackSlotI(sRegI reg) %{
4856 constraint(ALLOC_IN_RC(stack_slots));
4857 op_cost(100);
4858 //match(RegI);
4859 format %{ "[sp+$reg]" %}
4860 interface(MEMORY_INTER) %{
4861 base(0x1); // R1_SP
4862 index(0x0);
4863 scale(0x0);
4864 disp($reg); // Stack Offset
4865 %}
4866 %}
4867
4868 operand stackSlotL(sRegL reg) %{
4869 constraint(ALLOC_IN_RC(stack_slots));
4870 op_cost(100);
4871 //match(RegL);
4872 format %{ "[sp+$reg]" %}
4873 interface(MEMORY_INTER) %{
4874 base(0x1); // R1_SP
4875 index(0x0);
4876 scale(0x0);
4877 disp($reg); // Stack Offset
4878 %}
4879 %}
4880
4881 operand stackSlotP(sRegP reg) %{
4882 constraint(ALLOC_IN_RC(stack_slots));
4883 op_cost(100);
4884 //match(RegP);
4885 format %{ "[sp+$reg]" %}
4886 interface(MEMORY_INTER) %{
4887 base(0x1); // R1_SP
4888 index(0x0);
4889 scale(0x0);
4890 disp($reg); // Stack Offset
4891 %}
4892 %}
4893
4894 operand stackSlotF(sRegF reg) %{
4895 constraint(ALLOC_IN_RC(stack_slots));
4896 op_cost(100);
4897 //match(RegF);
4898 format %{ "[sp+$reg]" %}
4899 interface(MEMORY_INTER) %{
4900 base(0x1); // R1_SP
4901 index(0x0);
4902 scale(0x0);
4903 disp($reg); // Stack Offset
4904 %}
4905 %}
4906
4907 operand stackSlotD(sRegD reg) %{
4908 constraint(ALLOC_IN_RC(stack_slots));
4909 op_cost(100);
4910 //match(RegD);
4911 format %{ "[sp+$reg]" %}
4912 interface(MEMORY_INTER) %{
4913 base(0x1); // R1_SP
4914 index(0x0);
4915 scale(0x0);
4916 disp($reg); // Stack Offset
4917 %}
4918 %}
4919
4920 // Operands for expressing Control Flow
4921 // NOTE: Label is a predefined operand which should not be redefined in
4922 // the AD file. It is generically handled within the ADLC.
4923
4924 //----------Conditional Branch Operands----------------------------------------
4925 // Comparison Op
4926 //
4927 // This is the operation of the comparison, and is limited to the
4928 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4929 // (!=).
4930 //
4931 // Other attributes of the comparison, such as unsignedness, are specified
4932 // by the comparison instruction that sets a condition code flags register.
4933 // That result is represented by a flags operand whose subtype is appropriate
4934 // to the unsignedness (etc.) of the comparison.
4935 //
4936 // Later, the instruction which matches both the Comparison Op (a Bool) and
4937 // the flags (produced by the Cmp) specifies the coding of the comparison op
4938 // by matching a specific subtype of Bool operand below.
4939
4940 // When used for floating point comparisons: unordered same as less.
4941 operand cmpOp() %{
4942 match(Bool);
4943 format %{ "" %}
4944 interface(COND_INTER) %{
4945 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4946 // BO & BI
4947 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4948 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4949 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4950 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4951 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4952 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4953 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4954 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4955 %}
4956 %}
4957
4958 //----------OPERAND CLASSES----------------------------------------------------
4959 // Operand Classes are groups of operands that are used to simplify
4960 // instruction definitions by not requiring the AD writer to specify
4961 // seperate instructions for every form of operand when the
4962 // instruction accepts multiple operand types with the same basic
4963 // encoding and format. The classic case of this is memory operands.
4964 // Indirect is not included since its use is limited to Compare & Swap.
4965
4966 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4967 // Memory operand where offsets are 4-aligned. Required for ld, std.
4968 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4969 opclass indirectMemory(indirect, indirectNarrow);
4970
4971 // Special opclass for I and ConvL2I.
4972 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4973
4974 // Operand classes to match encode and decode. iRegN_P2N is only used
4975 // for storeN. I have never seen an encode node elsewhere.
4976 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4977 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4978
4979 //----------PIPELINE-----------------------------------------------------------
4980
4981 pipeline %{
4982
4983 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4984 // J. Res. & Dev., No. 1, Jan. 2002.
4985
4986 //----------ATTRIBUTES---------------------------------------------------------
4987 attributes %{
4988
4989 // Power4 instructions are of fixed length.
4990 fixed_size_instructions;
4991
4992 // TODO: if `bundle' means number of instructions fetched
4993 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4994 // max instructions issued per cycle, this is 5.
4995 max_instructions_per_bundle = 8;
4996
4997 // A Power4 instruction is 4 bytes long.
4998 instruction_unit_size = 4;
4999
5000 // The Power4 processor fetches 64 bytes...
5001 instruction_fetch_unit_size = 64;
5002
5003 // ...in one line
5004 instruction_fetch_units = 1
5005
5006 // Unused, list one so that array generated by adlc is not empty.
5007 // Aix compiler chokes if _nop_count = 0.
5008 nops(fxNop);
5009 %}
5010
5011 //----------RESOURCES----------------------------------------------------------
5012 // Resources are the functional units available to the machine
5013 resources(
5014 PPC_BR, // branch unit
5015 PPC_CR, // condition unit
5016 PPC_FX1, // integer arithmetic unit 1
5017 PPC_FX2, // integer arithmetic unit 2
5018 PPC_LDST1, // load/store unit 1
5019 PPC_LDST2, // load/store unit 2
5020 PPC_FP1, // float arithmetic unit 1
5021 PPC_FP2, // float arithmetic unit 2
5022 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5023 PPC_FX = PPC_FX1 | PPC_FX2,
5024 PPC_FP = PPC_FP1 | PPC_FP2
5025 );
5026
5027 //----------PIPELINE DESCRIPTION-----------------------------------------------
5028 // Pipeline Description specifies the stages in the machine's pipeline
5029 pipe_desc(
5030 // Power4 longest pipeline path
5031 PPC_IF, // instruction fetch
5032 PPC_IC,
5033 //PPC_BP, // branch prediction
5034 PPC_D0, // decode
5035 PPC_D1, // decode
5036 PPC_D2, // decode
5037 PPC_D3, // decode
5038 PPC_Xfer1,
5039 PPC_GD, // group definition
5040 PPC_MP, // map
5041 PPC_ISS, // issue
5042 PPC_RF, // resource fetch
5043 PPC_EX1, // execute (all units)
5044 PPC_EX2, // execute (FP, LDST)
5045 PPC_EX3, // execute (FP, LDST)
5046 PPC_EX4, // execute (FP)
5047 PPC_EX5, // execute (FP)
5048 PPC_EX6, // execute (FP)
5049 PPC_WB, // write back
5050 PPC_Xfer2,
5051 PPC_CP
5052 );
5053
5054 //----------PIPELINE CLASSES---------------------------------------------------
5055 // Pipeline Classes describe the stages in which input and output are
5056 // referenced by the hardware pipeline.
5057
5058 // Simple pipeline classes.
5059
5060 // Default pipeline class.
5061 pipe_class pipe_class_default() %{
5062 single_instruction;
5063 fixed_latency(2);
5064 %}
5065
5066 // Pipeline class for empty instructions.
5067 pipe_class pipe_class_empty() %{
5068 single_instruction;
5069 fixed_latency(0);
5070 %}
5071
5072 // Pipeline class for compares.
5073 pipe_class pipe_class_compare() %{
5074 single_instruction;
5075 fixed_latency(16);
5076 %}
5077
5078 // Pipeline class for traps.
5079 pipe_class pipe_class_trap() %{
5080 single_instruction;
5081 fixed_latency(100);
5082 %}
5083
5084 // Pipeline class for memory operations.
5085 pipe_class pipe_class_memory() %{
5086 single_instruction;
5087 fixed_latency(16);
5088 %}
5089
5090 // Pipeline class for call.
5091 pipe_class pipe_class_call() %{
5092 single_instruction;
5093 fixed_latency(100);
5094 %}
5095
5096 // Define the class for the Nop node.
5097 define %{
5098 MachNop = pipe_class_default;
5099 %}
5100
5101 %}
5102
5103 //----------INSTRUCTIONS-------------------------------------------------------
5104
5105 // Naming of instructions:
5106 // opA_operB / opA_operB_operC:
5107 // Operation 'op' with one or two source operands 'oper'. Result
5108 // type is A, source operand types are B and C.
5109 // Iff A == B == C, B and C are left out.
5110 //
5111 // The instructions are ordered according to the following scheme:
5112 // - loads
5113 // - load constants
5114 // - prefetch
5115 // - store
5116 // - encode/decode
5117 // - membar
5118 // - conditional moves
5119 // - compare & swap
5120 // - arithmetic and logic operations
5121 // * int: Add, Sub, Mul, Div, Mod
5122 // * int: lShift, arShift, urShift, rot
5123 // * float: Add, Sub, Mul, Div
5124 // * and, or, xor ...
5125 // - register moves: float <-> int, reg <-> stack, repl
5126 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5127 // - conv (low level type cast requiring bit changes (sign extend etc)
5128 // - compares, range & zero checks.
5129 // - branches
5130 // - complex operations, intrinsics, min, max, replicate
5131 // - lock
5132 // - Calls
5133 //
5134 // If there are similar instructions with different types they are sorted:
5135 // int before float
5136 // small before big
5137 // signed before unsigned
5138 // e.g., loadS before loadUS before loadI before loadF.
5139
5140
5141 //----------Load/Store Instructions--------------------------------------------
5142
5143 //----------Load Instructions--------------------------------------------------
5144
5145 // Converts byte to int.
5146 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5147 // reuses the 'amount' operand, but adlc expects that operand specification
5148 // and operands in match rule are equivalent.
5149 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5150 effect(DEF dst, USE src);
5151 format %{ "EXTSB $dst, $src \t// byte->int" %}
5152 size(4);
5153 ins_encode %{
5154 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5155 __ extsb($dst$$Register, $src$$Register);
5156 %}
5157 ins_pipe(pipe_class_default);
5158 %}
5159
5160 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5161 // match-rule, false predicate
5162 match(Set dst (LoadB mem));
5163 predicate(false);
5164
5165 format %{ "LBZ $dst, $mem" %}
5166 size(4);
5167 ins_encode( enc_lbz(dst, mem) );
5168 ins_pipe(pipe_class_memory);
5169 %}
5170
5171 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5172 // match-rule, false predicate
5173 match(Set dst (LoadB mem));
5174 predicate(false);
5175
5176 format %{ "LBZ $dst, $mem\n\t"
5177 "TWI $dst\n\t"
5178 "ISYNC" %}
5179 size(12);
5180 ins_encode( enc_lbz_ac(dst, mem) );
5181 ins_pipe(pipe_class_memory);
5182 %}
5183
5184 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5185 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5186 match(Set dst (LoadB mem));
5187 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5188 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5189 expand %{
5190 iRegIdst tmp;
5191 loadUB_indirect(tmp, mem);
5192 convB2I_reg_2(dst, tmp);
5193 %}
5194 %}
5195
5196 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5197 match(Set dst (LoadB mem));
5198 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5199 expand %{
5200 iRegIdst tmp;
5201 loadUB_indirect_ac(tmp, mem);
5202 convB2I_reg_2(dst, tmp);
5203 %}
5204 %}
5205
5206 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5207 // match-rule, false predicate
5208 match(Set dst (LoadB mem));
5209 predicate(false);
5210
5211 format %{ "LBZ $dst, $mem" %}
5212 size(4);
5213 ins_encode( enc_lbz(dst, mem) );
5214 ins_pipe(pipe_class_memory);
5215 %}
5216
5217 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5218 // match-rule, false predicate
5219 match(Set dst (LoadB mem));
5220 predicate(false);
5221
5222 format %{ "LBZ $dst, $mem\n\t"
5223 "TWI $dst\n\t"
5224 "ISYNC" %}
5225 size(12);
5226 ins_encode( enc_lbz_ac(dst, mem) );
5227 ins_pipe(pipe_class_memory);
5228 %}
5229
5230 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5231 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5232 match(Set dst (LoadB mem));
5233 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5234 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5235
5236 expand %{
5237 iRegIdst tmp;
5238 loadUB_indOffset16(tmp, mem);
5239 convB2I_reg_2(dst, tmp);
5240 %}
5241 %}
5242
5243 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5244 match(Set dst (LoadB mem));
5245 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5246
5247 expand %{
5248 iRegIdst tmp;
5249 loadUB_indOffset16_ac(tmp, mem);
5250 convB2I_reg_2(dst, tmp);
5251 %}
5252 %}
5253
5254 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5255 instruct loadUB(iRegIdst dst, memory mem) %{
5256 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5257 match(Set dst (LoadUB mem));
5258 ins_cost(MEMORY_REF_COST);
5259
5260 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5261 size(4);
5262 ins_encode( enc_lbz(dst, mem) );
5263 ins_pipe(pipe_class_memory);
5264 %}
5265
5266 // Load Unsigned Byte (8bit UNsigned) acquire.
5267 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5268 match(Set dst (LoadUB mem));
5269 ins_cost(3*MEMORY_REF_COST);
5270
5271 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5272 "TWI $dst\n\t"
5273 "ISYNC" %}
5274 size(12);
5275 ins_encode( enc_lbz_ac(dst, mem) );
5276 ins_pipe(pipe_class_memory);
5277 %}
5278
5279 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5280 instruct loadUB2L(iRegLdst dst, memory mem) %{
5281 match(Set dst (ConvI2L (LoadUB mem)));
5282 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5283 ins_cost(MEMORY_REF_COST);
5284
5285 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5286 size(4);
5287 ins_encode( enc_lbz(dst, mem) );
5288 ins_pipe(pipe_class_memory);
5289 %}
5290
5291 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5292 match(Set dst (ConvI2L (LoadUB mem)));
5293 ins_cost(3*MEMORY_REF_COST);
5294
5295 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5296 "TWI $dst\n\t"
5297 "ISYNC" %}
5298 size(12);
5299 ins_encode( enc_lbz_ac(dst, mem) );
5300 ins_pipe(pipe_class_memory);
5301 %}
5302
5303 // Load Short (16bit signed)
5304 instruct loadS(iRegIdst dst, memory mem) %{
5305 match(Set dst (LoadS mem));
5306 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5307 ins_cost(MEMORY_REF_COST);
5308
5309 format %{ "LHA $dst, $mem" %}
5310 size(4);
5311 ins_encode %{
5312 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5313 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5314 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5315 %}
5316 ins_pipe(pipe_class_memory);
5317 %}
5318
5319 // Load Short (16bit signed) acquire.
5320 instruct loadS_ac(iRegIdst dst, memory mem) %{
5321 match(Set dst (LoadS mem));
5322 ins_cost(3*MEMORY_REF_COST);
5323
5324 format %{ "LHA $dst, $mem\t acquire\n\t"
5325 "TWI $dst\n\t"
5326 "ISYNC" %}
5327 size(12);
5328 ins_encode %{
5329 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5330 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5331 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5332 __ twi_0($dst$$Register);
5333 __ isync();
5334 %}
5335 ins_pipe(pipe_class_memory);
5336 %}
5337
5338 // Load Char (16bit unsigned)
5339 instruct loadUS(iRegIdst dst, memory mem) %{
5340 match(Set dst (LoadUS mem));
5341 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5342 ins_cost(MEMORY_REF_COST);
5343
5344 format %{ "LHZ $dst, $mem" %}
5345 size(4);
5346 ins_encode( enc_lhz(dst, mem) );
5347 ins_pipe(pipe_class_memory);
5348 %}
5349
5350 // Load Char (16bit unsigned) acquire.
5351 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5352 match(Set dst (LoadUS mem));
5353 ins_cost(3*MEMORY_REF_COST);
5354
5355 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5356 "TWI $dst\n\t"
5357 "ISYNC" %}
5358 size(12);
5359 ins_encode( enc_lhz_ac(dst, mem) );
5360 ins_pipe(pipe_class_memory);
5361 %}
5362
5363 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5364 instruct loadUS2L(iRegLdst dst, memory mem) %{
5365 match(Set dst (ConvI2L (LoadUS mem)));
5366 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5367 ins_cost(MEMORY_REF_COST);
5368
5369 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5370 size(4);
5371 ins_encode( enc_lhz(dst, mem) );
5372 ins_pipe(pipe_class_memory);
5373 %}
5374
5375 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5376 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5377 match(Set dst (ConvI2L (LoadUS mem)));
5378 ins_cost(3*MEMORY_REF_COST);
5379
5380 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5381 "TWI $dst\n\t"
5382 "ISYNC" %}
5383 size(12);
5384 ins_encode( enc_lhz_ac(dst, mem) );
5385 ins_pipe(pipe_class_memory);
5386 %}
5387
5388 // Load Integer.
5389 instruct loadI(iRegIdst dst, memory mem) %{
5390 match(Set dst (LoadI mem));
5391 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5392 ins_cost(MEMORY_REF_COST);
5393
5394 format %{ "LWZ $dst, $mem" %}
5395 size(4);
5396 ins_encode( enc_lwz(dst, mem) );
5397 ins_pipe(pipe_class_memory);
5398 %}
5399
5400 // Load Integer acquire.
5401 instruct loadI_ac(iRegIdst dst, memory mem) %{
5402 match(Set dst (LoadI mem));
5403 ins_cost(3*MEMORY_REF_COST);
5404
5405 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5406 "TWI $dst\n\t"
5407 "ISYNC" %}
5408 size(12);
5409 ins_encode( enc_lwz_ac(dst, mem) );
5410 ins_pipe(pipe_class_memory);
5411 %}
5412
5413 // Match loading integer and casting it to unsigned int in
5414 // long register.
5415 // LoadI + ConvI2L + AndL 0xffffffff.
5416 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5417 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5418 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5419 ins_cost(MEMORY_REF_COST);
5420
5421 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5422 size(4);
5423 ins_encode( enc_lwz(dst, mem) );
5424 ins_pipe(pipe_class_memory);
5425 %}
5426
5427 // Match loading integer and casting it to long.
5428 instruct loadI2L(iRegLdst dst, memory mem) %{
5429 match(Set dst (ConvI2L (LoadI mem)));
5430 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5431 ins_cost(MEMORY_REF_COST);
5432
5433 format %{ "LWA $dst, $mem \t// loadI2L" %}
5434 size(4);
5435 ins_encode %{
5436 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5437 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5438 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5439 %}
5440 ins_pipe(pipe_class_memory);
5441 %}
5442
5443 // Match loading integer and casting it to long - acquire.
5444 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5445 match(Set dst (ConvI2L (LoadI mem)));
5446 ins_cost(3*MEMORY_REF_COST);
5447
5448 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5449 "TWI $dst\n\t"
5450 "ISYNC" %}
5451 size(12);
5452 ins_encode %{
5453 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5454 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5455 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5456 __ twi_0($dst$$Register);
5457 __ isync();
5458 %}
5459 ins_pipe(pipe_class_memory);
5460 %}
5461
5462 // Load Long - aligned
5463 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5464 match(Set dst (LoadL mem));
5465 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5466 ins_cost(MEMORY_REF_COST);
5467
5468 format %{ "LD $dst, $mem \t// long" %}
5469 size(4);
5470 ins_encode( enc_ld(dst, mem) );
5471 ins_pipe(pipe_class_memory);
5472 %}
5473
5474 // Load Long - aligned acquire.
5475 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5476 match(Set dst (LoadL mem));
5477 ins_cost(3*MEMORY_REF_COST);
5478
5479 format %{ "LD $dst, $mem \t// long acquire\n\t"
5480 "TWI $dst\n\t"
5481 "ISYNC" %}
5482 size(12);
5483 ins_encode( enc_ld_ac(dst, mem) );
5484 ins_pipe(pipe_class_memory);
5485 %}
5486
5487 // Load Long - UNaligned
5488 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5489 match(Set dst (LoadL_unaligned mem));
5490 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5491 ins_cost(MEMORY_REF_COST);
5492
5493 format %{ "LD $dst, $mem \t// unaligned long" %}
5494 size(4);
5495 ins_encode( enc_ld(dst, mem) );
5496 ins_pipe(pipe_class_memory);
5497 %}
5498
5499 // Load nodes for superwords
5500
5501 // Load Aligned Packed Byte
5502 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5503 predicate(n->as_LoadVector()->memory_size() == 8);
5504 match(Set dst (LoadVector mem));
5505 ins_cost(MEMORY_REF_COST);
5506
5507 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5508 size(4);
5509 ins_encode( enc_ld(dst, mem) );
5510 ins_pipe(pipe_class_memory);
5511 %}
5512
5513 // Load Range, range = array length (=jint)
5514 instruct loadRange(iRegIdst dst, memory mem) %{
5515 match(Set dst (LoadRange mem));
5516 ins_cost(MEMORY_REF_COST);
5517
5518 format %{ "LWZ $dst, $mem \t// range" %}
5519 size(4);
5520 ins_encode( enc_lwz(dst, mem) );
5521 ins_pipe(pipe_class_memory);
5522 %}
5523
5524 // Load Compressed Pointer
5525 instruct loadN(iRegNdst dst, memory mem) %{
5526 match(Set dst (LoadN mem));
5527 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5528 ins_cost(MEMORY_REF_COST);
5529
5530 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5531 size(4);
5532 ins_encode( enc_lwz(dst, mem) );
5533 ins_pipe(pipe_class_memory);
5534 %}
5535
5536 // Load Compressed Pointer acquire.
5537 instruct loadN_ac(iRegNdst dst, memory mem) %{
5538 match(Set dst (LoadN mem));
5539 ins_cost(3*MEMORY_REF_COST);
5540
5541 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5542 "TWI $dst\n\t"
5543 "ISYNC" %}
5544 size(12);
5545 ins_encode( enc_lwz_ac(dst, mem) );
5546 ins_pipe(pipe_class_memory);
5547 %}
5548
5549 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5550 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5551 match(Set dst (DecodeN (LoadN mem)));
5552 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5553 ins_cost(MEMORY_REF_COST);
5554
5555 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5556 size(4);
5557 ins_encode( enc_lwz(dst, mem) );
5558 ins_pipe(pipe_class_memory);
5559 %}
5560
5561 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5562 match(Set dst (DecodeNKlass (LoadNKlass mem)));
5563 // SAPJVM GL 2014-05-21 Differs.
5564 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5565 _kids[0]->_leaf->as_Load()->is_unordered());
5566 ins_cost(MEMORY_REF_COST);
5567
5568 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5569 size(4);
5570 ins_encode( enc_lwz(dst, mem) );
5571 ins_pipe(pipe_class_memory);
5572 %}
5573
5574 // Load Pointer
5575 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5576 match(Set dst (LoadP mem));
5577 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5578 ins_cost(MEMORY_REF_COST);
5579
5580 format %{ "LD $dst, $mem \t// ptr" %}
5581 size(4);
5582 ins_encode( enc_ld(dst, mem) );
5583 ins_pipe(pipe_class_memory);
5584 %}
5585
5586 // Load Pointer acquire.
5587 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5588 match(Set dst (LoadP mem));
5589 ins_cost(3*MEMORY_REF_COST);
5590
5591 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5592 "TWI $dst\n\t"
5593 "ISYNC" %}
5594 size(12);
5595 ins_encode( enc_ld_ac(dst, mem) );
5596 ins_pipe(pipe_class_memory);
5597 %}
5598
5599 // LoadP + CastP2L
5600 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5601 match(Set dst (CastP2X (LoadP mem)));
5602 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5603 ins_cost(MEMORY_REF_COST);
5604
5605 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5606 size(4);
5607 ins_encode( enc_ld(dst, mem) );
5608 ins_pipe(pipe_class_memory);
5609 %}
5610
5611 // Load compressed klass pointer.
5612 instruct loadNKlass(iRegNdst dst, memory mem) %{
5613 match(Set dst (LoadNKlass mem));
5614 ins_cost(MEMORY_REF_COST);
5615
5616 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5617 size(4);
5618 ins_encode( enc_lwz(dst, mem) );
5619 ins_pipe(pipe_class_memory);
5620 %}
5621
5622 // Load Klass Pointer
5623 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5624 match(Set dst (LoadKlass mem));
5625 ins_cost(MEMORY_REF_COST);
5626
5627 format %{ "LD $dst, $mem \t// klass ptr" %}
5628 size(4);
5629 ins_encode( enc_ld(dst, mem) );
5630 ins_pipe(pipe_class_memory);
5631 %}
5632
5633 // Load Float
5634 instruct loadF(regF dst, memory mem) %{
5635 match(Set dst (LoadF mem));
5636 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5637 ins_cost(MEMORY_REF_COST);
5638
5639 format %{ "LFS $dst, $mem" %}
5640 size(4);
5641 ins_encode %{
5642 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5643 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5644 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5645 %}
5646 ins_pipe(pipe_class_memory);
5647 %}
5648
5649 // Load Float acquire.
5650 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5651 match(Set dst (LoadF mem));
5652 effect(TEMP cr0);
5653 ins_cost(3*MEMORY_REF_COST);
5654
5655 format %{ "LFS $dst, $mem \t// acquire\n\t"
5656 "FCMPU cr0, $dst, $dst\n\t"
5657 "BNE cr0, next\n"
5658 "next:\n\t"
5659 "ISYNC" %}
5660 size(16);
5661 ins_encode %{
5662 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5663 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5664 Label next;
5665 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5666 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5667 __ bne(CCR0, next);
5668 __ bind(next);
5669 __ isync();
5670 %}
5671 ins_pipe(pipe_class_memory);
5672 %}
5673
5674 // Load Double - aligned
5675 instruct loadD(regD dst, memory mem) %{
5676 match(Set dst (LoadD mem));
5677 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5678 ins_cost(MEMORY_REF_COST);
5679
5680 format %{ "LFD $dst, $mem" %}
5681 size(4);
5682 ins_encode( enc_lfd(dst, mem) );
5683 ins_pipe(pipe_class_memory);
5684 %}
5685
5686 // Load Double - aligned acquire.
5687 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5688 match(Set dst (LoadD mem));
5689 effect(TEMP cr0);
5690 ins_cost(3*MEMORY_REF_COST);
5691
5692 format %{ "LFD $dst, $mem \t// acquire\n\t"
5693 "FCMPU cr0, $dst, $dst\n\t"
5694 "BNE cr0, next\n"
5695 "next:\n\t"
5696 "ISYNC" %}
5697 size(16);
5698 ins_encode %{
5699 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5700 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5701 Label next;
5702 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5703 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5704 __ bne(CCR0, next);
5705 __ bind(next);
5706 __ isync();
5707 %}
5708 ins_pipe(pipe_class_memory);
5709 %}
5710
5711 // Load Double - UNaligned
5712 instruct loadD_unaligned(regD dst, memory mem) %{
5713 match(Set dst (LoadD_unaligned mem));
5714 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5715 ins_cost(MEMORY_REF_COST);
5716
5717 format %{ "LFD $dst, $mem" %}
5718 size(4);
5719 ins_encode( enc_lfd(dst, mem) );
5720 ins_pipe(pipe_class_memory);
5721 %}
5722
5723 //----------Constants--------------------------------------------------------
5724
5725 // Load MachConstantTableBase: add hi offset to global toc.
5726 // TODO: Handle hidden register r29 in bundler!
5727 instruct loadToc_hi(iRegLdst dst) %{
5728 effect(DEF dst);
5729 ins_cost(DEFAULT_COST);
5730
5731 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5732 size(4);
5733 ins_encode %{
5734 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5735 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5736 %}
5737 ins_pipe(pipe_class_default);
5738 %}
5739
5740 // Load MachConstantTableBase: add lo offset to global toc.
5741 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5742 effect(DEF dst, USE src);
5743 ins_cost(DEFAULT_COST);
5744
5745 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5746 size(4);
5747 ins_encode %{
5748 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5749 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5750 %}
5751 ins_pipe(pipe_class_default);
5752 %}
5753
5754 // Load 16-bit integer constant 0xssss????
5755 instruct loadConI16(iRegIdst dst, immI16 src) %{
5756 match(Set dst src);
5757
5758 format %{ "LI $dst, $src" %}
5759 size(4);
5760 ins_encode %{
5761 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5762 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5763 %}
5764 ins_pipe(pipe_class_default);
5765 %}
5766
5767 // Load integer constant 0x????0000
5768 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5769 match(Set dst src);
5770 ins_cost(DEFAULT_COST);
5771
5772 format %{ "LIS $dst, $src.hi" %}
5773 size(4);
5774 ins_encode %{
5775 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5776 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5777 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5778 %}
5779 ins_pipe(pipe_class_default);
5780 %}
5781
5782 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5783 // and sign extended), this adds the low 16 bits.
5784 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5785 // no match-rule, false predicate
5786 effect(DEF dst, USE src1, USE src2);
5787 predicate(false);
5788
5789 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5790 size(4);
5791 ins_encode %{
5792 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5793 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5794 %}
5795 ins_pipe(pipe_class_default);
5796 %}
5797
5798 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5799 match(Set dst src);
5800 ins_cost(DEFAULT_COST*2);
5801
5802 expand %{
5803 // Would like to use $src$$constant.
5804 immI16 srcLo %{ _opnds[1]->constant() %}
5805 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5806 immIhi16 srcHi %{ _opnds[1]->constant() %}
5807 iRegIdst tmpI;
5808 loadConIhi16(tmpI, srcHi);
5809 loadConI32_lo16(dst, tmpI, srcLo);
5810 %}
5811 %}
5812
5813 // No constant pool entries required.
5814 instruct loadConL16(iRegLdst dst, immL16 src) %{
5815 match(Set dst src);
5816
5817 format %{ "LI $dst, $src \t// long" %}
5818 size(4);
5819 ins_encode %{
5820 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5821 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5822 %}
5823 ins_pipe(pipe_class_default);
5824 %}
5825
5826 // Load long constant 0xssssssss????0000
5827 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5828 match(Set dst src);
5829 ins_cost(DEFAULT_COST);
5830
5831 format %{ "LIS $dst, $src.hi \t// long" %}
5832 size(4);
5833 ins_encode %{
5834 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5835 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5836 %}
5837 ins_pipe(pipe_class_default);
5838 %}
5839
5840 // To load a 32 bit constant: merge lower 16 bits into already loaded
5841 // high 16 bits.
5842 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5843 // no match-rule, false predicate
5844 effect(DEF dst, USE src1, USE src2);
5845 predicate(false);
5846
5847 format %{ "ORI $dst, $src1, $src2.lo" %}
5848 size(4);
5849 ins_encode %{
5850 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5851 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5852 %}
5853 ins_pipe(pipe_class_default);
5854 %}
5855
5856 // Load 32-bit long constant
5857 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5858 match(Set dst src);
5859 ins_cost(DEFAULT_COST*2);
5860
5861 expand %{
5862 // Would like to use $src$$constant.
5863 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5864 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5865 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5866 iRegLdst tmpL;
5867 loadConL32hi16(tmpL, srcHi);
5868 loadConL32_lo16(dst, tmpL, srcLo);
5869 %}
5870 %}
5871
5872 // Load long constant 0x????000000000000.
5873 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5874 match(Set dst src);
5875 ins_cost(DEFAULT_COST);
5876
5877 expand %{
5878 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5879 immI shift32 %{ 32 %}
5880 iRegLdst tmpL;
5881 loadConL32hi16(tmpL, srcHi);
5882 lshiftL_regL_immI(dst, tmpL, shift32);
5883 %}
5884 %}
5885
5886 // Expand node for constant pool load: small offset.
5887 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5888 effect(DEF dst, USE src, USE toc);
5889 ins_cost(MEMORY_REF_COST);
5890
5891 ins_num_consts(1);
5892 // Needed so that CallDynamicJavaDirect can compute the address of this
5893 // instruction for relocation.
5894 ins_field_cbuf_insts_offset(int);
5895
5896 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5897 size(4);
5898 ins_encode( enc_load_long_constL(dst, src, toc) );
5899 ins_pipe(pipe_class_memory);
5900 %}
5901
5902 // Expand node for constant pool load: large offset.
5903 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5904 effect(DEF dst, USE src, USE toc);
5905 predicate(false);
5906
5907 ins_num_consts(1);
5908 ins_field_const_toc_offset(int);
5909 // Needed so that CallDynamicJavaDirect can compute the address of this
5910 // instruction for relocation.
5911 ins_field_cbuf_insts_offset(int);
5912
5913 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5914 size(4);
5915 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5916 ins_pipe(pipe_class_default);
5917 %}
5918
5919 // Expand node for constant pool load: large offset.
5920 // No constant pool entries required.
5921 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5922 effect(DEF dst, USE src, USE base);
5923 predicate(false);
5924
5925 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5926
5927 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5928 size(4);
5929 ins_encode %{
5930 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5931 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5932 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5933 %}
5934 ins_pipe(pipe_class_memory);
5935 %}
5936
5937 // Load long constant from constant table. Expand in case of
5938 // offset > 16 bit is needed.
5939 // Adlc adds toc node MachConstantTableBase.
5940 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5941 match(Set dst src);
5942 ins_cost(MEMORY_REF_COST);
5943
5944 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5945 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5946 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5947 %}
5948
5949 // Load NULL as compressed oop.
5950 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5951 match(Set dst src);
5952 ins_cost(DEFAULT_COST);
5953
5954 format %{ "LI $dst, $src \t// compressed ptr" %}
5955 size(4);
5956 ins_encode %{
5957 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5958 __ li($dst$$Register, 0);
5959 %}
5960 ins_pipe(pipe_class_default);
5961 %}
5962
5963 // Load hi part of compressed oop constant.
5964 instruct loadConN_hi(iRegNdst dst, immN src) %{
5965 effect(DEF dst, USE src);
5966 ins_cost(DEFAULT_COST);
5967
5968 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5969 size(4);
5970 ins_encode %{
5971 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5972 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5973 %}
5974 ins_pipe(pipe_class_default);
5975 %}
5976
5977 // Add lo part of compressed oop constant to already loaded hi part.
5978 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5979 effect(DEF dst, USE src1, USE src2);
5980 ins_cost(DEFAULT_COST);
5981
5982 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5983 size(4);
5984 ins_encode %{
5985 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5986 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5987 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5988 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5989 __ relocate(rspec, 1);
5990 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5991 %}
5992 ins_pipe(pipe_class_default);
5993 %}
5994
5995 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5996 // leaving the upper 32 bits with sign-extension bits.
5997 // This clears these bits: dst = src & 0xFFFFFFFF.
5998 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5999 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6000 effect(DEF dst, USE src);
6001 predicate(false);
6002
6003 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6004 size(4);
6005 ins_encode %{
6006 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6007 __ clrldi($dst$$Register, $src$$Register, 0x20);
6008 %}
6009 ins_pipe(pipe_class_default);
6010 %}
6011
6012 // Optimize DecodeN for disjoint base.
6013 // Load base of compressed oops into a register
6014 instruct loadBase(iRegLdst dst) %{
6015 effect(DEF dst);
6016
6017 format %{ "LoadConst $dst, heapbase" %}
6018 ins_encode %{
6019 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6020 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6021 %}
6022 ins_pipe(pipe_class_default);
6023 %}
6024
6025 // Loading ConN must be postalloc expanded so that edges between
6026 // the nodes are safe. They may not interfere with a safepoint.
6027 // GL TODO: This needs three instructions: better put this into the constant pool.
6028 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6029 match(Set dst src);
6030 ins_cost(DEFAULT_COST*2);
6031
6032 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6033 postalloc_expand %{
6034 MachNode *m1 = new loadConN_hiNode();
6035 MachNode *m2 = new loadConN_loNode();
6036 MachNode *m3 = new clearMs32bNode();
6037 m1->add_req(NULL);
6038 m2->add_req(NULL, m1);
6039 m3->add_req(NULL, m2);
6040 m1->_opnds[0] = op_dst;
6041 m1->_opnds[1] = op_src;
6042 m2->_opnds[0] = op_dst;
6043 m2->_opnds[1] = op_dst;
6044 m2->_opnds[2] = op_src;
6045 m3->_opnds[0] = op_dst;
6046 m3->_opnds[1] = op_dst;
6047 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6048 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6049 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6050 nodes->push(m1);
6051 nodes->push(m2);
6052 nodes->push(m3);
6053 %}
6054 %}
6055
6056 // We have seen a safepoint between the hi and lo parts, and this node was handled
6057 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6058 // not a narrow oop.
6059 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6060 match(Set dst src);
6061 effect(DEF dst, USE src);
6062 ins_cost(DEFAULT_COST);
6063
6064 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6065 size(4);
6066 ins_encode %{
6067 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6068 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6069 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6070 %}
6071 ins_pipe(pipe_class_default);
6072 %}
6073
6074 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6075 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6076 match(Set dst src1);
6077 effect(TEMP src2);
6078 ins_cost(DEFAULT_COST);
6079
6080 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6081 size(4);
6082 ins_encode %{
6083 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6084 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6085 %}
6086 ins_pipe(pipe_class_default);
6087 %}
6088
6089 // This needs a match rule so that build_oop_map knows this is
6090 // not a narrow oop.
6091 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6092 match(Set dst src1);
6093 effect(TEMP src2);
6094 ins_cost(DEFAULT_COST);
6095
6096 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6097 size(4);
6098 ins_encode %{
6099 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6100 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6101 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6102 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6103 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6104
6105 __ relocate(rspec, 1);
6106 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6107 %}
6108 ins_pipe(pipe_class_default);
6109 %}
6110
6111 // Loading ConNKlass must be postalloc expanded so that edges between
6112 // the nodes are safe. They may not interfere with a safepoint.
6113 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6114 match(Set dst src);
6115 ins_cost(DEFAULT_COST*2);
6116
6117 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6118 postalloc_expand %{
6119 // Load high bits into register. Sign extended.
6120 MachNode *m1 = new loadConNKlass_hiNode();
6121 m1->add_req(NULL);
6122 m1->_opnds[0] = op_dst;
6123 m1->_opnds[1] = op_src;
6124 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6125 nodes->push(m1);
6126
6127 MachNode *m2 = m1;
6128 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6129 // Value might be 1-extended. Mask out these bits.
6130 m2 = new loadConNKlass_maskNode();
6131 m2->add_req(NULL, m1);
6132 m2->_opnds[0] = op_dst;
6133 m2->_opnds[1] = op_src;
6134 m2->_opnds[2] = op_dst;
6135 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6136 nodes->push(m2);
6137 }
6138
6139 MachNode *m3 = new loadConNKlass_loNode();
6140 m3->add_req(NULL, m2);
6141 m3->_opnds[0] = op_dst;
6142 m3->_opnds[1] = op_src;
6143 m3->_opnds[2] = op_dst;
6144 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6145 nodes->push(m3);
6146 %}
6147 %}
6148
6149 // 0x1 is used in object initialization (initial object header).
6150 // No constant pool entries required.
6151 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6152 match(Set dst src);
6153
6154 format %{ "LI $dst, $src \t// ptr" %}
6155 size(4);
6156 ins_encode %{
6157 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6158 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6159 %}
6160 ins_pipe(pipe_class_default);
6161 %}
6162
6163 // Expand node for constant pool load: small offset.
6164 // The match rule is needed to generate the correct bottom_type(),
6165 // however this node should never match. The use of predicate is not
6166 // possible since ADLC forbids predicates for chain rules. The higher
6167 // costs do not prevent matching in this case. For that reason the
6168 // operand immP_NM with predicate(false) is used.
6169 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6170 match(Set dst src);
6171 effect(TEMP toc);
6172
6173 ins_num_consts(1);
6174
6175 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6176 size(4);
6177 ins_encode( enc_load_long_constP(dst, src, toc) );
6178 ins_pipe(pipe_class_memory);
6179 %}
6180
6181 // Expand node for constant pool load: large offset.
6182 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6183 effect(DEF dst, USE src, USE toc);
6184 predicate(false);
6185
6186 ins_num_consts(1);
6187 ins_field_const_toc_offset(int);
6188
6189 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6190 size(4);
6191 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6192 ins_pipe(pipe_class_default);
6193 %}
6194
6195 // Expand node for constant pool load: large offset.
6196 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6197 match(Set dst src);
6198 effect(TEMP base);
6199
6200 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6201
6202 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6203 size(4);
6204 ins_encode %{
6205 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6206 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6207 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6208 %}
6209 ins_pipe(pipe_class_memory);
6210 %}
6211
6212 // Load pointer constant from constant table. Expand in case an
6213 // offset > 16 bit is needed.
6214 // Adlc adds toc node MachConstantTableBase.
6215 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6216 match(Set dst src);
6217 ins_cost(MEMORY_REF_COST);
6218
6219 // This rule does not use "expand" because then
6220 // the result type is not known to be an Oop. An ADLC
6221 // enhancement will be needed to make that work - not worth it!
6222
6223 // If this instruction rematerializes, it prolongs the live range
6224 // of the toc node, causing illegal graphs.
6225 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6226 ins_cannot_rematerialize(true);
6227
6228 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6229 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6230 %}
6231
6232 // Expand node for constant pool load: small offset.
6233 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6234 effect(DEF dst, USE src, USE toc);
6235 ins_cost(MEMORY_REF_COST);
6236
6237 ins_num_consts(1);
6238
6239 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6240 size(4);
6241 ins_encode %{
6242 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6243 address float_address = __ float_constant($src$$constant);
6244 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6245 %}
6246 ins_pipe(pipe_class_memory);
6247 %}
6248
6249 // Expand node for constant pool load: large offset.
6250 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6251 effect(DEF dst, USE src, USE toc);
6252 ins_cost(MEMORY_REF_COST);
6253
6254 ins_num_consts(1);
6255
6256 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6257 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6258 "ADDIS $toc, $toc, -offset_hi"%}
6259 size(12);
6260 ins_encode %{
6261 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6262 FloatRegister Rdst = $dst$$FloatRegister;
6263 Register Rtoc = $toc$$Register;
6264 address float_address = __ float_constant($src$$constant);
6265 int offset = __ offset_to_method_toc(float_address);
6266 int hi = (offset + (1<<15))>>16;
6267 int lo = offset - hi * (1<<16);
6268
6269 __ addis(Rtoc, Rtoc, hi);
6270 __ lfs(Rdst, lo, Rtoc);
6271 __ addis(Rtoc, Rtoc, -hi);
6272 %}
6273 ins_pipe(pipe_class_memory);
6274 %}
6275
6276 // Adlc adds toc node MachConstantTableBase.
6277 instruct loadConF_Ex(regF dst, immF src) %{
6278 match(Set dst src);
6279 ins_cost(MEMORY_REF_COST);
6280
6281 // See loadConP.
6282 ins_cannot_rematerialize(true);
6283
6284 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6285 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6286 %}
6287
6288 // Expand node for constant pool load: small offset.
6289 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6290 effect(DEF dst, USE src, USE toc);
6291 ins_cost(MEMORY_REF_COST);
6292
6293 ins_num_consts(1);
6294
6295 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6296 size(4);
6297 ins_encode %{
6298 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6299 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6300 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6301 %}
6302 ins_pipe(pipe_class_memory);
6303 %}
6304
6305 // Expand node for constant pool load: large offset.
6306 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6307 effect(DEF dst, USE src, USE toc);
6308 ins_cost(MEMORY_REF_COST);
6309
6310 ins_num_consts(1);
6311
6312 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6313 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6314 "ADDIS $toc, $toc, -offset_hi" %}
6315 size(12);
6316 ins_encode %{
6317 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6318 FloatRegister Rdst = $dst$$FloatRegister;
6319 Register Rtoc = $toc$$Register;
6320 address float_address = __ double_constant($src$$constant);
6321 int offset = __ offset_to_method_toc(float_address);
6322 int hi = (offset + (1<<15))>>16;
6323 int lo = offset - hi * (1<<16);
6324
6325 __ addis(Rtoc, Rtoc, hi);
6326 __ lfd(Rdst, lo, Rtoc);
6327 __ addis(Rtoc, Rtoc, -hi);
6328 %}
6329 ins_pipe(pipe_class_memory);
6330 %}
6331
6332 // Adlc adds toc node MachConstantTableBase.
6333 instruct loadConD_Ex(regD dst, immD src) %{
6334 match(Set dst src);
6335 ins_cost(MEMORY_REF_COST);
6336
6337 // See loadConP.
6338 ins_cannot_rematerialize(true);
6339
6340 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6341 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6342 %}
6343
6344 // Prefetch instructions.
6345 // Must be safe to execute with invalid address (cannot fault).
6346
6347 // Special prefetch versions which use the dcbz instruction.
6348 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6349 match(PrefetchAllocation (AddP mem src));
6350 predicate(AllocatePrefetchStyle == 3);
6351 ins_cost(MEMORY_REF_COST);
6352
6353 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6354 size(4);
6355 ins_encode %{
6356 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6357 __ dcbz($src$$Register, $mem$$base$$Register);
6358 %}
6359 ins_pipe(pipe_class_memory);
6360 %}
6361
6362 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6363 match(PrefetchAllocation mem);
6364 predicate(AllocatePrefetchStyle == 3);
6365 ins_cost(MEMORY_REF_COST);
6366
6367 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6368 size(4);
6369 ins_encode %{
6370 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6371 __ dcbz($mem$$base$$Register);
6372 %}
6373 ins_pipe(pipe_class_memory);
6374 %}
6375
6376 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6377 match(PrefetchAllocation (AddP mem src));
6378 predicate(AllocatePrefetchStyle != 3);
6379 ins_cost(MEMORY_REF_COST);
6380
6381 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6382 size(4);
6383 ins_encode %{
6384 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6385 __ dcbtst($src$$Register, $mem$$base$$Register);
6386 %}
6387 ins_pipe(pipe_class_memory);
6388 %}
6389
6390 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6391 match(PrefetchAllocation mem);
6392 predicate(AllocatePrefetchStyle != 3);
6393 ins_cost(MEMORY_REF_COST);
6394
6395 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6396 size(4);
6397 ins_encode %{
6398 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6399 __ dcbtst($mem$$base$$Register);
6400 %}
6401 ins_pipe(pipe_class_memory);
6402 %}
6403
6404 //----------Store Instructions-------------------------------------------------
6405
6406 // Store Byte
6407 instruct storeB(memory mem, iRegIsrc src) %{
6408 match(Set mem (StoreB mem src));
6409 ins_cost(MEMORY_REF_COST);
6410
6411 format %{ "STB $src, $mem \t// byte" %}
6412 size(4);
6413 ins_encode %{
6414 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6415 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6416 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6417 %}
6418 ins_pipe(pipe_class_memory);
6419 %}
6420
6421 // Store Char/Short
6422 instruct storeC(memory mem, iRegIsrc src) %{
6423 match(Set mem (StoreC mem src));
6424 ins_cost(MEMORY_REF_COST);
6425
6426 format %{ "STH $src, $mem \t// short" %}
6427 size(4);
6428 ins_encode %{
6429 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6430 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6431 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6432 %}
6433 ins_pipe(pipe_class_memory);
6434 %}
6435
6436 // Store Integer
6437 instruct storeI(memory mem, iRegIsrc src) %{
6438 match(Set mem (StoreI mem src));
6439 ins_cost(MEMORY_REF_COST);
6440
6441 format %{ "STW $src, $mem" %}
6442 size(4);
6443 ins_encode( enc_stw(src, mem) );
6444 ins_pipe(pipe_class_memory);
6445 %}
6446
6447 // ConvL2I + StoreI.
6448 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6449 match(Set mem (StoreI mem (ConvL2I src)));
6450 ins_cost(MEMORY_REF_COST);
6451
6452 format %{ "STW l2i($src), $mem" %}
6453 size(4);
6454 ins_encode( enc_stw(src, mem) );
6455 ins_pipe(pipe_class_memory);
6456 %}
6457
6458 // Store Long
6459 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6460 match(Set mem (StoreL mem src));
6461 ins_cost(MEMORY_REF_COST);
6462
6463 format %{ "STD $src, $mem \t// long" %}
6464 size(4);
6465 ins_encode( enc_std(src, mem) );
6466 ins_pipe(pipe_class_memory);
6467 %}
6468
6469 // Store super word nodes.
6470
6471 // Store Aligned Packed Byte long register to memory
6472 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6473 predicate(n->as_StoreVector()->memory_size() == 8);
6474 match(Set mem (StoreVector mem src));
6475 ins_cost(MEMORY_REF_COST);
6476
6477 format %{ "STD $mem, $src \t// packed8B" %}
6478 size(4);
6479 ins_encode( enc_std(src, mem) );
6480 ins_pipe(pipe_class_memory);
6481 %}
6482
6483 // Store Compressed Oop
6484 instruct storeN(memory dst, iRegN_P2N src) %{
6485 match(Set dst (StoreN dst src));
6486 ins_cost(MEMORY_REF_COST);
6487
6488 format %{ "STW $src, $dst \t// compressed oop" %}
6489 size(4);
6490 ins_encode( enc_stw(src, dst) );
6491 ins_pipe(pipe_class_memory);
6492 %}
6493
6494 // Store Compressed KLass
6495 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6496 match(Set dst (StoreNKlass dst src));
6497 ins_cost(MEMORY_REF_COST);
6498
6499 format %{ "STW $src, $dst \t// compressed klass" %}
6500 size(4);
6501 ins_encode( enc_stw(src, dst) );
6502 ins_pipe(pipe_class_memory);
6503 %}
6504
6505 // Store Pointer
6506 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6507 match(Set dst (StoreP dst src));
6508 ins_cost(MEMORY_REF_COST);
6509
6510 format %{ "STD $src, $dst \t// ptr" %}
6511 size(4);
6512 ins_encode( enc_std(src, dst) );
6513 ins_pipe(pipe_class_memory);
6514 %}
6515
6516 // Store Float
6517 instruct storeF(memory mem, regF src) %{
6518 match(Set mem (StoreF mem src));
6519 ins_cost(MEMORY_REF_COST);
6520
6521 format %{ "STFS $src, $mem" %}
6522 size(4);
6523 ins_encode( enc_stfs(src, mem) );
6524 ins_pipe(pipe_class_memory);
6525 %}
6526
6527 // Store Double
6528 instruct storeD(memory mem, regD src) %{
6529 match(Set mem (StoreD mem src));
6530 ins_cost(MEMORY_REF_COST);
6531
6532 format %{ "STFD $src, $mem" %}
6533 size(4);
6534 ins_encode( enc_stfd(src, mem) );
6535 ins_pipe(pipe_class_memory);
6536 %}
6537
6538 //----------Store Instructions With Zeros--------------------------------------
6539
6540 // Card-mark for CMS garbage collection.
6541 // This cardmark does an optimization so that it must not always
6542 // do a releasing store. For this, it gets the address of
6543 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6544 // (Using releaseFieldAddr in the match rule is a hack.)
6545 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6546 match(Set mem (StoreCM mem releaseFieldAddr));
6547 effect(TEMP crx);
6548 predicate(false);
6549 ins_cost(MEMORY_REF_COST);
6550
6551 // See loadConP.
6552 ins_cannot_rematerialize(true);
6553
6554 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6555 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6556 ins_pipe(pipe_class_memory);
6557 %}
6558
6559 // Card-mark for CMS garbage collection.
6560 // This cardmark does an optimization so that it must not always
6561 // do a releasing store. For this, it needs the constant address of
6562 // CMSCollectorCardTableModRefBSExt::_requires_release.
6563 // This constant address is split off here by expand so we can use
6564 // adlc / matcher functionality to load it from the constant section.
6565 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6566 match(Set mem (StoreCM mem zero));
6567 predicate(UseConcMarkSweepGC);
6568
6569 expand %{
6570 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6571 iRegLdst releaseFieldAddress;
6572 flagsReg crx;
6573 loadConL_Ex(releaseFieldAddress, baseImm);
6574 storeCM_CMS(mem, releaseFieldAddress, crx);
6575 %}
6576 %}
6577
6578 instruct storeCM_G1(memory mem, immI_0 zero) %{
6579 match(Set mem (StoreCM mem zero));
6580 predicate(UseG1GC);
6581 ins_cost(MEMORY_REF_COST);
6582
6583 ins_cannot_rematerialize(true);
6584
6585 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6586 size(8);
6587 ins_encode %{
6588 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6589 __ li(R0, 0);
6590 //__ release(); // G1: oops are allowed to get visible after dirty marking
6591 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6592 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6593 %}
6594 ins_pipe(pipe_class_memory);
6595 %}
6596
6597 // Convert oop pointer into compressed form.
6598
6599 // Nodes for postalloc expand.
6600
6601 // Shift node for expand.
6602 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6603 // The match rule is needed to make it a 'MachTypeNode'!
6604 match(Set dst (EncodeP src));
6605 predicate(false);
6606
6607 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6608 size(4);
6609 ins_encode %{
6610 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6611 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6612 %}
6613 ins_pipe(pipe_class_default);
6614 %}
6615
6616 // Add node for expand.
6617 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6618 // The match rule is needed to make it a 'MachTypeNode'!
6619 match(Set dst (EncodeP src));
6620 predicate(false);
6621
6622 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6623 ins_encode %{
6624 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6625 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6626 %}
6627 ins_pipe(pipe_class_default);
6628 %}
6629
6630 // Conditional sub base.
6631 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6632 // The match rule is needed to make it a 'MachTypeNode'!
6633 match(Set dst (EncodeP (Binary crx src1)));
6634 predicate(false);
6635
6636 format %{ "BEQ $crx, done\n\t"
6637 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6638 "done:" %}
6639 ins_encode %{
6640 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6641 Label done;
6642 __ beq($crx$$CondRegister, done);
6643 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6644 __ bind(done);
6645 %}
6646 ins_pipe(pipe_class_default);
6647 %}
6648
6649 // Power 7 can use isel instruction
6650 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6651 // The match rule is needed to make it a 'MachTypeNode'!
6652 match(Set dst (EncodeP (Binary crx src1)));
6653 predicate(false);
6654
6655 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6656 size(4);
6657 ins_encode %{
6658 // This is a Power7 instruction for which no machine description exists.
6659 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6660 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6661 %}
6662 ins_pipe(pipe_class_default);
6663 %}
6664
6665 // Disjoint narrow oop base.
6666 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6667 match(Set dst (EncodeP src));
6668 predicate(Universe::narrow_oop_base_disjoint());
6669
6670 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6671 size(4);
6672 ins_encode %{
6673 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6674 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6675 %}
6676 ins_pipe(pipe_class_default);
6677 %}
6678
6679 // shift != 0, base != 0
6680 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6681 match(Set dst (EncodeP src));
6682 effect(TEMP crx);
6683 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6684 Universe::narrow_oop_shift() != 0 &&
6685 Universe::narrow_oop_base_overlaps());
6686
6687 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6688 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6689 %}
6690
6691 // shift != 0, base != 0
6692 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6693 match(Set dst (EncodeP src));
6694 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6695 Universe::narrow_oop_shift() != 0 &&
6696 Universe::narrow_oop_base_overlaps());
6697
6698 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6699 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6700 %}
6701
6702 // shift != 0, base == 0
6703 // TODO: This is the same as encodeP_shift. Merge!
6704 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6705 match(Set dst (EncodeP src));
6706 predicate(Universe::narrow_oop_shift() != 0 &&
6707 Universe::narrow_oop_base() ==0);
6708
6709 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6710 size(4);
6711 ins_encode %{
6712 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6713 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6714 %}
6715 ins_pipe(pipe_class_default);
6716 %}
6717
6718 // Compressed OOPs with narrow_oop_shift == 0.
6719 // shift == 0, base == 0
6720 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6721 match(Set dst (EncodeP src));
6722 predicate(Universe::narrow_oop_shift() == 0);
6723
6724 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6725 // variable size, 0 or 4.
6726 ins_encode %{
6727 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6728 __ mr_if_needed($dst$$Register, $src$$Register);
6729 %}
6730 ins_pipe(pipe_class_default);
6731 %}
6732
6733 // Decode nodes.
6734
6735 // Shift node for expand.
6736 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6737 // The match rule is needed to make it a 'MachTypeNode'!
6738 match(Set dst (DecodeN src));
6739 predicate(false);
6740
6741 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6742 size(4);
6743 ins_encode %{
6744 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6745 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6746 %}
6747 ins_pipe(pipe_class_default);
6748 %}
6749
6750 // Add node for expand.
6751 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6752 // The match rule is needed to make it a 'MachTypeNode'!
6753 match(Set dst (DecodeN src));
6754 predicate(false);
6755
6756 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %}
6757 ins_encode %{
6758 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6759 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6760 %}
6761 ins_pipe(pipe_class_default);
6762 %}
6763
6764 // conditianal add base for expand
6765 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6766 // The match rule is needed to make it a 'MachTypeNode'!
6767 // NOTICE that the rule is nonsense - we just have to make sure that:
6768 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6769 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6770 match(Set dst (DecodeN (Binary crx src)));
6771 predicate(false);
6772
6773 format %{ "BEQ $crx, done\n\t"
6774 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6775 "done:" %}
6776 ins_encode %{
6777 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6778 Label done;
6779 __ beq($crx$$CondRegister, done);
6780 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6781 __ bind(done);
6782 %}
6783 ins_pipe(pipe_class_default);
6784 %}
6785
6786 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6787 // The match rule is needed to make it a 'MachTypeNode'!
6788 // NOTICE that the rule is nonsense - we just have to make sure that:
6789 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6790 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6791 match(Set dst (DecodeN (Binary crx src1)));
6792 predicate(false);
6793
6794 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6795 size(4);
6796 ins_encode %{
6797 // This is a Power7 instruction for which no machine description exists.
6798 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6799 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6800 %}
6801 ins_pipe(pipe_class_default);
6802 %}
6803
6804 // shift != 0, base != 0
6805 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6806 match(Set dst (DecodeN src));
6807 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6808 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6809 Universe::narrow_oop_shift() != 0 &&
6810 Universe::narrow_oop_base() != 0);
6811 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6812 effect(TEMP crx);
6813
6814 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6815 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6816 %}
6817
6818 // shift != 0, base == 0
6819 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6820 match(Set dst (DecodeN src));
6821 predicate(Universe::narrow_oop_shift() != 0 &&
6822 Universe::narrow_oop_base() == 0);
6823
6824 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6825 size(4);
6826 ins_encode %{
6827 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6828 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6829 %}
6830 ins_pipe(pipe_class_default);
6831 %}
6832
6833 // Optimize DecodeN for disjoint base.
6834 // Shift narrow oop and or it into register that already contains the heap base.
6835 // Base == dst must hold, and is assured by construction in postaloc_expand.
6836 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6837 match(Set dst (DecodeN src));
6838 effect(TEMP base);
6839 predicate(false);
6840
6841 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6842 size(4);
6843 ins_encode %{
6844 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6845 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6846 %}
6847 ins_pipe(pipe_class_default);
6848 %}
6849
6850 // Optimize DecodeN for disjoint base.
6851 // This node requires only one cycle on the critical path.
6852 // We must postalloc_expand as we can not express use_def effects where
6853 // the used register is L and the def'ed register P.
6854 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6855 match(Set dst (DecodeN src));
6856 effect(TEMP_DEF dst);
6857 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6858 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6859 Universe::narrow_oop_base_disjoint());
6860 ins_cost(DEFAULT_COST);
6861
6862 format %{ "MOV $dst, heapbase \t\n"
6863 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6864 postalloc_expand %{
6865 loadBaseNode *n1 = new loadBaseNode();
6866 n1->add_req(NULL);
6867 n1->_opnds[0] = op_dst;
6868
6869 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6870 n2->add_req(n_region, n_src, n1);
6871 n2->_opnds[0] = op_dst;
6872 n2->_opnds[1] = op_src;
6873 n2->_opnds[2] = op_dst;
6874 n2->_bottom_type = _bottom_type;
6875
6876 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6877 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6878
6879 nodes->push(n1);
6880 nodes->push(n2);
6881 %}
6882 %}
6883
6884 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6885 match(Set dst (DecodeN src));
6886 effect(TEMP_DEF dst, TEMP crx);
6887 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6888 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6889 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6890 ins_cost(3 * DEFAULT_COST);
6891
6892 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %}
6893 postalloc_expand %{
6894 loadBaseNode *n1 = new loadBaseNode();
6895 n1->add_req(NULL);
6896 n1->_opnds[0] = op_dst;
6897
6898 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
6899 n_compare->add_req(n_region, n_src);
6900 n_compare->_opnds[0] = op_crx;
6901 n_compare->_opnds[1] = op_src;
6902 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6903
6904 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6905 n2->add_req(n_region, n_src, n1);
6906 n2->_opnds[0] = op_dst;
6907 n2->_opnds[1] = op_src;
6908 n2->_opnds[2] = op_dst;
6909 n2->_bottom_type = _bottom_type;
6910
6911 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6912 n_cond_set->add_req(n_region, n_compare, n2);
6913 n_cond_set->_opnds[0] = op_dst;
6914 n_cond_set->_opnds[1] = op_crx;
6915 n_cond_set->_opnds[2] = op_dst;
6916 n_cond_set->_bottom_type = _bottom_type;
6917
6918 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6919 ra_->set_oop(n_cond_set, true);
6920
6921 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6922 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6923 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6924 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6925
6926 nodes->push(n1);
6927 nodes->push(n_compare);
6928 nodes->push(n2);
6929 nodes->push(n_cond_set);
6930 %}
6931 %}
6932
6933 // src != 0, shift != 0, base != 0
6934 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6935 match(Set dst (DecodeN src));
6936 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6937 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6938 Universe::narrow_oop_shift() != 0 &&
6939 Universe::narrow_oop_base() != 0);
6940 ins_cost(2 * DEFAULT_COST);
6941
6942 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6943 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6944 %}
6945
6946 // Compressed OOPs with narrow_oop_shift == 0.
6947 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6948 match(Set dst (DecodeN src));
6949 predicate(Universe::narrow_oop_shift() == 0);
6950 ins_cost(DEFAULT_COST);
6951
6952 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6953 // variable size, 0 or 4.
6954 ins_encode %{
6955 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6956 __ mr_if_needed($dst$$Register, $src$$Register);
6957 %}
6958 ins_pipe(pipe_class_default);
6959 %}
6960
6961 // Convert compressed oop into int for vectors alignment masking.
6962 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6963 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6964 predicate(Universe::narrow_oop_shift() == 0);
6965 ins_cost(DEFAULT_COST);
6966
6967 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6968 // variable size, 0 or 4.
6969 ins_encode %{
6970 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6971 __ mr_if_needed($dst$$Register, $src$$Register);
6972 %}
6973 ins_pipe(pipe_class_default);
6974 %}
6975
6976 // Convert klass pointer into compressed form.
6977
6978 // Nodes for postalloc expand.
6979
6980 // Shift node for expand.
6981 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6982 // The match rule is needed to make it a 'MachTypeNode'!
6983 match(Set dst (EncodePKlass src));
6984 predicate(false);
6985
6986 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6987 size(4);
6988 ins_encode %{
6989 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6990 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6991 %}
6992 ins_pipe(pipe_class_default);
6993 %}
6994
6995 // Add node for expand.
6996 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6997 // The match rule is needed to make it a 'MachTypeNode'!
6998 match(Set dst (EncodePKlass (Binary base src)));
6999 predicate(false);
7000
7001 format %{ "SUB $dst, $base, $src \t// encode" %}
7002 size(4);
7003 ins_encode %{
7004 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7005 __ subf($dst$$Register, $base$$Register, $src$$Register);
7006 %}
7007 ins_pipe(pipe_class_default);
7008 %}
7009
7010 // Disjoint narrow oop base.
7011 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7012 match(Set dst (EncodePKlass src));
7013 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7014
7015 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
7016 size(4);
7017 ins_encode %{
7018 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7019 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7020 %}
7021 ins_pipe(pipe_class_default);
7022 %}
7023
7024 // shift != 0, base != 0
7025 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7026 match(Set dst (EncodePKlass (Binary base src)));
7027 predicate(false);
7028
7029 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7030 postalloc_expand %{
7031 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7032 n1->add_req(n_region, n_base, n_src);
7033 n1->_opnds[0] = op_dst;
7034 n1->_opnds[1] = op_base;
7035 n1->_opnds[2] = op_src;
7036 n1->_bottom_type = _bottom_type;
7037
7038 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7039 n2->add_req(n_region, n1);
7040 n2->_opnds[0] = op_dst;
7041 n2->_opnds[1] = op_dst;
7042 n2->_bottom_type = _bottom_type;
7043 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7044 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7045
7046 nodes->push(n1);
7047 nodes->push(n2);
7048 %}
7049 %}
7050
7051 // shift != 0, base != 0
7052 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7053 match(Set dst (EncodePKlass src));
7054 //predicate(Universe::narrow_klass_shift() != 0 &&
7055 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7056
7057 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7058 ins_cost(DEFAULT_COST*2); // Don't count constant.
7059 expand %{
7060 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7061 iRegLdst base;
7062 loadConL_Ex(base, baseImm);
7063 encodePKlass_not_null_Ex(dst, base, src);
7064 %}
7065 %}
7066
7067 // Decode nodes.
7068
7069 // Shift node for expand.
7070 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7071 // The match rule is needed to make it a 'MachTypeNode'!
7072 match(Set dst (DecodeNKlass src));
7073 predicate(false);
7074
7075 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7076 size(4);
7077 ins_encode %{
7078 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7079 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7080 %}
7081 ins_pipe(pipe_class_default);
7082 %}
7083
7084 // Add node for expand.
7085
7086 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7087 // The match rule is needed to make it a 'MachTypeNode'!
7088 match(Set dst (DecodeNKlass (Binary base src)));
7089 predicate(false);
7090
7091 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7092 size(4);
7093 ins_encode %{
7094 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7095 __ add($dst$$Register, $base$$Register, $src$$Register);
7096 %}
7097 ins_pipe(pipe_class_default);
7098 %}
7099
7100 // src != 0, shift != 0, base != 0
7101 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7102 match(Set dst (DecodeNKlass (Binary base src)));
7103 //effect(kill src); // We need a register for the immediate result after shifting.
7104 predicate(false);
7105
7106 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7107 postalloc_expand %{
7108 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7109 n1->add_req(n_region, n_base, n_src);
7110 n1->_opnds[0] = op_dst;
7111 n1->_opnds[1] = op_base;
7112 n1->_opnds[2] = op_src;
7113 n1->_bottom_type = _bottom_type;
7114
7115 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7116 n2->add_req(n_region, n1);
7117 n2->_opnds[0] = op_dst;
7118 n2->_opnds[1] = op_dst;
7119 n2->_bottom_type = _bottom_type;
7120
7121 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7122 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7123
7124 nodes->push(n1);
7125 nodes->push(n2);
7126 %}
7127 %}
7128
7129 // src != 0, shift != 0, base != 0
7130 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7131 match(Set dst (DecodeNKlass src));
7132 // predicate(Universe::narrow_klass_shift() != 0 &&
7133 // Universe::narrow_klass_base() != 0);
7134
7135 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7136
7137 ins_cost(DEFAULT_COST*2); // Don't count constant.
7138 expand %{
7139 // We add first, then we shift. Like this, we can get along with one register less.
7140 // But we have to load the base pre-shifted.
7141 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7142 iRegLdst base;
7143 loadConL_Ex(base, baseImm);
7144 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7145 %}
7146 %}
7147
7148 //----------MemBar Instructions-----------------------------------------------
7149 // Memory barrier flavors
7150
7151 instruct membar_acquire() %{
7152 match(LoadFence);
7153 ins_cost(4*MEMORY_REF_COST);
7154
7155 format %{ "MEMBAR-acquire" %}
7156 size(4);
7157 ins_encode %{
7158 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7159 __ acquire();
7160 %}
7161 ins_pipe(pipe_class_default);
7162 %}
7163
7164 instruct unnecessary_membar_acquire() %{
7165 match(MemBarAcquire);
7166 ins_cost(0);
7167
7168 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7169 size(0);
7170 ins_encode( /*empty*/ );
7171 ins_pipe(pipe_class_default);
7172 %}
7173
7174 instruct membar_acquire_lock() %{
7175 match(MemBarAcquireLock);
7176 ins_cost(0);
7177
7178 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7179 size(0);
7180 ins_encode( /*empty*/ );
7181 ins_pipe(pipe_class_default);
7182 %}
7183
7184 instruct membar_release() %{
7185 match(MemBarRelease);
7186 match(StoreFence);
7187 ins_cost(4*MEMORY_REF_COST);
7188
7189 format %{ "MEMBAR-release" %}
7190 size(4);
7191 ins_encode %{
7192 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7193 __ release();
7194 %}
7195 ins_pipe(pipe_class_default);
7196 %}
7197
7198 instruct membar_storestore() %{
7199 match(MemBarStoreStore);
7200 ins_cost(4*MEMORY_REF_COST);
7201
7202 format %{ "MEMBAR-store-store" %}
7203 size(4);
7204 ins_encode %{
7205 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7206 __ membar(Assembler::StoreStore);
7207 %}
7208 ins_pipe(pipe_class_default);
7209 %}
7210
7211 instruct membar_release_lock() %{
7212 match(MemBarReleaseLock);
7213 ins_cost(0);
7214
7215 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7216 size(0);
7217 ins_encode( /*empty*/ );
7218 ins_pipe(pipe_class_default);
7219 %}
7220
7221 instruct membar_volatile() %{
7222 match(MemBarVolatile);
7223 ins_cost(4*MEMORY_REF_COST);
7224
7225 format %{ "MEMBAR-volatile" %}
7226 size(4);
7227 ins_encode %{
7228 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7229 __ fence();
7230 %}
7231 ins_pipe(pipe_class_default);
7232 %}
7233
7234 // This optimization is wrong on PPC. The following pattern is not supported:
7235 // MemBarVolatile
7236 // ^ ^
7237 // | |
7238 // CtrlProj MemProj
7239 // ^ ^
7240 // | |
7241 // | Load
7242 // |
7243 // MemBarVolatile
7244 //
7245 // The first MemBarVolatile could get optimized out! According to
7246 // Vladimir, this pattern can not occur on Oracle platforms.
7247 // However, it does occur on PPC64 (because of membars in
7248 // inline_unsafe_load_store).
7249 //
7250 // Add this node again if we found a good solution for inline_unsafe_load_store().
7251 // Don't forget to look at the implementation of post_store_load_barrier again,
7252 // we did other fixes in that method.
7253 //instruct unnecessary_membar_volatile() %{
7254 // match(MemBarVolatile);
7255 // predicate(Matcher::post_store_load_barrier(n));
7256 // ins_cost(0);
7257 //
7258 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7259 // size(0);
7260 // ins_encode( /*empty*/ );
7261 // ins_pipe(pipe_class_default);
7262 //%}
7263
7264 instruct membar_CPUOrder() %{
7265 match(MemBarCPUOrder);
7266 ins_cost(0);
7267
7268 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7269 size(0);
7270 ins_encode( /*empty*/ );
7271 ins_pipe(pipe_class_default);
7272 %}
7273
7274 //----------Conditional Move---------------------------------------------------
7275
7276 // Cmove using isel.
7277 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7278 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7279 predicate(VM_Version::has_isel());
7280 ins_cost(DEFAULT_COST);
7281
7282 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7283 size(4);
7284 ins_encode %{
7285 // This is a Power7 instruction for which no machine description
7286 // exists. Anyways, the scheduler should be off on Power7.
7287 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7288 int cc = $cmp$$cmpcode;
7289 __ isel($dst$$Register, $crx$$CondRegister,
7290 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7291 %}
7292 ins_pipe(pipe_class_default);
7293 %}
7294
7295 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7296 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7297 predicate(!VM_Version::has_isel());
7298 ins_cost(DEFAULT_COST+BRANCH_COST);
7299
7300 ins_variable_size_depending_on_alignment(true);
7301
7302 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7303 // Worst case is branch + move + stop, no stop without scheduler
7304 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7305 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7306 ins_pipe(pipe_class_default);
7307 %}
7308
7309 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7310 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7311 ins_cost(DEFAULT_COST+BRANCH_COST);
7312
7313 ins_variable_size_depending_on_alignment(true);
7314
7315 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7316 // Worst case is branch + move + stop, no stop without scheduler
7317 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7318 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7319 ins_pipe(pipe_class_default);
7320 %}
7321
7322 // Cmove using isel.
7323 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7324 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7325 predicate(VM_Version::has_isel());
7326 ins_cost(DEFAULT_COST);
7327
7328 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7329 size(4);
7330 ins_encode %{
7331 // This is a Power7 instruction for which no machine description
7332 // exists. Anyways, the scheduler should be off on Power7.
7333 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7334 int cc = $cmp$$cmpcode;
7335 __ isel($dst$$Register, $crx$$CondRegister,
7336 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7337 %}
7338 ins_pipe(pipe_class_default);
7339 %}
7340
7341 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7342 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7343 predicate(!VM_Version::has_isel());
7344 ins_cost(DEFAULT_COST+BRANCH_COST);
7345
7346 ins_variable_size_depending_on_alignment(true);
7347
7348 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7349 // Worst case is branch + move + stop, no stop without scheduler.
7350 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7351 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7352 ins_pipe(pipe_class_default);
7353 %}
7354
7355 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7356 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7357 ins_cost(DEFAULT_COST+BRANCH_COST);
7358
7359 ins_variable_size_depending_on_alignment(true);
7360
7361 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7362 // Worst case is branch + move + stop, no stop without scheduler.
7363 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7364 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7365 ins_pipe(pipe_class_default);
7366 %}
7367
7368 // Cmove using isel.
7369 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7370 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7371 predicate(VM_Version::has_isel());
7372 ins_cost(DEFAULT_COST);
7373
7374 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7375 size(4);
7376 ins_encode %{
7377 // This is a Power7 instruction for which no machine description
7378 // exists. Anyways, the scheduler should be off on Power7.
7379 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7380 int cc = $cmp$$cmpcode;
7381 __ isel($dst$$Register, $crx$$CondRegister,
7382 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7383 %}
7384 ins_pipe(pipe_class_default);
7385 %}
7386
7387 // Conditional move for RegN. Only cmov(reg, reg).
7388 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7389 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7390 predicate(!VM_Version::has_isel());
7391 ins_cost(DEFAULT_COST+BRANCH_COST);
7392
7393 ins_variable_size_depending_on_alignment(true);
7394
7395 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7396 // Worst case is branch + move + stop, no stop without scheduler.
7397 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7398 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7399 ins_pipe(pipe_class_default);
7400 %}
7401
7402 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7403 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7404 ins_cost(DEFAULT_COST+BRANCH_COST);
7405
7406 ins_variable_size_depending_on_alignment(true);
7407
7408 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7409 // Worst case is branch + move + stop, no stop without scheduler.
7410 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7411 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7412 ins_pipe(pipe_class_default);
7413 %}
7414
7415 // Cmove using isel.
7416 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7417 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7418 predicate(VM_Version::has_isel());
7419 ins_cost(DEFAULT_COST);
7420
7421 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7422 size(4);
7423 ins_encode %{
7424 // This is a Power7 instruction for which no machine description
7425 // exists. Anyways, the scheduler should be off on Power7.
7426 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7427 int cc = $cmp$$cmpcode;
7428 __ isel($dst$$Register, $crx$$CondRegister,
7429 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7430 %}
7431 ins_pipe(pipe_class_default);
7432 %}
7433
7434 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7435 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7436 predicate(!VM_Version::has_isel());
7437 ins_cost(DEFAULT_COST+BRANCH_COST);
7438
7439 ins_variable_size_depending_on_alignment(true);
7440
7441 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7442 // Worst case is branch + move + stop, no stop without scheduler.
7443 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7444 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7445 ins_pipe(pipe_class_default);
7446 %}
7447
7448 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7449 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7450 ins_cost(DEFAULT_COST+BRANCH_COST);
7451
7452 ins_variable_size_depending_on_alignment(true);
7453
7454 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7455 // Worst case is branch + move + stop, no stop without scheduler.
7456 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7457 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7458 ins_pipe(pipe_class_default);
7459 %}
7460
7461 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7462 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7463 ins_cost(DEFAULT_COST+BRANCH_COST);
7464
7465 ins_variable_size_depending_on_alignment(true);
7466
7467 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7468 // Worst case is branch + move + stop, no stop without scheduler.
7469 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7470 ins_encode %{
7471 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7472 Label done;
7473 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7474 // Branch if not (cmp crx).
7475 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7476 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7477 // TODO PPC port __ endgroup_if_needed(_size == 12);
7478 __ bind(done);
7479 %}
7480 ins_pipe(pipe_class_default);
7481 %}
7482
7483 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7484 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7485 ins_cost(DEFAULT_COST+BRANCH_COST);
7486
7487 ins_variable_size_depending_on_alignment(true);
7488
7489 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7490 // Worst case is branch + move + stop, no stop without scheduler.
7491 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7492 ins_encode %{
7493 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7494 Label done;
7495 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7496 // Branch if not (cmp crx).
7497 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7498 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7499 // TODO PPC port __ endgroup_if_needed(_size == 12);
7500 __ bind(done);
7501 %}
7502 ins_pipe(pipe_class_default);
7503 %}
7504
7505 //----------Conditional_store--------------------------------------------------
7506 // Conditional-store of the updated heap-top.
7507 // Used during allocation of the shared heap.
7508 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7509
7510 // As compareAndSwapL, but return flag register instead of boolean value in
7511 // int register.
7512 // Used by sun/misc/AtomicLongCSImpl.java.
7513 // Mem_ptr must be a memory operand, else this node does not get
7514 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7515 // can be rematerialized which leads to errors.
7516 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7517 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7518 effect(TEMP cr0);
7519 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7520 ins_encode %{
7521 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7522 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7523 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7524 noreg, NULL, true);
7525 %}
7526 ins_pipe(pipe_class_default);
7527 %}
7528
7529 // As compareAndSwapP, but return flag register instead of boolean value in
7530 // int register.
7531 // This instruction is matched if UseTLAB is off.
7532 // Mem_ptr must be a memory operand, else this node does not get
7533 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7534 // can be rematerialized which leads to errors.
7535 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7536 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7537 ins_cost(2*MEMORY_REF_COST);
7538
7539 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7540 ins_encode %{
7541 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7542 __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7543 %}
7544 ins_pipe(pipe_class_memory);
7545 %}
7546
7547 // Implement LoadPLocked. Must be ordered against changes of the memory location
7548 // by storePConditional.
7549 // Don't know whether this is ever used.
7550 instruct loadPLocked(iRegPdst dst, memory mem) %{
7551 match(Set dst (LoadPLocked mem));
7552 ins_cost(2*MEMORY_REF_COST);
7553
7554 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %}
7555 size(4);
7556 ins_encode %{
7557 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7558 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7559 %}
7560 ins_pipe(pipe_class_memory);
7561 %}
7562
7563 //----------Compare-And-Swap---------------------------------------------------
7564
7565 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7566 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7567 // matched.
7568
7569 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7570 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7571 effect(TEMP cr0);
7572 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7573 // Variable size: instruction count smaller if regs are disjoint.
7574 ins_encode %{
7575 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7576 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7577 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7578 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7579 $res$$Register, true);
7580 %}
7581 ins_pipe(pipe_class_default);
7582 %}
7583
7584 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7585 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7586 effect(TEMP cr0);
7587 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7588 // Variable size: instruction count smaller if regs are disjoint.
7589 ins_encode %{
7590 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7591 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7592 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7593 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7594 $res$$Register, true);
7595 %}
7596 ins_pipe(pipe_class_default);
7597 %}
7598
7599 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7600 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7601 effect(TEMP cr0);
7602 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7603 // Variable size: instruction count smaller if regs are disjoint.
7604 ins_encode %{
7605 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7606 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7607 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7608 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7609 $res$$Register, NULL, true);
7610 %}
7611 ins_pipe(pipe_class_default);
7612 %}
7613
7614 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7615 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7616 effect(TEMP cr0);
7617 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7618 // Variable size: instruction count smaller if regs are disjoint.
7619 ins_encode %{
7620 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7621 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7622 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7623 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7624 $res$$Register, NULL, true);
7625 %}
7626 ins_pipe(pipe_class_default);
7627 %}
7628
7629 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7630 match(Set res (GetAndAddI mem_ptr src));
7631 effect(TEMP cr0);
7632 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7633 // Variable size: instruction count smaller if regs are disjoint.
7634 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7635 ins_pipe(pipe_class_default);
7636 %}
7637
7638 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7639 match(Set res (GetAndAddL mem_ptr src));
7640 effect(TEMP cr0);
7641 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7642 // Variable size: instruction count smaller if regs are disjoint.
7643 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7644 ins_pipe(pipe_class_default);
7645 %}
7646
7647 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7648 match(Set res (GetAndSetI mem_ptr src));
7649 effect(TEMP cr0);
7650 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7651 // Variable size: instruction count smaller if regs are disjoint.
7652 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7653 ins_pipe(pipe_class_default);
7654 %}
7655
7656 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7657 match(Set res (GetAndSetL mem_ptr src));
7658 effect(TEMP cr0);
7659 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7660 // Variable size: instruction count smaller if regs are disjoint.
7661 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7662 ins_pipe(pipe_class_default);
7663 %}
7664
7665 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7666 match(Set res (GetAndSetP mem_ptr src));
7667 effect(TEMP cr0);
7668 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7669 // Variable size: instruction count smaller if regs are disjoint.
7670 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7671 ins_pipe(pipe_class_default);
7672 %}
7673
7674 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7675 match(Set res (GetAndSetN mem_ptr src));
7676 effect(TEMP cr0);
7677 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7678 // Variable size: instruction count smaller if regs are disjoint.
7679 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7680 ins_pipe(pipe_class_default);
7681 %}
7682
7683 //----------Arithmetic Instructions--------------------------------------------
7684 // Addition Instructions
7685
7686 // Register Addition
7687 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7688 match(Set dst (AddI src1 src2));
7689 format %{ "ADD $dst, $src1, $src2" %}
7690 size(4);
7691 ins_encode %{
7692 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7693 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7694 %}
7695 ins_pipe(pipe_class_default);
7696 %}
7697
7698 // Expand does not work with above instruct. (??)
7699 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7700 // no match-rule
7701 effect(DEF dst, USE src1, USE src2);
7702 format %{ "ADD $dst, $src1, $src2" %}
7703 size(4);
7704 ins_encode %{
7705 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7706 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7707 %}
7708 ins_pipe(pipe_class_default);
7709 %}
7710
7711 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7712 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7713 ins_cost(DEFAULT_COST*3);
7714
7715 expand %{
7716 // FIXME: we should do this in the ideal world.
7717 iRegIdst tmp1;
7718 iRegIdst tmp2;
7719 addI_reg_reg(tmp1, src1, src2);
7720 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7721 addI_reg_reg(dst, tmp1, tmp2);
7722 %}
7723 %}
7724
7725 // Immediate Addition
7726 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7727 match(Set dst (AddI src1 src2));
7728 format %{ "ADDI $dst, $src1, $src2" %}
7729 size(4);
7730 ins_encode %{
7731 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7732 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7733 %}
7734 ins_pipe(pipe_class_default);
7735 %}
7736
7737 // Immediate Addition with 16-bit shifted operand
7738 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7739 match(Set dst (AddI src1 src2));
7740 format %{ "ADDIS $dst, $src1, $src2" %}
7741 size(4);
7742 ins_encode %{
7743 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7744 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7745 %}
7746 ins_pipe(pipe_class_default);
7747 %}
7748
7749 // Long Addition
7750 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7751 match(Set dst (AddL src1 src2));
7752 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7753 size(4);
7754 ins_encode %{
7755 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7756 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7757 %}
7758 ins_pipe(pipe_class_default);
7759 %}
7760
7761 // Expand does not work with above instruct. (??)
7762 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7763 // no match-rule
7764 effect(DEF dst, USE src1, USE src2);
7765 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7766 size(4);
7767 ins_encode %{
7768 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7769 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7770 %}
7771 ins_pipe(pipe_class_default);
7772 %}
7773
7774 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7775 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7776 ins_cost(DEFAULT_COST*3);
7777
7778 expand %{
7779 // FIXME: we should do this in the ideal world.
7780 iRegLdst tmp1;
7781 iRegLdst tmp2;
7782 addL_reg_reg(tmp1, src1, src2);
7783 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7784 addL_reg_reg(dst, tmp1, tmp2);
7785 %}
7786 %}
7787
7788 // AddL + ConvL2I.
7789 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7790 match(Set dst (ConvL2I (AddL src1 src2)));
7791
7792 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7793 size(4);
7794 ins_encode %{
7795 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7796 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7797 %}
7798 ins_pipe(pipe_class_default);
7799 %}
7800
7801 // No constant pool entries required.
7802 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7803 match(Set dst (AddL src1 src2));
7804
7805 format %{ "ADDI $dst, $src1, $src2" %}
7806 size(4);
7807 ins_encode %{
7808 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7809 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7810 %}
7811 ins_pipe(pipe_class_default);
7812 %}
7813
7814 // Long Immediate Addition with 16-bit shifted operand.
7815 // No constant pool entries required.
7816 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7817 match(Set dst (AddL src1 src2));
7818
7819 format %{ "ADDIS $dst, $src1, $src2" %}
7820 size(4);
7821 ins_encode %{
7822 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7823 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7824 %}
7825 ins_pipe(pipe_class_default);
7826 %}
7827
7828 // Pointer Register Addition
7829 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7830 match(Set dst (AddP src1 src2));
7831 format %{ "ADD $dst, $src1, $src2" %}
7832 size(4);
7833 ins_encode %{
7834 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7835 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7836 %}
7837 ins_pipe(pipe_class_default);
7838 %}
7839
7840 // Pointer Immediate Addition
7841 // No constant pool entries required.
7842 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7843 match(Set dst (AddP src1 src2));
7844
7845 format %{ "ADDI $dst, $src1, $src2" %}
7846 size(4);
7847 ins_encode %{
7848 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7849 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7850 %}
7851 ins_pipe(pipe_class_default);
7852 %}
7853
7854 // Pointer Immediate Addition with 16-bit shifted operand.
7855 // No constant pool entries required.
7856 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7857 match(Set dst (AddP src1 src2));
7858
7859 format %{ "ADDIS $dst, $src1, $src2" %}
7860 size(4);
7861 ins_encode %{
7862 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7863 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7864 %}
7865 ins_pipe(pipe_class_default);
7866 %}
7867
7868 //---------------------
7869 // Subtraction Instructions
7870
7871 // Register Subtraction
7872 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7873 match(Set dst (SubI src1 src2));
7874 format %{ "SUBF $dst, $src2, $src1" %}
7875 size(4);
7876 ins_encode %{
7877 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7878 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7879 %}
7880 ins_pipe(pipe_class_default);
7881 %}
7882
7883 // Immediate Subtraction
7884 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7885 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7886
7887 // SubI from constant (using subfic).
7888 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7889 match(Set dst (SubI src1 src2));
7890 format %{ "SUBI $dst, $src1, $src2" %}
7891
7892 size(4);
7893 ins_encode %{
7894 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7895 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7896 %}
7897 ins_pipe(pipe_class_default);
7898 %}
7899
7900 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7901 // positive integers and 0xF...F for negative ones.
7902 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7903 // no match-rule, false predicate
7904 effect(DEF dst, USE src);
7905 predicate(false);
7906
7907 format %{ "SRAWI $dst, $src, #31" %}
7908 size(4);
7909 ins_encode %{
7910 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7911 __ srawi($dst$$Register, $src$$Register, 0x1f);
7912 %}
7913 ins_pipe(pipe_class_default);
7914 %}
7915
7916 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7917 match(Set dst (AbsI src));
7918 ins_cost(DEFAULT_COST*3);
7919
7920 expand %{
7921 iRegIdst tmp1;
7922 iRegIdst tmp2;
7923 signmask32I_regI(tmp1, src);
7924 xorI_reg_reg(tmp2, tmp1, src);
7925 subI_reg_reg(dst, tmp2, tmp1);
7926 %}
7927 %}
7928
7929 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7930 match(Set dst (SubI zero src2));
7931 format %{ "NEG $dst, $src2" %}
7932 size(4);
7933 ins_encode %{
7934 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7935 __ neg($dst$$Register, $src2$$Register);
7936 %}
7937 ins_pipe(pipe_class_default);
7938 %}
7939
7940 // Long subtraction
7941 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7942 match(Set dst (SubL src1 src2));
7943 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7944 size(4);
7945 ins_encode %{
7946 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7947 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7948 %}
7949 ins_pipe(pipe_class_default);
7950 %}
7951
7952 // SubL + convL2I.
7953 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7954 match(Set dst (ConvL2I (SubL src1 src2)));
7955
7956 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7957 size(4);
7958 ins_encode %{
7959 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7960 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7961 %}
7962 ins_pipe(pipe_class_default);
7963 %}
7964
7965 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7966 // positive longs and 0xF...F for negative ones.
7967 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7968 // no match-rule, false predicate
7969 effect(DEF dst, USE src);
7970 predicate(false);
7971
7972 format %{ "SRADI $dst, $src, #63" %}
7973 size(4);
7974 ins_encode %{
7975 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7976 __ sradi($dst$$Register, $src$$Register, 0x3f);
7977 %}
7978 ins_pipe(pipe_class_default);
7979 %}
7980
7981 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7982 // positive longs and 0xF...F for negative ones.
7983 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7984 // no match-rule, false predicate
7985 effect(DEF dst, USE src);
7986 predicate(false);
7987
7988 format %{ "SRADI $dst, $src, #63" %}
7989 size(4);
7990 ins_encode %{
7991 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7992 __ sradi($dst$$Register, $src$$Register, 0x3f);
7993 %}
7994 ins_pipe(pipe_class_default);
7995 %}
7996
7997 // Long negation
7998 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7999 match(Set dst (SubL zero src2));
8000 format %{ "NEG $dst, $src2 \t// long" %}
8001 size(4);
8002 ins_encode %{
8003 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8004 __ neg($dst$$Register, $src2$$Register);
8005 %}
8006 ins_pipe(pipe_class_default);
8007 %}
8008
8009 // NegL + ConvL2I.
8010 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8011 match(Set dst (ConvL2I (SubL zero src2)));
8012
8013 format %{ "NEG $dst, $src2 \t// long + l2i" %}
8014 size(4);
8015 ins_encode %{
8016 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8017 __ neg($dst$$Register, $src2$$Register);
8018 %}
8019 ins_pipe(pipe_class_default);
8020 %}
8021
8022 // Multiplication Instructions
8023 // Integer Multiplication
8024
8025 // Register Multiplication
8026 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8027 match(Set dst (MulI src1 src2));
8028 ins_cost(DEFAULT_COST);
8029
8030 format %{ "MULLW $dst, $src1, $src2" %}
8031 size(4);
8032 ins_encode %{
8033 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8034 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8035 %}
8036 ins_pipe(pipe_class_default);
8037 %}
8038
8039 // Immediate Multiplication
8040 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8041 match(Set dst (MulI src1 src2));
8042 ins_cost(DEFAULT_COST);
8043
8044 format %{ "MULLI $dst, $src1, $src2" %}
8045 size(4);
8046 ins_encode %{
8047 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8048 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8049 %}
8050 ins_pipe(pipe_class_default);
8051 %}
8052
8053 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8054 match(Set dst (MulL src1 src2));
8055 ins_cost(DEFAULT_COST);
8056
8057 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8058 size(4);
8059 ins_encode %{
8060 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8061 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8062 %}
8063 ins_pipe(pipe_class_default);
8064 %}
8065
8066 // Multiply high for optimized long division by constant.
8067 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8068 match(Set dst (MulHiL src1 src2));
8069 ins_cost(DEFAULT_COST);
8070
8071 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8072 size(4);
8073 ins_encode %{
8074 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8075 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8076 %}
8077 ins_pipe(pipe_class_default);
8078 %}
8079
8080 // Immediate Multiplication
8081 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8082 match(Set dst (MulL src1 src2));
8083 ins_cost(DEFAULT_COST);
8084
8085 format %{ "MULLI $dst, $src1, $src2" %}
8086 size(4);
8087 ins_encode %{
8088 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8089 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8090 %}
8091 ins_pipe(pipe_class_default);
8092 %}
8093
8094 // Integer Division with Immediate -1: Negate.
8095 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8096 match(Set dst (DivI src1 src2));
8097 ins_cost(DEFAULT_COST);
8098
8099 format %{ "NEG $dst, $src1 \t// /-1" %}
8100 size(4);
8101 ins_encode %{
8102 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8103 __ neg($dst$$Register, $src1$$Register);
8104 %}
8105 ins_pipe(pipe_class_default);
8106 %}
8107
8108 // Integer Division with constant, but not -1.
8109 // We should be able to improve this by checking the type of src2.
8110 // It might well be that src2 is known to be positive.
8111 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8112 match(Set dst (DivI src1 src2));
8113 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8114 ins_cost(2*DEFAULT_COST);
8115
8116 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8117 size(4);
8118 ins_encode %{
8119 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8120 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8121 %}
8122 ins_pipe(pipe_class_default);
8123 %}
8124
8125 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8126 effect(USE_DEF dst, USE src1, USE crx);
8127 predicate(false);
8128
8129 ins_variable_size_depending_on_alignment(true);
8130
8131 format %{ "CMOVE $dst, neg($src1), $crx" %}
8132 // Worst case is branch + move + stop, no stop without scheduler.
8133 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8134 ins_encode %{
8135 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8136 Label done;
8137 __ bne($crx$$CondRegister, done);
8138 __ neg($dst$$Register, $src1$$Register);
8139 // TODO PPC port __ endgroup_if_needed(_size == 12);
8140 __ bind(done);
8141 %}
8142 ins_pipe(pipe_class_default);
8143 %}
8144
8145 // Integer Division with Registers not containing constants.
8146 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8147 match(Set dst (DivI src1 src2));
8148 ins_cost(10*DEFAULT_COST);
8149
8150 expand %{
8151 immI16 imm %{ (int)-1 %}
8152 flagsReg tmp1;
8153 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8154 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8155 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8156 %}
8157 %}
8158
8159 // Long Division with Immediate -1: Negate.
8160 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8161 match(Set dst (DivL src1 src2));
8162 ins_cost(DEFAULT_COST);
8163
8164 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8165 size(4);
8166 ins_encode %{
8167 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8168 __ neg($dst$$Register, $src1$$Register);
8169 %}
8170 ins_pipe(pipe_class_default);
8171 %}
8172
8173 // Long Division with constant, but not -1.
8174 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8175 match(Set dst (DivL src1 src2));
8176 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8177 ins_cost(2*DEFAULT_COST);
8178
8179 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8180 size(4);
8181 ins_encode %{
8182 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8183 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8184 %}
8185 ins_pipe(pipe_class_default);
8186 %}
8187
8188 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8189 effect(USE_DEF dst, USE src1, USE crx);
8190 predicate(false);
8191
8192 ins_variable_size_depending_on_alignment(true);
8193
8194 format %{ "CMOVE $dst, neg($src1), $crx" %}
8195 // Worst case is branch + move + stop, no stop without scheduler.
8196 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8197 ins_encode %{
8198 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8199 Label done;
8200 __ bne($crx$$CondRegister, done);
8201 __ neg($dst$$Register, $src1$$Register);
8202 // TODO PPC port __ endgroup_if_needed(_size == 12);
8203 __ bind(done);
8204 %}
8205 ins_pipe(pipe_class_default);
8206 %}
8207
8208 // Long Division with Registers not containing constants.
8209 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8210 match(Set dst (DivL src1 src2));
8211 ins_cost(10*DEFAULT_COST);
8212
8213 expand %{
8214 immL16 imm %{ (int)-1 %}
8215 flagsReg tmp1;
8216 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8217 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8218 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8219 %}
8220 %}
8221
8222 // Integer Remainder with registers.
8223 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8224 match(Set dst (ModI src1 src2));
8225 ins_cost(10*DEFAULT_COST);
8226
8227 expand %{
8228 immI16 imm %{ (int)-1 %}
8229 flagsReg tmp1;
8230 iRegIdst tmp2;
8231 iRegIdst tmp3;
8232 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8233 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8234 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8235 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8236 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8237 %}
8238 %}
8239
8240 // Long Remainder with registers
8241 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8242 match(Set dst (ModL src1 src2));
8243 ins_cost(10*DEFAULT_COST);
8244
8245 expand %{
8246 immL16 imm %{ (int)-1 %}
8247 flagsReg tmp1;
8248 iRegLdst tmp2;
8249 iRegLdst tmp3;
8250 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8251 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8252 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8253 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8254 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8255 %}
8256 %}
8257
8258 // Integer Shift Instructions
8259
8260 // Register Shift Left
8261
8262 // Clear all but the lowest #mask bits.
8263 // Used to normalize shift amounts in registers.
8264 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8265 // no match-rule, false predicate
8266 effect(DEF dst, USE src, USE mask);
8267 predicate(false);
8268
8269 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8270 size(4);
8271 ins_encode %{
8272 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8273 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8274 %}
8275 ins_pipe(pipe_class_default);
8276 %}
8277
8278 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8279 // no match-rule, false predicate
8280 effect(DEF dst, USE src1, USE src2);
8281 predicate(false);
8282
8283 format %{ "SLW $dst, $src1, $src2" %}
8284 size(4);
8285 ins_encode %{
8286 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8287 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8288 %}
8289 ins_pipe(pipe_class_default);
8290 %}
8291
8292 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8293 match(Set dst (LShiftI src1 src2));
8294 ins_cost(DEFAULT_COST*2);
8295 expand %{
8296 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8297 iRegIdst tmpI;
8298 maskI_reg_imm(tmpI, src2, mask);
8299 lShiftI_reg_reg(dst, src1, tmpI);
8300 %}
8301 %}
8302
8303 // Register Shift Left Immediate
8304 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8305 match(Set dst (LShiftI src1 src2));
8306
8307 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8308 size(4);
8309 ins_encode %{
8310 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8311 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8312 %}
8313 ins_pipe(pipe_class_default);
8314 %}
8315
8316 // AndI with negpow2-constant + LShiftI
8317 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8318 match(Set dst (LShiftI (AndI src1 src2) src3));
8319 predicate(UseRotateAndMaskInstructionsPPC64);
8320
8321 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8322 size(4);
8323 ins_encode %{
8324 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8325 long src2 = $src2$$constant;
8326 long src3 = $src3$$constant;
8327 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8328 if (maskbits >= 32) {
8329 __ li($dst$$Register, 0); // addi
8330 } else {
8331 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8332 }
8333 %}
8334 ins_pipe(pipe_class_default);
8335 %}
8336
8337 // RShiftI + AndI with negpow2-constant + LShiftI
8338 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8339 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8340 predicate(UseRotateAndMaskInstructionsPPC64);
8341
8342 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8343 size(4);
8344 ins_encode %{
8345 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8346 long src2 = $src2$$constant;
8347 long src3 = $src3$$constant;
8348 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8349 if (maskbits >= 32) {
8350 __ li($dst$$Register, 0); // addi
8351 } else {
8352 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8353 }
8354 %}
8355 ins_pipe(pipe_class_default);
8356 %}
8357
8358 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8359 // no match-rule, false predicate
8360 effect(DEF dst, USE src1, USE src2);
8361 predicate(false);
8362
8363 format %{ "SLD $dst, $src1, $src2" %}
8364 size(4);
8365 ins_encode %{
8366 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8367 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8368 %}
8369 ins_pipe(pipe_class_default);
8370 %}
8371
8372 // Register Shift Left
8373 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8374 match(Set dst (LShiftL src1 src2));
8375 ins_cost(DEFAULT_COST*2);
8376 expand %{
8377 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8378 iRegIdst tmpI;
8379 maskI_reg_imm(tmpI, src2, mask);
8380 lShiftL_regL_regI(dst, src1, tmpI);
8381 %}
8382 %}
8383
8384 // Register Shift Left Immediate
8385 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8386 match(Set dst (LShiftL src1 src2));
8387 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8388 size(4);
8389 ins_encode %{
8390 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8391 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8392 %}
8393 ins_pipe(pipe_class_default);
8394 %}
8395
8396 // If we shift more than 32 bits, we need not convert I2L.
8397 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8398 match(Set dst (LShiftL (ConvI2L src1) src2));
8399 ins_cost(DEFAULT_COST);
8400
8401 size(4);
8402 format %{ "SLDI $dst, i2l($src1), $src2" %}
8403 ins_encode %{
8404 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8405 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8406 %}
8407 ins_pipe(pipe_class_default);
8408 %}
8409
8410 // Shift a postivie int to the left.
8411 // Clrlsldi clears the upper 32 bits and shifts.
8412 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8413 match(Set dst (LShiftL (ConvI2L src1) src2));
8414 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8415
8416 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8417 size(4);
8418 ins_encode %{
8419 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8420 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8421 %}
8422 ins_pipe(pipe_class_default);
8423 %}
8424
8425 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8426 // no match-rule, false predicate
8427 effect(DEF dst, USE src1, USE src2);
8428 predicate(false);
8429
8430 format %{ "SRAW $dst, $src1, $src2" %}
8431 size(4);
8432 ins_encode %{
8433 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8434 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8435 %}
8436 ins_pipe(pipe_class_default);
8437 %}
8438
8439 // Register Arithmetic Shift Right
8440 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8441 match(Set dst (RShiftI src1 src2));
8442 ins_cost(DEFAULT_COST*2);
8443 expand %{
8444 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8445 iRegIdst tmpI;
8446 maskI_reg_imm(tmpI, src2, mask);
8447 arShiftI_reg_reg(dst, src1, tmpI);
8448 %}
8449 %}
8450
8451 // Register Arithmetic Shift Right Immediate
8452 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8453 match(Set dst (RShiftI src1 src2));
8454
8455 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8456 size(4);
8457 ins_encode %{
8458 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8459 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8460 %}
8461 ins_pipe(pipe_class_default);
8462 %}
8463
8464 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8465 // no match-rule, false predicate
8466 effect(DEF dst, USE src1, USE src2);
8467 predicate(false);
8468
8469 format %{ "SRAD $dst, $src1, $src2" %}
8470 size(4);
8471 ins_encode %{
8472 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8473 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8474 %}
8475 ins_pipe(pipe_class_default);
8476 %}
8477
8478 // Register Shift Right Arithmetic Long
8479 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8480 match(Set dst (RShiftL src1 src2));
8481 ins_cost(DEFAULT_COST*2);
8482
8483 expand %{
8484 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8485 iRegIdst tmpI;
8486 maskI_reg_imm(tmpI, src2, mask);
8487 arShiftL_regL_regI(dst, src1, tmpI);
8488 %}
8489 %}
8490
8491 // Register Shift Right Immediate
8492 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8493 match(Set dst (RShiftL src1 src2));
8494
8495 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8496 size(4);
8497 ins_encode %{
8498 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8499 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8500 %}
8501 ins_pipe(pipe_class_default);
8502 %}
8503
8504 // RShiftL + ConvL2I
8505 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8506 match(Set dst (ConvL2I (RShiftL src1 src2)));
8507
8508 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8509 size(4);
8510 ins_encode %{
8511 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8512 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8513 %}
8514 ins_pipe(pipe_class_default);
8515 %}
8516
8517 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8518 // no match-rule, false predicate
8519 effect(DEF dst, USE src1, USE src2);
8520 predicate(false);
8521
8522 format %{ "SRW $dst, $src1, $src2" %}
8523 size(4);
8524 ins_encode %{
8525 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8526 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8527 %}
8528 ins_pipe(pipe_class_default);
8529 %}
8530
8531 // Register Shift Right
8532 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8533 match(Set dst (URShiftI src1 src2));
8534 ins_cost(DEFAULT_COST*2);
8535
8536 expand %{
8537 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8538 iRegIdst tmpI;
8539 maskI_reg_imm(tmpI, src2, mask);
8540 urShiftI_reg_reg(dst, src1, tmpI);
8541 %}
8542 %}
8543
8544 // Register Shift Right Immediate
8545 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8546 match(Set dst (URShiftI src1 src2));
8547
8548 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8549 size(4);
8550 ins_encode %{
8551 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8552 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8553 %}
8554 ins_pipe(pipe_class_default);
8555 %}
8556
8557 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8558 // no match-rule, false predicate
8559 effect(DEF dst, USE src1, USE src2);
8560 predicate(false);
8561
8562 format %{ "SRD $dst, $src1, $src2" %}
8563 size(4);
8564 ins_encode %{
8565 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8566 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8567 %}
8568 ins_pipe(pipe_class_default);
8569 %}
8570
8571 // Register Shift Right
8572 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8573 match(Set dst (URShiftL src1 src2));
8574 ins_cost(DEFAULT_COST*2);
8575
8576 expand %{
8577 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8578 iRegIdst tmpI;
8579 maskI_reg_imm(tmpI, src2, mask);
8580 urShiftL_regL_regI(dst, src1, tmpI);
8581 %}
8582 %}
8583
8584 // Register Shift Right Immediate
8585 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8586 match(Set dst (URShiftL src1 src2));
8587
8588 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8589 size(4);
8590 ins_encode %{
8591 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8592 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8593 %}
8594 ins_pipe(pipe_class_default);
8595 %}
8596
8597 // URShiftL + ConvL2I.
8598 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8599 match(Set dst (ConvL2I (URShiftL src1 src2)));
8600
8601 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8602 size(4);
8603 ins_encode %{
8604 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8605 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8606 %}
8607 ins_pipe(pipe_class_default);
8608 %}
8609
8610 // Register Shift Right Immediate with a CastP2X
8611 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8612 match(Set dst (URShiftL (CastP2X src1) src2));
8613
8614 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8615 size(4);
8616 ins_encode %{
8617 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8618 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8619 %}
8620 ins_pipe(pipe_class_default);
8621 %}
8622
8623 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8624 match(Set dst (ConvL2I (ConvI2L src)));
8625
8626 format %{ "EXTSW $dst, $src \t// int->int" %}
8627 size(4);
8628 ins_encode %{
8629 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8630 __ extsw($dst$$Register, $src$$Register);
8631 %}
8632 ins_pipe(pipe_class_default);
8633 %}
8634
8635 //----------Rotate Instructions------------------------------------------------
8636
8637 // Rotate Left by 8-bit immediate
8638 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8639 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8640 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8641
8642 format %{ "ROTLWI $dst, $src, $lshift" %}
8643 size(4);
8644 ins_encode %{
8645 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8646 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8647 %}
8648 ins_pipe(pipe_class_default);
8649 %}
8650
8651 // Rotate Right by 8-bit immediate
8652 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8653 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8654 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8655
8656 format %{ "ROTRWI $dst, $rshift" %}
8657 size(4);
8658 ins_encode %{
8659 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8660 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8661 %}
8662 ins_pipe(pipe_class_default);
8663 %}
8664
8665 //----------Floating Point Arithmetic Instructions-----------------------------
8666
8667 // Add float single precision
8668 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8669 match(Set dst (AddF src1 src2));
8670
8671 format %{ "FADDS $dst, $src1, $src2" %}
8672 size(4);
8673 ins_encode %{
8674 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8675 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8676 %}
8677 ins_pipe(pipe_class_default);
8678 %}
8679
8680 // Add float double precision
8681 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8682 match(Set dst (AddD src1 src2));
8683
8684 format %{ "FADD $dst, $src1, $src2" %}
8685 size(4);
8686 ins_encode %{
8687 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8688 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8689 %}
8690 ins_pipe(pipe_class_default);
8691 %}
8692
8693 // Sub float single precision
8694 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8695 match(Set dst (SubF src1 src2));
8696
8697 format %{ "FSUBS $dst, $src1, $src2" %}
8698 size(4);
8699 ins_encode %{
8700 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8701 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8702 %}
8703 ins_pipe(pipe_class_default);
8704 %}
8705
8706 // Sub float double precision
8707 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8708 match(Set dst (SubD src1 src2));
8709 format %{ "FSUB $dst, $src1, $src2" %}
8710 size(4);
8711 ins_encode %{
8712 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8713 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8714 %}
8715 ins_pipe(pipe_class_default);
8716 %}
8717
8718 // Mul float single precision
8719 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8720 match(Set dst (MulF src1 src2));
8721 format %{ "FMULS $dst, $src1, $src2" %}
8722 size(4);
8723 ins_encode %{
8724 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8725 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8726 %}
8727 ins_pipe(pipe_class_default);
8728 %}
8729
8730 // Mul float double precision
8731 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8732 match(Set dst (MulD src1 src2));
8733 format %{ "FMUL $dst, $src1, $src2" %}
8734 size(4);
8735 ins_encode %{
8736 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8737 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8738 %}
8739 ins_pipe(pipe_class_default);
8740 %}
8741
8742 // Div float single precision
8743 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8744 match(Set dst (DivF src1 src2));
8745 format %{ "FDIVS $dst, $src1, $src2" %}
8746 size(4);
8747 ins_encode %{
8748 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8749 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8750 %}
8751 ins_pipe(pipe_class_default);
8752 %}
8753
8754 // Div float double precision
8755 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8756 match(Set dst (DivD src1 src2));
8757 format %{ "FDIV $dst, $src1, $src2" %}
8758 size(4);
8759 ins_encode %{
8760 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8761 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8762 %}
8763 ins_pipe(pipe_class_default);
8764 %}
8765
8766 // Absolute float single precision
8767 instruct absF_reg(regF dst, regF src) %{
8768 match(Set dst (AbsF src));
8769 format %{ "FABS $dst, $src \t// float" %}
8770 size(4);
8771 ins_encode %{
8772 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8773 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8774 %}
8775 ins_pipe(pipe_class_default);
8776 %}
8777
8778 // Absolute float double precision
8779 instruct absD_reg(regD dst, regD src) %{
8780 match(Set dst (AbsD src));
8781 format %{ "FABS $dst, $src \t// double" %}
8782 size(4);
8783 ins_encode %{
8784 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8785 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8786 %}
8787 ins_pipe(pipe_class_default);
8788 %}
8789
8790 instruct negF_reg(regF dst, regF src) %{
8791 match(Set dst (NegF src));
8792 format %{ "FNEG $dst, $src \t// float" %}
8793 size(4);
8794 ins_encode %{
8795 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8796 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8797 %}
8798 ins_pipe(pipe_class_default);
8799 %}
8800
8801 instruct negD_reg(regD dst, regD src) %{
8802 match(Set dst (NegD src));
8803 format %{ "FNEG $dst, $src \t// double" %}
8804 size(4);
8805 ins_encode %{
8806 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8807 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8808 %}
8809 ins_pipe(pipe_class_default);
8810 %}
8811
8812 // AbsF + NegF.
8813 instruct negF_absF_reg(regF dst, regF src) %{
8814 match(Set dst (NegF (AbsF src)));
8815 format %{ "FNABS $dst, $src \t// float" %}
8816 size(4);
8817 ins_encode %{
8818 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8819 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8820 %}
8821 ins_pipe(pipe_class_default);
8822 %}
8823
8824 // AbsD + NegD.
8825 instruct negD_absD_reg(regD dst, regD src) %{
8826 match(Set dst (NegD (AbsD src)));
8827 format %{ "FNABS $dst, $src \t// double" %}
8828 size(4);
8829 ins_encode %{
8830 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8831 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8832 %}
8833 ins_pipe(pipe_class_default);
8834 %}
8835
8836 // VM_Version::has_fsqrt() decides if this node will be used.
8837 // Sqrt float double precision
8838 instruct sqrtD_reg(regD dst, regD src) %{
8839 match(Set dst (SqrtD src));
8840 format %{ "FSQRT $dst, $src" %}
8841 size(4);
8842 ins_encode %{
8843 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8844 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8845 %}
8846 ins_pipe(pipe_class_default);
8847 %}
8848
8849 // Single-precision sqrt.
8850 instruct sqrtF_reg(regF dst, regF src) %{
8851 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8852 predicate(VM_Version::has_fsqrts());
8853 ins_cost(DEFAULT_COST);
8854
8855 format %{ "FSQRTS $dst, $src" %}
8856 size(4);
8857 ins_encode %{
8858 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8859 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8860 %}
8861 ins_pipe(pipe_class_default);
8862 %}
8863
8864 instruct roundDouble_nop(regD dst) %{
8865 match(Set dst (RoundDouble dst));
8866 ins_cost(0);
8867
8868 format %{ " -- \t// RoundDouble not needed - empty" %}
8869 size(0);
8870 // PPC results are already "rounded" (i.e., normal-format IEEE).
8871 ins_encode( /*empty*/ );
8872 ins_pipe(pipe_class_default);
8873 %}
8874
8875 instruct roundFloat_nop(regF dst) %{
8876 match(Set dst (RoundFloat dst));
8877 ins_cost(0);
8878
8879 format %{ " -- \t// RoundFloat not needed - empty" %}
8880 size(0);
8881 // PPC results are already "rounded" (i.e., normal-format IEEE).
8882 ins_encode( /*empty*/ );
8883 ins_pipe(pipe_class_default);
8884 %}
8885
8886 //----------Logical Instructions-----------------------------------------------
8887
8888 // And Instructions
8889
8890 // Register And
8891 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8892 match(Set dst (AndI src1 src2));
8893 format %{ "AND $dst, $src1, $src2" %}
8894 size(4);
8895 ins_encode %{
8896 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8897 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8898 %}
8899 ins_pipe(pipe_class_default);
8900 %}
8901
8902 // Immediate And
8903 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8904 match(Set dst (AndI src1 src2));
8905 effect(KILL cr0);
8906
8907 format %{ "ANDI $dst, $src1, $src2" %}
8908 size(4);
8909 ins_encode %{
8910 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8911 // FIXME: avoid andi_ ?
8912 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8913 %}
8914 ins_pipe(pipe_class_default);
8915 %}
8916
8917 // Immediate And where the immediate is a negative power of 2.
8918 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8919 match(Set dst (AndI src1 src2));
8920 format %{ "ANDWI $dst, $src1, $src2" %}
8921 size(4);
8922 ins_encode %{
8923 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8924 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8925 %}
8926 ins_pipe(pipe_class_default);
8927 %}
8928
8929 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8930 match(Set dst (AndI src1 src2));
8931 format %{ "ANDWI $dst, $src1, $src2" %}
8932 size(4);
8933 ins_encode %{
8934 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8935 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8936 %}
8937 ins_pipe(pipe_class_default);
8938 %}
8939
8940 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8941 match(Set dst (AndI src1 src2));
8942 predicate(UseRotateAndMaskInstructionsPPC64);
8943 format %{ "ANDWI $dst, $src1, $src2" %}
8944 size(4);
8945 ins_encode %{
8946 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8947 __ rlwinm($dst$$Register, $src1$$Register, 0,
8948 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8949 %}
8950 ins_pipe(pipe_class_default);
8951 %}
8952
8953 // Register And Long
8954 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8955 match(Set dst (AndL src1 src2));
8956 ins_cost(DEFAULT_COST);
8957
8958 format %{ "AND $dst, $src1, $src2 \t// long" %}
8959 size(4);
8960 ins_encode %{
8961 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8962 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8963 %}
8964 ins_pipe(pipe_class_default);
8965 %}
8966
8967 // Immediate And long
8968 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8969 match(Set dst (AndL src1 src2));
8970 effect(KILL cr0);
8971
8972 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8973 size(4);
8974 ins_encode %{
8975 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8976 // FIXME: avoid andi_ ?
8977 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8978 %}
8979 ins_pipe(pipe_class_default);
8980 %}
8981
8982 // Immediate And Long where the immediate is a negative power of 2.
8983 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8984 match(Set dst (AndL src1 src2));
8985 format %{ "ANDDI $dst, $src1, $src2" %}
8986 size(4);
8987 ins_encode %{
8988 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8989 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8990 %}
8991 ins_pipe(pipe_class_default);
8992 %}
8993
8994 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8995 match(Set dst (AndL src1 src2));
8996 format %{ "ANDDI $dst, $src1, $src2" %}
8997 size(4);
8998 ins_encode %{
8999 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9000 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9001 %}
9002 ins_pipe(pipe_class_default);
9003 %}
9004
9005 // AndL + ConvL2I.
9006 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9007 match(Set dst (ConvL2I (AndL src1 src2)));
9008 ins_cost(DEFAULT_COST);
9009
9010 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
9011 size(4);
9012 ins_encode %{
9013 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9014 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9015 %}
9016 ins_pipe(pipe_class_default);
9017 %}
9018
9019 // Or Instructions
9020
9021 // Register Or
9022 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9023 match(Set dst (OrI src1 src2));
9024 format %{ "OR $dst, $src1, $src2" %}
9025 size(4);
9026 ins_encode %{
9027 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9028 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9029 %}
9030 ins_pipe(pipe_class_default);
9031 %}
9032
9033 // Expand does not work with above instruct. (??)
9034 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9035 // no match-rule
9036 effect(DEF dst, USE src1, USE src2);
9037 format %{ "OR $dst, $src1, $src2" %}
9038 size(4);
9039 ins_encode %{
9040 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9041 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9042 %}
9043 ins_pipe(pipe_class_default);
9044 %}
9045
9046 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9047 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9048 ins_cost(DEFAULT_COST*3);
9049
9050 expand %{
9051 // FIXME: we should do this in the ideal world.
9052 iRegIdst tmp1;
9053 iRegIdst tmp2;
9054 orI_reg_reg(tmp1, src1, src2);
9055 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9056 orI_reg_reg(dst, tmp1, tmp2);
9057 %}
9058 %}
9059
9060 // Immediate Or
9061 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9062 match(Set dst (OrI src1 src2));
9063 format %{ "ORI $dst, $src1, $src2" %}
9064 size(4);
9065 ins_encode %{
9066 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9067 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9068 %}
9069 ins_pipe(pipe_class_default);
9070 %}
9071
9072 // Register Or Long
9073 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9074 match(Set dst (OrL src1 src2));
9075 ins_cost(DEFAULT_COST);
9076
9077 size(4);
9078 format %{ "OR $dst, $src1, $src2 \t// long" %}
9079 ins_encode %{
9080 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9081 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9082 %}
9083 ins_pipe(pipe_class_default);
9084 %}
9085
9086 // OrL + ConvL2I.
9087 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9088 match(Set dst (ConvL2I (OrL src1 src2)));
9089 ins_cost(DEFAULT_COST);
9090
9091 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9092 size(4);
9093 ins_encode %{
9094 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9095 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9096 %}
9097 ins_pipe(pipe_class_default);
9098 %}
9099
9100 // Immediate Or long
9101 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9102 match(Set dst (OrL src1 con));
9103 ins_cost(DEFAULT_COST);
9104
9105 format %{ "ORI $dst, $src1, $con \t// long" %}
9106 size(4);
9107 ins_encode %{
9108 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9109 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9110 %}
9111 ins_pipe(pipe_class_default);
9112 %}
9113
9114 // Xor Instructions
9115
9116 // Register Xor
9117 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9118 match(Set dst (XorI src1 src2));
9119 format %{ "XOR $dst, $src1, $src2" %}
9120 size(4);
9121 ins_encode %{
9122 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9123 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9124 %}
9125 ins_pipe(pipe_class_default);
9126 %}
9127
9128 // Expand does not work with above instruct. (??)
9129 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9130 // no match-rule
9131 effect(DEF dst, USE src1, USE src2);
9132 format %{ "XOR $dst, $src1, $src2" %}
9133 size(4);
9134 ins_encode %{
9135 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9136 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9137 %}
9138 ins_pipe(pipe_class_default);
9139 %}
9140
9141 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9142 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9143 ins_cost(DEFAULT_COST*3);
9144
9145 expand %{
9146 // FIXME: we should do this in the ideal world.
9147 iRegIdst tmp1;
9148 iRegIdst tmp2;
9149 xorI_reg_reg(tmp1, src1, src2);
9150 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9151 xorI_reg_reg(dst, tmp1, tmp2);
9152 %}
9153 %}
9154
9155 // Immediate Xor
9156 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9157 match(Set dst (XorI src1 src2));
9158 format %{ "XORI $dst, $src1, $src2" %}
9159 size(4);
9160 ins_encode %{
9161 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9162 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9163 %}
9164 ins_pipe(pipe_class_default);
9165 %}
9166
9167 // Register Xor Long
9168 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9169 match(Set dst (XorL src1 src2));
9170 ins_cost(DEFAULT_COST);
9171
9172 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9173 size(4);
9174 ins_encode %{
9175 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9176 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9177 %}
9178 ins_pipe(pipe_class_default);
9179 %}
9180
9181 // XorL + ConvL2I.
9182 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9183 match(Set dst (ConvL2I (XorL src1 src2)));
9184 ins_cost(DEFAULT_COST);
9185
9186 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9187 size(4);
9188 ins_encode %{
9189 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9190 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9191 %}
9192 ins_pipe(pipe_class_default);
9193 %}
9194
9195 // Immediate Xor Long
9196 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9197 match(Set dst (XorL src1 src2));
9198 ins_cost(DEFAULT_COST);
9199
9200 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9201 size(4);
9202 ins_encode %{
9203 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9204 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9205 %}
9206 ins_pipe(pipe_class_default);
9207 %}
9208
9209 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9210 match(Set dst (XorI src1 src2));
9211 ins_cost(DEFAULT_COST);
9212
9213 format %{ "NOT $dst, $src1 ($src2)" %}
9214 size(4);
9215 ins_encode %{
9216 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9217 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9218 %}
9219 ins_pipe(pipe_class_default);
9220 %}
9221
9222 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9223 match(Set dst (XorL src1 src2));
9224 ins_cost(DEFAULT_COST);
9225
9226 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9227 size(4);
9228 ins_encode %{
9229 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9230 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9231 %}
9232 ins_pipe(pipe_class_default);
9233 %}
9234
9235 // And-complement
9236 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9237 match(Set dst (AndI (XorI src1 src2) src3));
9238 ins_cost(DEFAULT_COST);
9239
9240 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9241 size(4);
9242 ins_encode( enc_andc(dst, src3, src1) );
9243 ins_pipe(pipe_class_default);
9244 %}
9245
9246 // And-complement
9247 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9248 // no match-rule, false predicate
9249 effect(DEF dst, USE src1, USE src2);
9250 predicate(false);
9251
9252 format %{ "ANDC $dst, $src1, $src2" %}
9253 size(4);
9254 ins_encode %{
9255 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9256 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9257 %}
9258 ins_pipe(pipe_class_default);
9259 %}
9260
9261 //----------Moves between int/long and float/double----------------------------
9262 //
9263 // The following rules move values from int/long registers/stack-locations
9264 // to float/double registers/stack-locations and vice versa, without doing any
9265 // conversions. These rules are used to implement the bit-conversion methods
9266 // of java.lang.Float etc., e.g.
9267 // int floatToIntBits(float value)
9268 // float intBitsToFloat(int bits)
9269 //
9270 // Notes on the implementation on ppc64:
9271 // We only provide rules which move between a register and a stack-location,
9272 // because we always have to go through memory when moving between a float
9273 // register and an integer register.
9274
9275 //---------- Chain stack slots between similar types --------
9276
9277 // These are needed so that the rules below can match.
9278
9279 // Load integer from stack slot
9280 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9281 match(Set dst src);
9282 ins_cost(MEMORY_REF_COST);
9283
9284 format %{ "LWZ $dst, $src" %}
9285 size(4);
9286 ins_encode( enc_lwz(dst, src) );
9287 ins_pipe(pipe_class_memory);
9288 %}
9289
9290 // Store integer to stack slot
9291 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9292 match(Set dst src);
9293 ins_cost(MEMORY_REF_COST);
9294
9295 format %{ "STW $src, $dst \t// stk" %}
9296 size(4);
9297 ins_encode( enc_stw(src, dst) ); // rs=rt
9298 ins_pipe(pipe_class_memory);
9299 %}
9300
9301 // Load long from stack slot
9302 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9303 match(Set dst src);
9304 ins_cost(MEMORY_REF_COST);
9305
9306 format %{ "LD $dst, $src \t// long" %}
9307 size(4);
9308 ins_encode( enc_ld(dst, src) );
9309 ins_pipe(pipe_class_memory);
9310 %}
9311
9312 // Store long to stack slot
9313 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9314 match(Set dst src);
9315 ins_cost(MEMORY_REF_COST);
9316
9317 format %{ "STD $src, $dst \t// long" %}
9318 size(4);
9319 ins_encode( enc_std(src, dst) ); // rs=rt
9320 ins_pipe(pipe_class_memory);
9321 %}
9322
9323 //----------Moves between int and float
9324
9325 // Move float value from float stack-location to integer register.
9326 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9327 match(Set dst (MoveF2I src));
9328 ins_cost(MEMORY_REF_COST);
9329
9330 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9331 size(4);
9332 ins_encode( enc_lwz(dst, src) );
9333 ins_pipe(pipe_class_memory);
9334 %}
9335
9336 // Move float value from float register to integer stack-location.
9337 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9338 match(Set dst (MoveF2I src));
9339 ins_cost(MEMORY_REF_COST);
9340
9341 format %{ "STFS $src, $dst \t// MoveF2I" %}
9342 size(4);
9343 ins_encode( enc_stfs(src, dst) );
9344 ins_pipe(pipe_class_memory);
9345 %}
9346
9347 // Move integer value from integer stack-location to float register.
9348 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9349 match(Set dst (MoveI2F src));
9350 ins_cost(MEMORY_REF_COST);
9351
9352 format %{ "LFS $dst, $src \t// MoveI2F" %}
9353 size(4);
9354 ins_encode %{
9355 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9356 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9357 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9358 %}
9359 ins_pipe(pipe_class_memory);
9360 %}
9361
9362 // Move integer value from integer register to float stack-location.
9363 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9364 match(Set dst (MoveI2F src));
9365 ins_cost(MEMORY_REF_COST);
9366
9367 format %{ "STW $src, $dst \t// MoveI2F" %}
9368 size(4);
9369 ins_encode( enc_stw(src, dst) );
9370 ins_pipe(pipe_class_memory);
9371 %}
9372
9373 //----------Moves between long and float
9374
9375 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9376 // no match-rule, false predicate
9377 effect(DEF dst, USE src);
9378 predicate(false);
9379
9380 format %{ "storeD $src, $dst \t// STACK" %}
9381 size(4);
9382 ins_encode( enc_stfd(src, dst) );
9383 ins_pipe(pipe_class_default);
9384 %}
9385
9386 //----------Moves between long and double
9387
9388 // Move double value from double stack-location to long register.
9389 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9390 match(Set dst (MoveD2L src));
9391 ins_cost(MEMORY_REF_COST);
9392 size(4);
9393 format %{ "LD $dst, $src \t// MoveD2L" %}
9394 ins_encode( enc_ld(dst, src) );
9395 ins_pipe(pipe_class_memory);
9396 %}
9397
9398 // Move double value from double register to long stack-location.
9399 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9400 match(Set dst (MoveD2L src));
9401 effect(DEF dst, USE src);
9402 ins_cost(MEMORY_REF_COST);
9403
9404 format %{ "STFD $src, $dst \t// MoveD2L" %}
9405 size(4);
9406 ins_encode( enc_stfd(src, dst) );
9407 ins_pipe(pipe_class_memory);
9408 %}
9409
9410 // Move long value from long stack-location to double register.
9411 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9412 match(Set dst (MoveL2D src));
9413 ins_cost(MEMORY_REF_COST);
9414
9415 format %{ "LFD $dst, $src \t// MoveL2D" %}
9416 size(4);
9417 ins_encode( enc_lfd(dst, src) );
9418 ins_pipe(pipe_class_memory);
9419 %}
9420
9421 // Move long value from long register to double stack-location.
9422 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9423 match(Set dst (MoveL2D src));
9424 ins_cost(MEMORY_REF_COST);
9425
9426 format %{ "STD $src, $dst \t// MoveL2D" %}
9427 size(4);
9428 ins_encode( enc_std(src, dst) );
9429 ins_pipe(pipe_class_memory);
9430 %}
9431
9432 //----------Register Move Instructions-----------------------------------------
9433
9434 // Replicate for Superword
9435
9436 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9437 predicate(false);
9438 effect(DEF dst, USE src);
9439
9440 format %{ "MR $dst, $src \t// replicate " %}
9441 // variable size, 0 or 4.
9442 ins_encode %{
9443 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9444 __ mr_if_needed($dst$$Register, $src$$Register);
9445 %}
9446 ins_pipe(pipe_class_default);
9447 %}
9448
9449 //----------Cast instructions (Java-level type cast)---------------------------
9450
9451 // Cast Long to Pointer for unsafe natives.
9452 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9453 match(Set dst (CastX2P src));
9454
9455 format %{ "MR $dst, $src \t// Long->Ptr" %}
9456 // variable size, 0 or 4.
9457 ins_encode %{
9458 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9459 __ mr_if_needed($dst$$Register, $src$$Register);
9460 %}
9461 ins_pipe(pipe_class_default);
9462 %}
9463
9464 // Cast Pointer to Long for unsafe natives.
9465 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9466 match(Set dst (CastP2X src));
9467
9468 format %{ "MR $dst, $src \t// Ptr->Long" %}
9469 // variable size, 0 or 4.
9470 ins_encode %{
9471 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9472 __ mr_if_needed($dst$$Register, $src$$Register);
9473 %}
9474 ins_pipe(pipe_class_default);
9475 %}
9476
9477 instruct castPP(iRegPdst dst) %{
9478 match(Set dst (CastPP dst));
9479 format %{ " -- \t// castPP of $dst" %}
9480 size(0);
9481 ins_encode( /*empty*/ );
9482 ins_pipe(pipe_class_default);
9483 %}
9484
9485 instruct castII(iRegIdst dst) %{
9486 match(Set dst (CastII dst));
9487 format %{ " -- \t// castII of $dst" %}
9488 size(0);
9489 ins_encode( /*empty*/ );
9490 ins_pipe(pipe_class_default);
9491 %}
9492
9493 instruct checkCastPP(iRegPdst dst) %{
9494 match(Set dst (CheckCastPP dst));
9495 format %{ " -- \t// checkcastPP of $dst" %}
9496 size(0);
9497 ins_encode( /*empty*/ );
9498 ins_pipe(pipe_class_default);
9499 %}
9500
9501 //----------Convert instructions-----------------------------------------------
9502
9503 // Convert to boolean.
9504
9505 // int_to_bool(src) : { 1 if src != 0
9506 // { 0 else
9507 //
9508 // strategy:
9509 // 1) Count leading zeros of 32 bit-value src,
9510 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9511 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9512 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9513
9514 // convI2Bool
9515 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9516 match(Set dst (Conv2B src));
9517 predicate(UseCountLeadingZerosInstructionsPPC64);
9518 ins_cost(DEFAULT_COST);
9519
9520 expand %{
9521 immI shiftAmount %{ 0x5 %}
9522 uimmI16 mask %{ 0x1 %}
9523 iRegIdst tmp1;
9524 iRegIdst tmp2;
9525 countLeadingZerosI(tmp1, src);
9526 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9527 xorI_reg_uimm16(dst, tmp2, mask);
9528 %}
9529 %}
9530
9531 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9532 match(Set dst (Conv2B src));
9533 effect(TEMP crx);
9534 predicate(!UseCountLeadingZerosInstructionsPPC64);
9535 ins_cost(DEFAULT_COST);
9536
9537 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9538 "LI $dst, #0\n\t"
9539 "BEQ $crx, done\n\t"
9540 "LI $dst, #1\n"
9541 "done:" %}
9542 size(16);
9543 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9544 ins_pipe(pipe_class_compare);
9545 %}
9546
9547 // ConvI2B + XorI
9548 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9549 match(Set dst (XorI (Conv2B src) mask));
9550 predicate(UseCountLeadingZerosInstructionsPPC64);
9551 ins_cost(DEFAULT_COST);
9552
9553 expand %{
9554 immI shiftAmount %{ 0x5 %}
9555 iRegIdst tmp1;
9556 countLeadingZerosI(tmp1, src);
9557 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9558 %}
9559 %}
9560
9561 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9562 match(Set dst (XorI (Conv2B src) mask));
9563 effect(TEMP crx);
9564 predicate(!UseCountLeadingZerosInstructionsPPC64);
9565 ins_cost(DEFAULT_COST);
9566
9567 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9568 "LI $dst, #1\n\t"
9569 "BEQ $crx, done\n\t"
9570 "LI $dst, #0\n"
9571 "done:" %}
9572 size(16);
9573 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9574 ins_pipe(pipe_class_compare);
9575 %}
9576
9577 // AndI 0b0..010..0 + ConvI2B
9578 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9579 match(Set dst (Conv2B (AndI src mask)));
9580 predicate(UseRotateAndMaskInstructionsPPC64);
9581 ins_cost(DEFAULT_COST);
9582
9583 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9584 size(4);
9585 ins_encode %{
9586 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9587 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9588 %}
9589 ins_pipe(pipe_class_default);
9590 %}
9591
9592 // Convert pointer to boolean.
9593 //
9594 // ptr_to_bool(src) : { 1 if src != 0
9595 // { 0 else
9596 //
9597 // strategy:
9598 // 1) Count leading zeros of 64 bit-value src,
9599 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9600 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9601 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9602
9603 // ConvP2B
9604 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9605 match(Set dst (Conv2B src));
9606 predicate(UseCountLeadingZerosInstructionsPPC64);
9607 ins_cost(DEFAULT_COST);
9608
9609 expand %{
9610 immI shiftAmount %{ 0x6 %}
9611 uimmI16 mask %{ 0x1 %}
9612 iRegIdst tmp1;
9613 iRegIdst tmp2;
9614 countLeadingZerosP(tmp1, src);
9615 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9616 xorI_reg_uimm16(dst, tmp2, mask);
9617 %}
9618 %}
9619
9620 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9621 match(Set dst (Conv2B src));
9622 effect(TEMP crx);
9623 predicate(!UseCountLeadingZerosInstructionsPPC64);
9624 ins_cost(DEFAULT_COST);
9625
9626 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9627 "LI $dst, #0\n\t"
9628 "BEQ $crx, done\n\t"
9629 "LI $dst, #1\n"
9630 "done:" %}
9631 size(16);
9632 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9633 ins_pipe(pipe_class_compare);
9634 %}
9635
9636 // ConvP2B + XorI
9637 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9638 match(Set dst (XorI (Conv2B src) mask));
9639 predicate(UseCountLeadingZerosInstructionsPPC64);
9640 ins_cost(DEFAULT_COST);
9641
9642 expand %{
9643 immI shiftAmount %{ 0x6 %}
9644 iRegIdst tmp1;
9645 countLeadingZerosP(tmp1, src);
9646 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9647 %}
9648 %}
9649
9650 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9651 match(Set dst (XorI (Conv2B src) mask));
9652 effect(TEMP crx);
9653 predicate(!UseCountLeadingZerosInstructionsPPC64);
9654 ins_cost(DEFAULT_COST);
9655
9656 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9657 "LI $dst, #1\n\t"
9658 "BEQ $crx, done\n\t"
9659 "LI $dst, #0\n"
9660 "done:" %}
9661 size(16);
9662 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9663 ins_pipe(pipe_class_compare);
9664 %}
9665
9666 // if src1 < src2, return -1 else return 0
9667 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9668 match(Set dst (CmpLTMask src1 src2));
9669 ins_cost(DEFAULT_COST*4);
9670
9671 expand %{
9672 iRegLdst src1s;
9673 iRegLdst src2s;
9674 iRegLdst diff;
9675 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9676 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9677 subL_reg_reg(diff, src1s, src2s);
9678 // Need to consider >=33 bit result, therefore we need signmaskL.
9679 signmask64I_regL(dst, diff);
9680 %}
9681 %}
9682
9683 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9684 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9685 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9686 size(4);
9687 ins_encode %{
9688 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9689 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9690 %}
9691 ins_pipe(pipe_class_default);
9692 %}
9693
9694 //----------Arithmetic Conversion Instructions---------------------------------
9695
9696 // Convert to Byte -- nop
9697 // Convert to Short -- nop
9698
9699 // Convert to Int
9700
9701 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9702 match(Set dst (RShiftI (LShiftI src amount) amount));
9703 format %{ "EXTSB $dst, $src \t// byte->int" %}
9704 size(4);
9705 ins_encode %{
9706 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9707 __ extsb($dst$$Register, $src$$Register);
9708 %}
9709 ins_pipe(pipe_class_default);
9710 %}
9711
9712 // LShiftI 16 + RShiftI 16 converts short to int.
9713 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9714 match(Set dst (RShiftI (LShiftI src amount) amount));
9715 format %{ "EXTSH $dst, $src \t// short->int" %}
9716 size(4);
9717 ins_encode %{
9718 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9719 __ extsh($dst$$Register, $src$$Register);
9720 %}
9721 ins_pipe(pipe_class_default);
9722 %}
9723
9724 // ConvL2I + ConvI2L: Sign extend int in long register.
9725 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9726 match(Set dst (ConvI2L (ConvL2I src)));
9727
9728 format %{ "EXTSW $dst, $src \t// long->long" %}
9729 size(4);
9730 ins_encode %{
9731 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9732 __ extsw($dst$$Register, $src$$Register);
9733 %}
9734 ins_pipe(pipe_class_default);
9735 %}
9736
9737 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9738 match(Set dst (ConvL2I src));
9739 format %{ "MR $dst, $src \t// long->int" %}
9740 // variable size, 0 or 4
9741 ins_encode %{
9742 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9743 __ mr_if_needed($dst$$Register, $src$$Register);
9744 %}
9745 ins_pipe(pipe_class_default);
9746 %}
9747
9748 instruct convD2IRaw_regD(regD dst, regD src) %{
9749 // no match-rule, false predicate
9750 effect(DEF dst, USE src);
9751 predicate(false);
9752
9753 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9754 size(4);
9755 ins_encode %{
9756 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9757 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9758 %}
9759 ins_pipe(pipe_class_default);
9760 %}
9761
9762 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9763 // no match-rule, false predicate
9764 effect(DEF dst, USE crx, USE src);
9765 predicate(false);
9766
9767 ins_variable_size_depending_on_alignment(true);
9768
9769 format %{ "cmovI $crx, $dst, $src" %}
9770 // Worst case is branch + move + stop, no stop without scheduler.
9771 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9772 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9773 ins_pipe(pipe_class_default);
9774 %}
9775
9776 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9777 // no match-rule, false predicate
9778 effect(DEF dst, USE crx, USE mem);
9779 predicate(false);
9780
9781 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9782 postalloc_expand %{
9783 //
9784 // replaces
9785 //
9786 // region dst crx mem
9787 // \ | | /
9788 // dst=cmovI_bso_stackSlotL_conLvalue0
9789 //
9790 // with
9791 //
9792 // region dst
9793 // \ /
9794 // dst=loadConI16(0)
9795 // |
9796 // ^ region dst crx mem
9797 // | \ | | /
9798 // dst=cmovI_bso_stackSlotL
9799 //
9800
9801 // Create new nodes.
9802 MachNode *m1 = new loadConI16Node();
9803 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9804
9805 // inputs for new nodes
9806 m1->add_req(n_region);
9807 m2->add_req(n_region, n_crx, n_mem);
9808
9809 // precedences for new nodes
9810 m2->add_prec(m1);
9811
9812 // operands for new nodes
9813 m1->_opnds[0] = op_dst;
9814 m1->_opnds[1] = new immI16Oper(0);
9815
9816 m2->_opnds[0] = op_dst;
9817 m2->_opnds[1] = op_crx;
9818 m2->_opnds[2] = op_mem;
9819
9820 // registers for new nodes
9821 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9822 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9823
9824 // Insert new nodes.
9825 nodes->push(m1);
9826 nodes->push(m2);
9827 %}
9828 %}
9829
9830 // Double to Int conversion, NaN is mapped to 0.
9831 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9832 match(Set dst (ConvD2I src));
9833 ins_cost(DEFAULT_COST);
9834
9835 expand %{
9836 regD tmpD;
9837 stackSlotL tmpS;
9838 flagsReg crx;
9839 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9840 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9841 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9842 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9843 %}
9844 %}
9845
9846 instruct convF2IRaw_regF(regF dst, regF src) %{
9847 // no match-rule, false predicate
9848 effect(DEF dst, USE src);
9849 predicate(false);
9850
9851 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9852 size(4);
9853 ins_encode %{
9854 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9855 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9856 %}
9857 ins_pipe(pipe_class_default);
9858 %}
9859
9860 // Float to Int conversion, NaN is mapped to 0.
9861 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9862 match(Set dst (ConvF2I src));
9863 ins_cost(DEFAULT_COST);
9864
9865 expand %{
9866 regF tmpF;
9867 stackSlotL tmpS;
9868 flagsReg crx;
9869 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9870 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9871 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9872 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9873 %}
9874 %}
9875
9876 // Convert to Long
9877
9878 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9879 match(Set dst (ConvI2L src));
9880 format %{ "EXTSW $dst, $src \t// int->long" %}
9881 size(4);
9882 ins_encode %{
9883 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9884 __ extsw($dst$$Register, $src$$Register);
9885 %}
9886 ins_pipe(pipe_class_default);
9887 %}
9888
9889 // Zero-extend: convert unsigned int to long (convUI2L).
9890 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9891 match(Set dst (AndL (ConvI2L src) mask));
9892 ins_cost(DEFAULT_COST);
9893
9894 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9895 size(4);
9896 ins_encode %{
9897 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9898 __ clrldi($dst$$Register, $src$$Register, 32);
9899 %}
9900 ins_pipe(pipe_class_default);
9901 %}
9902
9903 // Zero-extend: convert unsigned int to long in long register.
9904 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9905 match(Set dst (AndL src mask));
9906 ins_cost(DEFAULT_COST);
9907
9908 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9909 size(4);
9910 ins_encode %{
9911 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9912 __ clrldi($dst$$Register, $src$$Register, 32);
9913 %}
9914 ins_pipe(pipe_class_default);
9915 %}
9916
9917 instruct convF2LRaw_regF(regF dst, regF src) %{
9918 // no match-rule, false predicate
9919 effect(DEF dst, USE src);
9920 predicate(false);
9921
9922 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9923 size(4);
9924 ins_encode %{
9925 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9926 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9927 %}
9928 ins_pipe(pipe_class_default);
9929 %}
9930
9931 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9932 // no match-rule, false predicate
9933 effect(DEF dst, USE crx, USE src);
9934 predicate(false);
9935
9936 ins_variable_size_depending_on_alignment(true);
9937
9938 format %{ "cmovL $crx, $dst, $src" %}
9939 // Worst case is branch + move + stop, no stop without scheduler.
9940 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9941 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9942 ins_pipe(pipe_class_default);
9943 %}
9944
9945 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9946 // no match-rule, false predicate
9947 effect(DEF dst, USE crx, USE mem);
9948 predicate(false);
9949
9950 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9951 postalloc_expand %{
9952 //
9953 // replaces
9954 //
9955 // region dst crx mem
9956 // \ | | /
9957 // dst=cmovL_bso_stackSlotL_conLvalue0
9958 //
9959 // with
9960 //
9961 // region dst
9962 // \ /
9963 // dst=loadConL16(0)
9964 // |
9965 // ^ region dst crx mem
9966 // | \ | | /
9967 // dst=cmovL_bso_stackSlotL
9968 //
9969
9970 // Create new nodes.
9971 MachNode *m1 = new loadConL16Node();
9972 MachNode *m2 = new cmovL_bso_stackSlotLNode();
9973
9974 // inputs for new nodes
9975 m1->add_req(n_region);
9976 m2->add_req(n_region, n_crx, n_mem);
9977 m2->add_prec(m1);
9978
9979 // operands for new nodes
9980 m1->_opnds[0] = op_dst;
9981 m1->_opnds[1] = new immL16Oper(0);
9982 m2->_opnds[0] = op_dst;
9983 m2->_opnds[1] = op_crx;
9984 m2->_opnds[2] = op_mem;
9985
9986 // registers for new nodes
9987 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9988 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9989
9990 // Insert new nodes.
9991 nodes->push(m1);
9992 nodes->push(m2);
9993 %}
9994 %}
9995
9996 // Float to Long conversion, NaN is mapped to 0.
9997 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9998 match(Set dst (ConvF2L src));
9999 ins_cost(DEFAULT_COST);
10000
10001 expand %{
10002 regF tmpF;
10003 stackSlotL tmpS;
10004 flagsReg crx;
10005 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10006 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
10007 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
10008 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10009 %}
10010 %}
10011
10012 instruct convD2LRaw_regD(regD dst, regD src) %{
10013 // no match-rule, false predicate
10014 effect(DEF dst, USE src);
10015 predicate(false);
10016
10017 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10018 size(4);
10019 ins_encode %{
10020 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10021 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10022 %}
10023 ins_pipe(pipe_class_default);
10024 %}
10025
10026 // Double to Long conversion, NaN is mapped to 0.
10027 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10028 match(Set dst (ConvD2L src));
10029 ins_cost(DEFAULT_COST);
10030
10031 expand %{
10032 regD tmpD;
10033 stackSlotL tmpS;
10034 flagsReg crx;
10035 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10036 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10037 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10038 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10039 %}
10040 %}
10041
10042 // Convert to Float
10043
10044 // Placed here as needed in expand.
10045 instruct convL2DRaw_regD(regD dst, regD src) %{
10046 // no match-rule, false predicate
10047 effect(DEF dst, USE src);
10048 predicate(false);
10049
10050 format %{ "FCFID $dst, $src \t// convL2D" %}
10051 size(4);
10052 ins_encode %{
10053 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10054 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10055 %}
10056 ins_pipe(pipe_class_default);
10057 %}
10058
10059 // Placed here as needed in expand.
10060 instruct convD2F_reg(regF dst, regD src) %{
10061 match(Set dst (ConvD2F src));
10062 format %{ "FRSP $dst, $src \t// convD2F" %}
10063 size(4);
10064 ins_encode %{
10065 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10066 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10067 %}
10068 ins_pipe(pipe_class_default);
10069 %}
10070
10071 // Integer to Float conversion.
10072 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10073 match(Set dst (ConvI2F src));
10074 predicate(!VM_Version::has_fcfids());
10075 ins_cost(DEFAULT_COST);
10076
10077 expand %{
10078 iRegLdst tmpL;
10079 stackSlotL tmpS;
10080 regD tmpD;
10081 regD tmpD2;
10082 convI2L_reg(tmpL, src); // Sign-extension int to long.
10083 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10084 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10085 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10086 convD2F_reg(dst, tmpD2); // Convert double to float.
10087 %}
10088 %}
10089
10090 instruct convL2FRaw_regF(regF dst, regD src) %{
10091 // no match-rule, false predicate
10092 effect(DEF dst, USE src);
10093 predicate(false);
10094
10095 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10096 size(4);
10097 ins_encode %{
10098 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10099 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10100 %}
10101 ins_pipe(pipe_class_default);
10102 %}
10103
10104 // Integer to Float conversion. Special version for Power7.
10105 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10106 match(Set dst (ConvI2F src));
10107 predicate(VM_Version::has_fcfids());
10108 ins_cost(DEFAULT_COST);
10109
10110 expand %{
10111 iRegLdst tmpL;
10112 stackSlotL tmpS;
10113 regD tmpD;
10114 convI2L_reg(tmpL, src); // Sign-extension int to long.
10115 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10116 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10117 convL2FRaw_regF(dst, tmpD); // Convert to float.
10118 %}
10119 %}
10120
10121 // L2F to avoid runtime call.
10122 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10123 match(Set dst (ConvL2F src));
10124 predicate(VM_Version::has_fcfids());
10125 ins_cost(DEFAULT_COST);
10126
10127 expand %{
10128 stackSlotL tmpS;
10129 regD tmpD;
10130 regL_to_stkL(tmpS, src); // Store long to stack.
10131 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10132 convL2FRaw_regF(dst, tmpD); // Convert to float.
10133 %}
10134 %}
10135
10136 // Moved up as used in expand.
10137 //instruct convD2F_reg(regF dst, regD src) %{%}
10138
10139 // Convert to Double
10140
10141 // Integer to Double conversion.
10142 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10143 match(Set dst (ConvI2D src));
10144 ins_cost(DEFAULT_COST);
10145
10146 expand %{
10147 iRegLdst tmpL;
10148 stackSlotL tmpS;
10149 regD tmpD;
10150 convI2L_reg(tmpL, src); // Sign-extension int to long.
10151 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10152 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10153 convL2DRaw_regD(dst, tmpD); // Convert to double.
10154 %}
10155 %}
10156
10157 // Long to Double conversion
10158 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10159 match(Set dst (ConvL2D src));
10160 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10161
10162 expand %{
10163 regD tmpD;
10164 moveL2D_stack_reg(tmpD, src);
10165 convL2DRaw_regD(dst, tmpD);
10166 %}
10167 %}
10168
10169 instruct convF2D_reg(regD dst, regF src) %{
10170 match(Set dst (ConvF2D src));
10171 format %{ "FMR $dst, $src \t// float->double" %}
10172 // variable size, 0 or 4
10173 ins_encode %{
10174 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10175 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10176 %}
10177 ins_pipe(pipe_class_default);
10178 %}
10179
10180 //----------Control Flow Instructions------------------------------------------
10181 // Compare Instructions
10182
10183 // Compare Integers
10184 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10185 match(Set crx (CmpI src1 src2));
10186 size(4);
10187 format %{ "CMPW $crx, $src1, $src2" %}
10188 ins_encode %{
10189 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10190 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10191 %}
10192 ins_pipe(pipe_class_compare);
10193 %}
10194
10195 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10196 match(Set crx (CmpI src1 src2));
10197 format %{ "CMPWI $crx, $src1, $src2" %}
10198 size(4);
10199 ins_encode %{
10200 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10201 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10202 %}
10203 ins_pipe(pipe_class_compare);
10204 %}
10205
10206 // (src1 & src2) == 0?
10207 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10208 match(Set cr0 (CmpI (AndI src1 src2) zero));
10209 // r0 is killed
10210 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10211 size(4);
10212 ins_encode %{
10213 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10214 __ andi_(R0, $src1$$Register, $src2$$constant);
10215 %}
10216 ins_pipe(pipe_class_compare);
10217 %}
10218
10219 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10220 match(Set crx (CmpL src1 src2));
10221 format %{ "CMPD $crx, $src1, $src2" %}
10222 size(4);
10223 ins_encode %{
10224 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10225 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10226 %}
10227 ins_pipe(pipe_class_compare);
10228 %}
10229
10230 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10231 match(Set crx (CmpL src1 src2));
10232 format %{ "CMPDI $crx, $src1, $src2" %}
10233 size(4);
10234 ins_encode %{
10235 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10236 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10237 %}
10238 ins_pipe(pipe_class_compare);
10239 %}
10240
10241 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10242 match(Set cr0 (CmpL (AndL src1 src2) zero));
10243 // r0 is killed
10244 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10245 size(4);
10246 ins_encode %{
10247 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10248 __ and_(R0, $src1$$Register, $src2$$Register);
10249 %}
10250 ins_pipe(pipe_class_compare);
10251 %}
10252
10253 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10254 match(Set cr0 (CmpL (AndL src1 src2) zero));
10255 // r0 is killed
10256 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10257 size(4);
10258 ins_encode %{
10259 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10260 __ andi_(R0, $src1$$Register, $src2$$constant);
10261 %}
10262 ins_pipe(pipe_class_compare);
10263 %}
10264
10265 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10266 // no match-rule, false predicate
10267 effect(DEF dst, USE crx);
10268 predicate(false);
10269
10270 ins_variable_size_depending_on_alignment(true);
10271
10272 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10273 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10274 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10275 ins_encode %{
10276 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10277 Label done;
10278 // li(Rdst, 0); // equal -> 0
10279 __ beq($crx$$CondRegister, done);
10280 __ li($dst$$Register, 1); // greater -> +1
10281 __ bgt($crx$$CondRegister, done);
10282 __ li($dst$$Register, -1); // unordered or less -> -1
10283 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10284 __ bind(done);
10285 %}
10286 ins_pipe(pipe_class_compare);
10287 %}
10288
10289 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10290 // no match-rule, false predicate
10291 effect(DEF dst, USE crx);
10292 predicate(false);
10293
10294 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10295 postalloc_expand %{
10296 //
10297 // replaces
10298 //
10299 // region crx
10300 // \ |
10301 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10302 //
10303 // with
10304 //
10305 // region
10306 // \
10307 // dst=loadConI16(0)
10308 // |
10309 // ^ region crx
10310 // | \ |
10311 // dst=cmovI_conIvalueMinus1_conIvalue1
10312 //
10313
10314 // Create new nodes.
10315 MachNode *m1 = new loadConI16Node();
10316 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10317
10318 // inputs for new nodes
10319 m1->add_req(n_region);
10320 m2->add_req(n_region, n_crx);
10321 m2->add_prec(m1);
10322
10323 // operands for new nodes
10324 m1->_opnds[0] = op_dst;
10325 m1->_opnds[1] = new immI16Oper(0);
10326 m2->_opnds[0] = op_dst;
10327 m2->_opnds[1] = op_crx;
10328
10329 // registers for new nodes
10330 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10331 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10332
10333 // Insert new nodes.
10334 nodes->push(m1);
10335 nodes->push(m2);
10336 %}
10337 %}
10338
10339 // Manifest a CmpL3 result in an integer register. Very painful.
10340 // This is the test to avoid.
10341 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10342 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10343 match(Set dst (CmpL3 src1 src2));
10344 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10345
10346 expand %{
10347 flagsReg tmp1;
10348 cmpL_reg_reg(tmp1, src1, src2);
10349 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10350 %}
10351 %}
10352
10353 // Implicit range checks.
10354 // A range check in the ideal world has one of the following shapes:
10355 // - (If le (CmpU length index)), (IfTrue throw exception)
10356 // - (If lt (CmpU index length)), (IfFalse throw exception)
10357 //
10358 // Match range check 'If le (CmpU length index)'.
10359 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10360 match(If cmp (CmpU src_length index));
10361 effect(USE labl);
10362 predicate(TrapBasedRangeChecks &&
10363 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10364 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10365 (Matcher::branches_to_uncommon_trap(_leaf)));
10366
10367 ins_is_TrapBasedCheckNode(true);
10368
10369 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10370 size(4);
10371 ins_encode %{
10372 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10373 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10374 __ trap_range_check_le($src_length$$Register, $index$$constant);
10375 } else {
10376 // Both successors are uncommon traps, probability is 0.
10377 // Node got flipped during fixup flow.
10378 assert($cmp$$cmpcode == 0x9, "must be greater");
10379 __ trap_range_check_g($src_length$$Register, $index$$constant);
10380 }
10381 %}
10382 ins_pipe(pipe_class_trap);
10383 %}
10384
10385 // Match range check 'If lt (CmpU index length)'.
10386 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10387 match(If cmp (CmpU src_index src_length));
10388 effect(USE labl);
10389 predicate(TrapBasedRangeChecks &&
10390 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10391 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10392 (Matcher::branches_to_uncommon_trap(_leaf)));
10393
10394 ins_is_TrapBasedCheckNode(true);
10395
10396 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10397 size(4);
10398 ins_encode %{
10399 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10400 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10401 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10402 } else {
10403 // Both successors are uncommon traps, probability is 0.
10404 // Node got flipped during fixup flow.
10405 assert($cmp$$cmpcode == 0x8, "must be less");
10406 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10407 }
10408 %}
10409 ins_pipe(pipe_class_trap);
10410 %}
10411
10412 // Match range check 'If lt (CmpU index length)'.
10413 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10414 match(If cmp (CmpU src_index length));
10415 effect(USE labl);
10416 predicate(TrapBasedRangeChecks &&
10417 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10418 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10419 (Matcher::branches_to_uncommon_trap(_leaf)));
10420
10421 ins_is_TrapBasedCheckNode(true);
10422
10423 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10424 size(4);
10425 ins_encode %{
10426 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10427 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10428 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10429 } else {
10430 // Both successors are uncommon traps, probability is 0.
10431 // Node got flipped during fixup flow.
10432 assert($cmp$$cmpcode == 0x8, "must be less");
10433 __ trap_range_check_l($src_index$$Register, $length$$constant);
10434 }
10435 %}
10436 ins_pipe(pipe_class_trap);
10437 %}
10438
10439 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10440 match(Set crx (CmpU src1 src2));
10441 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10442 size(4);
10443 ins_encode %{
10444 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10445 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10446 %}
10447 ins_pipe(pipe_class_compare);
10448 %}
10449
10450 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10451 match(Set crx (CmpU src1 src2));
10452 size(4);
10453 format %{ "CMPLWI $crx, $src1, $src2" %}
10454 ins_encode %{
10455 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10456 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10457 %}
10458 ins_pipe(pipe_class_compare);
10459 %}
10460
10461 // Implicit zero checks (more implicit null checks).
10462 // No constant pool entries required.
10463 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10464 match(If cmp (CmpN value zero));
10465 effect(USE labl);
10466 predicate(TrapBasedNullChecks &&
10467 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10468 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10469 Matcher::branches_to_uncommon_trap(_leaf));
10470 ins_cost(1);
10471
10472 ins_is_TrapBasedCheckNode(true);
10473
10474 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10475 size(4);
10476 ins_encode %{
10477 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10478 if ($cmp$$cmpcode == 0xA) {
10479 __ trap_null_check($value$$Register);
10480 } else {
10481 // Both successors are uncommon traps, probability is 0.
10482 // Node got flipped during fixup flow.
10483 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10484 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10485 }
10486 %}
10487 ins_pipe(pipe_class_trap);
10488 %}
10489
10490 // Compare narrow oops.
10491 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10492 match(Set crx (CmpN src1 src2));
10493
10494 size(4);
10495 ins_cost(2);
10496 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10497 ins_encode %{
10498 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10499 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10500 %}
10501 ins_pipe(pipe_class_compare);
10502 %}
10503
10504 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10505 match(Set crx (CmpN src1 src2));
10506 // Make this more expensive than zeroCheckN_iReg_imm0.
10507 ins_cost(2);
10508
10509 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10510 size(4);
10511 ins_encode %{
10512 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10513 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10514 %}
10515 ins_pipe(pipe_class_compare);
10516 %}
10517
10518 // Implicit zero checks (more implicit null checks).
10519 // No constant pool entries required.
10520 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10521 match(If cmp (CmpP value zero));
10522 effect(USE labl);
10523 predicate(TrapBasedNullChecks &&
10524 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10525 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10526 Matcher::branches_to_uncommon_trap(_leaf));
10527 ins_cost(1); // Should not be cheaper than zeroCheckN.
10528
10529 ins_is_TrapBasedCheckNode(true);
10530
10531 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10532 size(4);
10533 ins_encode %{
10534 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10535 if ($cmp$$cmpcode == 0xA) {
10536 __ trap_null_check($value$$Register);
10537 } else {
10538 // Both successors are uncommon traps, probability is 0.
10539 // Node got flipped during fixup flow.
10540 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10541 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10542 }
10543 %}
10544 ins_pipe(pipe_class_trap);
10545 %}
10546
10547 // Compare Pointers
10548 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10549 match(Set crx (CmpP src1 src2));
10550 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10551 size(4);
10552 ins_encode %{
10553 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10554 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10555 %}
10556 ins_pipe(pipe_class_compare);
10557 %}
10558
10559 // Used in postalloc expand.
10560 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10561 // This match rule prevents reordering of node before a safepoint.
10562 // This only makes sense if this instructions is used exclusively
10563 // for the expansion of EncodeP!
10564 match(Set crx (CmpP src1 src2));
10565 predicate(false);
10566
10567 format %{ "CMPDI $crx, $src1, $src2" %}
10568 size(4);
10569 ins_encode %{
10570 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10571 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10572 %}
10573 ins_pipe(pipe_class_compare);
10574 %}
10575
10576 //----------Float Compares----------------------------------------------------
10577
10578 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10579 // Needs matchrule, see cmpDUnordered.
10580 match(Set crx (CmpF src1 src2));
10581 // no match-rule, false predicate
10582 predicate(false);
10583
10584 format %{ "cmpFUrd $crx, $src1, $src2" %}
10585 size(4);
10586 ins_encode %{
10587 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10588 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10589 %}
10590 ins_pipe(pipe_class_default);
10591 %}
10592
10593 instruct cmov_bns_less(flagsReg crx) %{
10594 // no match-rule, false predicate
10595 effect(DEF crx);
10596 predicate(false);
10597
10598 ins_variable_size_depending_on_alignment(true);
10599
10600 format %{ "cmov $crx" %}
10601 // Worst case is branch + move + stop, no stop without scheduler.
10602 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10603 ins_encode %{
10604 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10605 Label done;
10606 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10607 __ li(R0, 0);
10608 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10609 // TODO PPC port __ endgroup_if_needed(_size == 16);
10610 __ bind(done);
10611 %}
10612 ins_pipe(pipe_class_default);
10613 %}
10614
10615 // Compare floating, generate condition code.
10616 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10617 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10618 //
10619 // The following code sequence occurs a lot in mpegaudio:
10620 //
10621 // block BXX:
10622 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10623 // cmpFUrd CCR6, F11, F9
10624 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10625 // cmov CCR6
10626 // 8: instruct branchConSched:
10627 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10628 match(Set crx (CmpF src1 src2));
10629 ins_cost(DEFAULT_COST+BRANCH_COST);
10630
10631 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10632 postalloc_expand %{
10633 //
10634 // replaces
10635 //
10636 // region src1 src2
10637 // \ | |
10638 // crx=cmpF_reg_reg
10639 //
10640 // with
10641 //
10642 // region src1 src2
10643 // \ | |
10644 // crx=cmpFUnordered_reg_reg
10645 // |
10646 // ^ region
10647 // | \
10648 // crx=cmov_bns_less
10649 //
10650
10651 // Create new nodes.
10652 MachNode *m1 = new cmpFUnordered_reg_regNode();
10653 MachNode *m2 = new cmov_bns_lessNode();
10654
10655 // inputs for new nodes
10656 m1->add_req(n_region, n_src1, n_src2);
10657 m2->add_req(n_region);
10658 m2->add_prec(m1);
10659
10660 // operands for new nodes
10661 m1->_opnds[0] = op_crx;
10662 m1->_opnds[1] = op_src1;
10663 m1->_opnds[2] = op_src2;
10664 m2->_opnds[0] = op_crx;
10665
10666 // registers for new nodes
10667 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10668 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10669
10670 // Insert new nodes.
10671 nodes->push(m1);
10672 nodes->push(m2);
10673 %}
10674 %}
10675
10676 // Compare float, generate -1,0,1
10677 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10678 match(Set dst (CmpF3 src1 src2));
10679 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10680
10681 expand %{
10682 flagsReg tmp1;
10683 cmpFUnordered_reg_reg(tmp1, src1, src2);
10684 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10685 %}
10686 %}
10687
10688 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10689 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10690 // node right before the conditional move using it.
10691 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10692 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10693 // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10694 // conditional move was supposed to be spilled.
10695 match(Set crx (CmpD src1 src2));
10696 // False predicate, shall not be matched.
10697 predicate(false);
10698
10699 format %{ "cmpFUrd $crx, $src1, $src2" %}
10700 size(4);
10701 ins_encode %{
10702 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10703 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10704 %}
10705 ins_pipe(pipe_class_default);
10706 %}
10707
10708 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10709 match(Set crx (CmpD src1 src2));
10710 ins_cost(DEFAULT_COST+BRANCH_COST);
10711
10712 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10713 postalloc_expand %{
10714 //
10715 // replaces
10716 //
10717 // region src1 src2
10718 // \ | |
10719 // crx=cmpD_reg_reg
10720 //
10721 // with
10722 //
10723 // region src1 src2
10724 // \ | |
10725 // crx=cmpDUnordered_reg_reg
10726 // |
10727 // ^ region
10728 // | \
10729 // crx=cmov_bns_less
10730 //
10731
10732 // create new nodes
10733 MachNode *m1 = new cmpDUnordered_reg_regNode();
10734 MachNode *m2 = new cmov_bns_lessNode();
10735
10736 // inputs for new nodes
10737 m1->add_req(n_region, n_src1, n_src2);
10738 m2->add_req(n_region);
10739 m2->add_prec(m1);
10740
10741 // operands for new nodes
10742 m1->_opnds[0] = op_crx;
10743 m1->_opnds[1] = op_src1;
10744 m1->_opnds[2] = op_src2;
10745 m2->_opnds[0] = op_crx;
10746
10747 // registers for new nodes
10748 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10749 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10750
10751 // Insert new nodes.
10752 nodes->push(m1);
10753 nodes->push(m2);
10754 %}
10755 %}
10756
10757 // Compare double, generate -1,0,1
10758 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10759 match(Set dst (CmpD3 src1 src2));
10760 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10761
10762 expand %{
10763 flagsReg tmp1;
10764 cmpDUnordered_reg_reg(tmp1, src1, src2);
10765 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10766 %}
10767 %}
10768
10769 //----------Branches---------------------------------------------------------
10770 // Jump
10771
10772 // Direct Branch.
10773 instruct branch(label labl) %{
10774 match(Goto);
10775 effect(USE labl);
10776 ins_cost(BRANCH_COST);
10777
10778 format %{ "B $labl" %}
10779 size(4);
10780 ins_encode %{
10781 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10782 Label d; // dummy
10783 __ bind(d);
10784 Label* p = $labl$$label;
10785 // `p' is `NULL' when this encoding class is used only to
10786 // determine the size of the encoded instruction.
10787 Label& l = (NULL == p)? d : *(p);
10788 __ b(l);
10789 %}
10790 ins_pipe(pipe_class_default);
10791 %}
10792
10793 // Conditional Near Branch
10794 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10795 // Same match rule as `branchConFar'.
10796 match(If cmp crx);
10797 effect(USE lbl);
10798 ins_cost(BRANCH_COST);
10799
10800 // If set to 1 this indicates that the current instruction is a
10801 // short variant of a long branch. This avoids using this
10802 // instruction in first-pass matching. It will then only be used in
10803 // the `Shorten_branches' pass.
10804 ins_short_branch(1);
10805
10806 format %{ "B$cmp $crx, $lbl" %}
10807 size(4);
10808 ins_encode( enc_bc(crx, cmp, lbl) );
10809 ins_pipe(pipe_class_default);
10810 %}
10811
10812 // This is for cases when the ppc64 `bc' instruction does not
10813 // reach far enough. So we emit a far branch here, which is more
10814 // expensive.
10815 //
10816 // Conditional Far Branch
10817 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10818 // Same match rule as `branchCon'.
10819 match(If cmp crx);
10820 effect(USE crx, USE lbl);
10821 predicate(!false /* TODO: PPC port HB_Schedule*/);
10822 // Higher cost than `branchCon'.
10823 ins_cost(5*BRANCH_COST);
10824
10825 // This is not a short variant of a branch, but the long variant.
10826 ins_short_branch(0);
10827
10828 format %{ "B_FAR$cmp $crx, $lbl" %}
10829 size(8);
10830 ins_encode( enc_bc_far(crx, cmp, lbl) );
10831 ins_pipe(pipe_class_default);
10832 %}
10833
10834 // Conditional Branch used with Power6 scheduler (can be far or short).
10835 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10836 // Same match rule as `branchCon'.
10837 match(If cmp crx);
10838 effect(USE crx, USE lbl);
10839 predicate(false /* TODO: PPC port HB_Schedule*/);
10840 // Higher cost than `branchCon'.
10841 ins_cost(5*BRANCH_COST);
10842
10843 // Actually size doesn't depend on alignment but on shortening.
10844 ins_variable_size_depending_on_alignment(true);
10845 // long variant.
10846 ins_short_branch(0);
10847
10848 format %{ "B_FAR$cmp $crx, $lbl" %}
10849 size(8); // worst case
10850 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10851 ins_pipe(pipe_class_default);
10852 %}
10853
10854 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10855 match(CountedLoopEnd cmp crx);
10856 effect(USE labl);
10857 ins_cost(BRANCH_COST);
10858
10859 // short variant.
10860 ins_short_branch(1);
10861
10862 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10863 size(4);
10864 ins_encode( enc_bc(crx, cmp, labl) );
10865 ins_pipe(pipe_class_default);
10866 %}
10867
10868 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10869 match(CountedLoopEnd cmp crx);
10870 effect(USE labl);
10871 predicate(!false /* TODO: PPC port HB_Schedule */);
10872 ins_cost(BRANCH_COST);
10873
10874 // Long variant.
10875 ins_short_branch(0);
10876
10877 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10878 size(8);
10879 ins_encode( enc_bc_far(crx, cmp, labl) );
10880 ins_pipe(pipe_class_default);
10881 %}
10882
10883 // Conditional Branch used with Power6 scheduler (can be far or short).
10884 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10885 match(CountedLoopEnd cmp crx);
10886 effect(USE labl);
10887 predicate(false /* TODO: PPC port HB_Schedule */);
10888 // Higher cost than `branchCon'.
10889 ins_cost(5*BRANCH_COST);
10890
10891 // Actually size doesn't depend on alignment but on shortening.
10892 ins_variable_size_depending_on_alignment(true);
10893 // Long variant.
10894 ins_short_branch(0);
10895
10896 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10897 size(8); // worst case
10898 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10899 ins_pipe(pipe_class_default);
10900 %}
10901
10902 // ============================================================================
10903 // Java runtime operations, intrinsics and other complex operations.
10904
10905 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10906 // array for an instance of the superklass. Set a hidden internal cache on a
10907 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10908 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10909 //
10910 // GL TODO: Improve this.
10911 // - result should not be a TEMP
10912 // - Add match rule as on sparc avoiding additional Cmp.
10913 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10914 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10915 match(Set result (PartialSubtypeCheck subklass superklass));
10916 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10917 ins_cost(DEFAULT_COST*10);
10918
10919 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10920 ins_encode %{
10921 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10922 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10923 $tmp_klass$$Register, NULL, $result$$Register);
10924 %}
10925 ins_pipe(pipe_class_default);
10926 %}
10927
10928 // inlined locking and unlocking
10929
10930 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10931 match(Set crx (FastLock oop box));
10932 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10933 predicate(/*(!UseNewFastLockPPC64 || UseBiasedLocking) &&*/ !Compile::current()->use_rtm());
10934
10935 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10936 ins_encode %{
10937 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10938 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10939 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10940 UseBiasedLocking && !UseOptoBiasInlining); // SAPJVM MD 2014-11-06 UseOptoBiasInlining
10941 // If locking was successfull, crx should indicate 'EQ'.
10942 // The compiler generates a branch to the runtime call to
10943 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10944 %}
10945 ins_pipe(pipe_class_compare);
10946 %}
10947
10948 // Separate version for TM. Use bound register for box to enable USE_KILL.
10949 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10950 match(Set crx (FastLock oop box));
10951 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10952 predicate(Compile::current()->use_rtm());
10953
10954 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10955 ins_encode %{
10956 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10957 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10958 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10959 /*Biased Locking*/ false,
10960 _rtm_counters, _stack_rtm_counters,
10961 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10962 /*TM*/ true, ra_->C->profile_rtm());
10963 // If locking was successfull, crx should indicate 'EQ'.
10964 // The compiler generates a branch to the runtime call to
10965 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10966 %}
10967 ins_pipe(pipe_class_compare);
10968 %}
10969
10970 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10971 match(Set crx (FastUnlock oop box));
10972 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10973 predicate(!Compile::current()->use_rtm());
10974
10975 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10976 ins_encode %{
10977 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10978 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10979 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10980 UseBiasedLocking && !UseOptoBiasInlining,
10981 false);
10982 // If unlocking was successfull, crx should indicate 'EQ'.
10983 // The compiler generates a branch to the runtime call to
10984 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10985 %}
10986 ins_pipe(pipe_class_compare);
10987 %}
10988
10989 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10990 match(Set crx (FastUnlock oop box));
10991 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10992 predicate(Compile::current()->use_rtm());
10993
10994 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %}
10995 ins_encode %{
10996 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10997 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10998 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10999 /*Biased Locking*/ false, /*TM*/ true);
11000 // If unlocking was successfull, crx should indicate 'EQ'.
11001 // The compiler generates a branch to the runtime call to
11002 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11003 %}
11004 ins_pipe(pipe_class_compare);
11005 %}
11006
11007 // Align address.
11008 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11009 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11010
11011 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
11012 size(4);
11013 ins_encode %{
11014 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11015 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11016 %}
11017 ins_pipe(pipe_class_default);
11018 %}
11019
11020 // Array size computation.
11021 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11022 match(Set dst (SubL (CastP2X end) (CastP2X start)));
11023
11024 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
11025 size(4);
11026 ins_encode %{
11027 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11028 __ subf($dst$$Register, $start$$Register, $end$$Register);
11029 %}
11030 ins_pipe(pipe_class_default);
11031 %}
11032
11033 // Clear-array with dynamic array-size.
11034 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11035 match(Set dummy (ClearArray cnt base));
11036 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11037 ins_cost(MEMORY_REF_COST);
11038
11039 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11040
11041 format %{ "ClearArray $cnt, $base" %}
11042 ins_encode %{
11043 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11044 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11045 %}
11046 ins_pipe(pipe_class_default);
11047 %}
11048
11049 // String_IndexOf for needle of length 1.
11050 //
11051 // Match needle into immediate operands: no loadConP node needed. Saves one
11052 // register and two instructions over string_indexOf_imm1Node.
11053 //
11054 // Assumes register result differs from all input registers.
11055 //
11056 // Preserves registers haystack, haycnt
11057 // Kills registers tmp1, tmp2
11058 // Defines registers result
11059 //
11060 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11061 //
11062 // Unfortunately this does not match too often. In many situations the AddP is used
11063 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11064 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11065 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11066 iRegIdst tmp1, iRegIdst tmp2,
11067 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11068 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
11069 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11070
11071 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11072
11073 ins_cost(150);
11074 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11075 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11076
11077 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11078 ins_encode %{
11079 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11080 immPOper *needleOper = (immPOper *)$needleImm;
11081 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11082 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11083
11084 __ string_indexof_1($result$$Register,
11085 $haystack$$Register, $haycnt$$Register,
11086 R0, needle_values->char_at(0),
11087 $tmp1$$Register, $tmp2$$Register);
11088 %}
11089 ins_pipe(pipe_class_compare);
11090 %}
11091
11092 // String_IndexOf for needle of length 1.
11093 //
11094 // Special case requires less registers and emits less instructions.
11095 //
11096 // Assumes register result differs from all input registers.
11097 //
11098 // Preserves registers haystack, haycnt
11099 // Kills registers tmp1, tmp2, needle
11100 // Defines registers result
11101 //
11102 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11103 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11104 rscratch2RegP needle, immI_1 needlecntImm,
11105 iRegIdst tmp1, iRegIdst tmp2,
11106 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11107 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11108 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11109 TEMP tmp1, TEMP tmp2);
11110 // Required for EA: check if it is still a type_array.
11111 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11112 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11113 ins_cost(180);
11114
11115 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11116
11117 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11118 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11119 ins_encode %{
11120 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11121 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11122 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11123 guarantee(needle_values, "sanity");
11124 if (needle_values != NULL) {
11125 __ string_indexof_1($result$$Register,
11126 $haystack$$Register, $haycnt$$Register,
11127 R0, needle_values->char_at(0),
11128 $tmp1$$Register, $tmp2$$Register);
11129 } else {
11130 __ string_indexof_1($result$$Register,
11131 $haystack$$Register, $haycnt$$Register,
11132 $needle$$Register, 0,
11133 $tmp1$$Register, $tmp2$$Register);
11134 }
11135 %}
11136 ins_pipe(pipe_class_compare);
11137 %}
11138
11139 // String_IndexOf.
11140 //
11141 // Length of needle as immediate. This saves instruction loading constant needle
11142 // length.
11143 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11144 // completely or do it in vector instruction. This should save registers for
11145 // needlecnt and needle.
11146 //
11147 // Assumes register result differs from all input registers.
11148 // Overwrites haycnt, needlecnt.
11149 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11150 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11151 iRegPsrc needle, uimmI15 needlecntImm,
11152 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11153 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11154 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11155 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11156 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11157 // Required for EA: check if it is still a type_array.
11158 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11159 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11160 ins_cost(250);
11161
11162 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11163
11164 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11165 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11166 ins_encode %{
11167 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11168 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11169 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11170
11171 __ string_indexof($result$$Register,
11172 $haystack$$Register, $haycnt$$Register,
11173 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11174 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11175 %}
11176 ins_pipe(pipe_class_compare);
11177 %}
11178
11179 // StrIndexOf node.
11180 //
11181 // Assumes register result differs from all input registers.
11182 // Overwrites haycnt, needlecnt.
11183 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11184 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11185 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11186 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11187 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11188 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11189 TEMP_DEF result,
11190 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11191 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11192 ins_cost(300);
11193
11194 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11195
11196 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11197 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11198 ins_encode %{
11199 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11200 __ string_indexof($result$$Register,
11201 $haystack$$Register, $haycnt$$Register,
11202 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11203 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11204 %}
11205 ins_pipe(pipe_class_compare);
11206 %}
11207
11208 // String equals with immediate.
11209 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11210 iRegPdst tmp1, iRegPdst tmp2,
11211 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11212 match(Set result (StrEquals (Binary str1 str2) cntImm));
11213 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11214 KILL cr0, KILL cr6, KILL ctr);
11215 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11216 ins_cost(250);
11217
11218 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11219
11220 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11221 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11222 ins_encode %{
11223 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11224 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11225 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11226 %}
11227 ins_pipe(pipe_class_compare);
11228 %}
11229
11230 // String equals.
11231 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11232 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11233 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11234 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11235 match(Set result (StrEquals (Binary str1 str2) cnt));
11236 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11237 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11238 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11239 ins_cost(300);
11240
11241 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11242
11243 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11244 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11245 ins_encode %{
11246 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11247 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11248 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11249 %}
11250 ins_pipe(pipe_class_compare);
11251 %}
11252
11253 // String compare.
11254 // Char[] pointers are passed in.
11255 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11256 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11257 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11258 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11259 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11260 ins_cost(300);
11261
11262 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11263
11264 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11265 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11266 ins_encode %{
11267 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11268 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11269 $result$$Register, $tmp$$Register);
11270 %}
11271 ins_pipe(pipe_class_compare);
11272 %}
11273
11274 //---------- Min/Max Instructions ---------------------------------------------
11275
11276 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11277 match(Set dst (MinI src1 src2));
11278 ins_cost(DEFAULT_COST*6);
11279
11280 expand %{
11281 iRegLdst src1s;
11282 iRegLdst src2s;
11283 iRegLdst diff;
11284 iRegLdst sm;
11285 iRegLdst doz; // difference or zero
11286 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11287 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11288 subL_reg_reg(diff, src2s, src1s);
11289 // Need to consider >=33 bit result, therefore we need signmaskL.
11290 signmask64L_regL(sm, diff);
11291 andL_reg_reg(doz, diff, sm); // <=0
11292 addI_regL_regL(dst, doz, src1s);
11293 %}
11294 %}
11295
11296 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11297 match(Set dst (MaxI src1 src2));
11298 ins_cost(DEFAULT_COST*6);
11299
11300 expand %{
11301 iRegLdst src1s;
11302 iRegLdst src2s;
11303 iRegLdst diff;
11304 iRegLdst sm;
11305 iRegLdst doz; // difference or zero
11306 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11307 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11308 subL_reg_reg(diff, src2s, src1s);
11309 // Need to consider >=33 bit result, therefore we need signmaskL.
11310 signmask64L_regL(sm, diff);
11311 andcL_reg_reg(doz, diff, sm); // >=0
11312 addI_regL_regL(dst, doz, src1s);
11313 %}
11314 %}
11315
11316 //---------- Population Count Instructions ------------------------------------
11317
11318 // Popcnt for Power7.
11319 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11320 match(Set dst (PopCountI src));
11321 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11322 ins_cost(DEFAULT_COST);
11323
11324 format %{ "POPCNTW $dst, $src" %}
11325 size(4);
11326 ins_encode %{
11327 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11328 __ popcntw($dst$$Register, $src$$Register);
11329 %}
11330 ins_pipe(pipe_class_default);
11331 %}
11332
11333 // Popcnt for Power7.
11334 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11335 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11336 match(Set dst (PopCountL src));
11337 ins_cost(DEFAULT_COST);
11338
11339 format %{ "POPCNTD $dst, $src" %}
11340 size(4);
11341 ins_encode %{
11342 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11343 __ popcntd($dst$$Register, $src$$Register);
11344 %}
11345 ins_pipe(pipe_class_default);
11346 %}
11347
11348 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11349 match(Set dst (CountLeadingZerosI src));
11350 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11351 ins_cost(DEFAULT_COST);
11352
11353 format %{ "CNTLZW $dst, $src" %}
11354 size(4);
11355 ins_encode %{
11356 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11357 __ cntlzw($dst$$Register, $src$$Register);
11358 %}
11359 ins_pipe(pipe_class_default);
11360 %}
11361
11362 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11363 match(Set dst (CountLeadingZerosL src));
11364 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11365 ins_cost(DEFAULT_COST);
11366
11367 format %{ "CNTLZD $dst, $src" %}
11368 size(4);
11369 ins_encode %{
11370 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11371 __ cntlzd($dst$$Register, $src$$Register);
11372 %}
11373 ins_pipe(pipe_class_default);
11374 %}
11375
11376 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11377 // no match-rule, false predicate
11378 effect(DEF dst, USE src);
11379 predicate(false);
11380
11381 format %{ "CNTLZD $dst, $src" %}
11382 size(4);
11383 ins_encode %{
11384 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11385 __ cntlzd($dst$$Register, $src$$Register);
11386 %}
11387 ins_pipe(pipe_class_default);
11388 %}
11389
11390 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11391 match(Set dst (CountTrailingZerosI src));
11392 predicate(UseCountLeadingZerosInstructionsPPC64);
11393 ins_cost(DEFAULT_COST);
11394
11395 expand %{
11396 immI16 imm1 %{ (int)-1 %}
11397 immI16 imm2 %{ (int)32 %}
11398 immI_minus1 m1 %{ -1 %}
11399 iRegIdst tmpI1;
11400 iRegIdst tmpI2;
11401 iRegIdst tmpI3;
11402 addI_reg_imm16(tmpI1, src, imm1);
11403 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11404 countLeadingZerosI(tmpI3, tmpI2);
11405 subI_imm16_reg(dst, imm2, tmpI3);
11406 %}
11407 %}
11408
11409 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11410 match(Set dst (CountTrailingZerosL src));
11411 predicate(UseCountLeadingZerosInstructionsPPC64);
11412 ins_cost(DEFAULT_COST);
11413
11414 expand %{
11415 immL16 imm1 %{ (long)-1 %}
11416 immI16 imm2 %{ (int)64 %}
11417 iRegLdst tmpL1;
11418 iRegLdst tmpL2;
11419 iRegIdst tmpL3;
11420 addL_reg_imm16(tmpL1, src, imm1);
11421 andcL_reg_reg(tmpL2, tmpL1, src);
11422 countLeadingZerosL(tmpL3, tmpL2);
11423 subI_imm16_reg(dst, imm2, tmpL3);
11424 %}
11425 %}
11426
11427 // Expand nodes for byte_reverse_int.
11428 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11429 effect(DEF dst, USE src, USE pos, USE shift);
11430 predicate(false);
11431
11432 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11433 size(4);
11434 ins_encode %{
11435 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11436 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11437 %}
11438 ins_pipe(pipe_class_default);
11439 %}
11440
11441 // As insrwi_a, but with USE_DEF.
11442 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11443 effect(USE_DEF dst, USE src, USE pos, USE shift);
11444 predicate(false);
11445
11446 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11447 size(4);
11448 ins_encode %{
11449 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11450 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11451 %}
11452 ins_pipe(pipe_class_default);
11453 %}
11454
11455 // Just slightly faster than java implementation.
11456 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11457 match(Set dst (ReverseBytesI src));
11458 predicate(UseCountLeadingZerosInstructionsPPC64);
11459 ins_cost(DEFAULT_COST);
11460
11461 expand %{
11462 immI16 imm24 %{ (int) 24 %}
11463 immI16 imm16 %{ (int) 16 %}
11464 immI16 imm8 %{ (int) 8 %}
11465 immI16 imm4 %{ (int) 4 %}
11466 immI16 imm0 %{ (int) 0 %}
11467 iRegLdst tmpI1;
11468 iRegLdst tmpI2;
11469 iRegLdst tmpI3;
11470
11471 urShiftI_reg_imm(tmpI1, src, imm24);
11472 insrwi_a(dst, tmpI1, imm24, imm8);
11473 urShiftI_reg_imm(tmpI2, src, imm16);
11474 insrwi(dst, tmpI2, imm8, imm16);
11475 urShiftI_reg_imm(tmpI3, src, imm8);
11476 insrwi(dst, tmpI3, imm8, imm8);
11477 insrwi(dst, src, imm0, imm8);
11478 %}
11479 %}
11480
11481 //---------- Replicate Vector Instructions ------------------------------------
11482
11483 // Insrdi does replicate if src == dst.
11484 instruct repl32(iRegLdst dst) %{
11485 predicate(false);
11486 effect(USE_DEF dst);
11487
11488 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11489 size(4);
11490 ins_encode %{
11491 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11492 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11493 %}
11494 ins_pipe(pipe_class_default);
11495 %}
11496
11497 // Insrdi does replicate if src == dst.
11498 instruct repl48(iRegLdst dst) %{
11499 predicate(false);
11500 effect(USE_DEF dst);
11501
11502 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11503 size(4);
11504 ins_encode %{
11505 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11506 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11507 %}
11508 ins_pipe(pipe_class_default);
11509 %}
11510
11511 // Insrdi does replicate if src == dst.
11512 instruct repl56(iRegLdst dst) %{
11513 predicate(false);
11514 effect(USE_DEF dst);
11515
11516 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11517 size(4);
11518 ins_encode %{
11519 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11520 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11521 %}
11522 ins_pipe(pipe_class_default);
11523 %}
11524
11525 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11526 match(Set dst (ReplicateB src));
11527 predicate(n->as_Vector()->length() == 8);
11528 expand %{
11529 moveReg(dst, src);
11530 repl56(dst);
11531 repl48(dst);
11532 repl32(dst);
11533 %}
11534 %}
11535
11536 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11537 match(Set dst (ReplicateB zero));
11538 predicate(n->as_Vector()->length() == 8);
11539 format %{ "LI $dst, #0 \t// replicate8B" %}
11540 size(4);
11541 ins_encode %{
11542 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11543 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11544 %}
11545 ins_pipe(pipe_class_default);
11546 %}
11547
11548 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11549 match(Set dst (ReplicateB src));
11550 predicate(n->as_Vector()->length() == 8);
11551 format %{ "LI $dst, #-1 \t// replicate8B" %}
11552 size(4);
11553 ins_encode %{
11554 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11555 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11556 %}
11557 ins_pipe(pipe_class_default);
11558 %}
11559
11560 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11561 match(Set dst (ReplicateS src));
11562 predicate(n->as_Vector()->length() == 4);
11563 expand %{
11564 moveReg(dst, src);
11565 repl48(dst);
11566 repl32(dst);
11567 %}
11568 %}
11569
11570 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11571 match(Set dst (ReplicateS zero));
11572 predicate(n->as_Vector()->length() == 4);
11573 format %{ "LI $dst, #0 \t// replicate4C" %}
11574 size(4);
11575 ins_encode %{
11576 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11577 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11578 %}
11579 ins_pipe(pipe_class_default);
11580 %}
11581
11582 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11583 match(Set dst (ReplicateS src));
11584 predicate(n->as_Vector()->length() == 4);
11585 format %{ "LI $dst, -1 \t// replicate4C" %}
11586 size(4);
11587 ins_encode %{
11588 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11589 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11590 %}
11591 ins_pipe(pipe_class_default);
11592 %}
11593
11594 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11595 match(Set dst (ReplicateI src));
11596 predicate(n->as_Vector()->length() == 2);
11597 ins_cost(2 * DEFAULT_COST);
11598 expand %{
11599 moveReg(dst, src);
11600 repl32(dst);
11601 %}
11602 %}
11603
11604 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11605 match(Set dst (ReplicateI zero));
11606 predicate(n->as_Vector()->length() == 2);
11607 format %{ "LI $dst, #0 \t// replicate4C" %}
11608 size(4);
11609 ins_encode %{
11610 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11611 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11612 %}
11613 ins_pipe(pipe_class_default);
11614 %}
11615
11616 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11617 match(Set dst (ReplicateI src));
11618 predicate(n->as_Vector()->length() == 2);
11619 format %{ "LI $dst, -1 \t// replicate4C" %}
11620 size(4);
11621 ins_encode %{
11622 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11623 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11624 %}
11625 ins_pipe(pipe_class_default);
11626 %}
11627
11628 // Move float to int register via stack, replicate.
11629 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11630 match(Set dst (ReplicateF src));
11631 predicate(n->as_Vector()->length() == 2);
11632 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11633 expand %{
11634 stackSlotL tmpS;
11635 iRegIdst tmpI;
11636 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11637 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11638 moveReg(dst, tmpI); // Move int to long reg.
11639 repl32(dst); // Replicate bitpattern.
11640 %}
11641 %}
11642
11643 // Replicate scalar constant to packed float values in Double register
11644 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11645 match(Set dst (ReplicateF src));
11646 predicate(n->as_Vector()->length() == 2);
11647 ins_cost(5 * DEFAULT_COST);
11648
11649 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11650 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11651 %}
11652
11653 // Replicate scalar zero constant to packed float values in Double register
11654 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11655 match(Set dst (ReplicateF zero));
11656 predicate(n->as_Vector()->length() == 2);
11657
11658 format %{ "LI $dst, #0 \t// replicate2F" %}
11659 ins_encode %{
11660 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11661 __ li($dst$$Register, 0x0);
11662 %}
11663 ins_pipe(pipe_class_default);
11664 %}
11665
11666
11667 //----------Overflow Math Instructions-----------------------------------------
11668
11669 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
11670 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
11671 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
11672
11673 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11674 match(Set cr0 (OverflowAddL op1 op2));
11675
11676 format %{ "add_ $op1, $op2\t# overflow check long" %}
11677 ins_encode %{
11678 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11679 __ li(R0, 0);
11680 __ mtxer(R0); // clear XER.SO
11681 __ addo_(R0, $op1$$Register, $op2$$Register);
11682 %}
11683 ins_pipe(pipe_class_default);
11684 %}
11685
11686 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11687 match(Set cr0 (OverflowSubL op1 op2));
11688
11689 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %}
11690 ins_encode %{
11691 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11692 __ li(R0, 0);
11693 __ mtxer(R0); // clear XER.SO
11694 __ subfo_(R0, $op2$$Register, $op1$$Register);
11695 %}
11696 ins_pipe(pipe_class_default);
11697 %}
11698
11699 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
11700 match(Set cr0 (OverflowSubL zero op2));
11701
11702 format %{ "nego_ R0, $op2\t# overflow check long" %}
11703 ins_encode %{
11704 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11705 __ li(R0, 0);
11706 __ mtxer(R0); // clear XER.SO
11707 __ nego_(R0, $op2$$Register);
11708 %}
11709 ins_pipe(pipe_class_default);
11710 %}
11711
11712 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11713 match(Set cr0 (OverflowMulL op1 op2));
11714
11715 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
11716 ins_encode %{
11717 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11718 __ li(R0, 0);
11719 __ mtxer(R0); // clear XER.SO
11720 __ mulldo_(R0, $op1$$Register, $op2$$Register);
11721 %}
11722 ins_pipe(pipe_class_default);
11723 %}
11724
11725
11726 // ============================================================================
11727 // Safepoint Instruction
11728
11729 instruct safePoint_poll(iRegPdst poll) %{
11730 match(SafePoint poll);
11731 predicate(LoadPollAddressFromThread);
11732
11733 // It caused problems to add the effect that r0 is killed, but this
11734 // effect no longer needs to be mentioned, since r0 is not contained
11735 // in a reg_class.
11736
11737 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11738 size(4);
11739 ins_encode( enc_poll(0x0, poll) );
11740 ins_pipe(pipe_class_default);
11741 %}
11742
11743 // Safepoint without per-thread support. Load address of page to poll
11744 // as constant.
11745 // Rscratch2RegP is R12.
11746 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11747 // a seperate node so that the oop map is at the right location.
11748 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11749 match(SafePoint poll);
11750 predicate(!LoadPollAddressFromThread);
11751
11752 // It caused problems to add the effect that r0 is killed, but this
11753 // effect no longer needs to be mentioned, since r0 is not contained
11754 // in a reg_class.
11755
11756 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11757 ins_encode( enc_poll(0x0, poll) );
11758 ins_pipe(pipe_class_default);
11759 %}
11760
11761 // ============================================================================
11762 // Call Instructions
11763
11764 // Call Java Static Instruction
11765
11766 // Schedulable version of call static node.
11767 instruct CallStaticJavaDirect(method meth) %{
11768 match(CallStaticJava);
11769 effect(USE meth);
11770 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11771 ins_cost(CALL_COST);
11772
11773 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11774
11775 format %{ "CALL,static $meth \t// ==> " %}
11776 size(4);
11777 ins_encode( enc_java_static_call(meth) );
11778 ins_pipe(pipe_class_call);
11779 %}
11780
11781 // Schedulable version of call static node.
11782 instruct CallStaticJavaDirectHandle(method meth) %{
11783 match(CallStaticJava);
11784 effect(USE meth);
11785 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11786 ins_cost(CALL_COST);
11787
11788 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11789
11790 format %{ "CALL,static $meth \t// ==> " %}
11791 ins_encode( enc_java_handle_call(meth) );
11792 ins_pipe(pipe_class_call);
11793 %}
11794
11795 // Call Java Dynamic Instruction
11796
11797 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11798 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11799 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11800 // The call destination must still be placed in the constant pool.
11801 instruct CallDynamicJavaDirectSched(method meth) %{
11802 match(CallDynamicJava); // To get all the data fields we need ...
11803 effect(USE meth);
11804 predicate(false); // ... but never match.
11805
11806 ins_field_load_ic_hi_node(loadConL_hiNode*);
11807 ins_field_load_ic_node(loadConLNode*);
11808 ins_num_consts(1 /* 1 patchable constant: call destination */);
11809
11810 format %{ "BL \t// dynamic $meth ==> " %}
11811 size(4);
11812 ins_encode( enc_java_dynamic_call_sched(meth) );
11813 ins_pipe(pipe_class_call);
11814 %}
11815
11816 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11817 // We use postalloc expanded calls if we use inline caches
11818 // and do not update method data.
11819 //
11820 // This instruction has two constants: inline cache (IC) and call destination.
11821 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11822 // one constant.
11823 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11824 match(CallDynamicJava);
11825 effect(USE meth);
11826 predicate(UseInlineCaches);
11827 ins_cost(CALL_COST);
11828
11829 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11830
11831 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11832 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11833 %}
11834
11835 // Compound version of call dynamic java
11836 // We use postalloc expanded calls if we use inline caches
11837 // and do not update method data.
11838 instruct CallDynamicJavaDirect(method meth) %{
11839 match(CallDynamicJava);
11840 effect(USE meth);
11841 predicate(!UseInlineCaches);
11842 ins_cost(CALL_COST);
11843
11844 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11845 ins_num_consts(4);
11846
11847 format %{ "CALL,dynamic $meth \t// ==> " %}
11848 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11849 ins_pipe(pipe_class_call);
11850 %}
11851
11852 // Call Runtime Instruction
11853
11854 instruct CallRuntimeDirect(method meth) %{
11855 match(CallRuntime);
11856 effect(USE meth);
11857 ins_cost(CALL_COST);
11858
11859 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11860 // env for callee, C-toc.
11861 ins_num_consts(3);
11862
11863 format %{ "CALL,runtime" %}
11864 ins_encode( enc_java_to_runtime_call(meth) );
11865 ins_pipe(pipe_class_call);
11866 %}
11867
11868 // Call Leaf
11869
11870 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11871 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11872 effect(DEF dst, USE src);
11873
11874 ins_num_consts(1);
11875
11876 format %{ "MTCTR $src" %}
11877 size(4);
11878 ins_encode( enc_leaf_call_mtctr(src) );
11879 ins_pipe(pipe_class_default);
11880 %}
11881
11882 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11883 instruct CallLeafDirect(method meth) %{
11884 match(CallLeaf); // To get the data all the data fields we need ...
11885 effect(USE meth);
11886 predicate(false); // but never match.
11887
11888 format %{ "BCTRL \t// leaf call $meth ==> " %}
11889 size(4);
11890 ins_encode %{
11891 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11892 __ bctrl();
11893 %}
11894 ins_pipe(pipe_class_call);
11895 %}
11896
11897 // postalloc expand of CallLeafDirect.
11898 // Load adress to call from TOC, then bl to it.
11899 instruct CallLeafDirect_Ex(method meth) %{
11900 match(CallLeaf);
11901 effect(USE meth);
11902 ins_cost(CALL_COST);
11903
11904 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11905 // env for callee, C-toc.
11906 ins_num_consts(3);
11907
11908 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11909 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11910 %}
11911
11912 // Call runtime without safepoint - same as CallLeaf.
11913 // postalloc expand of CallLeafNoFPDirect.
11914 // Load adress to call from TOC, then bl to it.
11915 instruct CallLeafNoFPDirect_Ex(method meth) %{
11916 match(CallLeafNoFP);
11917 effect(USE meth);
11918 ins_cost(CALL_COST);
11919
11920 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11921 // env for callee, C-toc.
11922 ins_num_consts(3);
11923
11924 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11925 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11926 %}
11927
11928 // Tail Call; Jump from runtime stub to Java code.
11929 // Also known as an 'interprocedural jump'.
11930 // Target of jump will eventually return to caller.
11931 // TailJump below removes the return address.
11932 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11933 match(TailCall jump_target method_oop);
11934 ins_cost(CALL_COST);
11935
11936 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11937 "BCTR \t// tail call" %}
11938 size(8);
11939 ins_encode %{
11940 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11941 __ mtctr($jump_target$$Register);
11942 __ bctr();
11943 %}
11944 ins_pipe(pipe_class_call);
11945 %}
11946
11947 // Return Instruction
11948 instruct Ret() %{
11949 match(Return);
11950 format %{ "BLR \t// branch to link register" %}
11951 size(4);
11952 ins_encode %{
11953 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11954 // LR is restored in MachEpilogNode. Just do the RET here.
11955 __ blr();
11956 %}
11957 ins_pipe(pipe_class_default);
11958 %}
11959
11960 // Tail Jump; remove the return address; jump to target.
11961 // TailCall above leaves the return address around.
11962 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11963 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11964 // "restore" before this instruction (in Epilogue), we need to materialize it
11965 // in %i0.
11966 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11967 match(TailJump jump_target ex_oop);
11968 ins_cost(CALL_COST);
11969
11970 format %{ "LD R4_ARG2 = LR\n\t"
11971 "MTCTR $jump_target\n\t"
11972 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11973 size(12);
11974 ins_encode %{
11975 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11976 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11977 __ mtctr($jump_target$$Register);
11978 __ bctr();
11979 %}
11980 ins_pipe(pipe_class_call);
11981 %}
11982
11983 // Create exception oop: created by stack-crawling runtime code.
11984 // Created exception is now available to this handler, and is setup
11985 // just prior to jumping to this handler. No code emitted.
11986 instruct CreateException(rarg1RegP ex_oop) %{
11987 match(Set ex_oop (CreateEx));
11988 ins_cost(0);
11989
11990 format %{ " -- \t// exception oop; no code emitted" %}
11991 size(0);
11992 ins_encode( /*empty*/ );
11993 ins_pipe(pipe_class_default);
11994 %}
11995
11996 // Rethrow exception: The exception oop will come in the first
11997 // argument position. Then JUMP (not call) to the rethrow stub code.
11998 instruct RethrowException() %{
11999 match(Rethrow);
12000 ins_cost(CALL_COST);
12001
12002 format %{ "Jmp rethrow_stub" %}
12003 ins_encode %{
12004 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12005 cbuf.set_insts_mark();
12006 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12007 %}
12008 ins_pipe(pipe_class_call);
12009 %}
12010
12011 // Die now.
12012 instruct ShouldNotReachHere() %{
12013 match(Halt);
12014 ins_cost(CALL_COST);
12015
12016 format %{ "ShouldNotReachHere" %}
12017 size(4);
12018 ins_encode %{
12019 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12020 __ trap_should_not_reach_here();
12021 %}
12022 ins_pipe(pipe_class_default);
12023 %}
12024
12025 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
12026 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12027 // Get a DEF on threadRegP, no costs, no encoding, use
12028 // 'ins_should_rematerialize(true)' to avoid spilling.
12029 instruct tlsLoadP(threadRegP dst) %{
12030 match(Set dst (ThreadLocal));
12031 ins_cost(0);
12032
12033 ins_should_rematerialize(true);
12034
12035 format %{ " -- \t// $dst=Thread::current(), empty" %}
12036 size(0);
12037 ins_encode( /*empty*/ );
12038 ins_pipe(pipe_class_empty);
12039 %}
12040
12041 //---Some PPC specific nodes---------------------------------------------------
12042
12043 // Stop a group.
12044 instruct endGroup() %{
12045 ins_cost(0);
12046
12047 ins_is_nop(true);
12048
12049 format %{ "End Bundle (ori r1, r1, 0)" %}
12050 size(4);
12051 ins_encode %{
12052 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12053 __ endgroup();
12054 %}
12055 ins_pipe(pipe_class_default);
12056 %}
12057
12058 // Nop instructions
12059
12060 instruct fxNop() %{
12061 ins_cost(0);
12062
12063 ins_is_nop(true);
12064
12065 format %{ "fxNop" %}
12066 size(4);
12067 ins_encode %{
12068 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12069 __ nop();
12070 %}
12071 ins_pipe(pipe_class_default);
12072 %}
12073
12074 instruct fpNop0() %{
12075 ins_cost(0);
12076
12077 ins_is_nop(true);
12078
12079 format %{ "fpNop0" %}
12080 size(4);
12081 ins_encode %{
12082 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12083 __ fpnop0();
12084 %}
12085 ins_pipe(pipe_class_default);
12086 %}
12087
12088 instruct fpNop1() %{
12089 ins_cost(0);
12090
12091 ins_is_nop(true);
12092
12093 format %{ "fpNop1" %}
12094 size(4);
12095 ins_encode %{
12096 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12097 __ fpnop1();
12098 %}
12099 ins_pipe(pipe_class_default);
12100 %}
12101
12102 instruct brNop0() %{
12103 ins_cost(0);
12104 size(4);
12105 format %{ "brNop0" %}
12106 ins_encode %{
12107 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12108 __ brnop0();
12109 %}
12110 ins_is_nop(true);
12111 ins_pipe(pipe_class_default);
12112 %}
12113
12114 instruct brNop1() %{
12115 ins_cost(0);
12116
12117 ins_is_nop(true);
12118
12119 format %{ "brNop1" %}
12120 size(4);
12121 ins_encode %{
12122 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12123 __ brnop1();
12124 %}
12125 ins_pipe(pipe_class_default);
12126 %}
12127
12128 instruct brNop2() %{
12129 ins_cost(0);
12130
12131 ins_is_nop(true);
12132
12133 format %{ "brNop2" %}
12134 size(4);
12135 ins_encode %{
12136 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12137 __ brnop2();
12138 %}
12139 ins_pipe(pipe_class_default);
12140 %}
12141
12142 //----------PEEPHOLE RULES-----------------------------------------------------
12143 // These must follow all instruction definitions as they use the names
12144 // defined in the instructions definitions.
12145 //
12146 // peepmatch ( root_instr_name [preceeding_instruction]* );
12147 //
12148 // peepconstraint %{
12149 // (instruction_number.operand_name relational_op instruction_number.operand_name
12150 // [, ...] );
12151 // // instruction numbers are zero-based using left to right order in peepmatch
12152 //
12153 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12154 // // provide an instruction_number.operand_name for each operand that appears
12155 // // in the replacement instruction's match rule
12156 //
12157 // ---------VM FLAGS---------------------------------------------------------
12158 //
12159 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12160 //
12161 // Each peephole rule is given an identifying number starting with zero and
12162 // increasing by one in the order seen by the parser. An individual peephole
12163 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12164 // on the command-line.
12165 //
12166 // ---------CURRENT LIMITATIONS----------------------------------------------
12167 //
12168 // Only match adjacent instructions in same basic block
12169 // Only equality constraints
12170 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12171 // Only one replacement instruction
12172 //
12173 // ---------EXAMPLE----------------------------------------------------------
12174 //
12175 // // pertinent parts of existing instructions in architecture description
12176 // instruct movI(eRegI dst, eRegI src) %{
12177 // match(Set dst (CopyI src));
12178 // %}
12179 //
12180 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12181 // match(Set dst (AddI dst src));
12182 // effect(KILL cr);
12183 // %}
12184 //
12185 // // Change (inc mov) to lea
12186 // peephole %{
12187 // // increment preceeded by register-register move
12188 // peepmatch ( incI_eReg movI );
12189 // // require that the destination register of the increment
12190 // // match the destination register of the move
12191 // peepconstraint ( 0.dst == 1.dst );
12192 // // construct a replacement instruction that sets
12193 // // the destination to ( move's source register + one )
12194 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12195 // %}
12196 //
12197 // Implementation no longer uses movX instructions since
12198 // machine-independent system no longer uses CopyX nodes.
12199 //
12200 // peephole %{
12201 // peepmatch ( incI_eReg movI );
12202 // peepconstraint ( 0.dst == 1.dst );
12203 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12204 // %}
12205 //
12206 // peephole %{
12207 // peepmatch ( decI_eReg movI );
12208 // peepconstraint ( 0.dst == 1.dst );
12209 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12210 // %}
12211 //
12212 // peephole %{
12213 // peepmatch ( addI_eReg_imm movI );
12214 // peepconstraint ( 0.dst == 1.dst );
12215 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12216 // %}
12217 //
12218 // peephole %{
12219 // peepmatch ( addP_eReg_imm movP );
12220 // peepconstraint ( 0.dst == 1.dst );
12221 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12222 // %}
12223
12224 // // Change load of spilled value to only a spill
12225 // instruct storeI(memory mem, eRegI src) %{
12226 // match(Set mem (StoreI mem src));
12227 // %}
12228 //
12229 // instruct loadI(eRegI dst, memory mem) %{
12230 // match(Set dst (LoadI mem));
12231 // %}
12232 //
12233 peephole %{
12234 peepmatch ( loadI storeI );
12235 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12236 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12237 %}
12238
12239 peephole %{
12240 peepmatch ( loadL storeL );
12241 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12242 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12243 %}
12244
12245 peephole %{
12246 peepmatch ( loadP storeP );
12247 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12248 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12249 %}
12250
12251 //----------SMARTSPILL RULES---------------------------------------------------
12252 // These must follow all instruction definitions as they use the names
12253 // defined in the instructions definitions.