1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2015 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 int VM_Version::_features = VM_Version::unknown_m;
41 int VM_Version::_measured_cache_line_size = 32; // pessimistic init value
42 const char* VM_Version::_features_str = "";
43 bool VM_Version::_is_determine_features_test_running = false;
44
45
46 #define MSG(flag) \
47 if (flag && !FLAG_IS_DEFAULT(flag)) \
48 jio_fprintf(defaultStream::error_stream(), \
49 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
50 " -XX:+" #flag " will be disabled!\n");
51
52 void VM_Version::initialize() {
53
54 // Test which instructions are supported and measure cache line size.
55 determine_features();
56
57 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
58 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
59 if (VM_Version::has_lqarx()) {
60 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
61 } else if (VM_Version::has_popcntw()) {
62 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
63 } else if (VM_Version::has_cmpb()) {
64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
65 } else if (VM_Version::has_popcntb()) {
66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
67 } else {
68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
69 }
70 }
71 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
72 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 ||
73 PowerArchitecturePPC64 == 8,
74 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8");
75
76 // Power 8: Configure Data Stream Control Register.
77 if (PowerArchitecturePPC64 >= 8) {
78 config_dscr();
79 }
80
81 if (!UseSIGTRAP) {
82 MSG(TrapBasedICMissChecks);
83 MSG(TrapBasedNotEntrantChecks);
84 MSG(TrapBasedNullChecks);
85 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
86 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
87 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
88 }
89
90 #ifdef COMPILER2
91 if (!UseSIGTRAP) {
92 MSG(TrapBasedRangeChecks);
93 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
94 }
95
96 // On Power6 test for section size.
97 if (PowerArchitecturePPC64 == 6) {
98 determine_section_size();
99 // TODO: PPC port } else {
100 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
101 }
102
103 MaxVectorSize = 8;
104 #endif
105
106 // Create and print feature-string.
107 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
108 jio_snprintf(buf, sizeof(buf),
109 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s",
110 (has_fsqrt() ? " fsqrt" : ""),
111 (has_isel() ? " isel" : ""),
112 (has_lxarxeh() ? " lxarxeh" : ""),
113 (has_cmpb() ? " cmpb" : ""),
114 //(has_mftgpr()? " mftgpr" : ""),
115 (has_popcntb() ? " popcntb" : ""),
116 (has_popcntw() ? " popcntw" : ""),
117 (has_fcfids() ? " fcfids" : ""),
118 (has_vand() ? " vand" : ""),
119 (has_lqarx() ? " lqarx" : ""),
120 (has_vcipher() ? " vcipher" : ""),
121 (has_vpmsumb() ? " vpmsumb" : ""),
122 (has_tcheck() ? " tcheck" : "")
123 // Make sure number of %s matches num_features!
124 );
125 _features_str = os::strdup(buf);
126 if (Verbose) {
127 print_features();
128 }
129
130 // PPC64 supports 8-byte compare-exchange operations (see
131 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
132 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
133 _supports_cx8 = true;
134
135 UseSSE = 0; // Only on x86 and x64
136
137 intx cache_line_size = _measured_cache_line_size;
138
139 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
140
141 if (AllocatePrefetchStyle == 4) {
142 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
143 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
144 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
145 } else {
146 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
148 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
149 }
150
151 assert(AllocatePrefetchLines > 0, "invalid value");
152 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
153 AllocatePrefetchLines = 1; // Conservative value.
154 }
155
156 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
157 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
158 }
159
160 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
161
162 // Implementation does not use any of the vector instructions
163 // available with Power8. Their exploitation is still pending.
164 if (!UseCRC32Intrinsics) {
165 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
166 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
167 }
168 }
169
170 if (UseCRC32CIntrinsics) {
171 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
172 warning("CRC32C intrinsics are not available on this CPU");
173 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
174 }
175
176 // The AES intrinsic stubs require AES instruction support.
177 if (UseAES) {
178 warning("AES instructions are not available on this CPU");
179 FLAG_SET_DEFAULT(UseAES, false);
180 }
181 if (UseAESIntrinsics) {
182 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
183 warning("AES intrinsics are not available on this CPU");
184 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
185 }
186
187 if (UseGHASHIntrinsics) {
188 warning("GHASH intrinsics are not available on this CPU");
189 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
190 }
191
192 if (UseSHA) {
193 warning("SHA instructions are not available on this CPU");
194 FLAG_SET_DEFAULT(UseSHA, false);
195 }
196 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
197 warning("SHA intrinsics are not available on this CPU");
198 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
199 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
200 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
201 }
202
203 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
204 UseMultiplyToLenIntrinsic = true;
205 }
206
207 // Adjust RTM (Restricted Transactional Memory) flags.
208 if (!has_tcheck() && UseRTMLocking) {
209 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
210 // setting during arguments processing. See use_biased_locking().
211 // VM_Version_init() is executed after UseBiasedLocking is used
212 // in Thread::allocate().
213 vm_exit_during_initialization("RTM instructions are not available on this CPU");
214 }
215
216 if (UseRTMLocking) {
217 #if INCLUDE_RTM_OPT
218 if (!UnlockExperimentalVMOptions) {
219 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
220 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
221 } else {
222 warning("UseRTMLocking is only available as experimental option on this platform.");
223 }
224 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
225 // RTM locking should be used only for applications with
226 // high lock contention. For now we do not use it by default.
227 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
228 }
229 if (!is_power_of_2(RTMTotalCountIncrRate)) {
230 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
231 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
232 }
233 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
234 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
235 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
236 }
237 guarantee(RTMSpinLoopCount > 0, "unsupported");
238 #else
239 // Only C2 does RTM locking optimization.
240 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
241 // setting during arguments processing. See use_biased_locking().
242 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
243 #endif
244 } else { // !UseRTMLocking
245 if (UseRTMForStackLocks) {
246 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
247 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
248 }
249 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
250 }
251 if (UseRTMDeopt) {
252 FLAG_SET_DEFAULT(UseRTMDeopt, false);
253 }
254 if (PrintPreciseRTMLockingStatistics) {
255 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
256 }
257 }
258
259 // This machine does not allow unaligned memory accesses
260 if (UseUnalignedAccesses) {
261 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
262 warning("Unaligned memory access is not available on this CPU");
263 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
264 }
265 }
266
267 bool VM_Version::use_biased_locking() {
268 #if INCLUDE_RTM_OPT
269 // RTM locking is most useful when there is high lock contention and
270 // low data contention. With high lock contention the lock is usually
271 // inflated and biased locking is not suitable for that case.
272 // RTM locking code requires that biased locking is off.
273 // Note: we can't switch off UseBiasedLocking in get_processor_features()
274 // because it is used by Thread::allocate() which is called before
275 // VM_Version::initialize().
276 if (UseRTMLocking && UseBiasedLocking) {
277 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
278 FLAG_SET_DEFAULT(UseBiasedLocking, false);
279 } else {
280 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
281 UseBiasedLocking = false;
282 }
283 }
284 #endif
285 return UseBiasedLocking;
286 }
287
288 void VM_Version::print_features() {
289 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
290 }
291
292 #ifdef COMPILER2
293 // Determine section size on power6: If section size is 8 instructions,
294 // there should be a difference between the two testloops of ~15 %. If
295 // no difference is detected the section is assumed to be 32 instructions.
296 void VM_Version::determine_section_size() {
297
298 int unroll = 80;
299
300 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
301
302 // Allocate space for the code.
303 ResourceMark rm;
304 CodeBuffer cb("detect_section_size", code_size, 0);
305 MacroAssembler* a = new MacroAssembler(&cb);
306
307 uint32_t *code = (uint32_t *)a->pc();
308 // Emit code.
309 void (*test1)() = (void(*)())(void *)a->function_entry();
310
311 Label l1;
312
313 a->li(R4, 1);
314 a->sldi(R4, R4, 28);
315 a->b(l1);
316 a->align(CodeEntryAlignment);
317
318 a->bind(l1);
319
320 for (int i = 0; i < unroll; i++) {
321 // Schleife 1
322 // ------- sector 0 ------------
323 // ;; 0
324 a->nop(); // 1
325 a->fpnop0(); // 2
326 a->fpnop1(); // 3
327 a->addi(R4,R4, -1); // 4
328
329 // ;; 1
330 a->nop(); // 5
331 a->fmr(F6, F6); // 6
332 a->fmr(F7, F7); // 7
333 a->endgroup(); // 8
334 // ------- sector 8 ------------
335
336 // ;; 2
337 a->nop(); // 9
338 a->nop(); // 10
339 a->fmr(F8, F8); // 11
340 a->fmr(F9, F9); // 12
341
342 // ;; 3
343 a->nop(); // 13
344 a->fmr(F10, F10); // 14
345 a->fmr(F11, F11); // 15
346 a->endgroup(); // 16
347 // -------- sector 16 -------------
348
349 // ;; 4
350 a->nop(); // 17
351 a->nop(); // 18
352 a->fmr(F15, F15); // 19
353 a->fmr(F16, F16); // 20
354
355 // ;; 5
356 a->nop(); // 21
357 a->fmr(F17, F17); // 22
358 a->fmr(F18, F18); // 23
359 a->endgroup(); // 24
360 // ------- sector 24 ------------
361
362 // ;; 6
363 a->nop(); // 25
364 a->nop(); // 26
365 a->fmr(F19, F19); // 27
366 a->fmr(F20, F20); // 28
367
368 // ;; 7
369 a->nop(); // 29
370 a->fmr(F21, F21); // 30
371 a->fmr(F22, F22); // 31
372 a->brnop0(); // 32
373
374 // ------- sector 32 ------------
375 }
376
377 // ;; 8
378 a->cmpdi(CCR0, R4, unroll); // 33
379 a->bge(CCR0, l1); // 34
380 a->blr();
381
382 // Emit code.
383 void (*test2)() = (void(*)())(void *)a->function_entry();
384 // uint32_t *code = (uint32_t *)a->pc();
385
386 Label l2;
387
388 a->li(R4, 1);
389 a->sldi(R4, R4, 28);
390 a->b(l2);
391 a->align(CodeEntryAlignment);
392
393 a->bind(l2);
394
395 for (int i = 0; i < unroll; i++) {
396 // Schleife 2
397 // ------- sector 0 ------------
398 // ;; 0
399 a->brnop0(); // 1
400 a->nop(); // 2
401 //a->cmpdi(CCR0, R4, unroll);
402 a->fpnop0(); // 3
403 a->fpnop1(); // 4
404 a->addi(R4,R4, -1); // 5
405
406 // ;; 1
407
408 a->nop(); // 6
409 a->fmr(F6, F6); // 7
410 a->fmr(F7, F7); // 8
411 // ------- sector 8 ---------------
412
413 // ;; 2
414 a->endgroup(); // 9
415
416 // ;; 3
417 a->nop(); // 10
418 a->nop(); // 11
419 a->fmr(F8, F8); // 12
420
421 // ;; 4
422 a->fmr(F9, F9); // 13
423 a->nop(); // 14
424 a->fmr(F10, F10); // 15
425
426 // ;; 5
427 a->fmr(F11, F11); // 16
428 // -------- sector 16 -------------
429
430 // ;; 6
431 a->endgroup(); // 17
432
433 // ;; 7
434 a->nop(); // 18
435 a->nop(); // 19
436 a->fmr(F15, F15); // 20
437
438 // ;; 8
439 a->fmr(F16, F16); // 21
440 a->nop(); // 22
441 a->fmr(F17, F17); // 23
442
443 // ;; 9
444 a->fmr(F18, F18); // 24
445 // -------- sector 24 -------------
446
447 // ;; 10
448 a->endgroup(); // 25
449
450 // ;; 11
451 a->nop(); // 26
452 a->nop(); // 27
453 a->fmr(F19, F19); // 28
454
455 // ;; 12
456 a->fmr(F20, F20); // 29
457 a->nop(); // 30
458 a->fmr(F21, F21); // 31
459
460 // ;; 13
461 a->fmr(F22, F22); // 32
462 }
463
464 // -------- sector 32 -------------
465 // ;; 14
466 a->cmpdi(CCR0, R4, unroll); // 33
467 a->bge(CCR0, l2); // 34
468
469 a->blr();
470 uint32_t *code_end = (uint32_t *)a->pc();
471 a->flush();
472
473 double loop1_seconds,loop2_seconds, rel_diff;
474 uint64_t start1, stop1;
475
476 start1 = os::current_thread_cpu_time(false);
477 (*test1)();
478 stop1 = os::current_thread_cpu_time(false);
479 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
480
481
482 start1 = os::current_thread_cpu_time(false);
483 (*test2)();
484 stop1 = os::current_thread_cpu_time(false);
485
486 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
487
488 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
489
490 if (PrintAssembly) {
491 ttyLocker ttyl;
492 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
493 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
494 tty->print_cr("Time loop1 :%f", loop1_seconds);
495 tty->print_cr("Time loop2 :%f", loop2_seconds);
496 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
497
498 if (rel_diff > 12.0) {
499 tty->print_cr("Section Size 8 Instructions");
500 } else{
501 tty->print_cr("Section Size 32 Instructions or Power5");
502 }
503 }
504
505 #if 0 // TODO: PPC port
506 // Set sector size (if not set explicitly).
507 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
508 if (rel_diff > 12.0) {
509 PdScheduling::power6SectorSize = 0x20;
510 } else {
511 PdScheduling::power6SectorSize = 0x80;
512 }
513 } else if (Power6SectorSize128PPC64) {
514 PdScheduling::power6SectorSize = 0x80;
515 } else {
516 PdScheduling::power6SectorSize = 0x20;
517 }
518 #endif
519 if (UsePower6SchedulerPPC64) Unimplemented();
520 }
521 #endif // COMPILER2
522
523 void VM_Version::determine_features() {
524 #if defined(ABI_ELFv2)
525 // 1 InstWord per call for the blr instruction.
526 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
527 #else
528 // 7 InstWords for each call (function descriptor + blr instruction).
529 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
530 #endif
531 int features = 0;
532
533 // create test area
534 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
535 char test_area[BUFFER_SIZE];
536 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
537
538 // Allocate space for the code.
539 ResourceMark rm;
540 CodeBuffer cb("detect_cpu_features", code_size, 0);
541 MacroAssembler* a = new MacroAssembler(&cb);
542
543 // Must be set to true so we can generate the test code.
544 _features = VM_Version::all_features_m;
545
546 // Emit code.
547 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
548 uint32_t *code = (uint32_t *)a->pc();
549 // Don't use R0 in ldarx.
550 // Keep R3_ARG1 unmodified, it contains &field (see below).
551 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
552 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
553 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
554 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
555 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
556 a->cmpb(R7, R5, R6); // code[4] -> cmpb
557 a->popcntb(R7, R5); // code[5] -> popcntb
558 a->popcntw(R7, R5); // code[6] -> popcntw
559 a->fcfids(F3, F4); // code[7] -> fcfids
560 a->vand(VR0, VR0, VR0); // code[8] -> vand
561 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
562 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
563 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
564 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
565 a->tcheck(0); // code[12] -> tcheck
566 a->blr();
567
568 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
569 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
570 a->dcbz(R3_ARG1); // R3_ARG1 = addr
571 a->blr();
572
573 uint32_t *code_end = (uint32_t *)a->pc();
574 a->flush();
575 _features = VM_Version::unknown_m;
576
577 // Print the detection code.
578 if (PrintAssembly) {
579 ttyLocker ttyl;
580 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
581 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
582 }
583
584 // Measure cache line size.
585 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
586 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
587 int count = 0; // count zeroed bytes
588 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
589 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
590 _measured_cache_line_size = count;
591
592 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
593 VM_Version::_is_determine_features_test_running = true;
594 // We must align the first argument to 16 bytes because of the lqarx check.
595 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
596 VM_Version::_is_determine_features_test_running = false;
597
598 // determine which instructions are legal.
599 int feature_cntr = 0;
600 if (code[feature_cntr++]) features |= fsqrt_m;
601 if (code[feature_cntr++]) features |= fsqrts_m;
602 if (code[feature_cntr++]) features |= isel_m;
603 if (code[feature_cntr++]) features |= lxarxeh_m;
604 if (code[feature_cntr++]) features |= cmpb_m;
605 if (code[feature_cntr++]) features |= popcntb_m;
606 if (code[feature_cntr++]) features |= popcntw_m;
607 if (code[feature_cntr++]) features |= fcfids_m;
608 if (code[feature_cntr++]) features |= vand_m;
609 if (code[feature_cntr++]) features |= lqarx_m;
610 if (code[feature_cntr++]) features |= vcipher_m;
611 if (code[feature_cntr++]) features |= vpmsumb_m;
612 if (code[feature_cntr++]) features |= tcheck_m;
613
614 // Print the detection code.
615 if (PrintAssembly) {
616 ttyLocker ttyl;
617 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
618 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
619 }
620
621 _features = features;
622 }
623
624 // Power 8: Configure Data Stream Control Register.
625 void VM_Version::config_dscr() {
626 assert(has_tcheck(), "Only execute on Power 8 or later!");
627
628 // 7 InstWords for each call (function descriptor + blr instruction).
629 const int code_size = (2+2*7)*BytesPerInstWord;
630
631 // Allocate space for the code.
632 ResourceMark rm;
633 CodeBuffer cb("config_dscr", code_size, 0);
634 MacroAssembler* a = new MacroAssembler(&cb);
635
636 // Emit code.
637 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
638 uint32_t *code = (uint32_t *)a->pc();
639 a->mfdscr(R3);
640 a->blr();
641
642 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
643 a->mtdscr(R3);
644 a->blr();
645
646 uint32_t *code_end = (uint32_t *)a->pc();
647 a->flush();
648
649 // Print the detection code.
650 if (PrintAssembly) {
651 ttyLocker ttyl;
652 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
653 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
654 }
655
656 // Apply the configuration if needed.
657 uint64_t dscr_val = (*get_dscr)();
658 if (Verbose) {
659 tty->print_cr("dscr value was 0x%lx" , dscr_val);
660 }
661 bool change_requested = false;
662 if (DSCR_PPC64 != (uintx)-1) {
663 dscr_val = DSCR_PPC64;
664 change_requested = true;
665 }
666 if (DSCR_DPFD_PPC64 <= 7) {
667 uint64_t mask = 0x7;
668 if ((dscr_val & mask) != DSCR_DPFD_PPC64) {
669 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64);
670 change_requested = true;
671 }
672 }
673 if (DSCR_URG_PPC64 <= 7) {
674 uint64_t mask = 0x7 << 6;
675 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
676 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
677 change_requested = true;
678 }
679 }
680 if (change_requested) {
681 (*set_dscr)(dscr_val);
682 if (Verbose) {
683 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
684 }
685 }
686 }
687
688 static int saved_features = 0;
689
690 void VM_Version::allow_all() {
691 saved_features = _features;
692 _features = all_features_m;
693 }
694
695 void VM_Version::revert() {
696 _features = saved_features;
697 }