1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2012, 2015 SAP AG. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "runtime/java.hpp" 32 #include "runtime/os.hpp" 33 #include "runtime/stubCodeGenerator.hpp" 34 #include "utilities/defaultStream.hpp" 35 #include "utilities/globalDefinitions.hpp" 36 #include "vm_version_ppc.hpp" 37 38 # include <sys/sysinfo.h> 39 40 int VM_Version::_features = VM_Version::unknown_m; 41 int VM_Version::_measured_cache_line_size = 32; // pessimistic init value 42 const char* VM_Version::_features_str = ""; 43 bool VM_Version::_is_determine_features_test_running = false; 44 45 46 #define MSG(flag) \ 47 if (flag && !FLAG_IS_DEFAULT(flag)) \ 48 jio_fprintf(defaultStream::error_stream(), \ 49 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 50 " -XX:+" #flag " will be disabled!\n"); 51 52 void VM_Version::initialize() { 53 54 // Test which instructions are supported and measure cache line size. 55 determine_features(); 56 57 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 58 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 59 if (VM_Version::has_lqarx()) { 60 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 61 } else if (VM_Version::has_popcntw()) { 62 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 63 } else if (VM_Version::has_cmpb()) { 64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 65 } else if (VM_Version::has_popcntb()) { 66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 67 } else { 68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 69 } 70 } 71 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 || 72 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 || 73 PowerArchitecturePPC64 == 8, 74 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8"); 75 76 // Power 8: Configure Data Stream Control Register. 77 if (PowerArchitecturePPC64 >= 8) { 78 config_dscr(); 79 } 80 81 if (!UseSIGTRAP) { 82 MSG(TrapBasedICMissChecks); 83 MSG(TrapBasedNotEntrantChecks); 84 MSG(TrapBasedNullChecks); 85 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 86 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 87 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 88 } 89 90 #ifdef COMPILER2 91 if (!UseSIGTRAP) { 92 MSG(TrapBasedRangeChecks); 93 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 94 } 95 96 // On Power6 test for section size. 97 if (PowerArchitecturePPC64 == 6) { 98 determine_section_size(); 99 // TODO: PPC port } else { 100 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 101 } 102 103 MaxVectorSize = 8; 104 #endif 105 106 // Create and print feature-string. 107 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 108 jio_snprintf(buf, sizeof(buf), 109 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s", 110 (has_fsqrt() ? " fsqrt" : ""), 111 (has_isel() ? " isel" : ""), 112 (has_lxarxeh() ? " lxarxeh" : ""), 113 (has_cmpb() ? " cmpb" : ""), 114 //(has_mftgpr()? " mftgpr" : ""), 115 (has_popcntb() ? " popcntb" : ""), 116 (has_popcntw() ? " popcntw" : ""), 117 (has_fcfids() ? " fcfids" : ""), 118 (has_vand() ? " vand" : ""), 119 (has_lqarx() ? " lqarx" : ""), 120 (has_vcipher() ? " vcipher" : ""), 121 (has_vpmsumb() ? " vpmsumb" : ""), 122 (has_tcheck() ? " tcheck" : "") 123 // Make sure number of %s matches num_features! 124 ); 125 _features_str = os::strdup(buf); 126 if (Verbose) { 127 print_features(); 128 } 129 130 // PPC64 supports 8-byte compare-exchange operations (see 131 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 132 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 133 _supports_cx8 = true; 134 135 UseSSE = 0; // Only on x86 and x64 136 137 intx cache_line_size = _measured_cache_line_size; 138 139 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 140 141 if (AllocatePrefetchStyle == 4) { 142 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 143 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 144 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 145 } else { 146 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 148 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 149 } 150 151 assert(AllocatePrefetchLines > 0, "invalid value"); 152 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 153 AllocatePrefetchLines = 1; // Conservative value. 154 } 155 156 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 157 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 158 } 159 160 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 161 162 if (UseCRC32Intrinsics) { 163 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) 164 warning("CRC32 intrinsics are not available on this CPU"); 165 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 166 } 167 168 // The AES intrinsic stubs require AES instruction support. 169 if (UseAES) { 170 warning("AES instructions are not available on this CPU"); 171 FLAG_SET_DEFAULT(UseAES, false); 172 } 173 if (UseAESIntrinsics) { 174 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 175 warning("AES intrinsics are not available on this CPU"); 176 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 177 } 178 179 if (UseGHASHIntrinsics) { 180 warning("GHASH intrinsics are not available on this CPU"); 181 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 182 } 183 184 if (UseSHA) { 185 warning("SHA instructions are not available on this CPU"); 186 FLAG_SET_DEFAULT(UseSHA, false); 187 } 188 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 189 warning("SHA intrinsics are not available on this CPU"); 190 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 191 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 192 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 193 } 194 195 if (UseCRC32CIntrinsics) { 196 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) 197 warning("CRC32C intrinsics are not available on this CPU"); 198 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 199 } 200 201 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 202 UseMultiplyToLenIntrinsic = true; 203 } 204 205 // Adjust RTM (Restricted Transactional Memory) flags. 206 if (!has_tcheck() && UseRTMLocking) { 207 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 208 // setting during arguments processing. See use_biased_locking(). 209 // VM_Version_init() is executed after UseBiasedLocking is used 210 // in Thread::allocate(). 211 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 212 } 213 214 if (UseRTMLocking) { 215 #if INCLUDE_RTM_OPT 216 if (!UnlockExperimentalVMOptions) { 217 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. " 218 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 219 } else { 220 warning("UseRTMLocking is only available as experimental option on this platform."); 221 } 222 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 223 // RTM locking should be used only for applications with 224 // high lock contention. For now we do not use it by default. 225 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 226 } 227 if (!is_power_of_2(RTMTotalCountIncrRate)) { 228 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 229 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 230 } 231 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 232 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 233 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 234 } 235 guarantee(RTMSpinLoopCount > 0, "unsupported"); 236 #else 237 // Only C2 does RTM locking optimization. 238 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 239 // setting during arguments processing. See use_biased_locking(). 240 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 241 #endif 242 } else { // !UseRTMLocking 243 if (UseRTMForStackLocks) { 244 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 245 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 246 } 247 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 248 } 249 if (UseRTMDeopt) { 250 FLAG_SET_DEFAULT(UseRTMDeopt, false); 251 } 252 if (PrintPreciseRTMLockingStatistics) { 253 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 254 } 255 } 256 257 // This machine does not allow unaligned memory accesses 258 if (UseUnalignedAccesses) { 259 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) 260 warning("Unaligned memory access is not available on this CPU"); 261 FLAG_SET_DEFAULT(UseUnalignedAccesses, false); 262 } 263 } 264 265 bool VM_Version::use_biased_locking() { 266 #if INCLUDE_RTM_OPT 267 // RTM locking is most useful when there is high lock contention and 268 // low data contention. With high lock contention the lock is usually 269 // inflated and biased locking is not suitable for that case. 270 // RTM locking code requires that biased locking is off. 271 // Note: we can't switch off UseBiasedLocking in get_processor_features() 272 // because it is used by Thread::allocate() which is called before 273 // VM_Version::initialize(). 274 if (UseRTMLocking && UseBiasedLocking) { 275 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 276 FLAG_SET_DEFAULT(UseBiasedLocking, false); 277 } else { 278 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 279 UseBiasedLocking = false; 280 } 281 } 282 #endif 283 return UseBiasedLocking; 284 } 285 286 void VM_Version::print_features() { 287 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size()); 288 } 289 290 #ifdef COMPILER2 291 // Determine section size on power6: If section size is 8 instructions, 292 // there should be a difference between the two testloops of ~15 %. If 293 // no difference is detected the section is assumed to be 32 instructions. 294 void VM_Version::determine_section_size() { 295 296 int unroll = 80; 297 298 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 299 300 // Allocate space for the code. 301 ResourceMark rm; 302 CodeBuffer cb("detect_section_size", code_size, 0); 303 MacroAssembler* a = new MacroAssembler(&cb); 304 305 uint32_t *code = (uint32_t *)a->pc(); 306 // Emit code. 307 void (*test1)() = (void(*)())(void *)a->function_entry(); 308 309 Label l1; 310 311 a->li(R4, 1); 312 a->sldi(R4, R4, 28); 313 a->b(l1); 314 a->align(CodeEntryAlignment); 315 316 a->bind(l1); 317 318 for (int i = 0; i < unroll; i++) { 319 // Schleife 1 320 // ------- sector 0 ------------ 321 // ;; 0 322 a->nop(); // 1 323 a->fpnop0(); // 2 324 a->fpnop1(); // 3 325 a->addi(R4,R4, -1); // 4 326 327 // ;; 1 328 a->nop(); // 5 329 a->fmr(F6, F6); // 6 330 a->fmr(F7, F7); // 7 331 a->endgroup(); // 8 332 // ------- sector 8 ------------ 333 334 // ;; 2 335 a->nop(); // 9 336 a->nop(); // 10 337 a->fmr(F8, F8); // 11 338 a->fmr(F9, F9); // 12 339 340 // ;; 3 341 a->nop(); // 13 342 a->fmr(F10, F10); // 14 343 a->fmr(F11, F11); // 15 344 a->endgroup(); // 16 345 // -------- sector 16 ------------- 346 347 // ;; 4 348 a->nop(); // 17 349 a->nop(); // 18 350 a->fmr(F15, F15); // 19 351 a->fmr(F16, F16); // 20 352 353 // ;; 5 354 a->nop(); // 21 355 a->fmr(F17, F17); // 22 356 a->fmr(F18, F18); // 23 357 a->endgroup(); // 24 358 // ------- sector 24 ------------ 359 360 // ;; 6 361 a->nop(); // 25 362 a->nop(); // 26 363 a->fmr(F19, F19); // 27 364 a->fmr(F20, F20); // 28 365 366 // ;; 7 367 a->nop(); // 29 368 a->fmr(F21, F21); // 30 369 a->fmr(F22, F22); // 31 370 a->brnop0(); // 32 371 372 // ------- sector 32 ------------ 373 } 374 375 // ;; 8 376 a->cmpdi(CCR0, R4, unroll); // 33 377 a->bge(CCR0, l1); // 34 378 a->blr(); 379 380 // Emit code. 381 void (*test2)() = (void(*)())(void *)a->function_entry(); 382 // uint32_t *code = (uint32_t *)a->pc(); 383 384 Label l2; 385 386 a->li(R4, 1); 387 a->sldi(R4, R4, 28); 388 a->b(l2); 389 a->align(CodeEntryAlignment); 390 391 a->bind(l2); 392 393 for (int i = 0; i < unroll; i++) { 394 // Schleife 2 395 // ------- sector 0 ------------ 396 // ;; 0 397 a->brnop0(); // 1 398 a->nop(); // 2 399 //a->cmpdi(CCR0, R4, unroll); 400 a->fpnop0(); // 3 401 a->fpnop1(); // 4 402 a->addi(R4,R4, -1); // 5 403 404 // ;; 1 405 406 a->nop(); // 6 407 a->fmr(F6, F6); // 7 408 a->fmr(F7, F7); // 8 409 // ------- sector 8 --------------- 410 411 // ;; 2 412 a->endgroup(); // 9 413 414 // ;; 3 415 a->nop(); // 10 416 a->nop(); // 11 417 a->fmr(F8, F8); // 12 418 419 // ;; 4 420 a->fmr(F9, F9); // 13 421 a->nop(); // 14 422 a->fmr(F10, F10); // 15 423 424 // ;; 5 425 a->fmr(F11, F11); // 16 426 // -------- sector 16 ------------- 427 428 // ;; 6 429 a->endgroup(); // 17 430 431 // ;; 7 432 a->nop(); // 18 433 a->nop(); // 19 434 a->fmr(F15, F15); // 20 435 436 // ;; 8 437 a->fmr(F16, F16); // 21 438 a->nop(); // 22 439 a->fmr(F17, F17); // 23 440 441 // ;; 9 442 a->fmr(F18, F18); // 24 443 // -------- sector 24 ------------- 444 445 // ;; 10 446 a->endgroup(); // 25 447 448 // ;; 11 449 a->nop(); // 26 450 a->nop(); // 27 451 a->fmr(F19, F19); // 28 452 453 // ;; 12 454 a->fmr(F20, F20); // 29 455 a->nop(); // 30 456 a->fmr(F21, F21); // 31 457 458 // ;; 13 459 a->fmr(F22, F22); // 32 460 } 461 462 // -------- sector 32 ------------- 463 // ;; 14 464 a->cmpdi(CCR0, R4, unroll); // 33 465 a->bge(CCR0, l2); // 34 466 467 a->blr(); 468 uint32_t *code_end = (uint32_t *)a->pc(); 469 a->flush(); 470 471 double loop1_seconds,loop2_seconds, rel_diff; 472 uint64_t start1, stop1; 473 474 start1 = os::current_thread_cpu_time(false); 475 (*test1)(); 476 stop1 = os::current_thread_cpu_time(false); 477 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 478 479 480 start1 = os::current_thread_cpu_time(false); 481 (*test2)(); 482 stop1 = os::current_thread_cpu_time(false); 483 484 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 485 486 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 487 488 if (PrintAssembly) { 489 ttyLocker ttyl; 490 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 491 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 492 tty->print_cr("Time loop1 :%f", loop1_seconds); 493 tty->print_cr("Time loop2 :%f", loop2_seconds); 494 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 495 496 if (rel_diff > 12.0) { 497 tty->print_cr("Section Size 8 Instructions"); 498 } else{ 499 tty->print_cr("Section Size 32 Instructions or Power5"); 500 } 501 } 502 503 #if 0 // TODO: PPC port 504 // Set sector size (if not set explicitly). 505 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 506 if (rel_diff > 12.0) { 507 PdScheduling::power6SectorSize = 0x20; 508 } else { 509 PdScheduling::power6SectorSize = 0x80; 510 } 511 } else if (Power6SectorSize128PPC64) { 512 PdScheduling::power6SectorSize = 0x80; 513 } else { 514 PdScheduling::power6SectorSize = 0x20; 515 } 516 #endif 517 if (UsePower6SchedulerPPC64) Unimplemented(); 518 } 519 #endif // COMPILER2 520 521 void VM_Version::determine_features() { 522 #if defined(ABI_ELFv2) 523 // 1 InstWord per call for the blr instruction. 524 const int code_size = (num_features+1+2*1)*BytesPerInstWord; 525 #else 526 // 7 InstWords for each call (function descriptor + blr instruction). 527 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 528 #endif 529 int features = 0; 530 531 // create test area 532 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 533 char test_area[BUFFER_SIZE]; 534 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 535 536 // Allocate space for the code. 537 ResourceMark rm; 538 CodeBuffer cb("detect_cpu_features", code_size, 0); 539 MacroAssembler* a = new MacroAssembler(&cb); 540 541 // Must be set to true so we can generate the test code. 542 _features = VM_Version::all_features_m; 543 544 // Emit code. 545 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 546 uint32_t *code = (uint32_t *)a->pc(); 547 // Don't use R0 in ldarx. 548 // Keep R3_ARG1 unmodified, it contains &field (see below). 549 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 550 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 551 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 552 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 553 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 554 a->cmpb(R7, R5, R6); // code[4] -> cmpb 555 a->popcntb(R7, R5); // code[5] -> popcntb 556 a->popcntw(R7, R5); // code[6] -> popcntw 557 a->fcfids(F3, F4); // code[7] -> fcfids 558 a->vand(VR0, VR0, VR0); // code[8] -> vand 559 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16 560 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m 561 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher 562 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb 563 a->tcheck(0); // code[12] -> tcheck 564 a->blr(); 565 566 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 567 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 568 a->dcbz(R3_ARG1); // R3_ARG1 = addr 569 a->blr(); 570 571 uint32_t *code_end = (uint32_t *)a->pc(); 572 a->flush(); 573 _features = VM_Version::unknown_m; 574 575 // Print the detection code. 576 if (PrintAssembly) { 577 ttyLocker ttyl; 578 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 579 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 580 } 581 582 // Measure cache line size. 583 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 584 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 585 int count = 0; // count zeroed bytes 586 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 587 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 588 _measured_cache_line_size = count; 589 590 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 591 VM_Version::_is_determine_features_test_running = true; 592 // We must align the first argument to 16 bytes because of the lqarx check. 593 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0); 594 VM_Version::_is_determine_features_test_running = false; 595 596 // determine which instructions are legal. 597 int feature_cntr = 0; 598 if (code[feature_cntr++]) features |= fsqrt_m; 599 if (code[feature_cntr++]) features |= fsqrts_m; 600 if (code[feature_cntr++]) features |= isel_m; 601 if (code[feature_cntr++]) features |= lxarxeh_m; 602 if (code[feature_cntr++]) features |= cmpb_m; 603 if (code[feature_cntr++]) features |= popcntb_m; 604 if (code[feature_cntr++]) features |= popcntw_m; 605 if (code[feature_cntr++]) features |= fcfids_m; 606 if (code[feature_cntr++]) features |= vand_m; 607 if (code[feature_cntr++]) features |= lqarx_m; 608 if (code[feature_cntr++]) features |= vcipher_m; 609 if (code[feature_cntr++]) features |= vpmsumb_m; 610 if (code[feature_cntr++]) features |= tcheck_m; 611 612 // Print the detection code. 613 if (PrintAssembly) { 614 ttyLocker ttyl; 615 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 616 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 617 } 618 619 _features = features; 620 } 621 622 // Power 8: Configure Data Stream Control Register. 623 void VM_Version::config_dscr() { 624 assert(has_tcheck(), "Only execute on Power 8 or later!"); 625 626 // 7 InstWords for each call (function descriptor + blr instruction). 627 const int code_size = (2+2*7)*BytesPerInstWord; 628 629 // Allocate space for the code. 630 ResourceMark rm; 631 CodeBuffer cb("config_dscr", code_size, 0); 632 MacroAssembler* a = new MacroAssembler(&cb); 633 634 // Emit code. 635 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 636 uint32_t *code = (uint32_t *)a->pc(); 637 a->mfdscr(R3); 638 a->blr(); 639 640 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 641 a->mtdscr(R3); 642 a->blr(); 643 644 uint32_t *code_end = (uint32_t *)a->pc(); 645 a->flush(); 646 647 // Print the detection code. 648 if (PrintAssembly) { 649 ttyLocker ttyl; 650 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code)); 651 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 652 } 653 654 // Apply the configuration if needed. 655 uint64_t dscr_val = (*get_dscr)(); 656 if (Verbose) { 657 tty->print_cr("dscr value was 0x%lx" , dscr_val); 658 } 659 bool change_requested = false; 660 if (DSCR_PPC64 != (uintx)-1) { 661 dscr_val = DSCR_PPC64; 662 change_requested = true; 663 } 664 if (DSCR_DPFD_PPC64 <= 7) { 665 uint64_t mask = 0x7; 666 if ((dscr_val & mask) != DSCR_DPFD_PPC64) { 667 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64); 668 change_requested = true; 669 } 670 } 671 if (DSCR_URG_PPC64 <= 7) { 672 uint64_t mask = 0x7 << 6; 673 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 674 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 675 change_requested = true; 676 } 677 } 678 if (change_requested) { 679 (*set_dscr)(dscr_val); 680 if (Verbose) { 681 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 682 } 683 } 684 } 685 686 static int saved_features = 0; 687 688 void VM_Version::allow_all() { 689 saved_features = _features; 690 _features = all_features_m; 691 } 692 693 void VM_Version::revert() { 694 _features = saved_features; 695 }