142 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
143 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
144 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
145 } else {
146 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
148 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
149 }
150
151 assert(AllocatePrefetchLines > 0, "invalid value");
152 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
153 AllocatePrefetchLines = 1; // Conservative value.
154 }
155
156 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
157 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
158 }
159
160 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
161
162 if (UseCRC32Intrinsics) {
163 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
164 warning("CRC32 intrinsics are not available on this CPU");
165 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
166 }
167
168 // The AES intrinsic stubs require AES instruction support.
169 if (UseAES) {
170 warning("AES instructions are not available on this CPU");
171 FLAG_SET_DEFAULT(UseAES, false);
172 }
173 if (UseAESIntrinsics) {
174 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
175 warning("AES intrinsics are not available on this CPU");
176 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
177 }
178
179 if (UseGHASHIntrinsics) {
180 warning("GHASH intrinsics are not available on this CPU");
181 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
182 }
183
184 if (UseSHA) {
185 warning("SHA instructions are not available on this CPU");
186 FLAG_SET_DEFAULT(UseSHA, false);
187 }
188 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
189 warning("SHA intrinsics are not available on this CPU");
190 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
191 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
192 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
193 }
194
195 if (UseCRC32CIntrinsics) {
196 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
197 warning("CRC32C intrinsics are not available on this CPU");
198 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
199 }
200
201 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
202 UseMultiplyToLenIntrinsic = true;
203 }
204
205 // Adjust RTM (Restricted Transactional Memory) flags.
206 if (!has_tcheck() && UseRTMLocking) {
207 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
208 // setting during arguments processing. See use_biased_locking().
209 // VM_Version_init() is executed after UseBiasedLocking is used
210 // in Thread::allocate().
211 vm_exit_during_initialization("RTM instructions are not available on this CPU");
212 }
213
214 if (UseRTMLocking) {
215 #if INCLUDE_RTM_OPT
216 if (!UnlockExperimentalVMOptions) {
217 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
218 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
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142 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
143 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
144 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
145 } else {
146 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
148 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
149 }
150
151 assert(AllocatePrefetchLines > 0, "invalid value");
152 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
153 AllocatePrefetchLines = 1; // Conservative value.
154 }
155
156 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
157 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
158 }
159
160 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
161
162 // Implementation does not use any of the vector instructions
163 // available with Power8. Their exploitation is still pending.
164 if (!UseCRC32Intrinsics) {
165 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
166 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
167 }
168 }
169
170 if (UseCRC32CIntrinsics) {
171 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
172 warning("CRC32C intrinsics are not available on this CPU");
173 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
174 }
175
176 // The AES intrinsic stubs require AES instruction support.
177 if (UseAES) {
178 warning("AES instructions are not available on this CPU");
179 FLAG_SET_DEFAULT(UseAES, false);
180 }
181 if (UseAESIntrinsics) {
182 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
183 warning("AES intrinsics are not available on this CPU");
184 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
185 }
186
187 if (UseGHASHIntrinsics) {
188 warning("GHASH intrinsics are not available on this CPU");
189 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
190 }
191
192 if (UseSHA) {
193 warning("SHA instructions are not available on this CPU");
194 FLAG_SET_DEFAULT(UseSHA, false);
195 }
196 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
197 warning("SHA intrinsics are not available on this CPU");
198 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
199 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
200 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
201 }
202
203 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
204 UseMultiplyToLenIntrinsic = true;
205 }
206
207 // Adjust RTM (Restricted Transactional Memory) flags.
208 if (!has_tcheck() && UseRTMLocking) {
209 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
210 // setting during arguments processing. See use_biased_locking().
211 // VM_Version_init() is executed after UseBiasedLocking is used
212 // in Thread::allocate().
213 vm_exit_during_initialization("RTM instructions are not available on this CPU");
214 }
215
216 if (UseRTMLocking) {
217 #if INCLUDE_RTM_OPT
218 if (!UnlockExperimentalVMOptions) {
219 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
220 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
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