1 /*
   2  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/barrierSet.hpp"
  36 #include "gc/shared/cardTableModRefBS.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "nativeInst_x86.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "vmreg_x86.inline.hpp"
  42 
  43 
  44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  45 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  46 // fast versions of NegF/NegD and AbsF/AbsD.
  47 
  48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  50   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  51   // of 128-bits operands for SSE instructions.
  52   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  53   // Store the value to a 128-bits operand.
  54   operand[0] = lo;
  55   operand[1] = hi;
  56   return operand;
  57 }
  58 
  59 // Buffer for 128-bits masks used by SSE instructions.
  60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  61 
  62 // Static initialization during VM startup.
  63 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  65 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  67 
  68 
  69 
  70 NEEDS_CLEANUP // remove this definitions ?
  71 const Register IC_Klass    = rax;   // where the IC klass is cached
  72 const Register SYNC_header = rax;   // synchronization header
  73 const Register SHIFT_count = rcx;   // where count for shift operations must be
  74 
  75 #define __ _masm->
  76 
  77 
  78 static void select_different_registers(Register preserve,
  79                                        Register extra,
  80                                        Register &tmp1,
  81                                        Register &tmp2) {
  82   if (tmp1 == preserve) {
  83     assert_different_registers(tmp1, tmp2, extra);
  84     tmp1 = extra;
  85   } else if (tmp2 == preserve) {
  86     assert_different_registers(tmp1, tmp2, extra);
  87     tmp2 = extra;
  88   }
  89   assert_different_registers(preserve, tmp1, tmp2);
  90 }
  91 
  92 
  93 
  94 static void select_different_registers(Register preserve,
  95                                        Register extra,
  96                                        Register &tmp1,
  97                                        Register &tmp2,
  98                                        Register &tmp3) {
  99   if (tmp1 == preserve) {
 100     assert_different_registers(tmp1, tmp2, tmp3, extra);
 101     tmp1 = extra;
 102   } else if (tmp2 == preserve) {
 103     assert_different_registers(tmp1, tmp2, tmp3, extra);
 104     tmp2 = extra;
 105   } else if (tmp3 == preserve) {
 106     assert_different_registers(tmp1, tmp2, tmp3, extra);
 107     tmp3 = extra;
 108   }
 109   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 110 }
 111 
 112 
 113 
 114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 115   if (opr->is_constant()) {
 116     LIR_Const* constant = opr->as_constant_ptr();
 117     switch (constant->type()) {
 118       case T_INT: {
 119         return true;
 120       }
 121 
 122       default:
 123         return false;
 124     }
 125   }
 126   return false;
 127 }
 128 
 129 
 130 LIR_Opr LIR_Assembler::receiverOpr() {
 131   return FrameMap::receiver_opr;
 132 }
 133 
 134 LIR_Opr LIR_Assembler::osrBufferPointer() {
 135   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 136 }
 137 
 138 //--------------fpu register translations-----------------------
 139 
 140 
 141 address LIR_Assembler::float_constant(float f) {
 142   address const_addr = __ float_constant(f);
 143   if (const_addr == NULL) {
 144     bailout("const section overflow");
 145     return __ code()->consts()->start();
 146   } else {
 147     return const_addr;
 148   }
 149 }
 150 
 151 
 152 address LIR_Assembler::double_constant(double d) {
 153   address const_addr = __ double_constant(d);
 154   if (const_addr == NULL) {
 155     bailout("const section overflow");
 156     return __ code()->consts()->start();
 157   } else {
 158     return const_addr;
 159   }
 160 }
 161 
 162 
 163 void LIR_Assembler::set_24bit_FPU() {
 164   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
 165 }
 166 
 167 void LIR_Assembler::reset_FPU() {
 168   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 169 }
 170 
 171 void LIR_Assembler::fpop() {
 172   __ fpop();
 173 }
 174 
 175 void LIR_Assembler::fxch(int i) {
 176   __ fxch(i);
 177 }
 178 
 179 void LIR_Assembler::fld(int i) {
 180   __ fld_s(i);
 181 }
 182 
 183 void LIR_Assembler::ffree(int i) {
 184   __ ffree(i);
 185 }
 186 
 187 void LIR_Assembler::breakpoint() {
 188   __ int3();
 189 }
 190 
 191 void LIR_Assembler::push(LIR_Opr opr) {
 192   if (opr->is_single_cpu()) {
 193     __ push_reg(opr->as_register());
 194   } else if (opr->is_double_cpu()) {
 195     NOT_LP64(__ push_reg(opr->as_register_hi()));
 196     __ push_reg(opr->as_register_lo());
 197   } else if (opr->is_stack()) {
 198     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 199   } else if (opr->is_constant()) {
 200     LIR_Const* const_opr = opr->as_constant_ptr();
 201     if (const_opr->type() == T_OBJECT) {
 202       __ push_oop(const_opr->as_jobject());
 203     } else if (const_opr->type() == T_INT) {
 204       __ push_jint(const_opr->as_jint());
 205     } else {
 206       ShouldNotReachHere();
 207     }
 208 
 209   } else {
 210     ShouldNotReachHere();
 211   }
 212 }
 213 
 214 void LIR_Assembler::pop(LIR_Opr opr) {
 215   if (opr->is_single_cpu()) {
 216     __ pop_reg(opr->as_register());
 217   } else {
 218     ShouldNotReachHere();
 219   }
 220 }
 221 
 222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 223   return addr->base()->is_illegal() && addr->index()->is_illegal();
 224 }
 225 
 226 //-------------------------------------------
 227 
 228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 229   return as_Address(addr, rscratch1);
 230 }
 231 
 232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 233   if (addr->base()->is_illegal()) {
 234     assert(addr->index()->is_illegal(), "must be illegal too");
 235     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 236     if (! __ reachable(laddr)) {
 237       __ movptr(tmp, laddr.addr());
 238       Address res(tmp, 0);
 239       return res;
 240     } else {
 241       return __ as_Address(laddr);
 242     }
 243   }
 244 
 245   Register base = addr->base()->as_pointer_register();
 246 
 247   if (addr->index()->is_illegal()) {
 248     return Address( base, addr->disp());
 249   } else if (addr->index()->is_cpu_register()) {
 250     Register index = addr->index()->as_pointer_register();
 251     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 252   } else if (addr->index()->is_constant()) {
 253     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 254     assert(Assembler::is_simm32(addr_offset), "must be");
 255 
 256     return Address(base, addr_offset);
 257   } else {
 258     Unimplemented();
 259     return Address();
 260   }
 261 }
 262 
 263 
 264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 265   Address base = as_Address(addr);
 266   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 267 }
 268 
 269 
 270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 271   return as_Address(addr);
 272 }
 273 
 274 
 275 void LIR_Assembler::osr_entry() {
 276   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 277   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 278   ValueStack* entry_state = osr_entry->state();
 279   int number_of_locks = entry_state->locks_size();
 280 
 281   // we jump here if osr happens with the interpreter
 282   // state set up to continue at the beginning of the
 283   // loop that triggered osr - in particular, we have
 284   // the following registers setup:
 285   //
 286   // rcx: osr buffer
 287   //
 288 
 289   // build frame
 290   ciMethod* m = compilation()->method();
 291   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 292 
 293   // OSR buffer is
 294   //
 295   // locals[nlocals-1..0]
 296   // monitors[0..number_of_locks]
 297   //
 298   // locals is a direct copy of the interpreter frame so in the osr buffer
 299   // so first slot in the local array is the last local from the interpreter
 300   // and last slot is local[0] (receiver) from the interpreter
 301   //
 302   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 303   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 304   // in the interpreter frame (the method lock if a sync method)
 305 
 306   // Initialize monitors in the compiled activation.
 307   //   rcx: pointer to osr buffer
 308   //
 309   // All other registers are dead at this point and the locals will be
 310   // copied into place by code emitted in the IR.
 311 
 312   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 313   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 314     int monitor_offset = BytesPerWord * method()->max_locals() +
 315       (2 * BytesPerWord) * (number_of_locks - 1);
 316     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 317     // the OSR buffer using 2 word entries: first the lock and then
 318     // the oop.
 319     for (int i = 0; i < number_of_locks; i++) {
 320       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 321 #ifdef ASSERT
 322       // verify the interpreter's monitor has a non-null object
 323       {
 324         Label L;
 325         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 326         __ jcc(Assembler::notZero, L);
 327         __ stop("locked object is NULL");
 328         __ bind(L);
 329       }
 330 #endif
 331       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 332       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 333       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 334       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 335     }
 336   }
 337 }
 338 
 339 
 340 // inline cache check; done before the frame is built.
 341 int LIR_Assembler::check_icache() {
 342   Register receiver = FrameMap::receiver_opr->as_register();
 343   Register ic_klass = IC_Klass;
 344   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 345   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 346   if (!do_post_padding) {
 347     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 348     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 349   }
 350   int offset = __ offset();
 351   __ inline_cache_check(receiver, IC_Klass);
 352   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 353   if (do_post_padding) {
 354     // force alignment after the cache check.
 355     // It's been verified to be aligned if !VerifyOops
 356     __ align(CodeEntryAlignment);
 357   }
 358   return offset;
 359 }
 360 
 361 
 362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 363   jobject o = NULL;
 364   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 365   __ movoop(reg, o);
 366   patching_epilog(patch, lir_patch_normal, reg, info);
 367 }
 368 
 369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 370   Metadata* o = NULL;
 371   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 372   __ mov_metadata(reg, o);
 373   patching_epilog(patch, lir_patch_normal, reg, info);
 374 }
 375 
 376 // This specifies the rsp decrement needed to build the frame
 377 int LIR_Assembler::initial_frame_size_in_bytes() const {
 378   // if rounding, must let FrameMap know!
 379 
 380   // The frame_map records size in slots (32bit word)
 381 
 382   // subtract two words to account for return address and link
 383   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 384 }
 385 
 386 
 387 int LIR_Assembler::emit_exception_handler() {
 388   // if the last instruction is a call (typically to do a throw which
 389   // is coming at the end after block reordering) the return address
 390   // must still point into the code area in order to avoid assertion
 391   // failures when searching for the corresponding bci => add a nop
 392   // (was bug 5/14/1999 - gri)
 393   __ nop();
 394 
 395   // generate code for exception handler
 396   address handler_base = __ start_a_stub(exception_handler_size);
 397   if (handler_base == NULL) {
 398     // not enough space left for the handler
 399     bailout("exception handler overflow");
 400     return -1;
 401   }
 402 
 403   int offset = code_offset();
 404 
 405   // the exception oop and pc are in rax, and rdx
 406   // no other registers need to be preserved, so invalidate them
 407   __ invalidate_registers(false, true, true, false, true, true);
 408 
 409   // check that there is really an exception
 410   __ verify_not_null_oop(rax);
 411 
 412   // search an exception handler (rax: exception oop, rdx: throwing pc)
 413   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 414   __ should_not_reach_here();
 415   guarantee(code_offset() - offset <= exception_handler_size, "overflow");
 416   __ end_a_stub();
 417 
 418   return offset;
 419 }
 420 
 421 
 422 // Emit the code to remove the frame from the stack in the exception
 423 // unwind path.
 424 int LIR_Assembler::emit_unwind_handler() {
 425 #ifndef PRODUCT
 426   if (CommentedAssembly) {
 427     _masm->block_comment("Unwind handler");
 428   }
 429 #endif
 430 
 431   int offset = code_offset();
 432 
 433   // Fetch the exception from TLS and clear out exception related thread state
 434   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 435   NOT_LP64(__ get_thread(rsi));
 436   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 437   __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
 438   __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
 439 
 440   __ bind(_unwind_handler_entry);
 441   __ verify_not_null_oop(rax);
 442   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 443     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 444   }
 445 
 446   // Preform needed unlocking
 447   MonitorExitStub* stub = NULL;
 448   if (method()->is_synchronized()) {
 449     monitor_address(0, FrameMap::rax_opr);
 450     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 451     __ unlock_object(rdi, rsi, rax, *stub->entry());
 452     __ bind(*stub->continuation());
 453   }
 454 
 455   if (compilation()->env()->dtrace_method_probes()) {
 456 #ifdef _LP64
 457     __ mov(rdi, r15_thread);
 458     __ mov_metadata(rsi, method()->constant_encoding());
 459 #else
 460     __ get_thread(rax);
 461     __ movptr(Address(rsp, 0), rax);
 462     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 463 #endif
 464     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 465   }
 466 
 467   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 468     __ mov(rax, rbx);  // Restore the exception
 469   }
 470 
 471   // remove the activation and dispatch to the unwind handler
 472   __ remove_frame(initial_frame_size_in_bytes());
 473   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 474 
 475   // Emit the slow path assembly
 476   if (stub != NULL) {
 477     stub->emit_code(this);
 478   }
 479 
 480   return offset;
 481 }
 482 
 483 
 484 int LIR_Assembler::emit_deopt_handler() {
 485   // if the last instruction is a call (typically to do a throw which
 486   // is coming at the end after block reordering) the return address
 487   // must still point into the code area in order to avoid assertion
 488   // failures when searching for the corresponding bci => add a nop
 489   // (was bug 5/14/1999 - gri)
 490   __ nop();
 491 
 492   // generate code for exception handler
 493   address handler_base = __ start_a_stub(deopt_handler_size);
 494   if (handler_base == NULL) {
 495     // not enough space left for the handler
 496     bailout("deopt handler overflow");
 497     return -1;
 498   }
 499 
 500   int offset = code_offset();
 501   InternalAddress here(__ pc());
 502 
 503   __ pushptr(here.addr());
 504   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 505   guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
 506   __ end_a_stub();
 507 
 508   return offset;
 509 }
 510 
 511 
 512 // This is the fast version of java.lang.String.compare; it has not
 513 // OSR-entry and therefore, we generate a slow version for OSR's
 514 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
 515   __ movptr (rbx, rcx); // receiver is in rcx
 516   __ movptr (rax, arg1->as_register());
 517 
 518   // Get addresses of first characters from both Strings
 519   __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
 520   if (java_lang_String::has_offset_field()) {
 521     __ movptr     (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
 522     __ movl       (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
 523     __ lea        (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 524   } else {
 525     __ movl       (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
 526     __ lea        (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 527   }
 528 
 529   // rbx, may be NULL
 530   add_debug_info_for_null_check_here(info);
 531   __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
 532   if (java_lang_String::has_offset_field()) {
 533     __ movptr     (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
 534     __ movl       (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
 535     __ lea        (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 536   } else {
 537     __ movl       (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
 538     __ lea        (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 539   }
 540 
 541   // compute minimum length (in rax) and difference of lengths (on top of stack)
 542   __ mov   (rcx, rbx);
 543   __ subptr(rbx, rax); // subtract lengths
 544   __ push  (rbx);      // result
 545   __ cmov  (Assembler::lessEqual, rax, rcx);
 546 
 547   // is minimum length 0?
 548   Label noLoop, haveResult;
 549   __ testptr (rax, rax);
 550   __ jcc (Assembler::zero, noLoop);
 551 
 552   // compare first characters
 553   __ load_unsigned_short(rcx, Address(rdi, 0));
 554   __ load_unsigned_short(rbx, Address(rsi, 0));
 555   __ subl(rcx, rbx);
 556   __ jcc(Assembler::notZero, haveResult);
 557   // starting loop
 558   __ decrement(rax); // we already tested index: skip one
 559   __ jcc(Assembler::zero, noLoop);
 560 
 561   // set rsi.edi to the end of the arrays (arrays have same length)
 562   // negate the index
 563 
 564   __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
 565   __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
 566   __ negptr(rax);
 567 
 568   // compare the strings in a loop
 569 
 570   Label loop;
 571   __ align(wordSize);
 572   __ bind(loop);
 573   __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
 574   __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
 575   __ subl(rcx, rbx);
 576   __ jcc(Assembler::notZero, haveResult);
 577   __ increment(rax);
 578   __ jcc(Assembler::notZero, loop);
 579 
 580   // strings are equal up to min length
 581 
 582   __ bind(noLoop);
 583   __ pop(rax);
 584   return_op(LIR_OprFact::illegalOpr);
 585 
 586   __ bind(haveResult);
 587   // leave instruction is going to discard the TOS value
 588   __ mov (rax, rcx); // result of call is in rax,
 589 }
 590 
 591 
 592 void LIR_Assembler::return_op(LIR_Opr result) {
 593   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 594   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 595     assert(result->fpu() == 0, "result must already be on TOS");
 596   }
 597 
 598   // Pop the stack before the safepoint code
 599   __ remove_frame(initial_frame_size_in_bytes());
 600 
 601   bool result_is_oop = result->is_valid() ? result->is_oop() : false;
 602 
 603   // Note: we do not need to round double result; float result has the right precision
 604   // the poll sets the condition code, but no data registers
 605   AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
 606 
 607   if (Assembler::is_polling_page_far()) {
 608     __ lea(rscratch1, polling_page);
 609     __ relocate(relocInfo::poll_return_type);
 610     __ testl(rax, Address(rscratch1, 0));
 611   } else {
 612     __ testl(rax, polling_page);
 613   }
 614   __ ret(0);
 615 }
 616 
 617 
 618 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 619   AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
 620   guarantee(info != NULL, "Shouldn't be NULL");
 621   int offset = __ offset();
 622   if (Assembler::is_polling_page_far()) {
 623     __ lea(rscratch1, polling_page);
 624     offset = __ offset();
 625     add_debug_info_for_branch(info);
 626     __ relocate(relocInfo::poll_type);
 627     __ testl(rax, Address(rscratch1, 0));
 628   } else {
 629     add_debug_info_for_branch(info);
 630     __ testl(rax, polling_page);
 631   }
 632   return offset;
 633 }
 634 
 635 
 636 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 637   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 638 }
 639 
 640 void LIR_Assembler::swap_reg(Register a, Register b) {
 641   __ xchgptr(a, b);
 642 }
 643 
 644 
 645 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 646   assert(src->is_constant(), "should not call otherwise");
 647   assert(dest->is_register(), "should not call otherwise");
 648   LIR_Const* c = src->as_constant_ptr();
 649 
 650   switch (c->type()) {
 651     case T_INT: {
 652       assert(patch_code == lir_patch_none, "no patching handled here");
 653       __ movl(dest->as_register(), c->as_jint());
 654       break;
 655     }
 656 
 657     case T_ADDRESS: {
 658       assert(patch_code == lir_patch_none, "no patching handled here");
 659       __ movptr(dest->as_register(), c->as_jint());
 660       break;
 661     }
 662 
 663     case T_LONG: {
 664       assert(patch_code == lir_patch_none, "no patching handled here");
 665 #ifdef _LP64
 666       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 667 #else
 668       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 669       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 670 #endif // _LP64
 671       break;
 672     }
 673 
 674     case T_OBJECT: {
 675       if (patch_code != lir_patch_none) {
 676         jobject2reg_with_patching(dest->as_register(), info);
 677       } else {
 678         __ movoop(dest->as_register(), c->as_jobject());
 679       }
 680       break;
 681     }
 682 
 683     case T_METADATA: {
 684       if (patch_code != lir_patch_none) {
 685         klass2reg_with_patching(dest->as_register(), info);
 686       } else {
 687         __ mov_metadata(dest->as_register(), c->as_metadata());
 688       }
 689       break;
 690     }
 691 
 692     case T_FLOAT: {
 693       if (dest->is_single_xmm()) {
 694         if (c->is_zero_float()) {
 695           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 696         } else {
 697           __ movflt(dest->as_xmm_float_reg(),
 698                    InternalAddress(float_constant(c->as_jfloat())));
 699         }
 700       } else {
 701         assert(dest->is_single_fpu(), "must be");
 702         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 703         if (c->is_zero_float()) {
 704           __ fldz();
 705         } else if (c->is_one_float()) {
 706           __ fld1();
 707         } else {
 708           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 709         }
 710       }
 711       break;
 712     }
 713 
 714     case T_DOUBLE: {
 715       if (dest->is_double_xmm()) {
 716         if (c->is_zero_double()) {
 717           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 718         } else {
 719           __ movdbl(dest->as_xmm_double_reg(),
 720                     InternalAddress(double_constant(c->as_jdouble())));
 721         }
 722       } else {
 723         assert(dest->is_double_fpu(), "must be");
 724         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 725         if (c->is_zero_double()) {
 726           __ fldz();
 727         } else if (c->is_one_double()) {
 728           __ fld1();
 729         } else {
 730           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 731         }
 732       }
 733       break;
 734     }
 735 
 736     default:
 737       ShouldNotReachHere();
 738   }
 739 }
 740 
 741 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 742   assert(src->is_constant(), "should not call otherwise");
 743   assert(dest->is_stack(), "should not call otherwise");
 744   LIR_Const* c = src->as_constant_ptr();
 745 
 746   switch (c->type()) {
 747     case T_INT:  // fall through
 748     case T_FLOAT:
 749       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 750       break;
 751 
 752     case T_ADDRESS:
 753       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 754       break;
 755 
 756     case T_OBJECT:
 757       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 758       break;
 759 
 760     case T_LONG:  // fall through
 761     case T_DOUBLE:
 762 #ifdef _LP64
 763       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 764                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 765 #else
 766       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 767                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 768       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 769                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 770 #endif // _LP64
 771       break;
 772 
 773     default:
 774       ShouldNotReachHere();
 775   }
 776 }
 777 
 778 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 779   assert(src->is_constant(), "should not call otherwise");
 780   assert(dest->is_address(), "should not call otherwise");
 781   LIR_Const* c = src->as_constant_ptr();
 782   LIR_Address* addr = dest->as_address_ptr();
 783 
 784   int null_check_here = code_offset();
 785   switch (type) {
 786     case T_INT:    // fall through
 787     case T_FLOAT:
 788       __ movl(as_Address(addr), c->as_jint_bits());
 789       break;
 790 
 791     case T_ADDRESS:
 792       __ movptr(as_Address(addr), c->as_jint_bits());
 793       break;
 794 
 795     case T_OBJECT:  // fall through
 796     case T_ARRAY:
 797       if (c->as_jobject() == NULL) {
 798         if (UseCompressedOops && !wide) {
 799           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 800         } else {
 801 #ifdef _LP64
 802           __ xorptr(rscratch1, rscratch1);
 803           null_check_here = code_offset();
 804           __ movptr(as_Address(addr), rscratch1);
 805 #else
 806           __ movptr(as_Address(addr), NULL_WORD);
 807 #endif
 808         }
 809       } else {
 810         if (is_literal_address(addr)) {
 811           ShouldNotReachHere();
 812           __ movoop(as_Address(addr, noreg), c->as_jobject());
 813         } else {
 814 #ifdef _LP64
 815           __ movoop(rscratch1, c->as_jobject());
 816           if (UseCompressedOops && !wide) {
 817             __ encode_heap_oop(rscratch1);
 818             null_check_here = code_offset();
 819             __ movl(as_Address_lo(addr), rscratch1);
 820           } else {
 821             null_check_here = code_offset();
 822             __ movptr(as_Address_lo(addr), rscratch1);
 823           }
 824 #else
 825           __ movoop(as_Address(addr), c->as_jobject());
 826 #endif
 827         }
 828       }
 829       break;
 830 
 831     case T_LONG:    // fall through
 832     case T_DOUBLE:
 833 #ifdef _LP64
 834       if (is_literal_address(addr)) {
 835         ShouldNotReachHere();
 836         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 837       } else {
 838         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 839         null_check_here = code_offset();
 840         __ movptr(as_Address_lo(addr), r10);
 841       }
 842 #else
 843       // Always reachable in 32bit so this doesn't produce useless move literal
 844       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 845       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 846 #endif // _LP64
 847       break;
 848 
 849     case T_BOOLEAN: // fall through
 850     case T_BYTE:
 851       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 852       break;
 853 
 854     case T_CHAR:    // fall through
 855     case T_SHORT:
 856       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 857       break;
 858 
 859     default:
 860       ShouldNotReachHere();
 861   };
 862 
 863   if (info != NULL) {
 864     add_debug_info_for_null_check(null_check_here, info);
 865   }
 866 }
 867 
 868 
 869 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 870   assert(src->is_register(), "should not call otherwise");
 871   assert(dest->is_register(), "should not call otherwise");
 872 
 873   // move between cpu-registers
 874   if (dest->is_single_cpu()) {
 875 #ifdef _LP64
 876     if (src->type() == T_LONG) {
 877       // Can do LONG -> OBJECT
 878       move_regs(src->as_register_lo(), dest->as_register());
 879       return;
 880     }
 881 #endif
 882     assert(src->is_single_cpu(), "must match");
 883     if (src->type() == T_OBJECT) {
 884       __ verify_oop(src->as_register());
 885     }
 886     move_regs(src->as_register(), dest->as_register());
 887 
 888   } else if (dest->is_double_cpu()) {
 889 #ifdef _LP64
 890     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 891       // Surprising to me but we can see move of a long to t_object
 892       __ verify_oop(src->as_register());
 893       move_regs(src->as_register(), dest->as_register_lo());
 894       return;
 895     }
 896 #endif
 897     assert(src->is_double_cpu(), "must match");
 898     Register f_lo = src->as_register_lo();
 899     Register f_hi = src->as_register_hi();
 900     Register t_lo = dest->as_register_lo();
 901     Register t_hi = dest->as_register_hi();
 902 #ifdef _LP64
 903     assert(f_hi == f_lo, "must be same");
 904     assert(t_hi == t_lo, "must be same");
 905     move_regs(f_lo, t_lo);
 906 #else
 907     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 908 
 909 
 910     if (f_lo == t_hi && f_hi == t_lo) {
 911       swap_reg(f_lo, f_hi);
 912     } else if (f_hi == t_lo) {
 913       assert(f_lo != t_hi, "overwriting register");
 914       move_regs(f_hi, t_hi);
 915       move_regs(f_lo, t_lo);
 916     } else {
 917       assert(f_hi != t_lo, "overwriting register");
 918       move_regs(f_lo, t_lo);
 919       move_regs(f_hi, t_hi);
 920     }
 921 #endif // LP64
 922 
 923     // special moves from fpu-register to xmm-register
 924     // necessary for method results
 925   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 926     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 927     __ fld_s(Address(rsp, 0));
 928   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 929     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 930     __ fld_d(Address(rsp, 0));
 931   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 932     __ fstp_s(Address(rsp, 0));
 933     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 934   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 935     __ fstp_d(Address(rsp, 0));
 936     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 937 
 938     // move between xmm-registers
 939   } else if (dest->is_single_xmm()) {
 940     assert(src->is_single_xmm(), "must match");
 941     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 942   } else if (dest->is_double_xmm()) {
 943     assert(src->is_double_xmm(), "must match");
 944     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 945 
 946     // move between fpu-registers (no instruction necessary because of fpu-stack)
 947   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 948     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 949     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 950   } else {
 951     ShouldNotReachHere();
 952   }
 953 }
 954 
 955 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 956   assert(src->is_register(), "should not call otherwise");
 957   assert(dest->is_stack(), "should not call otherwise");
 958 
 959   if (src->is_single_cpu()) {
 960     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 961     if (type == T_OBJECT || type == T_ARRAY) {
 962       __ verify_oop(src->as_register());
 963       __ movptr (dst, src->as_register());
 964     } else if (type == T_METADATA) {
 965       __ movptr (dst, src->as_register());
 966     } else {
 967       __ movl (dst, src->as_register());
 968     }
 969 
 970   } else if (src->is_double_cpu()) {
 971     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 972     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 973     __ movptr (dstLO, src->as_register_lo());
 974     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 975 
 976   } else if (src->is_single_xmm()) {
 977     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 978     __ movflt(dst_addr, src->as_xmm_float_reg());
 979 
 980   } else if (src->is_double_xmm()) {
 981     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 982     __ movdbl(dst_addr, src->as_xmm_double_reg());
 983 
 984   } else if (src->is_single_fpu()) {
 985     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 986     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 987     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 988     else                   __ fst_s  (dst_addr);
 989 
 990   } else if (src->is_double_fpu()) {
 991     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 992     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 993     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 994     else                   __ fst_d  (dst_addr);
 995 
 996   } else {
 997     ShouldNotReachHere();
 998   }
 999 }
1000 
1001 
1002 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
1003   LIR_Address* to_addr = dest->as_address_ptr();
1004   PatchingStub* patch = NULL;
1005   Register compressed_src = rscratch1;
1006 
1007   if (type == T_ARRAY || type == T_OBJECT) {
1008     __ verify_oop(src->as_register());
1009 #ifdef _LP64
1010     if (UseCompressedOops && !wide) {
1011       __ movptr(compressed_src, src->as_register());
1012       __ encode_heap_oop(compressed_src);
1013       if (patch_code != lir_patch_none) {
1014         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1015       }
1016     }
1017 #endif
1018   }
1019 
1020   if (patch_code != lir_patch_none) {
1021     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1022     Address toa = as_Address(to_addr);
1023     assert(toa.disp() != 0, "must have");
1024   }
1025 
1026   int null_check_here = code_offset();
1027   switch (type) {
1028     case T_FLOAT: {
1029       if (src->is_single_xmm()) {
1030         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1031       } else {
1032         assert(src->is_single_fpu(), "must be");
1033         assert(src->fpu_regnr() == 0, "argument must be on TOS");
1034         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
1035         else                    __ fst_s (as_Address(to_addr));
1036       }
1037       break;
1038     }
1039 
1040     case T_DOUBLE: {
1041       if (src->is_double_xmm()) {
1042         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1043       } else {
1044         assert(src->is_double_fpu(), "must be");
1045         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1046         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1047         else                    __ fst_d (as_Address(to_addr));
1048       }
1049       break;
1050     }
1051 
1052     case T_ARRAY:   // fall through
1053     case T_OBJECT:  // fall through
1054       if (UseCompressedOops && !wide) {
1055         __ movl(as_Address(to_addr), compressed_src);
1056       } else {
1057         __ movptr(as_Address(to_addr), src->as_register());
1058       }
1059       break;
1060     case T_METADATA:
1061       // We get here to store a method pointer to the stack to pass to
1062       // a dtrace runtime call. This can't work on 64 bit with
1063       // compressed klass ptrs: T_METADATA can be a compressed klass
1064       // ptr or a 64 bit method pointer.
1065       LP64_ONLY(ShouldNotReachHere());
1066       __ movptr(as_Address(to_addr), src->as_register());
1067       break;
1068     case T_ADDRESS:
1069       __ movptr(as_Address(to_addr), src->as_register());
1070       break;
1071     case T_INT:
1072       __ movl(as_Address(to_addr), src->as_register());
1073       break;
1074 
1075     case T_LONG: {
1076       Register from_lo = src->as_register_lo();
1077       Register from_hi = src->as_register_hi();
1078 #ifdef _LP64
1079       __ movptr(as_Address_lo(to_addr), from_lo);
1080 #else
1081       Register base = to_addr->base()->as_register();
1082       Register index = noreg;
1083       if (to_addr->index()->is_register()) {
1084         index = to_addr->index()->as_register();
1085       }
1086       if (base == from_lo || index == from_lo) {
1087         assert(base != from_hi, "can't be");
1088         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1089         __ movl(as_Address_hi(to_addr), from_hi);
1090         if (patch != NULL) {
1091           patching_epilog(patch, lir_patch_high, base, info);
1092           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1093           patch_code = lir_patch_low;
1094         }
1095         __ movl(as_Address_lo(to_addr), from_lo);
1096       } else {
1097         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1098         __ movl(as_Address_lo(to_addr), from_lo);
1099         if (patch != NULL) {
1100           patching_epilog(patch, lir_patch_low, base, info);
1101           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1102           patch_code = lir_patch_high;
1103         }
1104         __ movl(as_Address_hi(to_addr), from_hi);
1105       }
1106 #endif // _LP64
1107       break;
1108     }
1109 
1110     case T_BYTE:    // fall through
1111     case T_BOOLEAN: {
1112       Register src_reg = src->as_register();
1113       Address dst_addr = as_Address(to_addr);
1114       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1115       __ movb(dst_addr, src_reg);
1116       break;
1117     }
1118 
1119     case T_CHAR:    // fall through
1120     case T_SHORT:
1121       __ movw(as_Address(to_addr), src->as_register());
1122       break;
1123 
1124     default:
1125       ShouldNotReachHere();
1126   }
1127   if (info != NULL) {
1128     add_debug_info_for_null_check(null_check_here, info);
1129   }
1130 
1131   if (patch_code != lir_patch_none) {
1132     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1133   }
1134 }
1135 
1136 
1137 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1138   assert(src->is_stack(), "should not call otherwise");
1139   assert(dest->is_register(), "should not call otherwise");
1140 
1141   if (dest->is_single_cpu()) {
1142     if (type == T_ARRAY || type == T_OBJECT) {
1143       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1144       __ verify_oop(dest->as_register());
1145     } else if (type == T_METADATA) {
1146       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1147     } else {
1148       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1149     }
1150 
1151   } else if (dest->is_double_cpu()) {
1152     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1153     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1154     __ movptr(dest->as_register_lo(), src_addr_LO);
1155     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1156 
1157   } else if (dest->is_single_xmm()) {
1158     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1159     __ movflt(dest->as_xmm_float_reg(), src_addr);
1160 
1161   } else if (dest->is_double_xmm()) {
1162     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1163     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1164 
1165   } else if (dest->is_single_fpu()) {
1166     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1167     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1168     __ fld_s(src_addr);
1169 
1170   } else if (dest->is_double_fpu()) {
1171     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1172     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1173     __ fld_d(src_addr);
1174 
1175   } else {
1176     ShouldNotReachHere();
1177   }
1178 }
1179 
1180 
1181 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1182   if (src->is_single_stack()) {
1183     if (type == T_OBJECT || type == T_ARRAY) {
1184       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1185       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1186     } else {
1187 #ifndef _LP64
1188       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1189       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1190 #else
1191       //no pushl on 64bits
1192       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1193       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1194 #endif
1195     }
1196 
1197   } else if (src->is_double_stack()) {
1198 #ifdef _LP64
1199     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1200     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1201 #else
1202     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1203     // push and pop the part at src + wordSize, adding wordSize for the previous push
1204     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1205     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1206     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1207 #endif // _LP64
1208 
1209   } else {
1210     ShouldNotReachHere();
1211   }
1212 }
1213 
1214 
1215 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1216   assert(src->is_address(), "should not call otherwise");
1217   assert(dest->is_register(), "should not call otherwise");
1218 
1219   LIR_Address* addr = src->as_address_ptr();
1220   Address from_addr = as_Address(addr);
1221 
1222   if (addr->base()->type() == T_OBJECT) {
1223     __ verify_oop(addr->base()->as_pointer_register());
1224   }
1225 
1226   switch (type) {
1227     case T_BOOLEAN: // fall through
1228     case T_BYTE:    // fall through
1229     case T_CHAR:    // fall through
1230     case T_SHORT:
1231       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1232         // on pre P6 processors we may get partial register stalls
1233         // so blow away the value of to_rinfo before loading a
1234         // partial word into it.  Do it here so that it precedes
1235         // the potential patch point below.
1236         __ xorptr(dest->as_register(), dest->as_register());
1237       }
1238       break;
1239   }
1240 
1241   PatchingStub* patch = NULL;
1242   if (patch_code != lir_patch_none) {
1243     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1244     assert(from_addr.disp() != 0, "must have");
1245   }
1246   if (info != NULL) {
1247     add_debug_info_for_null_check_here(info);
1248   }
1249 
1250   switch (type) {
1251     case T_FLOAT: {
1252       if (dest->is_single_xmm()) {
1253         __ movflt(dest->as_xmm_float_reg(), from_addr);
1254       } else {
1255         assert(dest->is_single_fpu(), "must be");
1256         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1257         __ fld_s(from_addr);
1258       }
1259       break;
1260     }
1261 
1262     case T_DOUBLE: {
1263       if (dest->is_double_xmm()) {
1264         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1265       } else {
1266         assert(dest->is_double_fpu(), "must be");
1267         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1268         __ fld_d(from_addr);
1269       }
1270       break;
1271     }
1272 
1273     case T_OBJECT:  // fall through
1274     case T_ARRAY:   // fall through
1275       if (UseCompressedOops && !wide) {
1276         __ movl(dest->as_register(), from_addr);
1277       } else {
1278         __ movptr(dest->as_register(), from_addr);
1279       }
1280       break;
1281 
1282     case T_ADDRESS:
1283       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1284         __ movl(dest->as_register(), from_addr);
1285       } else {
1286         __ movptr(dest->as_register(), from_addr);
1287       }
1288       break;
1289     case T_INT:
1290       __ movl(dest->as_register(), from_addr);
1291       break;
1292 
1293     case T_LONG: {
1294       Register to_lo = dest->as_register_lo();
1295       Register to_hi = dest->as_register_hi();
1296 #ifdef _LP64
1297       __ movptr(to_lo, as_Address_lo(addr));
1298 #else
1299       Register base = addr->base()->as_register();
1300       Register index = noreg;
1301       if (addr->index()->is_register()) {
1302         index = addr->index()->as_register();
1303       }
1304       if ((base == to_lo && index == to_hi) ||
1305           (base == to_hi && index == to_lo)) {
1306         // addresses with 2 registers are only formed as a result of
1307         // array access so this code will never have to deal with
1308         // patches or null checks.
1309         assert(info == NULL && patch == NULL, "must be");
1310         __ lea(to_hi, as_Address(addr));
1311         __ movl(to_lo, Address(to_hi, 0));
1312         __ movl(to_hi, Address(to_hi, BytesPerWord));
1313       } else if (base == to_lo || index == to_lo) {
1314         assert(base != to_hi, "can't be");
1315         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1316         __ movl(to_hi, as_Address_hi(addr));
1317         if (patch != NULL) {
1318           patching_epilog(patch, lir_patch_high, base, info);
1319           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1320           patch_code = lir_patch_low;
1321         }
1322         __ movl(to_lo, as_Address_lo(addr));
1323       } else {
1324         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1325         __ movl(to_lo, as_Address_lo(addr));
1326         if (patch != NULL) {
1327           patching_epilog(patch, lir_patch_low, base, info);
1328           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1329           patch_code = lir_patch_high;
1330         }
1331         __ movl(to_hi, as_Address_hi(addr));
1332       }
1333 #endif // _LP64
1334       break;
1335     }
1336 
1337     case T_BOOLEAN: // fall through
1338     case T_BYTE: {
1339       Register dest_reg = dest->as_register();
1340       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1341       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1342         __ movsbl(dest_reg, from_addr);
1343       } else {
1344         __ movb(dest_reg, from_addr);
1345         __ shll(dest_reg, 24);
1346         __ sarl(dest_reg, 24);
1347       }
1348       break;
1349     }
1350 
1351     case T_CHAR: {
1352       Register dest_reg = dest->as_register();
1353       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1354       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1355         __ movzwl(dest_reg, from_addr);
1356       } else {
1357         __ movw(dest_reg, from_addr);
1358       }
1359       break;
1360     }
1361 
1362     case T_SHORT: {
1363       Register dest_reg = dest->as_register();
1364       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1365         __ movswl(dest_reg, from_addr);
1366       } else {
1367         __ movw(dest_reg, from_addr);
1368         __ shll(dest_reg, 16);
1369         __ sarl(dest_reg, 16);
1370       }
1371       break;
1372     }
1373 
1374     default:
1375       ShouldNotReachHere();
1376   }
1377 
1378   if (patch != NULL) {
1379     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1380   }
1381 
1382   if (type == T_ARRAY || type == T_OBJECT) {
1383 #ifdef _LP64
1384     if (UseCompressedOops && !wide) {
1385       __ decode_heap_oop(dest->as_register());
1386     }
1387 #endif
1388     __ verify_oop(dest->as_register());
1389   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1390 #ifdef _LP64
1391     if (UseCompressedClassPointers) {
1392       __ decode_klass_not_null(dest->as_register());
1393     }
1394 #endif
1395   }
1396 }
1397 
1398 
1399 NEEDS_CLEANUP; // This could be static?
1400 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1401   int elem_size = type2aelembytes(type);
1402   switch (elem_size) {
1403     case 1: return Address::times_1;
1404     case 2: return Address::times_2;
1405     case 4: return Address::times_4;
1406     case 8: return Address::times_8;
1407   }
1408   ShouldNotReachHere();
1409   return Address::no_scale;
1410 }
1411 
1412 
1413 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1414   switch (op->code()) {
1415     case lir_idiv:
1416     case lir_irem:
1417       arithmetic_idiv(op->code(),
1418                       op->in_opr1(),
1419                       op->in_opr2(),
1420                       op->in_opr3(),
1421                       op->result_opr(),
1422                       op->info());
1423       break;
1424     default:      ShouldNotReachHere(); break;
1425   }
1426 }
1427 
1428 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1429 #ifdef ASSERT
1430   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1431   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1432   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1433 #endif
1434 
1435   if (op->cond() == lir_cond_always) {
1436     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1437     __ jmp (*(op->label()));
1438   } else {
1439     Assembler::Condition acond = Assembler::zero;
1440     if (op->code() == lir_cond_float_branch) {
1441       assert(op->ublock() != NULL, "must have unordered successor");
1442       __ jcc(Assembler::parity, *(op->ublock()->label()));
1443       switch(op->cond()) {
1444         case lir_cond_equal:        acond = Assembler::equal;      break;
1445         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1446         case lir_cond_less:         acond = Assembler::below;      break;
1447         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1448         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1449         case lir_cond_greater:      acond = Assembler::above;      break;
1450         default:                         ShouldNotReachHere();
1451       }
1452     } else {
1453       switch (op->cond()) {
1454         case lir_cond_equal:        acond = Assembler::equal;       break;
1455         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1456         case lir_cond_less:         acond = Assembler::less;        break;
1457         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1458         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1459         case lir_cond_greater:      acond = Assembler::greater;     break;
1460         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1461         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1462         default:                         ShouldNotReachHere();
1463       }
1464     }
1465     __ jcc(acond,*(op->label()));
1466   }
1467 }
1468 
1469 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1470   LIR_Opr src  = op->in_opr();
1471   LIR_Opr dest = op->result_opr();
1472 
1473   switch (op->bytecode()) {
1474     case Bytecodes::_i2l:
1475 #ifdef _LP64
1476       __ movl2ptr(dest->as_register_lo(), src->as_register());
1477 #else
1478       move_regs(src->as_register(), dest->as_register_lo());
1479       move_regs(src->as_register(), dest->as_register_hi());
1480       __ sarl(dest->as_register_hi(), 31);
1481 #endif // LP64
1482       break;
1483 
1484     case Bytecodes::_l2i:
1485 #ifdef _LP64
1486       __ movl(dest->as_register(), src->as_register_lo());
1487 #else
1488       move_regs(src->as_register_lo(), dest->as_register());
1489 #endif
1490       break;
1491 
1492     case Bytecodes::_i2b:
1493       move_regs(src->as_register(), dest->as_register());
1494       __ sign_extend_byte(dest->as_register());
1495       break;
1496 
1497     case Bytecodes::_i2c:
1498       move_regs(src->as_register(), dest->as_register());
1499       __ andl(dest->as_register(), 0xFFFF);
1500       break;
1501 
1502     case Bytecodes::_i2s:
1503       move_regs(src->as_register(), dest->as_register());
1504       __ sign_extend_short(dest->as_register());
1505       break;
1506 
1507 
1508     case Bytecodes::_f2d:
1509     case Bytecodes::_d2f:
1510       if (dest->is_single_xmm()) {
1511         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1512       } else if (dest->is_double_xmm()) {
1513         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1514       } else {
1515         assert(src->fpu() == dest->fpu(), "register must be equal");
1516         // do nothing (float result is rounded later through spilling)
1517       }
1518       break;
1519 
1520     case Bytecodes::_i2f:
1521     case Bytecodes::_i2d:
1522       if (dest->is_single_xmm()) {
1523         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1524       } else if (dest->is_double_xmm()) {
1525         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1526       } else {
1527         assert(dest->fpu() == 0, "result must be on TOS");
1528         __ movl(Address(rsp, 0), src->as_register());
1529         __ fild_s(Address(rsp, 0));
1530       }
1531       break;
1532 
1533     case Bytecodes::_f2i:
1534     case Bytecodes::_d2i:
1535       if (src->is_single_xmm()) {
1536         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1537       } else if (src->is_double_xmm()) {
1538         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1539       } else {
1540         assert(src->fpu() == 0, "input must be on TOS");
1541         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1542         __ fist_s(Address(rsp, 0));
1543         __ movl(dest->as_register(), Address(rsp, 0));
1544         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1545       }
1546 
1547       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1548       assert(op->stub() != NULL, "stub required");
1549       __ cmpl(dest->as_register(), 0x80000000);
1550       __ jcc(Assembler::equal, *op->stub()->entry());
1551       __ bind(*op->stub()->continuation());
1552       break;
1553 
1554     case Bytecodes::_l2f:
1555     case Bytecodes::_l2d:
1556       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1557       assert(dest->fpu() == 0, "result must be on TOS");
1558 
1559       __ movptr(Address(rsp, 0),            src->as_register_lo());
1560       NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1561       __ fild_d(Address(rsp, 0));
1562       // float result is rounded later through spilling
1563       break;
1564 
1565     case Bytecodes::_f2l:
1566     case Bytecodes::_d2l:
1567       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1568       assert(src->fpu() == 0, "input must be on TOS");
1569       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1570 
1571       // instruction sequence too long to inline it here
1572       {
1573         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1574       }
1575       break;
1576 
1577     default: ShouldNotReachHere();
1578   }
1579 }
1580 
1581 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1582   if (op->init_check()) {
1583     __ cmpb(Address(op->klass()->as_register(),
1584                     InstanceKlass::init_state_offset()),
1585                     InstanceKlass::fully_initialized);
1586     add_debug_info_for_null_check_here(op->stub()->info());
1587     __ jcc(Assembler::notEqual, *op->stub()->entry());
1588   }
1589   __ allocate_object(op->obj()->as_register(),
1590                      op->tmp1()->as_register(),
1591                      op->tmp2()->as_register(),
1592                      op->header_size(),
1593                      op->object_size(),
1594                      op->klass()->as_register(),
1595                      *op->stub()->entry());
1596   __ bind(*op->stub()->continuation());
1597 }
1598 
1599 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1600   Register len =  op->len()->as_register();
1601   LP64_ONLY( __ movslq(len, len); )
1602 
1603   if (UseSlowPath ||
1604       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1605       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1606     __ jmp(*op->stub()->entry());
1607   } else {
1608     Register tmp1 = op->tmp1()->as_register();
1609     Register tmp2 = op->tmp2()->as_register();
1610     Register tmp3 = op->tmp3()->as_register();
1611     if (len == tmp1) {
1612       tmp1 = tmp3;
1613     } else if (len == tmp2) {
1614       tmp2 = tmp3;
1615     } else if (len == tmp3) {
1616       // everything is ok
1617     } else {
1618       __ mov(tmp3, len);
1619     }
1620     __ allocate_array(op->obj()->as_register(),
1621                       len,
1622                       tmp1,
1623                       tmp2,
1624                       arrayOopDesc::header_size(op->type()),
1625                       array_element_size(op->type()),
1626                       op->klass()->as_register(),
1627                       *op->stub()->entry());
1628   }
1629   __ bind(*op->stub()->continuation());
1630 }
1631 
1632 void LIR_Assembler::type_profile_helper(Register mdo,
1633                                         ciMethodData *md, ciProfileData *data,
1634                                         Register recv, Label* update_done) {
1635   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1636     Label next_test;
1637     // See if the receiver is receiver[n].
1638     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1639     __ jccb(Assembler::notEqual, next_test);
1640     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1641     __ addptr(data_addr, DataLayout::counter_increment);
1642     __ jmp(*update_done);
1643     __ bind(next_test);
1644   }
1645 
1646   // Didn't find receiver; find next empty slot and fill it in
1647   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1648     Label next_test;
1649     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1650     __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1651     __ jccb(Assembler::notEqual, next_test);
1652     __ movptr(recv_addr, recv);
1653     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1654     __ jmp(*update_done);
1655     __ bind(next_test);
1656   }
1657 }
1658 
1659 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1660   // we always need a stub for the failure case.
1661   CodeStub* stub = op->stub();
1662   Register obj = op->object()->as_register();
1663   Register k_RInfo = op->tmp1()->as_register();
1664   Register klass_RInfo = op->tmp2()->as_register();
1665   Register dst = op->result_opr()->as_register();
1666   ciKlass* k = op->klass();
1667   Register Rtmp1 = noreg;
1668 
1669   // check if it needs to be profiled
1670   ciMethodData* md;
1671   ciProfileData* data;
1672 
1673   if (op->should_profile()) {
1674     ciMethod* method = op->profiled_method();
1675     assert(method != NULL, "Should have method");
1676     int bci = op->profiled_bci();
1677     md = method->method_data_or_null();
1678     assert(md != NULL, "Sanity");
1679     data = md->bci_to_data(bci);
1680     assert(data != NULL,                "need data for type check");
1681     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1682   }
1683   Label profile_cast_success, profile_cast_failure;
1684   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1685   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1686 
1687   if (obj == k_RInfo) {
1688     k_RInfo = dst;
1689   } else if (obj == klass_RInfo) {
1690     klass_RInfo = dst;
1691   }
1692   if (k->is_loaded() && !UseCompressedClassPointers) {
1693     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1694   } else {
1695     Rtmp1 = op->tmp3()->as_register();
1696     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1697   }
1698 
1699   assert_different_registers(obj, k_RInfo, klass_RInfo);
1700 
1701   __ cmpptr(obj, (int32_t)NULL_WORD);
1702   if (op->should_profile()) {
1703     Label not_null;
1704     __ jccb(Assembler::notEqual, not_null);
1705     // Object is null; update MDO and exit
1706     Register mdo  = klass_RInfo;
1707     __ mov_metadata(mdo, md->constant_encoding());
1708     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1709     int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1710     __ orl(data_addr, header_bits);
1711     __ jmp(*obj_is_null);
1712     __ bind(not_null);
1713   } else {
1714     __ jcc(Assembler::equal, *obj_is_null);
1715   }
1716 
1717   if (!k->is_loaded()) {
1718     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1719   } else {
1720 #ifdef _LP64
1721     __ mov_metadata(k_RInfo, k->constant_encoding());
1722 #endif // _LP64
1723   }
1724   __ verify_oop(obj);
1725 
1726   if (op->fast_check()) {
1727     // get object class
1728     // not a safepoint as obj null check happens earlier
1729 #ifdef _LP64
1730     if (UseCompressedClassPointers) {
1731       __ load_klass(Rtmp1, obj);
1732       __ cmpptr(k_RInfo, Rtmp1);
1733     } else {
1734       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1735     }
1736 #else
1737     if (k->is_loaded()) {
1738       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1739     } else {
1740       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1741     }
1742 #endif
1743     __ jcc(Assembler::notEqual, *failure_target);
1744     // successful cast, fall through to profile or jump
1745   } else {
1746     // get object class
1747     // not a safepoint as obj null check happens earlier
1748     __ load_klass(klass_RInfo, obj);
1749     if (k->is_loaded()) {
1750       // See if we get an immediate positive hit
1751 #ifdef _LP64
1752       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1753 #else
1754       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1755 #endif // _LP64
1756       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1757         __ jcc(Assembler::notEqual, *failure_target);
1758         // successful cast, fall through to profile or jump
1759       } else {
1760         // See if we get an immediate positive hit
1761         __ jcc(Assembler::equal, *success_target);
1762         // check for self
1763 #ifdef _LP64
1764         __ cmpptr(klass_RInfo, k_RInfo);
1765 #else
1766         __ cmpklass(klass_RInfo, k->constant_encoding());
1767 #endif // _LP64
1768         __ jcc(Assembler::equal, *success_target);
1769 
1770         __ push(klass_RInfo);
1771 #ifdef _LP64
1772         __ push(k_RInfo);
1773 #else
1774         __ pushklass(k->constant_encoding());
1775 #endif // _LP64
1776         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1777         __ pop(klass_RInfo);
1778         __ pop(klass_RInfo);
1779         // result is a boolean
1780         __ cmpl(klass_RInfo, 0);
1781         __ jcc(Assembler::equal, *failure_target);
1782         // successful cast, fall through to profile or jump
1783       }
1784     } else {
1785       // perform the fast part of the checking logic
1786       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1787       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1788       __ push(klass_RInfo);
1789       __ push(k_RInfo);
1790       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1791       __ pop(klass_RInfo);
1792       __ pop(k_RInfo);
1793       // result is a boolean
1794       __ cmpl(k_RInfo, 0);
1795       __ jcc(Assembler::equal, *failure_target);
1796       // successful cast, fall through to profile or jump
1797     }
1798   }
1799   if (op->should_profile()) {
1800     Register mdo  = klass_RInfo, recv = k_RInfo;
1801     __ bind(profile_cast_success);
1802     __ mov_metadata(mdo, md->constant_encoding());
1803     __ load_klass(recv, obj);
1804     Label update_done;
1805     type_profile_helper(mdo, md, data, recv, success);
1806     __ jmp(*success);
1807 
1808     __ bind(profile_cast_failure);
1809     __ mov_metadata(mdo, md->constant_encoding());
1810     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1811     __ subptr(counter_addr, DataLayout::counter_increment);
1812     __ jmp(*failure);
1813   }
1814   __ jmp(*success);
1815 }
1816 
1817 
1818 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1819   LIR_Code code = op->code();
1820   if (code == lir_store_check) {
1821     Register value = op->object()->as_register();
1822     Register array = op->array()->as_register();
1823     Register k_RInfo = op->tmp1()->as_register();
1824     Register klass_RInfo = op->tmp2()->as_register();
1825     Register Rtmp1 = op->tmp3()->as_register();
1826 
1827     CodeStub* stub = op->stub();
1828 
1829     // check if it needs to be profiled
1830     ciMethodData* md;
1831     ciProfileData* data;
1832 
1833     if (op->should_profile()) {
1834       ciMethod* method = op->profiled_method();
1835       assert(method != NULL, "Should have method");
1836       int bci = op->profiled_bci();
1837       md = method->method_data_or_null();
1838       assert(md != NULL, "Sanity");
1839       data = md->bci_to_data(bci);
1840       assert(data != NULL,                "need data for type check");
1841       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1842     }
1843     Label profile_cast_success, profile_cast_failure, done;
1844     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1845     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1846 
1847     __ cmpptr(value, (int32_t)NULL_WORD);
1848     if (op->should_profile()) {
1849       Label not_null;
1850       __ jccb(Assembler::notEqual, not_null);
1851       // Object is null; update MDO and exit
1852       Register mdo  = klass_RInfo;
1853       __ mov_metadata(mdo, md->constant_encoding());
1854       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1855       int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1856       __ orl(data_addr, header_bits);
1857       __ jmp(done);
1858       __ bind(not_null);
1859     } else {
1860       __ jcc(Assembler::equal, done);
1861     }
1862 
1863     add_debug_info_for_null_check_here(op->info_for_exception());
1864     __ load_klass(k_RInfo, array);
1865     __ load_klass(klass_RInfo, value);
1866 
1867     // get instance klass (it's already uncompressed)
1868     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1869     // perform the fast part of the checking logic
1870     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1871     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1872     __ push(klass_RInfo);
1873     __ push(k_RInfo);
1874     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1875     __ pop(klass_RInfo);
1876     __ pop(k_RInfo);
1877     // result is a boolean
1878     __ cmpl(k_RInfo, 0);
1879     __ jcc(Assembler::equal, *failure_target);
1880     // fall through to the success case
1881 
1882     if (op->should_profile()) {
1883       Register mdo  = klass_RInfo, recv = k_RInfo;
1884       __ bind(profile_cast_success);
1885       __ mov_metadata(mdo, md->constant_encoding());
1886       __ load_klass(recv, value);
1887       Label update_done;
1888       type_profile_helper(mdo, md, data, recv, &done);
1889       __ jmpb(done);
1890 
1891       __ bind(profile_cast_failure);
1892       __ mov_metadata(mdo, md->constant_encoding());
1893       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1894       __ subptr(counter_addr, DataLayout::counter_increment);
1895       __ jmp(*stub->entry());
1896     }
1897 
1898     __ bind(done);
1899   } else
1900     if (code == lir_checkcast) {
1901       Register obj = op->object()->as_register();
1902       Register dst = op->result_opr()->as_register();
1903       Label success;
1904       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1905       __ bind(success);
1906       if (dst != obj) {
1907         __ mov(dst, obj);
1908       }
1909     } else
1910       if (code == lir_instanceof) {
1911         Register obj = op->object()->as_register();
1912         Register dst = op->result_opr()->as_register();
1913         Label success, failure, done;
1914         emit_typecheck_helper(op, &success, &failure, &failure);
1915         __ bind(failure);
1916         __ xorptr(dst, dst);
1917         __ jmpb(done);
1918         __ bind(success);
1919         __ movptr(dst, 1);
1920         __ bind(done);
1921       } else {
1922         ShouldNotReachHere();
1923       }
1924 
1925 }
1926 
1927 
1928 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1929   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1930     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1931     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1932     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1933     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1934     Register addr = op->addr()->as_register();
1935     if (os::is_MP()) {
1936       __ lock();
1937     }
1938     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1939 
1940   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1941     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1942     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1943     Register newval = op->new_value()->as_register();
1944     Register cmpval = op->cmp_value()->as_register();
1945     assert(cmpval == rax, "wrong register");
1946     assert(newval != NULL, "new val must be register");
1947     assert(cmpval != newval, "cmp and new values must be in different registers");
1948     assert(cmpval != addr, "cmp and addr must be in different registers");
1949     assert(newval != addr, "new value and addr must be in different registers");
1950 
1951     if ( op->code() == lir_cas_obj) {
1952 #ifdef _LP64
1953       if (UseCompressedOops) {
1954         __ encode_heap_oop(cmpval);
1955         __ mov(rscratch1, newval);
1956         __ encode_heap_oop(rscratch1);
1957         if (os::is_MP()) {
1958           __ lock();
1959         }
1960         // cmpval (rax) is implicitly used by this instruction
1961         __ cmpxchgl(rscratch1, Address(addr, 0));
1962       } else
1963 #endif
1964       {
1965         if (os::is_MP()) {
1966           __ lock();
1967         }
1968         __ cmpxchgptr(newval, Address(addr, 0));
1969       }
1970     } else {
1971       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1972       if (os::is_MP()) {
1973         __ lock();
1974       }
1975       __ cmpxchgl(newval, Address(addr, 0));
1976     }
1977 #ifdef _LP64
1978   } else if (op->code() == lir_cas_long) {
1979     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1980     Register newval = op->new_value()->as_register_lo();
1981     Register cmpval = op->cmp_value()->as_register_lo();
1982     assert(cmpval == rax, "wrong register");
1983     assert(newval != NULL, "new val must be register");
1984     assert(cmpval != newval, "cmp and new values must be in different registers");
1985     assert(cmpval != addr, "cmp and addr must be in different registers");
1986     assert(newval != addr, "new value and addr must be in different registers");
1987     if (os::is_MP()) {
1988       __ lock();
1989     }
1990     __ cmpxchgq(newval, Address(addr, 0));
1991 #endif // _LP64
1992   } else {
1993     Unimplemented();
1994   }
1995 }
1996 
1997 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1998   Assembler::Condition acond = Assembler::equal, ncond = Assembler::notEqual;
1999   switch (condition) {
2000     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
2001     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
2002     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
2003     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
2004     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
2005     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
2006     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
2007     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
2008     default:                    ShouldNotReachHere();
2009   }
2010 
2011   if (opr1->is_cpu_register()) {
2012     reg2reg(opr1, result);
2013   } else if (opr1->is_stack()) {
2014     stack2reg(opr1, result, result->type());
2015   } else if (opr1->is_constant()) {
2016     const2reg(opr1, result, lir_patch_none, NULL);
2017   } else {
2018     ShouldNotReachHere();
2019   }
2020 
2021   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2022     // optimized version that does not require a branch
2023     if (opr2->is_single_cpu()) {
2024       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2025       __ cmov(ncond, result->as_register(), opr2->as_register());
2026     } else if (opr2->is_double_cpu()) {
2027       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2028       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2029       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2030       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2031     } else if (opr2->is_single_stack()) {
2032       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2033     } else if (opr2->is_double_stack()) {
2034       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2035       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2036     } else {
2037       ShouldNotReachHere();
2038     }
2039 
2040   } else {
2041     Label skip;
2042     __ jcc (acond, skip);
2043     if (opr2->is_cpu_register()) {
2044       reg2reg(opr2, result);
2045     } else if (opr2->is_stack()) {
2046       stack2reg(opr2, result, result->type());
2047     } else if (opr2->is_constant()) {
2048       const2reg(opr2, result, lir_patch_none, NULL);
2049     } else {
2050       ShouldNotReachHere();
2051     }
2052     __ bind(skip);
2053   }
2054 }
2055 
2056 
2057 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2058   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2059 
2060   if (left->is_single_cpu()) {
2061     assert(left == dest, "left and dest must be equal");
2062     Register lreg = left->as_register();
2063 
2064     if (right->is_single_cpu()) {
2065       // cpu register - cpu register
2066       Register rreg = right->as_register();
2067       switch (code) {
2068         case lir_add: __ addl (lreg, rreg); break;
2069         case lir_sub: __ subl (lreg, rreg); break;
2070         case lir_mul: __ imull(lreg, rreg); break;
2071         default:      ShouldNotReachHere();
2072       }
2073 
2074     } else if (right->is_stack()) {
2075       // cpu register - stack
2076       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2077       switch (code) {
2078         case lir_add: __ addl(lreg, raddr); break;
2079         case lir_sub: __ subl(lreg, raddr); break;
2080         default:      ShouldNotReachHere();
2081       }
2082 
2083     } else if (right->is_constant()) {
2084       // cpu register - constant
2085       jint c = right->as_constant_ptr()->as_jint();
2086       switch (code) {
2087         case lir_add: {
2088           __ incrementl(lreg, c);
2089           break;
2090         }
2091         case lir_sub: {
2092           __ decrementl(lreg, c);
2093           break;
2094         }
2095         default: ShouldNotReachHere();
2096       }
2097 
2098     } else {
2099       ShouldNotReachHere();
2100     }
2101 
2102   } else if (left->is_double_cpu()) {
2103     assert(left == dest, "left and dest must be equal");
2104     Register lreg_lo = left->as_register_lo();
2105     Register lreg_hi = left->as_register_hi();
2106 
2107     if (right->is_double_cpu()) {
2108       // cpu register - cpu register
2109       Register rreg_lo = right->as_register_lo();
2110       Register rreg_hi = right->as_register_hi();
2111       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2112       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2113       switch (code) {
2114         case lir_add:
2115           __ addptr(lreg_lo, rreg_lo);
2116           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2117           break;
2118         case lir_sub:
2119           __ subptr(lreg_lo, rreg_lo);
2120           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2121           break;
2122         case lir_mul:
2123 #ifdef _LP64
2124           __ imulq(lreg_lo, rreg_lo);
2125 #else
2126           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2127           __ imull(lreg_hi, rreg_lo);
2128           __ imull(rreg_hi, lreg_lo);
2129           __ addl (rreg_hi, lreg_hi);
2130           __ mull (rreg_lo);
2131           __ addl (lreg_hi, rreg_hi);
2132 #endif // _LP64
2133           break;
2134         default:
2135           ShouldNotReachHere();
2136       }
2137 
2138     } else if (right->is_constant()) {
2139       // cpu register - constant
2140 #ifdef _LP64
2141       jlong c = right->as_constant_ptr()->as_jlong_bits();
2142       __ movptr(r10, (intptr_t) c);
2143       switch (code) {
2144         case lir_add:
2145           __ addptr(lreg_lo, r10);
2146           break;
2147         case lir_sub:
2148           __ subptr(lreg_lo, r10);
2149           break;
2150         default:
2151           ShouldNotReachHere();
2152       }
2153 #else
2154       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2155       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2156       switch (code) {
2157         case lir_add:
2158           __ addptr(lreg_lo, c_lo);
2159           __ adcl(lreg_hi, c_hi);
2160           break;
2161         case lir_sub:
2162           __ subptr(lreg_lo, c_lo);
2163           __ sbbl(lreg_hi, c_hi);
2164           break;
2165         default:
2166           ShouldNotReachHere();
2167       }
2168 #endif // _LP64
2169 
2170     } else {
2171       ShouldNotReachHere();
2172     }
2173 
2174   } else if (left->is_single_xmm()) {
2175     assert(left == dest, "left and dest must be equal");
2176     XMMRegister lreg = left->as_xmm_float_reg();
2177 
2178     if (right->is_single_xmm()) {
2179       XMMRegister rreg = right->as_xmm_float_reg();
2180       switch (code) {
2181         case lir_add: __ addss(lreg, rreg);  break;
2182         case lir_sub: __ subss(lreg, rreg);  break;
2183         case lir_mul_strictfp: // fall through
2184         case lir_mul: __ mulss(lreg, rreg);  break;
2185         case lir_div_strictfp: // fall through
2186         case lir_div: __ divss(lreg, rreg);  break;
2187         default: ShouldNotReachHere();
2188       }
2189     } else {
2190       Address raddr;
2191       if (right->is_single_stack()) {
2192         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2193       } else if (right->is_constant()) {
2194         // hack for now
2195         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2196       } else {
2197         ShouldNotReachHere();
2198       }
2199       switch (code) {
2200         case lir_add: __ addss(lreg, raddr);  break;
2201         case lir_sub: __ subss(lreg, raddr);  break;
2202         case lir_mul_strictfp: // fall through
2203         case lir_mul: __ mulss(lreg, raddr);  break;
2204         case lir_div_strictfp: // fall through
2205         case lir_div: __ divss(lreg, raddr);  break;
2206         default: ShouldNotReachHere();
2207       }
2208     }
2209 
2210   } else if (left->is_double_xmm()) {
2211     assert(left == dest, "left and dest must be equal");
2212 
2213     XMMRegister lreg = left->as_xmm_double_reg();
2214     if (right->is_double_xmm()) {
2215       XMMRegister rreg = right->as_xmm_double_reg();
2216       switch (code) {
2217         case lir_add: __ addsd(lreg, rreg);  break;
2218         case lir_sub: __ subsd(lreg, rreg);  break;
2219         case lir_mul_strictfp: // fall through
2220         case lir_mul: __ mulsd(lreg, rreg);  break;
2221         case lir_div_strictfp: // fall through
2222         case lir_div: __ divsd(lreg, rreg);  break;
2223         default: ShouldNotReachHere();
2224       }
2225     } else {
2226       Address raddr;
2227       if (right->is_double_stack()) {
2228         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2229       } else if (right->is_constant()) {
2230         // hack for now
2231         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2232       } else {
2233         ShouldNotReachHere();
2234       }
2235       switch (code) {
2236         case lir_add: __ addsd(lreg, raddr);  break;
2237         case lir_sub: __ subsd(lreg, raddr);  break;
2238         case lir_mul_strictfp: // fall through
2239         case lir_mul: __ mulsd(lreg, raddr);  break;
2240         case lir_div_strictfp: // fall through
2241         case lir_div: __ divsd(lreg, raddr);  break;
2242         default: ShouldNotReachHere();
2243       }
2244     }
2245 
2246   } else if (left->is_single_fpu()) {
2247     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2248 
2249     if (right->is_single_fpu()) {
2250       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2251 
2252     } else {
2253       assert(left->fpu_regnr() == 0, "left must be on TOS");
2254       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2255 
2256       Address raddr;
2257       if (right->is_single_stack()) {
2258         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2259       } else if (right->is_constant()) {
2260         address const_addr = float_constant(right->as_jfloat());
2261         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2262         // hack for now
2263         raddr = __ as_Address(InternalAddress(const_addr));
2264       } else {
2265         ShouldNotReachHere();
2266       }
2267 
2268       switch (code) {
2269         case lir_add: __ fadd_s(raddr); break;
2270         case lir_sub: __ fsub_s(raddr); break;
2271         case lir_mul_strictfp: // fall through
2272         case lir_mul: __ fmul_s(raddr); break;
2273         case lir_div_strictfp: // fall through
2274         case lir_div: __ fdiv_s(raddr); break;
2275         default:      ShouldNotReachHere();
2276       }
2277     }
2278 
2279   } else if (left->is_double_fpu()) {
2280     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2281 
2282     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2283       // Double values require special handling for strictfp mul/div on x86
2284       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2285       __ fmulp(left->fpu_regnrLo() + 1);
2286     }
2287 
2288     if (right->is_double_fpu()) {
2289       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2290 
2291     } else {
2292       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2293       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2294 
2295       Address raddr;
2296       if (right->is_double_stack()) {
2297         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2298       } else if (right->is_constant()) {
2299         // hack for now
2300         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2301       } else {
2302         ShouldNotReachHere();
2303       }
2304 
2305       switch (code) {
2306         case lir_add: __ fadd_d(raddr); break;
2307         case lir_sub: __ fsub_d(raddr); break;
2308         case lir_mul_strictfp: // fall through
2309         case lir_mul: __ fmul_d(raddr); break;
2310         case lir_div_strictfp: // fall through
2311         case lir_div: __ fdiv_d(raddr); break;
2312         default: ShouldNotReachHere();
2313       }
2314     }
2315 
2316     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2317       // Double values require special handling for strictfp mul/div on x86
2318       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2319       __ fmulp(dest->fpu_regnrLo() + 1);
2320     }
2321 
2322   } else if (left->is_single_stack() || left->is_address()) {
2323     assert(left == dest, "left and dest must be equal");
2324 
2325     Address laddr;
2326     if (left->is_single_stack()) {
2327       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2328     } else if (left->is_address()) {
2329       laddr = as_Address(left->as_address_ptr());
2330     } else {
2331       ShouldNotReachHere();
2332     }
2333 
2334     if (right->is_single_cpu()) {
2335       Register rreg = right->as_register();
2336       switch (code) {
2337         case lir_add: __ addl(laddr, rreg); break;
2338         case lir_sub: __ subl(laddr, rreg); break;
2339         default:      ShouldNotReachHere();
2340       }
2341     } else if (right->is_constant()) {
2342       jint c = right->as_constant_ptr()->as_jint();
2343       switch (code) {
2344         case lir_add: {
2345           __ incrementl(laddr, c);
2346           break;
2347         }
2348         case lir_sub: {
2349           __ decrementl(laddr, c);
2350           break;
2351         }
2352         default: ShouldNotReachHere();
2353       }
2354     } else {
2355       ShouldNotReachHere();
2356     }
2357 
2358   } else {
2359     ShouldNotReachHere();
2360   }
2361 }
2362 
2363 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2364   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2365   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2366   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2367 
2368   bool left_is_tos = (left_index == 0);
2369   bool dest_is_tos = (dest_index == 0);
2370   int non_tos_index = (left_is_tos ? right_index : left_index);
2371 
2372   switch (code) {
2373     case lir_add:
2374       if (pop_fpu_stack)       __ faddp(non_tos_index);
2375       else if (dest_is_tos)    __ fadd (non_tos_index);
2376       else                     __ fadda(non_tos_index);
2377       break;
2378 
2379     case lir_sub:
2380       if (left_is_tos) {
2381         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2382         else if (dest_is_tos)  __ fsub  (non_tos_index);
2383         else                   __ fsubra(non_tos_index);
2384       } else {
2385         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2386         else if (dest_is_tos)  __ fsubr (non_tos_index);
2387         else                   __ fsuba (non_tos_index);
2388       }
2389       break;
2390 
2391     case lir_mul_strictfp: // fall through
2392     case lir_mul:
2393       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2394       else if (dest_is_tos)    __ fmul (non_tos_index);
2395       else                     __ fmula(non_tos_index);
2396       break;
2397 
2398     case lir_div_strictfp: // fall through
2399     case lir_div:
2400       if (left_is_tos) {
2401         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2402         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2403         else                   __ fdivra(non_tos_index);
2404       } else {
2405         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2406         else if (dest_is_tos)  __ fdivr (non_tos_index);
2407         else                   __ fdiva (non_tos_index);
2408       }
2409       break;
2410 
2411     case lir_rem:
2412       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2413       __ fremr(noreg);
2414       break;
2415 
2416     default:
2417       ShouldNotReachHere();
2418   }
2419 }
2420 
2421 
2422 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2423   if (value->is_double_xmm()) {
2424     switch(code) {
2425       case lir_abs :
2426         {
2427           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2428             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2429           }
2430           __ andpd(dest->as_xmm_double_reg(),
2431                     ExternalAddress((address)double_signmask_pool));
2432         }
2433         break;
2434 
2435       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2436       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2437       default      : ShouldNotReachHere();
2438     }
2439 
2440   } else if (value->is_double_fpu()) {
2441     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2442     switch(code) {
2443       case lir_log   : __ flog() ; break;
2444       case lir_log10 : __ flog10() ; break;
2445       case lir_abs   : __ fabs() ; break;
2446       case lir_sqrt  : __ fsqrt(); break;
2447       case lir_sin   :
2448         // Should consider not saving rbx, if not necessary
2449         __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2450         break;
2451       case lir_cos :
2452         // Should consider not saving rbx, if not necessary
2453         assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2454         __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2455         break;
2456       case lir_tan :
2457         // Should consider not saving rbx, if not necessary
2458         __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2459         break;
2460       case lir_exp :
2461         __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2462         break;
2463       case lir_pow :
2464         __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2465         break;
2466       default      : ShouldNotReachHere();
2467     }
2468   } else {
2469     Unimplemented();
2470   }
2471 }
2472 
2473 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2474   // assert(left->destroys_register(), "check");
2475   if (left->is_single_cpu()) {
2476     Register reg = left->as_register();
2477     if (right->is_constant()) {
2478       int val = right->as_constant_ptr()->as_jint();
2479       switch (code) {
2480         case lir_logic_and: __ andl (reg, val); break;
2481         case lir_logic_or:  __ orl  (reg, val); break;
2482         case lir_logic_xor: __ xorl (reg, val); break;
2483         default: ShouldNotReachHere();
2484       }
2485     } else if (right->is_stack()) {
2486       // added support for stack operands
2487       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2488       switch (code) {
2489         case lir_logic_and: __ andl (reg, raddr); break;
2490         case lir_logic_or:  __ orl  (reg, raddr); break;
2491         case lir_logic_xor: __ xorl (reg, raddr); break;
2492         default: ShouldNotReachHere();
2493       }
2494     } else {
2495       Register rright = right->as_register();
2496       switch (code) {
2497         case lir_logic_and: __ andptr (reg, rright); break;
2498         case lir_logic_or : __ orptr  (reg, rright); break;
2499         case lir_logic_xor: __ xorptr (reg, rright); break;
2500         default: ShouldNotReachHere();
2501       }
2502     }
2503     move_regs(reg, dst->as_register());
2504   } else {
2505     Register l_lo = left->as_register_lo();
2506     Register l_hi = left->as_register_hi();
2507     if (right->is_constant()) {
2508 #ifdef _LP64
2509       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2510       switch (code) {
2511         case lir_logic_and:
2512           __ andq(l_lo, rscratch1);
2513           break;
2514         case lir_logic_or:
2515           __ orq(l_lo, rscratch1);
2516           break;
2517         case lir_logic_xor:
2518           __ xorq(l_lo, rscratch1);
2519           break;
2520         default: ShouldNotReachHere();
2521       }
2522 #else
2523       int r_lo = right->as_constant_ptr()->as_jint_lo();
2524       int r_hi = right->as_constant_ptr()->as_jint_hi();
2525       switch (code) {
2526         case lir_logic_and:
2527           __ andl(l_lo, r_lo);
2528           __ andl(l_hi, r_hi);
2529           break;
2530         case lir_logic_or:
2531           __ orl(l_lo, r_lo);
2532           __ orl(l_hi, r_hi);
2533           break;
2534         case lir_logic_xor:
2535           __ xorl(l_lo, r_lo);
2536           __ xorl(l_hi, r_hi);
2537           break;
2538         default: ShouldNotReachHere();
2539       }
2540 #endif // _LP64
2541     } else {
2542 #ifdef _LP64
2543       Register r_lo;
2544       if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2545         r_lo = right->as_register();
2546       } else {
2547         r_lo = right->as_register_lo();
2548       }
2549 #else
2550       Register r_lo = right->as_register_lo();
2551       Register r_hi = right->as_register_hi();
2552       assert(l_lo != r_hi, "overwriting registers");
2553 #endif
2554       switch (code) {
2555         case lir_logic_and:
2556           __ andptr(l_lo, r_lo);
2557           NOT_LP64(__ andptr(l_hi, r_hi);)
2558           break;
2559         case lir_logic_or:
2560           __ orptr(l_lo, r_lo);
2561           NOT_LP64(__ orptr(l_hi, r_hi);)
2562           break;
2563         case lir_logic_xor:
2564           __ xorptr(l_lo, r_lo);
2565           NOT_LP64(__ xorptr(l_hi, r_hi);)
2566           break;
2567         default: ShouldNotReachHere();
2568       }
2569     }
2570 
2571     Register dst_lo = dst->as_register_lo();
2572     Register dst_hi = dst->as_register_hi();
2573 
2574 #ifdef _LP64
2575     move_regs(l_lo, dst_lo);
2576 #else
2577     if (dst_lo == l_hi) {
2578       assert(dst_hi != l_lo, "overwriting registers");
2579       move_regs(l_hi, dst_hi);
2580       move_regs(l_lo, dst_lo);
2581     } else {
2582       assert(dst_lo != l_hi, "overwriting registers");
2583       move_regs(l_lo, dst_lo);
2584       move_regs(l_hi, dst_hi);
2585     }
2586 #endif // _LP64
2587   }
2588 }
2589 
2590 
2591 // we assume that rax, and rdx can be overwritten
2592 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2593 
2594   assert(left->is_single_cpu(),   "left must be register");
2595   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2596   assert(result->is_single_cpu(), "result must be register");
2597 
2598   //  assert(left->destroys_register(), "check");
2599   //  assert(right->destroys_register(), "check");
2600 
2601   Register lreg = left->as_register();
2602   Register dreg = result->as_register();
2603 
2604   if (right->is_constant()) {
2605     int divisor = right->as_constant_ptr()->as_jint();
2606     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2607     if (code == lir_idiv) {
2608       assert(lreg == rax, "must be rax,");
2609       assert(temp->as_register() == rdx, "tmp register must be rdx");
2610       __ cdql(); // sign extend into rdx:rax
2611       if (divisor == 2) {
2612         __ subl(lreg, rdx);
2613       } else {
2614         __ andl(rdx, divisor - 1);
2615         __ addl(lreg, rdx);
2616       }
2617       __ sarl(lreg, log2_intptr(divisor));
2618       move_regs(lreg, dreg);
2619     } else if (code == lir_irem) {
2620       Label done;
2621       __ mov(dreg, lreg);
2622       __ andl(dreg, 0x80000000 | (divisor - 1));
2623       __ jcc(Assembler::positive, done);
2624       __ decrement(dreg);
2625       __ orl(dreg, ~(divisor - 1));
2626       __ increment(dreg);
2627       __ bind(done);
2628     } else {
2629       ShouldNotReachHere();
2630     }
2631   } else {
2632     Register rreg = right->as_register();
2633     assert(lreg == rax, "left register must be rax,");
2634     assert(rreg != rdx, "right register must not be rdx");
2635     assert(temp->as_register() == rdx, "tmp register must be rdx");
2636 
2637     move_regs(lreg, rax);
2638 
2639     int idivl_offset = __ corrected_idivl(rreg);
2640     add_debug_info_for_div0(idivl_offset, info);
2641     if (code == lir_irem) {
2642       move_regs(rdx, dreg); // result is in rdx
2643     } else {
2644       move_regs(rax, dreg);
2645     }
2646   }
2647 }
2648 
2649 
2650 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2651   if (opr1->is_single_cpu()) {
2652     Register reg1 = opr1->as_register();
2653     if (opr2->is_single_cpu()) {
2654       // cpu register - cpu register
2655       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2656         __ cmpptr(reg1, opr2->as_register());
2657       } else {
2658         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2659         __ cmpl(reg1, opr2->as_register());
2660       }
2661     } else if (opr2->is_stack()) {
2662       // cpu register - stack
2663       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2664         __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2665       } else {
2666         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2667       }
2668     } else if (opr2->is_constant()) {
2669       // cpu register - constant
2670       LIR_Const* c = opr2->as_constant_ptr();
2671       if (c->type() == T_INT) {
2672         __ cmpl(reg1, c->as_jint());
2673       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2674         // In 64bit oops are single register
2675         jobject o = c->as_jobject();
2676         if (o == NULL) {
2677           __ cmpptr(reg1, (int32_t)NULL_WORD);
2678         } else {
2679 #ifdef _LP64
2680           __ movoop(rscratch1, o);
2681           __ cmpptr(reg1, rscratch1);
2682 #else
2683           __ cmpoop(reg1, c->as_jobject());
2684 #endif // _LP64
2685         }
2686       } else {
2687         fatal("unexpected type: %s", basictype_to_str(c->type()));
2688       }
2689       // cpu register - address
2690     } else if (opr2->is_address()) {
2691       if (op->info() != NULL) {
2692         add_debug_info_for_null_check_here(op->info());
2693       }
2694       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2695     } else {
2696       ShouldNotReachHere();
2697     }
2698 
2699   } else if(opr1->is_double_cpu()) {
2700     Register xlo = opr1->as_register_lo();
2701     Register xhi = opr1->as_register_hi();
2702     if (opr2->is_double_cpu()) {
2703 #ifdef _LP64
2704       __ cmpptr(xlo, opr2->as_register_lo());
2705 #else
2706       // cpu register - cpu register
2707       Register ylo = opr2->as_register_lo();
2708       Register yhi = opr2->as_register_hi();
2709       __ subl(xlo, ylo);
2710       __ sbbl(xhi, yhi);
2711       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2712         __ orl(xhi, xlo);
2713       }
2714 #endif // _LP64
2715     } else if (opr2->is_constant()) {
2716       // cpu register - constant 0
2717       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2718 #ifdef _LP64
2719       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2720 #else
2721       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2722       __ orl(xhi, xlo);
2723 #endif // _LP64
2724     } else {
2725       ShouldNotReachHere();
2726     }
2727 
2728   } else if (opr1->is_single_xmm()) {
2729     XMMRegister reg1 = opr1->as_xmm_float_reg();
2730     if (opr2->is_single_xmm()) {
2731       // xmm register - xmm register
2732       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2733     } else if (opr2->is_stack()) {
2734       // xmm register - stack
2735       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2736     } else if (opr2->is_constant()) {
2737       // xmm register - constant
2738       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2739     } else if (opr2->is_address()) {
2740       // xmm register - address
2741       if (op->info() != NULL) {
2742         add_debug_info_for_null_check_here(op->info());
2743       }
2744       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2745     } else {
2746       ShouldNotReachHere();
2747     }
2748 
2749   } else if (opr1->is_double_xmm()) {
2750     XMMRegister reg1 = opr1->as_xmm_double_reg();
2751     if (opr2->is_double_xmm()) {
2752       // xmm register - xmm register
2753       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2754     } else if (opr2->is_stack()) {
2755       // xmm register - stack
2756       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2757     } else if (opr2->is_constant()) {
2758       // xmm register - constant
2759       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2760     } else if (opr2->is_address()) {
2761       // xmm register - address
2762       if (op->info() != NULL) {
2763         add_debug_info_for_null_check_here(op->info());
2764       }
2765       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2766     } else {
2767       ShouldNotReachHere();
2768     }
2769 
2770   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2771     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2772     assert(opr2->is_fpu_register(), "both must be registers");
2773     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2774 
2775   } else if (opr1->is_address() && opr2->is_constant()) {
2776     LIR_Const* c = opr2->as_constant_ptr();
2777 #ifdef _LP64
2778     if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2779       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2780       __ movoop(rscratch1, c->as_jobject());
2781     }
2782 #endif // LP64
2783     if (op->info() != NULL) {
2784       add_debug_info_for_null_check_here(op->info());
2785     }
2786     // special case: address - constant
2787     LIR_Address* addr = opr1->as_address_ptr();
2788     if (c->type() == T_INT) {
2789       __ cmpl(as_Address(addr), c->as_jint());
2790     } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2791 #ifdef _LP64
2792       // %%% Make this explode if addr isn't reachable until we figure out a
2793       // better strategy by giving noreg as the temp for as_Address
2794       __ cmpptr(rscratch1, as_Address(addr, noreg));
2795 #else
2796       __ cmpoop(as_Address(addr), c->as_jobject());
2797 #endif // _LP64
2798     } else {
2799       ShouldNotReachHere();
2800     }
2801 
2802   } else {
2803     ShouldNotReachHere();
2804   }
2805 }
2806 
2807 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2808   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2809     if (left->is_single_xmm()) {
2810       assert(right->is_single_xmm(), "must match");
2811       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2812     } else if (left->is_double_xmm()) {
2813       assert(right->is_double_xmm(), "must match");
2814       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2815 
2816     } else {
2817       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2818       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2819 
2820       assert(left->fpu() == 0, "left must be on TOS");
2821       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2822                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2823     }
2824   } else {
2825     assert(code == lir_cmp_l2i, "check");
2826 #ifdef _LP64
2827     Label done;
2828     Register dest = dst->as_register();
2829     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2830     __ movl(dest, -1);
2831     __ jccb(Assembler::less, done);
2832     __ set_byte_if_not_zero(dest);
2833     __ movzbl(dest, dest);
2834     __ bind(done);
2835 #else
2836     __ lcmp2int(left->as_register_hi(),
2837                 left->as_register_lo(),
2838                 right->as_register_hi(),
2839                 right->as_register_lo());
2840     move_regs(left->as_register_hi(), dst->as_register());
2841 #endif // _LP64
2842   }
2843 }
2844 
2845 
2846 void LIR_Assembler::align_call(LIR_Code code) {
2847   if (os::is_MP()) {
2848     // make sure that the displacement word of the call ends up word aligned
2849     int offset = __ offset();
2850     switch (code) {
2851       case lir_static_call:
2852       case lir_optvirtual_call:
2853       case lir_dynamic_call:
2854         offset += NativeCall::displacement_offset;
2855         break;
2856       case lir_icvirtual_call:
2857         offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2858       break;
2859       case lir_virtual_call:  // currently, sparc-specific for niagara
2860       default: ShouldNotReachHere();
2861     }
2862     __ align(BytesPerWord, offset);
2863   }
2864 }
2865 
2866 
2867 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2868   assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2869          "must be aligned");
2870   __ call(AddressLiteral(op->addr(), rtype));
2871   add_call_info(code_offset(), op->info());
2872 }
2873 
2874 
2875 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2876   __ ic_call(op->addr());
2877   add_call_info(code_offset(), op->info());
2878   assert(!os::is_MP() ||
2879          (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2880          "must be aligned");
2881 }
2882 
2883 
2884 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2885 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2886   ShouldNotReachHere();
2887 }
2888 
2889 
2890 void LIR_Assembler::emit_static_call_stub() {
2891   address call_pc = __ pc();
2892   address stub = __ start_a_stub(call_stub_size);
2893   if (stub == NULL) {
2894     bailout("static call stub overflow");
2895     return;
2896   }
2897 
2898   int start = __ offset();
2899   if (os::is_MP()) {
2900     // make sure that the displacement word of the call ends up word aligned
2901     __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2902   }
2903   __ relocate(static_stub_Relocation::spec(call_pc));
2904   __ mov_metadata(rbx, (Metadata*)NULL);
2905   // must be set to -1 at code generation time
2906   assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2907   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2908   __ jump(RuntimeAddress(__ pc()));
2909 
2910   assert(__ offset() - start <= call_stub_size, "stub too big");
2911   __ end_a_stub();
2912 }
2913 
2914 
2915 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2916   assert(exceptionOop->as_register() == rax, "must match");
2917   assert(exceptionPC->as_register() == rdx, "must match");
2918 
2919   // exception object is not added to oop map by LinearScan
2920   // (LinearScan assumes that no oops are in fixed registers)
2921   info->add_register_oop(exceptionOop);
2922   Runtime1::StubID unwind_id;
2923 
2924   // get current pc information
2925   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2926   int pc_for_athrow_offset = __ offset();
2927   InternalAddress pc_for_athrow(__ pc());
2928   __ lea(exceptionPC->as_register(), pc_for_athrow);
2929   add_call_info(pc_for_athrow_offset, info); // for exception handler
2930 
2931   __ verify_not_null_oop(rax);
2932   // search an exception handler (rax: exception oop, rdx: throwing pc)
2933   if (compilation()->has_fpu_code()) {
2934     unwind_id = Runtime1::handle_exception_id;
2935   } else {
2936     unwind_id = Runtime1::handle_exception_nofpu_id;
2937   }
2938   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2939 
2940   // enough room for two byte trap
2941   __ nop();
2942 }
2943 
2944 
2945 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2946   assert(exceptionOop->as_register() == rax, "must match");
2947 
2948   __ jmp(_unwind_handler_entry);
2949 }
2950 
2951 
2952 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2953 
2954   // optimized version for linear scan:
2955   // * count must be already in ECX (guaranteed by LinearScan)
2956   // * left and dest must be equal
2957   // * tmp must be unused
2958   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2959   assert(left == dest, "left and dest must be equal");
2960   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2961 
2962   if (left->is_single_cpu()) {
2963     Register value = left->as_register();
2964     assert(value != SHIFT_count, "left cannot be ECX");
2965 
2966     switch (code) {
2967       case lir_shl:  __ shll(value); break;
2968       case lir_shr:  __ sarl(value); break;
2969       case lir_ushr: __ shrl(value); break;
2970       default: ShouldNotReachHere();
2971     }
2972   } else if (left->is_double_cpu()) {
2973     Register lo = left->as_register_lo();
2974     Register hi = left->as_register_hi();
2975     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2976 #ifdef _LP64
2977     switch (code) {
2978       case lir_shl:  __ shlptr(lo);        break;
2979       case lir_shr:  __ sarptr(lo);        break;
2980       case lir_ushr: __ shrptr(lo);        break;
2981       default: ShouldNotReachHere();
2982     }
2983 #else
2984 
2985     switch (code) {
2986       case lir_shl:  __ lshl(hi, lo);        break;
2987       case lir_shr:  __ lshr(hi, lo, true);  break;
2988       case lir_ushr: __ lshr(hi, lo, false); break;
2989       default: ShouldNotReachHere();
2990     }
2991 #endif // LP64
2992   } else {
2993     ShouldNotReachHere();
2994   }
2995 }
2996 
2997 
2998 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2999   if (dest->is_single_cpu()) {
3000     // first move left into dest so that left is not destroyed by the shift
3001     Register value = dest->as_register();
3002     count = count & 0x1F; // Java spec
3003 
3004     move_regs(left->as_register(), value);
3005     switch (code) {
3006       case lir_shl:  __ shll(value, count); break;
3007       case lir_shr:  __ sarl(value, count); break;
3008       case lir_ushr: __ shrl(value, count); break;
3009       default: ShouldNotReachHere();
3010     }
3011   } else if (dest->is_double_cpu()) {
3012 #ifndef _LP64
3013     Unimplemented();
3014 #else
3015     // first move left into dest so that left is not destroyed by the shift
3016     Register value = dest->as_register_lo();
3017     count = count & 0x1F; // Java spec
3018 
3019     move_regs(left->as_register_lo(), value);
3020     switch (code) {
3021       case lir_shl:  __ shlptr(value, count); break;
3022       case lir_shr:  __ sarptr(value, count); break;
3023       case lir_ushr: __ shrptr(value, count); break;
3024       default: ShouldNotReachHere();
3025     }
3026 #endif // _LP64
3027   } else {
3028     ShouldNotReachHere();
3029   }
3030 }
3031 
3032 
3033 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3034   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3035   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3036   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3037   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3038 }
3039 
3040 
3041 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3042   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3043   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3044   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3045   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3046 }
3047 
3048 
3049 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
3050   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3051   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3052   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3053   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3054 }
3055 
3056 
3057 // This code replaces a call to arraycopy; no exception may
3058 // be thrown in this code, they must be thrown in the System.arraycopy
3059 // activation frame; we could save some checks if this would not be the case
3060 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3061   ciArrayKlass* default_type = op->expected_type();
3062   Register src = op->src()->as_register();
3063   Register dst = op->dst()->as_register();
3064   Register src_pos = op->src_pos()->as_register();
3065   Register dst_pos = op->dst_pos()->as_register();
3066   Register length  = op->length()->as_register();
3067   Register tmp = op->tmp()->as_register();
3068 
3069   CodeStub* stub = op->stub();
3070   int flags = op->flags();
3071   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3072   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3073 
3074   // if we don't know anything, just go through the generic arraycopy
3075   if (default_type == NULL) {
3076     Label done;
3077     // save outgoing arguments on stack in case call to System.arraycopy is needed
3078     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3079     // for interpreter calling conventions. Now we have to do it in new style conventions.
3080     // For the moment until C1 gets the new register allocator I just force all the
3081     // args to the right place (except the register args) and then on the back side
3082     // reload the register args properly if we go slow path. Yuck
3083 
3084     // These are proper for the calling convention
3085     store_parameter(length, 2);
3086     store_parameter(dst_pos, 1);
3087     store_parameter(dst, 0);
3088 
3089     // these are just temporary placements until we need to reload
3090     store_parameter(src_pos, 3);
3091     store_parameter(src, 4);
3092     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3093 
3094     address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3095 
3096     address copyfunc_addr = StubRoutines::generic_arraycopy();
3097 
3098     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3099 #ifdef _LP64
3100     // The arguments are in java calling convention so we can trivially shift them to C
3101     // convention
3102     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3103     __ mov(c_rarg0, j_rarg0);
3104     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3105     __ mov(c_rarg1, j_rarg1);
3106     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3107     __ mov(c_rarg2, j_rarg2);
3108     assert_different_registers(c_rarg3, j_rarg4);
3109     __ mov(c_rarg3, j_rarg3);
3110 #ifdef _WIN64
3111     // Allocate abi space for args but be sure to keep stack aligned
3112     __ subptr(rsp, 6*wordSize);
3113     store_parameter(j_rarg4, 4);
3114     if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3115       __ call(RuntimeAddress(C_entry));
3116     } else {
3117 #ifndef PRODUCT
3118       if (PrintC1Statistics) {
3119         __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3120       }
3121 #endif
3122       __ call(RuntimeAddress(copyfunc_addr));
3123     }
3124     __ addptr(rsp, 6*wordSize);
3125 #else
3126     __ mov(c_rarg4, j_rarg4);
3127     if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3128       __ call(RuntimeAddress(C_entry));
3129     } else {
3130 #ifndef PRODUCT
3131       if (PrintC1Statistics) {
3132         __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3133       }
3134 #endif
3135       __ call(RuntimeAddress(copyfunc_addr));
3136     }
3137 #endif // _WIN64
3138 #else
3139     __ push(length);
3140     __ push(dst_pos);
3141     __ push(dst);
3142     __ push(src_pos);
3143     __ push(src);
3144 
3145     if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3146       __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3147     } else {
3148 #ifndef PRODUCT
3149       if (PrintC1Statistics) {
3150         __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3151       }
3152 #endif
3153       __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3154     }
3155 
3156 #endif // _LP64
3157 
3158     __ cmpl(rax, 0);
3159     __ jcc(Assembler::equal, *stub->continuation());
3160 
3161     if (copyfunc_addr != NULL) {
3162       __ mov(tmp, rax);
3163       __ xorl(tmp, -1);
3164     }
3165 
3166     // Reload values from the stack so they are where the stub
3167     // expects them.
3168     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3169     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3170     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3171     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3172     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3173 
3174     if (copyfunc_addr != NULL) {
3175       __ subl(length, tmp);
3176       __ addl(src_pos, tmp);
3177       __ addl(dst_pos, tmp);
3178     }
3179     __ jmp(*stub->entry());
3180 
3181     __ bind(*stub->continuation());
3182     return;
3183   }
3184 
3185   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3186 
3187   int elem_size = type2aelembytes(basic_type);
3188   int shift_amount;
3189   Address::ScaleFactor scale;
3190 
3191   switch (elem_size) {
3192     case 1 :
3193       shift_amount = 0;
3194       scale = Address::times_1;
3195       break;
3196     case 2 :
3197       shift_amount = 1;
3198       scale = Address::times_2;
3199       break;
3200     case 4 :
3201       shift_amount = 2;
3202       scale = Address::times_4;
3203       break;
3204     case 8 :
3205       shift_amount = 3;
3206       scale = Address::times_8;
3207       break;
3208     default:
3209       ShouldNotReachHere();
3210   }
3211 
3212   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3213   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3214   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3215   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3216 
3217   // length and pos's are all sign extended at this point on 64bit
3218 
3219   // test for NULL
3220   if (flags & LIR_OpArrayCopy::src_null_check) {
3221     __ testptr(src, src);
3222     __ jcc(Assembler::zero, *stub->entry());
3223   }
3224   if (flags & LIR_OpArrayCopy::dst_null_check) {
3225     __ testptr(dst, dst);
3226     __ jcc(Assembler::zero, *stub->entry());
3227   }
3228 
3229   // check if negative
3230   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3231     __ testl(src_pos, src_pos);
3232     __ jcc(Assembler::less, *stub->entry());
3233   }
3234   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3235     __ testl(dst_pos, dst_pos);
3236     __ jcc(Assembler::less, *stub->entry());
3237   }
3238 
3239   if (flags & LIR_OpArrayCopy::src_range_check) {
3240     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3241     __ cmpl(tmp, src_length_addr);
3242     __ jcc(Assembler::above, *stub->entry());
3243   }
3244   if (flags & LIR_OpArrayCopy::dst_range_check) {
3245     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3246     __ cmpl(tmp, dst_length_addr);
3247     __ jcc(Assembler::above, *stub->entry());
3248   }
3249 
3250   if (flags & LIR_OpArrayCopy::length_positive_check) {
3251     __ testl(length, length);
3252     __ jcc(Assembler::less, *stub->entry());
3253     __ jcc(Assembler::zero, *stub->continuation());
3254   }
3255 
3256 #ifdef _LP64
3257   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3258   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3259 #endif
3260 
3261   if (flags & LIR_OpArrayCopy::type_check) {
3262     // We don't know the array types are compatible
3263     if (basic_type != T_OBJECT) {
3264       // Simple test for basic type arrays
3265       if (UseCompressedClassPointers) {
3266         __ movl(tmp, src_klass_addr);
3267         __ cmpl(tmp, dst_klass_addr);
3268       } else {
3269         __ movptr(tmp, src_klass_addr);
3270         __ cmpptr(tmp, dst_klass_addr);
3271       }
3272       __ jcc(Assembler::notEqual, *stub->entry());
3273     } else {
3274       // For object arrays, if src is a sub class of dst then we can
3275       // safely do the copy.
3276       Label cont, slow;
3277 
3278       __ push(src);
3279       __ push(dst);
3280 
3281       __ load_klass(src, src);
3282       __ load_klass(dst, dst);
3283 
3284       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3285 
3286       __ push(src);
3287       __ push(dst);
3288       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3289       __ pop(dst);
3290       __ pop(src);
3291 
3292       __ cmpl(src, 0);
3293       __ jcc(Assembler::notEqual, cont);
3294 
3295       __ bind(slow);
3296       __ pop(dst);
3297       __ pop(src);
3298 
3299       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3300       if (copyfunc_addr != NULL) { // use stub if available
3301         // src is not a sub class of dst so we have to do a
3302         // per-element check.
3303 
3304         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3305         if ((flags & mask) != mask) {
3306           // Check that at least both of them object arrays.
3307           assert(flags & mask, "one of the two should be known to be an object array");
3308 
3309           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3310             __ load_klass(tmp, src);
3311           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3312             __ load_klass(tmp, dst);
3313           }
3314           int lh_offset = in_bytes(Klass::layout_helper_offset());
3315           Address klass_lh_addr(tmp, lh_offset);
3316           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3317           __ cmpl(klass_lh_addr, objArray_lh);
3318           __ jcc(Assembler::notEqual, *stub->entry());
3319         }
3320 
3321        // Spill because stubs can use any register they like and it's
3322        // easier to restore just those that we care about.
3323        store_parameter(dst, 0);
3324        store_parameter(dst_pos, 1);
3325        store_parameter(length, 2);
3326        store_parameter(src_pos, 3);
3327        store_parameter(src, 4);
3328 
3329 #ifndef _LP64
3330         __ movptr(tmp, dst_klass_addr);
3331         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3332         __ push(tmp);
3333         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3334         __ push(tmp);
3335         __ push(length);
3336         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3337         __ push(tmp);
3338         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3339         __ push(tmp);
3340 
3341         __ call_VM_leaf(copyfunc_addr, 5);
3342 #else
3343         __ movl2ptr(length, length); //higher 32bits must be null
3344 
3345         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3346         assert_different_registers(c_rarg0, dst, dst_pos, length);
3347         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3348         assert_different_registers(c_rarg1, dst, length);
3349 
3350         __ mov(c_rarg2, length);
3351         assert_different_registers(c_rarg2, dst);
3352 
3353 #ifdef _WIN64
3354         // Allocate abi space for args but be sure to keep stack aligned
3355         __ subptr(rsp, 6*wordSize);
3356         __ load_klass(c_rarg3, dst);
3357         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3358         store_parameter(c_rarg3, 4);
3359         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3360         __ call(RuntimeAddress(copyfunc_addr));
3361         __ addptr(rsp, 6*wordSize);
3362 #else
3363         __ load_klass(c_rarg4, dst);
3364         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3365         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3366         __ call(RuntimeAddress(copyfunc_addr));
3367 #endif
3368 
3369 #endif
3370 
3371 #ifndef PRODUCT
3372         if (PrintC1Statistics) {
3373           Label failed;
3374           __ testl(rax, rax);
3375           __ jcc(Assembler::notZero, failed);
3376           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3377           __ bind(failed);
3378         }
3379 #endif
3380 
3381         __ testl(rax, rax);
3382         __ jcc(Assembler::zero, *stub->continuation());
3383 
3384 #ifndef PRODUCT
3385         if (PrintC1Statistics) {
3386           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3387         }
3388 #endif
3389 
3390         __ mov(tmp, rax);
3391 
3392         __ xorl(tmp, -1);
3393 
3394         // Restore previously spilled arguments
3395         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3396         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3397         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3398         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3399         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3400 
3401 
3402         __ subl(length, tmp);
3403         __ addl(src_pos, tmp);
3404         __ addl(dst_pos, tmp);
3405       }
3406 
3407       __ jmp(*stub->entry());
3408 
3409       __ bind(cont);
3410       __ pop(dst);
3411       __ pop(src);
3412     }
3413   }
3414 
3415 #ifdef ASSERT
3416   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3417     // Sanity check the known type with the incoming class.  For the
3418     // primitive case the types must match exactly with src.klass and
3419     // dst.klass each exactly matching the default type.  For the
3420     // object array case, if no type check is needed then either the
3421     // dst type is exactly the expected type and the src type is a
3422     // subtype which we can't check or src is the same array as dst
3423     // but not necessarily exactly of type default_type.
3424     Label known_ok, halt;
3425     __ mov_metadata(tmp, default_type->constant_encoding());
3426 #ifdef _LP64
3427     if (UseCompressedClassPointers) {
3428       __ encode_klass_not_null(tmp);
3429     }
3430 #endif
3431 
3432     if (basic_type != T_OBJECT) {
3433 
3434       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3435       else                   __ cmpptr(tmp, dst_klass_addr);
3436       __ jcc(Assembler::notEqual, halt);
3437       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3438       else                   __ cmpptr(tmp, src_klass_addr);
3439       __ jcc(Assembler::equal, known_ok);
3440     } else {
3441       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3442       else                   __ cmpptr(tmp, dst_klass_addr);
3443       __ jcc(Assembler::equal, known_ok);
3444       __ cmpptr(src, dst);
3445       __ jcc(Assembler::equal, known_ok);
3446     }
3447     __ bind(halt);
3448     __ stop("incorrect type information in arraycopy");
3449     __ bind(known_ok);
3450   }
3451 #endif
3452 
3453 #ifndef PRODUCT
3454   if (PrintC1Statistics) {
3455     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3456   }
3457 #endif
3458 
3459 #ifdef _LP64
3460   assert_different_registers(c_rarg0, dst, dst_pos, length);
3461   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3462   assert_different_registers(c_rarg1, length);
3463   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3464   __ mov(c_rarg2, length);
3465 
3466 #else
3467   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3468   store_parameter(tmp, 0);
3469   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3470   store_parameter(tmp, 1);
3471   store_parameter(length, 2);
3472 #endif // _LP64
3473 
3474   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3475   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3476   const char *name;
3477   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3478   __ call_VM_leaf(entry, 0);
3479 
3480   __ bind(*stub->continuation());
3481 }
3482 
3483 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3484   assert(op->crc()->is_single_cpu(),  "crc must be register");
3485   assert(op->val()->is_single_cpu(),  "byte value must be register");
3486   assert(op->result_opr()->is_single_cpu(), "result must be register");
3487   Register crc = op->crc()->as_register();
3488   Register val = op->val()->as_register();
3489   Register res = op->result_opr()->as_register();
3490 
3491   assert_different_registers(val, crc, res);
3492 
3493   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3494   __ notl(crc); // ~crc
3495   __ update_byte_crc32(crc, val, res);
3496   __ notl(crc); // ~crc
3497   __ mov(res, crc);
3498 }
3499 
3500 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3501   Register obj = op->obj_opr()->as_register();  // may not be an oop
3502   Register hdr = op->hdr_opr()->as_register();
3503   Register lock = op->lock_opr()->as_register();
3504   if (!UseFastLocking) {
3505     __ jmp(*op->stub()->entry());
3506   } else if (op->code() == lir_lock) {
3507     Register scratch = noreg;
3508     if (UseBiasedLocking) {
3509       scratch = op->scratch_opr()->as_register();
3510     }
3511     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3512     // add debug info for NullPointerException only if one is possible
3513     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3514     if (op->info() != NULL) {
3515       add_debug_info_for_null_check(null_check_offset, op->info());
3516     }
3517     // done
3518   } else if (op->code() == lir_unlock) {
3519     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3520     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3521   } else {
3522     Unimplemented();
3523   }
3524   __ bind(*op->stub()->continuation());
3525 }
3526 
3527 
3528 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3529   ciMethod* method = op->profiled_method();
3530   int bci          = op->profiled_bci();
3531   ciMethod* callee = op->profiled_callee();
3532 
3533   // Update counter for all call types
3534   ciMethodData* md = method->method_data_or_null();
3535   assert(md != NULL, "Sanity");
3536   ciProfileData* data = md->bci_to_data(bci);
3537   assert(data->is_CounterData(), "need CounterData for calls");
3538   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3539   Register mdo  = op->mdo()->as_register();
3540   __ mov_metadata(mdo, md->constant_encoding());
3541   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3542   Bytecodes::Code bc = method->java_code_at_bci(bci);
3543   const bool callee_is_static = callee->is_loaded() && callee->is_static();
3544   // Perform additional virtual call profiling for invokevirtual and
3545   // invokeinterface bytecodes
3546   if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3547       !callee_is_static &&  // required for optimized MH invokes
3548       C1ProfileVirtualCalls) {
3549     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3550     Register recv = op->recv()->as_register();
3551     assert_different_registers(mdo, recv);
3552     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3553     ciKlass* known_klass = op->known_holder();
3554     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3555       // We know the type that will be seen at this call site; we can
3556       // statically update the MethodData* rather than needing to do
3557       // dynamic tests on the receiver type
3558 
3559       // NOTE: we should probably put a lock around this search to
3560       // avoid collisions by concurrent compilations
3561       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3562       uint i;
3563       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3564         ciKlass* receiver = vc_data->receiver(i);
3565         if (known_klass->equals(receiver)) {
3566           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3567           __ addptr(data_addr, DataLayout::counter_increment);
3568           return;
3569         }
3570       }
3571 
3572       // Receiver type not found in profile data; select an empty slot
3573 
3574       // Note that this is less efficient than it should be because it
3575       // always does a write to the receiver part of the
3576       // VirtualCallData rather than just the first time
3577       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3578         ciKlass* receiver = vc_data->receiver(i);
3579         if (receiver == NULL) {
3580           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3581           __ mov_metadata(recv_addr, known_klass->constant_encoding());
3582           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3583           __ addptr(data_addr, DataLayout::counter_increment);
3584           return;
3585         }
3586       }
3587     } else {
3588       __ load_klass(recv, recv);
3589       Label update_done;
3590       type_profile_helper(mdo, md, data, recv, &update_done);
3591       // Receiver did not match any saved receiver and there is no empty row for it.
3592       // Increment total counter to indicate polymorphic case.
3593       __ addptr(counter_addr, DataLayout::counter_increment);
3594 
3595       __ bind(update_done);
3596     }
3597   } else {
3598     // Static call
3599     __ addptr(counter_addr, DataLayout::counter_increment);
3600   }
3601 }
3602 
3603 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3604   Register obj = op->obj()->as_register();
3605   Register tmp = op->tmp()->as_pointer_register();
3606   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3607   ciKlass* exact_klass = op->exact_klass();
3608   intptr_t current_klass = op->current_klass();
3609   bool not_null = op->not_null();
3610   bool no_conflict = op->no_conflict();
3611 
3612   Label update, next, none;
3613 
3614   bool do_null = !not_null;
3615   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3616   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3617 
3618   assert(do_null || do_update, "why are we here?");
3619   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3620 
3621   __ verify_oop(obj);
3622 
3623   if (tmp != obj) {
3624     __ mov(tmp, obj);
3625   }
3626   if (do_null) {
3627     __ testptr(tmp, tmp);
3628     __ jccb(Assembler::notZero, update);
3629     if (!TypeEntries::was_null_seen(current_klass)) {
3630       __ orptr(mdo_addr, TypeEntries::null_seen);
3631     }
3632     if (do_update) {
3633 #ifndef ASSERT
3634       __ jmpb(next);
3635     }
3636 #else
3637       __ jmp(next);
3638     }
3639   } else {
3640     __ testptr(tmp, tmp);
3641     __ jccb(Assembler::notZero, update);
3642     __ stop("unexpect null obj");
3643 #endif
3644   }
3645 
3646   __ bind(update);
3647 
3648   if (do_update) {
3649 #ifdef ASSERT
3650     if (exact_klass != NULL) {
3651       Label ok;
3652       __ load_klass(tmp, tmp);
3653       __ push(tmp);
3654       __ mov_metadata(tmp, exact_klass->constant_encoding());
3655       __ cmpptr(tmp, Address(rsp, 0));
3656       __ jccb(Assembler::equal, ok);
3657       __ stop("exact klass and actual klass differ");
3658       __ bind(ok);
3659       __ pop(tmp);
3660     }
3661 #endif
3662     if (!no_conflict) {
3663       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3664         if (exact_klass != NULL) {
3665           __ mov_metadata(tmp, exact_klass->constant_encoding());
3666         } else {
3667           __ load_klass(tmp, tmp);
3668         }
3669 
3670         __ xorptr(tmp, mdo_addr);
3671         __ testptr(tmp, TypeEntries::type_klass_mask);
3672         // klass seen before, nothing to do. The unknown bit may have been
3673         // set already but no need to check.
3674         __ jccb(Assembler::zero, next);
3675 
3676         __ testptr(tmp, TypeEntries::type_unknown);
3677         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3678 
3679         if (TypeEntries::is_type_none(current_klass)) {
3680           __ cmpptr(mdo_addr, 0);
3681           __ jccb(Assembler::equal, none);
3682           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3683           __ jccb(Assembler::equal, none);
3684           // There is a chance that the checks above (re-reading profiling
3685           // data from memory) fail if another thread has just set the
3686           // profiling to this obj's klass
3687           __ xorptr(tmp, mdo_addr);
3688           __ testptr(tmp, TypeEntries::type_klass_mask);
3689           __ jccb(Assembler::zero, next);
3690         }
3691       } else {
3692         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3693                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3694 
3695         __ movptr(tmp, mdo_addr);
3696         __ testptr(tmp, TypeEntries::type_unknown);
3697         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3698       }
3699 
3700       // different than before. Cannot keep accurate profile.
3701       __ orptr(mdo_addr, TypeEntries::type_unknown);
3702 
3703       if (TypeEntries::is_type_none(current_klass)) {
3704         __ jmpb(next);
3705 
3706         __ bind(none);
3707         // first time here. Set profile type.
3708         __ movptr(mdo_addr, tmp);
3709       }
3710     } else {
3711       // There's a single possible klass at this profile point
3712       assert(exact_klass != NULL, "should be");
3713       if (TypeEntries::is_type_none(current_klass)) {
3714         __ mov_metadata(tmp, exact_klass->constant_encoding());
3715         __ xorptr(tmp, mdo_addr);
3716         __ testptr(tmp, TypeEntries::type_klass_mask);
3717 #ifdef ASSERT
3718         __ jcc(Assembler::zero, next);
3719 
3720         {
3721           Label ok;
3722           __ push(tmp);
3723           __ cmpptr(mdo_addr, 0);
3724           __ jcc(Assembler::equal, ok);
3725           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3726           __ jcc(Assembler::equal, ok);
3727           // may have been set by another thread
3728           __ mov_metadata(tmp, exact_klass->constant_encoding());
3729           __ xorptr(tmp, mdo_addr);
3730           __ testptr(tmp, TypeEntries::type_mask);
3731           __ jcc(Assembler::zero, ok);
3732 
3733           __ stop("unexpected profiling mismatch");
3734           __ bind(ok);
3735           __ pop(tmp);
3736         }
3737 #else
3738         __ jccb(Assembler::zero, next);
3739 #endif
3740         // first time here. Set profile type.
3741         __ movptr(mdo_addr, tmp);
3742       } else {
3743         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3744                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3745 
3746         __ movptr(tmp, mdo_addr);
3747         __ testptr(tmp, TypeEntries::type_unknown);
3748         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3749 
3750         __ orptr(mdo_addr, TypeEntries::type_unknown);
3751       }
3752     }
3753 
3754     __ bind(next);
3755   }
3756 }
3757 
3758 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3759   Unimplemented();
3760 }
3761 
3762 
3763 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3764   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3765 }
3766 
3767 
3768 void LIR_Assembler::align_backward_branch_target() {
3769   __ align(BytesPerWord);
3770 }
3771 
3772 
3773 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3774   if (left->is_single_cpu()) {
3775     __ negl(left->as_register());
3776     move_regs(left->as_register(), dest->as_register());
3777 
3778   } else if (left->is_double_cpu()) {
3779     Register lo = left->as_register_lo();
3780 #ifdef _LP64
3781     Register dst = dest->as_register_lo();
3782     __ movptr(dst, lo);
3783     __ negptr(dst);
3784 #else
3785     Register hi = left->as_register_hi();
3786     __ lneg(hi, lo);
3787     if (dest->as_register_lo() == hi) {
3788       assert(dest->as_register_hi() != lo, "destroying register");
3789       move_regs(hi, dest->as_register_hi());
3790       move_regs(lo, dest->as_register_lo());
3791     } else {
3792       move_regs(lo, dest->as_register_lo());
3793       move_regs(hi, dest->as_register_hi());
3794     }
3795 #endif // _LP64
3796 
3797   } else if (dest->is_single_xmm()) {
3798     if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3799       __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3800     }
3801     if (UseAVX > 1) {
3802       __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3803                    ExternalAddress((address)float_signflip_pool));
3804     } else {
3805       __ xorps(dest->as_xmm_float_reg(),
3806                ExternalAddress((address)float_signflip_pool));
3807     }
3808   } else if (dest->is_double_xmm()) {
3809     if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3810       __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3811     }
3812     if (UseAVX > 1) {
3813       __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3814                    ExternalAddress((address)double_signflip_pool));
3815     } else {
3816       __ xorpd(dest->as_xmm_double_reg(),
3817                ExternalAddress((address)double_signflip_pool));
3818     }
3819   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3820     assert(left->fpu() == 0, "arg must be on TOS");
3821     assert(dest->fpu() == 0, "dest must be TOS");
3822     __ fchs();
3823 
3824   } else {
3825     ShouldNotReachHere();
3826   }
3827 }
3828 
3829 
3830 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3831   assert(addr->is_address() && dest->is_register(), "check");
3832   Register reg;
3833   reg = dest->as_pointer_register();
3834   __ lea(reg, as_Address(addr->as_address_ptr()));
3835 }
3836 
3837 
3838 
3839 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3840   assert(!tmp->is_valid(), "don't need temporary");
3841   __ call(RuntimeAddress(dest));
3842   if (info != NULL) {
3843     add_call_info_here(info);
3844   }
3845 }
3846 
3847 
3848 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3849   assert(type == T_LONG, "only for volatile long fields");
3850 
3851   if (info != NULL) {
3852     add_debug_info_for_null_check_here(info);
3853   }
3854 
3855   if (src->is_double_xmm()) {
3856     if (dest->is_double_cpu()) {
3857 #ifdef _LP64
3858       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3859 #else
3860       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3861       __ psrlq(src->as_xmm_double_reg(), 32);
3862       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3863 #endif // _LP64
3864     } else if (dest->is_double_stack()) {
3865       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3866     } else if (dest->is_address()) {
3867       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3868     } else {
3869       ShouldNotReachHere();
3870     }
3871 
3872   } else if (dest->is_double_xmm()) {
3873     if (src->is_double_stack()) {
3874       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3875     } else if (src->is_address()) {
3876       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3877     } else {
3878       ShouldNotReachHere();
3879     }
3880 
3881   } else if (src->is_double_fpu()) {
3882     assert(src->fpu_regnrLo() == 0, "must be TOS");
3883     if (dest->is_double_stack()) {
3884       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3885     } else if (dest->is_address()) {
3886       __ fistp_d(as_Address(dest->as_address_ptr()));
3887     } else {
3888       ShouldNotReachHere();
3889     }
3890 
3891   } else if (dest->is_double_fpu()) {
3892     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3893     if (src->is_double_stack()) {
3894       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3895     } else if (src->is_address()) {
3896       __ fild_d(as_Address(src->as_address_ptr()));
3897     } else {
3898       ShouldNotReachHere();
3899     }
3900   } else {
3901     ShouldNotReachHere();
3902   }
3903 }
3904 
3905 #ifdef ASSERT
3906 // emit run-time assertion
3907 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3908   assert(op->code() == lir_assert, "must be");
3909 
3910   if (op->in_opr1()->is_valid()) {
3911     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3912     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3913   } else {
3914     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3915     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3916   }
3917 
3918   Label ok;
3919   if (op->condition() != lir_cond_always) {
3920     Assembler::Condition acond = Assembler::zero;
3921     switch (op->condition()) {
3922       case lir_cond_equal:        acond = Assembler::equal;       break;
3923       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
3924       case lir_cond_less:         acond = Assembler::less;        break;
3925       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
3926       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3927       case lir_cond_greater:      acond = Assembler::greater;     break;
3928       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
3929       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
3930       default:                    ShouldNotReachHere();
3931     }
3932     __ jcc(acond, ok);
3933   }
3934   if (op->halt()) {
3935     const char* str = __ code_string(op->msg());
3936     __ stop(str);
3937   } else {
3938     breakpoint();
3939   }
3940   __ bind(ok);
3941 }
3942 #endif
3943 
3944 void LIR_Assembler::membar() {
3945   // QQQ sparc TSO uses this,
3946   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3947 }
3948 
3949 void LIR_Assembler::membar_acquire() {
3950   // No x86 machines currently require load fences
3951 }
3952 
3953 void LIR_Assembler::membar_release() {
3954   // No x86 machines currently require store fences
3955 }
3956 
3957 void LIR_Assembler::membar_loadload() {
3958   // no-op
3959   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3960 }
3961 
3962 void LIR_Assembler::membar_storestore() {
3963   // no-op
3964   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3965 }
3966 
3967 void LIR_Assembler::membar_loadstore() {
3968   // no-op
3969   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3970 }
3971 
3972 void LIR_Assembler::membar_storeload() {
3973   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3974 }
3975 
3976 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3977   assert(result_reg->is_register(), "check");
3978 #ifdef _LP64
3979   // __ get_thread(result_reg->as_register_lo());
3980   __ mov(result_reg->as_register(), r15_thread);
3981 #else
3982   __ get_thread(result_reg->as_register());
3983 #endif // _LP64
3984 }
3985 
3986 
3987 void LIR_Assembler::peephole(LIR_List*) {
3988   // do nothing for now
3989 }
3990 
3991 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3992   assert(data == dest, "xchg/xadd uses only 2 operands");
3993 
3994   if (data->type() == T_INT) {
3995     if (code == lir_xadd) {
3996       if (os::is_MP()) {
3997         __ lock();
3998       }
3999       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4000     } else {
4001       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4002     }
4003   } else if (data->is_oop()) {
4004     assert (code == lir_xchg, "xadd for oops");
4005     Register obj = data->as_register();
4006 #ifdef _LP64
4007     if (UseCompressedOops) {
4008       __ encode_heap_oop(obj);
4009       __ xchgl(obj, as_Address(src->as_address_ptr()));
4010       __ decode_heap_oop(obj);
4011     } else {
4012       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4013     }
4014 #else
4015     __ xchgl(obj, as_Address(src->as_address_ptr()));
4016 #endif
4017   } else if (data->type() == T_LONG) {
4018 #ifdef _LP64
4019     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4020     if (code == lir_xadd) {
4021       if (os::is_MP()) {
4022         __ lock();
4023       }
4024       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4025     } else {
4026       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4027     }
4028 #else
4029     ShouldNotReachHere();
4030 #endif
4031   } else {
4032     ShouldNotReachHere();
4033   }
4034 }
4035 
4036 #undef __