10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP
  26 #define CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP
  27 
  28 const int StackAlignmentInBytes  = 16;
  29 




  30 #define SUPPORTS_NATIVE_CX8
  31 
  32 // The expected size in bytes of a cache line, used to pad data structures.
  33 #if defined(TIERED)
  34   #ifdef _LP64
  35     // tiered, 64-bit, large machine
  36     #define DEFAULT_CACHE_LINE_SIZE 128
  37   #else
  38     // tiered, 32-bit, medium machine
  39     #define DEFAULT_CACHE_LINE_SIZE 64
  40   #endif
  41 #elif defined(COMPILER1)
  42   // pure C1, 32-bit, small machine
  43   // i486 was the last Intel chip with 16-byte cache line size
  44   #define DEFAULT_CACHE_LINE_SIZE 32
  45 #elif defined(COMPILER2) || defined(SHARK)
  46   #ifdef _LP64
  47     // pure C2, 64-bit, large machine
  48     #define DEFAULT_CACHE_LINE_SIZE 128
  49   #else

  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP
  26 #define CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP
  27 
  28 const int StackAlignmentInBytes  = 16;
  29 
  30 // Indicates whether the C calling conventions require that
  31 // 32-bit integer argument values are extended to 64 bits.
  32 const bool CCallingConventionRequiresIntsAsLongs = false;
  33 
  34 #define SUPPORTS_NATIVE_CX8
  35 
  36 // The expected size in bytes of a cache line, used to pad data structures.
  37 #if defined(TIERED)
  38   #ifdef _LP64
  39     // tiered, 64-bit, large machine
  40     #define DEFAULT_CACHE_LINE_SIZE 128
  41   #else
  42     // tiered, 32-bit, medium machine
  43     #define DEFAULT_CACHE_LINE_SIZE 64
  44   #endif
  45 #elif defined(COMPILER1)
  46   // pure C1, 32-bit, small machine
  47   // i486 was the last Intel chip with 16-byte cache line size
  48   #define DEFAULT_CACHE_LINE_SIZE 32
  49 #elif defined(COMPILER2) || defined(SHARK)
  50   #ifdef _LP64
  51     // pure C2, 64-bit, large machine
  52     #define DEFAULT_CACHE_LINE_SIZE 128
  53   #else