1 //
2 // Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedKlassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_klass_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if (Assembler::is_simm13(v_off)) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
580
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
592
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
598
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
604
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
610
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
614
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
618
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
626
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
634
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
639
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
644
645
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
659
660
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 assert(count*width == 8 && width <= 4, "sanity");
682 int bit_width = width * 8;
683 jlong val = con;
684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
685 for (int i = 0; i < count - 1; i++) {
686 val |= (val << bit_width);
687 }
688 jdouble dval = *((jdouble*) &val); // coerce to double type
689 return dval;
690 }
691
692 static inline jdouble replicate_immF(float con) {
693 // Replicate float con 2 times and pack into vector.
694 int val = *((int*)&con);
695 jlong lval = val;
696 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
697 jdouble dval = *((jdouble*) &lval); // coerce to double type
698 return dval;
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
703 f0 &= (1<<19)-1; // Mask displacement to 19 bits
704 int op = (f30 << 30) |
705 (f29 << 29) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f20 << 20) |
709 (f19 << 19) |
710 (f0 << 0);
711 cbuf.insts()->emit_int32(op);
712 }
713
714 // Standard Sparc opcode form2 field breakdown
715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
716 f0 >>= 10; // Drop 10 bits
717 f0 &= (1<<22)-1; // Mask displacement to 22 bits
718 int op = (f30 << 30) |
719 (f25 << 25) |
720 (f22 << 22) |
721 (f0 << 0);
722 cbuf.insts()->emit_int32(op);
723 }
724
725 // Standard Sparc opcode form3 field breakdown
726 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
727 int op = (f30 << 30) |
728 (f25 << 25) |
729 (f19 << 19) |
730 (f14 << 14) |
731 (f5 << 5) |
732 (f0 << 0);
733 cbuf.insts()->emit_int32(op);
734 }
735
736 // Standard Sparc opcode form3 field breakdown
737 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
738 simm13 &= (1<<13)-1; // Mask to 13 bits
739 int op = (f30 << 30) |
740 (f25 << 25) |
741 (f19 << 19) |
742 (f14 << 14) |
743 (1 << 13) | // bit to indicate immediate-mode
744 (simm13<<0);
745 cbuf.insts()->emit_int32(op);
746 }
747
748 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
749 simm10 &= (1<<10)-1; // Mask to 10 bits
750 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
751 }
752
753 #ifdef ASSERT
754 // Helper function for VerifyOops in emit_form3_mem_reg
755 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
756 warning("VerifyOops encountered unexpected instruction:");
757 n->dump(2);
758 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
759 }
760 #endif
761
762
763 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
764 int src1_enc, int disp32, int src2_enc, int dst_enc) {
765
766 #ifdef ASSERT
767 // The following code implements the +VerifyOops feature.
768 // It verifies oop values which are loaded into or stored out of
769 // the current method activation. +VerifyOops complements techniques
770 // like ScavengeALot, because it eagerly inspects oops in transit,
771 // as they enter or leave the stack, as opposed to ScavengeALot,
772 // which inspects oops "at rest", in the stack or heap, at safepoints.
773 // For this reason, +VerifyOops can sometimes detect bugs very close
774 // to their point of creation. It can also serve as a cross-check
775 // on the validity of oop maps, when used toegether with ScavengeALot.
776
777 // It would be good to verify oops at other points, especially
778 // when an oop is used as a base pointer for a load or store.
779 // This is presently difficult, because it is hard to know when
780 // a base address is biased or not. (If we had such information,
781 // it would be easy and useful to make a two-argument version of
782 // verify_oop which unbiases the base, and performs verification.)
783
784 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
785 bool is_verified_oop_base = false;
786 bool is_verified_oop_load = false;
787 bool is_verified_oop_store = false;
788 int tmp_enc = -1;
789 if (VerifyOops && src1_enc != R_SP_enc) {
790 // classify the op, mainly for an assert check
791 int st_op = 0, ld_op = 0;
792 switch (primary) {
793 case Assembler::stb_op3: st_op = Op_StoreB; break;
794 case Assembler::sth_op3: st_op = Op_StoreC; break;
795 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
796 case Assembler::stw_op3: st_op = Op_StoreI; break;
797 case Assembler::std_op3: st_op = Op_StoreL; break;
798 case Assembler::stf_op3: st_op = Op_StoreF; break;
799 case Assembler::stdf_op3: st_op = Op_StoreD; break;
800
801 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
803 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
804 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
805 case Assembler::ldx_op3: // may become LoadP or stay LoadI
806 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
807 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
808 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
809 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
810 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
811 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
812
813 default: ShouldNotReachHere();
814 }
815 if (tertiary == REGP_OP) {
816 if (st_op == Op_StoreI) st_op = Op_StoreP;
817 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
818 else ShouldNotReachHere();
819 if (st_op) {
820 // a store
821 // inputs are (0:control, 1:memory, 2:address, 3:value)
822 Node* n2 = n->in(3);
823 if (n2 != NULL) {
824 const Type* t = n2->bottom_type();
825 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
826 }
827 } else {
828 // a load
829 const Type* t = n->bottom_type();
830 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
831 }
832 }
833
834 if (ld_op) {
835 // a Load
836 // inputs are (0:control, 1:memory, 2:address)
837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
838 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
839 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
843 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
845 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
846 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
847 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
848 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
849 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
850 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
851 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
852 !(n->rule() == loadUB_rule)) {
853 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
854 }
855 } else if (st_op) {
856 // a Store
857 // inputs are (0:control, 1:memory, 2:address, 3:value)
858 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
859 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
860 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
861 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
862 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
863 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
864 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
865 verify_oops_warning(n, n->ideal_Opcode(), st_op);
866 }
867 }
868
869 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
870 Node* addr = n->in(2);
871 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
872 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
873 if (atype != NULL) {
874 intptr_t offset = get_offset_from_base(n, atype, disp32);
875 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
876 if (offset != offset_2) {
877 get_offset_from_base(n, atype, disp32);
878 get_offset_from_base_2(n, atype, disp32);
879 }
880 assert(offset == offset_2, "different offsets");
881 if (offset == disp32) {
882 // we now know that src1 is a true oop pointer
883 is_verified_oop_base = true;
884 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
885 if( primary == Assembler::ldd_op3 ) {
886 is_verified_oop_base = false; // Cannot 'ldd' into O7
887 } else {
888 tmp_enc = dst_enc;
889 dst_enc = R_O7_enc; // Load into O7; preserve source oop
890 assert(src1_enc != dst_enc, "");
891 }
892 }
893 }
894 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
895 || offset == oopDesc::mark_offset_in_bytes())) {
896 // loading the mark should not be allowed either, but
897 // we don't check this since it conflicts with InlineObjectHash
898 // usage of LoadINode to get the mark. We could keep the
899 // check if we create a new LoadMarkNode
900 // but do not verify the object before its header is initialized
901 ShouldNotReachHere();
902 }
903 }
904 }
905 }
906 }
907 #endif
908
909 uint instr;
910 instr = (Assembler::ldst_op << 30)
911 | (dst_enc << 25)
912 | (primary << 19)
913 | (src1_enc << 14);
914
915 uint index = src2_enc;
916 int disp = disp32;
917
918 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
919 disp += STACK_BIAS;
920
921 // We should have a compiler bailout here rather than a guarantee.
922 // Better yet would be some mechanism to handle variable-size matches correctly.
923 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
924
925 if( disp == 0 ) {
926 // use reg-reg form
927 // bit 13 is already zero
928 instr |= index;
929 } else {
930 // use reg-imm form
931 instr |= 0x00002000; // set bit 13 to one
932 instr |= disp & 0x1FFF;
933 }
934
935 cbuf.insts()->emit_int32(instr);
936
937 #ifdef ASSERT
938 {
939 MacroAssembler _masm(&cbuf);
940 if (is_verified_oop_base) {
941 __ verify_oop(reg_to_register_object(src1_enc));
942 }
943 if (is_verified_oop_store) {
944 __ verify_oop(reg_to_register_object(dst_enc));
945 }
946 if (tmp_enc != -1) {
947 __ mov(O7, reg_to_register_object(tmp_enc));
948 }
949 if (is_verified_oop_load) {
950 __ verify_oop(reg_to_register_object(dst_enc));
951 }
952 }
953 #endif
954 }
955
956 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
957 // The method which records debug information at every safepoint
958 // expects the call to be the first instruction in the snippet as
959 // it creates a PcDesc structure which tracks the offset of a call
960 // from the start of the codeBlob. This offset is computed as
961 // code_end() - code_begin() of the code which has been emitted
962 // so far.
963 // In this particular case we have skirted around the problem by
964 // putting the "mov" instruction in the delay slot but the problem
965 // may bite us again at some other point and a cleaner/generic
966 // solution using relocations would be needed.
967 MacroAssembler _masm(&cbuf);
968 __ set_inst_mark();
969
970 // We flush the current window just so that there is a valid stack copy
971 // the fact that the current window becomes active again instantly is
972 // not a problem there is nothing live in it.
973
974 #ifdef ASSERT
975 int startpos = __ offset();
976 #endif /* ASSERT */
977
978 __ call((address)entry_point, rtype);
979
980 if (preserve_g2) __ delayed()->mov(G2, L7);
981 else __ delayed()->nop();
982
983 if (preserve_g2) __ mov(L7, G2);
984
985 #ifdef ASSERT
986 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
987 #ifdef _LP64
988 // Trash argument dump slots.
989 __ set(0xb0b8ac0db0b8ac0d, G1);
990 __ mov(G1, G5);
991 __ stx(G1, SP, STACK_BIAS + 0x80);
992 __ stx(G1, SP, STACK_BIAS + 0x88);
993 __ stx(G1, SP, STACK_BIAS + 0x90);
994 __ stx(G1, SP, STACK_BIAS + 0x98);
995 __ stx(G1, SP, STACK_BIAS + 0xA0);
996 __ stx(G1, SP, STACK_BIAS + 0xA8);
997 #else // _LP64
998 // this is also a native call, so smash the first 7 stack locations,
999 // and the various registers
1000
1001 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1002 // while [SP+0x44..0x58] are the argument dump slots.
1003 __ set((intptr_t)0xbaadf00d, G1);
1004 __ mov(G1, G5);
1005 __ sllx(G1, 32, G1);
1006 __ or3(G1, G5, G1);
1007 __ mov(G1, G5);
1008 __ stx(G1, SP, 0x40);
1009 __ stx(G1, SP, 0x48);
1010 __ stx(G1, SP, 0x50);
1011 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1012 #endif // _LP64
1013 }
1014 #endif /*ASSERT*/
1015 }
1016
1017 //=============================================================================
1018 // REQUIRED FUNCTIONALITY for encoding
1019 void emit_lo(CodeBuffer &cbuf, int val) { }
1020 void emit_hi(CodeBuffer &cbuf, int val) { }
1021
1022
1023 //=============================================================================
1024 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1025
1026 int Compile::ConstantTable::calculate_table_base_offset() const {
1027 if (UseRDPCForConstantTableBase) {
1028 // The table base offset might be less but then it fits into
1029 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1030 return Assembler::min_simm13();
1031 } else {
1032 int offset = -(size() / 2);
1033 if (!Assembler::is_simm13(offset)) {
1034 offset = Assembler::min_simm13();
1035 }
1036 return offset;
1037 }
1038 }
1039
1040 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1041 Compile* C = ra_->C;
1042 Compile::ConstantTable& constant_table = C->constant_table();
1043 MacroAssembler _masm(&cbuf);
1044
1045 Register r = as_Register(ra_->get_encode(this));
1046 CodeSection* consts_section = __ code()->consts();
1047 int consts_size = consts_section->align_at_start(consts_section->size());
1048 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1049
1050 if (UseRDPCForConstantTableBase) {
1051 // For the following RDPC logic to work correctly the consts
1052 // section must be allocated right before the insts section. This
1053 // assert checks for that. The layout and the SECT_* constants
1054 // are defined in src/share/vm/asm/codeBuffer.hpp.
1055 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1056 int insts_offset = __ offset();
1057
1058 // Layout:
1059 //
1060 // |----------- consts section ------------|----------- insts section -----------...
1061 // |------ constant table -----|- padding -|------------------x----
1062 // \ current PC (RDPC instruction)
1063 // |<------------- consts_size ----------->|<- insts_offset ->|
1064 // \ table base
1065 // The table base offset is later added to the load displacement
1066 // so it has to be negative.
1067 int table_base_offset = -(consts_size + insts_offset);
1068 int disp;
1069
1070 // If the displacement from the current PC to the constant table
1071 // base fits into simm13 we set the constant table base to the
1072 // current PC.
1073 if (Assembler::is_simm13(table_base_offset)) {
1074 constant_table.set_table_base_offset(table_base_offset);
1075 disp = 0;
1076 } else {
1077 // Otherwise we set the constant table base offset to the
1078 // maximum negative displacement of load instructions to keep
1079 // the disp as small as possible:
1080 //
1081 // |<------------- consts_size ----------->|<- insts_offset ->|
1082 // |<--------- min_simm13 --------->|<-------- disp --------->|
1083 // \ table base
1084 table_base_offset = Assembler::min_simm13();
1085 constant_table.set_table_base_offset(table_base_offset);
1086 disp = (consts_size + insts_offset) + table_base_offset;
1087 }
1088
1089 __ rdpc(r);
1090
1091 if (disp != 0) {
1092 assert(r != O7, "need temporary");
1093 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1094 }
1095 }
1096 else {
1097 // Materialize the constant table base.
1098 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1099 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1100 AddressLiteral base(baseaddr, rspec);
1101 __ set(base, r);
1102 }
1103 }
1104
1105 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1106 if (UseRDPCForConstantTableBase) {
1107 // This is really the worst case but generally it's only 1 instruction.
1108 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1109 } else {
1110 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1111 }
1112 }
1113
1114 #ifndef PRODUCT
1115 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1116 char reg[128];
1117 ra_->dump_register(this, reg);
1118 if (UseRDPCForConstantTableBase) {
1119 st->print("RDPC %s\t! constant table base", reg);
1120 } else {
1121 st->print("SET &constanttable,%s\t! constant table base", reg);
1122 }
1123 }
1124 #endif
1125
1126
1127 //=============================================================================
1128
1129 #ifndef PRODUCT
1130 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1131 Compile* C = ra_->C;
1132
1133 for (int i = 0; i < OptoPrologueNops; i++) {
1134 st->print_cr("NOP"); st->print("\t");
1135 }
1136
1137 if( VerifyThread ) {
1138 st->print_cr("Verify_Thread"); st->print("\t");
1139 }
1140
1141 size_t framesize = C->frame_slots() << LogBytesPerInt;
1142
1143 // Calls to C2R adapters often do not accept exceptional returns.
1144 // We require that their callers must bang for them. But be careful, because
1145 // some VM calls (such as call site linkage) can use several kilobytes of
1146 // stack. But the stack safety zone should account for that.
1147 // See bugs 4446381, 4468289, 4497237.
1148 if (C->need_stack_bang(framesize)) {
1149 st->print_cr("! stack bang"); st->print("\t");
1150 }
1151
1152 if (Assembler::is_simm13(-framesize)) {
1153 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1154 } else {
1155 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1156 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1157 st->print ("SAVE R_SP,R_G3,R_SP");
1158 }
1159
1160 }
1161 #endif
1162
1163 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1164 Compile* C = ra_->C;
1165 MacroAssembler _masm(&cbuf);
1166
1167 for (int i = 0; i < OptoPrologueNops; i++) {
1168 __ nop();
1169 }
1170
1171 __ verify_thread();
1172
1173 size_t framesize = C->frame_slots() << LogBytesPerInt;
1174 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1175 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1176
1177 // Calls to C2R adapters often do not accept exceptional returns.
1178 // We require that their callers must bang for them. But be careful, because
1179 // some VM calls (such as call site linkage) can use several kilobytes of
1180 // stack. But the stack safety zone should account for that.
1181 // See bugs 4446381, 4468289, 4497237.
1182 if (C->need_stack_bang(framesize)) {
1183 __ generate_stack_overflow_check(framesize);
1184 }
1185
1186 if (Assembler::is_simm13(-framesize)) {
1187 __ save(SP, -framesize, SP);
1188 } else {
1189 __ sethi(-framesize & ~0x3ff, G3);
1190 __ add(G3, -framesize & 0x3ff, G3);
1191 __ save(SP, G3, SP);
1192 }
1193 C->set_frame_complete( __ offset() );
1194
1195 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1196 // NOTE: We set the table base offset here because users might be
1197 // emitted before MachConstantBaseNode.
1198 Compile::ConstantTable& constant_table = C->constant_table();
1199 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1200 }
1201 }
1202
1203 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1204 return MachNode::size(ra_);
1205 }
1206
1207 int MachPrologNode::reloc() const {
1208 return 10; // a large enough number
1209 }
1210
1211 //=============================================================================
1212 #ifndef PRODUCT
1213 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1214 Compile* C = ra_->C;
1215
1216 if( do_polling() && ra_->C->is_method_compilation() ) {
1217 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1218 #ifdef _LP64
1219 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1220 #else
1221 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1222 #endif
1223 }
1224
1225 if( do_polling() )
1226 st->print("RET\n\t");
1227
1228 st->print("RESTORE");
1229 }
1230 #endif
1231
1232 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 MacroAssembler _masm(&cbuf);
1234 Compile* C = ra_->C;
1235
1236 __ verify_thread();
1237
1238 // If this does safepoint polling, then do it here
1239 if( do_polling() && ra_->C->is_method_compilation() ) {
1240 AddressLiteral polling_page(os::get_polling_page());
1241 __ sethi(polling_page, L0);
1242 __ relocate(relocInfo::poll_return_type);
1243 __ ld_ptr( L0, 0, G0 );
1244 }
1245
1246 // If this is a return, then stuff the restore in the delay slot
1247 if( do_polling() ) {
1248 __ ret();
1249 __ delayed()->restore();
1250 } else {
1251 __ restore();
1252 }
1253 }
1254
1255 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1256 return MachNode::size(ra_);
1257 }
1258
1259 int MachEpilogNode::reloc() const {
1260 return 16; // a large enough number
1261 }
1262
1263 const Pipeline * MachEpilogNode::pipeline() const {
1264 return MachNode::pipeline_class();
1265 }
1266
1267 int MachEpilogNode::safepoint_offset() const {
1268 assert( do_polling(), "no return for this epilog node");
1269 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1270 }
1271
1272 //=============================================================================
1273
1274 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1275 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1276 static enum RC rc_class( OptoReg::Name reg ) {
1277 if( !OptoReg::is_valid(reg) ) return rc_bad;
1278 if (OptoReg::is_stack(reg)) return rc_stack;
1279 VMReg r = OptoReg::as_VMReg(reg);
1280 if (r->is_Register()) return rc_int;
1281 assert(r->is_FloatRegister(), "must be");
1282 return rc_float;
1283 }
1284
1285 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1286 if( cbuf ) {
1287 // Better yet would be some mechanism to handle variable-size matches correctly
1288 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1289 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1290 } else {
1291 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1292 }
1293 }
1294 #ifndef PRODUCT
1295 else if( !do_size ) {
1296 if( size != 0 ) st->print("\n\t");
1297 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1298 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1299 }
1300 #endif
1301 return size+4;
1302 }
1303
1304 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1305 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1306 #ifndef PRODUCT
1307 else if( !do_size ) {
1308 if( size != 0 ) st->print("\n\t");
1309 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1310 }
1311 #endif
1312 return size+4;
1313 }
1314
1315 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1316 PhaseRegAlloc *ra_,
1317 bool do_size,
1318 outputStream* st ) const {
1319 // Get registers to move
1320 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1321 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1322 OptoReg::Name dst_second = ra_->get_reg_second(this );
1323 OptoReg::Name dst_first = ra_->get_reg_first(this );
1324
1325 enum RC src_second_rc = rc_class(src_second);
1326 enum RC src_first_rc = rc_class(src_first);
1327 enum RC dst_second_rc = rc_class(dst_second);
1328 enum RC dst_first_rc = rc_class(dst_first);
1329
1330 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1331
1332 // Generate spill code!
1333 int size = 0;
1334
1335 if( src_first == dst_first && src_second == dst_second )
1336 return size; // Self copy, no move
1337
1338 // --------------------------------------
1339 // Check for mem-mem move. Load into unused float registers and fall into
1340 // the float-store case.
1341 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1342 int offset = ra_->reg2offset(src_first);
1343 // Further check for aligned-adjacent pair, so we can use a double load
1344 if( (src_first&1)==0 && src_first+1 == src_second ) {
1345 src_second = OptoReg::Name(R_F31_num);
1346 src_second_rc = rc_float;
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1348 } else {
1349 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1350 }
1351 src_first = OptoReg::Name(R_F30_num);
1352 src_first_rc = rc_float;
1353 }
1354
1355 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1356 int offset = ra_->reg2offset(src_second);
1357 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1358 src_second = OptoReg::Name(R_F31_num);
1359 src_second_rc = rc_float;
1360 }
1361
1362 // --------------------------------------
1363 // Check for float->int copy; requires a trip through memory
1364 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1365 int offset = frame::register_save_words*wordSize;
1366 if (cbuf) {
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1368 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1369 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1371 }
1372 #ifndef PRODUCT
1373 else if (!do_size) {
1374 if (size != 0) st->print("\n\t");
1375 st->print( "SUB R_SP,16,R_SP\n");
1376 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1377 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1378 st->print("\tADD R_SP,16,R_SP\n");
1379 }
1380 #endif
1381 size += 16;
1382 }
1383
1384 // Check for float->int copy on T4
1385 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1386 // Further check for aligned-adjacent pair, so we can use a double move
1387 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1388 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1389 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1390 }
1391 // Check for int->float copy on T4
1392 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1393 // Further check for aligned-adjacent pair, so we can use a double move
1394 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1395 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1396 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1397 }
1398
1399 // --------------------------------------
1400 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1401 // In such cases, I have to do the big-endian swap. For aligned targets, the
1402 // hardware does the flop for me. Doubles are always aligned, so no problem
1403 // there. Misaligned sources only come from native-long-returns (handled
1404 // special below).
1405 #ifndef _LP64
1406 if( src_first_rc == rc_int && // source is already big-endian
1407 src_second_rc != rc_bad && // 64-bit move
1408 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1409 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1410 // Do the big-endian flop.
1411 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1412 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1413 }
1414 #endif
1415
1416 // --------------------------------------
1417 // Check for integer reg-reg copy
1418 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1419 #ifndef _LP64
1420 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1421 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1422 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1423 // operand contains the least significant word of the 64-bit value and vice versa.
1424 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1425 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1426 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1427 if( cbuf ) {
1428 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1430 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1431 #ifndef PRODUCT
1432 } else if( !do_size ) {
1433 if( size != 0 ) st->print("\n\t");
1434 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1435 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1436 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1437 #endif
1438 }
1439 return size+12;
1440 }
1441 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1442 // returning a long value in I0/I1
1443 // a SpillCopy must be able to target a return instruction's reg_class
1444 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1445 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1446 // operand contains the least significant word of the 64-bit value and vice versa.
1447 OptoReg::Name tdest = dst_first;
1448
1449 if (src_first == dst_first) {
1450 tdest = OptoReg::Name(R_O7_num);
1451 size += 4;
1452 }
1453
1454 if( cbuf ) {
1455 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1456 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1457 // ShrL_reg_imm6
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1459 // ShrR_reg_imm6 src, 0, dst
1460 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1461 if (tdest != dst_first) {
1462 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1463 }
1464 }
1465 #ifndef PRODUCT
1466 else if( !do_size ) {
1467 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1468 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1469 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1470 if (tdest != dst_first) {
1471 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1472 }
1473 }
1474 #endif // PRODUCT
1475 return size+8;
1476 }
1477 #endif // !_LP64
1478 // Else normal reg-reg copy
1479 assert( src_second != dst_first, "smashed second before evacuating it" );
1480 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1481 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1482 // This moves an aligned adjacent pair.
1483 // See if we are done.
1484 if( src_first+1 == src_second && dst_first+1 == dst_second )
1485 return size;
1486 }
1487
1488 // Check for integer store
1489 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1490 int offset = ra_->reg2offset(dst_first);
1491 // Further check for aligned-adjacent pair, so we can use a double store
1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1493 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1494 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1495 }
1496
1497 // Check for integer load
1498 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1499 int offset = ra_->reg2offset(src_first);
1500 // Further check for aligned-adjacent pair, so we can use a double load
1501 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1502 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1503 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1504 }
1505
1506 // Check for float reg-reg copy
1507 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1508 // Further check for aligned-adjacent pair, so we can use a double move
1509 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1510 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1511 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1512 }
1513
1514 // Check for float store
1515 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1516 int offset = ra_->reg2offset(dst_first);
1517 // Further check for aligned-adjacent pair, so we can use a double store
1518 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1519 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1520 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1521 }
1522
1523 // Check for float load
1524 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1525 int offset = ra_->reg2offset(src_first);
1526 // Further check for aligned-adjacent pair, so we can use a double load
1527 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1528 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1529 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1530 }
1531
1532 // --------------------------------------------------------------------
1533 // Check for hi bits still needing moving. Only happens for misaligned
1534 // arguments to native calls.
1535 if( src_second == dst_second )
1536 return size; // Self copy; no move
1537 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1538
1539 #ifndef _LP64
1540 // In the LP64 build, all registers can be moved as aligned/adjacent
1541 // pairs, so there's never any need to move the high bits separately.
1542 // The 32-bit builds have to deal with the 32-bit ABI which can force
1543 // all sorts of silly alignment problems.
1544
1545 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1546 // 32-bits of a 64-bit register, but are needed in low bits of another
1547 // register (else it's a hi-bits-to-hi-bits copy which should have
1548 // happened already as part of a 64-bit move)
1549 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1550 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1551 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1552 // Shift src_second down to dst_second's low bits.
1553 if( cbuf ) {
1554 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1555 #ifndef PRODUCT
1556 } else if( !do_size ) {
1557 if( size != 0 ) st->print("\n\t");
1558 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1559 #endif
1560 }
1561 return size+4;
1562 }
1563
1564 // Check for high word integer store. Must down-shift the hi bits
1565 // into a temp register, then fall into the case of storing int bits.
1566 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1567 // Shift src_second down to dst_second's low bits.
1568 if( cbuf ) {
1569 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1570 #ifndef PRODUCT
1571 } else if( !do_size ) {
1572 if( size != 0 ) st->print("\n\t");
1573 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1574 #endif
1575 }
1576 size+=4;
1577 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1578 }
1579
1580 // Check for high word integer load
1581 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1582 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1583
1584 // Check for high word integer store
1585 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1586 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1587
1588 // Check for high word float store
1589 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1590 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1591
1592 #endif // !_LP64
1593
1594 Unimplemented();
1595 }
1596
1597 #ifndef PRODUCT
1598 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1599 implementation( NULL, ra_, false, st );
1600 }
1601 #endif
1602
1603 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1604 implementation( &cbuf, ra_, false, NULL );
1605 }
1606
1607 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1608 return implementation( NULL, ra_, true, NULL );
1609 }
1610
1611 //=============================================================================
1612 #ifndef PRODUCT
1613 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1614 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1615 }
1616 #endif
1617
1618 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1619 MacroAssembler _masm(&cbuf);
1620 for(int i = 0; i < _count; i += 1) {
1621 __ nop();
1622 }
1623 }
1624
1625 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1626 return 4 * _count;
1627 }
1628
1629
1630 //=============================================================================
1631 #ifndef PRODUCT
1632 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1633 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1634 int reg = ra_->get_reg_first(this);
1635 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1636 }
1637 #endif
1638
1639 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1640 MacroAssembler _masm(&cbuf);
1641 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1642 int reg = ra_->get_encode(this);
1643
1644 if (Assembler::is_simm13(offset)) {
1645 __ add(SP, offset, reg_to_register_object(reg));
1646 } else {
1647 __ set(offset, O7);
1648 __ add(SP, O7, reg_to_register_object(reg));
1649 }
1650 }
1651
1652 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1653 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1654 assert(ra_ == ra_->C->regalloc(), "sanity");
1655 return ra_->C->scratch_emit_size(this);
1656 }
1657
1658 //=============================================================================
1659
1660 // Offset from start of compiled java to interpreter stub to the load
1661 // constant that loads the inline cache (IC) (0 on sparc).
1662 const int CompiledStaticCall::comp_to_int_load_offset = 0;
1663
1664 // emit call stub, compiled java to interpretor
1665 void emit_java_to_interp(CodeBuffer &cbuf ) {
1666
1667 // Stub is fixed up when the corresponding call is converted from calling
1668 // compiled code to calling interpreted code.
1669 // set (empty), G5
1670 // jmp -1
1671
1672 address mark = cbuf.insts_mark(); // get mark within main instrs section
1673
1674 MacroAssembler _masm(&cbuf);
1675
1676 address base =
1677 __ start_a_stub(Compile::MAX_stubs_size);
1678 if (base == NULL) return; // CodeBuffer::expand failed
1679
1680 // static stub relocation stores the instruction address of the call
1681 __ relocate(static_stub_Relocation::spec(mark));
1682
1683 __ set_metadata(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1684
1685 __ set_inst_mark();
1686 AddressLiteral addrlit(-1);
1687 __ JUMP(addrlit, G3, 0);
1688
1689 __ delayed()->nop();
1690
1691 // Update current stubs pointer and restore code_end.
1692 __ end_a_stub();
1693 }
1694
1695 // size of call stub, compiled java to interpretor
1696 uint size_java_to_interp() {
1697 // This doesn't need to be accurate but it must be larger or equal to
1698 // the real size of the stub.
1699 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1700 NativeJump::instruction_size + // sethi; jmp; nop
1701 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1702 }
1703 // relocation entries for call stub, compiled java to interpretor
1704 uint reloc_java_to_interp() {
1705 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1706 }
1707
1708
1709 //=============================================================================
1710 #ifndef PRODUCT
1711 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1712 st->print_cr("\nUEP:");
1713 #ifdef _LP64
1714 if (UseCompressedKlassPointers) {
1715 assert(Universe::heap() != NULL, "java heap should be initialized");
1716 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1717 st->print_cr("\tSLL R_G5,3,R_G5");
1718 if (Universe::narrow_klass_base() != NULL)
1719 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1720 } else {
1721 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1722 }
1723 st->print_cr("\tCMP R_G5,R_G3" );
1724 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1725 #else // _LP64
1726 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1727 st->print_cr("\tCMP R_G5,R_G3" );
1728 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1729 #endif // _LP64
1730 }
1731 #endif
1732
1733 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1734 MacroAssembler _masm(&cbuf);
1735 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1736 Register temp_reg = G3;
1737 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1738
1739 // Load klass from receiver
1740 __ load_klass(O0, temp_reg);
1741 // Compare against expected klass
1742 __ cmp(temp_reg, G5_ic_reg);
1743 // Branch to miss code, checks xcc or icc depending
1744 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1745 }
1746
1747 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1748 return MachNode::size(ra_);
1749 }
1750
1751
1752 //=============================================================================
1753
1754 uint size_exception_handler() {
1755 if (TraceJumps) {
1756 return (400); // just a guess
1757 }
1758 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1759 }
1760
1761 uint size_deopt_handler() {
1762 if (TraceJumps) {
1763 return (400); // just a guess
1764 }
1765 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1766 }
1767
1768 // Emit exception handler code.
1769 int emit_exception_handler(CodeBuffer& cbuf) {
1770 Register temp_reg = G3;
1771 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1772 MacroAssembler _masm(&cbuf);
1773
1774 address base =
1775 __ start_a_stub(size_exception_handler());
1776 if (base == NULL) return 0; // CodeBuffer::expand failed
1777
1778 int offset = __ offset();
1779
1780 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1781 __ delayed()->nop();
1782
1783 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1784
1785 __ end_a_stub();
1786
1787 return offset;
1788 }
1789
1790 int emit_deopt_handler(CodeBuffer& cbuf) {
1791 // Can't use any of the current frame's registers as we may have deopted
1792 // at a poll and everything (including G3) can be live.
1793 Register temp_reg = L0;
1794 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1795 MacroAssembler _masm(&cbuf);
1796
1797 address base =
1798 __ start_a_stub(size_deopt_handler());
1799 if (base == NULL) return 0; // CodeBuffer::expand failed
1800
1801 int offset = __ offset();
1802 __ save_frame(0);
1803 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1804 __ delayed()->restore();
1805
1806 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1807
1808 __ end_a_stub();
1809 return offset;
1810
1811 }
1812
1813 // Given a register encoding, produce a Integer Register object
1814 static Register reg_to_register_object(int register_encoding) {
1815 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1816 return as_Register(register_encoding);
1817 }
1818
1819 // Given a register encoding, produce a single-precision Float Register object
1820 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1821 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1822 return as_SingleFloatRegister(register_encoding);
1823 }
1824
1825 // Given a register encoding, produce a double-precision Float Register object
1826 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1827 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1828 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1829 return as_DoubleFloatRegister(register_encoding);
1830 }
1831
1832 const bool Matcher::match_rule_supported(int opcode) {
1833 if (!has_match_rule(opcode))
1834 return false;
1835
1836 switch (opcode) {
1837 case Op_CountLeadingZerosI:
1838 case Op_CountLeadingZerosL:
1839 case Op_CountTrailingZerosI:
1840 case Op_CountTrailingZerosL:
1841 case Op_PopCountI:
1842 case Op_PopCountL:
1843 if (!UsePopCountInstruction)
1844 return false;
1845 case Op_CompareAndSwapL:
1846 #ifdef _LP64
1847 case Op_CompareAndSwapP:
1848 #endif
1849 if (!VM_Version::supports_cx8())
1850 return false;
1851 break;
1852 }
1853
1854 return true; // Per default match rules are supported.
1855 }
1856
1857 int Matcher::regnum_to_fpu_offset(int regnum) {
1858 return regnum - 32; // The FP registers are in the second chunk
1859 }
1860
1861 #ifdef ASSERT
1862 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1863 #endif
1864
1865 // Vector width in bytes
1866 const int Matcher::vector_width_in_bytes(BasicType bt) {
1867 assert(MaxVectorSize == 8, "");
1868 return 8;
1869 }
1870
1871 // Vector ideal reg
1872 const int Matcher::vector_ideal_reg(int size) {
1873 assert(MaxVectorSize == 8, "");
1874 return Op_RegD;
1875 }
1876
1877 const int Matcher::vector_shift_count_ideal_reg(int size) {
1878 fatal("vector shift is not supported");
1879 return Node::NotAMachineReg;
1880 }
1881
1882 // Limits on vector size (number of elements) loaded into vector.
1883 const int Matcher::max_vector_size(const BasicType bt) {
1884 assert(is_java_primitive(bt), "only primitive type vectors");
1885 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1886 }
1887
1888 const int Matcher::min_vector_size(const BasicType bt) {
1889 return max_vector_size(bt); // Same as max.
1890 }
1891
1892 // SPARC doesn't support misaligned vectors store/load.
1893 const bool Matcher::misaligned_vectors_ok() {
1894 return false;
1895 }
1896
1897 // USII supports fxtof through the whole range of number, USIII doesn't
1898 const bool Matcher::convL2FSupported(void) {
1899 return VM_Version::has_fast_fxtof();
1900 }
1901
1902 // Is this branch offset short enough that a short branch can be used?
1903 //
1904 // NOTE: If the platform does not provide any short branch variants, then
1905 // this method should return false for offset 0.
1906 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1907 // The passed offset is relative to address of the branch.
1908 // Don't need to adjust the offset.
1909 return UseCBCond && Assembler::is_simm12(offset);
1910 }
1911
1912 const bool Matcher::isSimpleConstant64(jlong value) {
1913 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1914 // Depends on optimizations in MacroAssembler::setx.
1915 int hi = (int)(value >> 32);
1916 int lo = (int)(value & ~0);
1917 return (hi == 0) || (hi == -1) || (lo == 0);
1918 }
1919
1920 // No scaling for the parameter the ClearArray node.
1921 const bool Matcher::init_array_count_is_in_bytes = true;
1922
1923 // Threshold size for cleararray.
1924 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1925
1926 // No additional cost for CMOVL.
1927 const int Matcher::long_cmove_cost() { return 0; }
1928
1929 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1930 const int Matcher::float_cmove_cost() {
1931 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1932 }
1933
1934 // Should the Matcher clone shifts on addressing modes, expecting them to
1935 // be subsumed into complex addressing expressions or compute them into
1936 // registers? True for Intel but false for most RISCs
1937 const bool Matcher::clone_shift_expressions = false;
1938
1939 // Do we need to mask the count passed to shift instructions or does
1940 // the cpu only look at the lower 5/6 bits anyway?
1941 const bool Matcher::need_masked_shift_count = false;
1942
1943 bool Matcher::narrow_oop_use_complex_address() {
1944 NOT_LP64(ShouldNotCallThis());
1945 assert(UseCompressedOops, "only for compressed oops code");
1946 return false;
1947 }
1948
1949 bool Matcher::narrow_klass_use_complex_address() {
1950 NOT_LP64(ShouldNotCallThis());
1951 assert(UseCompressedKlassPointers, "only for compressed klass code");
1952 return false;
1953 }
1954
1955 // Is it better to copy float constants, or load them directly from memory?
1956 // Intel can load a float constant from a direct address, requiring no
1957 // extra registers. Most RISCs will have to materialize an address into a
1958 // register first, so they would do better to copy the constant from stack.
1959 const bool Matcher::rematerialize_float_constants = false;
1960
1961 // If CPU can load and store mis-aligned doubles directly then no fixup is
1962 // needed. Else we split the double into 2 integer pieces and move it
1963 // piece-by-piece. Only happens when passing doubles into C code as the
1964 // Java calling convention forces doubles to be aligned.
1965 #ifdef _LP64
1966 const bool Matcher::misaligned_doubles_ok = true;
1967 #else
1968 const bool Matcher::misaligned_doubles_ok = false;
1969 #endif
1970
1971 // No-op on SPARC.
1972 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1973 }
1974
1975 // Advertise here if the CPU requires explicit rounding operations
1976 // to implement the UseStrictFP mode.
1977 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1978
1979 // Are floats conerted to double when stored to stack during deoptimization?
1980 // Sparc does not handle callee-save floats.
1981 bool Matcher::float_in_double() { return false; }
1982
1983 // Do ints take an entire long register or just half?
1984 // Note that we if-def off of _LP64.
1985 // The relevant question is how the int is callee-saved. In _LP64
1986 // the whole long is written but de-opt'ing will have to extract
1987 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1988 #ifdef _LP64
1989 const bool Matcher::int_in_long = true;
1990 #else
1991 const bool Matcher::int_in_long = false;
1992 #endif
1993
1994 // Return whether or not this register is ever used as an argument. This
1995 // function is used on startup to build the trampoline stubs in generateOptoStub.
1996 // Registers not mentioned will be killed by the VM call in the trampoline, and
1997 // arguments in those registers not be available to the callee.
1998 bool Matcher::can_be_java_arg( int reg ) {
1999 // Standard sparc 6 args in registers
2000 if( reg == R_I0_num ||
2001 reg == R_I1_num ||
2002 reg == R_I2_num ||
2003 reg == R_I3_num ||
2004 reg == R_I4_num ||
2005 reg == R_I5_num ) return true;
2006 #ifdef _LP64
2007 // 64-bit builds can pass 64-bit pointers and longs in
2008 // the high I registers
2009 if( reg == R_I0H_num ||
2010 reg == R_I1H_num ||
2011 reg == R_I2H_num ||
2012 reg == R_I3H_num ||
2013 reg == R_I4H_num ||
2014 reg == R_I5H_num ) return true;
2015
2016 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2017 return true;
2018 }
2019
2020 #else
2021 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2022 // Longs cannot be passed in O regs, because O regs become I regs
2023 // after a 'save' and I regs get their high bits chopped off on
2024 // interrupt.
2025 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2026 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2027 #endif
2028 // A few float args in registers
2029 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2030
2031 return false;
2032 }
2033
2034 bool Matcher::is_spillable_arg( int reg ) {
2035 return can_be_java_arg(reg);
2036 }
2037
2038 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2039 // Use hardware SDIVX instruction when it is
2040 // faster than a code which use multiply.
2041 return VM_Version::has_fast_idiv();
2042 }
2043
2044 // Register for DIVI projection of divmodI
2045 RegMask Matcher::divI_proj_mask() {
2046 ShouldNotReachHere();
2047 return RegMask();
2048 }
2049
2050 // Register for MODI projection of divmodI
2051 RegMask Matcher::modI_proj_mask() {
2052 ShouldNotReachHere();
2053 return RegMask();
2054 }
2055
2056 // Register for DIVL projection of divmodL
2057 RegMask Matcher::divL_proj_mask() {
2058 ShouldNotReachHere();
2059 return RegMask();
2060 }
2061
2062 // Register for MODL projection of divmodL
2063 RegMask Matcher::modL_proj_mask() {
2064 ShouldNotReachHere();
2065 return RegMask();
2066 }
2067
2068 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2069 return L7_REGP_mask();
2070 }
2071
2072 %}
2073
2074
2075 // The intptr_t operand types, defined by textual substitution.
2076 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2077 #ifdef _LP64
2078 #define immX immL
2079 #define immX13 immL13
2080 #define immX13m7 immL13m7
2081 #define iRegX iRegL
2082 #define g1RegX g1RegL
2083 #else
2084 #define immX immI
2085 #define immX13 immI13
2086 #define immX13m7 immI13m7
2087 #define iRegX iRegI
2088 #define g1RegX g1RegI
2089 #endif
2090
2091 //----------ENCODING BLOCK-----------------------------------------------------
2092 // This block specifies the encoding classes used by the compiler to output
2093 // byte streams. Encoding classes are parameterized macros used by
2094 // Machine Instruction Nodes in order to generate the bit encoding of the
2095 // instruction. Operands specify their base encoding interface with the
2096 // interface keyword. There are currently supported four interfaces,
2097 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2098 // operand to generate a function which returns its register number when
2099 // queried. CONST_INTER causes an operand to generate a function which
2100 // returns the value of the constant when queried. MEMORY_INTER causes an
2101 // operand to generate four functions which return the Base Register, the
2102 // Index Register, the Scale Value, and the Offset Value of the operand when
2103 // queried. COND_INTER causes an operand to generate six functions which
2104 // return the encoding code (ie - encoding bits for the instruction)
2105 // associated with each basic boolean condition for a conditional instruction.
2106 //
2107 // Instructions specify two basic values for encoding. Again, a function
2108 // is available to check if the constant displacement is an oop. They use the
2109 // ins_encode keyword to specify their encoding classes (which must be
2110 // a sequence of enc_class names, and their parameters, specified in
2111 // the encoding block), and they use the
2112 // opcode keyword to specify, in order, their primary, secondary, and
2113 // tertiary opcode. Only the opcode sections which a particular instruction
2114 // needs for encoding need to be specified.
2115 encode %{
2116 enc_class enc_untested %{
2117 #ifdef ASSERT
2118 MacroAssembler _masm(&cbuf);
2119 __ untested("encoding");
2120 #endif
2121 %}
2122
2123 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2124 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2125 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2126 %}
2127
2128 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2129 emit_form3_mem_reg(cbuf, this, $primary, -1,
2130 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2131 %}
2132
2133 enc_class form3_mem_prefetch_read( memory mem ) %{
2134 emit_form3_mem_reg(cbuf, this, $primary, -1,
2135 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2136 %}
2137
2138 enc_class form3_mem_prefetch_write( memory mem ) %{
2139 emit_form3_mem_reg(cbuf, this, $primary, -1,
2140 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2141 %}
2142
2143 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2144 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2145 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2146 guarantee($mem$$index == R_G0_enc, "double index?");
2147 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2148 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2149 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2150 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2151 %}
2152
2153 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2154 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2155 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2156 guarantee($mem$$index == R_G0_enc, "double index?");
2157 // Load long with 2 instructions
2158 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2159 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2160 %}
2161
2162 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2163 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2164 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2165 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2166 %}
2167
2168 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2169 // Encode a reg-reg copy. If it is useless, then empty encoding.
2170 if( $rs2$$reg != $rd$$reg )
2171 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2172 %}
2173
2174 // Target lo half of long
2175 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2176 // Encode a reg-reg copy. If it is useless, then empty encoding.
2177 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2178 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2179 %}
2180
2181 // Source lo half of long
2182 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2183 // Encode a reg-reg copy. If it is useless, then empty encoding.
2184 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2185 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2186 %}
2187
2188 // Target hi half of long
2189 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2190 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2191 %}
2192
2193 // Source lo half of long, and leave it sign extended.
2194 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2195 // Sign extend low half
2196 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2197 %}
2198
2199 // Source hi half of long, and leave it sign extended.
2200 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2201 // Shift high half to low half
2202 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2203 %}
2204
2205 // Source hi half of long
2206 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2207 // Encode a reg-reg copy. If it is useless, then empty encoding.
2208 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2209 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2210 %}
2211
2212 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2213 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2214 %}
2215
2216 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2217 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2218 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2219 %}
2220
2221 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2222 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2223 // clear if nothing else is happening
2224 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2225 // blt,a,pn done
2226 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2227 // mov dst,-1 in delay slot
2228 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2229 %}
2230
2231 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2232 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2233 %}
2234
2235 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2236 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2237 %}
2238
2239 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2240 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2241 %}
2242
2243 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2244 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2245 %}
2246
2247 enc_class move_return_pc_to_o1() %{
2248 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2249 %}
2250
2251 #ifdef _LP64
2252 /* %%% merge with enc_to_bool */
2253 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2254 MacroAssembler _masm(&cbuf);
2255
2256 Register src_reg = reg_to_register_object($src$$reg);
2257 Register dst_reg = reg_to_register_object($dst$$reg);
2258 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2259 %}
2260 #endif
2261
2262 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2263 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2264 MacroAssembler _masm(&cbuf);
2265
2266 Register p_reg = reg_to_register_object($p$$reg);
2267 Register q_reg = reg_to_register_object($q$$reg);
2268 Register y_reg = reg_to_register_object($y$$reg);
2269 Register tmp_reg = reg_to_register_object($tmp$$reg);
2270
2271 __ subcc( p_reg, q_reg, p_reg );
2272 __ add ( p_reg, y_reg, tmp_reg );
2273 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2274 %}
2275
2276 enc_class form_d2i_helper(regD src, regF dst) %{
2277 // fcmp %fcc0,$src,$src
2278 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2279 // branch %fcc0 not-nan, predict taken
2280 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2281 // fdtoi $src,$dst
2282 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2283 // fitos $dst,$dst (if nan)
2284 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2285 // clear $dst (if nan)
2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2287 // carry on here...
2288 %}
2289
2290 enc_class form_d2l_helper(regD src, regD dst) %{
2291 // fcmp %fcc0,$src,$src check for NAN
2292 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2293 // branch %fcc0 not-nan, predict taken
2294 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2295 // fdtox $src,$dst convert in delay slot
2296 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2297 // fxtod $dst,$dst (if nan)
2298 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2299 // clear $dst (if nan)
2300 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2301 // carry on here...
2302 %}
2303
2304 enc_class form_f2i_helper(regF src, regF dst) %{
2305 // fcmps %fcc0,$src,$src
2306 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2307 // branch %fcc0 not-nan, predict taken
2308 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2309 // fstoi $src,$dst
2310 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2311 // fitos $dst,$dst (if nan)
2312 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2313 // clear $dst (if nan)
2314 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2315 // carry on here...
2316 %}
2317
2318 enc_class form_f2l_helper(regF src, regD dst) %{
2319 // fcmps %fcc0,$src,$src
2320 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2321 // branch %fcc0 not-nan, predict taken
2322 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2323 // fstox $src,$dst
2324 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2325 // fxtod $dst,$dst (if nan)
2326 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2327 // clear $dst (if nan)
2328 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2329 // carry on here...
2330 %}
2331
2332 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2333 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2334 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2335 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2336
2337 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2338
2339 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2340 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2341
2342 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2343 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2344 %}
2345
2346 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2347 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2348 %}
2349
2350 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2351 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2352 %}
2353
2354 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2355 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2356 %}
2357
2358 enc_class form3_convI2F(regF rs2, regF rd) %{
2359 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2360 %}
2361
2362 // Encloding class for traceable jumps
2363 enc_class form_jmpl(g3RegP dest) %{
2364 emit_jmpl(cbuf, $dest$$reg);
2365 %}
2366
2367 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2368 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2369 %}
2370
2371 enc_class form2_nop() %{
2372 emit_nop(cbuf);
2373 %}
2374
2375 enc_class form2_illtrap() %{
2376 emit_illtrap(cbuf);
2377 %}
2378
2379
2380 // Compare longs and convert into -1, 0, 1.
2381 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2382 // CMP $src1,$src2
2383 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2384 // blt,a,pn done
2385 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2386 // mov dst,-1 in delay slot
2387 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2388 // bgt,a,pn done
2389 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2390 // mov dst,1 in delay slot
2391 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2392 // CLR $dst
2393 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2394 %}
2395
2396 enc_class enc_PartialSubtypeCheck() %{
2397 MacroAssembler _masm(&cbuf);
2398 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2399 __ delayed()->nop();
2400 %}
2401
2402 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2403 MacroAssembler _masm(&cbuf);
2404 Label* L = $labl$$label;
2405 Assembler::Predict predict_taken =
2406 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2407
2408 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2409 __ delayed()->nop();
2410 %}
2411
2412 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2413 MacroAssembler _masm(&cbuf);
2414 Label* L = $labl$$label;
2415 Assembler::Predict predict_taken =
2416 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2417
2418 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2419 __ delayed()->nop();
2420 %}
2421
2422 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2423 int op = (Assembler::arith_op << 30) |
2424 ($dst$$reg << 25) |
2425 (Assembler::movcc_op3 << 19) |
2426 (1 << 18) | // cc2 bit for 'icc'
2427 ($cmp$$cmpcode << 14) |
2428 (0 << 13) | // select register move
2429 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2430 ($src$$reg << 0);
2431 cbuf.insts()->emit_int32(op);
2432 %}
2433
2434 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2435 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2436 int op = (Assembler::arith_op << 30) |
2437 ($dst$$reg << 25) |
2438 (Assembler::movcc_op3 << 19) |
2439 (1 << 18) | // cc2 bit for 'icc'
2440 ($cmp$$cmpcode << 14) |
2441 (1 << 13) | // select immediate move
2442 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2443 (simm11 << 0);
2444 cbuf.insts()->emit_int32(op);
2445 %}
2446
2447 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2448 int op = (Assembler::arith_op << 30) |
2449 ($dst$$reg << 25) |
2450 (Assembler::movcc_op3 << 19) |
2451 (0 << 18) | // cc2 bit for 'fccX'
2452 ($cmp$$cmpcode << 14) |
2453 (0 << 13) | // select register move
2454 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2455 ($src$$reg << 0);
2456 cbuf.insts()->emit_int32(op);
2457 %}
2458
2459 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2460 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2461 int op = (Assembler::arith_op << 30) |
2462 ($dst$$reg << 25) |
2463 (Assembler::movcc_op3 << 19) |
2464 (0 << 18) | // cc2 bit for 'fccX'
2465 ($cmp$$cmpcode << 14) |
2466 (1 << 13) | // select immediate move
2467 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2468 (simm11 << 0);
2469 cbuf.insts()->emit_int32(op);
2470 %}
2471
2472 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2473 int op = (Assembler::arith_op << 30) |
2474 ($dst$$reg << 25) |
2475 (Assembler::fpop2_op3 << 19) |
2476 (0 << 18) |
2477 ($cmp$$cmpcode << 14) |
2478 (1 << 13) | // select register move
2479 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2480 ($primary << 5) | // select single, double or quad
2481 ($src$$reg << 0);
2482 cbuf.insts()->emit_int32(op);
2483 %}
2484
2485 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2486 int op = (Assembler::arith_op << 30) |
2487 ($dst$$reg << 25) |
2488 (Assembler::fpop2_op3 << 19) |
2489 (0 << 18) |
2490 ($cmp$$cmpcode << 14) |
2491 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2492 ($primary << 5) | // select single, double or quad
2493 ($src$$reg << 0);
2494 cbuf.insts()->emit_int32(op);
2495 %}
2496
2497 // Used by the MIN/MAX encodings. Same as a CMOV, but
2498 // the condition comes from opcode-field instead of an argument.
2499 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2500 int op = (Assembler::arith_op << 30) |
2501 ($dst$$reg << 25) |
2502 (Assembler::movcc_op3 << 19) |
2503 (1 << 18) | // cc2 bit for 'icc'
2504 ($primary << 14) |
2505 (0 << 13) | // select register move
2506 (0 << 11) | // cc1, cc0 bits for 'icc'
2507 ($src$$reg << 0);
2508 cbuf.insts()->emit_int32(op);
2509 %}
2510
2511 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2512 int op = (Assembler::arith_op << 30) |
2513 ($dst$$reg << 25) |
2514 (Assembler::movcc_op3 << 19) |
2515 (6 << 16) | // cc2 bit for 'xcc'
2516 ($primary << 14) |
2517 (0 << 13) | // select register move
2518 (0 << 11) | // cc1, cc0 bits for 'icc'
2519 ($src$$reg << 0);
2520 cbuf.insts()->emit_int32(op);
2521 %}
2522
2523 enc_class Set13( immI13 src, iRegI rd ) %{
2524 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2525 %}
2526
2527 enc_class SetHi22( immI src, iRegI rd ) %{
2528 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2529 %}
2530
2531 enc_class Set32( immI src, iRegI rd ) %{
2532 MacroAssembler _masm(&cbuf);
2533 __ set($src$$constant, reg_to_register_object($rd$$reg));
2534 %}
2535
2536 enc_class call_epilog %{
2537 if( VerifyStackAtCalls ) {
2538 MacroAssembler _masm(&cbuf);
2539 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2540 Register temp_reg = G3;
2541 __ add(SP, framesize, temp_reg);
2542 __ cmp(temp_reg, FP);
2543 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2544 }
2545 %}
2546
2547 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2548 // to G1 so the register allocator will not have to deal with the misaligned register
2549 // pair.
2550 enc_class adjust_long_from_native_call %{
2551 #ifndef _LP64
2552 if (returns_long()) {
2553 // sllx O0,32,O0
2554 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2555 // srl O1,0,O1
2556 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2557 // or O0,O1,G1
2558 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2559 }
2560 #endif
2561 %}
2562
2563 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2564 // CALL directly to the runtime
2565 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2566 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2567 /*preserve_g2=*/true);
2568 %}
2569
2570 enc_class preserve_SP %{
2571 MacroAssembler _masm(&cbuf);
2572 __ mov(SP, L7_mh_SP_save);
2573 %}
2574
2575 enc_class restore_SP %{
2576 MacroAssembler _masm(&cbuf);
2577 __ mov(L7_mh_SP_save, SP);
2578 %}
2579
2580 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2581 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2582 // who we intended to call.
2583 if ( !_method ) {
2584 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2585 } else if (_optimized_virtual) {
2586 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2587 } else {
2588 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2589 }
2590 if( _method ) { // Emit stub for static call
2591 emit_java_to_interp(cbuf);
2592 }
2593 %}
2594
2595 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2596 MacroAssembler _masm(&cbuf);
2597 __ set_inst_mark();
2598 int vtable_index = this->_vtable_index;
2599 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2600 if (vtable_index < 0) {
2601 // must be invalid_vtable_index, not nonvirtual_vtable_index
2602 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2603 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2604 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2605 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2606 __ ic_call((address)$meth$$method);
2607 } else {
2608 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2609 // Just go thru the vtable
2610 // get receiver klass (receiver already checked for non-null)
2611 // If we end up going thru a c2i adapter interpreter expects method in G5
2612 int off = __ offset();
2613 __ load_klass(O0, G3_scratch);
2614 int klass_load_size;
2615 if (UseCompressedKlassPointers) {
2616 assert(Universe::heap() != NULL, "java heap should be initialized");
2617 if (Universe::narrow_klass_base() == NULL)
2618 klass_load_size = 2*BytesPerInstWord;
2619 else
2620 klass_load_size = 3*BytesPerInstWord;
2621 } else {
2622 klass_load_size = 1*BytesPerInstWord;
2623 }
2624 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2625 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2626 if (Assembler::is_simm13(v_off)) {
2627 __ ld_ptr(G3, v_off, G5_method);
2628 } else {
2629 // Generate 2 instructions
2630 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2631 __ or3(G5_method, v_off & 0x3ff, G5_method);
2632 // ld_ptr, set_hi, set
2633 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2634 "Unexpected instruction size(s)");
2635 __ ld_ptr(G3, G5_method, G5_method);
2636 }
2637 // NOTE: for vtable dispatches, the vtable entry will never be null.
2638 // However it may very well end up in handle_wrong_method if the
2639 // method is abstract for the particular class.
2640 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2641 // jump to target (either compiled code or c2iadapter)
2642 __ jmpl(G3_scratch, G0, O7);
2643 __ delayed()->nop();
2644 }
2645 %}
2646
2647 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2648 MacroAssembler _masm(&cbuf);
2649
2650 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2651 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2652 // we might be calling a C2I adapter which needs it.
2653
2654 assert(temp_reg != G5_ic_reg, "conflicting registers");
2655 // Load nmethod
2656 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2657
2658 // CALL to compiled java, indirect the contents of G3
2659 __ set_inst_mark();
2660 __ callr(temp_reg, G0);
2661 __ delayed()->nop();
2662 %}
2663
2664 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2665 MacroAssembler _masm(&cbuf);
2666 Register Rdividend = reg_to_register_object($src1$$reg);
2667 Register Rdivisor = reg_to_register_object($src2$$reg);
2668 Register Rresult = reg_to_register_object($dst$$reg);
2669
2670 __ sra(Rdivisor, 0, Rdivisor);
2671 __ sra(Rdividend, 0, Rdividend);
2672 __ sdivx(Rdividend, Rdivisor, Rresult);
2673 %}
2674
2675 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2676 MacroAssembler _masm(&cbuf);
2677
2678 Register Rdividend = reg_to_register_object($src1$$reg);
2679 int divisor = $imm$$constant;
2680 Register Rresult = reg_to_register_object($dst$$reg);
2681
2682 __ sra(Rdividend, 0, Rdividend);
2683 __ sdivx(Rdividend, divisor, Rresult);
2684 %}
2685
2686 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2687 MacroAssembler _masm(&cbuf);
2688 Register Rsrc1 = reg_to_register_object($src1$$reg);
2689 Register Rsrc2 = reg_to_register_object($src2$$reg);
2690 Register Rdst = reg_to_register_object($dst$$reg);
2691
2692 __ sra( Rsrc1, 0, Rsrc1 );
2693 __ sra( Rsrc2, 0, Rsrc2 );
2694 __ mulx( Rsrc1, Rsrc2, Rdst );
2695 __ srlx( Rdst, 32, Rdst );
2696 %}
2697
2698 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2699 MacroAssembler _masm(&cbuf);
2700 Register Rdividend = reg_to_register_object($src1$$reg);
2701 Register Rdivisor = reg_to_register_object($src2$$reg);
2702 Register Rresult = reg_to_register_object($dst$$reg);
2703 Register Rscratch = reg_to_register_object($scratch$$reg);
2704
2705 assert(Rdividend != Rscratch, "");
2706 assert(Rdivisor != Rscratch, "");
2707
2708 __ sra(Rdividend, 0, Rdividend);
2709 __ sra(Rdivisor, 0, Rdivisor);
2710 __ sdivx(Rdividend, Rdivisor, Rscratch);
2711 __ mulx(Rscratch, Rdivisor, Rscratch);
2712 __ sub(Rdividend, Rscratch, Rresult);
2713 %}
2714
2715 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2716 MacroAssembler _masm(&cbuf);
2717
2718 Register Rdividend = reg_to_register_object($src1$$reg);
2719 int divisor = $imm$$constant;
2720 Register Rresult = reg_to_register_object($dst$$reg);
2721 Register Rscratch = reg_to_register_object($scratch$$reg);
2722
2723 assert(Rdividend != Rscratch, "");
2724
2725 __ sra(Rdividend, 0, Rdividend);
2726 __ sdivx(Rdividend, divisor, Rscratch);
2727 __ mulx(Rscratch, divisor, Rscratch);
2728 __ sub(Rdividend, Rscratch, Rresult);
2729 %}
2730
2731 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2732 MacroAssembler _masm(&cbuf);
2733
2734 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2735 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2736
2737 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2738 %}
2739
2740 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2741 MacroAssembler _masm(&cbuf);
2742
2743 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2744 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2745
2746 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2747 %}
2748
2749 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2750 MacroAssembler _masm(&cbuf);
2751
2752 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2753 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2754
2755 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2756 %}
2757
2758 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2759 MacroAssembler _masm(&cbuf);
2760
2761 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2762 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2763
2764 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2765 %}
2766
2767 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2768 MacroAssembler _masm(&cbuf);
2769
2770 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2771 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2772
2773 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2774 %}
2775
2776 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2777 MacroAssembler _masm(&cbuf);
2778
2779 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2780 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2781
2782 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2783 %}
2784
2785 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2786 MacroAssembler _masm(&cbuf);
2787
2788 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2789 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2790
2791 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2792 %}
2793
2794 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2795 MacroAssembler _masm(&cbuf);
2796
2797 Register Roop = reg_to_register_object($oop$$reg);
2798 Register Rbox = reg_to_register_object($box$$reg);
2799 Register Rscratch = reg_to_register_object($scratch$$reg);
2800 Register Rmark = reg_to_register_object($scratch2$$reg);
2801
2802 assert(Roop != Rscratch, "");
2803 assert(Roop != Rmark, "");
2804 assert(Rbox != Rscratch, "");
2805 assert(Rbox != Rmark, "");
2806
2807 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2808 %}
2809
2810 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2811 MacroAssembler _masm(&cbuf);
2812
2813 Register Roop = reg_to_register_object($oop$$reg);
2814 Register Rbox = reg_to_register_object($box$$reg);
2815 Register Rscratch = reg_to_register_object($scratch$$reg);
2816 Register Rmark = reg_to_register_object($scratch2$$reg);
2817
2818 assert(Roop != Rscratch, "");
2819 assert(Roop != Rmark, "");
2820 assert(Rbox != Rscratch, "");
2821 assert(Rbox != Rmark, "");
2822
2823 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2824 %}
2825
2826 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2827 MacroAssembler _masm(&cbuf);
2828 Register Rmem = reg_to_register_object($mem$$reg);
2829 Register Rold = reg_to_register_object($old$$reg);
2830 Register Rnew = reg_to_register_object($new$$reg);
2831
2832 // casx_under_lock picks 1 of 3 encodings:
2833 // For 32-bit pointers you get a 32-bit CAS
2834 // For 64-bit pointers you get a 64-bit CASX
2835 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2836 __ cmp( Rold, Rnew );
2837 %}
2838
2839 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2840 Register Rmem = reg_to_register_object($mem$$reg);
2841 Register Rold = reg_to_register_object($old$$reg);
2842 Register Rnew = reg_to_register_object($new$$reg);
2843
2844 MacroAssembler _masm(&cbuf);
2845 __ mov(Rnew, O7);
2846 __ casx(Rmem, Rold, O7);
2847 __ cmp( Rold, O7 );
2848 %}
2849
2850 // raw int cas, used for compareAndSwap
2851 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2852 Register Rmem = reg_to_register_object($mem$$reg);
2853 Register Rold = reg_to_register_object($old$$reg);
2854 Register Rnew = reg_to_register_object($new$$reg);
2855
2856 MacroAssembler _masm(&cbuf);
2857 __ mov(Rnew, O7);
2858 __ cas(Rmem, Rold, O7);
2859 __ cmp( Rold, O7 );
2860 %}
2861
2862 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2863 Register Rres = reg_to_register_object($res$$reg);
2864
2865 MacroAssembler _masm(&cbuf);
2866 __ mov(1, Rres);
2867 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2868 %}
2869
2870 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2871 Register Rres = reg_to_register_object($res$$reg);
2872
2873 MacroAssembler _masm(&cbuf);
2874 __ mov(1, Rres);
2875 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2876 %}
2877
2878 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2879 MacroAssembler _masm(&cbuf);
2880 Register Rdst = reg_to_register_object($dst$$reg);
2881 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2882 : reg_to_DoubleFloatRegister_object($src1$$reg);
2883 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2884 : reg_to_DoubleFloatRegister_object($src2$$reg);
2885
2886 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2887 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2888 %}
2889
2890
2891 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2892 Label Ldone, Lloop;
2893 MacroAssembler _masm(&cbuf);
2894
2895 Register str1_reg = reg_to_register_object($str1$$reg);
2896 Register str2_reg = reg_to_register_object($str2$$reg);
2897 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2898 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2899 Register result_reg = reg_to_register_object($result$$reg);
2900
2901 assert(result_reg != str1_reg &&
2902 result_reg != str2_reg &&
2903 result_reg != cnt1_reg &&
2904 result_reg != cnt2_reg ,
2905 "need different registers");
2906
2907 // Compute the minimum of the string lengths(str1_reg) and the
2908 // difference of the string lengths (stack)
2909
2910 // See if the lengths are different, and calculate min in str1_reg.
2911 // Stash diff in O7 in case we need it for a tie-breaker.
2912 Label Lskip;
2913 __ subcc(cnt1_reg, cnt2_reg, O7);
2914 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2915 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2916 // cnt2 is shorter, so use its count:
2917 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2918 __ bind(Lskip);
2919
2920 // reallocate cnt1_reg, cnt2_reg, result_reg
2921 // Note: limit_reg holds the string length pre-scaled by 2
2922 Register limit_reg = cnt1_reg;
2923 Register chr2_reg = cnt2_reg;
2924 Register chr1_reg = result_reg;
2925 // str{12} are the base pointers
2926
2927 // Is the minimum length zero?
2928 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2929 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2930 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2931
2932 // Load first characters
2933 __ lduh(str1_reg, 0, chr1_reg);
2934 __ lduh(str2_reg, 0, chr2_reg);
2935
2936 // Compare first characters
2937 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2938 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2939 assert(chr1_reg == result_reg, "result must be pre-placed");
2940 __ delayed()->nop();
2941
2942 {
2943 // Check after comparing first character to see if strings are equivalent
2944 Label LSkip2;
2945 // Check if the strings start at same location
2946 __ cmp(str1_reg, str2_reg);
2947 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2948 __ delayed()->nop();
2949
2950 // Check if the length difference is zero (in O7)
2951 __ cmp(G0, O7);
2952 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2953 __ delayed()->mov(G0, result_reg); // result is zero
2954
2955 // Strings might not be equal
2956 __ bind(LSkip2);
2957 }
2958
2959 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2960 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2961 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2962
2963 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2964 __ add(str1_reg, limit_reg, str1_reg);
2965 __ add(str2_reg, limit_reg, str2_reg);
2966 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2967
2968 // Compare the rest of the characters
2969 __ lduh(str1_reg, limit_reg, chr1_reg);
2970 __ bind(Lloop);
2971 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2972 __ lduh(str2_reg, limit_reg, chr2_reg);
2973 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2974 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2975 assert(chr1_reg == result_reg, "result must be pre-placed");
2976 __ delayed()->inccc(limit_reg, sizeof(jchar));
2977 // annul LDUH if branch is not taken to prevent access past end of string
2978 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2979 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2980
2981 // If strings are equal up to min length, return the length difference.
2982 __ mov(O7, result_reg);
2983
2984 // Otherwise, return the difference between the first mismatched chars.
2985 __ bind(Ldone);
2986 %}
2987
2988 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2989 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2990 MacroAssembler _masm(&cbuf);
2991
2992 Register str1_reg = reg_to_register_object($str1$$reg);
2993 Register str2_reg = reg_to_register_object($str2$$reg);
2994 Register cnt_reg = reg_to_register_object($cnt$$reg);
2995 Register tmp1_reg = O7;
2996 Register result_reg = reg_to_register_object($result$$reg);
2997
2998 assert(result_reg != str1_reg &&
2999 result_reg != str2_reg &&
3000 result_reg != cnt_reg &&
3001 result_reg != tmp1_reg ,
3002 "need different registers");
3003
3004 __ cmp(str1_reg, str2_reg); //same char[] ?
3005 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3006 __ delayed()->add(G0, 1, result_reg);
3007
3008 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
3009 __ delayed()->add(G0, 1, result_reg); // count == 0
3010
3011 //rename registers
3012 Register limit_reg = cnt_reg;
3013 Register chr1_reg = result_reg;
3014 Register chr2_reg = tmp1_reg;
3015
3016 //check for alignment and position the pointers to the ends
3017 __ or3(str1_reg, str2_reg, chr1_reg);
3018 __ andcc(chr1_reg, 0x3, chr1_reg);
3019 // notZero means at least one not 4-byte aligned.
3020 // We could optimize the case when both arrays are not aligned
3021 // but it is not frequent case and it requires additional checks.
3022 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3023 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3024
3025 // Compare char[] arrays aligned to 4 bytes.
3026 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3027 chr1_reg, chr2_reg, Ldone);
3028 __ ba(Ldone);
3029 __ delayed()->add(G0, 1, result_reg);
3030
3031 // char by char compare
3032 __ bind(Lchar);
3033 __ add(str1_reg, limit_reg, str1_reg);
3034 __ add(str2_reg, limit_reg, str2_reg);
3035 __ neg(limit_reg); //negate count
3036
3037 __ lduh(str1_reg, limit_reg, chr1_reg);
3038 // Lchar_loop
3039 __ bind(Lchar_loop);
3040 __ lduh(str2_reg, limit_reg, chr2_reg);
3041 __ cmp(chr1_reg, chr2_reg);
3042 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3043 __ delayed()->mov(G0, result_reg); //not equal
3044 __ inccc(limit_reg, sizeof(jchar));
3045 // annul LDUH if branch is not taken to prevent access past end of string
3046 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3047 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3048
3049 __ add(G0, 1, result_reg); //equal
3050
3051 __ bind(Ldone);
3052 %}
3053
3054 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3055 Label Lvector, Ldone, Lloop;
3056 MacroAssembler _masm(&cbuf);
3057
3058 Register ary1_reg = reg_to_register_object($ary1$$reg);
3059 Register ary2_reg = reg_to_register_object($ary2$$reg);
3060 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3061 Register tmp2_reg = O7;
3062 Register result_reg = reg_to_register_object($result$$reg);
3063
3064 int length_offset = arrayOopDesc::length_offset_in_bytes();
3065 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3066
3067 // return true if the same array
3068 __ cmp(ary1_reg, ary2_reg);
3069 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3070 __ delayed()->add(G0, 1, result_reg); // equal
3071
3072 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3073 __ delayed()->mov(G0, result_reg); // not equal
3074
3075 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3076 __ delayed()->mov(G0, result_reg); // not equal
3077
3078 //load the lengths of arrays
3079 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3080 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3081
3082 // return false if the two arrays are not equal length
3083 __ cmp(tmp1_reg, tmp2_reg);
3084 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3085 __ delayed()->mov(G0, result_reg); // not equal
3086
3087 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3088 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3089
3090 // load array addresses
3091 __ add(ary1_reg, base_offset, ary1_reg);
3092 __ add(ary2_reg, base_offset, ary2_reg);
3093
3094 // renaming registers
3095 Register chr1_reg = result_reg; // for characters in ary1
3096 Register chr2_reg = tmp2_reg; // for characters in ary2
3097 Register limit_reg = tmp1_reg; // length
3098
3099 // set byte count
3100 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3101
3102 // Compare char[] arrays aligned to 4 bytes.
3103 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3104 chr1_reg, chr2_reg, Ldone);
3105 __ add(G0, 1, result_reg); // equals
3106
3107 __ bind(Ldone);
3108 %}
3109
3110 enc_class enc_rethrow() %{
3111 cbuf.set_insts_mark();
3112 Register temp_reg = G3;
3113 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3114 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3115 MacroAssembler _masm(&cbuf);
3116 #ifdef ASSERT
3117 __ save_frame(0);
3118 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3119 __ sethi(last_rethrow_addrlit, L1);
3120 Address addr(L1, last_rethrow_addrlit.low10());
3121 __ get_pc(L2);
3122 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3123 __ st_ptr(L2, addr);
3124 __ restore();
3125 #endif
3126 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3127 __ delayed()->nop();
3128 %}
3129
3130 enc_class emit_mem_nop() %{
3131 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3132 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3133 %}
3134
3135 enc_class emit_fadd_nop() %{
3136 // Generates the instruction FMOVS f31,f31
3137 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3138 %}
3139
3140 enc_class emit_br_nop() %{
3141 // Generates the instruction BPN,PN .
3142 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3143 %}
3144
3145 enc_class enc_membar_acquire %{
3146 MacroAssembler _masm(&cbuf);
3147 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3148 %}
3149
3150 enc_class enc_membar_release %{
3151 MacroAssembler _masm(&cbuf);
3152 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3153 %}
3154
3155 enc_class enc_membar_volatile %{
3156 MacroAssembler _masm(&cbuf);
3157 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3158 %}
3159
3160 %}
3161
3162 //----------FRAME--------------------------------------------------------------
3163 // Definition of frame structure and management information.
3164 //
3165 // S T A C K L A Y O U T Allocators stack-slot number
3166 // | (to get allocators register number
3167 // G Owned by | | v add VMRegImpl::stack0)
3168 // r CALLER | |
3169 // o | +--------+ pad to even-align allocators stack-slot
3170 // w V | pad0 | numbers; owned by CALLER
3171 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3172 // h ^ | in | 5
3173 // | | args | 4 Holes in incoming args owned by SELF
3174 // | | | | 3
3175 // | | +--------+
3176 // V | | old out| Empty on Intel, window on Sparc
3177 // | old |preserve| Must be even aligned.
3178 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3179 // | | in | 3 area for Intel ret address
3180 // Owned by |preserve| Empty on Sparc.
3181 // SELF +--------+
3182 // | | pad2 | 2 pad to align old SP
3183 // | +--------+ 1
3184 // | | locks | 0
3185 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3186 // | | pad1 | 11 pad to align new SP
3187 // | +--------+
3188 // | | | 10
3189 // | | spills | 9 spills
3190 // V | | 8 (pad0 slot for callee)
3191 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3192 // ^ | out | 7
3193 // | | args | 6 Holes in outgoing args owned by CALLEE
3194 // Owned by +--------+
3195 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3196 // | new |preserve| Must be even-aligned.
3197 // | SP-+--------+----> Matcher::_new_SP, even aligned
3198 // | | |
3199 //
3200 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3201 // known from SELF's arguments and the Java calling convention.
3202 // Region 6-7 is determined per call site.
3203 // Note 2: If the calling convention leaves holes in the incoming argument
3204 // area, those holes are owned by SELF. Holes in the outgoing area
3205 // are owned by the CALLEE. Holes should not be nessecary in the
3206 // incoming area, as the Java calling convention is completely under
3207 // the control of the AD file. Doubles can be sorted and packed to
3208 // avoid holes. Holes in the outgoing arguments may be nessecary for
3209 // varargs C calling conventions.
3210 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3211 // even aligned with pad0 as needed.
3212 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3213 // region 6-11 is even aligned; it may be padded out more so that
3214 // the region from SP to FP meets the minimum stack alignment.
3215
3216 frame %{
3217 // What direction does stack grow in (assumed to be same for native & Java)
3218 stack_direction(TOWARDS_LOW);
3219
3220 // These two registers define part of the calling convention
3221 // between compiled code and the interpreter.
3222 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3223 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3224
3225 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3226 cisc_spilling_operand_name(indOffset);
3227
3228 // Number of stack slots consumed by a Monitor enter
3229 #ifdef _LP64
3230 sync_stack_slots(2);
3231 #else
3232 sync_stack_slots(1);
3233 #endif
3234
3235 // Compiled code's Frame Pointer
3236 frame_pointer(R_SP);
3237
3238 // Stack alignment requirement
3239 stack_alignment(StackAlignmentInBytes);
3240 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3241 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3242
3243 // Number of stack slots between incoming argument block and the start of
3244 // a new frame. The PROLOG must add this many slots to the stack. The
3245 // EPILOG must remove this many slots.
3246 in_preserve_stack_slots(0);
3247
3248 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3249 // for calls to C. Supports the var-args backing area for register parms.
3250 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3251 #ifdef _LP64
3252 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3253 varargs_C_out_slots_killed(12);
3254 #else
3255 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3256 varargs_C_out_slots_killed( 7);
3257 #endif
3258
3259 // The after-PROLOG location of the return address. Location of
3260 // return address specifies a type (REG or STACK) and a number
3261 // representing the register number (i.e. - use a register name) or
3262 // stack slot.
3263 return_addr(REG R_I7); // Ret Addr is in register I7
3264
3265 // Body of function which returns an OptoRegs array locating
3266 // arguments either in registers or in stack slots for calling
3267 // java
3268 calling_convention %{
3269 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3270
3271 %}
3272
3273 // Body of function which returns an OptoRegs array locating
3274 // arguments either in registers or in stack slots for callin
3275 // C.
3276 c_calling_convention %{
3277 // This is obviously always outgoing
3278 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3279 %}
3280
3281 // Location of native (C/C++) and interpreter return values. This is specified to
3282 // be the same as Java. In the 32-bit VM, long values are actually returned from
3283 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3284 // to and from the register pairs is done by the appropriate call and epilog
3285 // opcodes. This simplifies the register allocator.
3286 c_return_value %{
3287 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3288 #ifdef _LP64
3289 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3290 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3291 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3292 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3293 #else // !_LP64
3294 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3295 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3296 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3297 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3298 #endif
3299 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3300 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3301 %}
3302
3303 // Location of compiled Java return values. Same as C
3304 return_value %{
3305 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3306 #ifdef _LP64
3307 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3308 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3309 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3310 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3311 #else // !_LP64
3312 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3313 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3314 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3315 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3316 #endif
3317 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3318 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3319 %}
3320
3321 %}
3322
3323
3324 //----------ATTRIBUTES---------------------------------------------------------
3325 //----------Operand Attributes-------------------------------------------------
3326 op_attrib op_cost(1); // Required cost attribute
3327
3328 //----------Instruction Attributes---------------------------------------------
3329 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3330 ins_attrib ins_size(32); // Required size attribute (in bits)
3331 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3332 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3333 // non-matching short branch variant of some
3334 // long branch?
3335
3336 //----------OPERANDS-----------------------------------------------------------
3337 // Operand definitions must precede instruction definitions for correct parsing
3338 // in the ADLC because operands constitute user defined types which are used in
3339 // instruction definitions.
3340
3341 //----------Simple Operands----------------------------------------------------
3342 // Immediate Operands
3343 // Integer Immediate: 32-bit
3344 operand immI() %{
3345 match(ConI);
3346
3347 op_cost(0);
3348 // formats are generated automatically for constants and base registers
3349 format %{ %}
3350 interface(CONST_INTER);
3351 %}
3352
3353 // Integer Immediate: 8-bit
3354 operand immI8() %{
3355 predicate(Assembler::is_simm8(n->get_int()));
3356 match(ConI);
3357 op_cost(0);
3358 format %{ %}
3359 interface(CONST_INTER);
3360 %}
3361
3362 // Integer Immediate: 13-bit
3363 operand immI13() %{
3364 predicate(Assembler::is_simm13(n->get_int()));
3365 match(ConI);
3366 op_cost(0);
3367
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3371
3372 // Integer Immediate: 13-bit minus 7
3373 operand immI13m7() %{
3374 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3375 match(ConI);
3376 op_cost(0);
3377
3378 format %{ %}
3379 interface(CONST_INTER);
3380 %}
3381
3382 // Integer Immediate: 16-bit
3383 operand immI16() %{
3384 predicate(Assembler::is_simm16(n->get_int()));
3385 match(ConI);
3386 op_cost(0);
3387 format %{ %}
3388 interface(CONST_INTER);
3389 %}
3390
3391 // Unsigned (positive) Integer Immediate: 13-bit
3392 operand immU13() %{
3393 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3394 match(ConI);
3395 op_cost(0);
3396
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 // Integer Immediate: 6-bit
3402 operand immU6() %{
3403 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3404 match(ConI);
3405 op_cost(0);
3406 format %{ %}
3407 interface(CONST_INTER);
3408 %}
3409
3410 // Integer Immediate: 11-bit
3411 operand immI11() %{
3412 predicate(Assembler::is_simm11(n->get_int()));
3413 match(ConI);
3414 op_cost(0);
3415 format %{ %}
3416 interface(CONST_INTER);
3417 %}
3418
3419 // Integer Immediate: 5-bit
3420 operand immI5() %{
3421 predicate(Assembler::is_simm5(n->get_int()));
3422 match(ConI);
3423 op_cost(0);
3424 format %{ %}
3425 interface(CONST_INTER);
3426 %}
3427
3428 // Integer Immediate: 0-bit
3429 operand immI0() %{
3430 predicate(n->get_int() == 0);
3431 match(ConI);
3432 op_cost(0);
3433
3434 format %{ %}
3435 interface(CONST_INTER);
3436 %}
3437
3438 // Integer Immediate: the value 10
3439 operand immI10() %{
3440 predicate(n->get_int() == 10);
3441 match(ConI);
3442 op_cost(0);
3443
3444 format %{ %}
3445 interface(CONST_INTER);
3446 %}
3447
3448 // Integer Immediate: the values 0-31
3449 operand immU5() %{
3450 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3451 match(ConI);
3452 op_cost(0);
3453
3454 format %{ %}
3455 interface(CONST_INTER);
3456 %}
3457
3458 // Integer Immediate: the values 1-31
3459 operand immI_1_31() %{
3460 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3461 match(ConI);
3462 op_cost(0);
3463
3464 format %{ %}
3465 interface(CONST_INTER);
3466 %}
3467
3468 // Integer Immediate: the values 32-63
3469 operand immI_32_63() %{
3470 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3471 match(ConI);
3472 op_cost(0);
3473
3474 format %{ %}
3475 interface(CONST_INTER);
3476 %}
3477
3478 // Immediates for special shifts (sign extend)
3479
3480 // Integer Immediate: the value 16
3481 operand immI_16() %{
3482 predicate(n->get_int() == 16);
3483 match(ConI);
3484 op_cost(0);
3485
3486 format %{ %}
3487 interface(CONST_INTER);
3488 %}
3489
3490 // Integer Immediate: the value 24
3491 operand immI_24() %{
3492 predicate(n->get_int() == 24);
3493 match(ConI);
3494 op_cost(0);
3495
3496 format %{ %}
3497 interface(CONST_INTER);
3498 %}
3499
3500 // Integer Immediate: the value 255
3501 operand immI_255() %{
3502 predicate( n->get_int() == 255 );
3503 match(ConI);
3504 op_cost(0);
3505
3506 format %{ %}
3507 interface(CONST_INTER);
3508 %}
3509
3510 // Integer Immediate: the value 65535
3511 operand immI_65535() %{
3512 predicate(n->get_int() == 65535);
3513 match(ConI);
3514 op_cost(0);
3515
3516 format %{ %}
3517 interface(CONST_INTER);
3518 %}
3519
3520 // Long Immediate: the value FF
3521 operand immL_FF() %{
3522 predicate( n->get_long() == 0xFFL );
3523 match(ConL);
3524 op_cost(0);
3525
3526 format %{ %}
3527 interface(CONST_INTER);
3528 %}
3529
3530 // Long Immediate: the value FFFF
3531 operand immL_FFFF() %{
3532 predicate( n->get_long() == 0xFFFFL );
3533 match(ConL);
3534 op_cost(0);
3535
3536 format %{ %}
3537 interface(CONST_INTER);
3538 %}
3539
3540 // Pointer Immediate: 32 or 64-bit
3541 operand immP() %{
3542 match(ConP);
3543
3544 op_cost(5);
3545 // formats are generated automatically for constants and base registers
3546 format %{ %}
3547 interface(CONST_INTER);
3548 %}
3549
3550 #ifdef _LP64
3551 // Pointer Immediate: 64-bit
3552 operand immP_set() %{
3553 predicate(!VM_Version::is_niagara_plus());
3554 match(ConP);
3555
3556 op_cost(5);
3557 // formats are generated automatically for constants and base registers
3558 format %{ %}
3559 interface(CONST_INTER);
3560 %}
3561
3562 // Pointer Immediate: 64-bit
3563 // From Niagara2 processors on a load should be better than materializing.
3564 operand immP_load() %{
3565 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3566 match(ConP);
3567
3568 op_cost(5);
3569 // formats are generated automatically for constants and base registers
3570 format %{ %}
3571 interface(CONST_INTER);
3572 %}
3573
3574 // Pointer Immediate: 64-bit
3575 operand immP_no_oop_cheap() %{
3576 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3577 match(ConP);
3578
3579 op_cost(5);
3580 // formats are generated automatically for constants and base registers
3581 format %{ %}
3582 interface(CONST_INTER);
3583 %}
3584 #endif
3585
3586 operand immP13() %{
3587 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3588 match(ConP);
3589 op_cost(0);
3590
3591 format %{ %}
3592 interface(CONST_INTER);
3593 %}
3594
3595 operand immP0() %{
3596 predicate(n->get_ptr() == 0);
3597 match(ConP);
3598 op_cost(0);
3599
3600 format %{ %}
3601 interface(CONST_INTER);
3602 %}
3603
3604 operand immP_poll() %{
3605 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3606 match(ConP);
3607
3608 // formats are generated automatically for constants and base registers
3609 format %{ %}
3610 interface(CONST_INTER);
3611 %}
3612
3613 // Pointer Immediate
3614 operand immN()
3615 %{
3616 match(ConN);
3617
3618 op_cost(10);
3619 format %{ %}
3620 interface(CONST_INTER);
3621 %}
3622
3623 operand immNKlass()
3624 %{
3625 match(ConNKlass);
3626
3627 op_cost(10);
3628 format %{ %}
3629 interface(CONST_INTER);
3630 %}
3631
3632 // NULL Pointer Immediate
3633 operand immN0()
3634 %{
3635 predicate(n->get_narrowcon() == 0);
3636 match(ConN);
3637
3638 op_cost(0);
3639 format %{ %}
3640 interface(CONST_INTER);
3641 %}
3642
3643 operand immL() %{
3644 match(ConL);
3645 op_cost(40);
3646 // formats are generated automatically for constants and base registers
3647 format %{ %}
3648 interface(CONST_INTER);
3649 %}
3650
3651 operand immL0() %{
3652 predicate(n->get_long() == 0L);
3653 match(ConL);
3654 op_cost(0);
3655 // formats are generated automatically for constants and base registers
3656 format %{ %}
3657 interface(CONST_INTER);
3658 %}
3659
3660 // Integer Immediate: 5-bit
3661 operand immL5() %{
3662 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3663 match(ConL);
3664 op_cost(0);
3665 format %{ %}
3666 interface(CONST_INTER);
3667 %}
3668
3669 // Long Immediate: 13-bit
3670 operand immL13() %{
3671 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3672 match(ConL);
3673 op_cost(0);
3674
3675 format %{ %}
3676 interface(CONST_INTER);
3677 %}
3678
3679 // Long Immediate: 13-bit minus 7
3680 operand immL13m7() %{
3681 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3682 match(ConL);
3683 op_cost(0);
3684
3685 format %{ %}
3686 interface(CONST_INTER);
3687 %}
3688
3689 // Long Immediate: low 32-bit mask
3690 operand immL_32bits() %{
3691 predicate(n->get_long() == 0xFFFFFFFFL);
3692 match(ConL);
3693 op_cost(0);
3694
3695 format %{ %}
3696 interface(CONST_INTER);
3697 %}
3698
3699 // Long Immediate: cheap (materialize in <= 3 instructions)
3700 operand immL_cheap() %{
3701 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3702 match(ConL);
3703 op_cost(0);
3704
3705 format %{ %}
3706 interface(CONST_INTER);
3707 %}
3708
3709 // Long Immediate: expensive (materialize in > 3 instructions)
3710 operand immL_expensive() %{
3711 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3712 match(ConL);
3713 op_cost(0);
3714
3715 format %{ %}
3716 interface(CONST_INTER);
3717 %}
3718
3719 // Double Immediate
3720 operand immD() %{
3721 match(ConD);
3722
3723 op_cost(40);
3724 format %{ %}
3725 interface(CONST_INTER);
3726 %}
3727
3728 operand immD0() %{
3729 #ifdef _LP64
3730 // on 64-bit architectures this comparision is faster
3731 predicate(jlong_cast(n->getd()) == 0);
3732 #else
3733 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3734 #endif
3735 match(ConD);
3736
3737 op_cost(0);
3738 format %{ %}
3739 interface(CONST_INTER);
3740 %}
3741
3742 // Float Immediate
3743 operand immF() %{
3744 match(ConF);
3745
3746 op_cost(20);
3747 format %{ %}
3748 interface(CONST_INTER);
3749 %}
3750
3751 // Float Immediate: 0
3752 operand immF0() %{
3753 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3754 match(ConF);
3755
3756 op_cost(0);
3757 format %{ %}
3758 interface(CONST_INTER);
3759 %}
3760
3761 // Integer Register Operands
3762 // Integer Register
3763 operand iRegI() %{
3764 constraint(ALLOC_IN_RC(int_reg));
3765 match(RegI);
3766
3767 match(notemp_iRegI);
3768 match(g1RegI);
3769 match(o0RegI);
3770 match(iRegIsafe);
3771
3772 format %{ %}
3773 interface(REG_INTER);
3774 %}
3775
3776 operand notemp_iRegI() %{
3777 constraint(ALLOC_IN_RC(notemp_int_reg));
3778 match(RegI);
3779
3780 match(o0RegI);
3781
3782 format %{ %}
3783 interface(REG_INTER);
3784 %}
3785
3786 operand o0RegI() %{
3787 constraint(ALLOC_IN_RC(o0_regI));
3788 match(iRegI);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 // Pointer Register
3795 operand iRegP() %{
3796 constraint(ALLOC_IN_RC(ptr_reg));
3797 match(RegP);
3798
3799 match(lock_ptr_RegP);
3800 match(g1RegP);
3801 match(g2RegP);
3802 match(g3RegP);
3803 match(g4RegP);
3804 match(i0RegP);
3805 match(o0RegP);
3806 match(o1RegP);
3807 match(l7RegP);
3808
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand sp_ptr_RegP() %{
3814 constraint(ALLOC_IN_RC(sp_ptr_reg));
3815 match(RegP);
3816 match(iRegP);
3817
3818 format %{ %}
3819 interface(REG_INTER);
3820 %}
3821
3822 operand lock_ptr_RegP() %{
3823 constraint(ALLOC_IN_RC(lock_ptr_reg));
3824 match(RegP);
3825 match(i0RegP);
3826 match(o0RegP);
3827 match(o1RegP);
3828 match(l7RegP);
3829
3830 format %{ %}
3831 interface(REG_INTER);
3832 %}
3833
3834 operand g1RegP() %{
3835 constraint(ALLOC_IN_RC(g1_regP));
3836 match(iRegP);
3837
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3841
3842 operand g2RegP() %{
3843 constraint(ALLOC_IN_RC(g2_regP));
3844 match(iRegP);
3845
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3849
3850 operand g3RegP() %{
3851 constraint(ALLOC_IN_RC(g3_regP));
3852 match(iRegP);
3853
3854 format %{ %}
3855 interface(REG_INTER);
3856 %}
3857
3858 operand g1RegI() %{
3859 constraint(ALLOC_IN_RC(g1_regI));
3860 match(iRegI);
3861
3862 format %{ %}
3863 interface(REG_INTER);
3864 %}
3865
3866 operand g3RegI() %{
3867 constraint(ALLOC_IN_RC(g3_regI));
3868 match(iRegI);
3869
3870 format %{ %}
3871 interface(REG_INTER);
3872 %}
3873
3874 operand g4RegI() %{
3875 constraint(ALLOC_IN_RC(g4_regI));
3876 match(iRegI);
3877
3878 format %{ %}
3879 interface(REG_INTER);
3880 %}
3881
3882 operand g4RegP() %{
3883 constraint(ALLOC_IN_RC(g4_regP));
3884 match(iRegP);
3885
3886 format %{ %}
3887 interface(REG_INTER);
3888 %}
3889
3890 operand i0RegP() %{
3891 constraint(ALLOC_IN_RC(i0_regP));
3892 match(iRegP);
3893
3894 format %{ %}
3895 interface(REG_INTER);
3896 %}
3897
3898 operand o0RegP() %{
3899 constraint(ALLOC_IN_RC(o0_regP));
3900 match(iRegP);
3901
3902 format %{ %}
3903 interface(REG_INTER);
3904 %}
3905
3906 operand o1RegP() %{
3907 constraint(ALLOC_IN_RC(o1_regP));
3908 match(iRegP);
3909
3910 format %{ %}
3911 interface(REG_INTER);
3912 %}
3913
3914 operand o2RegP() %{
3915 constraint(ALLOC_IN_RC(o2_regP));
3916 match(iRegP);
3917
3918 format %{ %}
3919 interface(REG_INTER);
3920 %}
3921
3922 operand o7RegP() %{
3923 constraint(ALLOC_IN_RC(o7_regP));
3924 match(iRegP);
3925
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3929
3930 operand l7RegP() %{
3931 constraint(ALLOC_IN_RC(l7_regP));
3932 match(iRegP);
3933
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3937
3938 operand o7RegI() %{
3939 constraint(ALLOC_IN_RC(o7_regI));
3940 match(iRegI);
3941
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3945
3946 operand iRegN() %{
3947 constraint(ALLOC_IN_RC(int_reg));
3948 match(RegN);
3949
3950 format %{ %}
3951 interface(REG_INTER);
3952 %}
3953
3954 // Long Register
3955 operand iRegL() %{
3956 constraint(ALLOC_IN_RC(long_reg));
3957 match(RegL);
3958
3959 format %{ %}
3960 interface(REG_INTER);
3961 %}
3962
3963 operand o2RegL() %{
3964 constraint(ALLOC_IN_RC(o2_regL));
3965 match(iRegL);
3966
3967 format %{ %}
3968 interface(REG_INTER);
3969 %}
3970
3971 operand o7RegL() %{
3972 constraint(ALLOC_IN_RC(o7_regL));
3973 match(iRegL);
3974
3975 format %{ %}
3976 interface(REG_INTER);
3977 %}
3978
3979 operand g1RegL() %{
3980 constraint(ALLOC_IN_RC(g1_regL));
3981 match(iRegL);
3982
3983 format %{ %}
3984 interface(REG_INTER);
3985 %}
3986
3987 operand g3RegL() %{
3988 constraint(ALLOC_IN_RC(g3_regL));
3989 match(iRegL);
3990
3991 format %{ %}
3992 interface(REG_INTER);
3993 %}
3994
3995 // Int Register safe
3996 // This is 64bit safe
3997 operand iRegIsafe() %{
3998 constraint(ALLOC_IN_RC(long_reg));
3999
4000 match(iRegI);
4001
4002 format %{ %}
4003 interface(REG_INTER);
4004 %}
4005
4006 // Condition Code Flag Register
4007 operand flagsReg() %{
4008 constraint(ALLOC_IN_RC(int_flags));
4009 match(RegFlags);
4010
4011 format %{ "ccr" %} // both ICC and XCC
4012 interface(REG_INTER);
4013 %}
4014
4015 // Condition Code Register, unsigned comparisons.
4016 operand flagsRegU() %{
4017 constraint(ALLOC_IN_RC(int_flags));
4018 match(RegFlags);
4019
4020 format %{ "icc_U" %}
4021 interface(REG_INTER);
4022 %}
4023
4024 // Condition Code Register, pointer comparisons.
4025 operand flagsRegP() %{
4026 constraint(ALLOC_IN_RC(int_flags));
4027 match(RegFlags);
4028
4029 #ifdef _LP64
4030 format %{ "xcc_P" %}
4031 #else
4032 format %{ "icc_P" %}
4033 #endif
4034 interface(REG_INTER);
4035 %}
4036
4037 // Condition Code Register, long comparisons.
4038 operand flagsRegL() %{
4039 constraint(ALLOC_IN_RC(int_flags));
4040 match(RegFlags);
4041
4042 format %{ "xcc_L" %}
4043 interface(REG_INTER);
4044 %}
4045
4046 // Condition Code Register, floating comparisons, unordered same as "less".
4047 operand flagsRegF() %{
4048 constraint(ALLOC_IN_RC(float_flags));
4049 match(RegFlags);
4050 match(flagsRegF0);
4051
4052 format %{ %}
4053 interface(REG_INTER);
4054 %}
4055
4056 operand flagsRegF0() %{
4057 constraint(ALLOC_IN_RC(float_flag0));
4058 match(RegFlags);
4059
4060 format %{ %}
4061 interface(REG_INTER);
4062 %}
4063
4064
4065 // Condition Code Flag Register used by long compare
4066 operand flagsReg_long_LTGE() %{
4067 constraint(ALLOC_IN_RC(int_flags));
4068 match(RegFlags);
4069 format %{ "icc_LTGE" %}
4070 interface(REG_INTER);
4071 %}
4072 operand flagsReg_long_EQNE() %{
4073 constraint(ALLOC_IN_RC(int_flags));
4074 match(RegFlags);
4075 format %{ "icc_EQNE" %}
4076 interface(REG_INTER);
4077 %}
4078 operand flagsReg_long_LEGT() %{
4079 constraint(ALLOC_IN_RC(int_flags));
4080 match(RegFlags);
4081 format %{ "icc_LEGT" %}
4082 interface(REG_INTER);
4083 %}
4084
4085
4086 operand regD() %{
4087 constraint(ALLOC_IN_RC(dflt_reg));
4088 match(RegD);
4089
4090 match(regD_low);
4091
4092 format %{ %}
4093 interface(REG_INTER);
4094 %}
4095
4096 operand regF() %{
4097 constraint(ALLOC_IN_RC(sflt_reg));
4098 match(RegF);
4099
4100 format %{ %}
4101 interface(REG_INTER);
4102 %}
4103
4104 operand regD_low() %{
4105 constraint(ALLOC_IN_RC(dflt_low_reg));
4106 match(regD);
4107
4108 format %{ %}
4109 interface(REG_INTER);
4110 %}
4111
4112 // Special Registers
4113
4114 // Method Register
4115 operand inline_cache_regP(iRegP reg) %{
4116 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4117 match(reg);
4118 format %{ %}
4119 interface(REG_INTER);
4120 %}
4121
4122 operand interpreter_method_oop_regP(iRegP reg) %{
4123 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4124 match(reg);
4125 format %{ %}
4126 interface(REG_INTER);
4127 %}
4128
4129
4130 //----------Complex Operands---------------------------------------------------
4131 // Indirect Memory Reference
4132 operand indirect(sp_ptr_RegP reg) %{
4133 constraint(ALLOC_IN_RC(sp_ptr_reg));
4134 match(reg);
4135
4136 op_cost(100);
4137 format %{ "[$reg]" %}
4138 interface(MEMORY_INTER) %{
4139 base($reg);
4140 index(0x0);
4141 scale(0x0);
4142 disp(0x0);
4143 %}
4144 %}
4145
4146 // Indirect with simm13 Offset
4147 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4148 constraint(ALLOC_IN_RC(sp_ptr_reg));
4149 match(AddP reg offset);
4150
4151 op_cost(100);
4152 format %{ "[$reg + $offset]" %}
4153 interface(MEMORY_INTER) %{
4154 base($reg);
4155 index(0x0);
4156 scale(0x0);
4157 disp($offset);
4158 %}
4159 %}
4160
4161 // Indirect with simm13 Offset minus 7
4162 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4163 constraint(ALLOC_IN_RC(sp_ptr_reg));
4164 match(AddP reg offset);
4165
4166 op_cost(100);
4167 format %{ "[$reg + $offset]" %}
4168 interface(MEMORY_INTER) %{
4169 base($reg);
4170 index(0x0);
4171 scale(0x0);
4172 disp($offset);
4173 %}
4174 %}
4175
4176 // Note: Intel has a swapped version also, like this:
4177 //operand indOffsetX(iRegI reg, immP offset) %{
4178 // constraint(ALLOC_IN_RC(int_reg));
4179 // match(AddP offset reg);
4180 //
4181 // op_cost(100);
4182 // format %{ "[$reg + $offset]" %}
4183 // interface(MEMORY_INTER) %{
4184 // base($reg);
4185 // index(0x0);
4186 // scale(0x0);
4187 // disp($offset);
4188 // %}
4189 //%}
4190 //// However, it doesn't make sense for SPARC, since
4191 // we have no particularly good way to embed oops in
4192 // single instructions.
4193
4194 // Indirect with Register Index
4195 operand indIndex(iRegP addr, iRegX index) %{
4196 constraint(ALLOC_IN_RC(ptr_reg));
4197 match(AddP addr index);
4198
4199 op_cost(100);
4200 format %{ "[$addr + $index]" %}
4201 interface(MEMORY_INTER) %{
4202 base($addr);
4203 index($index);
4204 scale(0x0);
4205 disp(0x0);
4206 %}
4207 %}
4208
4209 //----------Special Memory Operands--------------------------------------------
4210 // Stack Slot Operand - This operand is used for loading and storing temporary
4211 // values on the stack where a match requires a value to
4212 // flow through memory.
4213 operand stackSlotI(sRegI reg) %{
4214 constraint(ALLOC_IN_RC(stack_slots));
4215 op_cost(100);
4216 //match(RegI);
4217 format %{ "[$reg]" %}
4218 interface(MEMORY_INTER) %{
4219 base(0xE); // R_SP
4220 index(0x0);
4221 scale(0x0);
4222 disp($reg); // Stack Offset
4223 %}
4224 %}
4225
4226 operand stackSlotP(sRegP reg) %{
4227 constraint(ALLOC_IN_RC(stack_slots));
4228 op_cost(100);
4229 //match(RegP);
4230 format %{ "[$reg]" %}
4231 interface(MEMORY_INTER) %{
4232 base(0xE); // R_SP
4233 index(0x0);
4234 scale(0x0);
4235 disp($reg); // Stack Offset
4236 %}
4237 %}
4238
4239 operand stackSlotF(sRegF reg) %{
4240 constraint(ALLOC_IN_RC(stack_slots));
4241 op_cost(100);
4242 //match(RegF);
4243 format %{ "[$reg]" %}
4244 interface(MEMORY_INTER) %{
4245 base(0xE); // R_SP
4246 index(0x0);
4247 scale(0x0);
4248 disp($reg); // Stack Offset
4249 %}
4250 %}
4251 operand stackSlotD(sRegD reg) %{
4252 constraint(ALLOC_IN_RC(stack_slots));
4253 op_cost(100);
4254 //match(RegD);
4255 format %{ "[$reg]" %}
4256 interface(MEMORY_INTER) %{
4257 base(0xE); // R_SP
4258 index(0x0);
4259 scale(0x0);
4260 disp($reg); // Stack Offset
4261 %}
4262 %}
4263 operand stackSlotL(sRegL reg) %{
4264 constraint(ALLOC_IN_RC(stack_slots));
4265 op_cost(100);
4266 //match(RegL);
4267 format %{ "[$reg]" %}
4268 interface(MEMORY_INTER) %{
4269 base(0xE); // R_SP
4270 index(0x0);
4271 scale(0x0);
4272 disp($reg); // Stack Offset
4273 %}
4274 %}
4275
4276 // Operands for expressing Control Flow
4277 // NOTE: Label is a predefined operand which should not be redefined in
4278 // the AD file. It is generically handled within the ADLC.
4279
4280 //----------Conditional Branch Operands----------------------------------------
4281 // Comparison Op - This is the operation of the comparison, and is limited to
4282 // the following set of codes:
4283 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4284 //
4285 // Other attributes of the comparison, such as unsignedness, are specified
4286 // by the comparison instruction that sets a condition code flags register.
4287 // That result is represented by a flags operand whose subtype is appropriate
4288 // to the unsignedness (etc.) of the comparison.
4289 //
4290 // Later, the instruction which matches both the Comparison Op (a Bool) and
4291 // the flags (produced by the Cmp) specifies the coding of the comparison op
4292 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4293
4294 operand cmpOp() %{
4295 match(Bool);
4296
4297 format %{ "" %}
4298 interface(COND_INTER) %{
4299 equal(0x1);
4300 not_equal(0x9);
4301 less(0x3);
4302 greater_equal(0xB);
4303 less_equal(0x2);
4304 greater(0xA);
4305 %}
4306 %}
4307
4308 // Comparison Op, unsigned
4309 operand cmpOpU() %{
4310 match(Bool);
4311
4312 format %{ "u" %}
4313 interface(COND_INTER) %{
4314 equal(0x1);
4315 not_equal(0x9);
4316 less(0x5);
4317 greater_equal(0xD);
4318 less_equal(0x4);
4319 greater(0xC);
4320 %}
4321 %}
4322
4323 // Comparison Op, pointer (same as unsigned)
4324 operand cmpOpP() %{
4325 match(Bool);
4326
4327 format %{ "p" %}
4328 interface(COND_INTER) %{
4329 equal(0x1);
4330 not_equal(0x9);
4331 less(0x5);
4332 greater_equal(0xD);
4333 less_equal(0x4);
4334 greater(0xC);
4335 %}
4336 %}
4337
4338 // Comparison Op, branch-register encoding
4339 operand cmpOp_reg() %{
4340 match(Bool);
4341
4342 format %{ "" %}
4343 interface(COND_INTER) %{
4344 equal (0x1);
4345 not_equal (0x5);
4346 less (0x3);
4347 greater_equal(0x7);
4348 less_equal (0x2);
4349 greater (0x6);
4350 %}
4351 %}
4352
4353 // Comparison Code, floating, unordered same as less
4354 operand cmpOpF() %{
4355 match(Bool);
4356
4357 format %{ "fl" %}
4358 interface(COND_INTER) %{
4359 equal(0x9);
4360 not_equal(0x1);
4361 less(0x3);
4362 greater_equal(0xB);
4363 less_equal(0xE);
4364 greater(0x6);
4365 %}
4366 %}
4367
4368 // Used by long compare
4369 operand cmpOp_commute() %{
4370 match(Bool);
4371
4372 format %{ "" %}
4373 interface(COND_INTER) %{
4374 equal(0x1);
4375 not_equal(0x9);
4376 less(0xA);
4377 greater_equal(0x2);
4378 less_equal(0xB);
4379 greater(0x3);
4380 %}
4381 %}
4382
4383 //----------OPERAND CLASSES----------------------------------------------------
4384 // Operand Classes are groups of operands that are used to simplify
4385 // instruction definitions by not requiring the AD writer to specify separate
4386 // instructions for every form of operand when the instruction accepts
4387 // multiple operand types with the same basic encoding and format. The classic
4388 // case of this is memory operands.
4389 opclass memory( indirect, indOffset13, indIndex );
4390 opclass indIndexMemory( indIndex );
4391
4392 //----------PIPELINE-----------------------------------------------------------
4393 pipeline %{
4394
4395 //----------ATTRIBUTES---------------------------------------------------------
4396 attributes %{
4397 fixed_size_instructions; // Fixed size instructions
4398 branch_has_delay_slot; // Branch has delay slot following
4399 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4400 instruction_unit_size = 4; // An instruction is 4 bytes long
4401 instruction_fetch_unit_size = 16; // The processor fetches one line
4402 instruction_fetch_units = 1; // of 16 bytes
4403
4404 // List of nop instructions
4405 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4406 %}
4407
4408 //----------RESOURCES----------------------------------------------------------
4409 // Resources are the functional units available to the machine
4410 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4411
4412 //----------PIPELINE DESCRIPTION-----------------------------------------------
4413 // Pipeline Description specifies the stages in the machine's pipeline
4414
4415 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4416
4417 //----------PIPELINE CLASSES---------------------------------------------------
4418 // Pipeline Classes describe the stages in which input and output are
4419 // referenced by the hardware pipeline.
4420
4421 // Integer ALU reg-reg operation
4422 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4423 single_instruction;
4424 dst : E(write);
4425 src1 : R(read);
4426 src2 : R(read);
4427 IALU : R;
4428 %}
4429
4430 // Integer ALU reg-reg long operation
4431 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4432 instruction_count(2);
4433 dst : E(write);
4434 src1 : R(read);
4435 src2 : R(read);
4436 IALU : R;
4437 IALU : R;
4438 %}
4439
4440 // Integer ALU reg-reg long dependent operation
4441 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4442 instruction_count(1); multiple_bundles;
4443 dst : E(write);
4444 src1 : R(read);
4445 src2 : R(read);
4446 cr : E(write);
4447 IALU : R(2);
4448 %}
4449
4450 // Integer ALU reg-imm operaion
4451 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4452 single_instruction;
4453 dst : E(write);
4454 src1 : R(read);
4455 IALU : R;
4456 %}
4457
4458 // Integer ALU reg-reg operation with condition code
4459 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4460 single_instruction;
4461 dst : E(write);
4462 cr : E(write);
4463 src1 : R(read);
4464 src2 : R(read);
4465 IALU : R;
4466 %}
4467
4468 // Integer ALU reg-imm operation with condition code
4469 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4470 single_instruction;
4471 dst : E(write);
4472 cr : E(write);
4473 src1 : R(read);
4474 IALU : R;
4475 %}
4476
4477 // Integer ALU zero-reg operation
4478 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4479 single_instruction;
4480 dst : E(write);
4481 src2 : R(read);
4482 IALU : R;
4483 %}
4484
4485 // Integer ALU zero-reg operation with condition code only
4486 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4487 single_instruction;
4488 cr : E(write);
4489 src : R(read);
4490 IALU : R;
4491 %}
4492
4493 // Integer ALU reg-reg operation with condition code only
4494 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4495 single_instruction;
4496 cr : E(write);
4497 src1 : R(read);
4498 src2 : R(read);
4499 IALU : R;
4500 %}
4501
4502 // Integer ALU reg-imm operation with condition code only
4503 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4504 single_instruction;
4505 cr : E(write);
4506 src1 : R(read);
4507 IALU : R;
4508 %}
4509
4510 // Integer ALU reg-reg-zero operation with condition code only
4511 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4512 single_instruction;
4513 cr : E(write);
4514 src1 : R(read);
4515 src2 : R(read);
4516 IALU : R;
4517 %}
4518
4519 // Integer ALU reg-imm-zero operation with condition code only
4520 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4521 single_instruction;
4522 cr : E(write);
4523 src1 : R(read);
4524 IALU : R;
4525 %}
4526
4527 // Integer ALU reg-reg operation with condition code, src1 modified
4528 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4529 single_instruction;
4530 cr : E(write);
4531 src1 : E(write);
4532 src1 : R(read);
4533 src2 : R(read);
4534 IALU : R;
4535 %}
4536
4537 // Integer ALU reg-imm operation with condition code, src1 modified
4538 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4539 single_instruction;
4540 cr : E(write);
4541 src1 : E(write);
4542 src1 : R(read);
4543 IALU : R;
4544 %}
4545
4546 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4547 multiple_bundles;
4548 dst : E(write)+4;
4549 cr : E(write);
4550 src1 : R(read);
4551 src2 : R(read);
4552 IALU : R(3);
4553 BR : R(2);
4554 %}
4555
4556 // Integer ALU operation
4557 pipe_class ialu_none(iRegI dst) %{
4558 single_instruction;
4559 dst : E(write);
4560 IALU : R;
4561 %}
4562
4563 // Integer ALU reg operation
4564 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4565 single_instruction; may_have_no_code;
4566 dst : E(write);
4567 src : R(read);
4568 IALU : R;
4569 %}
4570
4571 // Integer ALU reg conditional operation
4572 // This instruction has a 1 cycle stall, and cannot execute
4573 // in the same cycle as the instruction setting the condition
4574 // code. We kludge this by pretending to read the condition code
4575 // 1 cycle earlier, and by marking the functional units as busy
4576 // for 2 cycles with the result available 1 cycle later than
4577 // is really the case.
4578 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4579 single_instruction;
4580 op2_out : C(write);
4581 op1 : R(read);
4582 cr : R(read); // This is really E, with a 1 cycle stall
4583 BR : R(2);
4584 MS : R(2);
4585 %}
4586
4587 #ifdef _LP64
4588 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4589 instruction_count(1); multiple_bundles;
4590 dst : C(write)+1;
4591 src : R(read)+1;
4592 IALU : R(1);
4593 BR : E(2);
4594 MS : E(2);
4595 %}
4596 #endif
4597
4598 // Integer ALU reg operation
4599 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4600 single_instruction; may_have_no_code;
4601 dst : E(write);
4602 src : R(read);
4603 IALU : R;
4604 %}
4605 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4606 single_instruction; may_have_no_code;
4607 dst : E(write);
4608 src : R(read);
4609 IALU : R;
4610 %}
4611
4612 // Two integer ALU reg operations
4613 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4614 instruction_count(2);
4615 dst : E(write);
4616 src : R(read);
4617 A0 : R;
4618 A1 : R;
4619 %}
4620
4621 // Two integer ALU reg operations
4622 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4623 instruction_count(2); may_have_no_code;
4624 dst : E(write);
4625 src : R(read);
4626 A0 : R;
4627 A1 : R;
4628 %}
4629
4630 // Integer ALU imm operation
4631 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4632 single_instruction;
4633 dst : E(write);
4634 IALU : R;
4635 %}
4636
4637 // Integer ALU reg-reg with carry operation
4638 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4639 single_instruction;
4640 dst : E(write);
4641 src1 : R(read);
4642 src2 : R(read);
4643 IALU : R;
4644 %}
4645
4646 // Integer ALU cc operation
4647 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4648 single_instruction;
4649 dst : E(write);
4650 cc : R(read);
4651 IALU : R;
4652 %}
4653
4654 // Integer ALU cc / second IALU operation
4655 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4656 instruction_count(1); multiple_bundles;
4657 dst : E(write)+1;
4658 src : R(read);
4659 IALU : R;
4660 %}
4661
4662 // Integer ALU cc / second IALU operation
4663 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4664 instruction_count(1); multiple_bundles;
4665 dst : E(write)+1;
4666 p : R(read);
4667 q : R(read);
4668 IALU : R;
4669 %}
4670
4671 // Integer ALU hi-lo-reg operation
4672 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4673 instruction_count(1); multiple_bundles;
4674 dst : E(write)+1;
4675 IALU : R(2);
4676 %}
4677
4678 // Float ALU hi-lo-reg operation (with temp)
4679 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4680 instruction_count(1); multiple_bundles;
4681 dst : E(write)+1;
4682 IALU : R(2);
4683 %}
4684
4685 // Long Constant
4686 pipe_class loadConL( iRegL dst, immL src ) %{
4687 instruction_count(2); multiple_bundles;
4688 dst : E(write)+1;
4689 IALU : R(2);
4690 IALU : R(2);
4691 %}
4692
4693 // Pointer Constant
4694 pipe_class loadConP( iRegP dst, immP src ) %{
4695 instruction_count(0); multiple_bundles;
4696 fixed_latency(6);
4697 %}
4698
4699 // Polling Address
4700 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4701 #ifdef _LP64
4702 instruction_count(0); multiple_bundles;
4703 fixed_latency(6);
4704 #else
4705 dst : E(write);
4706 IALU : R;
4707 #endif
4708 %}
4709
4710 // Long Constant small
4711 pipe_class loadConLlo( iRegL dst, immL src ) %{
4712 instruction_count(2);
4713 dst : E(write);
4714 IALU : R;
4715 IALU : R;
4716 %}
4717
4718 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4719 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4720 instruction_count(1); multiple_bundles;
4721 src : R(read);
4722 dst : M(write)+1;
4723 IALU : R;
4724 MS : E;
4725 %}
4726
4727 // Integer ALU nop operation
4728 pipe_class ialu_nop() %{
4729 single_instruction;
4730 IALU : R;
4731 %}
4732
4733 // Integer ALU nop operation
4734 pipe_class ialu_nop_A0() %{
4735 single_instruction;
4736 A0 : R;
4737 %}
4738
4739 // Integer ALU nop operation
4740 pipe_class ialu_nop_A1() %{
4741 single_instruction;
4742 A1 : R;
4743 %}
4744
4745 // Integer Multiply reg-reg operation
4746 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4747 single_instruction;
4748 dst : E(write);
4749 src1 : R(read);
4750 src2 : R(read);
4751 MS : R(5);
4752 %}
4753
4754 // Integer Multiply reg-imm operation
4755 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4756 single_instruction;
4757 dst : E(write);
4758 src1 : R(read);
4759 MS : R(5);
4760 %}
4761
4762 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4763 single_instruction;
4764 dst : E(write)+4;
4765 src1 : R(read);
4766 src2 : R(read);
4767 MS : R(6);
4768 %}
4769
4770 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4771 single_instruction;
4772 dst : E(write)+4;
4773 src1 : R(read);
4774 MS : R(6);
4775 %}
4776
4777 // Integer Divide reg-reg
4778 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4779 instruction_count(1); multiple_bundles;
4780 dst : E(write);
4781 temp : E(write);
4782 src1 : R(read);
4783 src2 : R(read);
4784 temp : R(read);
4785 MS : R(38);
4786 %}
4787
4788 // Integer Divide reg-imm
4789 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4790 instruction_count(1); multiple_bundles;
4791 dst : E(write);
4792 temp : E(write);
4793 src1 : R(read);
4794 temp : R(read);
4795 MS : R(38);
4796 %}
4797
4798 // Long Divide
4799 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4800 dst : E(write)+71;
4801 src1 : R(read);
4802 src2 : R(read)+1;
4803 MS : R(70);
4804 %}
4805
4806 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4807 dst : E(write)+71;
4808 src1 : R(read);
4809 MS : R(70);
4810 %}
4811
4812 // Floating Point Add Float
4813 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4814 single_instruction;
4815 dst : X(write);
4816 src1 : E(read);
4817 src2 : E(read);
4818 FA : R;
4819 %}
4820
4821 // Floating Point Add Double
4822 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4823 single_instruction;
4824 dst : X(write);
4825 src1 : E(read);
4826 src2 : E(read);
4827 FA : R;
4828 %}
4829
4830 // Floating Point Conditional Move based on integer flags
4831 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4832 single_instruction;
4833 dst : X(write);
4834 src : E(read);
4835 cr : R(read);
4836 FA : R(2);
4837 BR : R(2);
4838 %}
4839
4840 // Floating Point Conditional Move based on integer flags
4841 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4842 single_instruction;
4843 dst : X(write);
4844 src : E(read);
4845 cr : R(read);
4846 FA : R(2);
4847 BR : R(2);
4848 %}
4849
4850 // Floating Point Multiply Float
4851 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4852 single_instruction;
4853 dst : X(write);
4854 src1 : E(read);
4855 src2 : E(read);
4856 FM : R;
4857 %}
4858
4859 // Floating Point Multiply Double
4860 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4861 single_instruction;
4862 dst : X(write);
4863 src1 : E(read);
4864 src2 : E(read);
4865 FM : R;
4866 %}
4867
4868 // Floating Point Divide Float
4869 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4870 single_instruction;
4871 dst : X(write);
4872 src1 : E(read);
4873 src2 : E(read);
4874 FM : R;
4875 FDIV : C(14);
4876 %}
4877
4878 // Floating Point Divide Double
4879 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4880 single_instruction;
4881 dst : X(write);
4882 src1 : E(read);
4883 src2 : E(read);
4884 FM : R;
4885 FDIV : C(17);
4886 %}
4887
4888 // Floating Point Move/Negate/Abs Float
4889 pipe_class faddF_reg(regF dst, regF src) %{
4890 single_instruction;
4891 dst : W(write);
4892 src : E(read);
4893 FA : R(1);
4894 %}
4895
4896 // Floating Point Move/Negate/Abs Double
4897 pipe_class faddD_reg(regD dst, regD src) %{
4898 single_instruction;
4899 dst : W(write);
4900 src : E(read);
4901 FA : R;
4902 %}
4903
4904 // Floating Point Convert F->D
4905 pipe_class fcvtF2D(regD dst, regF src) %{
4906 single_instruction;
4907 dst : X(write);
4908 src : E(read);
4909 FA : R;
4910 %}
4911
4912 // Floating Point Convert I->D
4913 pipe_class fcvtI2D(regD dst, regF src) %{
4914 single_instruction;
4915 dst : X(write);
4916 src : E(read);
4917 FA : R;
4918 %}
4919
4920 // Floating Point Convert LHi->D
4921 pipe_class fcvtLHi2D(regD dst, regD src) %{
4922 single_instruction;
4923 dst : X(write);
4924 src : E(read);
4925 FA : R;
4926 %}
4927
4928 // Floating Point Convert L->D
4929 pipe_class fcvtL2D(regD dst, regF src) %{
4930 single_instruction;
4931 dst : X(write);
4932 src : E(read);
4933 FA : R;
4934 %}
4935
4936 // Floating Point Convert L->F
4937 pipe_class fcvtL2F(regD dst, regF src) %{
4938 single_instruction;
4939 dst : X(write);
4940 src : E(read);
4941 FA : R;
4942 %}
4943
4944 // Floating Point Convert D->F
4945 pipe_class fcvtD2F(regD dst, regF src) %{
4946 single_instruction;
4947 dst : X(write);
4948 src : E(read);
4949 FA : R;
4950 %}
4951
4952 // Floating Point Convert I->L
4953 pipe_class fcvtI2L(regD dst, regF src) %{
4954 single_instruction;
4955 dst : X(write);
4956 src : E(read);
4957 FA : R;
4958 %}
4959
4960 // Floating Point Convert D->F
4961 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4962 instruction_count(1); multiple_bundles;
4963 dst : X(write)+6;
4964 src : E(read);
4965 FA : R;
4966 %}
4967
4968 // Floating Point Convert D->L
4969 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4970 instruction_count(1); multiple_bundles;
4971 dst : X(write)+6;
4972 src : E(read);
4973 FA : R;
4974 %}
4975
4976 // Floating Point Convert F->I
4977 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4978 instruction_count(1); multiple_bundles;
4979 dst : X(write)+6;
4980 src : E(read);
4981 FA : R;
4982 %}
4983
4984 // Floating Point Convert F->L
4985 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4986 instruction_count(1); multiple_bundles;
4987 dst : X(write)+6;
4988 src : E(read);
4989 FA : R;
4990 %}
4991
4992 // Floating Point Convert I->F
4993 pipe_class fcvtI2F(regF dst, regF src) %{
4994 single_instruction;
4995 dst : X(write);
4996 src : E(read);
4997 FA : R;
4998 %}
4999
5000 // Floating Point Compare
5001 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5002 single_instruction;
5003 cr : X(write);
5004 src1 : E(read);
5005 src2 : E(read);
5006 FA : R;
5007 %}
5008
5009 // Floating Point Compare
5010 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5011 single_instruction;
5012 cr : X(write);
5013 src1 : E(read);
5014 src2 : E(read);
5015 FA : R;
5016 %}
5017
5018 // Floating Add Nop
5019 pipe_class fadd_nop() %{
5020 single_instruction;
5021 FA : R;
5022 %}
5023
5024 // Integer Store to Memory
5025 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5026 single_instruction;
5027 mem : R(read);
5028 src : C(read);
5029 MS : R;
5030 %}
5031
5032 // Integer Store to Memory
5033 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5034 single_instruction;
5035 mem : R(read);
5036 src : C(read);
5037 MS : R;
5038 %}
5039
5040 // Integer Store Zero to Memory
5041 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5042 single_instruction;
5043 mem : R(read);
5044 MS : R;
5045 %}
5046
5047 // Special Stack Slot Store
5048 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5049 single_instruction;
5050 stkSlot : R(read);
5051 src : C(read);
5052 MS : R;
5053 %}
5054
5055 // Special Stack Slot Store
5056 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5057 instruction_count(2); multiple_bundles;
5058 stkSlot : R(read);
5059 src : C(read);
5060 MS : R(2);
5061 %}
5062
5063 // Float Store
5064 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5065 single_instruction;
5066 mem : R(read);
5067 src : C(read);
5068 MS : R;
5069 %}
5070
5071 // Float Store
5072 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5073 single_instruction;
5074 mem : R(read);
5075 MS : R;
5076 %}
5077
5078 // Double Store
5079 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5080 instruction_count(1);
5081 mem : R(read);
5082 src : C(read);
5083 MS : R;
5084 %}
5085
5086 // Double Store
5087 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5088 single_instruction;
5089 mem : R(read);
5090 MS : R;
5091 %}
5092
5093 // Special Stack Slot Float Store
5094 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5095 single_instruction;
5096 stkSlot : R(read);
5097 src : C(read);
5098 MS : R;
5099 %}
5100
5101 // Special Stack Slot Double Store
5102 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5103 single_instruction;
5104 stkSlot : R(read);
5105 src : C(read);
5106 MS : R;
5107 %}
5108
5109 // Integer Load (when sign bit propagation not needed)
5110 pipe_class iload_mem(iRegI dst, memory mem) %{
5111 single_instruction;
5112 mem : R(read);
5113 dst : C(write);
5114 MS : R;
5115 %}
5116
5117 // Integer Load from stack operand
5118 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5119 single_instruction;
5120 mem : R(read);
5121 dst : C(write);
5122 MS : R;
5123 %}
5124
5125 // Integer Load (when sign bit propagation or masking is needed)
5126 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5127 single_instruction;
5128 mem : R(read);
5129 dst : M(write);
5130 MS : R;
5131 %}
5132
5133 // Float Load
5134 pipe_class floadF_mem(regF dst, memory mem) %{
5135 single_instruction;
5136 mem : R(read);
5137 dst : M(write);
5138 MS : R;
5139 %}
5140
5141 // Float Load
5142 pipe_class floadD_mem(regD dst, memory mem) %{
5143 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5144 mem : R(read);
5145 dst : M(write);
5146 MS : R;
5147 %}
5148
5149 // Float Load
5150 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5151 single_instruction;
5152 stkSlot : R(read);
5153 dst : M(write);
5154 MS : R;
5155 %}
5156
5157 // Float Load
5158 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5159 single_instruction;
5160 stkSlot : R(read);
5161 dst : M(write);
5162 MS : R;
5163 %}
5164
5165 // Memory Nop
5166 pipe_class mem_nop() %{
5167 single_instruction;
5168 MS : R;
5169 %}
5170
5171 pipe_class sethi(iRegP dst, immI src) %{
5172 single_instruction;
5173 dst : E(write);
5174 IALU : R;
5175 %}
5176
5177 pipe_class loadPollP(iRegP poll) %{
5178 single_instruction;
5179 poll : R(read);
5180 MS : R;
5181 %}
5182
5183 pipe_class br(Universe br, label labl) %{
5184 single_instruction_with_delay_slot;
5185 BR : R;
5186 %}
5187
5188 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5189 single_instruction_with_delay_slot;
5190 cr : E(read);
5191 BR : R;
5192 %}
5193
5194 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5195 single_instruction_with_delay_slot;
5196 op1 : E(read);
5197 BR : R;
5198 MS : R;
5199 %}
5200
5201 // Compare and branch
5202 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5203 instruction_count(2); has_delay_slot;
5204 cr : E(write);
5205 src1 : R(read);
5206 src2 : R(read);
5207 IALU : R;
5208 BR : R;
5209 %}
5210
5211 // Compare and branch
5212 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5213 instruction_count(2); has_delay_slot;
5214 cr : E(write);
5215 src1 : R(read);
5216 IALU : R;
5217 BR : R;
5218 %}
5219
5220 // Compare and branch using cbcond
5221 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5222 single_instruction;
5223 src1 : E(read);
5224 src2 : E(read);
5225 IALU : R;
5226 BR : R;
5227 %}
5228
5229 // Compare and branch using cbcond
5230 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5231 single_instruction;
5232 src1 : E(read);
5233 IALU : R;
5234 BR : R;
5235 %}
5236
5237 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5238 single_instruction_with_delay_slot;
5239 cr : E(read);
5240 BR : R;
5241 %}
5242
5243 pipe_class br_nop() %{
5244 single_instruction;
5245 BR : R;
5246 %}
5247
5248 pipe_class simple_call(method meth) %{
5249 instruction_count(2); multiple_bundles; force_serialization;
5250 fixed_latency(100);
5251 BR : R(1);
5252 MS : R(1);
5253 A0 : R(1);
5254 %}
5255
5256 pipe_class compiled_call(method meth) %{
5257 instruction_count(1); multiple_bundles; force_serialization;
5258 fixed_latency(100);
5259 MS : R(1);
5260 %}
5261
5262 pipe_class call(method meth) %{
5263 instruction_count(0); multiple_bundles; force_serialization;
5264 fixed_latency(100);
5265 %}
5266
5267 pipe_class tail_call(Universe ignore, label labl) %{
5268 single_instruction; has_delay_slot;
5269 fixed_latency(100);
5270 BR : R(1);
5271 MS : R(1);
5272 %}
5273
5274 pipe_class ret(Universe ignore) %{
5275 single_instruction; has_delay_slot;
5276 BR : R(1);
5277 MS : R(1);
5278 %}
5279
5280 pipe_class ret_poll(g3RegP poll) %{
5281 instruction_count(3); has_delay_slot;
5282 poll : E(read);
5283 MS : R;
5284 %}
5285
5286 // The real do-nothing guy
5287 pipe_class empty( ) %{
5288 instruction_count(0);
5289 %}
5290
5291 pipe_class long_memory_op() %{
5292 instruction_count(0); multiple_bundles; force_serialization;
5293 fixed_latency(25);
5294 MS : R(1);
5295 %}
5296
5297 // Check-cast
5298 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5299 array : R(read);
5300 match : R(read);
5301 IALU : R(2);
5302 BR : R(2);
5303 MS : R;
5304 %}
5305
5306 // Convert FPU flags into +1,0,-1
5307 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5308 src1 : E(read);
5309 src2 : E(read);
5310 dst : E(write);
5311 FA : R;
5312 MS : R(2);
5313 BR : R(2);
5314 %}
5315
5316 // Compare for p < q, and conditionally add y
5317 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5318 p : E(read);
5319 q : E(read);
5320 y : E(read);
5321 IALU : R(3)
5322 %}
5323
5324 // Perform a compare, then move conditionally in a branch delay slot.
5325 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5326 src2 : E(read);
5327 srcdst : E(read);
5328 IALU : R;
5329 BR : R;
5330 %}
5331
5332 // Define the class for the Nop node
5333 define %{
5334 MachNop = ialu_nop;
5335 %}
5336
5337 %}
5338
5339 //----------INSTRUCTIONS-------------------------------------------------------
5340
5341 //------------Special Stack Slot instructions - no match rules-----------------
5342 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5343 // No match rule to avoid chain rule match.
5344 effect(DEF dst, USE src);
5345 ins_cost(MEMORY_REF_COST);
5346 size(4);
5347 format %{ "LDF $src,$dst\t! stkI to regF" %}
5348 opcode(Assembler::ldf_op3);
5349 ins_encode(simple_form3_mem_reg(src, dst));
5350 ins_pipe(floadF_stk);
5351 %}
5352
5353 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5354 // No match rule to avoid chain rule match.
5355 effect(DEF dst, USE src);
5356 ins_cost(MEMORY_REF_COST);
5357 size(4);
5358 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5359 opcode(Assembler::lddf_op3);
5360 ins_encode(simple_form3_mem_reg(src, dst));
5361 ins_pipe(floadD_stk);
5362 %}
5363
5364 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5365 // No match rule to avoid chain rule match.
5366 effect(DEF dst, USE src);
5367 ins_cost(MEMORY_REF_COST);
5368 size(4);
5369 format %{ "STF $src,$dst\t! regF to stkI" %}
5370 opcode(Assembler::stf_op3);
5371 ins_encode(simple_form3_mem_reg(dst, src));
5372 ins_pipe(fstoreF_stk_reg);
5373 %}
5374
5375 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5376 // No match rule to avoid chain rule match.
5377 effect(DEF dst, USE src);
5378 ins_cost(MEMORY_REF_COST);
5379 size(4);
5380 format %{ "STDF $src,$dst\t! regD to stkL" %}
5381 opcode(Assembler::stdf_op3);
5382 ins_encode(simple_form3_mem_reg(dst, src));
5383 ins_pipe(fstoreD_stk_reg);
5384 %}
5385
5386 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5387 effect(DEF dst, USE src);
5388 ins_cost(MEMORY_REF_COST*2);
5389 size(8);
5390 format %{ "STW $src,$dst.hi\t! long\n\t"
5391 "STW R_G0,$dst.lo" %}
5392 opcode(Assembler::stw_op3);
5393 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5394 ins_pipe(lstoreI_stk_reg);
5395 %}
5396
5397 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5398 // No match rule to avoid chain rule match.
5399 effect(DEF dst, USE src);
5400 ins_cost(MEMORY_REF_COST);
5401 size(4);
5402 format %{ "STX $src,$dst\t! regL to stkD" %}
5403 opcode(Assembler::stx_op3);
5404 ins_encode(simple_form3_mem_reg( dst, src ) );
5405 ins_pipe(istore_stk_reg);
5406 %}
5407
5408 //---------- Chain stack slots between similar types --------
5409
5410 // Load integer from stack slot
5411 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5412 match(Set dst src);
5413 ins_cost(MEMORY_REF_COST);
5414
5415 size(4);
5416 format %{ "LDUW $src,$dst\t!stk" %}
5417 opcode(Assembler::lduw_op3);
5418 ins_encode(simple_form3_mem_reg( src, dst ) );
5419 ins_pipe(iload_mem);
5420 %}
5421
5422 // Store integer to stack slot
5423 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5424 match(Set dst src);
5425 ins_cost(MEMORY_REF_COST);
5426
5427 size(4);
5428 format %{ "STW $src,$dst\t!stk" %}
5429 opcode(Assembler::stw_op3);
5430 ins_encode(simple_form3_mem_reg( dst, src ) );
5431 ins_pipe(istore_mem_reg);
5432 %}
5433
5434 // Load long from stack slot
5435 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5436 match(Set dst src);
5437
5438 ins_cost(MEMORY_REF_COST);
5439 size(4);
5440 format %{ "LDX $src,$dst\t! long" %}
5441 opcode(Assembler::ldx_op3);
5442 ins_encode(simple_form3_mem_reg( src, dst ) );
5443 ins_pipe(iload_mem);
5444 %}
5445
5446 // Store long to stack slot
5447 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5448 match(Set dst src);
5449
5450 ins_cost(MEMORY_REF_COST);
5451 size(4);
5452 format %{ "STX $src,$dst\t! long" %}
5453 opcode(Assembler::stx_op3);
5454 ins_encode(simple_form3_mem_reg( dst, src ) );
5455 ins_pipe(istore_mem_reg);
5456 %}
5457
5458 #ifdef _LP64
5459 // Load pointer from stack slot, 64-bit encoding
5460 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5461 match(Set dst src);
5462 ins_cost(MEMORY_REF_COST);
5463 size(4);
5464 format %{ "LDX $src,$dst\t!ptr" %}
5465 opcode(Assembler::ldx_op3);
5466 ins_encode(simple_form3_mem_reg( src, dst ) );
5467 ins_pipe(iload_mem);
5468 %}
5469
5470 // Store pointer to stack slot
5471 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5472 match(Set dst src);
5473 ins_cost(MEMORY_REF_COST);
5474 size(4);
5475 format %{ "STX $src,$dst\t!ptr" %}
5476 opcode(Assembler::stx_op3);
5477 ins_encode(simple_form3_mem_reg( dst, src ) );
5478 ins_pipe(istore_mem_reg);
5479 %}
5480 #else // _LP64
5481 // Load pointer from stack slot, 32-bit encoding
5482 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5483 match(Set dst src);
5484 ins_cost(MEMORY_REF_COST);
5485 format %{ "LDUW $src,$dst\t!ptr" %}
5486 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5487 ins_encode(simple_form3_mem_reg( src, dst ) );
5488 ins_pipe(iload_mem);
5489 %}
5490
5491 // Store pointer to stack slot
5492 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5493 match(Set dst src);
5494 ins_cost(MEMORY_REF_COST);
5495 format %{ "STW $src,$dst\t!ptr" %}
5496 opcode(Assembler::stw_op3, Assembler::ldst_op);
5497 ins_encode(simple_form3_mem_reg( dst, src ) );
5498 ins_pipe(istore_mem_reg);
5499 %}
5500 #endif // _LP64
5501
5502 //------------Special Nop instructions for bundling - no match rules-----------
5503 // Nop using the A0 functional unit
5504 instruct Nop_A0() %{
5505 ins_cost(0);
5506
5507 format %{ "NOP ! Alu Pipeline" %}
5508 opcode(Assembler::or_op3, Assembler::arith_op);
5509 ins_encode( form2_nop() );
5510 ins_pipe(ialu_nop_A0);
5511 %}
5512
5513 // Nop using the A1 functional unit
5514 instruct Nop_A1( ) %{
5515 ins_cost(0);
5516
5517 format %{ "NOP ! Alu Pipeline" %}
5518 opcode(Assembler::or_op3, Assembler::arith_op);
5519 ins_encode( form2_nop() );
5520 ins_pipe(ialu_nop_A1);
5521 %}
5522
5523 // Nop using the memory functional unit
5524 instruct Nop_MS( ) %{
5525 ins_cost(0);
5526
5527 format %{ "NOP ! Memory Pipeline" %}
5528 ins_encode( emit_mem_nop );
5529 ins_pipe(mem_nop);
5530 %}
5531
5532 // Nop using the floating add functional unit
5533 instruct Nop_FA( ) %{
5534 ins_cost(0);
5535
5536 format %{ "NOP ! Floating Add Pipeline" %}
5537 ins_encode( emit_fadd_nop );
5538 ins_pipe(fadd_nop);
5539 %}
5540
5541 // Nop using the branch functional unit
5542 instruct Nop_BR( ) %{
5543 ins_cost(0);
5544
5545 format %{ "NOP ! Branch Pipeline" %}
5546 ins_encode( emit_br_nop );
5547 ins_pipe(br_nop);
5548 %}
5549
5550 //----------Load/Store/Move Instructions---------------------------------------
5551 //----------Load Instructions--------------------------------------------------
5552 // Load Byte (8bit signed)
5553 instruct loadB(iRegI dst, memory mem) %{
5554 match(Set dst (LoadB mem));
5555 ins_cost(MEMORY_REF_COST);
5556
5557 size(4);
5558 format %{ "LDSB $mem,$dst\t! byte" %}
5559 ins_encode %{
5560 __ ldsb($mem$$Address, $dst$$Register);
5561 %}
5562 ins_pipe(iload_mask_mem);
5563 %}
5564
5565 // Load Byte (8bit signed) into a Long Register
5566 instruct loadB2L(iRegL dst, memory mem) %{
5567 match(Set dst (ConvI2L (LoadB mem)));
5568 ins_cost(MEMORY_REF_COST);
5569
5570 size(4);
5571 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5572 ins_encode %{
5573 __ ldsb($mem$$Address, $dst$$Register);
5574 %}
5575 ins_pipe(iload_mask_mem);
5576 %}
5577
5578 // Load Unsigned Byte (8bit UNsigned) into an int reg
5579 instruct loadUB(iRegI dst, memory mem) %{
5580 match(Set dst (LoadUB mem));
5581 ins_cost(MEMORY_REF_COST);
5582
5583 size(4);
5584 format %{ "LDUB $mem,$dst\t! ubyte" %}
5585 ins_encode %{
5586 __ ldub($mem$$Address, $dst$$Register);
5587 %}
5588 ins_pipe(iload_mem);
5589 %}
5590
5591 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5592 instruct loadUB2L(iRegL dst, memory mem) %{
5593 match(Set dst (ConvI2L (LoadUB mem)));
5594 ins_cost(MEMORY_REF_COST);
5595
5596 size(4);
5597 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5598 ins_encode %{
5599 __ ldub($mem$$Address, $dst$$Register);
5600 %}
5601 ins_pipe(iload_mem);
5602 %}
5603
5604 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5605 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5606 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5607 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5608
5609 size(2*4);
5610 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5611 "AND $dst,$mask,$dst" %}
5612 ins_encode %{
5613 __ ldub($mem$$Address, $dst$$Register);
5614 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5615 %}
5616 ins_pipe(iload_mem);
5617 %}
5618
5619 // Load Short (16bit signed)
5620 instruct loadS(iRegI dst, memory mem) %{
5621 match(Set dst (LoadS mem));
5622 ins_cost(MEMORY_REF_COST);
5623
5624 size(4);
5625 format %{ "LDSH $mem,$dst\t! short" %}
5626 ins_encode %{
5627 __ ldsh($mem$$Address, $dst$$Register);
5628 %}
5629 ins_pipe(iload_mask_mem);
5630 %}
5631
5632 // Load Short (16 bit signed) to Byte (8 bit signed)
5633 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5634 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5635 ins_cost(MEMORY_REF_COST);
5636
5637 size(4);
5638
5639 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5640 ins_encode %{
5641 __ ldsb($mem$$Address, $dst$$Register, 1);
5642 %}
5643 ins_pipe(iload_mask_mem);
5644 %}
5645
5646 // Load Short (16bit signed) into a Long Register
5647 instruct loadS2L(iRegL dst, memory mem) %{
5648 match(Set dst (ConvI2L (LoadS mem)));
5649 ins_cost(MEMORY_REF_COST);
5650
5651 size(4);
5652 format %{ "LDSH $mem,$dst\t! short -> long" %}
5653 ins_encode %{
5654 __ ldsh($mem$$Address, $dst$$Register);
5655 %}
5656 ins_pipe(iload_mask_mem);
5657 %}
5658
5659 // Load Unsigned Short/Char (16bit UNsigned)
5660 instruct loadUS(iRegI dst, memory mem) %{
5661 match(Set dst (LoadUS mem));
5662 ins_cost(MEMORY_REF_COST);
5663
5664 size(4);
5665 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5666 ins_encode %{
5667 __ lduh($mem$$Address, $dst$$Register);
5668 %}
5669 ins_pipe(iload_mem);
5670 %}
5671
5672 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5673 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5674 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5675 ins_cost(MEMORY_REF_COST);
5676
5677 size(4);
5678 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5679 ins_encode %{
5680 __ ldsb($mem$$Address, $dst$$Register, 1);
5681 %}
5682 ins_pipe(iload_mask_mem);
5683 %}
5684
5685 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5686 instruct loadUS2L(iRegL dst, memory mem) %{
5687 match(Set dst (ConvI2L (LoadUS mem)));
5688 ins_cost(MEMORY_REF_COST);
5689
5690 size(4);
5691 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5692 ins_encode %{
5693 __ lduh($mem$$Address, $dst$$Register);
5694 %}
5695 ins_pipe(iload_mem);
5696 %}
5697
5698 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5699 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5700 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5701 ins_cost(MEMORY_REF_COST);
5702
5703 size(4);
5704 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5705 ins_encode %{
5706 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5707 %}
5708 ins_pipe(iload_mem);
5709 %}
5710
5711 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5712 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5713 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5714 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5715
5716 size(2*4);
5717 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5718 "AND $dst,$mask,$dst" %}
5719 ins_encode %{
5720 Register Rdst = $dst$$Register;
5721 __ lduh($mem$$Address, Rdst);
5722 __ and3(Rdst, $mask$$constant, Rdst);
5723 %}
5724 ins_pipe(iload_mem);
5725 %}
5726
5727 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5728 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5729 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5730 effect(TEMP dst, TEMP tmp);
5731 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5732
5733 size((3+1)*4); // set may use two instructions.
5734 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5735 "SET $mask,$tmp\n\t"
5736 "AND $dst,$tmp,$dst" %}
5737 ins_encode %{
5738 Register Rdst = $dst$$Register;
5739 Register Rtmp = $tmp$$Register;
5740 __ lduh($mem$$Address, Rdst);
5741 __ set($mask$$constant, Rtmp);
5742 __ and3(Rdst, Rtmp, Rdst);
5743 %}
5744 ins_pipe(iload_mem);
5745 %}
5746
5747 // Load Integer
5748 instruct loadI(iRegI dst, memory mem) %{
5749 match(Set dst (LoadI mem));
5750 ins_cost(MEMORY_REF_COST);
5751
5752 size(4);
5753 format %{ "LDUW $mem,$dst\t! int" %}
5754 ins_encode %{
5755 __ lduw($mem$$Address, $dst$$Register);
5756 %}
5757 ins_pipe(iload_mem);
5758 %}
5759
5760 // Load Integer to Byte (8 bit signed)
5761 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5762 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5763 ins_cost(MEMORY_REF_COST);
5764
5765 size(4);
5766
5767 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5768 ins_encode %{
5769 __ ldsb($mem$$Address, $dst$$Register, 3);
5770 %}
5771 ins_pipe(iload_mask_mem);
5772 %}
5773
5774 // Load Integer to Unsigned Byte (8 bit UNsigned)
5775 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5776 match(Set dst (AndI (LoadI mem) mask));
5777 ins_cost(MEMORY_REF_COST);
5778
5779 size(4);
5780
5781 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5782 ins_encode %{
5783 __ ldub($mem$$Address, $dst$$Register, 3);
5784 %}
5785 ins_pipe(iload_mask_mem);
5786 %}
5787
5788 // Load Integer to Short (16 bit signed)
5789 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5790 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5791 ins_cost(MEMORY_REF_COST);
5792
5793 size(4);
5794
5795 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5796 ins_encode %{
5797 __ ldsh($mem$$Address, $dst$$Register, 2);
5798 %}
5799 ins_pipe(iload_mask_mem);
5800 %}
5801
5802 // Load Integer to Unsigned Short (16 bit UNsigned)
5803 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5804 match(Set dst (AndI (LoadI mem) mask));
5805 ins_cost(MEMORY_REF_COST);
5806
5807 size(4);
5808
5809 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5810 ins_encode %{
5811 __ lduh($mem$$Address, $dst$$Register, 2);
5812 %}
5813 ins_pipe(iload_mask_mem);
5814 %}
5815
5816 // Load Integer into a Long Register
5817 instruct loadI2L(iRegL dst, memory mem) %{
5818 match(Set dst (ConvI2L (LoadI mem)));
5819 ins_cost(MEMORY_REF_COST);
5820
5821 size(4);
5822 format %{ "LDSW $mem,$dst\t! int -> long" %}
5823 ins_encode %{
5824 __ ldsw($mem$$Address, $dst$$Register);
5825 %}
5826 ins_pipe(iload_mask_mem);
5827 %}
5828
5829 // Load Integer with mask 0xFF into a Long Register
5830 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5831 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5832 ins_cost(MEMORY_REF_COST);
5833
5834 size(4);
5835 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5836 ins_encode %{
5837 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5838 %}
5839 ins_pipe(iload_mem);
5840 %}
5841
5842 // Load Integer with mask 0xFFFF into a Long Register
5843 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5844 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5845 ins_cost(MEMORY_REF_COST);
5846
5847 size(4);
5848 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5849 ins_encode %{
5850 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5851 %}
5852 ins_pipe(iload_mem);
5853 %}
5854
5855 // Load Integer with a 13-bit mask into a Long Register
5856 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5857 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5858 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5859
5860 size(2*4);
5861 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5862 "AND $dst,$mask,$dst" %}
5863 ins_encode %{
5864 Register Rdst = $dst$$Register;
5865 __ lduw($mem$$Address, Rdst);
5866 __ and3(Rdst, $mask$$constant, Rdst);
5867 %}
5868 ins_pipe(iload_mem);
5869 %}
5870
5871 // Load Integer with a 32-bit mask into a Long Register
5872 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5873 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5874 effect(TEMP dst, TEMP tmp);
5875 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5876
5877 size((3+1)*4); // set may use two instructions.
5878 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5879 "SET $mask,$tmp\n\t"
5880 "AND $dst,$tmp,$dst" %}
5881 ins_encode %{
5882 Register Rdst = $dst$$Register;
5883 Register Rtmp = $tmp$$Register;
5884 __ lduw($mem$$Address, Rdst);
5885 __ set($mask$$constant, Rtmp);
5886 __ and3(Rdst, Rtmp, Rdst);
5887 %}
5888 ins_pipe(iload_mem);
5889 %}
5890
5891 // Load Unsigned Integer into a Long Register
5892 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5893 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5894 ins_cost(MEMORY_REF_COST);
5895
5896 size(4);
5897 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5898 ins_encode %{
5899 __ lduw($mem$$Address, $dst$$Register);
5900 %}
5901 ins_pipe(iload_mem);
5902 %}
5903
5904 // Load Long - aligned
5905 instruct loadL(iRegL dst, memory mem ) %{
5906 match(Set dst (LoadL mem));
5907 ins_cost(MEMORY_REF_COST);
5908
5909 size(4);
5910 format %{ "LDX $mem,$dst\t! long" %}
5911 ins_encode %{
5912 __ ldx($mem$$Address, $dst$$Register);
5913 %}
5914 ins_pipe(iload_mem);
5915 %}
5916
5917 // Load Long - UNaligned
5918 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5919 match(Set dst (LoadL_unaligned mem));
5920 effect(KILL tmp);
5921 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5922 size(16);
5923 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5924 "\tLDUW $mem ,$dst\n"
5925 "\tSLLX #32, $dst, $dst\n"
5926 "\tOR $dst, R_O7, $dst" %}
5927 opcode(Assembler::lduw_op3);
5928 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5929 ins_pipe(iload_mem);
5930 %}
5931
5932 // Load Range
5933 instruct loadRange(iRegI dst, memory mem) %{
5934 match(Set dst (LoadRange mem));
5935 ins_cost(MEMORY_REF_COST);
5936
5937 size(4);
5938 format %{ "LDUW $mem,$dst\t! range" %}
5939 opcode(Assembler::lduw_op3);
5940 ins_encode(simple_form3_mem_reg( mem, dst ) );
5941 ins_pipe(iload_mem);
5942 %}
5943
5944 // Load Integer into %f register (for fitos/fitod)
5945 instruct loadI_freg(regF dst, memory mem) %{
5946 match(Set dst (LoadI mem));
5947 ins_cost(MEMORY_REF_COST);
5948 size(4);
5949
5950 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5951 opcode(Assembler::ldf_op3);
5952 ins_encode(simple_form3_mem_reg( mem, dst ) );
5953 ins_pipe(floadF_mem);
5954 %}
5955
5956 // Load Pointer
5957 instruct loadP(iRegP dst, memory mem) %{
5958 match(Set dst (LoadP mem));
5959 ins_cost(MEMORY_REF_COST);
5960 size(4);
5961
5962 #ifndef _LP64
5963 format %{ "LDUW $mem,$dst\t! ptr" %}
5964 ins_encode %{
5965 __ lduw($mem$$Address, $dst$$Register);
5966 %}
5967 #else
5968 format %{ "LDX $mem,$dst\t! ptr" %}
5969 ins_encode %{
5970 __ ldx($mem$$Address, $dst$$Register);
5971 %}
5972 #endif
5973 ins_pipe(iload_mem);
5974 %}
5975
5976 // Load Compressed Pointer
5977 instruct loadN(iRegN dst, memory mem) %{
5978 match(Set dst (LoadN mem));
5979 ins_cost(MEMORY_REF_COST);
5980 size(4);
5981
5982 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5983 ins_encode %{
5984 __ lduw($mem$$Address, $dst$$Register);
5985 %}
5986 ins_pipe(iload_mem);
5987 %}
5988
5989 // Load Klass Pointer
5990 instruct loadKlass(iRegP dst, memory mem) %{
5991 match(Set dst (LoadKlass mem));
5992 ins_cost(MEMORY_REF_COST);
5993 size(4);
5994
5995 #ifndef _LP64
5996 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5997 ins_encode %{
5998 __ lduw($mem$$Address, $dst$$Register);
5999 %}
6000 #else
6001 format %{ "LDX $mem,$dst\t! klass ptr" %}
6002 ins_encode %{
6003 __ ldx($mem$$Address, $dst$$Register);
6004 %}
6005 #endif
6006 ins_pipe(iload_mem);
6007 %}
6008
6009 // Load narrow Klass Pointer
6010 instruct loadNKlass(iRegN dst, memory mem) %{
6011 match(Set dst (LoadNKlass mem));
6012 ins_cost(MEMORY_REF_COST);
6013 size(4);
6014
6015 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6016 ins_encode %{
6017 __ lduw($mem$$Address, $dst$$Register);
6018 %}
6019 ins_pipe(iload_mem);
6020 %}
6021
6022 // Load Double
6023 instruct loadD(regD dst, memory mem) %{
6024 match(Set dst (LoadD mem));
6025 ins_cost(MEMORY_REF_COST);
6026
6027 size(4);
6028 format %{ "LDDF $mem,$dst" %}
6029 opcode(Assembler::lddf_op3);
6030 ins_encode(simple_form3_mem_reg( mem, dst ) );
6031 ins_pipe(floadD_mem);
6032 %}
6033
6034 // Load Double - UNaligned
6035 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6036 match(Set dst (LoadD_unaligned mem));
6037 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6038 size(8);
6039 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6040 "\tLDF $mem+4,$dst.lo\t!" %}
6041 opcode(Assembler::ldf_op3);
6042 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6043 ins_pipe(iload_mem);
6044 %}
6045
6046 // Load Float
6047 instruct loadF(regF dst, memory mem) %{
6048 match(Set dst (LoadF mem));
6049 ins_cost(MEMORY_REF_COST);
6050
6051 size(4);
6052 format %{ "LDF $mem,$dst" %}
6053 opcode(Assembler::ldf_op3);
6054 ins_encode(simple_form3_mem_reg( mem, dst ) );
6055 ins_pipe(floadF_mem);
6056 %}
6057
6058 // Load Constant
6059 instruct loadConI( iRegI dst, immI src ) %{
6060 match(Set dst src);
6061 ins_cost(DEFAULT_COST * 3/2);
6062 format %{ "SET $src,$dst" %}
6063 ins_encode( Set32(src, dst) );
6064 ins_pipe(ialu_hi_lo_reg);
6065 %}
6066
6067 instruct loadConI13( iRegI dst, immI13 src ) %{
6068 match(Set dst src);
6069
6070 size(4);
6071 format %{ "MOV $src,$dst" %}
6072 ins_encode( Set13( src, dst ) );
6073 ins_pipe(ialu_imm);
6074 %}
6075
6076 #ifndef _LP64
6077 instruct loadConP(iRegP dst, immP con) %{
6078 match(Set dst con);
6079 ins_cost(DEFAULT_COST * 3/2);
6080 format %{ "SET $con,$dst\t!ptr" %}
6081 ins_encode %{
6082 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6083 intptr_t val = $con$$constant;
6084 if (constant_reloc == relocInfo::oop_type) {
6085 __ set_oop_constant((jobject) val, $dst$$Register);
6086 } else if (constant_reloc == relocInfo::metadata_type) {
6087 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6088 } else { // non-oop pointers, e.g. card mark base, heap top
6089 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6090 __ set(val, $dst$$Register);
6091 }
6092 %}
6093 ins_pipe(loadConP);
6094 %}
6095 #else
6096 instruct loadConP_set(iRegP dst, immP_set con) %{
6097 match(Set dst con);
6098 ins_cost(DEFAULT_COST * 3/2);
6099 format %{ "SET $con,$dst\t! ptr" %}
6100 ins_encode %{
6101 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6102 intptr_t val = $con$$constant;
6103 if (constant_reloc == relocInfo::oop_type) {
6104 __ set_oop_constant((jobject) val, $dst$$Register);
6105 } else if (constant_reloc == relocInfo::metadata_type) {
6106 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6107 } else { // non-oop pointers, e.g. card mark base, heap top
6108 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6109 __ set(val, $dst$$Register);
6110 }
6111 %}
6112 ins_pipe(loadConP);
6113 %}
6114
6115 instruct loadConP_load(iRegP dst, immP_load con) %{
6116 match(Set dst con);
6117 ins_cost(MEMORY_REF_COST);
6118 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6119 ins_encode %{
6120 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6121 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6122 %}
6123 ins_pipe(loadConP);
6124 %}
6125
6126 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6127 match(Set dst con);
6128 ins_cost(DEFAULT_COST * 3/2);
6129 format %{ "SET $con,$dst\t! non-oop ptr" %}
6130 ins_encode %{
6131 __ set($con$$constant, $dst$$Register);
6132 %}
6133 ins_pipe(loadConP);
6134 %}
6135 #endif // _LP64
6136
6137 instruct loadConP0(iRegP dst, immP0 src) %{
6138 match(Set dst src);
6139
6140 size(4);
6141 format %{ "CLR $dst\t!ptr" %}
6142 ins_encode %{
6143 __ clr($dst$$Register);
6144 %}
6145 ins_pipe(ialu_imm);
6146 %}
6147
6148 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6149 match(Set dst src);
6150 ins_cost(DEFAULT_COST);
6151 format %{ "SET $src,$dst\t!ptr" %}
6152 ins_encode %{
6153 AddressLiteral polling_page(os::get_polling_page());
6154 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6155 %}
6156 ins_pipe(loadConP_poll);
6157 %}
6158
6159 instruct loadConN0(iRegN dst, immN0 src) %{
6160 match(Set dst src);
6161
6162 size(4);
6163 format %{ "CLR $dst\t! compressed NULL ptr" %}
6164 ins_encode %{
6165 __ clr($dst$$Register);
6166 %}
6167 ins_pipe(ialu_imm);
6168 %}
6169
6170 instruct loadConN(iRegN dst, immN src) %{
6171 match(Set dst src);
6172 ins_cost(DEFAULT_COST * 3/2);
6173 format %{ "SET $src,$dst\t! compressed ptr" %}
6174 ins_encode %{
6175 Register dst = $dst$$Register;
6176 __ set_narrow_oop((jobject)$src$$constant, dst);
6177 %}
6178 ins_pipe(ialu_hi_lo_reg);
6179 %}
6180
6181 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6182 match(Set dst src);
6183 ins_cost(DEFAULT_COST * 3/2);
6184 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6185 ins_encode %{
6186 Register dst = $dst$$Register;
6187 __ set_narrow_klass((Klass*)$src$$constant, dst);
6188 %}
6189 ins_pipe(ialu_hi_lo_reg);
6190 %}
6191
6192 // Materialize long value (predicated by immL_cheap).
6193 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6194 match(Set dst con);
6195 effect(KILL tmp);
6196 ins_cost(DEFAULT_COST * 3);
6197 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6198 ins_encode %{
6199 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6200 %}
6201 ins_pipe(loadConL);
6202 %}
6203
6204 // Load long value from constant table (predicated by immL_expensive).
6205 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6206 match(Set dst con);
6207 ins_cost(MEMORY_REF_COST);
6208 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6209 ins_encode %{
6210 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6211 __ ldx($constanttablebase, con_offset, $dst$$Register);
6212 %}
6213 ins_pipe(loadConL);
6214 %}
6215
6216 instruct loadConL0( iRegL dst, immL0 src ) %{
6217 match(Set dst src);
6218 ins_cost(DEFAULT_COST);
6219 size(4);
6220 format %{ "CLR $dst\t! long" %}
6221 ins_encode( Set13( src, dst ) );
6222 ins_pipe(ialu_imm);
6223 %}
6224
6225 instruct loadConL13( iRegL dst, immL13 src ) %{
6226 match(Set dst src);
6227 ins_cost(DEFAULT_COST * 2);
6228
6229 size(4);
6230 format %{ "MOV $src,$dst\t! long" %}
6231 ins_encode( Set13( src, dst ) );
6232 ins_pipe(ialu_imm);
6233 %}
6234
6235 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6236 match(Set dst con);
6237 effect(KILL tmp);
6238 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6239 ins_encode %{
6240 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6241 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6242 %}
6243 ins_pipe(loadConFD);
6244 %}
6245
6246 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6247 match(Set dst con);
6248 effect(KILL tmp);
6249 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6250 ins_encode %{
6251 // XXX This is a quick fix for 6833573.
6252 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6253 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6254 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6255 %}
6256 ins_pipe(loadConFD);
6257 %}
6258
6259 // Prefetch instructions.
6260 // Must be safe to execute with invalid address (cannot fault).
6261
6262 instruct prefetchr( memory mem ) %{
6263 match( PrefetchRead mem );
6264 ins_cost(MEMORY_REF_COST);
6265 size(4);
6266
6267 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6268 opcode(Assembler::prefetch_op3);
6269 ins_encode( form3_mem_prefetch_read( mem ) );
6270 ins_pipe(iload_mem);
6271 %}
6272
6273 instruct prefetchw( memory mem ) %{
6274 match( PrefetchWrite mem );
6275 ins_cost(MEMORY_REF_COST);
6276 size(4);
6277
6278 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6279 opcode(Assembler::prefetch_op3);
6280 ins_encode( form3_mem_prefetch_write( mem ) );
6281 ins_pipe(iload_mem);
6282 %}
6283
6284 // Prefetch instructions for allocation.
6285
6286 instruct prefetchAlloc( memory mem ) %{
6287 predicate(AllocatePrefetchInstr == 0);
6288 match( PrefetchAllocation mem );
6289 ins_cost(MEMORY_REF_COST);
6290 size(4);
6291
6292 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6293 opcode(Assembler::prefetch_op3);
6294 ins_encode( form3_mem_prefetch_write( mem ) );
6295 ins_pipe(iload_mem);
6296 %}
6297
6298 // Use BIS instruction to prefetch for allocation.
6299 // Could fault, need space at the end of TLAB.
6300 instruct prefetchAlloc_bis( iRegP dst ) %{
6301 predicate(AllocatePrefetchInstr == 1);
6302 match( PrefetchAllocation dst );
6303 ins_cost(MEMORY_REF_COST);
6304 size(4);
6305
6306 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6307 ins_encode %{
6308 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6309 %}
6310 ins_pipe(istore_mem_reg);
6311 %}
6312
6313 // Next code is used for finding next cache line address to prefetch.
6314 #ifndef _LP64
6315 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6316 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6317 ins_cost(DEFAULT_COST);
6318 size(4);
6319
6320 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6321 ins_encode %{
6322 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6323 %}
6324 ins_pipe(ialu_reg_imm);
6325 %}
6326 #else
6327 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6328 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6329 ins_cost(DEFAULT_COST);
6330 size(4);
6331
6332 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6333 ins_encode %{
6334 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6335 %}
6336 ins_pipe(ialu_reg_imm);
6337 %}
6338 #endif
6339
6340 //----------Store Instructions-------------------------------------------------
6341 // Store Byte
6342 instruct storeB(memory mem, iRegI src) %{
6343 match(Set mem (StoreB mem src));
6344 ins_cost(MEMORY_REF_COST);
6345
6346 size(4);
6347 format %{ "STB $src,$mem\t! byte" %}
6348 opcode(Assembler::stb_op3);
6349 ins_encode(simple_form3_mem_reg( mem, src ) );
6350 ins_pipe(istore_mem_reg);
6351 %}
6352
6353 instruct storeB0(memory mem, immI0 src) %{
6354 match(Set mem (StoreB mem src));
6355 ins_cost(MEMORY_REF_COST);
6356
6357 size(4);
6358 format %{ "STB $src,$mem\t! byte" %}
6359 opcode(Assembler::stb_op3);
6360 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6361 ins_pipe(istore_mem_zero);
6362 %}
6363
6364 instruct storeCM0(memory mem, immI0 src) %{
6365 match(Set mem (StoreCM mem src));
6366 ins_cost(MEMORY_REF_COST);
6367
6368 size(4);
6369 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6370 opcode(Assembler::stb_op3);
6371 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6372 ins_pipe(istore_mem_zero);
6373 %}
6374
6375 // Store Char/Short
6376 instruct storeC(memory mem, iRegI src) %{
6377 match(Set mem (StoreC mem src));
6378 ins_cost(MEMORY_REF_COST);
6379
6380 size(4);
6381 format %{ "STH $src,$mem\t! short" %}
6382 opcode(Assembler::sth_op3);
6383 ins_encode(simple_form3_mem_reg( mem, src ) );
6384 ins_pipe(istore_mem_reg);
6385 %}
6386
6387 instruct storeC0(memory mem, immI0 src) %{
6388 match(Set mem (StoreC mem src));
6389 ins_cost(MEMORY_REF_COST);
6390
6391 size(4);
6392 format %{ "STH $src,$mem\t! short" %}
6393 opcode(Assembler::sth_op3);
6394 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6395 ins_pipe(istore_mem_zero);
6396 %}
6397
6398 // Store Integer
6399 instruct storeI(memory mem, iRegI src) %{
6400 match(Set mem (StoreI mem src));
6401 ins_cost(MEMORY_REF_COST);
6402
6403 size(4);
6404 format %{ "STW $src,$mem" %}
6405 opcode(Assembler::stw_op3);
6406 ins_encode(simple_form3_mem_reg( mem, src ) );
6407 ins_pipe(istore_mem_reg);
6408 %}
6409
6410 // Store Long
6411 instruct storeL(memory mem, iRegL src) %{
6412 match(Set mem (StoreL mem src));
6413 ins_cost(MEMORY_REF_COST);
6414 size(4);
6415 format %{ "STX $src,$mem\t! long" %}
6416 opcode(Assembler::stx_op3);
6417 ins_encode(simple_form3_mem_reg( mem, src ) );
6418 ins_pipe(istore_mem_reg);
6419 %}
6420
6421 instruct storeI0(memory mem, immI0 src) %{
6422 match(Set mem (StoreI mem src));
6423 ins_cost(MEMORY_REF_COST);
6424
6425 size(4);
6426 format %{ "STW $src,$mem" %}
6427 opcode(Assembler::stw_op3);
6428 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6429 ins_pipe(istore_mem_zero);
6430 %}
6431
6432 instruct storeL0(memory mem, immL0 src) %{
6433 match(Set mem (StoreL mem src));
6434 ins_cost(MEMORY_REF_COST);
6435
6436 size(4);
6437 format %{ "STX $src,$mem" %}
6438 opcode(Assembler::stx_op3);
6439 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6440 ins_pipe(istore_mem_zero);
6441 %}
6442
6443 // Store Integer from float register (used after fstoi)
6444 instruct storeI_Freg(memory mem, regF src) %{
6445 match(Set mem (StoreI mem src));
6446 ins_cost(MEMORY_REF_COST);
6447
6448 size(4);
6449 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6450 opcode(Assembler::stf_op3);
6451 ins_encode(simple_form3_mem_reg( mem, src ) );
6452 ins_pipe(fstoreF_mem_reg);
6453 %}
6454
6455 // Store Pointer
6456 instruct storeP(memory dst, sp_ptr_RegP src) %{
6457 match(Set dst (StoreP dst src));
6458 ins_cost(MEMORY_REF_COST);
6459 size(4);
6460
6461 #ifndef _LP64
6462 format %{ "STW $src,$dst\t! ptr" %}
6463 opcode(Assembler::stw_op3, 0, REGP_OP);
6464 #else
6465 format %{ "STX $src,$dst\t! ptr" %}
6466 opcode(Assembler::stx_op3, 0, REGP_OP);
6467 #endif
6468 ins_encode( form3_mem_reg( dst, src ) );
6469 ins_pipe(istore_mem_spORreg);
6470 %}
6471
6472 instruct storeP0(memory dst, immP0 src) %{
6473 match(Set dst (StoreP dst src));
6474 ins_cost(MEMORY_REF_COST);
6475 size(4);
6476
6477 #ifndef _LP64
6478 format %{ "STW $src,$dst\t! ptr" %}
6479 opcode(Assembler::stw_op3, 0, REGP_OP);
6480 #else
6481 format %{ "STX $src,$dst\t! ptr" %}
6482 opcode(Assembler::stx_op3, 0, REGP_OP);
6483 #endif
6484 ins_encode( form3_mem_reg( dst, R_G0 ) );
6485 ins_pipe(istore_mem_zero);
6486 %}
6487
6488 // Store Compressed Pointer
6489 instruct storeN(memory dst, iRegN src) %{
6490 match(Set dst (StoreN dst src));
6491 ins_cost(MEMORY_REF_COST);
6492 size(4);
6493
6494 format %{ "STW $src,$dst\t! compressed ptr" %}
6495 ins_encode %{
6496 Register base = as_Register($dst$$base);
6497 Register index = as_Register($dst$$index);
6498 Register src = $src$$Register;
6499 if (index != G0) {
6500 __ stw(src, base, index);
6501 } else {
6502 __ stw(src, base, $dst$$disp);
6503 }
6504 %}
6505 ins_pipe(istore_mem_spORreg);
6506 %}
6507
6508 instruct storeNKlass(memory dst, iRegN src) %{
6509 match(Set dst (StoreNKlass dst src));
6510 ins_cost(MEMORY_REF_COST);
6511 size(4);
6512
6513 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6514 ins_encode %{
6515 Register base = as_Register($dst$$base);
6516 Register index = as_Register($dst$$index);
6517 Register src = $src$$Register;
6518 if (index != G0) {
6519 __ stw(src, base, index);
6520 } else {
6521 __ stw(src, base, $dst$$disp);
6522 }
6523 %}
6524 ins_pipe(istore_mem_spORreg);
6525 %}
6526
6527 instruct storeN0(memory dst, immN0 src) %{
6528 match(Set dst (StoreN dst src));
6529 ins_cost(MEMORY_REF_COST);
6530 size(4);
6531
6532 format %{ "STW $src,$dst\t! compressed ptr" %}
6533 ins_encode %{
6534 Register base = as_Register($dst$$base);
6535 Register index = as_Register($dst$$index);
6536 if (index != G0) {
6537 __ stw(0, base, index);
6538 } else {
6539 __ stw(0, base, $dst$$disp);
6540 }
6541 %}
6542 ins_pipe(istore_mem_zero);
6543 %}
6544
6545 // Store Double
6546 instruct storeD( memory mem, regD src) %{
6547 match(Set mem (StoreD mem src));
6548 ins_cost(MEMORY_REF_COST);
6549
6550 size(4);
6551 format %{ "STDF $src,$mem" %}
6552 opcode(Assembler::stdf_op3);
6553 ins_encode(simple_form3_mem_reg( mem, src ) );
6554 ins_pipe(fstoreD_mem_reg);
6555 %}
6556
6557 instruct storeD0( memory mem, immD0 src) %{
6558 match(Set mem (StoreD mem src));
6559 ins_cost(MEMORY_REF_COST);
6560
6561 size(4);
6562 format %{ "STX $src,$mem" %}
6563 opcode(Assembler::stx_op3);
6564 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6565 ins_pipe(fstoreD_mem_zero);
6566 %}
6567
6568 // Store Float
6569 instruct storeF( memory mem, regF src) %{
6570 match(Set mem (StoreF mem src));
6571 ins_cost(MEMORY_REF_COST);
6572
6573 size(4);
6574 format %{ "STF $src,$mem" %}
6575 opcode(Assembler::stf_op3);
6576 ins_encode(simple_form3_mem_reg( mem, src ) );
6577 ins_pipe(fstoreF_mem_reg);
6578 %}
6579
6580 instruct storeF0( memory mem, immF0 src) %{
6581 match(Set mem (StoreF mem src));
6582 ins_cost(MEMORY_REF_COST);
6583
6584 size(4);
6585 format %{ "STW $src,$mem\t! storeF0" %}
6586 opcode(Assembler::stw_op3);
6587 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6588 ins_pipe(fstoreF_mem_zero);
6589 %}
6590
6591 // Convert oop pointer into compressed form
6592 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6593 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6594 match(Set dst (EncodeP src));
6595 format %{ "encode_heap_oop $src, $dst" %}
6596 ins_encode %{
6597 __ encode_heap_oop($src$$Register, $dst$$Register);
6598 %}
6599 ins_pipe(ialu_reg);
6600 %}
6601
6602 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6603 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6604 match(Set dst (EncodeP src));
6605 format %{ "encode_heap_oop_not_null $src, $dst" %}
6606 ins_encode %{
6607 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6608 %}
6609 ins_pipe(ialu_reg);
6610 %}
6611
6612 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6613 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6614 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6615 match(Set dst (DecodeN src));
6616 format %{ "decode_heap_oop $src, $dst" %}
6617 ins_encode %{
6618 __ decode_heap_oop($src$$Register, $dst$$Register);
6619 %}
6620 ins_pipe(ialu_reg);
6621 %}
6622
6623 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6624 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6625 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6626 match(Set dst (DecodeN src));
6627 format %{ "decode_heap_oop_not_null $src, $dst" %}
6628 ins_encode %{
6629 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6630 %}
6631 ins_pipe(ialu_reg);
6632 %}
6633
6634 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6635 match(Set dst (EncodePKlass src));
6636 format %{ "encode_klass_not_null $src, $dst" %}
6637 ins_encode %{
6638 __ encode_klass_not_null($src$$Register, $dst$$Register);
6639 %}
6640 ins_pipe(ialu_reg);
6641 %}
6642
6643 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6644 match(Set dst (DecodeNKlass src));
6645 format %{ "decode_klass_not_null $src, $dst" %}
6646 ins_encode %{
6647 __ decode_klass_not_null($src$$Register, $dst$$Register);
6648 %}
6649 ins_pipe(ialu_reg);
6650 %}
6651
6652 //----------MemBar Instructions-----------------------------------------------
6653 // Memory barrier flavors
6654
6655 instruct membar_acquire() %{
6656 match(MemBarAcquire);
6657 ins_cost(4*MEMORY_REF_COST);
6658
6659 size(0);
6660 format %{ "MEMBAR-acquire" %}
6661 ins_encode( enc_membar_acquire );
6662 ins_pipe(long_memory_op);
6663 %}
6664
6665 instruct membar_acquire_lock() %{
6666 match(MemBarAcquireLock);
6667 ins_cost(0);
6668
6669 size(0);
6670 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6671 ins_encode( );
6672 ins_pipe(empty);
6673 %}
6674
6675 instruct membar_release() %{
6676 match(MemBarRelease);
6677 ins_cost(4*MEMORY_REF_COST);
6678
6679 size(0);
6680 format %{ "MEMBAR-release" %}
6681 ins_encode( enc_membar_release );
6682 ins_pipe(long_memory_op);
6683 %}
6684
6685 instruct membar_release_lock() %{
6686 match(MemBarReleaseLock);
6687 ins_cost(0);
6688
6689 size(0);
6690 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6691 ins_encode( );
6692 ins_pipe(empty);
6693 %}
6694
6695 instruct membar_volatile() %{
6696 match(MemBarVolatile);
6697 ins_cost(4*MEMORY_REF_COST);
6698
6699 size(4);
6700 format %{ "MEMBAR-volatile" %}
6701 ins_encode( enc_membar_volatile );
6702 ins_pipe(long_memory_op);
6703 %}
6704
6705 instruct unnecessary_membar_volatile() %{
6706 match(MemBarVolatile);
6707 predicate(Matcher::post_store_load_barrier(n));
6708 ins_cost(0);
6709
6710 size(0);
6711 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6712 ins_encode( );
6713 ins_pipe(empty);
6714 %}
6715
6716 instruct membar_storestore() %{
6717 match(MemBarStoreStore);
6718 ins_cost(0);
6719
6720 size(0);
6721 format %{ "!MEMBAR-storestore (empty encoding)" %}
6722 ins_encode( );
6723 ins_pipe(empty);
6724 %}
6725
6726 //----------Register Move Instructions-----------------------------------------
6727 instruct roundDouble_nop(regD dst) %{
6728 match(Set dst (RoundDouble dst));
6729 ins_cost(0);
6730 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6731 ins_encode( );
6732 ins_pipe(empty);
6733 %}
6734
6735
6736 instruct roundFloat_nop(regF dst) %{
6737 match(Set dst (RoundFloat dst));
6738 ins_cost(0);
6739 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6740 ins_encode( );
6741 ins_pipe(empty);
6742 %}
6743
6744
6745 // Cast Index to Pointer for unsafe natives
6746 instruct castX2P(iRegX src, iRegP dst) %{
6747 match(Set dst (CastX2P src));
6748
6749 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6750 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6751 ins_pipe(ialu_reg);
6752 %}
6753
6754 // Cast Pointer to Index for unsafe natives
6755 instruct castP2X(iRegP src, iRegX dst) %{
6756 match(Set dst (CastP2X src));
6757
6758 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6759 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6760 ins_pipe(ialu_reg);
6761 %}
6762
6763 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6764 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6765 match(Set stkSlot src); // chain rule
6766 ins_cost(MEMORY_REF_COST);
6767 format %{ "STDF $src,$stkSlot\t!stk" %}
6768 opcode(Assembler::stdf_op3);
6769 ins_encode(simple_form3_mem_reg(stkSlot, src));
6770 ins_pipe(fstoreD_stk_reg);
6771 %}
6772
6773 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6774 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6775 match(Set dst stkSlot); // chain rule
6776 ins_cost(MEMORY_REF_COST);
6777 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6778 opcode(Assembler::lddf_op3);
6779 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6780 ins_pipe(floadD_stk);
6781 %}
6782
6783 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6784 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6785 match(Set stkSlot src); // chain rule
6786 ins_cost(MEMORY_REF_COST);
6787 format %{ "STF $src,$stkSlot\t!stk" %}
6788 opcode(Assembler::stf_op3);
6789 ins_encode(simple_form3_mem_reg(stkSlot, src));
6790 ins_pipe(fstoreF_stk_reg);
6791 %}
6792
6793 //----------Conditional Move---------------------------------------------------
6794 // Conditional move
6795 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6796 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6797 ins_cost(150);
6798 format %{ "MOV$cmp $pcc,$src,$dst" %}
6799 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6800 ins_pipe(ialu_reg);
6801 %}
6802
6803 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6804 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6805 ins_cost(140);
6806 format %{ "MOV$cmp $pcc,$src,$dst" %}
6807 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6808 ins_pipe(ialu_imm);
6809 %}
6810
6811 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6812 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6813 ins_cost(150);
6814 size(4);
6815 format %{ "MOV$cmp $icc,$src,$dst" %}
6816 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6817 ins_pipe(ialu_reg);
6818 %}
6819
6820 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6821 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6822 ins_cost(140);
6823 size(4);
6824 format %{ "MOV$cmp $icc,$src,$dst" %}
6825 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6826 ins_pipe(ialu_imm);
6827 %}
6828
6829 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6830 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6831 ins_cost(150);
6832 size(4);
6833 format %{ "MOV$cmp $icc,$src,$dst" %}
6834 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6835 ins_pipe(ialu_reg);
6836 %}
6837
6838 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6839 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6840 ins_cost(140);
6841 size(4);
6842 format %{ "MOV$cmp $icc,$src,$dst" %}
6843 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6844 ins_pipe(ialu_imm);
6845 %}
6846
6847 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6848 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6849 ins_cost(150);
6850 size(4);
6851 format %{ "MOV$cmp $fcc,$src,$dst" %}
6852 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6853 ins_pipe(ialu_reg);
6854 %}
6855
6856 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6857 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6858 ins_cost(140);
6859 size(4);
6860 format %{ "MOV$cmp $fcc,$src,$dst" %}
6861 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6862 ins_pipe(ialu_imm);
6863 %}
6864
6865 // Conditional move for RegN. Only cmov(reg,reg).
6866 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6867 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6868 ins_cost(150);
6869 format %{ "MOV$cmp $pcc,$src,$dst" %}
6870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6871 ins_pipe(ialu_reg);
6872 %}
6873
6874 // This instruction also works with CmpN so we don't need cmovNN_reg.
6875 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6876 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6877 ins_cost(150);
6878 size(4);
6879 format %{ "MOV$cmp $icc,$src,$dst" %}
6880 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6881 ins_pipe(ialu_reg);
6882 %}
6883
6884 // This instruction also works with CmpN so we don't need cmovNN_reg.
6885 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6886 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6887 ins_cost(150);
6888 size(4);
6889 format %{ "MOV$cmp $icc,$src,$dst" %}
6890 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6891 ins_pipe(ialu_reg);
6892 %}
6893
6894 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6895 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6896 ins_cost(150);
6897 size(4);
6898 format %{ "MOV$cmp $fcc,$src,$dst" %}
6899 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6900 ins_pipe(ialu_reg);
6901 %}
6902
6903 // Conditional move
6904 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6905 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6906 ins_cost(150);
6907 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6908 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6909 ins_pipe(ialu_reg);
6910 %}
6911
6912 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6913 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6914 ins_cost(140);
6915 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6916 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6917 ins_pipe(ialu_imm);
6918 %}
6919
6920 // This instruction also works with CmpN so we don't need cmovPN_reg.
6921 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6922 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6923 ins_cost(150);
6924
6925 size(4);
6926 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6927 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6928 ins_pipe(ialu_reg);
6929 %}
6930
6931 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6932 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6933 ins_cost(150);
6934
6935 size(4);
6936 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6937 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6938 ins_pipe(ialu_reg);
6939 %}
6940
6941 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6942 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6943 ins_cost(140);
6944
6945 size(4);
6946 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6947 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6948 ins_pipe(ialu_imm);
6949 %}
6950
6951 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6952 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6953 ins_cost(140);
6954
6955 size(4);
6956 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6957 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6958 ins_pipe(ialu_imm);
6959 %}
6960
6961 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6962 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6963 ins_cost(150);
6964 size(4);
6965 format %{ "MOV$cmp $fcc,$src,$dst" %}
6966 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6967 ins_pipe(ialu_imm);
6968 %}
6969
6970 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6971 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6972 ins_cost(140);
6973 size(4);
6974 format %{ "MOV$cmp $fcc,$src,$dst" %}
6975 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6976 ins_pipe(ialu_imm);
6977 %}
6978
6979 // Conditional move
6980 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6981 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6982 ins_cost(150);
6983 opcode(0x101);
6984 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6985 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6986 ins_pipe(int_conditional_float_move);
6987 %}
6988
6989 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6990 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6991 ins_cost(150);
6992
6993 size(4);
6994 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6995 opcode(0x101);
6996 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6997 ins_pipe(int_conditional_float_move);
6998 %}
6999
7000 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7001 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7002 ins_cost(150);
7003
7004 size(4);
7005 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7006 opcode(0x101);
7007 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7008 ins_pipe(int_conditional_float_move);
7009 %}
7010
7011 // Conditional move,
7012 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7013 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7014 ins_cost(150);
7015 size(4);
7016 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7017 opcode(0x1);
7018 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7019 ins_pipe(int_conditional_double_move);
7020 %}
7021
7022 // Conditional move
7023 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7024 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7025 ins_cost(150);
7026 size(4);
7027 opcode(0x102);
7028 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7029 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7030 ins_pipe(int_conditional_double_move);
7031 %}
7032
7033 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7034 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7035 ins_cost(150);
7036
7037 size(4);
7038 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7039 opcode(0x102);
7040 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7041 ins_pipe(int_conditional_double_move);
7042 %}
7043
7044 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7045 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7046 ins_cost(150);
7047
7048 size(4);
7049 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7050 opcode(0x102);
7051 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7052 ins_pipe(int_conditional_double_move);
7053 %}
7054
7055 // Conditional move,
7056 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7057 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7058 ins_cost(150);
7059 size(4);
7060 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7061 opcode(0x2);
7062 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7063 ins_pipe(int_conditional_double_move);
7064 %}
7065
7066 // Conditional move
7067 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7068 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7069 ins_cost(150);
7070 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7071 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7072 ins_pipe(ialu_reg);
7073 %}
7074
7075 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7076 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7077 ins_cost(140);
7078 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7079 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7080 ins_pipe(ialu_imm);
7081 %}
7082
7083 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7084 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7085 ins_cost(150);
7086
7087 size(4);
7088 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7089 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7090 ins_pipe(ialu_reg);
7091 %}
7092
7093
7094 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7095 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7096 ins_cost(150);
7097
7098 size(4);
7099 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7100 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7101 ins_pipe(ialu_reg);
7102 %}
7103
7104
7105 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7106 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7107 ins_cost(150);
7108
7109 size(4);
7110 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7111 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7112 ins_pipe(ialu_reg);
7113 %}
7114
7115
7116
7117 //----------OS and Locking Instructions----------------------------------------
7118
7119 // This name is KNOWN by the ADLC and cannot be changed.
7120 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7121 // for this guy.
7122 instruct tlsLoadP(g2RegP dst) %{
7123 match(Set dst (ThreadLocal));
7124
7125 size(0);
7126 ins_cost(0);
7127 format %{ "# TLS is in G2" %}
7128 ins_encode( /*empty encoding*/ );
7129 ins_pipe(ialu_none);
7130 %}
7131
7132 instruct checkCastPP( iRegP dst ) %{
7133 match(Set dst (CheckCastPP dst));
7134
7135 size(0);
7136 format %{ "# checkcastPP of $dst" %}
7137 ins_encode( /*empty encoding*/ );
7138 ins_pipe(empty);
7139 %}
7140
7141
7142 instruct castPP( iRegP dst ) %{
7143 match(Set dst (CastPP dst));
7144 format %{ "# castPP of $dst" %}
7145 ins_encode( /*empty encoding*/ );
7146 ins_pipe(empty);
7147 %}
7148
7149 instruct castII( iRegI dst ) %{
7150 match(Set dst (CastII dst));
7151 format %{ "# castII of $dst" %}
7152 ins_encode( /*empty encoding*/ );
7153 ins_cost(0);
7154 ins_pipe(empty);
7155 %}
7156
7157 //----------Arithmetic Instructions--------------------------------------------
7158 // Addition Instructions
7159 // Register Addition
7160 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7161 match(Set dst (AddI src1 src2));
7162
7163 size(4);
7164 format %{ "ADD $src1,$src2,$dst" %}
7165 ins_encode %{
7166 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7167 %}
7168 ins_pipe(ialu_reg_reg);
7169 %}
7170
7171 // Immediate Addition
7172 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7173 match(Set dst (AddI src1 src2));
7174
7175 size(4);
7176 format %{ "ADD $src1,$src2,$dst" %}
7177 opcode(Assembler::add_op3, Assembler::arith_op);
7178 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7179 ins_pipe(ialu_reg_imm);
7180 %}
7181
7182 // Pointer Register Addition
7183 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7184 match(Set dst (AddP src1 src2));
7185
7186 size(4);
7187 format %{ "ADD $src1,$src2,$dst" %}
7188 opcode(Assembler::add_op3, Assembler::arith_op);
7189 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7190 ins_pipe(ialu_reg_reg);
7191 %}
7192
7193 // Pointer Immediate Addition
7194 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7195 match(Set dst (AddP src1 src2));
7196
7197 size(4);
7198 format %{ "ADD $src1,$src2,$dst" %}
7199 opcode(Assembler::add_op3, Assembler::arith_op);
7200 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7201 ins_pipe(ialu_reg_imm);
7202 %}
7203
7204 // Long Addition
7205 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7206 match(Set dst (AddL src1 src2));
7207
7208 size(4);
7209 format %{ "ADD $src1,$src2,$dst\t! long" %}
7210 opcode(Assembler::add_op3, Assembler::arith_op);
7211 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7212 ins_pipe(ialu_reg_reg);
7213 %}
7214
7215 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7216 match(Set dst (AddL src1 con));
7217
7218 size(4);
7219 format %{ "ADD $src1,$con,$dst" %}
7220 opcode(Assembler::add_op3, Assembler::arith_op);
7221 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7222 ins_pipe(ialu_reg_imm);
7223 %}
7224
7225 //----------Conditional_store--------------------------------------------------
7226 // Conditional-store of the updated heap-top.
7227 // Used during allocation of the shared heap.
7228 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7229
7230 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7231 instruct loadPLocked(iRegP dst, memory mem) %{
7232 match(Set dst (LoadPLocked mem));
7233 ins_cost(MEMORY_REF_COST);
7234
7235 #ifndef _LP64
7236 size(4);
7237 format %{ "LDUW $mem,$dst\t! ptr" %}
7238 opcode(Assembler::lduw_op3, 0, REGP_OP);
7239 #else
7240 format %{ "LDX $mem,$dst\t! ptr" %}
7241 opcode(Assembler::ldx_op3, 0, REGP_OP);
7242 #endif
7243 ins_encode( form3_mem_reg( mem, dst ) );
7244 ins_pipe(iload_mem);
7245 %}
7246
7247 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7248 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7249 effect( KILL newval );
7250 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7251 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7252 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7253 ins_pipe( long_memory_op );
7254 %}
7255
7256 // Conditional-store of an int value.
7257 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7258 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7259 effect( KILL newval );
7260 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7261 "CMP $oldval,$newval\t\t! See if we made progress" %}
7262 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7263 ins_pipe( long_memory_op );
7264 %}
7265
7266 // Conditional-store of a long value.
7267 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7268 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7269 effect( KILL newval );
7270 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7271 "CMP $oldval,$newval\t\t! See if we made progress" %}
7272 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7273 ins_pipe( long_memory_op );
7274 %}
7275
7276 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7277
7278 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7279 predicate(VM_Version::supports_cx8());
7280 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7281 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7282 format %{
7283 "MOV $newval,O7\n\t"
7284 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7285 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7286 "MOV 1,$res\n\t"
7287 "MOVne xcc,R_G0,$res"
7288 %}
7289 ins_encode( enc_casx(mem_ptr, oldval, newval),
7290 enc_lflags_ne_to_boolean(res) );
7291 ins_pipe( long_memory_op );
7292 %}
7293
7294
7295 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7296 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7297 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7298 format %{
7299 "MOV $newval,O7\n\t"
7300 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7301 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7302 "MOV 1,$res\n\t"
7303 "MOVne icc,R_G0,$res"
7304 %}
7305 ins_encode( enc_casi(mem_ptr, oldval, newval),
7306 enc_iflags_ne_to_boolean(res) );
7307 ins_pipe( long_memory_op );
7308 %}
7309
7310 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7311 #ifdef _LP64
7312 predicate(VM_Version::supports_cx8());
7313 #endif
7314 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7315 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7316 format %{
7317 "MOV $newval,O7\n\t"
7318 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7319 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7320 "MOV 1,$res\n\t"
7321 "MOVne xcc,R_G0,$res"
7322 %}
7323 #ifdef _LP64
7324 ins_encode( enc_casx(mem_ptr, oldval, newval),
7325 enc_lflags_ne_to_boolean(res) );
7326 #else
7327 ins_encode( enc_casi(mem_ptr, oldval, newval),
7328 enc_iflags_ne_to_boolean(res) );
7329 #endif
7330 ins_pipe( long_memory_op );
7331 %}
7332
7333 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7334 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7335 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7336 format %{
7337 "MOV $newval,O7\n\t"
7338 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7339 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7340 "MOV 1,$res\n\t"
7341 "MOVne icc,R_G0,$res"
7342 %}
7343 ins_encode( enc_casi(mem_ptr, oldval, newval),
7344 enc_iflags_ne_to_boolean(res) );
7345 ins_pipe( long_memory_op );
7346 %}
7347
7348 instruct xchgI( memory mem, iRegI newval) %{
7349 match(Set newval (GetAndSetI mem newval));
7350 format %{ "SWAP [$mem],$newval" %}
7351 size(4);
7352 ins_encode %{
7353 __ swap($mem$$Address, $newval$$Register);
7354 %}
7355 ins_pipe( long_memory_op );
7356 %}
7357
7358 #ifndef _LP64
7359 instruct xchgP( memory mem, iRegP newval) %{
7360 match(Set newval (GetAndSetP mem newval));
7361 format %{ "SWAP [$mem],$newval" %}
7362 size(4);
7363 ins_encode %{
7364 __ swap($mem$$Address, $newval$$Register);
7365 %}
7366 ins_pipe( long_memory_op );
7367 %}
7368 #endif
7369
7370 instruct xchgN( memory mem, iRegN newval) %{
7371 match(Set newval (GetAndSetN mem newval));
7372 format %{ "SWAP [$mem],$newval" %}
7373 size(4);
7374 ins_encode %{
7375 __ swap($mem$$Address, $newval$$Register);
7376 %}
7377 ins_pipe( long_memory_op );
7378 %}
7379
7380 //---------------------
7381 // Subtraction Instructions
7382 // Register Subtraction
7383 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7384 match(Set dst (SubI src1 src2));
7385
7386 size(4);
7387 format %{ "SUB $src1,$src2,$dst" %}
7388 opcode(Assembler::sub_op3, Assembler::arith_op);
7389 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7390 ins_pipe(ialu_reg_reg);
7391 %}
7392
7393 // Immediate Subtraction
7394 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7395 match(Set dst (SubI src1 src2));
7396
7397 size(4);
7398 format %{ "SUB $src1,$src2,$dst" %}
7399 opcode(Assembler::sub_op3, Assembler::arith_op);
7400 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7401 ins_pipe(ialu_reg_imm);
7402 %}
7403
7404 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7405 match(Set dst (SubI zero src2));
7406
7407 size(4);
7408 format %{ "NEG $src2,$dst" %}
7409 opcode(Assembler::sub_op3, Assembler::arith_op);
7410 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7411 ins_pipe(ialu_zero_reg);
7412 %}
7413
7414 // Long subtraction
7415 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7416 match(Set dst (SubL src1 src2));
7417
7418 size(4);
7419 format %{ "SUB $src1,$src2,$dst\t! long" %}
7420 opcode(Assembler::sub_op3, Assembler::arith_op);
7421 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7422 ins_pipe(ialu_reg_reg);
7423 %}
7424
7425 // Immediate Subtraction
7426 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7427 match(Set dst (SubL src1 con));
7428
7429 size(4);
7430 format %{ "SUB $src1,$con,$dst\t! long" %}
7431 opcode(Assembler::sub_op3, Assembler::arith_op);
7432 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7433 ins_pipe(ialu_reg_imm);
7434 %}
7435
7436 // Long negation
7437 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7438 match(Set dst (SubL zero src2));
7439
7440 size(4);
7441 format %{ "NEG $src2,$dst\t! long" %}
7442 opcode(Assembler::sub_op3, Assembler::arith_op);
7443 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7444 ins_pipe(ialu_zero_reg);
7445 %}
7446
7447 // Multiplication Instructions
7448 // Integer Multiplication
7449 // Register Multiplication
7450 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7451 match(Set dst (MulI src1 src2));
7452
7453 size(4);
7454 format %{ "MULX $src1,$src2,$dst" %}
7455 opcode(Assembler::mulx_op3, Assembler::arith_op);
7456 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7457 ins_pipe(imul_reg_reg);
7458 %}
7459
7460 // Immediate Multiplication
7461 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7462 match(Set dst (MulI src1 src2));
7463
7464 size(4);
7465 format %{ "MULX $src1,$src2,$dst" %}
7466 opcode(Assembler::mulx_op3, Assembler::arith_op);
7467 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7468 ins_pipe(imul_reg_imm);
7469 %}
7470
7471 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7472 match(Set dst (MulL src1 src2));
7473 ins_cost(DEFAULT_COST * 5);
7474 size(4);
7475 format %{ "MULX $src1,$src2,$dst\t! long" %}
7476 opcode(Assembler::mulx_op3, Assembler::arith_op);
7477 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7478 ins_pipe(mulL_reg_reg);
7479 %}
7480
7481 // Immediate Multiplication
7482 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7483 match(Set dst (MulL src1 src2));
7484 ins_cost(DEFAULT_COST * 5);
7485 size(4);
7486 format %{ "MULX $src1,$src2,$dst" %}
7487 opcode(Assembler::mulx_op3, Assembler::arith_op);
7488 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7489 ins_pipe(mulL_reg_imm);
7490 %}
7491
7492 // Integer Division
7493 // Register Division
7494 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7495 match(Set dst (DivI src1 src2));
7496 ins_cost((2+71)*DEFAULT_COST);
7497
7498 format %{ "SRA $src2,0,$src2\n\t"
7499 "SRA $src1,0,$src1\n\t"
7500 "SDIVX $src1,$src2,$dst" %}
7501 ins_encode( idiv_reg( src1, src2, dst ) );
7502 ins_pipe(sdiv_reg_reg);
7503 %}
7504
7505 // Immediate Division
7506 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7507 match(Set dst (DivI src1 src2));
7508 ins_cost((2+71)*DEFAULT_COST);
7509
7510 format %{ "SRA $src1,0,$src1\n\t"
7511 "SDIVX $src1,$src2,$dst" %}
7512 ins_encode( idiv_imm( src1, src2, dst ) );
7513 ins_pipe(sdiv_reg_imm);
7514 %}
7515
7516 //----------Div-By-10-Expansion------------------------------------------------
7517 // Extract hi bits of a 32x32->64 bit multiply.
7518 // Expand rule only, not matched
7519 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7520 effect( DEF dst, USE src1, USE src2 );
7521 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7522 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7523 ins_encode( enc_mul_hi(dst,src1,src2));
7524 ins_pipe(sdiv_reg_reg);
7525 %}
7526
7527 // Magic constant, reciprocal of 10
7528 instruct loadConI_x66666667(iRegIsafe dst) %{
7529 effect( DEF dst );
7530
7531 size(8);
7532 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7533 ins_encode( Set32(0x66666667, dst) );
7534 ins_pipe(ialu_hi_lo_reg);
7535 %}
7536
7537 // Register Shift Right Arithmetic Long by 32-63
7538 instruct sra_31( iRegI dst, iRegI src ) %{
7539 effect( DEF dst, USE src );
7540 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7541 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7542 ins_pipe(ialu_reg_reg);
7543 %}
7544
7545 // Arithmetic Shift Right by 8-bit immediate
7546 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7547 effect( DEF dst, USE src );
7548 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7549 opcode(Assembler::sra_op3, Assembler::arith_op);
7550 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7551 ins_pipe(ialu_reg_imm);
7552 %}
7553
7554 // Integer DIV with 10
7555 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7556 match(Set dst (DivI src div));
7557 ins_cost((6+6)*DEFAULT_COST);
7558 expand %{
7559 iRegIsafe tmp1; // Killed temps;
7560 iRegIsafe tmp2; // Killed temps;
7561 iRegI tmp3; // Killed temps;
7562 iRegI tmp4; // Killed temps;
7563 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7564 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7565 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7566 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7567 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7568 %}
7569 %}
7570
7571 // Register Long Division
7572 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7573 match(Set dst (DivL src1 src2));
7574 ins_cost(DEFAULT_COST*71);
7575 size(4);
7576 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7577 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7578 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7579 ins_pipe(divL_reg_reg);
7580 %}
7581
7582 // Register Long Division
7583 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7584 match(Set dst (DivL src1 src2));
7585 ins_cost(DEFAULT_COST*71);
7586 size(4);
7587 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7588 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7589 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7590 ins_pipe(divL_reg_imm);
7591 %}
7592
7593 // Integer Remainder
7594 // Register Remainder
7595 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7596 match(Set dst (ModI src1 src2));
7597 effect( KILL ccr, KILL temp);
7598
7599 format %{ "SREM $src1,$src2,$dst" %}
7600 ins_encode( irem_reg(src1, src2, dst, temp) );
7601 ins_pipe(sdiv_reg_reg);
7602 %}
7603
7604 // Immediate Remainder
7605 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7606 match(Set dst (ModI src1 src2));
7607 effect( KILL ccr, KILL temp);
7608
7609 format %{ "SREM $src1,$src2,$dst" %}
7610 ins_encode( irem_imm(src1, src2, dst, temp) );
7611 ins_pipe(sdiv_reg_imm);
7612 %}
7613
7614 // Register Long Remainder
7615 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7616 effect(DEF dst, USE src1, USE src2);
7617 size(4);
7618 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7619 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7620 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7621 ins_pipe(divL_reg_reg);
7622 %}
7623
7624 // Register Long Division
7625 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7626 effect(DEF dst, USE src1, USE src2);
7627 size(4);
7628 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7629 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7630 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7631 ins_pipe(divL_reg_imm);
7632 %}
7633
7634 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7635 effect(DEF dst, USE src1, USE src2);
7636 size(4);
7637 format %{ "MULX $src1,$src2,$dst\t! long" %}
7638 opcode(Assembler::mulx_op3, Assembler::arith_op);
7639 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7640 ins_pipe(mulL_reg_reg);
7641 %}
7642
7643 // Immediate Multiplication
7644 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7645 effect(DEF dst, USE src1, USE src2);
7646 size(4);
7647 format %{ "MULX $src1,$src2,$dst" %}
7648 opcode(Assembler::mulx_op3, Assembler::arith_op);
7649 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7650 ins_pipe(mulL_reg_imm);
7651 %}
7652
7653 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7654 effect(DEF dst, USE src1, USE src2);
7655 size(4);
7656 format %{ "SUB $src1,$src2,$dst\t! long" %}
7657 opcode(Assembler::sub_op3, Assembler::arith_op);
7658 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7659 ins_pipe(ialu_reg_reg);
7660 %}
7661
7662 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7663 effect(DEF dst, USE src1, USE src2);
7664 size(4);
7665 format %{ "SUB $src1,$src2,$dst\t! long" %}
7666 opcode(Assembler::sub_op3, Assembler::arith_op);
7667 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7668 ins_pipe(ialu_reg_reg);
7669 %}
7670
7671 // Register Long Remainder
7672 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7673 match(Set dst (ModL src1 src2));
7674 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7675 expand %{
7676 iRegL tmp1;
7677 iRegL tmp2;
7678 divL_reg_reg_1(tmp1, src1, src2);
7679 mulL_reg_reg_1(tmp2, tmp1, src2);
7680 subL_reg_reg_1(dst, src1, tmp2);
7681 %}
7682 %}
7683
7684 // Register Long Remainder
7685 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7686 match(Set dst (ModL src1 src2));
7687 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7688 expand %{
7689 iRegL tmp1;
7690 iRegL tmp2;
7691 divL_reg_imm13_1(tmp1, src1, src2);
7692 mulL_reg_imm13_1(tmp2, tmp1, src2);
7693 subL_reg_reg_2 (dst, src1, tmp2);
7694 %}
7695 %}
7696
7697 // Integer Shift Instructions
7698 // Register Shift Left
7699 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7700 match(Set dst (LShiftI src1 src2));
7701
7702 size(4);
7703 format %{ "SLL $src1,$src2,$dst" %}
7704 opcode(Assembler::sll_op3, Assembler::arith_op);
7705 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7706 ins_pipe(ialu_reg_reg);
7707 %}
7708
7709 // Register Shift Left Immediate
7710 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7711 match(Set dst (LShiftI src1 src2));
7712
7713 size(4);
7714 format %{ "SLL $src1,$src2,$dst" %}
7715 opcode(Assembler::sll_op3, Assembler::arith_op);
7716 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7717 ins_pipe(ialu_reg_imm);
7718 %}
7719
7720 // Register Shift Left
7721 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7722 match(Set dst (LShiftL src1 src2));
7723
7724 size(4);
7725 format %{ "SLLX $src1,$src2,$dst" %}
7726 opcode(Assembler::sllx_op3, Assembler::arith_op);
7727 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7728 ins_pipe(ialu_reg_reg);
7729 %}
7730
7731 // Register Shift Left Immediate
7732 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7733 match(Set dst (LShiftL src1 src2));
7734
7735 size(4);
7736 format %{ "SLLX $src1,$src2,$dst" %}
7737 opcode(Assembler::sllx_op3, Assembler::arith_op);
7738 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7739 ins_pipe(ialu_reg_imm);
7740 %}
7741
7742 // Register Arithmetic Shift Right
7743 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7744 match(Set dst (RShiftI src1 src2));
7745 size(4);
7746 format %{ "SRA $src1,$src2,$dst" %}
7747 opcode(Assembler::sra_op3, Assembler::arith_op);
7748 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7749 ins_pipe(ialu_reg_reg);
7750 %}
7751
7752 // Register Arithmetic Shift Right Immediate
7753 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7754 match(Set dst (RShiftI src1 src2));
7755
7756 size(4);
7757 format %{ "SRA $src1,$src2,$dst" %}
7758 opcode(Assembler::sra_op3, Assembler::arith_op);
7759 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7760 ins_pipe(ialu_reg_imm);
7761 %}
7762
7763 // Register Shift Right Arithmatic Long
7764 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7765 match(Set dst (RShiftL src1 src2));
7766
7767 size(4);
7768 format %{ "SRAX $src1,$src2,$dst" %}
7769 opcode(Assembler::srax_op3, Assembler::arith_op);
7770 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7771 ins_pipe(ialu_reg_reg);
7772 %}
7773
7774 // Register Shift Left Immediate
7775 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7776 match(Set dst (RShiftL src1 src2));
7777
7778 size(4);
7779 format %{ "SRAX $src1,$src2,$dst" %}
7780 opcode(Assembler::srax_op3, Assembler::arith_op);
7781 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7782 ins_pipe(ialu_reg_imm);
7783 %}
7784
7785 // Register Shift Right
7786 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7787 match(Set dst (URShiftI src1 src2));
7788
7789 size(4);
7790 format %{ "SRL $src1,$src2,$dst" %}
7791 opcode(Assembler::srl_op3, Assembler::arith_op);
7792 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7793 ins_pipe(ialu_reg_reg);
7794 %}
7795
7796 // Register Shift Right Immediate
7797 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7798 match(Set dst (URShiftI src1 src2));
7799
7800 size(4);
7801 format %{ "SRL $src1,$src2,$dst" %}
7802 opcode(Assembler::srl_op3, Assembler::arith_op);
7803 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7804 ins_pipe(ialu_reg_imm);
7805 %}
7806
7807 // Register Shift Right
7808 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7809 match(Set dst (URShiftL src1 src2));
7810
7811 size(4);
7812 format %{ "SRLX $src1,$src2,$dst" %}
7813 opcode(Assembler::srlx_op3, Assembler::arith_op);
7814 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7815 ins_pipe(ialu_reg_reg);
7816 %}
7817
7818 // Register Shift Right Immediate
7819 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7820 match(Set dst (URShiftL src1 src2));
7821
7822 size(4);
7823 format %{ "SRLX $src1,$src2,$dst" %}
7824 opcode(Assembler::srlx_op3, Assembler::arith_op);
7825 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7826 ins_pipe(ialu_reg_imm);
7827 %}
7828
7829 // Register Shift Right Immediate with a CastP2X
7830 #ifdef _LP64
7831 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7832 match(Set dst (URShiftL (CastP2X src1) src2));
7833 size(4);
7834 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7835 opcode(Assembler::srlx_op3, Assembler::arith_op);
7836 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7837 ins_pipe(ialu_reg_imm);
7838 %}
7839 #else
7840 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7841 match(Set dst (URShiftI (CastP2X src1) src2));
7842 size(4);
7843 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7844 opcode(Assembler::srl_op3, Assembler::arith_op);
7845 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7846 ins_pipe(ialu_reg_imm);
7847 %}
7848 #endif
7849
7850
7851 //----------Floating Point Arithmetic Instructions-----------------------------
7852
7853 // Add float single precision
7854 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7855 match(Set dst (AddF src1 src2));
7856
7857 size(4);
7858 format %{ "FADDS $src1,$src2,$dst" %}
7859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7860 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7861 ins_pipe(faddF_reg_reg);
7862 %}
7863
7864 // Add float double precision
7865 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7866 match(Set dst (AddD src1 src2));
7867
7868 size(4);
7869 format %{ "FADDD $src1,$src2,$dst" %}
7870 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7871 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7872 ins_pipe(faddD_reg_reg);
7873 %}
7874
7875 // Sub float single precision
7876 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7877 match(Set dst (SubF src1 src2));
7878
7879 size(4);
7880 format %{ "FSUBS $src1,$src2,$dst" %}
7881 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7882 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7883 ins_pipe(faddF_reg_reg);
7884 %}
7885
7886 // Sub float double precision
7887 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7888 match(Set dst (SubD src1 src2));
7889
7890 size(4);
7891 format %{ "FSUBD $src1,$src2,$dst" %}
7892 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7893 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7894 ins_pipe(faddD_reg_reg);
7895 %}
7896
7897 // Mul float single precision
7898 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7899 match(Set dst (MulF src1 src2));
7900
7901 size(4);
7902 format %{ "FMULS $src1,$src2,$dst" %}
7903 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7904 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7905 ins_pipe(fmulF_reg_reg);
7906 %}
7907
7908 // Mul float double precision
7909 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7910 match(Set dst (MulD src1 src2));
7911
7912 size(4);
7913 format %{ "FMULD $src1,$src2,$dst" %}
7914 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7915 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7916 ins_pipe(fmulD_reg_reg);
7917 %}
7918
7919 // Div float single precision
7920 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7921 match(Set dst (DivF src1 src2));
7922
7923 size(4);
7924 format %{ "FDIVS $src1,$src2,$dst" %}
7925 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7926 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7927 ins_pipe(fdivF_reg_reg);
7928 %}
7929
7930 // Div float double precision
7931 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7932 match(Set dst (DivD src1 src2));
7933
7934 size(4);
7935 format %{ "FDIVD $src1,$src2,$dst" %}
7936 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7937 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7938 ins_pipe(fdivD_reg_reg);
7939 %}
7940
7941 // Absolute float double precision
7942 instruct absD_reg(regD dst, regD src) %{
7943 match(Set dst (AbsD src));
7944
7945 format %{ "FABSd $src,$dst" %}
7946 ins_encode(fabsd(dst, src));
7947 ins_pipe(faddD_reg);
7948 %}
7949
7950 // Absolute float single precision
7951 instruct absF_reg(regF dst, regF src) %{
7952 match(Set dst (AbsF src));
7953
7954 format %{ "FABSs $src,$dst" %}
7955 ins_encode(fabss(dst, src));
7956 ins_pipe(faddF_reg);
7957 %}
7958
7959 instruct negF_reg(regF dst, regF src) %{
7960 match(Set dst (NegF src));
7961
7962 size(4);
7963 format %{ "FNEGs $src,$dst" %}
7964 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7965 ins_encode(form3_opf_rs2F_rdF(src, dst));
7966 ins_pipe(faddF_reg);
7967 %}
7968
7969 instruct negD_reg(regD dst, regD src) %{
7970 match(Set dst (NegD src));
7971
7972 format %{ "FNEGd $src,$dst" %}
7973 ins_encode(fnegd(dst, src));
7974 ins_pipe(faddD_reg);
7975 %}
7976
7977 // Sqrt float double precision
7978 instruct sqrtF_reg_reg(regF dst, regF src) %{
7979 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7980
7981 size(4);
7982 format %{ "FSQRTS $src,$dst" %}
7983 ins_encode(fsqrts(dst, src));
7984 ins_pipe(fdivF_reg_reg);
7985 %}
7986
7987 // Sqrt float double precision
7988 instruct sqrtD_reg_reg(regD dst, regD src) %{
7989 match(Set dst (SqrtD src));
7990
7991 size(4);
7992 format %{ "FSQRTD $src,$dst" %}
7993 ins_encode(fsqrtd(dst, src));
7994 ins_pipe(fdivD_reg_reg);
7995 %}
7996
7997 //----------Logical Instructions-----------------------------------------------
7998 // And Instructions
7999 // Register And
8000 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8001 match(Set dst (AndI src1 src2));
8002
8003 size(4);
8004 format %{ "AND $src1,$src2,$dst" %}
8005 opcode(Assembler::and_op3, Assembler::arith_op);
8006 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8007 ins_pipe(ialu_reg_reg);
8008 %}
8009
8010 // Immediate And
8011 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8012 match(Set dst (AndI src1 src2));
8013
8014 size(4);
8015 format %{ "AND $src1,$src2,$dst" %}
8016 opcode(Assembler::and_op3, Assembler::arith_op);
8017 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8018 ins_pipe(ialu_reg_imm);
8019 %}
8020
8021 // Register And Long
8022 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8023 match(Set dst (AndL src1 src2));
8024
8025 ins_cost(DEFAULT_COST);
8026 size(4);
8027 format %{ "AND $src1,$src2,$dst\t! long" %}
8028 opcode(Assembler::and_op3, Assembler::arith_op);
8029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8030 ins_pipe(ialu_reg_reg);
8031 %}
8032
8033 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8034 match(Set dst (AndL src1 con));
8035
8036 ins_cost(DEFAULT_COST);
8037 size(4);
8038 format %{ "AND $src1,$con,$dst\t! long" %}
8039 opcode(Assembler::and_op3, Assembler::arith_op);
8040 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8041 ins_pipe(ialu_reg_imm);
8042 %}
8043
8044 // Or Instructions
8045 // Register Or
8046 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8047 match(Set dst (OrI src1 src2));
8048
8049 size(4);
8050 format %{ "OR $src1,$src2,$dst" %}
8051 opcode(Assembler::or_op3, Assembler::arith_op);
8052 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8053 ins_pipe(ialu_reg_reg);
8054 %}
8055
8056 // Immediate Or
8057 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8058 match(Set dst (OrI src1 src2));
8059
8060 size(4);
8061 format %{ "OR $src1,$src2,$dst" %}
8062 opcode(Assembler::or_op3, Assembler::arith_op);
8063 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8064 ins_pipe(ialu_reg_imm);
8065 %}
8066
8067 // Register Or Long
8068 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8069 match(Set dst (OrL src1 src2));
8070
8071 ins_cost(DEFAULT_COST);
8072 size(4);
8073 format %{ "OR $src1,$src2,$dst\t! long" %}
8074 opcode(Assembler::or_op3, Assembler::arith_op);
8075 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8076 ins_pipe(ialu_reg_reg);
8077 %}
8078
8079 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8080 match(Set dst (OrL src1 con));
8081 ins_cost(DEFAULT_COST*2);
8082
8083 ins_cost(DEFAULT_COST);
8084 size(4);
8085 format %{ "OR $src1,$con,$dst\t! long" %}
8086 opcode(Assembler::or_op3, Assembler::arith_op);
8087 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8088 ins_pipe(ialu_reg_imm);
8089 %}
8090
8091 #ifndef _LP64
8092
8093 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8094 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8095 match(Set dst (OrI src1 (CastP2X src2)));
8096
8097 size(4);
8098 format %{ "OR $src1,$src2,$dst" %}
8099 opcode(Assembler::or_op3, Assembler::arith_op);
8100 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8101 ins_pipe(ialu_reg_reg);
8102 %}
8103
8104 #else
8105
8106 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8107 match(Set dst (OrL src1 (CastP2X src2)));
8108
8109 ins_cost(DEFAULT_COST);
8110 size(4);
8111 format %{ "OR $src1,$src2,$dst\t! long" %}
8112 opcode(Assembler::or_op3, Assembler::arith_op);
8113 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8114 ins_pipe(ialu_reg_reg);
8115 %}
8116
8117 #endif
8118
8119 // Xor Instructions
8120 // Register Xor
8121 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8122 match(Set dst (XorI src1 src2));
8123
8124 size(4);
8125 format %{ "XOR $src1,$src2,$dst" %}
8126 opcode(Assembler::xor_op3, Assembler::arith_op);
8127 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8128 ins_pipe(ialu_reg_reg);
8129 %}
8130
8131 // Immediate Xor
8132 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8133 match(Set dst (XorI src1 src2));
8134
8135 size(4);
8136 format %{ "XOR $src1,$src2,$dst" %}
8137 opcode(Assembler::xor_op3, Assembler::arith_op);
8138 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8139 ins_pipe(ialu_reg_imm);
8140 %}
8141
8142 // Register Xor Long
8143 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8144 match(Set dst (XorL src1 src2));
8145
8146 ins_cost(DEFAULT_COST);
8147 size(4);
8148 format %{ "XOR $src1,$src2,$dst\t! long" %}
8149 opcode(Assembler::xor_op3, Assembler::arith_op);
8150 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8151 ins_pipe(ialu_reg_reg);
8152 %}
8153
8154 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8155 match(Set dst (XorL src1 con));
8156
8157 ins_cost(DEFAULT_COST);
8158 size(4);
8159 format %{ "XOR $src1,$con,$dst\t! long" %}
8160 opcode(Assembler::xor_op3, Assembler::arith_op);
8161 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8162 ins_pipe(ialu_reg_imm);
8163 %}
8164
8165 //----------Convert to Boolean-------------------------------------------------
8166 // Nice hack for 32-bit tests but doesn't work for
8167 // 64-bit pointers.
8168 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8169 match(Set dst (Conv2B src));
8170 effect( KILL ccr );
8171 ins_cost(DEFAULT_COST*2);
8172 format %{ "CMP R_G0,$src\n\t"
8173 "ADDX R_G0,0,$dst" %}
8174 ins_encode( enc_to_bool( src, dst ) );
8175 ins_pipe(ialu_reg_ialu);
8176 %}
8177
8178 #ifndef _LP64
8179 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8180 match(Set dst (Conv2B src));
8181 effect( KILL ccr );
8182 ins_cost(DEFAULT_COST*2);
8183 format %{ "CMP R_G0,$src\n\t"
8184 "ADDX R_G0,0,$dst" %}
8185 ins_encode( enc_to_bool( src, dst ) );
8186 ins_pipe(ialu_reg_ialu);
8187 %}
8188 #else
8189 instruct convP2B( iRegI dst, iRegP src ) %{
8190 match(Set dst (Conv2B src));
8191 ins_cost(DEFAULT_COST*2);
8192 format %{ "MOV $src,$dst\n\t"
8193 "MOVRNZ $src,1,$dst" %}
8194 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8195 ins_pipe(ialu_clr_and_mover);
8196 %}
8197 #endif
8198
8199 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8200 match(Set dst (CmpLTMask src zero));
8201 effect(KILL ccr);
8202 size(4);
8203 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8204 ins_encode %{
8205 __ sra($src$$Register, 31, $dst$$Register);
8206 %}
8207 ins_pipe(ialu_reg_imm);
8208 %}
8209
8210 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8211 match(Set dst (CmpLTMask p q));
8212 effect( KILL ccr );
8213 ins_cost(DEFAULT_COST*4);
8214 format %{ "CMP $p,$q\n\t"
8215 "MOV #0,$dst\n\t"
8216 "BLT,a .+8\n\t"
8217 "MOV #-1,$dst" %}
8218 ins_encode( enc_ltmask(p,q,dst) );
8219 ins_pipe(ialu_reg_reg_ialu);
8220 %}
8221
8222 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8223 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8224 effect(KILL ccr, TEMP tmp);
8225 ins_cost(DEFAULT_COST*3);
8226
8227 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8228 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8229 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8230 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8231 ins_pipe( cadd_cmpltmask );
8232 %}
8233
8234
8235 //-----------------------------------------------------------------
8236 // Direct raw moves between float and general registers using VIS3.
8237
8238 // ins_pipe(faddF_reg);
8239 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8240 predicate(UseVIS >= 3);
8241 match(Set dst (MoveF2I src));
8242
8243 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8244 ins_encode %{
8245 __ movstouw($src$$FloatRegister, $dst$$Register);
8246 %}
8247 ins_pipe(ialu_reg_reg);
8248 %}
8249
8250 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8251 predicate(UseVIS >= 3);
8252 match(Set dst (MoveI2F src));
8253
8254 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8255 ins_encode %{
8256 __ movwtos($src$$Register, $dst$$FloatRegister);
8257 %}
8258 ins_pipe(ialu_reg_reg);
8259 %}
8260
8261 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8262 predicate(UseVIS >= 3);
8263 match(Set dst (MoveD2L src));
8264
8265 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8266 ins_encode %{
8267 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8268 %}
8269 ins_pipe(ialu_reg_reg);
8270 %}
8271
8272 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8273 predicate(UseVIS >= 3);
8274 match(Set dst (MoveL2D src));
8275
8276 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8277 ins_encode %{
8278 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8279 %}
8280 ins_pipe(ialu_reg_reg);
8281 %}
8282
8283
8284 // Raw moves between float and general registers using stack.
8285
8286 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8287 match(Set dst (MoveF2I src));
8288 effect(DEF dst, USE src);
8289 ins_cost(MEMORY_REF_COST);
8290
8291 size(4);
8292 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8293 opcode(Assembler::lduw_op3);
8294 ins_encode(simple_form3_mem_reg( src, dst ) );
8295 ins_pipe(iload_mem);
8296 %}
8297
8298 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8299 match(Set dst (MoveI2F src));
8300 effect(DEF dst, USE src);
8301 ins_cost(MEMORY_REF_COST);
8302
8303 size(4);
8304 format %{ "LDF $src,$dst\t! MoveI2F" %}
8305 opcode(Assembler::ldf_op3);
8306 ins_encode(simple_form3_mem_reg(src, dst));
8307 ins_pipe(floadF_stk);
8308 %}
8309
8310 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8311 match(Set dst (MoveD2L src));
8312 effect(DEF dst, USE src);
8313 ins_cost(MEMORY_REF_COST);
8314
8315 size(4);
8316 format %{ "LDX $src,$dst\t! MoveD2L" %}
8317 opcode(Assembler::ldx_op3);
8318 ins_encode(simple_form3_mem_reg( src, dst ) );
8319 ins_pipe(iload_mem);
8320 %}
8321
8322 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8323 match(Set dst (MoveL2D src));
8324 effect(DEF dst, USE src);
8325 ins_cost(MEMORY_REF_COST);
8326
8327 size(4);
8328 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8329 opcode(Assembler::lddf_op3);
8330 ins_encode(simple_form3_mem_reg(src, dst));
8331 ins_pipe(floadD_stk);
8332 %}
8333
8334 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8335 match(Set dst (MoveF2I src));
8336 effect(DEF dst, USE src);
8337 ins_cost(MEMORY_REF_COST);
8338
8339 size(4);
8340 format %{ "STF $src,$dst\t! MoveF2I" %}
8341 opcode(Assembler::stf_op3);
8342 ins_encode(simple_form3_mem_reg(dst, src));
8343 ins_pipe(fstoreF_stk_reg);
8344 %}
8345
8346 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8347 match(Set dst (MoveI2F src));
8348 effect(DEF dst, USE src);
8349 ins_cost(MEMORY_REF_COST);
8350
8351 size(4);
8352 format %{ "STW $src,$dst\t! MoveI2F" %}
8353 opcode(Assembler::stw_op3);
8354 ins_encode(simple_form3_mem_reg( dst, src ) );
8355 ins_pipe(istore_mem_reg);
8356 %}
8357
8358 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8359 match(Set dst (MoveD2L src));
8360 effect(DEF dst, USE src);
8361 ins_cost(MEMORY_REF_COST);
8362
8363 size(4);
8364 format %{ "STDF $src,$dst\t! MoveD2L" %}
8365 opcode(Assembler::stdf_op3);
8366 ins_encode(simple_form3_mem_reg(dst, src));
8367 ins_pipe(fstoreD_stk_reg);
8368 %}
8369
8370 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8371 match(Set dst (MoveL2D src));
8372 effect(DEF dst, USE src);
8373 ins_cost(MEMORY_REF_COST);
8374
8375 size(4);
8376 format %{ "STX $src,$dst\t! MoveL2D" %}
8377 opcode(Assembler::stx_op3);
8378 ins_encode(simple_form3_mem_reg( dst, src ) );
8379 ins_pipe(istore_mem_reg);
8380 %}
8381
8382
8383 //----------Arithmetic Conversion Instructions---------------------------------
8384 // The conversions operations are all Alpha sorted. Please keep it that way!
8385
8386 instruct convD2F_reg(regF dst, regD src) %{
8387 match(Set dst (ConvD2F src));
8388 size(4);
8389 format %{ "FDTOS $src,$dst" %}
8390 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8391 ins_encode(form3_opf_rs2D_rdF(src, dst));
8392 ins_pipe(fcvtD2F);
8393 %}
8394
8395
8396 // Convert a double to an int in a float register.
8397 // If the double is a NAN, stuff a zero in instead.
8398 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8399 effect(DEF dst, USE src, KILL fcc0);
8400 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8401 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8402 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8403 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8404 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8405 "skip:" %}
8406 ins_encode(form_d2i_helper(src,dst));
8407 ins_pipe(fcvtD2I);
8408 %}
8409
8410 instruct convD2I_stk(stackSlotI dst, regD src) %{
8411 match(Set dst (ConvD2I src));
8412 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8413 expand %{
8414 regF tmp;
8415 convD2I_helper(tmp, src);
8416 regF_to_stkI(dst, tmp);
8417 %}
8418 %}
8419
8420 instruct convD2I_reg(iRegI dst, regD src) %{
8421 predicate(UseVIS >= 3);
8422 match(Set dst (ConvD2I src));
8423 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8424 expand %{
8425 regF tmp;
8426 convD2I_helper(tmp, src);
8427 MoveF2I_reg_reg(dst, tmp);
8428 %}
8429 %}
8430
8431
8432 // Convert a double to a long in a double register.
8433 // If the double is a NAN, stuff a zero in instead.
8434 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8435 effect(DEF dst, USE src, KILL fcc0);
8436 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8437 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8438 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8439 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8440 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8441 "skip:" %}
8442 ins_encode(form_d2l_helper(src,dst));
8443 ins_pipe(fcvtD2L);
8444 %}
8445
8446 instruct convD2L_stk(stackSlotL dst, regD src) %{
8447 match(Set dst (ConvD2L src));
8448 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8449 expand %{
8450 regD tmp;
8451 convD2L_helper(tmp, src);
8452 regD_to_stkL(dst, tmp);
8453 %}
8454 %}
8455
8456 instruct convD2L_reg(iRegL dst, regD src) %{
8457 predicate(UseVIS >= 3);
8458 match(Set dst (ConvD2L src));
8459 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8460 expand %{
8461 regD tmp;
8462 convD2L_helper(tmp, src);
8463 MoveD2L_reg_reg(dst, tmp);
8464 %}
8465 %}
8466
8467
8468 instruct convF2D_reg(regD dst, regF src) %{
8469 match(Set dst (ConvF2D src));
8470 format %{ "FSTOD $src,$dst" %}
8471 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8472 ins_encode(form3_opf_rs2F_rdD(src, dst));
8473 ins_pipe(fcvtF2D);
8474 %}
8475
8476
8477 // Convert a float to an int in a float register.
8478 // If the float is a NAN, stuff a zero in instead.
8479 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8480 effect(DEF dst, USE src, KILL fcc0);
8481 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8482 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8483 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8484 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8485 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8486 "skip:" %}
8487 ins_encode(form_f2i_helper(src,dst));
8488 ins_pipe(fcvtF2I);
8489 %}
8490
8491 instruct convF2I_stk(stackSlotI dst, regF src) %{
8492 match(Set dst (ConvF2I src));
8493 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8494 expand %{
8495 regF tmp;
8496 convF2I_helper(tmp, src);
8497 regF_to_stkI(dst, tmp);
8498 %}
8499 %}
8500
8501 instruct convF2I_reg(iRegI dst, regF src) %{
8502 predicate(UseVIS >= 3);
8503 match(Set dst (ConvF2I src));
8504 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8505 expand %{
8506 regF tmp;
8507 convF2I_helper(tmp, src);
8508 MoveF2I_reg_reg(dst, tmp);
8509 %}
8510 %}
8511
8512
8513 // Convert a float to a long in a float register.
8514 // If the float is a NAN, stuff a zero in instead.
8515 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8516 effect(DEF dst, USE src, KILL fcc0);
8517 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8518 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8519 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8520 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8521 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8522 "skip:" %}
8523 ins_encode(form_f2l_helper(src,dst));
8524 ins_pipe(fcvtF2L);
8525 %}
8526
8527 instruct convF2L_stk(stackSlotL dst, regF src) %{
8528 match(Set dst (ConvF2L src));
8529 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8530 expand %{
8531 regD tmp;
8532 convF2L_helper(tmp, src);
8533 regD_to_stkL(dst, tmp);
8534 %}
8535 %}
8536
8537 instruct convF2L_reg(iRegL dst, regF src) %{
8538 predicate(UseVIS >= 3);
8539 match(Set dst (ConvF2L src));
8540 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8541 expand %{
8542 regD tmp;
8543 convF2L_helper(tmp, src);
8544 MoveD2L_reg_reg(dst, tmp);
8545 %}
8546 %}
8547
8548
8549 instruct convI2D_helper(regD dst, regF tmp) %{
8550 effect(USE tmp, DEF dst);
8551 format %{ "FITOD $tmp,$dst" %}
8552 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8553 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8554 ins_pipe(fcvtI2D);
8555 %}
8556
8557 instruct convI2D_stk(stackSlotI src, regD dst) %{
8558 match(Set dst (ConvI2D src));
8559 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8560 expand %{
8561 regF tmp;
8562 stkI_to_regF(tmp, src);
8563 convI2D_helper(dst, tmp);
8564 %}
8565 %}
8566
8567 instruct convI2D_reg(regD_low dst, iRegI src) %{
8568 predicate(UseVIS >= 3);
8569 match(Set dst (ConvI2D src));
8570 expand %{
8571 regF tmp;
8572 MoveI2F_reg_reg(tmp, src);
8573 convI2D_helper(dst, tmp);
8574 %}
8575 %}
8576
8577 instruct convI2D_mem(regD_low dst, memory mem) %{
8578 match(Set dst (ConvI2D (LoadI mem)));
8579 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8580 size(8);
8581 format %{ "LDF $mem,$dst\n\t"
8582 "FITOD $dst,$dst" %}
8583 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8584 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8585 ins_pipe(floadF_mem);
8586 %}
8587
8588
8589 instruct convI2F_helper(regF dst, regF tmp) %{
8590 effect(DEF dst, USE tmp);
8591 format %{ "FITOS $tmp,$dst" %}
8592 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8593 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8594 ins_pipe(fcvtI2F);
8595 %}
8596
8597 instruct convI2F_stk(regF dst, stackSlotI src) %{
8598 match(Set dst (ConvI2F src));
8599 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8600 expand %{
8601 regF tmp;
8602 stkI_to_regF(tmp,src);
8603 convI2F_helper(dst, tmp);
8604 %}
8605 %}
8606
8607 instruct convI2F_reg(regF dst, iRegI src) %{
8608 predicate(UseVIS >= 3);
8609 match(Set dst (ConvI2F src));
8610 ins_cost(DEFAULT_COST);
8611 expand %{
8612 regF tmp;
8613 MoveI2F_reg_reg(tmp, src);
8614 convI2F_helper(dst, tmp);
8615 %}
8616 %}
8617
8618 instruct convI2F_mem( regF dst, memory mem ) %{
8619 match(Set dst (ConvI2F (LoadI mem)));
8620 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8621 size(8);
8622 format %{ "LDF $mem,$dst\n\t"
8623 "FITOS $dst,$dst" %}
8624 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8625 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8626 ins_pipe(floadF_mem);
8627 %}
8628
8629
8630 instruct convI2L_reg(iRegL dst, iRegI src) %{
8631 match(Set dst (ConvI2L src));
8632 size(4);
8633 format %{ "SRA $src,0,$dst\t! int->long" %}
8634 opcode(Assembler::sra_op3, Assembler::arith_op);
8635 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8636 ins_pipe(ialu_reg_reg);
8637 %}
8638
8639 // Zero-extend convert int to long
8640 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8641 match(Set dst (AndL (ConvI2L src) mask) );
8642 size(4);
8643 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8644 opcode(Assembler::srl_op3, Assembler::arith_op);
8645 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8646 ins_pipe(ialu_reg_reg);
8647 %}
8648
8649 // Zero-extend long
8650 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8651 match(Set dst (AndL src mask) );
8652 size(4);
8653 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8654 opcode(Assembler::srl_op3, Assembler::arith_op);
8655 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8656 ins_pipe(ialu_reg_reg);
8657 %}
8658
8659
8660 //-----------
8661 // Long to Double conversion using V8 opcodes.
8662 // Still useful because cheetah traps and becomes
8663 // amazingly slow for some common numbers.
8664
8665 // Magic constant, 0x43300000
8666 instruct loadConI_x43300000(iRegI dst) %{
8667 effect(DEF dst);
8668 size(4);
8669 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8670 ins_encode(SetHi22(0x43300000, dst));
8671 ins_pipe(ialu_none);
8672 %}
8673
8674 // Magic constant, 0x41f00000
8675 instruct loadConI_x41f00000(iRegI dst) %{
8676 effect(DEF dst);
8677 size(4);
8678 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8679 ins_encode(SetHi22(0x41f00000, dst));
8680 ins_pipe(ialu_none);
8681 %}
8682
8683 // Construct a double from two float halves
8684 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8685 effect(DEF dst, USE src1, USE src2);
8686 size(8);
8687 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8688 "FMOVS $src2.lo,$dst.lo" %}
8689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8690 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8691 ins_pipe(faddD_reg_reg);
8692 %}
8693
8694 // Convert integer in high half of a double register (in the lower half of
8695 // the double register file) to double
8696 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8697 effect(DEF dst, USE src);
8698 size(4);
8699 format %{ "FITOD $src,$dst" %}
8700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8701 ins_encode(form3_opf_rs2D_rdD(src, dst));
8702 ins_pipe(fcvtLHi2D);
8703 %}
8704
8705 // Add float double precision
8706 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8707 effect(DEF dst, USE src1, USE src2);
8708 size(4);
8709 format %{ "FADDD $src1,$src2,$dst" %}
8710 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8711 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8712 ins_pipe(faddD_reg_reg);
8713 %}
8714
8715 // Sub float double precision
8716 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8717 effect(DEF dst, USE src1, USE src2);
8718 size(4);
8719 format %{ "FSUBD $src1,$src2,$dst" %}
8720 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8721 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8722 ins_pipe(faddD_reg_reg);
8723 %}
8724
8725 // Mul float double precision
8726 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8727 effect(DEF dst, USE src1, USE src2);
8728 size(4);
8729 format %{ "FMULD $src1,$src2,$dst" %}
8730 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8731 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8732 ins_pipe(fmulD_reg_reg);
8733 %}
8734
8735 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8736 match(Set dst (ConvL2D src));
8737 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8738
8739 expand %{
8740 regD_low tmpsrc;
8741 iRegI ix43300000;
8742 iRegI ix41f00000;
8743 stackSlotL lx43300000;
8744 stackSlotL lx41f00000;
8745 regD_low dx43300000;
8746 regD dx41f00000;
8747 regD tmp1;
8748 regD_low tmp2;
8749 regD tmp3;
8750 regD tmp4;
8751
8752 stkL_to_regD(tmpsrc, src);
8753
8754 loadConI_x43300000(ix43300000);
8755 loadConI_x41f00000(ix41f00000);
8756 regI_to_stkLHi(lx43300000, ix43300000);
8757 regI_to_stkLHi(lx41f00000, ix41f00000);
8758 stkL_to_regD(dx43300000, lx43300000);
8759 stkL_to_regD(dx41f00000, lx41f00000);
8760
8761 convI2D_regDHi_regD(tmp1, tmpsrc);
8762 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8763 subD_regD_regD(tmp3, tmp2, dx43300000);
8764 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8765 addD_regD_regD(dst, tmp3, tmp4);
8766 %}
8767 %}
8768
8769 // Long to Double conversion using fast fxtof
8770 instruct convL2D_helper(regD dst, regD tmp) %{
8771 effect(DEF dst, USE tmp);
8772 size(4);
8773 format %{ "FXTOD $tmp,$dst" %}
8774 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8775 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8776 ins_pipe(fcvtL2D);
8777 %}
8778
8779 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8780 predicate(VM_Version::has_fast_fxtof());
8781 match(Set dst (ConvL2D src));
8782 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8783 expand %{
8784 regD tmp;
8785 stkL_to_regD(tmp, src);
8786 convL2D_helper(dst, tmp);
8787 %}
8788 %}
8789
8790 instruct convL2D_reg(regD dst, iRegL src) %{
8791 predicate(UseVIS >= 3);
8792 match(Set dst (ConvL2D src));
8793 expand %{
8794 regD tmp;
8795 MoveL2D_reg_reg(tmp, src);
8796 convL2D_helper(dst, tmp);
8797 %}
8798 %}
8799
8800 // Long to Float conversion using fast fxtof
8801 instruct convL2F_helper(regF dst, regD tmp) %{
8802 effect(DEF dst, USE tmp);
8803 size(4);
8804 format %{ "FXTOS $tmp,$dst" %}
8805 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8806 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8807 ins_pipe(fcvtL2F);
8808 %}
8809
8810 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8811 match(Set dst (ConvL2F src));
8812 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8813 expand %{
8814 regD tmp;
8815 stkL_to_regD(tmp, src);
8816 convL2F_helper(dst, tmp);
8817 %}
8818 %}
8819
8820 instruct convL2F_reg(regF dst, iRegL src) %{
8821 predicate(UseVIS >= 3);
8822 match(Set dst (ConvL2F src));
8823 ins_cost(DEFAULT_COST);
8824 expand %{
8825 regD tmp;
8826 MoveL2D_reg_reg(tmp, src);
8827 convL2F_helper(dst, tmp);
8828 %}
8829 %}
8830
8831 //-----------
8832
8833 instruct convL2I_reg(iRegI dst, iRegL src) %{
8834 match(Set dst (ConvL2I src));
8835 #ifndef _LP64
8836 format %{ "MOV $src.lo,$dst\t! long->int" %}
8837 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8838 ins_pipe(ialu_move_reg_I_to_L);
8839 #else
8840 size(4);
8841 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8842 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8843 ins_pipe(ialu_reg);
8844 #endif
8845 %}
8846
8847 // Register Shift Right Immediate
8848 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8849 match(Set dst (ConvL2I (RShiftL src cnt)));
8850
8851 size(4);
8852 format %{ "SRAX $src,$cnt,$dst" %}
8853 opcode(Assembler::srax_op3, Assembler::arith_op);
8854 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8855 ins_pipe(ialu_reg_imm);
8856 %}
8857
8858 //----------Control Flow Instructions------------------------------------------
8859 // Compare Instructions
8860 // Compare Integers
8861 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8862 match(Set icc (CmpI op1 op2));
8863 effect( DEF icc, USE op1, USE op2 );
8864
8865 size(4);
8866 format %{ "CMP $op1,$op2" %}
8867 opcode(Assembler::subcc_op3, Assembler::arith_op);
8868 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8869 ins_pipe(ialu_cconly_reg_reg);
8870 %}
8871
8872 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8873 match(Set icc (CmpU op1 op2));
8874
8875 size(4);
8876 format %{ "CMP $op1,$op2\t! unsigned" %}
8877 opcode(Assembler::subcc_op3, Assembler::arith_op);
8878 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8879 ins_pipe(ialu_cconly_reg_reg);
8880 %}
8881
8882 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8883 match(Set icc (CmpI op1 op2));
8884 effect( DEF icc, USE op1 );
8885
8886 size(4);
8887 format %{ "CMP $op1,$op2" %}
8888 opcode(Assembler::subcc_op3, Assembler::arith_op);
8889 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8890 ins_pipe(ialu_cconly_reg_imm);
8891 %}
8892
8893 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8894 match(Set icc (CmpI (AndI op1 op2) zero));
8895
8896 size(4);
8897 format %{ "BTST $op2,$op1" %}
8898 opcode(Assembler::andcc_op3, Assembler::arith_op);
8899 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8900 ins_pipe(ialu_cconly_reg_reg_zero);
8901 %}
8902
8903 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8904 match(Set icc (CmpI (AndI op1 op2) zero));
8905
8906 size(4);
8907 format %{ "BTST $op2,$op1" %}
8908 opcode(Assembler::andcc_op3, Assembler::arith_op);
8909 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8910 ins_pipe(ialu_cconly_reg_imm_zero);
8911 %}
8912
8913 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8914 match(Set xcc (CmpL op1 op2));
8915 effect( DEF xcc, USE op1, USE op2 );
8916
8917 size(4);
8918 format %{ "CMP $op1,$op2\t\t! long" %}
8919 opcode(Assembler::subcc_op3, Assembler::arith_op);
8920 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8921 ins_pipe(ialu_cconly_reg_reg);
8922 %}
8923
8924 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8925 match(Set xcc (CmpL op1 con));
8926 effect( DEF xcc, USE op1, USE con );
8927
8928 size(4);
8929 format %{ "CMP $op1,$con\t\t! long" %}
8930 opcode(Assembler::subcc_op3, Assembler::arith_op);
8931 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8932 ins_pipe(ialu_cconly_reg_reg);
8933 %}
8934
8935 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8936 match(Set xcc (CmpL (AndL op1 op2) zero));
8937 effect( DEF xcc, USE op1, USE op2 );
8938
8939 size(4);
8940 format %{ "BTST $op1,$op2\t\t! long" %}
8941 opcode(Assembler::andcc_op3, Assembler::arith_op);
8942 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8943 ins_pipe(ialu_cconly_reg_reg);
8944 %}
8945
8946 // useful for checking the alignment of a pointer:
8947 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8948 match(Set xcc (CmpL (AndL op1 con) zero));
8949 effect( DEF xcc, USE op1, USE con );
8950
8951 size(4);
8952 format %{ "BTST $op1,$con\t\t! long" %}
8953 opcode(Assembler::andcc_op3, Assembler::arith_op);
8954 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8955 ins_pipe(ialu_cconly_reg_reg);
8956 %}
8957
8958 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8959 match(Set icc (CmpU op1 op2));
8960
8961 size(4);
8962 format %{ "CMP $op1,$op2\t! unsigned" %}
8963 opcode(Assembler::subcc_op3, Assembler::arith_op);
8964 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8965 ins_pipe(ialu_cconly_reg_imm);
8966 %}
8967
8968 // Compare Pointers
8969 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8970 match(Set pcc (CmpP op1 op2));
8971
8972 size(4);
8973 format %{ "CMP $op1,$op2\t! ptr" %}
8974 opcode(Assembler::subcc_op3, Assembler::arith_op);
8975 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8976 ins_pipe(ialu_cconly_reg_reg);
8977 %}
8978
8979 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8980 match(Set pcc (CmpP op1 op2));
8981
8982 size(4);
8983 format %{ "CMP $op1,$op2\t! ptr" %}
8984 opcode(Assembler::subcc_op3, Assembler::arith_op);
8985 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8986 ins_pipe(ialu_cconly_reg_imm);
8987 %}
8988
8989 // Compare Narrow oops
8990 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8991 match(Set icc (CmpN op1 op2));
8992
8993 size(4);
8994 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8995 opcode(Assembler::subcc_op3, Assembler::arith_op);
8996 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8997 ins_pipe(ialu_cconly_reg_reg);
8998 %}
8999
9000 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9001 match(Set icc (CmpN op1 op2));
9002
9003 size(4);
9004 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9005 opcode(Assembler::subcc_op3, Assembler::arith_op);
9006 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9007 ins_pipe(ialu_cconly_reg_imm);
9008 %}
9009
9010 //----------Max and Min--------------------------------------------------------
9011 // Min Instructions
9012 // Conditional move for min
9013 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9014 effect( USE_DEF op2, USE op1, USE icc );
9015
9016 size(4);
9017 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9018 opcode(Assembler::less);
9019 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9020 ins_pipe(ialu_reg_flags);
9021 %}
9022
9023 // Min Register with Register.
9024 instruct minI_eReg(iRegI op1, iRegI op2) %{
9025 match(Set op2 (MinI op1 op2));
9026 ins_cost(DEFAULT_COST*2);
9027 expand %{
9028 flagsReg icc;
9029 compI_iReg(icc,op1,op2);
9030 cmovI_reg_lt(op2,op1,icc);
9031 %}
9032 %}
9033
9034 // Max Instructions
9035 // Conditional move for max
9036 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9037 effect( USE_DEF op2, USE op1, USE icc );
9038 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9039 opcode(Assembler::greater);
9040 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9041 ins_pipe(ialu_reg_flags);
9042 %}
9043
9044 // Max Register with Register
9045 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9046 match(Set op2 (MaxI op1 op2));
9047 ins_cost(DEFAULT_COST*2);
9048 expand %{
9049 flagsReg icc;
9050 compI_iReg(icc,op1,op2);
9051 cmovI_reg_gt(op2,op1,icc);
9052 %}
9053 %}
9054
9055
9056 //----------Float Compares----------------------------------------------------
9057 // Compare floating, generate condition code
9058 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9059 match(Set fcc (CmpF src1 src2));
9060
9061 size(4);
9062 format %{ "FCMPs $fcc,$src1,$src2" %}
9063 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9064 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9065 ins_pipe(faddF_fcc_reg_reg_zero);
9066 %}
9067
9068 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9069 match(Set fcc (CmpD src1 src2));
9070
9071 size(4);
9072 format %{ "FCMPd $fcc,$src1,$src2" %}
9073 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9074 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9075 ins_pipe(faddD_fcc_reg_reg_zero);
9076 %}
9077
9078
9079 // Compare floating, generate -1,0,1
9080 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9081 match(Set dst (CmpF3 src1 src2));
9082 effect(KILL fcc0);
9083 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9084 format %{ "fcmpl $dst,$src1,$src2" %}
9085 // Primary = float
9086 opcode( true );
9087 ins_encode( floating_cmp( dst, src1, src2 ) );
9088 ins_pipe( floating_cmp );
9089 %}
9090
9091 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9092 match(Set dst (CmpD3 src1 src2));
9093 effect(KILL fcc0);
9094 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9095 format %{ "dcmpl $dst,$src1,$src2" %}
9096 // Primary = double (not float)
9097 opcode( false );
9098 ins_encode( floating_cmp( dst, src1, src2 ) );
9099 ins_pipe( floating_cmp );
9100 %}
9101
9102 //----------Branches---------------------------------------------------------
9103 // Jump
9104 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9105 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9106 match(Jump switch_val);
9107 effect(TEMP table);
9108
9109 ins_cost(350);
9110
9111 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9112 "LD [O7 + $switch_val], O7\n\t"
9113 "JUMP O7" %}
9114 ins_encode %{
9115 // Calculate table address into a register.
9116 Register table_reg;
9117 Register label_reg = O7;
9118 // If we are calculating the size of this instruction don't trust
9119 // zero offsets because they might change when
9120 // MachConstantBaseNode decides to optimize the constant table
9121 // base.
9122 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9123 table_reg = $constanttablebase;
9124 } else {
9125 table_reg = O7;
9126 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9127 __ add($constanttablebase, con_offset, table_reg);
9128 }
9129
9130 // Jump to base address + switch value
9131 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9132 __ jmp(label_reg, G0);
9133 __ delayed()->nop();
9134 %}
9135 ins_pipe(ialu_reg_reg);
9136 %}
9137
9138 // Direct Branch. Use V8 version with longer range.
9139 instruct branch(label labl) %{
9140 match(Goto);
9141 effect(USE labl);
9142
9143 size(8);
9144 ins_cost(BRANCH_COST);
9145 format %{ "BA $labl" %}
9146 ins_encode %{
9147 Label* L = $labl$$label;
9148 __ ba(*L);
9149 __ delayed()->nop();
9150 %}
9151 ins_pipe(br);
9152 %}
9153
9154 // Direct Branch, short with no delay slot
9155 instruct branch_short(label labl) %{
9156 match(Goto);
9157 predicate(UseCBCond);
9158 effect(USE labl);
9159
9160 size(4);
9161 ins_cost(BRANCH_COST);
9162 format %{ "BA $labl\t! short branch" %}
9163 ins_encode %{
9164 Label* L = $labl$$label;
9165 assert(__ use_cbcond(*L), "back to back cbcond");
9166 __ ba_short(*L);
9167 %}
9168 ins_short_branch(1);
9169 ins_avoid_back_to_back(1);
9170 ins_pipe(cbcond_reg_imm);
9171 %}
9172
9173 // Conditional Direct Branch
9174 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9175 match(If cmp icc);
9176 effect(USE labl);
9177
9178 size(8);
9179 ins_cost(BRANCH_COST);
9180 format %{ "BP$cmp $icc,$labl" %}
9181 // Prim = bits 24-22, Secnd = bits 31-30
9182 ins_encode( enc_bp( labl, cmp, icc ) );
9183 ins_pipe(br_cc);
9184 %}
9185
9186 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9187 match(If cmp icc);
9188 effect(USE labl);
9189
9190 ins_cost(BRANCH_COST);
9191 format %{ "BP$cmp $icc,$labl" %}
9192 // Prim = bits 24-22, Secnd = bits 31-30
9193 ins_encode( enc_bp( labl, cmp, icc ) );
9194 ins_pipe(br_cc);
9195 %}
9196
9197 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9198 match(If cmp pcc);
9199 effect(USE labl);
9200
9201 size(8);
9202 ins_cost(BRANCH_COST);
9203 format %{ "BP$cmp $pcc,$labl" %}
9204 ins_encode %{
9205 Label* L = $labl$$label;
9206 Assembler::Predict predict_taken =
9207 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9208
9209 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9210 __ delayed()->nop();
9211 %}
9212 ins_pipe(br_cc);
9213 %}
9214
9215 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9216 match(If cmp fcc);
9217 effect(USE labl);
9218
9219 size(8);
9220 ins_cost(BRANCH_COST);
9221 format %{ "FBP$cmp $fcc,$labl" %}
9222 ins_encode %{
9223 Label* L = $labl$$label;
9224 Assembler::Predict predict_taken =
9225 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9226
9227 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9228 __ delayed()->nop();
9229 %}
9230 ins_pipe(br_fcc);
9231 %}
9232
9233 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9234 match(CountedLoopEnd cmp icc);
9235 effect(USE labl);
9236
9237 size(8);
9238 ins_cost(BRANCH_COST);
9239 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9240 // Prim = bits 24-22, Secnd = bits 31-30
9241 ins_encode( enc_bp( labl, cmp, icc ) );
9242 ins_pipe(br_cc);
9243 %}
9244
9245 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9246 match(CountedLoopEnd cmp icc);
9247 effect(USE labl);
9248
9249 size(8);
9250 ins_cost(BRANCH_COST);
9251 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9252 // Prim = bits 24-22, Secnd = bits 31-30
9253 ins_encode( enc_bp( labl, cmp, icc ) );
9254 ins_pipe(br_cc);
9255 %}
9256
9257 // Compare and branch instructions
9258 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9259 match(If cmp (CmpI op1 op2));
9260 effect(USE labl, KILL icc);
9261
9262 size(12);
9263 ins_cost(BRANCH_COST);
9264 format %{ "CMP $op1,$op2\t! int\n\t"
9265 "BP$cmp $labl" %}
9266 ins_encode %{
9267 Label* L = $labl$$label;
9268 Assembler::Predict predict_taken =
9269 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9270 __ cmp($op1$$Register, $op2$$Register);
9271 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9272 __ delayed()->nop();
9273 %}
9274 ins_pipe(cmp_br_reg_reg);
9275 %}
9276
9277 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9278 match(If cmp (CmpI op1 op2));
9279 effect(USE labl, KILL icc);
9280
9281 size(12);
9282 ins_cost(BRANCH_COST);
9283 format %{ "CMP $op1,$op2\t! int\n\t"
9284 "BP$cmp $labl" %}
9285 ins_encode %{
9286 Label* L = $labl$$label;
9287 Assembler::Predict predict_taken =
9288 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9289 __ cmp($op1$$Register, $op2$$constant);
9290 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9291 __ delayed()->nop();
9292 %}
9293 ins_pipe(cmp_br_reg_imm);
9294 %}
9295
9296 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9297 match(If cmp (CmpU op1 op2));
9298 effect(USE labl, KILL icc);
9299
9300 size(12);
9301 ins_cost(BRANCH_COST);
9302 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9303 "BP$cmp $labl" %}
9304 ins_encode %{
9305 Label* L = $labl$$label;
9306 Assembler::Predict predict_taken =
9307 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9308 __ cmp($op1$$Register, $op2$$Register);
9309 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9310 __ delayed()->nop();
9311 %}
9312 ins_pipe(cmp_br_reg_reg);
9313 %}
9314
9315 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9316 match(If cmp (CmpU op1 op2));
9317 effect(USE labl, KILL icc);
9318
9319 size(12);
9320 ins_cost(BRANCH_COST);
9321 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9322 "BP$cmp $labl" %}
9323 ins_encode %{
9324 Label* L = $labl$$label;
9325 Assembler::Predict predict_taken =
9326 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9327 __ cmp($op1$$Register, $op2$$constant);
9328 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9329 __ delayed()->nop();
9330 %}
9331 ins_pipe(cmp_br_reg_imm);
9332 %}
9333
9334 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9335 match(If cmp (CmpL op1 op2));
9336 effect(USE labl, KILL xcc);
9337
9338 size(12);
9339 ins_cost(BRANCH_COST);
9340 format %{ "CMP $op1,$op2\t! long\n\t"
9341 "BP$cmp $labl" %}
9342 ins_encode %{
9343 Label* L = $labl$$label;
9344 Assembler::Predict predict_taken =
9345 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9346 __ cmp($op1$$Register, $op2$$Register);
9347 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9348 __ delayed()->nop();
9349 %}
9350 ins_pipe(cmp_br_reg_reg);
9351 %}
9352
9353 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9354 match(If cmp (CmpL op1 op2));
9355 effect(USE labl, KILL xcc);
9356
9357 size(12);
9358 ins_cost(BRANCH_COST);
9359 format %{ "CMP $op1,$op2\t! long\n\t"
9360 "BP$cmp $labl" %}
9361 ins_encode %{
9362 Label* L = $labl$$label;
9363 Assembler::Predict predict_taken =
9364 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9365 __ cmp($op1$$Register, $op2$$constant);
9366 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9367 __ delayed()->nop();
9368 %}
9369 ins_pipe(cmp_br_reg_imm);
9370 %}
9371
9372 // Compare Pointers and branch
9373 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9374 match(If cmp (CmpP op1 op2));
9375 effect(USE labl, KILL pcc);
9376
9377 size(12);
9378 ins_cost(BRANCH_COST);
9379 format %{ "CMP $op1,$op2\t! ptr\n\t"
9380 "B$cmp $labl" %}
9381 ins_encode %{
9382 Label* L = $labl$$label;
9383 Assembler::Predict predict_taken =
9384 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9385 __ cmp($op1$$Register, $op2$$Register);
9386 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9387 __ delayed()->nop();
9388 %}
9389 ins_pipe(cmp_br_reg_reg);
9390 %}
9391
9392 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9393 match(If cmp (CmpP op1 null));
9394 effect(USE labl, KILL pcc);
9395
9396 size(12);
9397 ins_cost(BRANCH_COST);
9398 format %{ "CMP $op1,0\t! ptr\n\t"
9399 "B$cmp $labl" %}
9400 ins_encode %{
9401 Label* L = $labl$$label;
9402 Assembler::Predict predict_taken =
9403 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9404 __ cmp($op1$$Register, G0);
9405 // bpr() is not used here since it has shorter distance.
9406 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9407 __ delayed()->nop();
9408 %}
9409 ins_pipe(cmp_br_reg_reg);
9410 %}
9411
9412 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9413 match(If cmp (CmpN op1 op2));
9414 effect(USE labl, KILL icc);
9415
9416 size(12);
9417 ins_cost(BRANCH_COST);
9418 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9419 "BP$cmp $labl" %}
9420 ins_encode %{
9421 Label* L = $labl$$label;
9422 Assembler::Predict predict_taken =
9423 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9424 __ cmp($op1$$Register, $op2$$Register);
9425 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9426 __ delayed()->nop();
9427 %}
9428 ins_pipe(cmp_br_reg_reg);
9429 %}
9430
9431 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9432 match(If cmp (CmpN op1 null));
9433 effect(USE labl, KILL icc);
9434
9435 size(12);
9436 ins_cost(BRANCH_COST);
9437 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9438 "BP$cmp $labl" %}
9439 ins_encode %{
9440 Label* L = $labl$$label;
9441 Assembler::Predict predict_taken =
9442 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9443 __ cmp($op1$$Register, G0);
9444 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9445 __ delayed()->nop();
9446 %}
9447 ins_pipe(cmp_br_reg_reg);
9448 %}
9449
9450 // Loop back branch
9451 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9452 match(CountedLoopEnd cmp (CmpI op1 op2));
9453 effect(USE labl, KILL icc);
9454
9455 size(12);
9456 ins_cost(BRANCH_COST);
9457 format %{ "CMP $op1,$op2\t! int\n\t"
9458 "BP$cmp $labl\t! Loop end" %}
9459 ins_encode %{
9460 Label* L = $labl$$label;
9461 Assembler::Predict predict_taken =
9462 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9463 __ cmp($op1$$Register, $op2$$Register);
9464 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9465 __ delayed()->nop();
9466 %}
9467 ins_pipe(cmp_br_reg_reg);
9468 %}
9469
9470 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9471 match(CountedLoopEnd cmp (CmpI op1 op2));
9472 effect(USE labl, KILL icc);
9473
9474 size(12);
9475 ins_cost(BRANCH_COST);
9476 format %{ "CMP $op1,$op2\t! int\n\t"
9477 "BP$cmp $labl\t! Loop end" %}
9478 ins_encode %{
9479 Label* L = $labl$$label;
9480 Assembler::Predict predict_taken =
9481 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9482 __ cmp($op1$$Register, $op2$$constant);
9483 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9484 __ delayed()->nop();
9485 %}
9486 ins_pipe(cmp_br_reg_imm);
9487 %}
9488
9489 // Short compare and branch instructions
9490 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9491 match(If cmp (CmpI op1 op2));
9492 predicate(UseCBCond);
9493 effect(USE labl, KILL icc);
9494
9495 size(4);
9496 ins_cost(BRANCH_COST);
9497 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9498 ins_encode %{
9499 Label* L = $labl$$label;
9500 assert(__ use_cbcond(*L), "back to back cbcond");
9501 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9502 %}
9503 ins_short_branch(1);
9504 ins_avoid_back_to_back(1);
9505 ins_pipe(cbcond_reg_reg);
9506 %}
9507
9508 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9509 match(If cmp (CmpI op1 op2));
9510 predicate(UseCBCond);
9511 effect(USE labl, KILL icc);
9512
9513 size(4);
9514 ins_cost(BRANCH_COST);
9515 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9516 ins_encode %{
9517 Label* L = $labl$$label;
9518 assert(__ use_cbcond(*L), "back to back cbcond");
9519 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9520 %}
9521 ins_short_branch(1);
9522 ins_avoid_back_to_back(1);
9523 ins_pipe(cbcond_reg_imm);
9524 %}
9525
9526 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9527 match(If cmp (CmpU op1 op2));
9528 predicate(UseCBCond);
9529 effect(USE labl, KILL icc);
9530
9531 size(4);
9532 ins_cost(BRANCH_COST);
9533 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9534 ins_encode %{
9535 Label* L = $labl$$label;
9536 assert(__ use_cbcond(*L), "back to back cbcond");
9537 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9538 %}
9539 ins_short_branch(1);
9540 ins_avoid_back_to_back(1);
9541 ins_pipe(cbcond_reg_reg);
9542 %}
9543
9544 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9545 match(If cmp (CmpU op1 op2));
9546 predicate(UseCBCond);
9547 effect(USE labl, KILL icc);
9548
9549 size(4);
9550 ins_cost(BRANCH_COST);
9551 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9552 ins_encode %{
9553 Label* L = $labl$$label;
9554 assert(__ use_cbcond(*L), "back to back cbcond");
9555 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9556 %}
9557 ins_short_branch(1);
9558 ins_avoid_back_to_back(1);
9559 ins_pipe(cbcond_reg_imm);
9560 %}
9561
9562 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9563 match(If cmp (CmpL op1 op2));
9564 predicate(UseCBCond);
9565 effect(USE labl, KILL xcc);
9566
9567 size(4);
9568 ins_cost(BRANCH_COST);
9569 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9570 ins_encode %{
9571 Label* L = $labl$$label;
9572 assert(__ use_cbcond(*L), "back to back cbcond");
9573 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9574 %}
9575 ins_short_branch(1);
9576 ins_avoid_back_to_back(1);
9577 ins_pipe(cbcond_reg_reg);
9578 %}
9579
9580 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9581 match(If cmp (CmpL op1 op2));
9582 predicate(UseCBCond);
9583 effect(USE labl, KILL xcc);
9584
9585 size(4);
9586 ins_cost(BRANCH_COST);
9587 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9588 ins_encode %{
9589 Label* L = $labl$$label;
9590 assert(__ use_cbcond(*L), "back to back cbcond");
9591 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9592 %}
9593 ins_short_branch(1);
9594 ins_avoid_back_to_back(1);
9595 ins_pipe(cbcond_reg_imm);
9596 %}
9597
9598 // Compare Pointers and branch
9599 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9600 match(If cmp (CmpP op1 op2));
9601 predicate(UseCBCond);
9602 effect(USE labl, KILL pcc);
9603
9604 size(4);
9605 ins_cost(BRANCH_COST);
9606 #ifdef _LP64
9607 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9608 #else
9609 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9610 #endif
9611 ins_encode %{
9612 Label* L = $labl$$label;
9613 assert(__ use_cbcond(*L), "back to back cbcond");
9614 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9615 %}
9616 ins_short_branch(1);
9617 ins_avoid_back_to_back(1);
9618 ins_pipe(cbcond_reg_reg);
9619 %}
9620
9621 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9622 match(If cmp (CmpP op1 null));
9623 predicate(UseCBCond);
9624 effect(USE labl, KILL pcc);
9625
9626 size(4);
9627 ins_cost(BRANCH_COST);
9628 #ifdef _LP64
9629 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9630 #else
9631 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9632 #endif
9633 ins_encode %{
9634 Label* L = $labl$$label;
9635 assert(__ use_cbcond(*L), "back to back cbcond");
9636 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9637 %}
9638 ins_short_branch(1);
9639 ins_avoid_back_to_back(1);
9640 ins_pipe(cbcond_reg_reg);
9641 %}
9642
9643 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9644 match(If cmp (CmpN op1 op2));
9645 predicate(UseCBCond);
9646 effect(USE labl, KILL icc);
9647
9648 size(4);
9649 ins_cost(BRANCH_COST);
9650 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9651 ins_encode %{
9652 Label* L = $labl$$label;
9653 assert(__ use_cbcond(*L), "back to back cbcond");
9654 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9655 %}
9656 ins_short_branch(1);
9657 ins_avoid_back_to_back(1);
9658 ins_pipe(cbcond_reg_reg);
9659 %}
9660
9661 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9662 match(If cmp (CmpN op1 null));
9663 predicate(UseCBCond);
9664 effect(USE labl, KILL icc);
9665
9666 size(4);
9667 ins_cost(BRANCH_COST);
9668 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9669 ins_encode %{
9670 Label* L = $labl$$label;
9671 assert(__ use_cbcond(*L), "back to back cbcond");
9672 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9673 %}
9674 ins_short_branch(1);
9675 ins_avoid_back_to_back(1);
9676 ins_pipe(cbcond_reg_reg);
9677 %}
9678
9679 // Loop back branch
9680 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9681 match(CountedLoopEnd cmp (CmpI op1 op2));
9682 predicate(UseCBCond);
9683 effect(USE labl, KILL icc);
9684
9685 size(4);
9686 ins_cost(BRANCH_COST);
9687 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9688 ins_encode %{
9689 Label* L = $labl$$label;
9690 assert(__ use_cbcond(*L), "back to back cbcond");
9691 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9692 %}
9693 ins_short_branch(1);
9694 ins_avoid_back_to_back(1);
9695 ins_pipe(cbcond_reg_reg);
9696 %}
9697
9698 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9699 match(CountedLoopEnd cmp (CmpI op1 op2));
9700 predicate(UseCBCond);
9701 effect(USE labl, KILL icc);
9702
9703 size(4);
9704 ins_cost(BRANCH_COST);
9705 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9706 ins_encode %{
9707 Label* L = $labl$$label;
9708 assert(__ use_cbcond(*L), "back to back cbcond");
9709 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9710 %}
9711 ins_short_branch(1);
9712 ins_avoid_back_to_back(1);
9713 ins_pipe(cbcond_reg_imm);
9714 %}
9715
9716 // Branch-on-register tests all 64 bits. We assume that values
9717 // in 64-bit registers always remains zero or sign extended
9718 // unless our code munges the high bits. Interrupts can chop
9719 // the high order bits to zero or sign at any time.
9720 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9721 match(If cmp (CmpI op1 zero));
9722 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9723 effect(USE labl);
9724
9725 size(8);
9726 ins_cost(BRANCH_COST);
9727 format %{ "BR$cmp $op1,$labl" %}
9728 ins_encode( enc_bpr( labl, cmp, op1 ) );
9729 ins_pipe(br_reg);
9730 %}
9731
9732 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9733 match(If cmp (CmpP op1 null));
9734 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9735 effect(USE labl);
9736
9737 size(8);
9738 ins_cost(BRANCH_COST);
9739 format %{ "BR$cmp $op1,$labl" %}
9740 ins_encode( enc_bpr( labl, cmp, op1 ) );
9741 ins_pipe(br_reg);
9742 %}
9743
9744 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9745 match(If cmp (CmpL op1 zero));
9746 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9747 effect(USE labl);
9748
9749 size(8);
9750 ins_cost(BRANCH_COST);
9751 format %{ "BR$cmp $op1,$labl" %}
9752 ins_encode( enc_bpr( labl, cmp, op1 ) );
9753 ins_pipe(br_reg);
9754 %}
9755
9756
9757 // ============================================================================
9758 // Long Compare
9759 //
9760 // Currently we hold longs in 2 registers. Comparing such values efficiently
9761 // is tricky. The flavor of compare used depends on whether we are testing
9762 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9763 // The GE test is the negated LT test. The LE test can be had by commuting
9764 // the operands (yielding a GE test) and then negating; negate again for the
9765 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9766 // NE test is negated from that.
9767
9768 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9769 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9770 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9771 // are collapsed internally in the ADLC's dfa-gen code. The match for
9772 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9773 // foo match ends up with the wrong leaf. One fix is to not match both
9774 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9775 // both forms beat the trinary form of long-compare and both are very useful
9776 // on Intel which has so few registers.
9777
9778 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9779 match(If cmp xcc);
9780 effect(USE labl);
9781
9782 size(8);
9783 ins_cost(BRANCH_COST);
9784 format %{ "BP$cmp $xcc,$labl" %}
9785 ins_encode %{
9786 Label* L = $labl$$label;
9787 Assembler::Predict predict_taken =
9788 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9789
9790 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9791 __ delayed()->nop();
9792 %}
9793 ins_pipe(br_cc);
9794 %}
9795
9796 // Manifest a CmpL3 result in an integer register. Very painful.
9797 // This is the test to avoid.
9798 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9799 match(Set dst (CmpL3 src1 src2) );
9800 effect( KILL ccr );
9801 ins_cost(6*DEFAULT_COST);
9802 size(24);
9803 format %{ "CMP $src1,$src2\t\t! long\n"
9804 "\tBLT,a,pn done\n"
9805 "\tMOV -1,$dst\t! delay slot\n"
9806 "\tBGT,a,pn done\n"
9807 "\tMOV 1,$dst\t! delay slot\n"
9808 "\tCLR $dst\n"
9809 "done:" %}
9810 ins_encode( cmpl_flag(src1,src2,dst) );
9811 ins_pipe(cmpL_reg);
9812 %}
9813
9814 // Conditional move
9815 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9816 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9817 ins_cost(150);
9818 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9819 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9820 ins_pipe(ialu_reg);
9821 %}
9822
9823 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9824 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9825 ins_cost(140);
9826 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9827 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9828 ins_pipe(ialu_imm);
9829 %}
9830
9831 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9832 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9833 ins_cost(150);
9834 format %{ "MOV$cmp $xcc,$src,$dst" %}
9835 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9836 ins_pipe(ialu_reg);
9837 %}
9838
9839 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9840 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9841 ins_cost(140);
9842 format %{ "MOV$cmp $xcc,$src,$dst" %}
9843 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9844 ins_pipe(ialu_imm);
9845 %}
9846
9847 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9848 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9849 ins_cost(150);
9850 format %{ "MOV$cmp $xcc,$src,$dst" %}
9851 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9852 ins_pipe(ialu_reg);
9853 %}
9854
9855 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9856 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9857 ins_cost(150);
9858 format %{ "MOV$cmp $xcc,$src,$dst" %}
9859 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9860 ins_pipe(ialu_reg);
9861 %}
9862
9863 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9864 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9865 ins_cost(140);
9866 format %{ "MOV$cmp $xcc,$src,$dst" %}
9867 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9868 ins_pipe(ialu_imm);
9869 %}
9870
9871 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9872 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9873 ins_cost(150);
9874 opcode(0x101);
9875 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9876 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9877 ins_pipe(int_conditional_float_move);
9878 %}
9879
9880 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9881 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9882 ins_cost(150);
9883 opcode(0x102);
9884 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9885 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9886 ins_pipe(int_conditional_float_move);
9887 %}
9888
9889 // ============================================================================
9890 // Safepoint Instruction
9891 instruct safePoint_poll(iRegP poll) %{
9892 match(SafePoint poll);
9893 effect(USE poll);
9894
9895 size(4);
9896 #ifdef _LP64
9897 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9898 #else
9899 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9900 #endif
9901 ins_encode %{
9902 __ relocate(relocInfo::poll_type);
9903 __ ld_ptr($poll$$Register, 0, G0);
9904 %}
9905 ins_pipe(loadPollP);
9906 %}
9907
9908 // ============================================================================
9909 // Call Instructions
9910 // Call Java Static Instruction
9911 instruct CallStaticJavaDirect( method meth ) %{
9912 match(CallStaticJava);
9913 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9914 effect(USE meth);
9915
9916 size(8);
9917 ins_cost(CALL_COST);
9918 format %{ "CALL,static ; NOP ==> " %}
9919 ins_encode( Java_Static_Call( meth ), call_epilog );
9920 ins_pipe(simple_call);
9921 %}
9922
9923 // Call Java Static Instruction (method handle version)
9924 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9925 match(CallStaticJava);
9926 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9927 effect(USE meth, KILL l7_mh_SP_save);
9928
9929 size(16);
9930 ins_cost(CALL_COST);
9931 format %{ "CALL,static/MethodHandle" %}
9932 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9933 ins_pipe(simple_call);
9934 %}
9935
9936 // Call Java Dynamic Instruction
9937 instruct CallDynamicJavaDirect( method meth ) %{
9938 match(CallDynamicJava);
9939 effect(USE meth);
9940
9941 ins_cost(CALL_COST);
9942 format %{ "SET (empty),R_G5\n\t"
9943 "CALL,dynamic ; NOP ==> " %}
9944 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9945 ins_pipe(call);
9946 %}
9947
9948 // Call Runtime Instruction
9949 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9950 match(CallRuntime);
9951 effect(USE meth, KILL l7);
9952 ins_cost(CALL_COST);
9953 format %{ "CALL,runtime" %}
9954 ins_encode( Java_To_Runtime( meth ),
9955 call_epilog, adjust_long_from_native_call );
9956 ins_pipe(simple_call);
9957 %}
9958
9959 // Call runtime without safepoint - same as CallRuntime
9960 instruct CallLeafDirect(method meth, l7RegP l7) %{
9961 match(CallLeaf);
9962 effect(USE meth, KILL l7);
9963 ins_cost(CALL_COST);
9964 format %{ "CALL,runtime leaf" %}
9965 ins_encode( Java_To_Runtime( meth ),
9966 call_epilog,
9967 adjust_long_from_native_call );
9968 ins_pipe(simple_call);
9969 %}
9970
9971 // Call runtime without safepoint - same as CallLeaf
9972 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9973 match(CallLeafNoFP);
9974 effect(USE meth, KILL l7);
9975 ins_cost(CALL_COST);
9976 format %{ "CALL,runtime leaf nofp" %}
9977 ins_encode( Java_To_Runtime( meth ),
9978 call_epilog,
9979 adjust_long_from_native_call );
9980 ins_pipe(simple_call);
9981 %}
9982
9983 // Tail Call; Jump from runtime stub to Java code.
9984 // Also known as an 'interprocedural jump'.
9985 // Target of jump will eventually return to caller.
9986 // TailJump below removes the return address.
9987 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9988 match(TailCall jump_target method_oop );
9989
9990 ins_cost(CALL_COST);
9991 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9992 ins_encode(form_jmpl(jump_target));
9993 ins_pipe(tail_call);
9994 %}
9995
9996
9997 // Return Instruction
9998 instruct Ret() %{
9999 match(Return);
10000
10001 // The epilogue node did the ret already.
10002 size(0);
10003 format %{ "! return" %}
10004 ins_encode();
10005 ins_pipe(empty);
10006 %}
10007
10008
10009 // Tail Jump; remove the return address; jump to target.
10010 // TailCall above leaves the return address around.
10011 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10012 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10013 // "restore" before this instruction (in Epilogue), we need to materialize it
10014 // in %i0.
10015 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10016 match( TailJump jump_target ex_oop );
10017 ins_cost(CALL_COST);
10018 format %{ "! discard R_O7\n\t"
10019 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10020 ins_encode(form_jmpl_set_exception_pc(jump_target));
10021 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10022 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10023 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10024 ins_pipe(tail_call);
10025 %}
10026
10027 // Create exception oop: created by stack-crawling runtime code.
10028 // Created exception is now available to this handler, and is setup
10029 // just prior to jumping to this handler. No code emitted.
10030 instruct CreateException( o0RegP ex_oop )
10031 %{
10032 match(Set ex_oop (CreateEx));
10033 ins_cost(0);
10034
10035 size(0);
10036 // use the following format syntax
10037 format %{ "! exception oop is in R_O0; no code emitted" %}
10038 ins_encode();
10039 ins_pipe(empty);
10040 %}
10041
10042
10043 // Rethrow exception:
10044 // The exception oop will come in the first argument position.
10045 // Then JUMP (not call) to the rethrow stub code.
10046 instruct RethrowException()
10047 %{
10048 match(Rethrow);
10049 ins_cost(CALL_COST);
10050
10051 // use the following format syntax
10052 format %{ "Jmp rethrow_stub" %}
10053 ins_encode(enc_rethrow);
10054 ins_pipe(tail_call);
10055 %}
10056
10057
10058 // Die now
10059 instruct ShouldNotReachHere( )
10060 %{
10061 match(Halt);
10062 ins_cost(CALL_COST);
10063
10064 size(4);
10065 // Use the following format syntax
10066 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10067 ins_encode( form2_illtrap() );
10068 ins_pipe(tail_call);
10069 %}
10070
10071 // ============================================================================
10072 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10073 // array for an instance of the superklass. Set a hidden internal cache on a
10074 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10075 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10076 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10077 match(Set index (PartialSubtypeCheck sub super));
10078 effect( KILL pcc, KILL o7 );
10079 ins_cost(DEFAULT_COST*10);
10080 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10081 ins_encode( enc_PartialSubtypeCheck() );
10082 ins_pipe(partial_subtype_check_pipe);
10083 %}
10084
10085 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10086 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10087 effect( KILL idx, KILL o7 );
10088 ins_cost(DEFAULT_COST*10);
10089 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10090 ins_encode( enc_PartialSubtypeCheck() );
10091 ins_pipe(partial_subtype_check_pipe);
10092 %}
10093
10094
10095 // ============================================================================
10096 // inlined locking and unlocking
10097
10098 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10099 match(Set pcc (FastLock object box));
10100
10101 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10102 ins_cost(100);
10103
10104 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10105 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10106 ins_pipe(long_memory_op);
10107 %}
10108
10109
10110 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10111 match(Set pcc (FastUnlock object box));
10112 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10113 ins_cost(100);
10114
10115 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10116 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10117 ins_pipe(long_memory_op);
10118 %}
10119
10120 // The encodings are generic.
10121 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10122 predicate(!use_block_zeroing(n->in(2)) );
10123 match(Set dummy (ClearArray cnt base));
10124 effect(TEMP temp, KILL ccr);
10125 ins_cost(300);
10126 format %{ "MOV $cnt,$temp\n"
10127 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10128 " BRge loop\t\t! Clearing loop\n"
10129 " STX G0,[$base+$temp]\t! delay slot" %}
10130
10131 ins_encode %{
10132 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10133 Register nof_bytes_arg = $cnt$$Register;
10134 Register nof_bytes_tmp = $temp$$Register;
10135 Register base_pointer_arg = $base$$Register;
10136
10137 Label loop;
10138 __ mov(nof_bytes_arg, nof_bytes_tmp);
10139
10140 // Loop and clear, walking backwards through the array.
10141 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10142 __ bind(loop);
10143 __ deccc(nof_bytes_tmp, 8);
10144 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10145 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10146 // %%%% this mini-loop must not cross a cache boundary!
10147 %}
10148 ins_pipe(long_memory_op);
10149 %}
10150
10151 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10152 predicate(use_block_zeroing(n->in(2)));
10153 match(Set dummy (ClearArray cnt base));
10154 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10155 ins_cost(300);
10156 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10157
10158 ins_encode %{
10159
10160 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10161 Register to = $base$$Register;
10162 Register count = $cnt$$Register;
10163
10164 Label Ldone;
10165 __ nop(); // Separate short branches
10166 // Use BIS for zeroing (temp is not used).
10167 __ bis_zeroing(to, count, G0, Ldone);
10168 __ bind(Ldone);
10169
10170 %}
10171 ins_pipe(long_memory_op);
10172 %}
10173
10174 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10175 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10176 match(Set dummy (ClearArray cnt base));
10177 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10178 ins_cost(300);
10179 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10180
10181 ins_encode %{
10182
10183 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10184 Register to = $base$$Register;
10185 Register count = $cnt$$Register;
10186 Register temp = $tmp$$Register;
10187
10188 Label Ldone;
10189 __ nop(); // Separate short branches
10190 // Use BIS for zeroing
10191 __ bis_zeroing(to, count, temp, Ldone);
10192 __ bind(Ldone);
10193
10194 %}
10195 ins_pipe(long_memory_op);
10196 %}
10197
10198 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10199 o7RegI tmp, flagsReg ccr) %{
10200 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10201 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10202 ins_cost(300);
10203 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10204 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10205 ins_pipe(long_memory_op);
10206 %}
10207
10208 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10209 o7RegI tmp, flagsReg ccr) %{
10210 match(Set result (StrEquals (Binary str1 str2) cnt));
10211 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10212 ins_cost(300);
10213 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10214 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10215 ins_pipe(long_memory_op);
10216 %}
10217
10218 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10219 o7RegI tmp2, flagsReg ccr) %{
10220 match(Set result (AryEq ary1 ary2));
10221 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10222 ins_cost(300);
10223 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10224 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10225 ins_pipe(long_memory_op);
10226 %}
10227
10228
10229 //---------- Zeros Count Instructions ------------------------------------------
10230
10231 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10232 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10233 match(Set dst (CountLeadingZerosI src));
10234 effect(TEMP dst, TEMP tmp, KILL cr);
10235
10236 // x |= (x >> 1);
10237 // x |= (x >> 2);
10238 // x |= (x >> 4);
10239 // x |= (x >> 8);
10240 // x |= (x >> 16);
10241 // return (WORDBITS - popc(x));
10242 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10243 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10244 "OR $dst,$tmp,$dst\n\t"
10245 "SRL $dst,2,$tmp\n\t"
10246 "OR $dst,$tmp,$dst\n\t"
10247 "SRL $dst,4,$tmp\n\t"
10248 "OR $dst,$tmp,$dst\n\t"
10249 "SRL $dst,8,$tmp\n\t"
10250 "OR $dst,$tmp,$dst\n\t"
10251 "SRL $dst,16,$tmp\n\t"
10252 "OR $dst,$tmp,$dst\n\t"
10253 "POPC $dst,$dst\n\t"
10254 "MOV 32,$tmp\n\t"
10255 "SUB $tmp,$dst,$dst" %}
10256 ins_encode %{
10257 Register Rdst = $dst$$Register;
10258 Register Rsrc = $src$$Register;
10259 Register Rtmp = $tmp$$Register;
10260 __ srl(Rsrc, 1, Rtmp);
10261 __ srl(Rsrc, 0, Rdst);
10262 __ or3(Rdst, Rtmp, Rdst);
10263 __ srl(Rdst, 2, Rtmp);
10264 __ or3(Rdst, Rtmp, Rdst);
10265 __ srl(Rdst, 4, Rtmp);
10266 __ or3(Rdst, Rtmp, Rdst);
10267 __ srl(Rdst, 8, Rtmp);
10268 __ or3(Rdst, Rtmp, Rdst);
10269 __ srl(Rdst, 16, Rtmp);
10270 __ or3(Rdst, Rtmp, Rdst);
10271 __ popc(Rdst, Rdst);
10272 __ mov(BitsPerInt, Rtmp);
10273 __ sub(Rtmp, Rdst, Rdst);
10274 %}
10275 ins_pipe(ialu_reg);
10276 %}
10277
10278 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10279 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10280 match(Set dst (CountLeadingZerosL src));
10281 effect(TEMP dst, TEMP tmp, KILL cr);
10282
10283 // x |= (x >> 1);
10284 // x |= (x >> 2);
10285 // x |= (x >> 4);
10286 // x |= (x >> 8);
10287 // x |= (x >> 16);
10288 // x |= (x >> 32);
10289 // return (WORDBITS - popc(x));
10290 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10291 "OR $src,$tmp,$dst\n\t"
10292 "SRLX $dst,2,$tmp\n\t"
10293 "OR $dst,$tmp,$dst\n\t"
10294 "SRLX $dst,4,$tmp\n\t"
10295 "OR $dst,$tmp,$dst\n\t"
10296 "SRLX $dst,8,$tmp\n\t"
10297 "OR $dst,$tmp,$dst\n\t"
10298 "SRLX $dst,16,$tmp\n\t"
10299 "OR $dst,$tmp,$dst\n\t"
10300 "SRLX $dst,32,$tmp\n\t"
10301 "OR $dst,$tmp,$dst\n\t"
10302 "POPC $dst,$dst\n\t"
10303 "MOV 64,$tmp\n\t"
10304 "SUB $tmp,$dst,$dst" %}
10305 ins_encode %{
10306 Register Rdst = $dst$$Register;
10307 Register Rsrc = $src$$Register;
10308 Register Rtmp = $tmp$$Register;
10309 __ srlx(Rsrc, 1, Rtmp);
10310 __ or3( Rsrc, Rtmp, Rdst);
10311 __ srlx(Rdst, 2, Rtmp);
10312 __ or3( Rdst, Rtmp, Rdst);
10313 __ srlx(Rdst, 4, Rtmp);
10314 __ or3( Rdst, Rtmp, Rdst);
10315 __ srlx(Rdst, 8, Rtmp);
10316 __ or3( Rdst, Rtmp, Rdst);
10317 __ srlx(Rdst, 16, Rtmp);
10318 __ or3( Rdst, Rtmp, Rdst);
10319 __ srlx(Rdst, 32, Rtmp);
10320 __ or3( Rdst, Rtmp, Rdst);
10321 __ popc(Rdst, Rdst);
10322 __ mov(BitsPerLong, Rtmp);
10323 __ sub(Rtmp, Rdst, Rdst);
10324 %}
10325 ins_pipe(ialu_reg);
10326 %}
10327
10328 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
10329 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10330 match(Set dst (CountTrailingZerosI src));
10331 effect(TEMP dst, KILL cr);
10332
10333 // return popc(~x & (x - 1));
10334 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10335 "ANDN $dst,$src,$dst\n\t"
10336 "SRL $dst,R_G0,$dst\n\t"
10337 "POPC $dst,$dst" %}
10338 ins_encode %{
10339 Register Rdst = $dst$$Register;
10340 Register Rsrc = $src$$Register;
10341 __ sub(Rsrc, 1, Rdst);
10342 __ andn(Rdst, Rsrc, Rdst);
10343 __ srl(Rdst, G0, Rdst);
10344 __ popc(Rdst, Rdst);
10345 %}
10346 ins_pipe(ialu_reg);
10347 %}
10348
10349 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10350 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10351 match(Set dst (CountTrailingZerosL src));
10352 effect(TEMP dst, KILL cr);
10353
10354 // return popc(~x & (x - 1));
10355 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10356 "ANDN $dst,$src,$dst\n\t"
10357 "POPC $dst,$dst" %}
10358 ins_encode %{
10359 Register Rdst = $dst$$Register;
10360 Register Rsrc = $src$$Register;
10361 __ sub(Rsrc, 1, Rdst);
10362 __ andn(Rdst, Rsrc, Rdst);
10363 __ popc(Rdst, Rdst);
10364 %}
10365 ins_pipe(ialu_reg);
10366 %}
10367
10368
10369 //---------- Population Count Instructions -------------------------------------
10370
10371 instruct popCountI(iRegI dst, iRegI src) %{
10372 predicate(UsePopCountInstruction);
10373 match(Set dst (PopCountI src));
10374
10375 format %{ "POPC $src, $dst" %}
10376 ins_encode %{
10377 __ popc($src$$Register, $dst$$Register);
10378 %}
10379 ins_pipe(ialu_reg);
10380 %}
10381
10382 // Note: Long.bitCount(long) returns an int.
10383 instruct popCountL(iRegI dst, iRegL src) %{
10384 predicate(UsePopCountInstruction);
10385 match(Set dst (PopCountL src));
10386
10387 format %{ "POPC $src, $dst" %}
10388 ins_encode %{
10389 __ popc($src$$Register, $dst$$Register);
10390 %}
10391 ins_pipe(ialu_reg);
10392 %}
10393
10394
10395 // ============================================================================
10396 //------------Bytes reverse--------------------------------------------------
10397
10398 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10399 match(Set dst (ReverseBytesI src));
10400
10401 // Op cost is artificially doubled to make sure that load or store
10402 // instructions are preferred over this one which requires a spill
10403 // onto a stack slot.
10404 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10405 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10406
10407 ins_encode %{
10408 __ set($src$$disp + STACK_BIAS, O7);
10409 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10410 %}
10411 ins_pipe( iload_mem );
10412 %}
10413
10414 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10415 match(Set dst (ReverseBytesL src));
10416
10417 // Op cost is artificially doubled to make sure that load or store
10418 // instructions are preferred over this one which requires a spill
10419 // onto a stack slot.
10420 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10421 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10422
10423 ins_encode %{
10424 __ set($src$$disp + STACK_BIAS, O7);
10425 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10426 %}
10427 ins_pipe( iload_mem );
10428 %}
10429
10430 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10431 match(Set dst (ReverseBytesUS src));
10432
10433 // Op cost is artificially doubled to make sure that load or store
10434 // instructions are preferred over this one which requires a spill
10435 // onto a stack slot.
10436 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10437 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10438
10439 ins_encode %{
10440 // the value was spilled as an int so bias the load
10441 __ set($src$$disp + STACK_BIAS + 2, O7);
10442 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10443 %}
10444 ins_pipe( iload_mem );
10445 %}
10446
10447 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10448 match(Set dst (ReverseBytesS src));
10449
10450 // Op cost is artificially doubled to make sure that load or store
10451 // instructions are preferred over this one which requires a spill
10452 // onto a stack slot.
10453 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10454 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10455
10456 ins_encode %{
10457 // the value was spilled as an int so bias the load
10458 __ set($src$$disp + STACK_BIAS + 2, O7);
10459 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10460 %}
10461 ins_pipe( iload_mem );
10462 %}
10463
10464 // Load Integer reversed byte order
10465 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10466 match(Set dst (ReverseBytesI (LoadI src)));
10467
10468 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10469 size(4);
10470 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10471
10472 ins_encode %{
10473 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10474 %}
10475 ins_pipe(iload_mem);
10476 %}
10477
10478 // Load Long - aligned and reversed
10479 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10480 match(Set dst (ReverseBytesL (LoadL src)));
10481
10482 ins_cost(MEMORY_REF_COST);
10483 size(4);
10484 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10485
10486 ins_encode %{
10487 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10488 %}
10489 ins_pipe(iload_mem);
10490 %}
10491
10492 // Load unsigned short / char reversed byte order
10493 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10494 match(Set dst (ReverseBytesUS (LoadUS src)));
10495
10496 ins_cost(MEMORY_REF_COST);
10497 size(4);
10498 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10499
10500 ins_encode %{
10501 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10502 %}
10503 ins_pipe(iload_mem);
10504 %}
10505
10506 // Load short reversed byte order
10507 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10508 match(Set dst (ReverseBytesS (LoadS src)));
10509
10510 ins_cost(MEMORY_REF_COST);
10511 size(4);
10512 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10513
10514 ins_encode %{
10515 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10516 %}
10517 ins_pipe(iload_mem);
10518 %}
10519
10520 // Store Integer reversed byte order
10521 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10522 match(Set dst (StoreI dst (ReverseBytesI src)));
10523
10524 ins_cost(MEMORY_REF_COST);
10525 size(4);
10526 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10527
10528 ins_encode %{
10529 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10530 %}
10531 ins_pipe(istore_mem_reg);
10532 %}
10533
10534 // Store Long reversed byte order
10535 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10536 match(Set dst (StoreL dst (ReverseBytesL src)));
10537
10538 ins_cost(MEMORY_REF_COST);
10539 size(4);
10540 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10541
10542 ins_encode %{
10543 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10544 %}
10545 ins_pipe(istore_mem_reg);
10546 %}
10547
10548 // Store unsighed short/char reversed byte order
10549 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10550 match(Set dst (StoreC dst (ReverseBytesUS src)));
10551
10552 ins_cost(MEMORY_REF_COST);
10553 size(4);
10554 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10555
10556 ins_encode %{
10557 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10558 %}
10559 ins_pipe(istore_mem_reg);
10560 %}
10561
10562 // Store short reversed byte order
10563 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10564 match(Set dst (StoreC dst (ReverseBytesS src)));
10565
10566 ins_cost(MEMORY_REF_COST);
10567 size(4);
10568 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10569
10570 ins_encode %{
10571 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10572 %}
10573 ins_pipe(istore_mem_reg);
10574 %}
10575
10576 // ====================VECTOR INSTRUCTIONS=====================================
10577
10578 // Load Aligned Packed values into a Double Register
10579 instruct loadV8(regD dst, memory mem) %{
10580 predicate(n->as_LoadVector()->memory_size() == 8);
10581 match(Set dst (LoadVector mem));
10582 ins_cost(MEMORY_REF_COST);
10583 size(4);
10584 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10585 ins_encode %{
10586 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10587 %}
10588 ins_pipe(floadD_mem);
10589 %}
10590
10591 // Store Vector in Double register to memory
10592 instruct storeV8(memory mem, regD src) %{
10593 predicate(n->as_StoreVector()->memory_size() == 8);
10594 match(Set mem (StoreVector mem src));
10595 ins_cost(MEMORY_REF_COST);
10596 size(4);
10597 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10598 ins_encode %{
10599 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10600 %}
10601 ins_pipe(fstoreD_mem_reg);
10602 %}
10603
10604 // Store Zero into vector in memory
10605 instruct storeV8B_zero(memory mem, immI0 zero) %{
10606 predicate(n->as_StoreVector()->memory_size() == 8);
10607 match(Set mem (StoreVector mem (ReplicateB zero)));
10608 ins_cost(MEMORY_REF_COST);
10609 size(4);
10610 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10611 ins_encode %{
10612 __ stx(G0, $mem$$Address);
10613 %}
10614 ins_pipe(fstoreD_mem_zero);
10615 %}
10616
10617 instruct storeV4S_zero(memory mem, immI0 zero) %{
10618 predicate(n->as_StoreVector()->memory_size() == 8);
10619 match(Set mem (StoreVector mem (ReplicateS zero)));
10620 ins_cost(MEMORY_REF_COST);
10621 size(4);
10622 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10623 ins_encode %{
10624 __ stx(G0, $mem$$Address);
10625 %}
10626 ins_pipe(fstoreD_mem_zero);
10627 %}
10628
10629 instruct storeV2I_zero(memory mem, immI0 zero) %{
10630 predicate(n->as_StoreVector()->memory_size() == 8);
10631 match(Set mem (StoreVector mem (ReplicateI zero)));
10632 ins_cost(MEMORY_REF_COST);
10633 size(4);
10634 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10635 ins_encode %{
10636 __ stx(G0, $mem$$Address);
10637 %}
10638 ins_pipe(fstoreD_mem_zero);
10639 %}
10640
10641 instruct storeV2F_zero(memory mem, immF0 zero) %{
10642 predicate(n->as_StoreVector()->memory_size() == 8);
10643 match(Set mem (StoreVector mem (ReplicateF zero)));
10644 ins_cost(MEMORY_REF_COST);
10645 size(4);
10646 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10647 ins_encode %{
10648 __ stx(G0, $mem$$Address);
10649 %}
10650 ins_pipe(fstoreD_mem_zero);
10651 %}
10652
10653 // Replicate scalar to packed byte values into Double register
10654 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10655 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10656 match(Set dst (ReplicateB src));
10657 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10658 format %{ "SLLX $src,56,$tmp\n\t"
10659 "SRLX $tmp, 8,$tmp2\n\t"
10660 "OR $tmp,$tmp2,$tmp\n\t"
10661 "SRLX $tmp,16,$tmp2\n\t"
10662 "OR $tmp,$tmp2,$tmp\n\t"
10663 "SRLX $tmp,32,$tmp2\n\t"
10664 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10665 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10666 ins_encode %{
10667 Register Rsrc = $src$$Register;
10668 Register Rtmp = $tmp$$Register;
10669 Register Rtmp2 = $tmp2$$Register;
10670 __ sllx(Rsrc, 56, Rtmp);
10671 __ srlx(Rtmp, 8, Rtmp2);
10672 __ or3 (Rtmp, Rtmp2, Rtmp);
10673 __ srlx(Rtmp, 16, Rtmp2);
10674 __ or3 (Rtmp, Rtmp2, Rtmp);
10675 __ srlx(Rtmp, 32, Rtmp2);
10676 __ or3 (Rtmp, Rtmp2, Rtmp);
10677 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10678 %}
10679 ins_pipe(ialu_reg);
10680 %}
10681
10682 // Replicate scalar to packed byte values into Double stack
10683 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10684 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10685 match(Set dst (ReplicateB src));
10686 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10687 format %{ "SLLX $src,56,$tmp\n\t"
10688 "SRLX $tmp, 8,$tmp2\n\t"
10689 "OR $tmp,$tmp2,$tmp\n\t"
10690 "SRLX $tmp,16,$tmp2\n\t"
10691 "OR $tmp,$tmp2,$tmp\n\t"
10692 "SRLX $tmp,32,$tmp2\n\t"
10693 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10694 "STX $tmp,$dst\t! regL to stkD" %}
10695 ins_encode %{
10696 Register Rsrc = $src$$Register;
10697 Register Rtmp = $tmp$$Register;
10698 Register Rtmp2 = $tmp2$$Register;
10699 __ sllx(Rsrc, 56, Rtmp);
10700 __ srlx(Rtmp, 8, Rtmp2);
10701 __ or3 (Rtmp, Rtmp2, Rtmp);
10702 __ srlx(Rtmp, 16, Rtmp2);
10703 __ or3 (Rtmp, Rtmp2, Rtmp);
10704 __ srlx(Rtmp, 32, Rtmp2);
10705 __ or3 (Rtmp, Rtmp2, Rtmp);
10706 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10707 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10708 %}
10709 ins_pipe(ialu_reg);
10710 %}
10711
10712 // Replicate scalar constant to packed byte values in Double register
10713 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10714 predicate(n->as_Vector()->length() == 8);
10715 match(Set dst (ReplicateB con));
10716 effect(KILL tmp);
10717 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10718 ins_encode %{
10719 // XXX This is a quick fix for 6833573.
10720 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10721 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10722 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10723 %}
10724 ins_pipe(loadConFD);
10725 %}
10726
10727 // Replicate scalar to packed char/short values into Double register
10728 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10729 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10730 match(Set dst (ReplicateS src));
10731 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10732 format %{ "SLLX $src,48,$tmp\n\t"
10733 "SRLX $tmp,16,$tmp2\n\t"
10734 "OR $tmp,$tmp2,$tmp\n\t"
10735 "SRLX $tmp,32,$tmp2\n\t"
10736 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10737 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10738 ins_encode %{
10739 Register Rsrc = $src$$Register;
10740 Register Rtmp = $tmp$$Register;
10741 Register Rtmp2 = $tmp2$$Register;
10742 __ sllx(Rsrc, 48, Rtmp);
10743 __ srlx(Rtmp, 16, Rtmp2);
10744 __ or3 (Rtmp, Rtmp2, Rtmp);
10745 __ srlx(Rtmp, 32, Rtmp2);
10746 __ or3 (Rtmp, Rtmp2, Rtmp);
10747 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10748 %}
10749 ins_pipe(ialu_reg);
10750 %}
10751
10752 // Replicate scalar to packed char/short values into Double stack
10753 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10754 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10755 match(Set dst (ReplicateS src));
10756 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10757 format %{ "SLLX $src,48,$tmp\n\t"
10758 "SRLX $tmp,16,$tmp2\n\t"
10759 "OR $tmp,$tmp2,$tmp\n\t"
10760 "SRLX $tmp,32,$tmp2\n\t"
10761 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10762 "STX $tmp,$dst\t! regL to stkD" %}
10763 ins_encode %{
10764 Register Rsrc = $src$$Register;
10765 Register Rtmp = $tmp$$Register;
10766 Register Rtmp2 = $tmp2$$Register;
10767 __ sllx(Rsrc, 48, Rtmp);
10768 __ srlx(Rtmp, 16, Rtmp2);
10769 __ or3 (Rtmp, Rtmp2, Rtmp);
10770 __ srlx(Rtmp, 32, Rtmp2);
10771 __ or3 (Rtmp, Rtmp2, Rtmp);
10772 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10773 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10774 %}
10775 ins_pipe(ialu_reg);
10776 %}
10777
10778 // Replicate scalar constant to packed char/short values in Double register
10779 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10780 predicate(n->as_Vector()->length() == 4);
10781 match(Set dst (ReplicateS con));
10782 effect(KILL tmp);
10783 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10784 ins_encode %{
10785 // XXX This is a quick fix for 6833573.
10786 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10787 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10788 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10789 %}
10790 ins_pipe(loadConFD);
10791 %}
10792
10793 // Replicate scalar to packed int values into Double register
10794 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10795 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10796 match(Set dst (ReplicateI src));
10797 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10798 format %{ "SLLX $src,32,$tmp\n\t"
10799 "SRLX $tmp,32,$tmp2\n\t"
10800 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10801 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10802 ins_encode %{
10803 Register Rsrc = $src$$Register;
10804 Register Rtmp = $tmp$$Register;
10805 Register Rtmp2 = $tmp2$$Register;
10806 __ sllx(Rsrc, 32, Rtmp);
10807 __ srlx(Rtmp, 32, Rtmp2);
10808 __ or3 (Rtmp, Rtmp2, Rtmp);
10809 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10810 %}
10811 ins_pipe(ialu_reg);
10812 %}
10813
10814 // Replicate scalar to packed int values into Double stack
10815 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10816 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10817 match(Set dst (ReplicateI src));
10818 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10819 format %{ "SLLX $src,32,$tmp\n\t"
10820 "SRLX $tmp,32,$tmp2\n\t"
10821 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10822 "STX $tmp,$dst\t! regL to stkD" %}
10823 ins_encode %{
10824 Register Rsrc = $src$$Register;
10825 Register Rtmp = $tmp$$Register;
10826 Register Rtmp2 = $tmp2$$Register;
10827 __ sllx(Rsrc, 32, Rtmp);
10828 __ srlx(Rtmp, 32, Rtmp2);
10829 __ or3 (Rtmp, Rtmp2, Rtmp);
10830 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10831 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10832 %}
10833 ins_pipe(ialu_reg);
10834 %}
10835
10836 // Replicate scalar zero constant to packed int values in Double register
10837 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10838 predicate(n->as_Vector()->length() == 2);
10839 match(Set dst (ReplicateI con));
10840 effect(KILL tmp);
10841 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10842 ins_encode %{
10843 // XXX This is a quick fix for 6833573.
10844 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10845 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10846 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10847 %}
10848 ins_pipe(loadConFD);
10849 %}
10850
10851 // Replicate scalar to packed float values into Double stack
10852 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10853 predicate(n->as_Vector()->length() == 2);
10854 match(Set dst (ReplicateF src));
10855 ins_cost(MEMORY_REF_COST*2);
10856 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10857 "STF $src,$dst.lo" %}
10858 opcode(Assembler::stf_op3);
10859 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10860 ins_pipe(fstoreF_stk_reg);
10861 %}
10862
10863 // Replicate scalar zero constant to packed float values in Double register
10864 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10865 predicate(n->as_Vector()->length() == 2);
10866 match(Set dst (ReplicateF con));
10867 effect(KILL tmp);
10868 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10869 ins_encode %{
10870 // XXX This is a quick fix for 6833573.
10871 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10872 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10873 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10874 %}
10875 ins_pipe(loadConFD);
10876 %}
10877
10878 //----------PEEPHOLE RULES-----------------------------------------------------
10879 // These must follow all instruction definitions as they use the names
10880 // defined in the instructions definitions.
10881 //
10882 // peepmatch ( root_instr_name [preceding_instruction]* );
10883 //
10884 // peepconstraint %{
10885 // (instruction_number.operand_name relational_op instruction_number.operand_name
10886 // [, ...] );
10887 // // instruction numbers are zero-based using left to right order in peepmatch
10888 //
10889 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10890 // // provide an instruction_number.operand_name for each operand that appears
10891 // // in the replacement instruction's match rule
10892 //
10893 // ---------VM FLAGS---------------------------------------------------------
10894 //
10895 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10896 //
10897 // Each peephole rule is given an identifying number starting with zero and
10898 // increasing by one in the order seen by the parser. An individual peephole
10899 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10900 // on the command-line.
10901 //
10902 // ---------CURRENT LIMITATIONS----------------------------------------------
10903 //
10904 // Only match adjacent instructions in same basic block
10905 // Only equality constraints
10906 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10907 // Only one replacement instruction
10908 //
10909 // ---------EXAMPLE----------------------------------------------------------
10910 //
10911 // // pertinent parts of existing instructions in architecture description
10912 // instruct movI(eRegI dst, eRegI src) %{
10913 // match(Set dst (CopyI src));
10914 // %}
10915 //
10916 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10917 // match(Set dst (AddI dst src));
10918 // effect(KILL cr);
10919 // %}
10920 //
10921 // // Change (inc mov) to lea
10922 // peephole %{
10923 // // increment preceeded by register-register move
10924 // peepmatch ( incI_eReg movI );
10925 // // require that the destination register of the increment
10926 // // match the destination register of the move
10927 // peepconstraint ( 0.dst == 1.dst );
10928 // // construct a replacement instruction that sets
10929 // // the destination to ( move's source register + one )
10930 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10931 // %}
10932 //
10933
10934 // // Change load of spilled value to only a spill
10935 // instruct storeI(memory mem, eRegI src) %{
10936 // match(Set mem (StoreI mem src));
10937 // %}
10938 //
10939 // instruct loadI(eRegI dst, memory mem) %{
10940 // match(Set dst (LoadI mem));
10941 // %}
10942 //
10943 // peephole %{
10944 // peepmatch ( loadI storeI );
10945 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10946 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10947 // %}
10948
10949 //----------SMARTSPILL RULES---------------------------------------------------
10950 // These must follow all instruction definitions as they use the names
10951 // defined in the instructions definitions.
10952 //
10953 // SPARC will probably not have any of these rules due to RISC instruction set.
10954
10955 //----------PIPELINE-----------------------------------------------------------
10956 // Rules which define the behavior of the target architectures pipeline.