1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_FPU_size() {
232 if (Compile::current()->in_24_bit_fp_mode())
233 return 6; // fldcw
234 return 0;
235 }
236
237 static int preserve_SP_size() {
238 return 2; // op, rm(reg/reg)
239 }
240
241 // !!!!! Special hack to get all type of calls to specify the byte offset
242 // from the start of the call to the point where the return address
243 // will point.
244 int MachCallStaticJavaNode::ret_addr_offset() {
245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
246 if (_method_handle_invoke)
247 offset += preserve_SP_size();
248 return offset;
249 }
250
251 int MachCallDynamicJavaNode::ret_addr_offset() {
252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
253 }
254
255 static int sizeof_FFree_Float_Stack_All = -1;
256
257 int MachCallRuntimeNode::ret_addr_offset() {
258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
260 }
261
262 // Indicate if the safepoint node needs the polling page as an input.
263 // Since x86 does have absolute addressing, it doesn't.
264 bool SafePointNode::needs_polling_address_input() {
265 return false;
266 }
267
268 //
269 // Compute padding required for nodes which need alignment
270 //
271
272 // The address of the call instruction needs to be 4-byte aligned to
273 // ensure that it does not span a cache line so that it can be patched.
274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
275 current_offset += pre_call_FPU_size(); // skip fldcw, if any
276 current_offset += 1; // skip call opcode byte
277 return round_to(current_offset, alignment_required()) - current_offset;
278 }
279
280 // The address of the call instruction needs to be 4-byte aligned to
281 // ensure that it does not span a cache line so that it can be patched.
282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
283 current_offset += pre_call_FPU_size(); // skip fldcw, if any
284 current_offset += preserve_SP_size(); // skip mov rbp, rsp
285 current_offset += 1; // skip call opcode byte
286 return round_to(current_offset, alignment_required()) - current_offset;
287 }
288
289 // The address of the call instruction needs to be 4-byte aligned to
290 // ensure that it does not span a cache line so that it can be patched.
291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
292 current_offset += pre_call_FPU_size(); // skip fldcw, if any
293 current_offset += 5; // skip MOV instruction
294 current_offset += 1; // skip call opcode byte
295 return round_to(current_offset, alignment_required()) - current_offset;
296 }
297
298 // EMIT_RM()
299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
301 cbuf.insts()->emit_int8(c);
302 }
303
304 // EMIT_CC()
305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
306 unsigned char c = (unsigned char)( f1 | f2 );
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_OPCODE()
311 void emit_opcode(CodeBuffer &cbuf, int code) {
312 cbuf.insts()->emit_int8((unsigned char) code);
313 }
314
315 // EMIT_OPCODE() w/ relocation information
316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
317 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
318 emit_opcode(cbuf, code);
319 }
320
321 // EMIT_D8()
322 void emit_d8(CodeBuffer &cbuf, int d8) {
323 cbuf.insts()->emit_int8((unsigned char) d8);
324 }
325
326 // EMIT_D16()
327 void emit_d16(CodeBuffer &cbuf, int d16) {
328 cbuf.insts()->emit_int16(d16);
329 }
330
331 // EMIT_D32()
332 void emit_d32(CodeBuffer &cbuf, int d32) {
333 cbuf.insts()->emit_int32(d32);
334 }
335
336 // emit 32 bit value and construct relocation entry from relocInfo::relocType
337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
338 int format) {
339 cbuf.relocate(cbuf.insts_mark(), reloc, format);
340 cbuf.insts()->emit_int32(d32);
341 }
342
343 // emit 32 bit value and construct relocation entry from RelocationHolder
344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
345 int format) {
346 #ifdef ASSERT
347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
349 }
350 #endif
351 cbuf.relocate(cbuf.insts_mark(), rspec, format);
352 cbuf.insts()->emit_int32(d32);
353 }
354
355 // Access stack slot for load or store
356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
358 if( -128 <= disp && disp <= 127 ) {
359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
361 emit_d8 (cbuf, disp); // Displacement // R/M byte
362 } else {
363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 }
367 }
368
369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 }
378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127)
380 && (disp_reloc == relocInfo::none) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace);
383 }
384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here)
388 if ( disp_reloc != relocInfo::none ) {
389 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
390 } else {
391 emit_d32 (cbuf, displace);
392 }
393 }
394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( disp_reloc != relocInfo::none ) {
397 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
398 } else {
399 emit_d32 (cbuf, displace);
400 }
401 }
402 }
403 }
404 }
405 else { // Else, encode with the SIB byte
406 // If no displacement, mode is 0x0; unless base is [EBP]
407 if (displace == 0 && (base != EBP_enc)) { // If no displacement
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base);
410 }
411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127)
413 && (disp_reloc == relocInfo::none) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == 0x04 ) {
420 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, 0x04);
422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base);
425 }
426 if ( disp_reloc != relocInfo::none ) {
427 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
428 } else {
429 emit_d32 (cbuf, displace);
430 }
431 }
432 }
433 }
434 }
435
436
437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
438 if( dst_encoding == src_encoding ) {
439 // reg-reg copy, use an empty encoding
440 } else {
441 emit_opcode( cbuf, 0x8B );
442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
443 }
444 }
445
446 void emit_cmpfp_fixup(MacroAssembler& _masm) {
447 Label exit;
448 __ jccb(Assembler::noParity, exit);
449 __ pushf();
450 //
451 // comiss/ucomiss instructions set ZF,PF,CF flags and
452 // zero OF,AF,SF for NaN values.
453 // Fixup flags by zeroing ZF,PF so that compare of NaN
454 // values returns 'less than' result (CF is set).
455 // Leave the rest of flags unchanged.
456 //
457 // 7 6 5 4 3 2 1 0
458 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
459 // 0 0 1 0 1 0 1 1 (0x2B)
460 //
461 __ andl(Address(rsp, 0), 0xffffff2b);
462 __ popf();
463 __ bind(exit);
464 }
465
466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
467 Label done;
468 __ movl(dst, -1);
469 __ jcc(Assembler::parity, done);
470 __ jcc(Assembler::below, done);
471 __ setb(Assembler::notEqual, dst);
472 __ movzbl(dst, dst);
473 __ bind(done);
474 }
475
476
477 //=============================================================================
478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
479
480 int Compile::ConstantTable::calculate_table_base_offset() const {
481 return 0; // absolute addressing, no offset
482 }
483
484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
485 // Empty encoding
486 }
487
488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
489 return 0;
490 }
491
492 #ifndef PRODUCT
493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
494 st->print("# MachConstantBaseNode (empty encoding)");
495 }
496 #endif
497
498
499 //=============================================================================
500 #ifndef PRODUCT
501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
502 Compile* C = ra_->C;
503
504 int framesize = C->frame_slots() << LogBytesPerInt;
505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
506 // Remove wordSize for return addr which is already pushed.
507 framesize -= wordSize;
508
509 if (C->need_stack_bang(framesize)) {
510 framesize -= wordSize;
511 st->print("# stack bang");
512 st->print("\n\t");
513 st->print("PUSH EBP\t# Save EBP");
514 if (framesize) {
515 st->print("\n\t");
516 st->print("SUB ESP, #%d\t# Create frame",framesize);
517 }
518 } else {
519 st->print("SUB ESP, #%d\t# Create frame",framesize);
520 st->print("\n\t");
521 framesize -= wordSize;
522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
523 }
524
525 if (VerifyStackAtCalls) {
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
529 }
530
531 if( C->in_24_bit_fp_mode() ) {
532 st->print("\n\t");
533 st->print("FLDCW \t# load 24 bit fpu control word");
534 }
535 if (UseSSE >= 2 && VerifyFPU) {
536 st->print("\n\t");
537 st->print("# verify FPU stack (must be clean on entry)");
538 }
539
540 #ifdef ASSERT
541 if (VerifyStackAtCalls) {
542 st->print("\n\t");
543 st->print("# stack alignment check");
544 }
545 #endif
546 st->cr();
547 }
548 #endif
549
550
551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
552 Compile* C = ra_->C;
553 MacroAssembler _masm(&cbuf);
554
555 int framesize = C->frame_slots() << LogBytesPerInt;
556
557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
558
559 C->set_frame_complete(cbuf.insts_size());
560
561 if (C->has_mach_constant_base_node()) {
562 // NOTE: We set the table base offset here because users might be
563 // emitted before MachConstantBaseNode.
564 Compile::ConstantTable& constant_table = C->constant_table();
565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
566 }
567 }
568
569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
570 return MachNode::size(ra_); // too many variables; just compute it the hard way
571 }
572
573 int MachPrologNode::reloc() const {
574 return 0; // a large enough number
575 }
576
577 //=============================================================================
578 #ifndef PRODUCT
579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
580 Compile *C = ra_->C;
581 int framesize = C->frame_slots() << LogBytesPerInt;
582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
583 // Remove two words for return addr and rbp,
584 framesize -= 2*wordSize;
585
586 if( C->in_24_bit_fp_mode() ) {
587 st->print("FLDCW standard control word");
588 st->cr(); st->print("\t");
589 }
590 if( framesize ) {
591 st->print("ADD ESP,%d\t# Destroy frame",framesize);
592 st->cr(); st->print("\t");
593 }
594 st->print_cr("POPL EBP"); st->print("\t");
595 if( do_polling() && C->is_method_compilation() ) {
596 st->print("TEST PollPage,EAX\t! Poll Safepoint");
597 st->cr(); st->print("\t");
598 }
599 }
600 #endif
601
602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 Compile *C = ra_->C;
604
605 // If method set FPU control word, restore to standard control word
606 if( C->in_24_bit_fp_mode() ) {
607 MacroAssembler masm(&cbuf);
608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
609 }
610
611 int framesize = C->frame_slots() << LogBytesPerInt;
612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
613 // Remove two words for return addr and rbp,
614 framesize -= 2*wordSize;
615
616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
617
618 if( framesize >= 128 ) {
619 emit_opcode(cbuf, 0x81); // add SP, #framesize
620 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
621 emit_d32(cbuf, framesize);
622 }
623 else if( framesize ) {
624 emit_opcode(cbuf, 0x83); // add SP, #framesize
625 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
626 emit_d8(cbuf, framesize);
627 }
628
629 emit_opcode(cbuf, 0x58 | EBP_enc);
630
631 if( do_polling() && C->is_method_compilation() ) {
632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
633 emit_opcode(cbuf,0x85);
634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
635 emit_d32(cbuf, (intptr_t)os::get_polling_page());
636 }
637 }
638
639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
640 Compile *C = ra_->C;
641 // If method set FPU control word, restore to standard control word
642 int size = C->in_24_bit_fp_mode() ? 6 : 0;
643 if( do_polling() && C->is_method_compilation() ) size += 6;
644
645 int framesize = C->frame_slots() << LogBytesPerInt;
646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
647 // Remove two words for return addr and rbp,
648 framesize -= 2*wordSize;
649
650 size++; // popl rbp,
651
652 if( framesize >= 128 ) {
653 size += 6;
654 } else {
655 size += framesize ? 3 : 0;
656 }
657 return size;
658 }
659
660 int MachEpilogNode::reloc() const {
661 return 0; // a large enough number
662 }
663
664 const Pipeline * MachEpilogNode::pipeline() const {
665 return MachNode::pipeline_class();
666 }
667
668 int MachEpilogNode::safepoint_offset() const { return 0; }
669
670 //=============================================================================
671
672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
673 static enum RC rc_class( OptoReg::Name reg ) {
674
675 if( !OptoReg::is_valid(reg) ) return rc_bad;
676 if (OptoReg::is_stack(reg)) return rc_stack;
677
678 VMReg r = OptoReg::as_VMReg(reg);
679 if (r->is_Register()) return rc_int;
680 if (r->is_FloatRegister()) {
681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
682 return rc_float;
683 }
684 assert(r->is_XMMRegister(), "must be");
685 return rc_xmm;
686 }
687
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
693 #ifndef PRODUCT
694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
699 } else { // FLD, FST, PUSH, POP
700 st->print("%s [ESP + #%d]",op_str,offset);
701 }
702 #endif
703 }
704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
705 return size+3+offset_size;
706 }
707
708 // Helper for XMM registers. Extra opcode bits, limited syntax.
709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
711 if (cbuf) {
712 MacroAssembler _masm(cbuf);
713 if (reg_lo+1 == reg_hi) { // double move?
714 if (is_load) {
715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
716 } else {
717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
718 }
719 } else {
720 if (is_load) {
721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
722 } else {
723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
724 }
725 }
726 #ifndef PRODUCT
727 } else if (!do_size) {
728 if (size != 0) st->print("\n\t");
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) st->print("%s %s,[ESP + #%d]",
731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
732 Matcher::regName[reg_lo], offset);
733 else st->print("MOVSD [ESP + #%d],%s",
734 offset, Matcher::regName[reg_lo]);
735 } else {
736 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
737 Matcher::regName[reg_lo], offset);
738 else st->print("MOVSS [ESP + #%d],%s",
739 offset, Matcher::regName[reg_lo]);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
745 return size+5+offset_size;
746 }
747
748
749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
750 int src_hi, int dst_hi, int size, outputStream* st ) {
751 if (cbuf) {
752 MacroAssembler _masm(cbuf);
753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
755 as_XMMRegister(Matcher::_regEncode[src_lo]));
756 } else {
757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
758 as_XMMRegister(Matcher::_regEncode[src_lo]));
759 }
760 #ifndef PRODUCT
761 } else if (!do_size) {
762 if (size != 0) st->print("\n\t");
763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
766 } else {
767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
768 }
769 } else {
770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
772 } else {
773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
774 }
775 }
776 #endif
777 }
778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
779 // Only MOVAPS SSE prefix uses 1 byte.
780 int sz = 4;
781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
783 return size + sz;
784 }
785
786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
787 int src_hi, int dst_hi, int size, outputStream* st ) {
788 // 32-bit
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
792 as_Register(Matcher::_regEncode[src_lo]));
793 #ifndef PRODUCT
794 } else if (!do_size) {
795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
796 #endif
797 }
798 return 4;
799 }
800
801
802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
808 as_XMMRegister(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
818 if( cbuf ) {
819 emit_opcode(*cbuf, 0x8B );
820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
821 #ifndef PRODUCT
822 } else if( !do_size ) {
823 if( size != 0 ) st->print("\n\t");
824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
825 #endif
826 }
827 return size+2;
828 }
829
830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
831 int offset, int size, outputStream* st ) {
832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
833 if( cbuf ) {
834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 st->print("FLD %s",Matcher::regName[src_lo]);
840 #endif
841 }
842 size += 2;
843 }
844
845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
846 const char *op_str;
847 int op;
848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
850 op = 0xDD;
851 } else { // 32-bit store
852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
853 op = 0xD9;
854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
855 }
856
857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
858 }
859
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
863
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
866
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
961
962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
963 // Get registers to move
964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
966 OptoReg::Name dst_second = ra_->get_reg_second(this );
967 OptoReg::Name dst_first = ra_->get_reg_first(this );
968
969 enum RC src_second_rc = rc_class(src_second);
970 enum RC src_first_rc = rc_class(src_first);
971 enum RC dst_second_rc = rc_class(dst_second);
972 enum RC dst_first_rc = rc_class(dst_first);
973
974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
975
976 // Generate spill code!
977 int size = 0;
978
979 if( src_first == dst_first && src_second == dst_second )
980 return size; // Self copy, no move
981
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1004
1005 // --------------------------------------
1006 // Check for mem-mem move. push/pop to move.
1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1013 }
1014 // move low bits
1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1020 }
1021 return size;
1022 }
1023
1024 // --------------------------------------
1025 // Check for integer reg-reg copy
1026 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1028
1029 // Check for integer store
1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1032
1033 // Check for integer load
1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1036
1037 // Check for integer reg-xmm reg copy
1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1040 "no 64 bit integer-float reg moves" );
1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1042 }
1043 // --------------------------------------
1044 // Check for float reg-reg copy
1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1048 if( cbuf ) {
1049
1050 // Note the mucking with the register encode to compensate for the 0/1
1051 // indexing issue mentioned in a comment in the reg_def sections
1052 // for FPR registers many lines above here.
1053
1054 if( src_first != FPR1L_num ) {
1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1059 } else {
1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1062 }
1063 #ifndef PRODUCT
1064 } else if( !do_size ) {
1065 if( size != 0 ) st->print("\n\t");
1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1067 else st->print( "FST %s", Matcher::regName[dst_first]);
1068 #endif
1069 }
1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1071 }
1072
1073 // Check for float store
1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1076 }
1077
1078 // Check for float load
1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1080 int offset = ra_->reg2offset(src_first);
1081 const char *op_str;
1082 int op;
1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1084 op_str = "FLD_D";
1085 op = 0xDD;
1086 } else { // 32-bit load
1087 op_str = "FLD_S";
1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 }
1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT
1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t");
1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1100 #endif
1101 }
1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1103 return size + 3+offset_size+2;
1104 }
1105
1106 // Check for xmm reg-reg copy
1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1109 (src_first+1 == src_second && dst_first+1 == dst_second),
1110 "no non-adjacent float-moves" );
1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1112 }
1113
1114 // Check for xmm reg-integer reg copy
1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1117 "no 64 bit float-integer reg moves" );
1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1119 }
1120
1121 // Check for xmm store
1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1124 }
1125
1126 // Check for float xmm load
1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1129 }
1130
1131 // Copy from float reg to xmm reg
1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1133 // copy to the top of stack from floating point reg
1134 // and use LEA to preserve flags
1135 if( cbuf ) {
1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d8(*cbuf,0xF8);
1140 #ifndef PRODUCT
1141 } else if( !do_size ) {
1142 if( size != 0 ) st->print("\n\t");
1143 st->print("LEA ESP,[ESP-8]");
1144 #endif
1145 }
1146 size += 4;
1147
1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1149
1150 // Copy from the temp memory to the xmm reg.
1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1152
1153 if( cbuf ) {
1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1157 emit_d8(*cbuf,0x08);
1158 #ifndef PRODUCT
1159 } else if( !do_size ) {
1160 if( size != 0 ) st->print("\n\t");
1161 st->print("LEA ESP,[ESP+8]");
1162 #endif
1163 }
1164 size += 4;
1165 return size;
1166 }
1167
1168 assert( size > 0, "missed a case" );
1169
1170 // --------------------------------------------------------------------
1171 // Check for second bits still needing moving.
1172 if( src_second == dst_second )
1173 return size; // Self copy; no move
1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1175
1176 // Check for second word int-int move
1177 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1179
1180 // Check for second word integer store
1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1183
1184 // Check for second word integer load
1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1187
1188
1189 Unimplemented();
1190 }
1191
1192 #ifndef PRODUCT
1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1194 implementation( NULL, ra_, false, st );
1195 }
1196 #endif
1197
1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1199 implementation( &cbuf, ra_, false, NULL );
1200 }
1201
1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1203 return implementation( NULL, ra_, true, NULL );
1204 }
1205
1206
1207 //=============================================================================
1208 #ifndef PRODUCT
1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1211 int reg = ra_->get_reg_first(this);
1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1213 }
1214 #endif
1215
1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1218 int reg = ra_->get_encode(this);
1219 if( offset >= 128 ) {
1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1221 emit_rm(cbuf, 0x2, reg, 0x04);
1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1223 emit_d32(cbuf, offset);
1224 }
1225 else {
1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1227 emit_rm(cbuf, 0x1, reg, 0x04);
1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1229 emit_d8(cbuf, offset);
1230 }
1231 }
1232
1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 if( offset >= 128 ) {
1236 return 7;
1237 }
1238 else {
1239 return 4;
1240 }
1241 }
1242
1243 //=============================================================================
1244
1245 // Offset from start of compiled java to interpreter stub to the load
1246 // constant that loads the inline cache (IC) (0 on i486).
1247 const int CompiledStaticCall::comp_to_int_load_offset = 0;
1248
1249 // emit call stub, compiled java to interpreter
1250 void emit_java_to_interp(CodeBuffer &cbuf ) {
1251 // Stub is fixed up when the corresponding call is converted from calling
1252 // compiled code to calling interpreted code.
1253 // mov rbx,0
1254 // jmp -1
1255
1256 address mark = cbuf.insts_mark(); // get mark within main instrs section
1257
1258 // Note that the code buffer's insts_mark is always relative to insts.
1259 // That's why we must use the macroassembler to generate a stub.
1260 MacroAssembler _masm(&cbuf);
1261
1262 address base =
1263 __ start_a_stub(Compile::MAX_stubs_size);
1264 if (base == NULL) return; // CodeBuffer::expand failed
1265 // static stub relocation stores the instruction address of the call
1266 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1267 // static stub relocation also tags the Method* in the code-stream.
1268 __ mov_metadata(rbx, (Metadata*)NULL); // method is zapped till fixup time
1269 // This is recognized as unresolved by relocs/nativeInst/ic code
1270 __ jump(RuntimeAddress(__ pc()));
1271
1272 __ end_a_stub();
1273 // Update current stubs pointer and restore insts_end.
1274 }
1275 // size of call stub, compiled java to interpretor
1276 uint size_java_to_interp() {
1277 return 10; // movl; jmp
1278 }
1279 // relocation entries for call stub, compiled java to interpretor
1280 uint reloc_java_to_interp() {
1281 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1282 }
1283
1284 //=============================================================================
1285 #ifndef PRODUCT
1286 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1287 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1288 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1289 st->print_cr("\tNOP");
1290 st->print_cr("\tNOP");
1291 if( !OptoBreakpoint )
1292 st->print_cr("\tNOP");
1293 }
1294 #endif
1295
1296 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1297 MacroAssembler masm(&cbuf);
1298 #ifdef ASSERT
1299 uint insts_size = cbuf.insts_size();
1300 #endif
1301 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1302 masm.jump_cc(Assembler::notEqual,
1303 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1304 /* WARNING these NOPs are critical so that verified entry point is properly
1305 aligned for patching by NativeJump::patch_verified_entry() */
1306 int nops_cnt = 2;
1307 if( !OptoBreakpoint ) // Leave space for int3
1308 nops_cnt += 1;
1309 masm.nop(nops_cnt);
1310
1311 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1312 }
1313
1314 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1315 return OptoBreakpoint ? 11 : 12;
1316 }
1317
1318
1319 //=============================================================================
1320 uint size_exception_handler() {
1321 // NativeCall instruction size is the same as NativeJump.
1322 // exception handler starts out as jump and can be patched to
1323 // a call be deoptimization. (4932387)
1324 // Note that this value is also credited (in output.cpp) to
1325 // the size of the code section.
1326 return NativeJump::instruction_size;
1327 }
1328
1329 // Emit exception handler code. Stuff framesize into a register
1330 // and call a VM stub routine.
1331 int emit_exception_handler(CodeBuffer& cbuf) {
1332
1333 // Note that the code buffer's insts_mark is always relative to insts.
1334 // That's why we must use the macroassembler to generate a handler.
1335 MacroAssembler _masm(&cbuf);
1336 address base =
1337 __ start_a_stub(size_exception_handler());
1338 if (base == NULL) return 0; // CodeBuffer::expand failed
1339 int offset = __ offset();
1340 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1341 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1342 __ end_a_stub();
1343 return offset;
1344 }
1345
1346 uint size_deopt_handler() {
1347 // NativeCall instruction size is the same as NativeJump.
1348 // exception handler starts out as jump and can be patched to
1349 // a call be deoptimization. (4932387)
1350 // Note that this value is also credited (in output.cpp) to
1351 // the size of the code section.
1352 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1353 }
1354
1355 // Emit deopt handler code.
1356 int emit_deopt_handler(CodeBuffer& cbuf) {
1357
1358 // Note that the code buffer's insts_mark is always relative to insts.
1359 // That's why we must use the macroassembler to generate a handler.
1360 MacroAssembler _masm(&cbuf);
1361 address base =
1362 __ start_a_stub(size_exception_handler());
1363 if (base == NULL) return 0; // CodeBuffer::expand failed
1364 int offset = __ offset();
1365 InternalAddress here(__ pc());
1366 __ pushptr(here.addr());
1367
1368 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1369 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1370 __ end_a_stub();
1371 return offset;
1372 }
1373
1374 int Matcher::regnum_to_fpu_offset(int regnum) {
1375 return regnum - 32; // The FP registers are in the second chunk
1376 }
1377
1378 // This is UltraSparc specific, true just means we have fast l2f conversion
1379 const bool Matcher::convL2FSupported(void) {
1380 return true;
1381 }
1382
1383 // Is this branch offset short enough that a short branch can be used?
1384 //
1385 // NOTE: If the platform does not provide any short branch variants, then
1386 // this method should return false for offset 0.
1387 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1388 // The passed offset is relative to address of the branch.
1389 // On 86 a branch displacement is calculated relative to address
1390 // of a next instruction.
1391 offset -= br_size;
1392
1393 // the short version of jmpConUCF2 contains multiple branches,
1394 // making the reach slightly less
1395 if (rule == jmpConUCF2_rule)
1396 return (-126 <= offset && offset <= 125);
1397 return (-128 <= offset && offset <= 127);
1398 }
1399
1400 const bool Matcher::isSimpleConstant64(jlong value) {
1401 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1402 return false;
1403 }
1404
1405 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1406 const bool Matcher::init_array_count_is_in_bytes = false;
1407
1408 // Threshold size for cleararray.
1409 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1410
1411 // Needs 2 CMOV's for longs.
1412 const int Matcher::long_cmove_cost() { return 1; }
1413
1414 // No CMOVF/CMOVD with SSE/SSE2
1415 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1416
1417 // Should the Matcher clone shifts on addressing modes, expecting them to
1418 // be subsumed into complex addressing expressions or compute them into
1419 // registers? True for Intel but false for most RISCs
1420 const bool Matcher::clone_shift_expressions = true;
1421
1422 // Do we need to mask the count passed to shift instructions or does
1423 // the cpu only look at the lower 5/6 bits anyway?
1424 const bool Matcher::need_masked_shift_count = false;
1425
1426 bool Matcher::narrow_oop_use_complex_address() {
1427 ShouldNotCallThis();
1428 return true;
1429 }
1430
1431 bool Matcher::narrow_klass_use_complex_address() {
1432 ShouldNotCallThis();
1433 return true;
1434 }
1435
1436
1437 // Is it better to copy float constants, or load them directly from memory?
1438 // Intel can load a float constant from a direct address, requiring no
1439 // extra registers. Most RISCs will have to materialize an address into a
1440 // register first, so they would do better to copy the constant from stack.
1441 const bool Matcher::rematerialize_float_constants = true;
1442
1443 // If CPU can load and store mis-aligned doubles directly then no fixup is
1444 // needed. Else we split the double into 2 integer pieces and move it
1445 // piece-by-piece. Only happens when passing doubles into C code as the
1446 // Java calling convention forces doubles to be aligned.
1447 const bool Matcher::misaligned_doubles_ok = true;
1448
1449
1450 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1451 // Get the memory operand from the node
1452 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1453 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1454 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1455 uint opcnt = 1; // First operand
1456 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1457 while( idx >= skipped+num_edges ) {
1458 skipped += num_edges;
1459 opcnt++; // Bump operand count
1460 assert( opcnt < numopnds, "Accessing non-existent operand" );
1461 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1462 }
1463
1464 MachOper *memory = node->_opnds[opcnt];
1465 MachOper *new_memory = NULL;
1466 switch (memory->opcode()) {
1467 case DIRECT:
1468 case INDOFFSET32X:
1469 // No transformation necessary.
1470 return;
1471 case INDIRECT:
1472 new_memory = new (C) indirect_win95_safeOper( );
1473 break;
1474 case INDOFFSET8:
1475 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1476 break;
1477 case INDOFFSET32:
1478 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1479 break;
1480 case INDINDEXOFFSET:
1481 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1482 break;
1483 case INDINDEXSCALE:
1484 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1485 break;
1486 case INDINDEXSCALEOFFSET:
1487 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1488 break;
1489 case LOAD_LONG_INDIRECT:
1490 case LOAD_LONG_INDOFFSET32:
1491 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1492 return;
1493 default:
1494 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1495 return;
1496 }
1497 node->_opnds[opcnt] = new_memory;
1498 }
1499
1500 // Advertise here if the CPU requires explicit rounding operations
1501 // to implement the UseStrictFP mode.
1502 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1503
1504 // Are floats conerted to double when stored to stack during deoptimization?
1505 // On x32 it is stored with convertion only when FPU is used for floats.
1506 bool Matcher::float_in_double() { return (UseSSE == 0); }
1507
1508 // Do ints take an entire long register or just half?
1509 const bool Matcher::int_in_long = false;
1510
1511 // Return whether or not this register is ever used as an argument. This
1512 // function is used on startup to build the trampoline stubs in generateOptoStub.
1513 // Registers not mentioned will be killed by the VM call in the trampoline, and
1514 // arguments in those registers not be available to the callee.
1515 bool Matcher::can_be_java_arg( int reg ) {
1516 if( reg == ECX_num || reg == EDX_num ) return true;
1517 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1518 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1519 return false;
1520 }
1521
1522 bool Matcher::is_spillable_arg( int reg ) {
1523 return can_be_java_arg(reg);
1524 }
1525
1526 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1527 // Use hardware integer DIV instruction when
1528 // it is faster than a code which use multiply.
1529 // Only when constant divisor fits into 32 bit
1530 // (min_jint is excluded to get only correct
1531 // positive 32 bit values from negative).
1532 return VM_Version::has_fast_idiv() &&
1533 (divisor == (int)divisor && divisor != min_jint);
1534 }
1535
1536 // Register for DIVI projection of divmodI
1537 RegMask Matcher::divI_proj_mask() {
1538 return EAX_REG_mask();
1539 }
1540
1541 // Register for MODI projection of divmodI
1542 RegMask Matcher::modI_proj_mask() {
1543 return EDX_REG_mask();
1544 }
1545
1546 // Register for DIVL projection of divmodL
1547 RegMask Matcher::divL_proj_mask() {
1548 ShouldNotReachHere();
1549 return RegMask();
1550 }
1551
1552 // Register for MODL projection of divmodL
1553 RegMask Matcher::modL_proj_mask() {
1554 ShouldNotReachHere();
1555 return RegMask();
1556 }
1557
1558 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1559 return EBP_REG_mask();
1560 }
1561
1562 // Returns true if the high 32 bits of the value is known to be zero.
1563 bool is_operand_hi32_zero(Node* n) {
1564 int opc = n->Opcode();
1565 if (opc == Op_AndL) {
1566 Node* o2 = n->in(2);
1567 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1568 return true;
1569 }
1570 }
1571 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1572 return true;
1573 }
1574 return false;
1575 }
1576
1577 %}
1578
1579 //----------ENCODING BLOCK-----------------------------------------------------
1580 // This block specifies the encoding classes used by the compiler to output
1581 // byte streams. Encoding classes generate functions which are called by
1582 // Machine Instruction Nodes in order to generate the bit encoding of the
1583 // instruction. Operands specify their base encoding interface with the
1584 // interface keyword. There are currently supported four interfaces,
1585 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1586 // operand to generate a function which returns its register number when
1587 // queried. CONST_INTER causes an operand to generate a function which
1588 // returns the value of the constant when queried. MEMORY_INTER causes an
1589 // operand to generate four functions which return the Base Register, the
1590 // Index Register, the Scale Value, and the Offset Value of the operand when
1591 // queried. COND_INTER causes an operand to generate six functions which
1592 // return the encoding code (ie - encoding bits for the instruction)
1593 // associated with each basic boolean condition for a conditional instruction.
1594 // Instructions specify two basic values for encoding. They use the
1595 // ins_encode keyword to specify their encoding class (which must be one of
1596 // the class names specified in the encoding block), and they use the
1597 // opcode keyword to specify, in order, their primary, secondary, and
1598 // tertiary opcode. Only the opcode sections which a particular instruction
1599 // needs for encoding need to be specified.
1600 encode %{
1601 // Build emit functions for each basic byte or larger field in the intel
1602 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1603 // code in the enc_class source block. Emit functions will live in the
1604 // main source block for now. In future, we can generalize this by
1605 // adding a syntax that specifies the sizes of fields in an order,
1606 // so that the adlc can build the emit functions automagically
1607
1608 // Emit primary opcode
1609 enc_class OpcP %{
1610 emit_opcode(cbuf, $primary);
1611 %}
1612
1613 // Emit secondary opcode
1614 enc_class OpcS %{
1615 emit_opcode(cbuf, $secondary);
1616 %}
1617
1618 // Emit opcode directly
1619 enc_class Opcode(immI d8) %{
1620 emit_opcode(cbuf, $d8$$constant);
1621 %}
1622
1623 enc_class SizePrefix %{
1624 emit_opcode(cbuf,0x66);
1625 %}
1626
1627 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1628 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1629 %}
1630
1631 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1632 emit_opcode(cbuf,$opcode$$constant);
1633 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1634 %}
1635
1636 enc_class mov_r32_imm0( rRegI dst ) %{
1637 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1638 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1639 %}
1640
1641 enc_class cdq_enc %{
1642 // Full implementation of Java idiv and irem; checks for
1643 // special case as described in JVM spec., p.243 & p.271.
1644 //
1645 // normal case special case
1646 //
1647 // input : rax,: dividend min_int
1648 // reg: divisor -1
1649 //
1650 // output: rax,: quotient (= rax, idiv reg) min_int
1651 // rdx: remainder (= rax, irem reg) 0
1652 //
1653 // Code sequnce:
1654 //
1655 // 81 F8 00 00 00 80 cmp rax,80000000h
1656 // 0F 85 0B 00 00 00 jne normal_case
1657 // 33 D2 xor rdx,edx
1658 // 83 F9 FF cmp rcx,0FFh
1659 // 0F 84 03 00 00 00 je done
1660 // normal_case:
1661 // 99 cdq
1662 // F7 F9 idiv rax,ecx
1663 // done:
1664 //
1665 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1666 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1667 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1668 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1669 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1670 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1671 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1672 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1673 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1674 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1675 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1676 // normal_case:
1677 emit_opcode(cbuf,0x99); // cdq
1678 // idiv (note: must be emitted by the user of this rule)
1679 // normal:
1680 %}
1681
1682 // Dense encoding for older common ops
1683 enc_class Opc_plus(immI opcode, rRegI reg) %{
1684 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1685 %}
1686
1687
1688 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1689 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1690 // Check for 8-bit immediate, and set sign extend bit in opcode
1691 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1692 emit_opcode(cbuf, $primary | 0x02);
1693 }
1694 else { // If 32-bit immediate
1695 emit_opcode(cbuf, $primary);
1696 }
1697 %}
1698
1699 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1700 // Emit primary opcode and set sign-extend bit
1701 // Check for 8-bit immediate, and set sign extend bit in opcode
1702 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1703 emit_opcode(cbuf, $primary | 0x02); }
1704 else { // If 32-bit immediate
1705 emit_opcode(cbuf, $primary);
1706 }
1707 // Emit r/m byte with secondary opcode, after primary opcode.
1708 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1709 %}
1710
1711 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1712 // Check for 8-bit immediate, and set sign extend bit in opcode
1713 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1714 $$$emit8$imm$$constant;
1715 }
1716 else { // If 32-bit immediate
1717 // Output immediate
1718 $$$emit32$imm$$constant;
1719 }
1720 %}
1721
1722 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1723 // Emit primary opcode and set sign-extend bit
1724 // Check for 8-bit immediate, and set sign extend bit in opcode
1725 int con = (int)$imm$$constant; // Throw away top bits
1726 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1727 // Emit r/m byte with secondary opcode, after primary opcode.
1728 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1729 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1730 else emit_d32(cbuf,con);
1731 %}
1732
1733 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1734 // Emit primary opcode and set sign-extend bit
1735 // Check for 8-bit immediate, and set sign extend bit in opcode
1736 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1737 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1738 // Emit r/m byte with tertiary opcode, after primary opcode.
1739 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1740 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1741 else emit_d32(cbuf,con);
1742 %}
1743
1744 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1745 emit_cc(cbuf, $secondary, $dst$$reg );
1746 %}
1747
1748 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1749 int destlo = $dst$$reg;
1750 int desthi = HIGH_FROM_LOW(destlo);
1751 // bswap lo
1752 emit_opcode(cbuf, 0x0F);
1753 emit_cc(cbuf, 0xC8, destlo);
1754 // bswap hi
1755 emit_opcode(cbuf, 0x0F);
1756 emit_cc(cbuf, 0xC8, desthi);
1757 // xchg lo and hi
1758 emit_opcode(cbuf, 0x87);
1759 emit_rm(cbuf, 0x3, destlo, desthi);
1760 %}
1761
1762 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1763 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1764 %}
1765
1766 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1767 $$$emit8$primary;
1768 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1769 %}
1770
1771 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1772 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1773 emit_d8(cbuf, op >> 8 );
1774 emit_d8(cbuf, op & 255);
1775 %}
1776
1777 // emulate a CMOV with a conditional branch around a MOV
1778 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1779 // Invert sense of branch from sense of CMOV
1780 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1781 emit_d8( cbuf, $brOffs$$constant );
1782 %}
1783
1784 enc_class enc_PartialSubtypeCheck( ) %{
1785 Register Redi = as_Register(EDI_enc); // result register
1786 Register Reax = as_Register(EAX_enc); // super class
1787 Register Recx = as_Register(ECX_enc); // killed
1788 Register Resi = as_Register(ESI_enc); // sub class
1789 Label miss;
1790
1791 MacroAssembler _masm(&cbuf);
1792 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1793 NULL, &miss,
1794 /*set_cond_codes:*/ true);
1795 if ($primary) {
1796 __ xorptr(Redi, Redi);
1797 }
1798 __ bind(miss);
1799 %}
1800
1801 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1802 MacroAssembler masm(&cbuf);
1803 int start = masm.offset();
1804 if (UseSSE >= 2) {
1805 if (VerifyFPU) {
1806 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1807 }
1808 } else {
1809 // External c_calling_convention expects the FPU stack to be 'clean'.
1810 // Compiled code leaves it dirty. Do cleanup now.
1811 masm.empty_FPU_stack();
1812 }
1813 if (sizeof_FFree_Float_Stack_All == -1) {
1814 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1815 } else {
1816 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1817 }
1818 %}
1819
1820 enc_class Verify_FPU_For_Leaf %{
1821 if( VerifyFPU ) {
1822 MacroAssembler masm(&cbuf);
1823 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1824 }
1825 %}
1826
1827 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1828 // This is the instruction starting address for relocation info.
1829 cbuf.set_insts_mark();
1830 $$$emit8$primary;
1831 // CALL directly to the runtime
1832 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1833 runtime_call_Relocation::spec(), RELOC_IMM32 );
1834
1835 if (UseSSE >= 2) {
1836 MacroAssembler _masm(&cbuf);
1837 BasicType rt = tf()->return_type();
1838
1839 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1840 // A C runtime call where the return value is unused. In SSE2+
1841 // mode the result needs to be removed from the FPU stack. It's
1842 // likely that this function call could be removed by the
1843 // optimizer if the C function is a pure function.
1844 __ ffree(0);
1845 } else if (rt == T_FLOAT) {
1846 __ lea(rsp, Address(rsp, -4));
1847 __ fstp_s(Address(rsp, 0));
1848 __ movflt(xmm0, Address(rsp, 0));
1849 __ lea(rsp, Address(rsp, 4));
1850 } else if (rt == T_DOUBLE) {
1851 __ lea(rsp, Address(rsp, -8));
1852 __ fstp_d(Address(rsp, 0));
1853 __ movdbl(xmm0, Address(rsp, 0));
1854 __ lea(rsp, Address(rsp, 8));
1855 }
1856 }
1857 %}
1858
1859
1860 enc_class pre_call_FPU %{
1861 // If method sets FPU control word restore it here
1862 debug_only(int off0 = cbuf.insts_size());
1863 if( Compile::current()->in_24_bit_fp_mode() ) {
1864 MacroAssembler masm(&cbuf);
1865 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1866 }
1867 debug_only(int off1 = cbuf.insts_size());
1868 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1869 %}
1870
1871 enc_class post_call_FPU %{
1872 // If method sets FPU control word do it here also
1873 if( Compile::current()->in_24_bit_fp_mode() ) {
1874 MacroAssembler masm(&cbuf);
1875 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1876 }
1877 %}
1878
1879 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1880 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1881 // who we intended to call.
1882 cbuf.set_insts_mark();
1883 $$$emit8$primary;
1884 if ( !_method ) {
1885 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1886 runtime_call_Relocation::spec(), RELOC_IMM32 );
1887 } else if(_optimized_virtual) {
1888 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1889 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1890 } else {
1891 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1892 static_call_Relocation::spec(), RELOC_IMM32 );
1893 }
1894 if( _method ) { // Emit stub for static call
1895 emit_java_to_interp(cbuf);
1896 }
1897 %}
1898
1899 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1900 MacroAssembler _masm(&cbuf);
1901 __ ic_call((address)$meth$$method);
1902 %}
1903
1904 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1905 int disp = in_bytes(Method::from_compiled_offset());
1906 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1907
1908 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1909 cbuf.set_insts_mark();
1910 $$$emit8$primary;
1911 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1912 emit_d8(cbuf, disp); // Displacement
1913
1914 %}
1915
1916 // Following encoding is no longer used, but may be restored if calling
1917 // convention changes significantly.
1918 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1919 //
1920 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1921 // // int ic_reg = Matcher::inline_cache_reg();
1922 // // int ic_encode = Matcher::_regEncode[ic_reg];
1923 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1924 // // int imo_encode = Matcher::_regEncode[imo_reg];
1925 //
1926 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1927 // // // so we load it immediately before the call
1928 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1929 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1930 //
1931 // // xor rbp,ebp
1932 // emit_opcode(cbuf, 0x33);
1933 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1934 //
1935 // // CALL to interpreter.
1936 // cbuf.set_insts_mark();
1937 // $$$emit8$primary;
1938 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1939 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1940 // %}
1941
1942 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1943 $$$emit8$primary;
1944 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1945 $$$emit8$shift$$constant;
1946 %}
1947
1948 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1949 // Load immediate does not have a zero or sign extended version
1950 // for 8-bit immediates
1951 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1952 $$$emit32$src$$constant;
1953 %}
1954
1955 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1956 // Load immediate does not have a zero or sign extended version
1957 // for 8-bit immediates
1958 emit_opcode(cbuf, $primary + $dst$$reg);
1959 $$$emit32$src$$constant;
1960 %}
1961
1962 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1963 // Load immediate does not have a zero or sign extended version
1964 // for 8-bit immediates
1965 int dst_enc = $dst$$reg;
1966 int src_con = $src$$constant & 0x0FFFFFFFFL;
1967 if (src_con == 0) {
1968 // xor dst, dst
1969 emit_opcode(cbuf, 0x33);
1970 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1971 } else {
1972 emit_opcode(cbuf, $primary + dst_enc);
1973 emit_d32(cbuf, src_con);
1974 }
1975 %}
1976
1977 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1978 // Load immediate does not have a zero or sign extended version
1979 // for 8-bit immediates
1980 int dst_enc = $dst$$reg + 2;
1981 int src_con = ((julong)($src$$constant)) >> 32;
1982 if (src_con == 0) {
1983 // xor dst, dst
1984 emit_opcode(cbuf, 0x33);
1985 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1986 } else {
1987 emit_opcode(cbuf, $primary + dst_enc);
1988 emit_d32(cbuf, src_con);
1989 }
1990 %}
1991
1992
1993 // Encode a reg-reg copy. If it is useless, then empty encoding.
1994 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1995 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1996 %}
1997
1998 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1999 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2000 %}
2001
2002 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2003 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2004 %}
2005
2006 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2007 $$$emit8$primary;
2008 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2009 %}
2010
2011 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2012 $$$emit8$secondary;
2013 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2014 %}
2015
2016 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2017 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2018 %}
2019
2020 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2021 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2022 %}
2023
2024 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2025 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2026 %}
2027
2028 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2029 // Output immediate
2030 $$$emit32$src$$constant;
2031 %}
2032
2033 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2034 // Output Float immediate bits
2035 jfloat jf = $src$$constant;
2036 int jf_as_bits = jint_cast( jf );
2037 emit_d32(cbuf, jf_as_bits);
2038 %}
2039
2040 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2041 // Output Float immediate bits
2042 jfloat jf = $src$$constant;
2043 int jf_as_bits = jint_cast( jf );
2044 emit_d32(cbuf, jf_as_bits);
2045 %}
2046
2047 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2048 // Output immediate
2049 $$$emit16$src$$constant;
2050 %}
2051
2052 enc_class Con_d32(immI src) %{
2053 emit_d32(cbuf,$src$$constant);
2054 %}
2055
2056 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2057 // Output immediate memory reference
2058 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2059 emit_d32(cbuf, 0x00);
2060 %}
2061
2062 enc_class lock_prefix( ) %{
2063 if( os::is_MP() )
2064 emit_opcode(cbuf,0xF0); // [Lock]
2065 %}
2066
2067 // Cmp-xchg long value.
2068 // Note: we need to swap rbx, and rcx before and after the
2069 // cmpxchg8 instruction because the instruction uses
2070 // rcx as the high order word of the new value to store but
2071 // our register encoding uses rbx,.
2072 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2073
2074 // XCHG rbx,ecx
2075 emit_opcode(cbuf,0x87);
2076 emit_opcode(cbuf,0xD9);
2077 // [Lock]
2078 if( os::is_MP() )
2079 emit_opcode(cbuf,0xF0);
2080 // CMPXCHG8 [Eptr]
2081 emit_opcode(cbuf,0x0F);
2082 emit_opcode(cbuf,0xC7);
2083 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2084 // XCHG rbx,ecx
2085 emit_opcode(cbuf,0x87);
2086 emit_opcode(cbuf,0xD9);
2087 %}
2088
2089 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2090 // [Lock]
2091 if( os::is_MP() )
2092 emit_opcode(cbuf,0xF0);
2093
2094 // CMPXCHG [Eptr]
2095 emit_opcode(cbuf,0x0F);
2096 emit_opcode(cbuf,0xB1);
2097 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2098 %}
2099
2100 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2101 int res_encoding = $res$$reg;
2102
2103 // MOV res,0
2104 emit_opcode( cbuf, 0xB8 + res_encoding);
2105 emit_d32( cbuf, 0 );
2106 // JNE,s fail
2107 emit_opcode(cbuf,0x75);
2108 emit_d8(cbuf, 5 );
2109 // MOV res,1
2110 emit_opcode( cbuf, 0xB8 + res_encoding);
2111 emit_d32( cbuf, 1 );
2112 // fail:
2113 %}
2114
2115 enc_class set_instruction_start( ) %{
2116 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2117 %}
2118
2119 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2120 int reg_encoding = $ereg$$reg;
2121 int base = $mem$$base;
2122 int index = $mem$$index;
2123 int scale = $mem$$scale;
2124 int displace = $mem$$disp;
2125 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2126 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2127 %}
2128
2129 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2130 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2131 int base = $mem$$base;
2132 int index = $mem$$index;
2133 int scale = $mem$$scale;
2134 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2135 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2136 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2137 %}
2138
2139 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2140 int r1, r2;
2141 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2142 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2143 emit_opcode(cbuf,0x0F);
2144 emit_opcode(cbuf,$tertiary);
2145 emit_rm(cbuf, 0x3, r1, r2);
2146 emit_d8(cbuf,$cnt$$constant);
2147 emit_d8(cbuf,$primary);
2148 emit_rm(cbuf, 0x3, $secondary, r1);
2149 emit_d8(cbuf,$cnt$$constant);
2150 %}
2151
2152 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2153 emit_opcode( cbuf, 0x8B ); // Move
2154 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2155 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2156 emit_d8(cbuf,$primary);
2157 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2158 emit_d8(cbuf,$cnt$$constant-32);
2159 }
2160 emit_d8(cbuf,$primary);
2161 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2162 emit_d8(cbuf,31);
2163 %}
2164
2165 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2166 int r1, r2;
2167 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2168 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2169
2170 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2171 emit_rm(cbuf, 0x3, r1, r2);
2172 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2173 emit_opcode(cbuf,$primary);
2174 emit_rm(cbuf, 0x3, $secondary, r1);
2175 emit_d8(cbuf,$cnt$$constant-32);
2176 }
2177 emit_opcode(cbuf,0x33); // XOR r2,r2
2178 emit_rm(cbuf, 0x3, r2, r2);
2179 %}
2180
2181 // Clone of RegMem but accepts an extra parameter to access each
2182 // half of a double in memory; it never needs relocation info.
2183 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2184 emit_opcode(cbuf,$opcode$$constant);
2185 int reg_encoding = $rm_reg$$reg;
2186 int base = $mem$$base;
2187 int index = $mem$$index;
2188 int scale = $mem$$scale;
2189 int displace = $mem$$disp + $disp_for_half$$constant;
2190 relocInfo::relocType disp_reloc = relocInfo::none;
2191 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2192 %}
2193
2194 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2195 //
2196 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2197 // and it never needs relocation information.
2198 // Frequently used to move data between FPU's Stack Top and memory.
2199 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2200 int rm_byte_opcode = $rm_opcode$$constant;
2201 int base = $mem$$base;
2202 int index = $mem$$index;
2203 int scale = $mem$$scale;
2204 int displace = $mem$$disp;
2205 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2206 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2207 %}
2208
2209 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2210 int rm_byte_opcode = $rm_opcode$$constant;
2211 int base = $mem$$base;
2212 int index = $mem$$index;
2213 int scale = $mem$$scale;
2214 int displace = $mem$$disp;
2215 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2216 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2217 %}
2218
2219 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2220 int reg_encoding = $dst$$reg;
2221 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2222 int index = 0x04; // 0x04 indicates no index
2223 int scale = 0x00; // 0x00 indicates no scale
2224 int displace = $src1$$constant; // 0x00 indicates no displacement
2225 relocInfo::relocType disp_reloc = relocInfo::none;
2226 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2227 %}
2228
2229 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2230 // Compare dst,src
2231 emit_opcode(cbuf,0x3B);
2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2233 // jmp dst < src around move
2234 emit_opcode(cbuf,0x7C);
2235 emit_d8(cbuf,2);
2236 // move dst,src
2237 emit_opcode(cbuf,0x8B);
2238 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2239 %}
2240
2241 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2242 // Compare dst,src
2243 emit_opcode(cbuf,0x3B);
2244 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2245 // jmp dst > src around move
2246 emit_opcode(cbuf,0x7F);
2247 emit_d8(cbuf,2);
2248 // move dst,src
2249 emit_opcode(cbuf,0x8B);
2250 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2251 %}
2252
2253 enc_class enc_FPR_store(memory mem, regDPR src) %{
2254 // If src is FPR1, we can just FST to store it.
2255 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2256 int reg_encoding = 0x2; // Just store
2257 int base = $mem$$base;
2258 int index = $mem$$index;
2259 int scale = $mem$$scale;
2260 int displace = $mem$$disp;
2261 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2262 if( $src$$reg != FPR1L_enc ) {
2263 reg_encoding = 0x3; // Store & pop
2264 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2265 emit_d8( cbuf, 0xC0-1+$src$$reg );
2266 }
2267 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2268 emit_opcode(cbuf,$primary);
2269 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2270 %}
2271
2272 enc_class neg_reg(rRegI dst) %{
2273 // NEG $dst
2274 emit_opcode(cbuf,0xF7);
2275 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2276 %}
2277
2278 enc_class setLT_reg(eCXRegI dst) %{
2279 // SETLT $dst
2280 emit_opcode(cbuf,0x0F);
2281 emit_opcode(cbuf,0x9C);
2282 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2283 %}
2284
2285 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2286 int tmpReg = $tmp$$reg;
2287
2288 // SUB $p,$q
2289 emit_opcode(cbuf,0x2B);
2290 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2291 // SBB $tmp,$tmp
2292 emit_opcode(cbuf,0x1B);
2293 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2294 // AND $tmp,$y
2295 emit_opcode(cbuf,0x23);
2296 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2297 // ADD $p,$tmp
2298 emit_opcode(cbuf,0x03);
2299 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2300 %}
2301
2302 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2303 int tmpReg = $tmp$$reg;
2304
2305 // SUB $p,$q
2306 emit_opcode(cbuf,0x2B);
2307 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2308 // SBB $tmp,$tmp
2309 emit_opcode(cbuf,0x1B);
2310 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2311 // AND $tmp,$y
2312 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2313 emit_opcode(cbuf,0x23);
2314 int reg_encoding = tmpReg;
2315 int base = $mem$$base;
2316 int index = $mem$$index;
2317 int scale = $mem$$scale;
2318 int displace = $mem$$disp;
2319 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2320 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2321 // ADD $p,$tmp
2322 emit_opcode(cbuf,0x03);
2323 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2324 %}
2325
2326 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2327 // TEST shift,32
2328 emit_opcode(cbuf,0xF7);
2329 emit_rm(cbuf, 0x3, 0, ECX_enc);
2330 emit_d32(cbuf,0x20);
2331 // JEQ,s small
2332 emit_opcode(cbuf, 0x74);
2333 emit_d8(cbuf, 0x04);
2334 // MOV $dst.hi,$dst.lo
2335 emit_opcode( cbuf, 0x8B );
2336 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2337 // CLR $dst.lo
2338 emit_opcode(cbuf, 0x33);
2339 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2340 // small:
2341 // SHLD $dst.hi,$dst.lo,$shift
2342 emit_opcode(cbuf,0x0F);
2343 emit_opcode(cbuf,0xA5);
2344 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2345 // SHL $dst.lo,$shift"
2346 emit_opcode(cbuf,0xD3);
2347 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2348 %}
2349
2350 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2351 // TEST shift,32
2352 emit_opcode(cbuf,0xF7);
2353 emit_rm(cbuf, 0x3, 0, ECX_enc);
2354 emit_d32(cbuf,0x20);
2355 // JEQ,s small
2356 emit_opcode(cbuf, 0x74);
2357 emit_d8(cbuf, 0x04);
2358 // MOV $dst.lo,$dst.hi
2359 emit_opcode( cbuf, 0x8B );
2360 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2361 // CLR $dst.hi
2362 emit_opcode(cbuf, 0x33);
2363 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2364 // small:
2365 // SHRD $dst.lo,$dst.hi,$shift
2366 emit_opcode(cbuf,0x0F);
2367 emit_opcode(cbuf,0xAD);
2368 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2369 // SHR $dst.hi,$shift"
2370 emit_opcode(cbuf,0xD3);
2371 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2372 %}
2373
2374 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2375 // TEST shift,32
2376 emit_opcode(cbuf,0xF7);
2377 emit_rm(cbuf, 0x3, 0, ECX_enc);
2378 emit_d32(cbuf,0x20);
2379 // JEQ,s small
2380 emit_opcode(cbuf, 0x74);
2381 emit_d8(cbuf, 0x05);
2382 // MOV $dst.lo,$dst.hi
2383 emit_opcode( cbuf, 0x8B );
2384 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2385 // SAR $dst.hi,31
2386 emit_opcode(cbuf, 0xC1);
2387 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2388 emit_d8(cbuf, 0x1F );
2389 // small:
2390 // SHRD $dst.lo,$dst.hi,$shift
2391 emit_opcode(cbuf,0x0F);
2392 emit_opcode(cbuf,0xAD);
2393 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2394 // SAR $dst.hi,$shift"
2395 emit_opcode(cbuf,0xD3);
2396 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2397 %}
2398
2399
2400 // ----------------- Encodings for floating point unit -----------------
2401 // May leave result in FPU-TOS or FPU reg depending on opcodes
2402 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2403 $$$emit8$primary;
2404 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2405 %}
2406
2407 // Pop argument in FPR0 with FSTP ST(0)
2408 enc_class PopFPU() %{
2409 emit_opcode( cbuf, 0xDD );
2410 emit_d8( cbuf, 0xD8 );
2411 %}
2412
2413 // !!!!! equivalent to Pop_Reg_F
2414 enc_class Pop_Reg_DPR( regDPR dst ) %{
2415 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2416 emit_d8( cbuf, 0xD8+$dst$$reg );
2417 %}
2418
2419 enc_class Push_Reg_DPR( regDPR dst ) %{
2420 emit_opcode( cbuf, 0xD9 );
2421 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2422 %}
2423
2424 enc_class strictfp_bias1( regDPR dst ) %{
2425 emit_opcode( cbuf, 0xDB ); // FLD m80real
2426 emit_opcode( cbuf, 0x2D );
2427 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2428 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2429 emit_opcode( cbuf, 0xC8+$dst$$reg );
2430 %}
2431
2432 enc_class strictfp_bias2( regDPR dst ) %{
2433 emit_opcode( cbuf, 0xDB ); // FLD m80real
2434 emit_opcode( cbuf, 0x2D );
2435 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2436 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2437 emit_opcode( cbuf, 0xC8+$dst$$reg );
2438 %}
2439
2440 // Special case for moving an integer register to a stack slot.
2441 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2442 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2443 %}
2444
2445 // Special case for moving a register to a stack slot.
2446 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2447 // Opcode already emitted
2448 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2449 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2450 emit_d32(cbuf, $dst$$disp); // Displacement
2451 %}
2452
2453 // Push the integer in stackSlot 'src' onto FP-stack
2454 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2455 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2456 %}
2457
2458 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2459 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2460 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2461 %}
2462
2463 // Same as Pop_Mem_F except for opcode
2464 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2465 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2466 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2467 %}
2468
2469 enc_class Pop_Reg_FPR( regFPR dst ) %{
2470 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2471 emit_d8( cbuf, 0xD8+$dst$$reg );
2472 %}
2473
2474 enc_class Push_Reg_FPR( regFPR dst ) %{
2475 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2476 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2477 %}
2478
2479 // Push FPU's float to a stack-slot, and pop FPU-stack
2480 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2481 int pop = 0x02;
2482 if ($src$$reg != FPR1L_enc) {
2483 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2484 emit_d8( cbuf, 0xC0-1+$src$$reg );
2485 pop = 0x03;
2486 }
2487 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2488 %}
2489
2490 // Push FPU's double to a stack-slot, and pop FPU-stack
2491 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2492 int pop = 0x02;
2493 if ($src$$reg != FPR1L_enc) {
2494 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2495 emit_d8( cbuf, 0xC0-1+$src$$reg );
2496 pop = 0x03;
2497 }
2498 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2499 %}
2500
2501 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2502 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2503 int pop = 0xD0 - 1; // -1 since we skip FLD
2504 if ($src$$reg != FPR1L_enc) {
2505 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2506 emit_d8( cbuf, 0xC0-1+$src$$reg );
2507 pop = 0xD8;
2508 }
2509 emit_opcode( cbuf, 0xDD );
2510 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2511 %}
2512
2513
2514 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2515 // load dst in FPR0
2516 emit_opcode( cbuf, 0xD9 );
2517 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2518 if ($src$$reg != FPR1L_enc) {
2519 // fincstp
2520 emit_opcode (cbuf, 0xD9);
2521 emit_opcode (cbuf, 0xF7);
2522 // swap src with FPR1:
2523 // FXCH FPR1 with src
2524 emit_opcode(cbuf, 0xD9);
2525 emit_d8(cbuf, 0xC8-1+$src$$reg );
2526 // fdecstp
2527 emit_opcode (cbuf, 0xD9);
2528 emit_opcode (cbuf, 0xF6);
2529 }
2530 %}
2531
2532 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2533 MacroAssembler _masm(&cbuf);
2534 __ subptr(rsp, 8);
2535 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2536 __ fld_d(Address(rsp, 0));
2537 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2538 __ fld_d(Address(rsp, 0));
2539 %}
2540
2541 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2542 MacroAssembler _masm(&cbuf);
2543 __ subptr(rsp, 4);
2544 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2545 __ fld_s(Address(rsp, 0));
2546 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2547 __ fld_s(Address(rsp, 0));
2548 %}
2549
2550 enc_class Push_ResultD(regD dst) %{
2551 MacroAssembler _masm(&cbuf);
2552 __ fstp_d(Address(rsp, 0));
2553 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2554 __ addptr(rsp, 8);
2555 %}
2556
2557 enc_class Push_ResultF(regF dst, immI d8) %{
2558 MacroAssembler _masm(&cbuf);
2559 __ fstp_s(Address(rsp, 0));
2560 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2561 __ addptr(rsp, $d8$$constant);
2562 %}
2563
2564 enc_class Push_SrcD(regD src) %{
2565 MacroAssembler _masm(&cbuf);
2566 __ subptr(rsp, 8);
2567 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2568 __ fld_d(Address(rsp, 0));
2569 %}
2570
2571 enc_class push_stack_temp_qword() %{
2572 MacroAssembler _masm(&cbuf);
2573 __ subptr(rsp, 8);
2574 %}
2575
2576 enc_class pop_stack_temp_qword() %{
2577 MacroAssembler _masm(&cbuf);
2578 __ addptr(rsp, 8);
2579 %}
2580
2581 enc_class push_xmm_to_fpr1(regD src) %{
2582 MacroAssembler _masm(&cbuf);
2583 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2584 __ fld_d(Address(rsp, 0));
2585 %}
2586
2587 enc_class Push_Result_Mod_DPR( regDPR src) %{
2588 if ($src$$reg != FPR1L_enc) {
2589 // fincstp
2590 emit_opcode (cbuf, 0xD9);
2591 emit_opcode (cbuf, 0xF7);
2592 // FXCH FPR1 with src
2593 emit_opcode(cbuf, 0xD9);
2594 emit_d8(cbuf, 0xC8-1+$src$$reg );
2595 // fdecstp
2596 emit_opcode (cbuf, 0xD9);
2597 emit_opcode (cbuf, 0xF6);
2598 }
2599 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2600 // // FSTP FPR$dst$$reg
2601 // emit_opcode( cbuf, 0xDD );
2602 // emit_d8( cbuf, 0xD8+$dst$$reg );
2603 %}
2604
2605 enc_class fnstsw_sahf_skip_parity() %{
2606 // fnstsw ax
2607 emit_opcode( cbuf, 0xDF );
2608 emit_opcode( cbuf, 0xE0 );
2609 // sahf
2610 emit_opcode( cbuf, 0x9E );
2611 // jnp ::skip
2612 emit_opcode( cbuf, 0x7B );
2613 emit_opcode( cbuf, 0x05 );
2614 %}
2615
2616 enc_class emitModDPR() %{
2617 // fprem must be iterative
2618 // :: loop
2619 // fprem
2620 emit_opcode( cbuf, 0xD9 );
2621 emit_opcode( cbuf, 0xF8 );
2622 // wait
2623 emit_opcode( cbuf, 0x9b );
2624 // fnstsw ax
2625 emit_opcode( cbuf, 0xDF );
2626 emit_opcode( cbuf, 0xE0 );
2627 // sahf
2628 emit_opcode( cbuf, 0x9E );
2629 // jp ::loop
2630 emit_opcode( cbuf, 0x0F );
2631 emit_opcode( cbuf, 0x8A );
2632 emit_opcode( cbuf, 0xF4 );
2633 emit_opcode( cbuf, 0xFF );
2634 emit_opcode( cbuf, 0xFF );
2635 emit_opcode( cbuf, 0xFF );
2636 %}
2637
2638 enc_class fpu_flags() %{
2639 // fnstsw_ax
2640 emit_opcode( cbuf, 0xDF);
2641 emit_opcode( cbuf, 0xE0);
2642 // test ax,0x0400
2643 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2644 emit_opcode( cbuf, 0xA9 );
2645 emit_d16 ( cbuf, 0x0400 );
2646 // // // This sequence works, but stalls for 12-16 cycles on PPro
2647 // // test rax,0x0400
2648 // emit_opcode( cbuf, 0xA9 );
2649 // emit_d32 ( cbuf, 0x00000400 );
2650 //
2651 // jz exit (no unordered comparison)
2652 emit_opcode( cbuf, 0x74 );
2653 emit_d8 ( cbuf, 0x02 );
2654 // mov ah,1 - treat as LT case (set carry flag)
2655 emit_opcode( cbuf, 0xB4 );
2656 emit_d8 ( cbuf, 0x01 );
2657 // sahf
2658 emit_opcode( cbuf, 0x9E);
2659 %}
2660
2661 enc_class cmpF_P6_fixup() %{
2662 // Fixup the integer flags in case comparison involved a NaN
2663 //
2664 // JNP exit (no unordered comparison, P-flag is set by NaN)
2665 emit_opcode( cbuf, 0x7B );
2666 emit_d8 ( cbuf, 0x03 );
2667 // MOV AH,1 - treat as LT case (set carry flag)
2668 emit_opcode( cbuf, 0xB4 );
2669 emit_d8 ( cbuf, 0x01 );
2670 // SAHF
2671 emit_opcode( cbuf, 0x9E);
2672 // NOP // target for branch to avoid branch to branch
2673 emit_opcode( cbuf, 0x90);
2674 %}
2675
2676 // fnstsw_ax();
2677 // sahf();
2678 // movl(dst, nan_result);
2679 // jcc(Assembler::parity, exit);
2680 // movl(dst, less_result);
2681 // jcc(Assembler::below, exit);
2682 // movl(dst, equal_result);
2683 // jcc(Assembler::equal, exit);
2684 // movl(dst, greater_result);
2685
2686 // less_result = 1;
2687 // greater_result = -1;
2688 // equal_result = 0;
2689 // nan_result = -1;
2690
2691 enc_class CmpF_Result(rRegI dst) %{
2692 // fnstsw_ax();
2693 emit_opcode( cbuf, 0xDF);
2694 emit_opcode( cbuf, 0xE0);
2695 // sahf
2696 emit_opcode( cbuf, 0x9E);
2697 // movl(dst, nan_result);
2698 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2699 emit_d32( cbuf, -1 );
2700 // jcc(Assembler::parity, exit);
2701 emit_opcode( cbuf, 0x7A );
2702 emit_d8 ( cbuf, 0x13 );
2703 // movl(dst, less_result);
2704 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2705 emit_d32( cbuf, -1 );
2706 // jcc(Assembler::below, exit);
2707 emit_opcode( cbuf, 0x72 );
2708 emit_d8 ( cbuf, 0x0C );
2709 // movl(dst, equal_result);
2710 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2711 emit_d32( cbuf, 0 );
2712 // jcc(Assembler::equal, exit);
2713 emit_opcode( cbuf, 0x74 );
2714 emit_d8 ( cbuf, 0x05 );
2715 // movl(dst, greater_result);
2716 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2717 emit_d32( cbuf, 1 );
2718 %}
2719
2720
2721 // Compare the longs and set flags
2722 // BROKEN! Do Not use as-is
2723 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2724 // CMP $src1.hi,$src2.hi
2725 emit_opcode( cbuf, 0x3B );
2726 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2727 // JNE,s done
2728 emit_opcode(cbuf,0x75);
2729 emit_d8(cbuf, 2 );
2730 // CMP $src1.lo,$src2.lo
2731 emit_opcode( cbuf, 0x3B );
2732 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2733 // done:
2734 %}
2735
2736 enc_class convert_int_long( regL dst, rRegI src ) %{
2737 // mov $dst.lo,$src
2738 int dst_encoding = $dst$$reg;
2739 int src_encoding = $src$$reg;
2740 encode_Copy( cbuf, dst_encoding , src_encoding );
2741 // mov $dst.hi,$src
2742 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2743 // sar $dst.hi,31
2744 emit_opcode( cbuf, 0xC1 );
2745 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2746 emit_d8(cbuf, 0x1F );
2747 %}
2748
2749 enc_class convert_long_double( eRegL src ) %{
2750 // push $src.hi
2751 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2752 // push $src.lo
2753 emit_opcode(cbuf, 0x50+$src$$reg );
2754 // fild 64-bits at [SP]
2755 emit_opcode(cbuf,0xdf);
2756 emit_d8(cbuf, 0x6C);
2757 emit_d8(cbuf, 0x24);
2758 emit_d8(cbuf, 0x00);
2759 // pop stack
2760 emit_opcode(cbuf, 0x83); // add SP, #8
2761 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2762 emit_d8(cbuf, 0x8);
2763 %}
2764
2765 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2766 // IMUL EDX:EAX,$src1
2767 emit_opcode( cbuf, 0xF7 );
2768 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2769 // SAR EDX,$cnt-32
2770 int shift_count = ((int)$cnt$$constant) - 32;
2771 if (shift_count > 0) {
2772 emit_opcode(cbuf, 0xC1);
2773 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2774 emit_d8(cbuf, shift_count);
2775 }
2776 %}
2777
2778 // this version doesn't have add sp, 8
2779 enc_class convert_long_double2( eRegL src ) %{
2780 // push $src.hi
2781 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2782 // push $src.lo
2783 emit_opcode(cbuf, 0x50+$src$$reg );
2784 // fild 64-bits at [SP]
2785 emit_opcode(cbuf,0xdf);
2786 emit_d8(cbuf, 0x6C);
2787 emit_d8(cbuf, 0x24);
2788 emit_d8(cbuf, 0x00);
2789 %}
2790
2791 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2792 // Basic idea: long = (long)int * (long)int
2793 // IMUL EDX:EAX, src
2794 emit_opcode( cbuf, 0xF7 );
2795 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2796 %}
2797
2798 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2799 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2800 // MUL EDX:EAX, src
2801 emit_opcode( cbuf, 0xF7 );
2802 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2803 %}
2804
2805 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2806 // Basic idea: lo(result) = lo(x_lo * y_lo)
2807 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2808 // MOV $tmp,$src.lo
2809 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2810 // IMUL $tmp,EDX
2811 emit_opcode( cbuf, 0x0F );
2812 emit_opcode( cbuf, 0xAF );
2813 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2814 // MOV EDX,$src.hi
2815 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2816 // IMUL EDX,EAX
2817 emit_opcode( cbuf, 0x0F );
2818 emit_opcode( cbuf, 0xAF );
2819 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2820 // ADD $tmp,EDX
2821 emit_opcode( cbuf, 0x03 );
2822 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2823 // MUL EDX:EAX,$src.lo
2824 emit_opcode( cbuf, 0xF7 );
2825 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2826 // ADD EDX,ESI
2827 emit_opcode( cbuf, 0x03 );
2828 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2829 %}
2830
2831 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2832 // Basic idea: lo(result) = lo(src * y_lo)
2833 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2834 // IMUL $tmp,EDX,$src
2835 emit_opcode( cbuf, 0x6B );
2836 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2837 emit_d8( cbuf, (int)$src$$constant );
2838 // MOV EDX,$src
2839 emit_opcode(cbuf, 0xB8 + EDX_enc);
2840 emit_d32( cbuf, (int)$src$$constant );
2841 // MUL EDX:EAX,EDX
2842 emit_opcode( cbuf, 0xF7 );
2843 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2844 // ADD EDX,ESI
2845 emit_opcode( cbuf, 0x03 );
2846 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2847 %}
2848
2849 enc_class long_div( eRegL src1, eRegL src2 ) %{
2850 // PUSH src1.hi
2851 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2852 // PUSH src1.lo
2853 emit_opcode(cbuf, 0x50+$src1$$reg );
2854 // PUSH src2.hi
2855 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2856 // PUSH src2.lo
2857 emit_opcode(cbuf, 0x50+$src2$$reg );
2858 // CALL directly to the runtime
2859 cbuf.set_insts_mark();
2860 emit_opcode(cbuf,0xE8); // Call into runtime
2861 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2862 // Restore stack
2863 emit_opcode(cbuf, 0x83); // add SP, #framesize
2864 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2865 emit_d8(cbuf, 4*4);
2866 %}
2867
2868 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2869 // PUSH src1.hi
2870 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2871 // PUSH src1.lo
2872 emit_opcode(cbuf, 0x50+$src1$$reg );
2873 // PUSH src2.hi
2874 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2875 // PUSH src2.lo
2876 emit_opcode(cbuf, 0x50+$src2$$reg );
2877 // CALL directly to the runtime
2878 cbuf.set_insts_mark();
2879 emit_opcode(cbuf,0xE8); // Call into runtime
2880 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2881 // Restore stack
2882 emit_opcode(cbuf, 0x83); // add SP, #framesize
2883 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2884 emit_d8(cbuf, 4*4);
2885 %}
2886
2887 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2888 // MOV $tmp,$src.lo
2889 emit_opcode(cbuf, 0x8B);
2890 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2891 // OR $tmp,$src.hi
2892 emit_opcode(cbuf, 0x0B);
2893 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2894 %}
2895
2896 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2897 // CMP $src1.lo,$src2.lo
2898 emit_opcode( cbuf, 0x3B );
2899 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2900 // JNE,s skip
2901 emit_cc(cbuf, 0x70, 0x5);
2902 emit_d8(cbuf,2);
2903 // CMP $src1.hi,$src2.hi
2904 emit_opcode( cbuf, 0x3B );
2905 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2906 %}
2907
2908 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2909 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2910 emit_opcode( cbuf, 0x3B );
2911 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2912 // MOV $tmp,$src1.hi
2913 emit_opcode( cbuf, 0x8B );
2914 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2915 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2916 emit_opcode( cbuf, 0x1B );
2917 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2918 %}
2919
2920 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2921 // XOR $tmp,$tmp
2922 emit_opcode(cbuf,0x33); // XOR
2923 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2924 // CMP $tmp,$src.lo
2925 emit_opcode( cbuf, 0x3B );
2926 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2927 // SBB $tmp,$src.hi
2928 emit_opcode( cbuf, 0x1B );
2929 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2930 %}
2931
2932 // Sniff, sniff... smells like Gnu Superoptimizer
2933 enc_class neg_long( eRegL dst ) %{
2934 emit_opcode(cbuf,0xF7); // NEG hi
2935 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2936 emit_opcode(cbuf,0xF7); // NEG lo
2937 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2938 emit_opcode(cbuf,0x83); // SBB hi,0
2939 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2940 emit_d8 (cbuf,0 );
2941 %}
2942
2943
2944 // Because the transitions from emitted code to the runtime
2945 // monitorenter/exit helper stubs are so slow it's critical that
2946 // we inline both the stack-locking fast-path and the inflated fast path.
2947 //
2948 // See also: cmpFastLock and cmpFastUnlock.
2949 //
2950 // What follows is a specialized inline transliteration of the code
2951 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2952 // another option would be to emit TrySlowEnter and TrySlowExit methods
2953 // at startup-time. These methods would accept arguments as
2954 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2955 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2956 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2957 // In practice, however, the # of lock sites is bounded and is usually small.
2958 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2959 // if the processor uses simple bimodal branch predictors keyed by EIP
2960 // Since the helper routines would be called from multiple synchronization
2961 // sites.
2962 //
2963 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2964 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2965 // to those specialized methods. That'd give us a mostly platform-independent
2966 // implementation that the JITs could optimize and inline at their pleasure.
2967 // Done correctly, the only time we'd need to cross to native could would be
2968 // to park() or unpark() threads. We'd also need a few more unsafe operators
2969 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2970 // (b) explicit barriers or fence operations.
2971 //
2972 // TODO:
2973 //
2974 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2975 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2976 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2977 // the lock operators would typically be faster than reifying Self.
2978 //
2979 // * Ideally I'd define the primitives as:
2980 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2981 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2982 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2983 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2984 // Furthermore the register assignments are overconstrained, possibly resulting in
2985 // sub-optimal code near the synchronization site.
2986 //
2987 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2988 // Alternately, use a better sp-proximity test.
2989 //
2990 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2991 // Either one is sufficient to uniquely identify a thread.
2992 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2993 //
2994 // * Intrinsify notify() and notifyAll() for the common cases where the
2995 // object is locked by the calling thread but the waitlist is empty.
2996 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2997 //
2998 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2999 // But beware of excessive branch density on AMD Opterons.
3000 //
3001 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3002 // or failure of the fast-path. If the fast-path fails then we pass
3003 // control to the slow-path, typically in C. In Fast_Lock and
3004 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3005 // will emit a conditional branch immediately after the node.
3006 // So we have branches to branches and lots of ICC.ZF games.
3007 // Instead, it might be better to have C2 pass a "FailureLabel"
3008 // into Fast_Lock and Fast_Unlock. In the case of success, control
3009 // will drop through the node. ICC.ZF is undefined at exit.
3010 // In the case of failure, the node will branch directly to the
3011 // FailureLabel
3012
3013
3014 // obj: object to lock
3015 // box: on-stack box address (displaced header location) - KILLED
3016 // rax,: tmp -- KILLED
3017 // scr: tmp -- KILLED
3018 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3019
3020 Register objReg = as_Register($obj$$reg);
3021 Register boxReg = as_Register($box$$reg);
3022 Register tmpReg = as_Register($tmp$$reg);
3023 Register scrReg = as_Register($scr$$reg);
3024
3025 // Ensure the register assignents are disjoint
3026 guarantee (objReg != boxReg, "") ;
3027 guarantee (objReg != tmpReg, "") ;
3028 guarantee (objReg != scrReg, "") ;
3029 guarantee (boxReg != tmpReg, "") ;
3030 guarantee (boxReg != scrReg, "") ;
3031 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3032
3033 MacroAssembler masm(&cbuf);
3034
3035 if (_counters != NULL) {
3036 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3037 }
3038 if (EmitSync & 1) {
3039 // set box->dhw = unused_mark (3)
3040 // Force all sync thru slow-path: slow_enter() and slow_exit()
3041 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3042 masm.cmpptr (rsp, (int32_t)0) ;
3043 } else
3044 if (EmitSync & 2) {
3045 Label DONE_LABEL ;
3046 if (UseBiasedLocking) {
3047 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3048 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3049 }
3050
3051 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3052 masm.orptr (tmpReg, 0x1);
3053 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3054 if (os::is_MP()) { masm.lock(); }
3055 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3056 masm.jcc(Assembler::equal, DONE_LABEL);
3057 // Recursive locking
3058 masm.subptr(tmpReg, rsp);
3059 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3060 masm.movptr(Address(boxReg, 0), tmpReg);
3061 masm.bind(DONE_LABEL) ;
3062 } else {
3063 // Possible cases that we'll encounter in fast_lock
3064 // ------------------------------------------------
3065 // * Inflated
3066 // -- unlocked
3067 // -- Locked
3068 // = by self
3069 // = by other
3070 // * biased
3071 // -- by Self
3072 // -- by other
3073 // * neutral
3074 // * stack-locked
3075 // -- by self
3076 // = sp-proximity test hits
3077 // = sp-proximity test generates false-negative
3078 // -- by other
3079 //
3080
3081 Label IsInflated, DONE_LABEL, PopDone ;
3082
3083 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3084 // order to reduce the number of conditional branches in the most common cases.
3085 // Beware -- there's a subtle invariant that fetch of the markword
3086 // at [FETCH], below, will never observe a biased encoding (*101b).
3087 // If this invariant is not held we risk exclusion (safety) failure.
3088 if (UseBiasedLocking && !UseOptoBiasInlining) {
3089 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3090 }
3091
3092 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3093 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3094 masm.jccb (Assembler::notZero, IsInflated) ;
3095
3096 // Attempt stack-locking ...
3097 masm.orptr (tmpReg, 0x1);
3098 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3099 if (os::is_MP()) { masm.lock(); }
3100 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3101 if (_counters != NULL) {
3102 masm.cond_inc32(Assembler::equal,
3103 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3104 }
3105 masm.jccb (Assembler::equal, DONE_LABEL);
3106
3107 // Recursive locking
3108 masm.subptr(tmpReg, rsp);
3109 masm.andptr(tmpReg, 0xFFFFF003 );
3110 masm.movptr(Address(boxReg, 0), tmpReg);
3111 if (_counters != NULL) {
3112 masm.cond_inc32(Assembler::equal,
3113 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3114 }
3115 masm.jmp (DONE_LABEL) ;
3116
3117 masm.bind (IsInflated) ;
3118
3119 // The object is inflated.
3120 //
3121 // TODO-FIXME: eliminate the ugly use of manifest constants:
3122 // Use markOopDesc::monitor_value instead of "2".
3123 // use markOop::unused_mark() instead of "3".
3124 // The tmpReg value is an objectMonitor reference ORed with
3125 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3126 // objectmonitor pointer by masking off the "2" bit or we can just
3127 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3128 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3129 //
3130 // I use the latter as it avoids AGI stalls.
3131 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3132 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3133 //
3134 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3135
3136 // boxReg refers to the on-stack BasicLock in the current frame.
3137 // We'd like to write:
3138 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3139 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3140 // additional latency as we have another ST in the store buffer that must drain.
3141
3142 if (EmitSync & 8192) {
3143 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3144 masm.get_thread (scrReg) ;
3145 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3146 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3147 if (os::is_MP()) { masm.lock(); }
3148 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3149 } else
3150 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3151 masm.movptr(scrReg, boxReg) ;
3152 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3153
3154 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3155 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3156 // prefetchw [eax + Offset(_owner)-2]
3157 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3158 }
3159
3160 if ((EmitSync & 64) == 0) {
3161 // Optimistic form: consider XORL tmpReg,tmpReg
3162 masm.movptr(tmpReg, NULL_WORD) ;
3163 } else {
3164 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3165 // Test-And-CAS instead of CAS
3166 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3167 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3168 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3169 }
3170
3171 // Appears unlocked - try to swing _owner from null to non-null.
3172 // Ideally, I'd manifest "Self" with get_thread and then attempt
3173 // to CAS the register containing Self into m->Owner.
3174 // But we don't have enough registers, so instead we can either try to CAS
3175 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3176 // we later store "Self" into m->Owner. Transiently storing a stack address
3177 // (rsp or the address of the box) into m->owner is harmless.
3178 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3179 if (os::is_MP()) { masm.lock(); }
3180 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3181 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3182 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3183 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3184 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3185 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3186
3187 // If the CAS fails we can either retry or pass control to the slow-path.
3188 // We use the latter tactic.
3189 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3190 // If the CAS was successful ...
3191 // Self has acquired the lock
3192 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3193 // Intentional fall-through into DONE_LABEL ...
3194 } else {
3195 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3196 masm.movptr(boxReg, tmpReg) ;
3197
3198 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3199 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3200 // prefetchw [eax + Offset(_owner)-2]
3201 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3202 }
3203
3204 if ((EmitSync & 64) == 0) {
3205 // Optimistic form
3206 masm.xorptr (tmpReg, tmpReg) ;
3207 } else {
3208 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3209 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3210 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3211 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3212 }
3213
3214 // Appears unlocked - try to swing _owner from null to non-null.
3215 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3216 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3217 masm.get_thread (scrReg) ;
3218 if (os::is_MP()) { masm.lock(); }
3219 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3220
3221 // If the CAS fails we can either retry or pass control to the slow-path.
3222 // We use the latter tactic.
3223 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3224 // If the CAS was successful ...
3225 // Self has acquired the lock
3226 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3227 // Intentional fall-through into DONE_LABEL ...
3228 }
3229
3230 // DONE_LABEL is a hot target - we'd really like to place it at the
3231 // start of cache line by padding with NOPs.
3232 // See the AMD and Intel software optimization manuals for the
3233 // most efficient "long" NOP encodings.
3234 // Unfortunately none of our alignment mechanisms suffice.
3235 masm.bind(DONE_LABEL);
3236
3237 // Avoid branch-to-branch on AMD processors
3238 // This appears to be superstition.
3239 if (EmitSync & 32) masm.nop() ;
3240
3241
3242 // At DONE_LABEL the icc ZFlag is set as follows ...
3243 // Fast_Unlock uses the same protocol.
3244 // ZFlag == 1 -> Success
3245 // ZFlag == 0 -> Failure - force control through the slow-path
3246 }
3247 %}
3248
3249 // obj: object to unlock
3250 // box: box address (displaced header location), killed. Must be EAX.
3251 // rbx,: killed tmp; cannot be obj nor box.
3252 //
3253 // Some commentary on balanced locking:
3254 //
3255 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3256 // Methods that don't have provably balanced locking are forced to run in the
3257 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3258 // The interpreter provides two properties:
3259 // I1: At return-time the interpreter automatically and quietly unlocks any
3260 // objects acquired the current activation (frame). Recall that the
3261 // interpreter maintains an on-stack list of locks currently held by
3262 // a frame.
3263 // I2: If a method attempts to unlock an object that is not held by the
3264 // the frame the interpreter throws IMSX.
3265 //
3266 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3267 // B() doesn't have provably balanced locking so it runs in the interpreter.
3268 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3269 // is still locked by A().
3270 //
3271 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3272 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3273 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3274 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3275
3276 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3277
3278 Register objReg = as_Register($obj$$reg);
3279 Register boxReg = as_Register($box$$reg);
3280 Register tmpReg = as_Register($tmp$$reg);
3281
3282 guarantee (objReg != boxReg, "") ;
3283 guarantee (objReg != tmpReg, "") ;
3284 guarantee (boxReg != tmpReg, "") ;
3285 guarantee (boxReg == as_Register(EAX_enc), "") ;
3286 MacroAssembler masm(&cbuf);
3287
3288 if (EmitSync & 4) {
3289 // Disable - inhibit all inlining. Force control through the slow-path
3290 masm.cmpptr (rsp, 0) ;
3291 } else
3292 if (EmitSync & 8) {
3293 Label DONE_LABEL ;
3294 if (UseBiasedLocking) {
3295 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3296 }
3297 // classic stack-locking code ...
3298 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3299 masm.testptr(tmpReg, tmpReg) ;
3300 masm.jcc (Assembler::zero, DONE_LABEL) ;
3301 if (os::is_MP()) { masm.lock(); }
3302 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3303 masm.bind(DONE_LABEL);
3304 } else {
3305 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3306
3307 // Critically, the biased locking test must have precedence over
3308 // and appear before the (box->dhw == 0) recursive stack-lock test.
3309 if (UseBiasedLocking && !UseOptoBiasInlining) {
3310 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3311 }
3312
3313 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3314 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3315 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3316
3317 masm.testptr(tmpReg, 0x02) ; // Inflated?
3318 masm.jccb (Assembler::zero, Stacked) ;
3319
3320 masm.bind (Inflated) ;
3321 // It's inflated.
3322 // Despite our balanced locking property we still check that m->_owner == Self
3323 // as java routines or native JNI code called by this thread might
3324 // have released the lock.
3325 // Refer to the comments in synchronizer.cpp for how we might encode extra
3326 // state in _succ so we can avoid fetching EntryList|cxq.
3327 //
3328 // I'd like to add more cases in fast_lock() and fast_unlock() --
3329 // such as recursive enter and exit -- but we have to be wary of
3330 // I$ bloat, T$ effects and BP$ effects.
3331 //
3332 // If there's no contention try a 1-0 exit. That is, exit without
3333 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3334 // we detect and recover from the race that the 1-0 exit admits.
3335 //
3336 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3337 // before it STs null into _owner, releasing the lock. Updates
3338 // to data protected by the critical section must be visible before
3339 // we drop the lock (and thus before any other thread could acquire
3340 // the lock and observe the fields protected by the lock).
3341 // IA32's memory-model is SPO, so STs are ordered with respect to
3342 // each other and there's no need for an explicit barrier (fence).
3343 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3344
3345 masm.get_thread (boxReg) ;
3346 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3347 // prefetchw [ebx + Offset(_owner)-2]
3348 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3349 }
3350
3351 // Note that we could employ various encoding schemes to reduce
3352 // the number of loads below (currently 4) to just 2 or 3.
3353 // Refer to the comments in synchronizer.cpp.
3354 // In practice the chain of fetches doesn't seem to impact performance, however.
3355 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3356 // Attempt to reduce branch density - AMD's branch predictor.
3357 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3358 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3359 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3360 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3361 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3362 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3363 masm.jmpb (DONE_LABEL) ;
3364 } else {
3365 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3366 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3367 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3368 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3369 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3370 masm.jccb (Assembler::notZero, CheckSucc) ;
3371 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3372 masm.jmpb (DONE_LABEL) ;
3373 }
3374
3375 // The Following code fragment (EmitSync & 65536) improves the performance of
3376 // contended applications and contended synchronization microbenchmarks.
3377 // Unfortunately the emission of the code - even though not executed - causes regressions
3378 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3379 // with an equal number of never-executed NOPs results in the same regression.
3380 // We leave it off by default.
3381
3382 if ((EmitSync & 65536) != 0) {
3383 Label LSuccess, LGoSlowPath ;
3384
3385 masm.bind (CheckSucc) ;
3386
3387 // Optional pre-test ... it's safe to elide this
3388 if ((EmitSync & 16) == 0) {
3389 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3390 masm.jccb (Assembler::zero, LGoSlowPath) ;
3391 }
3392
3393 // We have a classic Dekker-style idiom:
3394 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3395 // There are a number of ways to implement the barrier:
3396 // (1) lock:andl &m->_owner, 0
3397 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3398 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3399 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3400 // (2) If supported, an explicit MFENCE is appealing.
3401 // In older IA32 processors MFENCE is slower than lock:add or xchg
3402 // particularly if the write-buffer is full as might be the case if
3403 // if stores closely precede the fence or fence-equivalent instruction.
3404 // In more modern implementations MFENCE appears faster, however.
3405 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3406 // The $lines underlying the top-of-stack should be in M-state.
3407 // The locked add instruction is serializing, of course.
3408 // (4) Use xchg, which is serializing
3409 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3410 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3411 // The integer condition codes will tell us if succ was 0.
3412 // Since _succ and _owner should reside in the same $line and
3413 // we just stored into _owner, it's likely that the $line
3414 // remains in M-state for the lock:orl.
3415 //
3416 // We currently use (3), although it's likely that switching to (2)
3417 // is correct for the future.
3418
3419 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3420 if (os::is_MP()) {
3421 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3422 masm.mfence();
3423 } else {
3424 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3425 }
3426 }
3427 // Ratify _succ remains non-null
3428 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3429 masm.jccb (Assembler::notZero, LSuccess) ;
3430
3431 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3432 if (os::is_MP()) { masm.lock(); }
3433 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3434 masm.jccb (Assembler::notEqual, LSuccess) ;
3435 // Since we're low on registers we installed rsp as a placeholding in _owner.
3436 // Now install Self over rsp. This is safe as we're transitioning from
3437 // non-null to non=null
3438 masm.get_thread (boxReg) ;
3439 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3440 // Intentional fall-through into LGoSlowPath ...
3441
3442 masm.bind (LGoSlowPath) ;
3443 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3444 masm.jmpb (DONE_LABEL) ;
3445
3446 masm.bind (LSuccess) ;
3447 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3448 masm.jmpb (DONE_LABEL) ;
3449 }
3450
3451 masm.bind (Stacked) ;
3452 // It's not inflated and it's not recursively stack-locked and it's not biased.
3453 // It must be stack-locked.
3454 // Try to reset the header to displaced header.
3455 // The "box" value on the stack is stable, so we can reload
3456 // and be assured we observe the same value as above.
3457 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3458 if (os::is_MP()) { masm.lock(); }
3459 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3460 // Intention fall-thru into DONE_LABEL
3461
3462
3463 // DONE_LABEL is a hot target - we'd really like to place it at the
3464 // start of cache line by padding with NOPs.
3465 // See the AMD and Intel software optimization manuals for the
3466 // most efficient "long" NOP encodings.
3467 // Unfortunately none of our alignment mechanisms suffice.
3468 if ((EmitSync & 65536) == 0) {
3469 masm.bind (CheckSucc) ;
3470 }
3471 masm.bind(DONE_LABEL);
3472
3473 // Avoid branch to branch on AMD processors
3474 if (EmitSync & 32768) { masm.nop() ; }
3475 }
3476 %}
3477
3478
3479 enc_class enc_pop_rdx() %{
3480 emit_opcode(cbuf,0x5A);
3481 %}
3482
3483 enc_class enc_rethrow() %{
3484 cbuf.set_insts_mark();
3485 emit_opcode(cbuf, 0xE9); // jmp entry
3486 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3487 runtime_call_Relocation::spec(), RELOC_IMM32 );
3488 %}
3489
3490
3491 // Convert a double to an int. Java semantics require we do complex
3492 // manglelations in the corner cases. So we set the rounding mode to
3493 // 'zero', store the darned double down as an int, and reset the
3494 // rounding mode to 'nearest'. The hardware throws an exception which
3495 // patches up the correct value directly to the stack.
3496 enc_class DPR2I_encoding( regDPR src ) %{
3497 // Flip to round-to-zero mode. We attempted to allow invalid-op
3498 // exceptions here, so that a NAN or other corner-case value will
3499 // thrown an exception (but normal values get converted at full speed).
3500 // However, I2C adapters and other float-stack manglers leave pending
3501 // invalid-op exceptions hanging. We would have to clear them before
3502 // enabling them and that is more expensive than just testing for the
3503 // invalid value Intel stores down in the corner cases.
3504 emit_opcode(cbuf,0xD9); // FLDCW trunc
3505 emit_opcode(cbuf,0x2D);
3506 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3507 // Allocate a word
3508 emit_opcode(cbuf,0x83); // SUB ESP,4
3509 emit_opcode(cbuf,0xEC);
3510 emit_d8(cbuf,0x04);
3511 // Encoding assumes a double has been pushed into FPR0.
3512 // Store down the double as an int, popping the FPU stack
3513 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3514 emit_opcode(cbuf,0x1C);
3515 emit_d8(cbuf,0x24);
3516 // Restore the rounding mode; mask the exception
3517 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3518 emit_opcode(cbuf,0x2D);
3519 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3520 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3521 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3522
3523 // Load the converted int; adjust CPU stack
3524 emit_opcode(cbuf,0x58); // POP EAX
3525 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3526 emit_d32 (cbuf,0x80000000); // 0x80000000
3527 emit_opcode(cbuf,0x75); // JNE around_slow_call
3528 emit_d8 (cbuf,0x07); // Size of slow_call
3529 // Push src onto stack slow-path
3530 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3531 emit_d8 (cbuf,0xC0-1+$src$$reg );
3532 // CALL directly to the runtime
3533 cbuf.set_insts_mark();
3534 emit_opcode(cbuf,0xE8); // Call into runtime
3535 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3536 // Carry on here...
3537 %}
3538
3539 enc_class DPR2L_encoding( regDPR src ) %{
3540 emit_opcode(cbuf,0xD9); // FLDCW trunc
3541 emit_opcode(cbuf,0x2D);
3542 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3543 // Allocate a word
3544 emit_opcode(cbuf,0x83); // SUB ESP,8
3545 emit_opcode(cbuf,0xEC);
3546 emit_d8(cbuf,0x08);
3547 // Encoding assumes a double has been pushed into FPR0.
3548 // Store down the double as a long, popping the FPU stack
3549 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3550 emit_opcode(cbuf,0x3C);
3551 emit_d8(cbuf,0x24);
3552 // Restore the rounding mode; mask the exception
3553 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3554 emit_opcode(cbuf,0x2D);
3555 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3556 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3557 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3558
3559 // Load the converted int; adjust CPU stack
3560 emit_opcode(cbuf,0x58); // POP EAX
3561 emit_opcode(cbuf,0x5A); // POP EDX
3562 emit_opcode(cbuf,0x81); // CMP EDX,imm
3563 emit_d8 (cbuf,0xFA); // rdx
3564 emit_d32 (cbuf,0x80000000); // 0x80000000
3565 emit_opcode(cbuf,0x75); // JNE around_slow_call
3566 emit_d8 (cbuf,0x07+4); // Size of slow_call
3567 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3568 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3569 emit_opcode(cbuf,0x75); // JNE around_slow_call
3570 emit_d8 (cbuf,0x07); // Size of slow_call
3571 // Push src onto stack slow-path
3572 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3573 emit_d8 (cbuf,0xC0-1+$src$$reg );
3574 // CALL directly to the runtime
3575 cbuf.set_insts_mark();
3576 emit_opcode(cbuf,0xE8); // Call into runtime
3577 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3578 // Carry on here...
3579 %}
3580
3581 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3582 // Operand was loaded from memory into fp ST (stack top)
3583 // FMUL ST,$src /* D8 C8+i */
3584 emit_opcode(cbuf, 0xD8);
3585 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3586 %}
3587
3588 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3589 // FADDP ST,src2 /* D8 C0+i */
3590 emit_opcode(cbuf, 0xD8);
3591 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3592 //could use FADDP src2,fpST /* DE C0+i */
3593 %}
3594
3595 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3596 // FADDP src2,ST /* DE C0+i */
3597 emit_opcode(cbuf, 0xDE);
3598 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3599 %}
3600
3601 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3602 // Operand has been loaded into fp ST (stack top)
3603 // FSUB ST,$src1
3604 emit_opcode(cbuf, 0xD8);
3605 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3606
3607 // FDIV
3608 emit_opcode(cbuf, 0xD8);
3609 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3610 %}
3611
3612 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3613 // Operand was loaded from memory into fp ST (stack top)
3614 // FADD ST,$src /* D8 C0+i */
3615 emit_opcode(cbuf, 0xD8);
3616 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3617
3618 // FMUL ST,src2 /* D8 C*+i */
3619 emit_opcode(cbuf, 0xD8);
3620 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3621 %}
3622
3623
3624 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3625 // Operand was loaded from memory into fp ST (stack top)
3626 // FADD ST,$src /* D8 C0+i */
3627 emit_opcode(cbuf, 0xD8);
3628 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3629
3630 // FMULP src2,ST /* DE C8+i */
3631 emit_opcode(cbuf, 0xDE);
3632 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3633 %}
3634
3635 // Atomically load the volatile long
3636 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3637 emit_opcode(cbuf,0xDF);
3638 int rm_byte_opcode = 0x05;
3639 int base = $mem$$base;
3640 int index = $mem$$index;
3641 int scale = $mem$$scale;
3642 int displace = $mem$$disp;
3643 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3644 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3645 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3646 %}
3647
3648 // Volatile Store Long. Must be atomic, so move it into
3649 // the FP TOS and then do a 64-bit FIST. Has to probe the
3650 // target address before the store (for null-ptr checks)
3651 // so the memory operand is used twice in the encoding.
3652 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3653 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3654 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3655 emit_opcode(cbuf,0xDF);
3656 int rm_byte_opcode = 0x07;
3657 int base = $mem$$base;
3658 int index = $mem$$index;
3659 int scale = $mem$$scale;
3660 int displace = $mem$$disp;
3661 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3662 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3663 %}
3664
3665 // Safepoint Poll. This polls the safepoint page, and causes an
3666 // exception if it is not readable. Unfortunately, it kills the condition code
3667 // in the process
3668 // We current use TESTL [spp],EDI
3669 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3670
3671 enc_class Safepoint_Poll() %{
3672 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3673 emit_opcode(cbuf,0x85);
3674 emit_rm (cbuf, 0x0, 0x7, 0x5);
3675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3676 %}
3677 %}
3678
3679
3680 //----------FRAME--------------------------------------------------------------
3681 // Definition of frame structure and management information.
3682 //
3683 // S T A C K L A Y O U T Allocators stack-slot number
3684 // | (to get allocators register number
3685 // G Owned by | | v add OptoReg::stack0())
3686 // r CALLER | |
3687 // o | +--------+ pad to even-align allocators stack-slot
3688 // w V | pad0 | numbers; owned by CALLER
3689 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3690 // h ^ | in | 5
3691 // | | args | 4 Holes in incoming args owned by SELF
3692 // | | | | 3
3693 // | | +--------+
3694 // V | | old out| Empty on Intel, window on Sparc
3695 // | old |preserve| Must be even aligned.
3696 // | SP-+--------+----> Matcher::_old_SP, even aligned
3697 // | | in | 3 area for Intel ret address
3698 // Owned by |preserve| Empty on Sparc.
3699 // SELF +--------+
3700 // | | pad2 | 2 pad to align old SP
3701 // | +--------+ 1
3702 // | | locks | 0
3703 // | +--------+----> OptoReg::stack0(), even aligned
3704 // | | pad1 | 11 pad to align new SP
3705 // | +--------+
3706 // | | | 10
3707 // | | spills | 9 spills
3708 // V | | 8 (pad0 slot for callee)
3709 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3710 // ^ | out | 7
3711 // | | args | 6 Holes in outgoing args owned by CALLEE
3712 // Owned by +--------+
3713 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3714 // | new |preserve| Must be even-aligned.
3715 // | SP-+--------+----> Matcher::_new_SP, even aligned
3716 // | | |
3717 //
3718 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3719 // known from SELF's arguments and the Java calling convention.
3720 // Region 6-7 is determined per call site.
3721 // Note 2: If the calling convention leaves holes in the incoming argument
3722 // area, those holes are owned by SELF. Holes in the outgoing area
3723 // are owned by the CALLEE. Holes should not be nessecary in the
3724 // incoming area, as the Java calling convention is completely under
3725 // the control of the AD file. Doubles can be sorted and packed to
3726 // avoid holes. Holes in the outgoing arguments may be nessecary for
3727 // varargs C calling conventions.
3728 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3729 // even aligned with pad0 as needed.
3730 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3731 // region 6-11 is even aligned; it may be padded out more so that
3732 // the region from SP to FP meets the minimum stack alignment.
3733
3734 frame %{
3735 // What direction does stack grow in (assumed to be same for C & Java)
3736 stack_direction(TOWARDS_LOW);
3737
3738 // These three registers define part of the calling convention
3739 // between compiled code and the interpreter.
3740 inline_cache_reg(EAX); // Inline Cache Register
3741 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3742
3743 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3744 cisc_spilling_operand_name(indOffset32);
3745
3746 // Number of stack slots consumed by locking an object
3747 sync_stack_slots(1);
3748
3749 // Compiled code's Frame Pointer
3750 frame_pointer(ESP);
3751 // Interpreter stores its frame pointer in a register which is
3752 // stored to the stack by I2CAdaptors.
3753 // I2CAdaptors convert from interpreted java to compiled java.
3754 interpreter_frame_pointer(EBP);
3755
3756 // Stack alignment requirement
3757 // Alignment size in bytes (128-bit -> 16 bytes)
3758 stack_alignment(StackAlignmentInBytes);
3759
3760 // Number of stack slots between incoming argument block and the start of
3761 // a new frame. The PROLOG must add this many slots to the stack. The
3762 // EPILOG must remove this many slots. Intel needs one slot for
3763 // return address and one for rbp, (must save rbp)
3764 in_preserve_stack_slots(2+VerifyStackAtCalls);
3765
3766 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3767 // for calls to C. Supports the var-args backing area for register parms.
3768 varargs_C_out_slots_killed(0);
3769
3770 // The after-PROLOG location of the return address. Location of
3771 // return address specifies a type (REG or STACK) and a number
3772 // representing the register number (i.e. - use a register name) or
3773 // stack slot.
3774 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3775 // Otherwise, it is above the locks and verification slot and alignment word
3776 return_addr(STACK - 1 +
3777 round_to((Compile::current()->in_preserve_stack_slots() +
3778 Compile::current()->fixed_slots()),
3779 stack_alignment_in_slots()));
3780
3781 // Body of function which returns an integer array locating
3782 // arguments either in registers or in stack slots. Passed an array
3783 // of ideal registers called "sig" and a "length" count. Stack-slot
3784 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3785 // arguments for a CALLEE. Incoming stack arguments are
3786 // automatically biased by the preserve_stack_slots field above.
3787 calling_convention %{
3788 // No difference between ingoing/outgoing just pass false
3789 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3790 %}
3791
3792
3793 // Body of function which returns an integer array locating
3794 // arguments either in registers or in stack slots. Passed an array
3795 // of ideal registers called "sig" and a "length" count. Stack-slot
3796 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3797 // arguments for a CALLEE. Incoming stack arguments are
3798 // automatically biased by the preserve_stack_slots field above.
3799 c_calling_convention %{
3800 // This is obviously always outgoing
3801 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3802 %}
3803
3804 // Location of C & interpreter return values
3805 c_return_value %{
3806 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3807 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3808 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3809
3810 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3811 // that C functions return float and double results in XMM0.
3812 if( ideal_reg == Op_RegD && UseSSE>=2 )
3813 return OptoRegPair(XMM0b_num,XMM0_num);
3814 if( ideal_reg == Op_RegF && UseSSE>=2 )
3815 return OptoRegPair(OptoReg::Bad,XMM0_num);
3816
3817 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3818 %}
3819
3820 // Location of return values
3821 return_value %{
3822 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3823 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3824 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3825 if( ideal_reg == Op_RegD && UseSSE>=2 )
3826 return OptoRegPair(XMM0b_num,XMM0_num);
3827 if( ideal_reg == Op_RegF && UseSSE>=1 )
3828 return OptoRegPair(OptoReg::Bad,XMM0_num);
3829 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3830 %}
3831
3832 %}
3833
3834 //----------ATTRIBUTES---------------------------------------------------------
3835 //----------Operand Attributes-------------------------------------------------
3836 op_attrib op_cost(0); // Required cost attribute
3837
3838 //----------Instruction Attributes---------------------------------------------
3839 ins_attrib ins_cost(100); // Required cost attribute
3840 ins_attrib ins_size(8); // Required size attribute (in bits)
3841 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3842 // non-matching short branch variant of some
3843 // long branch?
3844 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3845 // specifies the alignment that some part of the instruction (not
3846 // necessarily the start) requires. If > 1, a compute_padding()
3847 // function must be provided for the instruction
3848
3849 //----------OPERANDS-----------------------------------------------------------
3850 // Operand definitions must precede instruction definitions for correct parsing
3851 // in the ADLC because operands constitute user defined types which are used in
3852 // instruction definitions.
3853
3854 //----------Simple Operands----------------------------------------------------
3855 // Immediate Operands
3856 // Integer Immediate
3857 operand immI() %{
3858 match(ConI);
3859
3860 op_cost(10);
3861 format %{ %}
3862 interface(CONST_INTER);
3863 %}
3864
3865 // Constant for test vs zero
3866 operand immI0() %{
3867 predicate(n->get_int() == 0);
3868 match(ConI);
3869
3870 op_cost(0);
3871 format %{ %}
3872 interface(CONST_INTER);
3873 %}
3874
3875 // Constant for increment
3876 operand immI1() %{
3877 predicate(n->get_int() == 1);
3878 match(ConI);
3879
3880 op_cost(0);
3881 format %{ %}
3882 interface(CONST_INTER);
3883 %}
3884
3885 // Constant for decrement
3886 operand immI_M1() %{
3887 predicate(n->get_int() == -1);
3888 match(ConI);
3889
3890 op_cost(0);
3891 format %{ %}
3892 interface(CONST_INTER);
3893 %}
3894
3895 // Valid scale values for addressing modes
3896 operand immI2() %{
3897 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3898 match(ConI);
3899
3900 format %{ %}
3901 interface(CONST_INTER);
3902 %}
3903
3904 operand immI8() %{
3905 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3906 match(ConI);
3907
3908 op_cost(5);
3909 format %{ %}
3910 interface(CONST_INTER);
3911 %}
3912
3913 operand immI16() %{
3914 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3915 match(ConI);
3916
3917 op_cost(10);
3918 format %{ %}
3919 interface(CONST_INTER);
3920 %}
3921
3922 // Constant for long shifts
3923 operand immI_32() %{
3924 predicate( n->get_int() == 32 );
3925 match(ConI);
3926
3927 op_cost(0);
3928 format %{ %}
3929 interface(CONST_INTER);
3930 %}
3931
3932 operand immI_1_31() %{
3933 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3934 match(ConI);
3935
3936 op_cost(0);
3937 format %{ %}
3938 interface(CONST_INTER);
3939 %}
3940
3941 operand immI_32_63() %{
3942 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3943 match(ConI);
3944 op_cost(0);
3945
3946 format %{ %}
3947 interface(CONST_INTER);
3948 %}
3949
3950 operand immI_1() %{
3951 predicate( n->get_int() == 1 );
3952 match(ConI);
3953
3954 op_cost(0);
3955 format %{ %}
3956 interface(CONST_INTER);
3957 %}
3958
3959 operand immI_2() %{
3960 predicate( n->get_int() == 2 );
3961 match(ConI);
3962
3963 op_cost(0);
3964 format %{ %}
3965 interface(CONST_INTER);
3966 %}
3967
3968 operand immI_3() %{
3969 predicate( n->get_int() == 3 );
3970 match(ConI);
3971
3972 op_cost(0);
3973 format %{ %}
3974 interface(CONST_INTER);
3975 %}
3976
3977 // Pointer Immediate
3978 operand immP() %{
3979 match(ConP);
3980
3981 op_cost(10);
3982 format %{ %}
3983 interface(CONST_INTER);
3984 %}
3985
3986 // NULL Pointer Immediate
3987 operand immP0() %{
3988 predicate( n->get_ptr() == 0 );
3989 match(ConP);
3990 op_cost(0);
3991
3992 format %{ %}
3993 interface(CONST_INTER);
3994 %}
3995
3996 // Long Immediate
3997 operand immL() %{
3998 match(ConL);
3999
4000 op_cost(20);
4001 format %{ %}
4002 interface(CONST_INTER);
4003 %}
4004
4005 // Long Immediate zero
4006 operand immL0() %{
4007 predicate( n->get_long() == 0L );
4008 match(ConL);
4009 op_cost(0);
4010
4011 format %{ %}
4012 interface(CONST_INTER);
4013 %}
4014
4015 // Long Immediate zero
4016 operand immL_M1() %{
4017 predicate( n->get_long() == -1L );
4018 match(ConL);
4019 op_cost(0);
4020
4021 format %{ %}
4022 interface(CONST_INTER);
4023 %}
4024
4025 // Long immediate from 0 to 127.
4026 // Used for a shorter form of long mul by 10.
4027 operand immL_127() %{
4028 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4029 match(ConL);
4030 op_cost(0);
4031
4032 format %{ %}
4033 interface(CONST_INTER);
4034 %}
4035
4036 // Long Immediate: low 32-bit mask
4037 operand immL_32bits() %{
4038 predicate(n->get_long() == 0xFFFFFFFFL);
4039 match(ConL);
4040 op_cost(0);
4041
4042 format %{ %}
4043 interface(CONST_INTER);
4044 %}
4045
4046 // Long Immediate: low 32-bit mask
4047 operand immL32() %{
4048 predicate(n->get_long() == (int)(n->get_long()));
4049 match(ConL);
4050 op_cost(20);
4051
4052 format %{ %}
4053 interface(CONST_INTER);
4054 %}
4055
4056 //Double Immediate zero
4057 operand immDPR0() %{
4058 // Do additional (and counter-intuitive) test against NaN to work around VC++
4059 // bug that generates code such that NaNs compare equal to 0.0
4060 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4061 match(ConD);
4062
4063 op_cost(5);
4064 format %{ %}
4065 interface(CONST_INTER);
4066 %}
4067
4068 // Double Immediate one
4069 operand immDPR1() %{
4070 predicate( UseSSE<=1 && n->getd() == 1.0 );
4071 match(ConD);
4072
4073 op_cost(5);
4074 format %{ %}
4075 interface(CONST_INTER);
4076 %}
4077
4078 // Double Immediate
4079 operand immDPR() %{
4080 predicate(UseSSE<=1);
4081 match(ConD);
4082
4083 op_cost(5);
4084 format %{ %}
4085 interface(CONST_INTER);
4086 %}
4087
4088 operand immD() %{
4089 predicate(UseSSE>=2);
4090 match(ConD);
4091
4092 op_cost(5);
4093 format %{ %}
4094 interface(CONST_INTER);
4095 %}
4096
4097 // Double Immediate zero
4098 operand immD0() %{
4099 // Do additional (and counter-intuitive) test against NaN to work around VC++
4100 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4101 // compare equal to -0.0.
4102 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4103 match(ConD);
4104
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4108
4109 // Float Immediate zero
4110 operand immFPR0() %{
4111 predicate(UseSSE == 0 && n->getf() == 0.0F);
4112 match(ConF);
4113
4114 op_cost(5);
4115 format %{ %}
4116 interface(CONST_INTER);
4117 %}
4118
4119 // Float Immediate one
4120 operand immFPR1() %{
4121 predicate(UseSSE == 0 && n->getf() == 1.0F);
4122 match(ConF);
4123
4124 op_cost(5);
4125 format %{ %}
4126 interface(CONST_INTER);
4127 %}
4128
4129 // Float Immediate
4130 operand immFPR() %{
4131 predicate( UseSSE == 0 );
4132 match(ConF);
4133
4134 op_cost(5);
4135 format %{ %}
4136 interface(CONST_INTER);
4137 %}
4138
4139 // Float Immediate
4140 operand immF() %{
4141 predicate(UseSSE >= 1);
4142 match(ConF);
4143
4144 op_cost(5);
4145 format %{ %}
4146 interface(CONST_INTER);
4147 %}
4148
4149 // Float Immediate zero. Zero and not -0.0
4150 operand immF0() %{
4151 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4152 match(ConF);
4153
4154 op_cost(5);
4155 format %{ %}
4156 interface(CONST_INTER);
4157 %}
4158
4159 // Immediates for special shifts (sign extend)
4160
4161 // Constants for increment
4162 operand immI_16() %{
4163 predicate( n->get_int() == 16 );
4164 match(ConI);
4165
4166 format %{ %}
4167 interface(CONST_INTER);
4168 %}
4169
4170 operand immI_24() %{
4171 predicate( n->get_int() == 24 );
4172 match(ConI);
4173
4174 format %{ %}
4175 interface(CONST_INTER);
4176 %}
4177
4178 // Constant for byte-wide masking
4179 operand immI_255() %{
4180 predicate( n->get_int() == 255 );
4181 match(ConI);
4182
4183 format %{ %}
4184 interface(CONST_INTER);
4185 %}
4186
4187 // Constant for short-wide masking
4188 operand immI_65535() %{
4189 predicate(n->get_int() == 65535);
4190 match(ConI);
4191
4192 format %{ %}
4193 interface(CONST_INTER);
4194 %}
4195
4196 // Register Operands
4197 // Integer Register
4198 operand rRegI() %{
4199 constraint(ALLOC_IN_RC(int_reg));
4200 match(RegI);
4201 match(xRegI);
4202 match(eAXRegI);
4203 match(eBXRegI);
4204 match(eCXRegI);
4205 match(eDXRegI);
4206 match(eDIRegI);
4207 match(eSIRegI);
4208
4209 format %{ %}
4210 interface(REG_INTER);
4211 %}
4212
4213 // Subset of Integer Register
4214 operand xRegI(rRegI reg) %{
4215 constraint(ALLOC_IN_RC(int_x_reg));
4216 match(reg);
4217 match(eAXRegI);
4218 match(eBXRegI);
4219 match(eCXRegI);
4220 match(eDXRegI);
4221
4222 format %{ %}
4223 interface(REG_INTER);
4224 %}
4225
4226 // Special Registers
4227 operand eAXRegI(xRegI reg) %{
4228 constraint(ALLOC_IN_RC(eax_reg));
4229 match(reg);
4230 match(rRegI);
4231
4232 format %{ "EAX" %}
4233 interface(REG_INTER);
4234 %}
4235
4236 // Special Registers
4237 operand eBXRegI(xRegI reg) %{
4238 constraint(ALLOC_IN_RC(ebx_reg));
4239 match(reg);
4240 match(rRegI);
4241
4242 format %{ "EBX" %}
4243 interface(REG_INTER);
4244 %}
4245
4246 operand eCXRegI(xRegI reg) %{
4247 constraint(ALLOC_IN_RC(ecx_reg));
4248 match(reg);
4249 match(rRegI);
4250
4251 format %{ "ECX" %}
4252 interface(REG_INTER);
4253 %}
4254
4255 operand eDXRegI(xRegI reg) %{
4256 constraint(ALLOC_IN_RC(edx_reg));
4257 match(reg);
4258 match(rRegI);
4259
4260 format %{ "EDX" %}
4261 interface(REG_INTER);
4262 %}
4263
4264 operand eDIRegI(xRegI reg) %{
4265 constraint(ALLOC_IN_RC(edi_reg));
4266 match(reg);
4267 match(rRegI);
4268
4269 format %{ "EDI" %}
4270 interface(REG_INTER);
4271 %}
4272
4273 operand naxRegI() %{
4274 constraint(ALLOC_IN_RC(nax_reg));
4275 match(RegI);
4276 match(eCXRegI);
4277 match(eDXRegI);
4278 match(eSIRegI);
4279 match(eDIRegI);
4280
4281 format %{ %}
4282 interface(REG_INTER);
4283 %}
4284
4285 operand nadxRegI() %{
4286 constraint(ALLOC_IN_RC(nadx_reg));
4287 match(RegI);
4288 match(eBXRegI);
4289 match(eCXRegI);
4290 match(eSIRegI);
4291 match(eDIRegI);
4292
4293 format %{ %}
4294 interface(REG_INTER);
4295 %}
4296
4297 operand ncxRegI() %{
4298 constraint(ALLOC_IN_RC(ncx_reg));
4299 match(RegI);
4300 match(eAXRegI);
4301 match(eDXRegI);
4302 match(eSIRegI);
4303 match(eDIRegI);
4304
4305 format %{ %}
4306 interface(REG_INTER);
4307 %}
4308
4309 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4310 // //
4311 operand eSIRegI(xRegI reg) %{
4312 constraint(ALLOC_IN_RC(esi_reg));
4313 match(reg);
4314 match(rRegI);
4315
4316 format %{ "ESI" %}
4317 interface(REG_INTER);
4318 %}
4319
4320 // Pointer Register
4321 operand anyRegP() %{
4322 constraint(ALLOC_IN_RC(any_reg));
4323 match(RegP);
4324 match(eAXRegP);
4325 match(eBXRegP);
4326 match(eCXRegP);
4327 match(eDIRegP);
4328 match(eRegP);
4329
4330 format %{ %}
4331 interface(REG_INTER);
4332 %}
4333
4334 operand eRegP() %{
4335 constraint(ALLOC_IN_RC(int_reg));
4336 match(RegP);
4337 match(eAXRegP);
4338 match(eBXRegP);
4339 match(eCXRegP);
4340 match(eDIRegP);
4341
4342 format %{ %}
4343 interface(REG_INTER);
4344 %}
4345
4346 // On windows95, EBP is not safe to use for implicit null tests.
4347 operand eRegP_no_EBP() %{
4348 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4349 match(RegP);
4350 match(eAXRegP);
4351 match(eBXRegP);
4352 match(eCXRegP);
4353 match(eDIRegP);
4354
4355 op_cost(100);
4356 format %{ %}
4357 interface(REG_INTER);
4358 %}
4359
4360 operand naxRegP() %{
4361 constraint(ALLOC_IN_RC(nax_reg));
4362 match(RegP);
4363 match(eBXRegP);
4364 match(eDXRegP);
4365 match(eCXRegP);
4366 match(eSIRegP);
4367 match(eDIRegP);
4368
4369 format %{ %}
4370 interface(REG_INTER);
4371 %}
4372
4373 operand nabxRegP() %{
4374 constraint(ALLOC_IN_RC(nabx_reg));
4375 match(RegP);
4376 match(eCXRegP);
4377 match(eDXRegP);
4378 match(eSIRegP);
4379 match(eDIRegP);
4380
4381 format %{ %}
4382 interface(REG_INTER);
4383 %}
4384
4385 operand pRegP() %{
4386 constraint(ALLOC_IN_RC(p_reg));
4387 match(RegP);
4388 match(eBXRegP);
4389 match(eDXRegP);
4390 match(eSIRegP);
4391 match(eDIRegP);
4392
4393 format %{ %}
4394 interface(REG_INTER);
4395 %}
4396
4397 // Special Registers
4398 // Return a pointer value
4399 operand eAXRegP(eRegP reg) %{
4400 constraint(ALLOC_IN_RC(eax_reg));
4401 match(reg);
4402 format %{ "EAX" %}
4403 interface(REG_INTER);
4404 %}
4405
4406 // Used in AtomicAdd
4407 operand eBXRegP(eRegP reg) %{
4408 constraint(ALLOC_IN_RC(ebx_reg));
4409 match(reg);
4410 format %{ "EBX" %}
4411 interface(REG_INTER);
4412 %}
4413
4414 // Tail-call (interprocedural jump) to interpreter
4415 operand eCXRegP(eRegP reg) %{
4416 constraint(ALLOC_IN_RC(ecx_reg));
4417 match(reg);
4418 format %{ "ECX" %}
4419 interface(REG_INTER);
4420 %}
4421
4422 operand eSIRegP(eRegP reg) %{
4423 constraint(ALLOC_IN_RC(esi_reg));
4424 match(reg);
4425 format %{ "ESI" %}
4426 interface(REG_INTER);
4427 %}
4428
4429 // Used in rep stosw
4430 operand eDIRegP(eRegP reg) %{
4431 constraint(ALLOC_IN_RC(edi_reg));
4432 match(reg);
4433 format %{ "EDI" %}
4434 interface(REG_INTER);
4435 %}
4436
4437 operand eBPRegP() %{
4438 constraint(ALLOC_IN_RC(ebp_reg));
4439 match(RegP);
4440 format %{ "EBP" %}
4441 interface(REG_INTER);
4442 %}
4443
4444 operand eRegL() %{
4445 constraint(ALLOC_IN_RC(long_reg));
4446 match(RegL);
4447 match(eADXRegL);
4448
4449 format %{ %}
4450 interface(REG_INTER);
4451 %}
4452
4453 operand eADXRegL( eRegL reg ) %{
4454 constraint(ALLOC_IN_RC(eadx_reg));
4455 match(reg);
4456
4457 format %{ "EDX:EAX" %}
4458 interface(REG_INTER);
4459 %}
4460
4461 operand eBCXRegL( eRegL reg ) %{
4462 constraint(ALLOC_IN_RC(ebcx_reg));
4463 match(reg);
4464
4465 format %{ "EBX:ECX" %}
4466 interface(REG_INTER);
4467 %}
4468
4469 // Special case for integer high multiply
4470 operand eADXRegL_low_only() %{
4471 constraint(ALLOC_IN_RC(eadx_reg));
4472 match(RegL);
4473
4474 format %{ "EAX" %}
4475 interface(REG_INTER);
4476 %}
4477
4478 // Flags register, used as output of compare instructions
4479 operand eFlagsReg() %{
4480 constraint(ALLOC_IN_RC(int_flags));
4481 match(RegFlags);
4482
4483 format %{ "EFLAGS" %}
4484 interface(REG_INTER);
4485 %}
4486
4487 // Flags register, used as output of FLOATING POINT compare instructions
4488 operand eFlagsRegU() %{
4489 constraint(ALLOC_IN_RC(int_flags));
4490 match(RegFlags);
4491
4492 format %{ "EFLAGS_U" %}
4493 interface(REG_INTER);
4494 %}
4495
4496 operand eFlagsRegUCF() %{
4497 constraint(ALLOC_IN_RC(int_flags));
4498 match(RegFlags);
4499 predicate(false);
4500
4501 format %{ "EFLAGS_U_CF" %}
4502 interface(REG_INTER);
4503 %}
4504
4505 // Condition Code Register used by long compare
4506 operand flagsReg_long_LTGE() %{
4507 constraint(ALLOC_IN_RC(int_flags));
4508 match(RegFlags);
4509 format %{ "FLAGS_LTGE" %}
4510 interface(REG_INTER);
4511 %}
4512 operand flagsReg_long_EQNE() %{
4513 constraint(ALLOC_IN_RC(int_flags));
4514 match(RegFlags);
4515 format %{ "FLAGS_EQNE" %}
4516 interface(REG_INTER);
4517 %}
4518 operand flagsReg_long_LEGT() %{
4519 constraint(ALLOC_IN_RC(int_flags));
4520 match(RegFlags);
4521 format %{ "FLAGS_LEGT" %}
4522 interface(REG_INTER);
4523 %}
4524
4525 // Float register operands
4526 operand regDPR() %{
4527 predicate( UseSSE < 2 );
4528 constraint(ALLOC_IN_RC(fp_dbl_reg));
4529 match(RegD);
4530 match(regDPR1);
4531 match(regDPR2);
4532 format %{ %}
4533 interface(REG_INTER);
4534 %}
4535
4536 operand regDPR1(regDPR reg) %{
4537 predicate( UseSSE < 2 );
4538 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4539 match(reg);
4540 format %{ "FPR1" %}
4541 interface(REG_INTER);
4542 %}
4543
4544 operand regDPR2(regDPR reg) %{
4545 predicate( UseSSE < 2 );
4546 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4547 match(reg);
4548 format %{ "FPR2" %}
4549 interface(REG_INTER);
4550 %}
4551
4552 operand regnotDPR1(regDPR reg) %{
4553 predicate( UseSSE < 2 );
4554 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4555 match(reg);
4556 format %{ %}
4557 interface(REG_INTER);
4558 %}
4559
4560 // Float register operands
4561 operand regFPR() %{
4562 predicate( UseSSE < 2 );
4563 constraint(ALLOC_IN_RC(fp_flt_reg));
4564 match(RegF);
4565 match(regFPR1);
4566 format %{ %}
4567 interface(REG_INTER);
4568 %}
4569
4570 // Float register operands
4571 operand regFPR1(regFPR reg) %{
4572 predicate( UseSSE < 2 );
4573 constraint(ALLOC_IN_RC(fp_flt_reg0));
4574 match(reg);
4575 format %{ "FPR1" %}
4576 interface(REG_INTER);
4577 %}
4578
4579 // XMM Float register operands
4580 operand regF() %{
4581 predicate( UseSSE>=1 );
4582 constraint(ALLOC_IN_RC(float_reg));
4583 match(RegF);
4584 format %{ %}
4585 interface(REG_INTER);
4586 %}
4587
4588 // XMM Double register operands
4589 operand regD() %{
4590 predicate( UseSSE>=2 );
4591 constraint(ALLOC_IN_RC(double_reg));
4592 match(RegD);
4593 format %{ %}
4594 interface(REG_INTER);
4595 %}
4596
4597
4598 //----------Memory Operands----------------------------------------------------
4599 // Direct Memory Operand
4600 operand direct(immP addr) %{
4601 match(addr);
4602
4603 format %{ "[$addr]" %}
4604 interface(MEMORY_INTER) %{
4605 base(0xFFFFFFFF);
4606 index(0x4);
4607 scale(0x0);
4608 disp($addr);
4609 %}
4610 %}
4611
4612 // Indirect Memory Operand
4613 operand indirect(eRegP reg) %{
4614 constraint(ALLOC_IN_RC(int_reg));
4615 match(reg);
4616
4617 format %{ "[$reg]" %}
4618 interface(MEMORY_INTER) %{
4619 base($reg);
4620 index(0x4);
4621 scale(0x0);
4622 disp(0x0);
4623 %}
4624 %}
4625
4626 // Indirect Memory Plus Short Offset Operand
4627 operand indOffset8(eRegP reg, immI8 off) %{
4628 match(AddP reg off);
4629
4630 format %{ "[$reg + $off]" %}
4631 interface(MEMORY_INTER) %{
4632 base($reg);
4633 index(0x4);
4634 scale(0x0);
4635 disp($off);
4636 %}
4637 %}
4638
4639 // Indirect Memory Plus Long Offset Operand
4640 operand indOffset32(eRegP reg, immI off) %{
4641 match(AddP reg off);
4642
4643 format %{ "[$reg + $off]" %}
4644 interface(MEMORY_INTER) %{
4645 base($reg);
4646 index(0x4);
4647 scale(0x0);
4648 disp($off);
4649 %}
4650 %}
4651
4652 // Indirect Memory Plus Long Offset Operand
4653 operand indOffset32X(rRegI reg, immP off) %{
4654 match(AddP off reg);
4655
4656 format %{ "[$reg + $off]" %}
4657 interface(MEMORY_INTER) %{
4658 base($reg);
4659 index(0x4);
4660 scale(0x0);
4661 disp($off);
4662 %}
4663 %}
4664
4665 // Indirect Memory Plus Index Register Plus Offset Operand
4666 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4667 match(AddP (AddP reg ireg) off);
4668
4669 op_cost(10);
4670 format %{"[$reg + $off + $ireg]" %}
4671 interface(MEMORY_INTER) %{
4672 base($reg);
4673 index($ireg);
4674 scale(0x0);
4675 disp($off);
4676 %}
4677 %}
4678
4679 // Indirect Memory Plus Index Register Plus Offset Operand
4680 operand indIndex(eRegP reg, rRegI ireg) %{
4681 match(AddP reg ireg);
4682
4683 op_cost(10);
4684 format %{"[$reg + $ireg]" %}
4685 interface(MEMORY_INTER) %{
4686 base($reg);
4687 index($ireg);
4688 scale(0x0);
4689 disp(0x0);
4690 %}
4691 %}
4692
4693 // // -------------------------------------------------------------------------
4694 // // 486 architecture doesn't support "scale * index + offset" with out a base
4695 // // -------------------------------------------------------------------------
4696 // // Scaled Memory Operands
4697 // // Indirect Memory Times Scale Plus Offset Operand
4698 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4699 // match(AddP off (LShiftI ireg scale));
4700 //
4701 // op_cost(10);
4702 // format %{"[$off + $ireg << $scale]" %}
4703 // interface(MEMORY_INTER) %{
4704 // base(0x4);
4705 // index($ireg);
4706 // scale($scale);
4707 // disp($off);
4708 // %}
4709 // %}
4710
4711 // Indirect Memory Times Scale Plus Index Register
4712 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4713 match(AddP reg (LShiftI ireg scale));
4714
4715 op_cost(10);
4716 format %{"[$reg + $ireg << $scale]" %}
4717 interface(MEMORY_INTER) %{
4718 base($reg);
4719 index($ireg);
4720 scale($scale);
4721 disp(0x0);
4722 %}
4723 %}
4724
4725 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4726 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4727 match(AddP (AddP reg (LShiftI ireg scale)) off);
4728
4729 op_cost(10);
4730 format %{"[$reg + $off + $ireg << $scale]" %}
4731 interface(MEMORY_INTER) %{
4732 base($reg);
4733 index($ireg);
4734 scale($scale);
4735 disp($off);
4736 %}
4737 %}
4738
4739 //----------Load Long Memory Operands------------------------------------------
4740 // The load-long idiom will use it's address expression again after loading
4741 // the first word of the long. If the load-long destination overlaps with
4742 // registers used in the addressing expression, the 2nd half will be loaded
4743 // from a clobbered address. Fix this by requiring that load-long use
4744 // address registers that do not overlap with the load-long target.
4745
4746 // load-long support
4747 operand load_long_RegP() %{
4748 constraint(ALLOC_IN_RC(esi_reg));
4749 match(RegP);
4750 match(eSIRegP);
4751 op_cost(100);
4752 format %{ %}
4753 interface(REG_INTER);
4754 %}
4755
4756 // Indirect Memory Operand Long
4757 operand load_long_indirect(load_long_RegP reg) %{
4758 constraint(ALLOC_IN_RC(esi_reg));
4759 match(reg);
4760
4761 format %{ "[$reg]" %}
4762 interface(MEMORY_INTER) %{
4763 base($reg);
4764 index(0x4);
4765 scale(0x0);
4766 disp(0x0);
4767 %}
4768 %}
4769
4770 // Indirect Memory Plus Long Offset Operand
4771 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4772 match(AddP reg off);
4773
4774 format %{ "[$reg + $off]" %}
4775 interface(MEMORY_INTER) %{
4776 base($reg);
4777 index(0x4);
4778 scale(0x0);
4779 disp($off);
4780 %}
4781 %}
4782
4783 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4784
4785
4786 //----------Special Memory Operands--------------------------------------------
4787 // Stack Slot Operand - This operand is used for loading and storing temporary
4788 // values on the stack where a match requires a value to
4789 // flow through memory.
4790 operand stackSlotP(sRegP reg) %{
4791 constraint(ALLOC_IN_RC(stack_slots));
4792 // No match rule because this operand is only generated in matching
4793 format %{ "[$reg]" %}
4794 interface(MEMORY_INTER) %{
4795 base(0x4); // ESP
4796 index(0x4); // No Index
4797 scale(0x0); // No Scale
4798 disp($reg); // Stack Offset
4799 %}
4800 %}
4801
4802 operand stackSlotI(sRegI reg) %{
4803 constraint(ALLOC_IN_RC(stack_slots));
4804 // No match rule because this operand is only generated in matching
4805 format %{ "[$reg]" %}
4806 interface(MEMORY_INTER) %{
4807 base(0x4); // ESP
4808 index(0x4); // No Index
4809 scale(0x0); // No Scale
4810 disp($reg); // Stack Offset
4811 %}
4812 %}
4813
4814 operand stackSlotF(sRegF reg) %{
4815 constraint(ALLOC_IN_RC(stack_slots));
4816 // No match rule because this operand is only generated in matching
4817 format %{ "[$reg]" %}
4818 interface(MEMORY_INTER) %{
4819 base(0x4); // ESP
4820 index(0x4); // No Index
4821 scale(0x0); // No Scale
4822 disp($reg); // Stack Offset
4823 %}
4824 %}
4825
4826 operand stackSlotD(sRegD reg) %{
4827 constraint(ALLOC_IN_RC(stack_slots));
4828 // No match rule because this operand is only generated in matching
4829 format %{ "[$reg]" %}
4830 interface(MEMORY_INTER) %{
4831 base(0x4); // ESP
4832 index(0x4); // No Index
4833 scale(0x0); // No Scale
4834 disp($reg); // Stack Offset
4835 %}
4836 %}
4837
4838 operand stackSlotL(sRegL reg) %{
4839 constraint(ALLOC_IN_RC(stack_slots));
4840 // No match rule because this operand is only generated in matching
4841 format %{ "[$reg]" %}
4842 interface(MEMORY_INTER) %{
4843 base(0x4); // ESP
4844 index(0x4); // No Index
4845 scale(0x0); // No Scale
4846 disp($reg); // Stack Offset
4847 %}
4848 %}
4849
4850 //----------Memory Operands - Win95 Implicit Null Variants----------------
4851 // Indirect Memory Operand
4852 operand indirect_win95_safe(eRegP_no_EBP reg)
4853 %{
4854 constraint(ALLOC_IN_RC(int_reg));
4855 match(reg);
4856
4857 op_cost(100);
4858 format %{ "[$reg]" %}
4859 interface(MEMORY_INTER) %{
4860 base($reg);
4861 index(0x4);
4862 scale(0x0);
4863 disp(0x0);
4864 %}
4865 %}
4866
4867 // Indirect Memory Plus Short Offset Operand
4868 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4869 %{
4870 match(AddP reg off);
4871
4872 op_cost(100);
4873 format %{ "[$reg + $off]" %}
4874 interface(MEMORY_INTER) %{
4875 base($reg);
4876 index(0x4);
4877 scale(0x0);
4878 disp($off);
4879 %}
4880 %}
4881
4882 // Indirect Memory Plus Long Offset Operand
4883 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4884 %{
4885 match(AddP reg off);
4886
4887 op_cost(100);
4888 format %{ "[$reg + $off]" %}
4889 interface(MEMORY_INTER) %{
4890 base($reg);
4891 index(0x4);
4892 scale(0x0);
4893 disp($off);
4894 %}
4895 %}
4896
4897 // Indirect Memory Plus Index Register Plus Offset Operand
4898 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4899 %{
4900 match(AddP (AddP reg ireg) off);
4901
4902 op_cost(100);
4903 format %{"[$reg + $off + $ireg]" %}
4904 interface(MEMORY_INTER) %{
4905 base($reg);
4906 index($ireg);
4907 scale(0x0);
4908 disp($off);
4909 %}
4910 %}
4911
4912 // Indirect Memory Times Scale Plus Index Register
4913 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4914 %{
4915 match(AddP reg (LShiftI ireg scale));
4916
4917 op_cost(100);
4918 format %{"[$reg + $ireg << $scale]" %}
4919 interface(MEMORY_INTER) %{
4920 base($reg);
4921 index($ireg);
4922 scale($scale);
4923 disp(0x0);
4924 %}
4925 %}
4926
4927 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4928 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4929 %{
4930 match(AddP (AddP reg (LShiftI ireg scale)) off);
4931
4932 op_cost(100);
4933 format %{"[$reg + $off + $ireg << $scale]" %}
4934 interface(MEMORY_INTER) %{
4935 base($reg);
4936 index($ireg);
4937 scale($scale);
4938 disp($off);
4939 %}
4940 %}
4941
4942 //----------Conditional Branch Operands----------------------------------------
4943 // Comparison Op - This is the operation of the comparison, and is limited to
4944 // the following set of codes:
4945 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4946 //
4947 // Other attributes of the comparison, such as unsignedness, are specified
4948 // by the comparison instruction that sets a condition code flags register.
4949 // That result is represented by a flags operand whose subtype is appropriate
4950 // to the unsignedness (etc.) of the comparison.
4951 //
4952 // Later, the instruction which matches both the Comparison Op (a Bool) and
4953 // the flags (produced by the Cmp) specifies the coding of the comparison op
4954 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4955
4956 // Comparision Code
4957 operand cmpOp() %{
4958 match(Bool);
4959
4960 format %{ "" %}
4961 interface(COND_INTER) %{
4962 equal(0x4, "e");
4963 not_equal(0x5, "ne");
4964 less(0xC, "l");
4965 greater_equal(0xD, "ge");
4966 less_equal(0xE, "le");
4967 greater(0xF, "g");
4968 %}
4969 %}
4970
4971 // Comparison Code, unsigned compare. Used by FP also, with
4972 // C2 (unordered) turned into GT or LT already. The other bits
4973 // C0 and C3 are turned into Carry & Zero flags.
4974 operand cmpOpU() %{
4975 match(Bool);
4976
4977 format %{ "" %}
4978 interface(COND_INTER) %{
4979 equal(0x4, "e");
4980 not_equal(0x5, "ne");
4981 less(0x2, "b");
4982 greater_equal(0x3, "nb");
4983 less_equal(0x6, "be");
4984 greater(0x7, "nbe");
4985 %}
4986 %}
4987
4988 // Floating comparisons that don't require any fixup for the unordered case
4989 operand cmpOpUCF() %{
4990 match(Bool);
4991 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4992 n->as_Bool()->_test._test == BoolTest::ge ||
4993 n->as_Bool()->_test._test == BoolTest::le ||
4994 n->as_Bool()->_test._test == BoolTest::gt);
4995 format %{ "" %}
4996 interface(COND_INTER) %{
4997 equal(0x4, "e");
4998 not_equal(0x5, "ne");
4999 less(0x2, "b");
5000 greater_equal(0x3, "nb");
5001 less_equal(0x6, "be");
5002 greater(0x7, "nbe");
5003 %}
5004 %}
5005
5006
5007 // Floating comparisons that can be fixed up with extra conditional jumps
5008 operand cmpOpUCF2() %{
5009 match(Bool);
5010 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5011 n->as_Bool()->_test._test == BoolTest::eq);
5012 format %{ "" %}
5013 interface(COND_INTER) %{
5014 equal(0x4, "e");
5015 not_equal(0x5, "ne");
5016 less(0x2, "b");
5017 greater_equal(0x3, "nb");
5018 less_equal(0x6, "be");
5019 greater(0x7, "nbe");
5020 %}
5021 %}
5022
5023 // Comparison Code for FP conditional move
5024 operand cmpOp_fcmov() %{
5025 match(Bool);
5026
5027 format %{ "" %}
5028 interface(COND_INTER) %{
5029 equal (0x0C8);
5030 not_equal (0x1C8);
5031 less (0x0C0);
5032 greater_equal(0x1C0);
5033 less_equal (0x0D0);
5034 greater (0x1D0);
5035 %}
5036 %}
5037
5038 // Comparision Code used in long compares
5039 operand cmpOp_commute() %{
5040 match(Bool);
5041
5042 format %{ "" %}
5043 interface(COND_INTER) %{
5044 equal(0x4, "e");
5045 not_equal(0x5, "ne");
5046 less(0xF, "g");
5047 greater_equal(0xE, "le");
5048 less_equal(0xD, "ge");
5049 greater(0xC, "l");
5050 %}
5051 %}
5052
5053 //----------OPERAND CLASSES----------------------------------------------------
5054 // Operand Classes are groups of operands that are used as to simplify
5055 // instruction definitions by not requiring the AD writer to specify separate
5056 // instructions for every form of operand when the instruction accepts
5057 // multiple operand types with the same basic encoding and format. The classic
5058 // case of this is memory operands.
5059
5060 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5061 indIndex, indIndexScale, indIndexScaleOffset);
5062
5063 // Long memory operations are encoded in 2 instructions and a +4 offset.
5064 // This means some kind of offset is always required and you cannot use
5065 // an oop as the offset (done when working on static globals).
5066 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5067 indIndex, indIndexScale, indIndexScaleOffset);
5068
5069
5070 //----------PIPELINE-----------------------------------------------------------
5071 // Rules which define the behavior of the target architectures pipeline.
5072 pipeline %{
5073
5074 //----------ATTRIBUTES---------------------------------------------------------
5075 attributes %{
5076 variable_size_instructions; // Fixed size instructions
5077 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5078 instruction_unit_size = 1; // An instruction is 1 bytes long
5079 instruction_fetch_unit_size = 16; // The processor fetches one line
5080 instruction_fetch_units = 1; // of 16 bytes
5081
5082 // List of nop instructions
5083 nops( MachNop );
5084 %}
5085
5086 //----------RESOURCES----------------------------------------------------------
5087 // Resources are the functional units available to the machine
5088
5089 // Generic P2/P3 pipeline
5090 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5091 // 3 instructions decoded per cycle.
5092 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5093 // 2 ALU op, only ALU0 handles mul/div instructions.
5094 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5095 MS0, MS1, MEM = MS0 | MS1,
5096 BR, FPU,
5097 ALU0, ALU1, ALU = ALU0 | ALU1 );
5098
5099 //----------PIPELINE DESCRIPTION-----------------------------------------------
5100 // Pipeline Description specifies the stages in the machine's pipeline
5101
5102 // Generic P2/P3 pipeline
5103 pipe_desc(S0, S1, S2, S3, S4, S5);
5104
5105 //----------PIPELINE CLASSES---------------------------------------------------
5106 // Pipeline Classes describe the stages in which input and output are
5107 // referenced by the hardware pipeline.
5108
5109 // Naming convention: ialu or fpu
5110 // Then: _reg
5111 // Then: _reg if there is a 2nd register
5112 // Then: _long if it's a pair of instructions implementing a long
5113 // Then: _fat if it requires the big decoder
5114 // Or: _mem if it requires the big decoder and a memory unit.
5115
5116 // Integer ALU reg operation
5117 pipe_class ialu_reg(rRegI dst) %{
5118 single_instruction;
5119 dst : S4(write);
5120 dst : S3(read);
5121 DECODE : S0; // any decoder
5122 ALU : S3; // any alu
5123 %}
5124
5125 // Long ALU reg operation
5126 pipe_class ialu_reg_long(eRegL dst) %{
5127 instruction_count(2);
5128 dst : S4(write);
5129 dst : S3(read);
5130 DECODE : S0(2); // any 2 decoders
5131 ALU : S3(2); // both alus
5132 %}
5133
5134 // Integer ALU reg operation using big decoder
5135 pipe_class ialu_reg_fat(rRegI dst) %{
5136 single_instruction;
5137 dst : S4(write);
5138 dst : S3(read);
5139 D0 : S0; // big decoder only
5140 ALU : S3; // any alu
5141 %}
5142
5143 // Long ALU reg operation using big decoder
5144 pipe_class ialu_reg_long_fat(eRegL dst) %{
5145 instruction_count(2);
5146 dst : S4(write);
5147 dst : S3(read);
5148 D0 : S0(2); // big decoder only; twice
5149 ALU : S3(2); // any 2 alus
5150 %}
5151
5152 // Integer ALU reg-reg operation
5153 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5154 single_instruction;
5155 dst : S4(write);
5156 src : S3(read);
5157 DECODE : S0; // any decoder
5158 ALU : S3; // any alu
5159 %}
5160
5161 // Long ALU reg-reg operation
5162 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5163 instruction_count(2);
5164 dst : S4(write);
5165 src : S3(read);
5166 DECODE : S0(2); // any 2 decoders
5167 ALU : S3(2); // both alus
5168 %}
5169
5170 // Integer ALU reg-reg operation
5171 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5172 single_instruction;
5173 dst : S4(write);
5174 src : S3(read);
5175 D0 : S0; // big decoder only
5176 ALU : S3; // any alu
5177 %}
5178
5179 // Long ALU reg-reg operation
5180 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5181 instruction_count(2);
5182 dst : S4(write);
5183 src : S3(read);
5184 D0 : S0(2); // big decoder only; twice
5185 ALU : S3(2); // both alus
5186 %}
5187
5188 // Integer ALU reg-mem operation
5189 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5190 single_instruction;
5191 dst : S5(write);
5192 mem : S3(read);
5193 D0 : S0; // big decoder only
5194 ALU : S4; // any alu
5195 MEM : S3; // any mem
5196 %}
5197
5198 // Long ALU reg-mem operation
5199 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5200 instruction_count(2);
5201 dst : S5(write);
5202 mem : S3(read);
5203 D0 : S0(2); // big decoder only; twice
5204 ALU : S4(2); // any 2 alus
5205 MEM : S3(2); // both mems
5206 %}
5207
5208 // Integer mem operation (prefetch)
5209 pipe_class ialu_mem(memory mem)
5210 %{
5211 single_instruction;
5212 mem : S3(read);
5213 D0 : S0; // big decoder only
5214 MEM : S3; // any mem
5215 %}
5216
5217 // Integer Store to Memory
5218 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5219 single_instruction;
5220 mem : S3(read);
5221 src : S5(read);
5222 D0 : S0; // big decoder only
5223 ALU : S4; // any alu
5224 MEM : S3;
5225 %}
5226
5227 // Long Store to Memory
5228 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5229 instruction_count(2);
5230 mem : S3(read);
5231 src : S5(read);
5232 D0 : S0(2); // big decoder only; twice
5233 ALU : S4(2); // any 2 alus
5234 MEM : S3(2); // Both mems
5235 %}
5236
5237 // Integer Store to Memory
5238 pipe_class ialu_mem_imm(memory mem) %{
5239 single_instruction;
5240 mem : S3(read);
5241 D0 : S0; // big decoder only
5242 ALU : S4; // any alu
5243 MEM : S3;
5244 %}
5245
5246 // Integer ALU0 reg-reg operation
5247 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5248 single_instruction;
5249 dst : S4(write);
5250 src : S3(read);
5251 D0 : S0; // Big decoder only
5252 ALU0 : S3; // only alu0
5253 %}
5254
5255 // Integer ALU0 reg-mem operation
5256 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5257 single_instruction;
5258 dst : S5(write);
5259 mem : S3(read);
5260 D0 : S0; // big decoder only
5261 ALU0 : S4; // ALU0 only
5262 MEM : S3; // any mem
5263 %}
5264
5265 // Integer ALU reg-reg operation
5266 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5267 single_instruction;
5268 cr : S4(write);
5269 src1 : S3(read);
5270 src2 : S3(read);
5271 DECODE : S0; // any decoder
5272 ALU : S3; // any alu
5273 %}
5274
5275 // Integer ALU reg-imm operation
5276 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5277 single_instruction;
5278 cr : S4(write);
5279 src1 : S3(read);
5280 DECODE : S0; // any decoder
5281 ALU : S3; // any alu
5282 %}
5283
5284 // Integer ALU reg-mem operation
5285 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5286 single_instruction;
5287 cr : S4(write);
5288 src1 : S3(read);
5289 src2 : S3(read);
5290 D0 : S0; // big decoder only
5291 ALU : S4; // any alu
5292 MEM : S3;
5293 %}
5294
5295 // Conditional move reg-reg
5296 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5297 instruction_count(4);
5298 y : S4(read);
5299 q : S3(read);
5300 p : S3(read);
5301 DECODE : S0(4); // any decoder
5302 %}
5303
5304 // Conditional move reg-reg
5305 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5306 single_instruction;
5307 dst : S4(write);
5308 src : S3(read);
5309 cr : S3(read);
5310 DECODE : S0; // any decoder
5311 %}
5312
5313 // Conditional move reg-mem
5314 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5315 single_instruction;
5316 dst : S4(write);
5317 src : S3(read);
5318 cr : S3(read);
5319 DECODE : S0; // any decoder
5320 MEM : S3;
5321 %}
5322
5323 // Conditional move reg-reg long
5324 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5325 single_instruction;
5326 dst : S4(write);
5327 src : S3(read);
5328 cr : S3(read);
5329 DECODE : S0(2); // any 2 decoders
5330 %}
5331
5332 // Conditional move double reg-reg
5333 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5334 single_instruction;
5335 dst : S4(write);
5336 src : S3(read);
5337 cr : S3(read);
5338 DECODE : S0; // any decoder
5339 %}
5340
5341 // Float reg-reg operation
5342 pipe_class fpu_reg(regDPR dst) %{
5343 instruction_count(2);
5344 dst : S3(read);
5345 DECODE : S0(2); // any 2 decoders
5346 FPU : S3;
5347 %}
5348
5349 // Float reg-reg operation
5350 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5351 instruction_count(2);
5352 dst : S4(write);
5353 src : S3(read);
5354 DECODE : S0(2); // any 2 decoders
5355 FPU : S3;
5356 %}
5357
5358 // Float reg-reg operation
5359 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5360 instruction_count(3);
5361 dst : S4(write);
5362 src1 : S3(read);
5363 src2 : S3(read);
5364 DECODE : S0(3); // any 3 decoders
5365 FPU : S3(2);
5366 %}
5367
5368 // Float reg-reg operation
5369 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5370 instruction_count(4);
5371 dst : S4(write);
5372 src1 : S3(read);
5373 src2 : S3(read);
5374 src3 : S3(read);
5375 DECODE : S0(4); // any 3 decoders
5376 FPU : S3(2);
5377 %}
5378
5379 // Float reg-reg operation
5380 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5381 instruction_count(4);
5382 dst : S4(write);
5383 src1 : S3(read);
5384 src2 : S3(read);
5385 src3 : S3(read);
5386 DECODE : S1(3); // any 3 decoders
5387 D0 : S0; // Big decoder only
5388 FPU : S3(2);
5389 MEM : S3;
5390 %}
5391
5392 // Float reg-mem operation
5393 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5394 instruction_count(2);
5395 dst : S5(write);
5396 mem : S3(read);
5397 D0 : S0; // big decoder only
5398 DECODE : S1; // any decoder for FPU POP
5399 FPU : S4;
5400 MEM : S3; // any mem
5401 %}
5402
5403 // Float reg-mem operation
5404 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5405 instruction_count(3);
5406 dst : S5(write);
5407 src1 : S3(read);
5408 mem : S3(read);
5409 D0 : S0; // big decoder only
5410 DECODE : S1(2); // any decoder for FPU POP
5411 FPU : S4;
5412 MEM : S3; // any mem
5413 %}
5414
5415 // Float mem-reg operation
5416 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5417 instruction_count(2);
5418 src : S5(read);
5419 mem : S3(read);
5420 DECODE : S0; // any decoder for FPU PUSH
5421 D0 : S1; // big decoder only
5422 FPU : S4;
5423 MEM : S3; // any mem
5424 %}
5425
5426 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5427 instruction_count(3);
5428 src1 : S3(read);
5429 src2 : S3(read);
5430 mem : S3(read);
5431 DECODE : S0(2); // any decoder for FPU PUSH
5432 D0 : S1; // big decoder only
5433 FPU : S4;
5434 MEM : S3; // any mem
5435 %}
5436
5437 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5438 instruction_count(3);
5439 src1 : S3(read);
5440 src2 : S3(read);
5441 mem : S4(read);
5442 DECODE : S0; // any decoder for FPU PUSH
5443 D0 : S0(2); // big decoder only
5444 FPU : S4;
5445 MEM : S3(2); // any mem
5446 %}
5447
5448 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5449 instruction_count(2);
5450 src1 : S3(read);
5451 dst : S4(read);
5452 D0 : S0(2); // big decoder only
5453 MEM : S3(2); // any mem
5454 %}
5455
5456 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5457 instruction_count(3);
5458 src1 : S3(read);
5459 src2 : S3(read);
5460 dst : S4(read);
5461 D0 : S0(3); // big decoder only
5462 FPU : S4;
5463 MEM : S3(3); // any mem
5464 %}
5465
5466 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5467 instruction_count(3);
5468 src1 : S4(read);
5469 mem : S4(read);
5470 DECODE : S0; // any decoder for FPU PUSH
5471 D0 : S0(2); // big decoder only
5472 FPU : S4;
5473 MEM : S3(2); // any mem
5474 %}
5475
5476 // Float load constant
5477 pipe_class fpu_reg_con(regDPR dst) %{
5478 instruction_count(2);
5479 dst : S5(write);
5480 D0 : S0; // big decoder only for the load
5481 DECODE : S1; // any decoder for FPU POP
5482 FPU : S4;
5483 MEM : S3; // any mem
5484 %}
5485
5486 // Float load constant
5487 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5488 instruction_count(3);
5489 dst : S5(write);
5490 src : S3(read);
5491 D0 : S0; // big decoder only for the load
5492 DECODE : S1(2); // any decoder for FPU POP
5493 FPU : S4;
5494 MEM : S3; // any mem
5495 %}
5496
5497 // UnConditional branch
5498 pipe_class pipe_jmp( label labl ) %{
5499 single_instruction;
5500 BR : S3;
5501 %}
5502
5503 // Conditional branch
5504 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5505 single_instruction;
5506 cr : S1(read);
5507 BR : S3;
5508 %}
5509
5510 // Allocation idiom
5511 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5512 instruction_count(1); force_serialization;
5513 fixed_latency(6);
5514 heap_ptr : S3(read);
5515 DECODE : S0(3);
5516 D0 : S2;
5517 MEM : S3;
5518 ALU : S3(2);
5519 dst : S5(write);
5520 BR : S5;
5521 %}
5522
5523 // Generic big/slow expanded idiom
5524 pipe_class pipe_slow( ) %{
5525 instruction_count(10); multiple_bundles; force_serialization;
5526 fixed_latency(100);
5527 D0 : S0(2);
5528 MEM : S3(2);
5529 %}
5530
5531 // The real do-nothing guy
5532 pipe_class empty( ) %{
5533 instruction_count(0);
5534 %}
5535
5536 // Define the class for the Nop node
5537 define %{
5538 MachNop = empty;
5539 %}
5540
5541 %}
5542
5543 //----------INSTRUCTIONS-------------------------------------------------------
5544 //
5545 // match -- States which machine-independent subtree may be replaced
5546 // by this instruction.
5547 // ins_cost -- The estimated cost of this instruction is used by instruction
5548 // selection to identify a minimum cost tree of machine
5549 // instructions that matches a tree of machine-independent
5550 // instructions.
5551 // format -- A string providing the disassembly for this instruction.
5552 // The value of an instruction's operand may be inserted
5553 // by referring to it with a '$' prefix.
5554 // opcode -- Three instruction opcodes may be provided. These are referred
5555 // to within an encode class as $primary, $secondary, and $tertiary
5556 // respectively. The primary opcode is commonly used to
5557 // indicate the type of machine instruction, while secondary
5558 // and tertiary are often used for prefix options or addressing
5559 // modes.
5560 // ins_encode -- A list of encode classes with parameters. The encode class
5561 // name must have been defined in an 'enc_class' specification
5562 // in the encode section of the architecture description.
5563
5564 //----------BSWAP-Instruction--------------------------------------------------
5565 instruct bytes_reverse_int(rRegI dst) %{
5566 match(Set dst (ReverseBytesI dst));
5567
5568 format %{ "BSWAP $dst" %}
5569 opcode(0x0F, 0xC8);
5570 ins_encode( OpcP, OpcSReg(dst) );
5571 ins_pipe( ialu_reg );
5572 %}
5573
5574 instruct bytes_reverse_long(eRegL dst) %{
5575 match(Set dst (ReverseBytesL dst));
5576
5577 format %{ "BSWAP $dst.lo\n\t"
5578 "BSWAP $dst.hi\n\t"
5579 "XCHG $dst.lo $dst.hi" %}
5580
5581 ins_cost(125);
5582 ins_encode( bswap_long_bytes(dst) );
5583 ins_pipe( ialu_reg_reg);
5584 %}
5585
5586 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5587 match(Set dst (ReverseBytesUS dst));
5588 effect(KILL cr);
5589
5590 format %{ "BSWAP $dst\n\t"
5591 "SHR $dst,16\n\t" %}
5592 ins_encode %{
5593 __ bswapl($dst$$Register);
5594 __ shrl($dst$$Register, 16);
5595 %}
5596 ins_pipe( ialu_reg );
5597 %}
5598
5599 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5600 match(Set dst (ReverseBytesS dst));
5601 effect(KILL cr);
5602
5603 format %{ "BSWAP $dst\n\t"
5604 "SAR $dst,16\n\t" %}
5605 ins_encode %{
5606 __ bswapl($dst$$Register);
5607 __ sarl($dst$$Register, 16);
5608 %}
5609 ins_pipe( ialu_reg );
5610 %}
5611
5612
5613 //---------- Zeros Count Instructions ------------------------------------------
5614
5615 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5616 predicate(UseCountLeadingZerosInstruction);
5617 match(Set dst (CountLeadingZerosI src));
5618 effect(KILL cr);
5619
5620 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5621 ins_encode %{
5622 __ lzcntl($dst$$Register, $src$$Register);
5623 %}
5624 ins_pipe(ialu_reg);
5625 %}
5626
5627 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5628 predicate(!UseCountLeadingZerosInstruction);
5629 match(Set dst (CountLeadingZerosI src));
5630 effect(KILL cr);
5631
5632 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5633 "JNZ skip\n\t"
5634 "MOV $dst, -1\n"
5635 "skip:\n\t"
5636 "NEG $dst\n\t"
5637 "ADD $dst, 31" %}
5638 ins_encode %{
5639 Register Rdst = $dst$$Register;
5640 Register Rsrc = $src$$Register;
5641 Label skip;
5642 __ bsrl(Rdst, Rsrc);
5643 __ jccb(Assembler::notZero, skip);
5644 __ movl(Rdst, -1);
5645 __ bind(skip);
5646 __ negl(Rdst);
5647 __ addl(Rdst, BitsPerInt - 1);
5648 %}
5649 ins_pipe(ialu_reg);
5650 %}
5651
5652 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5653 predicate(UseCountLeadingZerosInstruction);
5654 match(Set dst (CountLeadingZerosL src));
5655 effect(TEMP dst, KILL cr);
5656
5657 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5658 "JNC done\n\t"
5659 "LZCNT $dst, $src.lo\n\t"
5660 "ADD $dst, 32\n"
5661 "done:" %}
5662 ins_encode %{
5663 Register Rdst = $dst$$Register;
5664 Register Rsrc = $src$$Register;
5665 Label done;
5666 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5667 __ jccb(Assembler::carryClear, done);
5668 __ lzcntl(Rdst, Rsrc);
5669 __ addl(Rdst, BitsPerInt);
5670 __ bind(done);
5671 %}
5672 ins_pipe(ialu_reg);
5673 %}
5674
5675 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5676 predicate(!UseCountLeadingZerosInstruction);
5677 match(Set dst (CountLeadingZerosL src));
5678 effect(TEMP dst, KILL cr);
5679
5680 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5681 "JZ msw_is_zero\n\t"
5682 "ADD $dst, 32\n\t"
5683 "JMP not_zero\n"
5684 "msw_is_zero:\n\t"
5685 "BSR $dst, $src.lo\n\t"
5686 "JNZ not_zero\n\t"
5687 "MOV $dst, -1\n"
5688 "not_zero:\n\t"
5689 "NEG $dst\n\t"
5690 "ADD $dst, 63\n" %}
5691 ins_encode %{
5692 Register Rdst = $dst$$Register;
5693 Register Rsrc = $src$$Register;
5694 Label msw_is_zero;
5695 Label not_zero;
5696 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5697 __ jccb(Assembler::zero, msw_is_zero);
5698 __ addl(Rdst, BitsPerInt);
5699 __ jmpb(not_zero);
5700 __ bind(msw_is_zero);
5701 __ bsrl(Rdst, Rsrc);
5702 __ jccb(Assembler::notZero, not_zero);
5703 __ movl(Rdst, -1);
5704 __ bind(not_zero);
5705 __ negl(Rdst);
5706 __ addl(Rdst, BitsPerLong - 1);
5707 %}
5708 ins_pipe(ialu_reg);
5709 %}
5710
5711 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5712 match(Set dst (CountTrailingZerosI src));
5713 effect(KILL cr);
5714
5715 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5716 "JNZ done\n\t"
5717 "MOV $dst, 32\n"
5718 "done:" %}
5719 ins_encode %{
5720 Register Rdst = $dst$$Register;
5721 Label done;
5722 __ bsfl(Rdst, $src$$Register);
5723 __ jccb(Assembler::notZero, done);
5724 __ movl(Rdst, BitsPerInt);
5725 __ bind(done);
5726 %}
5727 ins_pipe(ialu_reg);
5728 %}
5729
5730 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5731 match(Set dst (CountTrailingZerosL src));
5732 effect(TEMP dst, KILL cr);
5733
5734 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5735 "JNZ done\n\t"
5736 "BSF $dst, $src.hi\n\t"
5737 "JNZ msw_not_zero\n\t"
5738 "MOV $dst, 32\n"
5739 "msw_not_zero:\n\t"
5740 "ADD $dst, 32\n"
5741 "done:" %}
5742 ins_encode %{
5743 Register Rdst = $dst$$Register;
5744 Register Rsrc = $src$$Register;
5745 Label msw_not_zero;
5746 Label done;
5747 __ bsfl(Rdst, Rsrc);
5748 __ jccb(Assembler::notZero, done);
5749 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5750 __ jccb(Assembler::notZero, msw_not_zero);
5751 __ movl(Rdst, BitsPerInt);
5752 __ bind(msw_not_zero);
5753 __ addl(Rdst, BitsPerInt);
5754 __ bind(done);
5755 %}
5756 ins_pipe(ialu_reg);
5757 %}
5758
5759
5760 //---------- Population Count Instructions -------------------------------------
5761
5762 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5763 predicate(UsePopCountInstruction);
5764 match(Set dst (PopCountI src));
5765 effect(KILL cr);
5766
5767 format %{ "POPCNT $dst, $src" %}
5768 ins_encode %{
5769 __ popcntl($dst$$Register, $src$$Register);
5770 %}
5771 ins_pipe(ialu_reg);
5772 %}
5773
5774 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5775 predicate(UsePopCountInstruction);
5776 match(Set dst (PopCountI (LoadI mem)));
5777 effect(KILL cr);
5778
5779 format %{ "POPCNT $dst, $mem" %}
5780 ins_encode %{
5781 __ popcntl($dst$$Register, $mem$$Address);
5782 %}
5783 ins_pipe(ialu_reg);
5784 %}
5785
5786 // Note: Long.bitCount(long) returns an int.
5787 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5788 predicate(UsePopCountInstruction);
5789 match(Set dst (PopCountL src));
5790 effect(KILL cr, TEMP tmp, TEMP dst);
5791
5792 format %{ "POPCNT $dst, $src.lo\n\t"
5793 "POPCNT $tmp, $src.hi\n\t"
5794 "ADD $dst, $tmp" %}
5795 ins_encode %{
5796 __ popcntl($dst$$Register, $src$$Register);
5797 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5798 __ addl($dst$$Register, $tmp$$Register);
5799 %}
5800 ins_pipe(ialu_reg);
5801 %}
5802
5803 // Note: Long.bitCount(long) returns an int.
5804 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5805 predicate(UsePopCountInstruction);
5806 match(Set dst (PopCountL (LoadL mem)));
5807 effect(KILL cr, TEMP tmp, TEMP dst);
5808
5809 format %{ "POPCNT $dst, $mem\n\t"
5810 "POPCNT $tmp, $mem+4\n\t"
5811 "ADD $dst, $tmp" %}
5812 ins_encode %{
5813 //__ popcntl($dst$$Register, $mem$$Address$$first);
5814 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5815 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5816 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5817 __ addl($dst$$Register, $tmp$$Register);
5818 %}
5819 ins_pipe(ialu_reg);
5820 %}
5821
5822
5823 //----------Load/Store/Move Instructions---------------------------------------
5824 //----------Load Instructions--------------------------------------------------
5825 // Load Byte (8bit signed)
5826 instruct loadB(xRegI dst, memory mem) %{
5827 match(Set dst (LoadB mem));
5828
5829 ins_cost(125);
5830 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5831
5832 ins_encode %{
5833 __ movsbl($dst$$Register, $mem$$Address);
5834 %}
5835
5836 ins_pipe(ialu_reg_mem);
5837 %}
5838
5839 // Load Byte (8bit signed) into Long Register
5840 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5841 match(Set dst (ConvI2L (LoadB mem)));
5842 effect(KILL cr);
5843
5844 ins_cost(375);
5845 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5846 "MOV $dst.hi,$dst.lo\n\t"
5847 "SAR $dst.hi,7" %}
5848
5849 ins_encode %{
5850 __ movsbl($dst$$Register, $mem$$Address);
5851 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5852 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5853 %}
5854
5855 ins_pipe(ialu_reg_mem);
5856 %}
5857
5858 // Load Unsigned Byte (8bit UNsigned)
5859 instruct loadUB(xRegI dst, memory mem) %{
5860 match(Set dst (LoadUB mem));
5861
5862 ins_cost(125);
5863 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5864
5865 ins_encode %{
5866 __ movzbl($dst$$Register, $mem$$Address);
5867 %}
5868
5869 ins_pipe(ialu_reg_mem);
5870 %}
5871
5872 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5873 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5874 match(Set dst (ConvI2L (LoadUB mem)));
5875 effect(KILL cr);
5876
5877 ins_cost(250);
5878 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5879 "XOR $dst.hi,$dst.hi" %}
5880
5881 ins_encode %{
5882 Register Rdst = $dst$$Register;
5883 __ movzbl(Rdst, $mem$$Address);
5884 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5885 %}
5886
5887 ins_pipe(ialu_reg_mem);
5888 %}
5889
5890 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5891 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5892 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5893 effect(KILL cr);
5894
5895 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5896 "XOR $dst.hi,$dst.hi\n\t"
5897 "AND $dst.lo,$mask" %}
5898 ins_encode %{
5899 Register Rdst = $dst$$Register;
5900 __ movzbl(Rdst, $mem$$Address);
5901 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5902 __ andl(Rdst, $mask$$constant);
5903 %}
5904 ins_pipe(ialu_reg_mem);
5905 %}
5906
5907 // Load Short (16bit signed)
5908 instruct loadS(rRegI dst, memory mem) %{
5909 match(Set dst (LoadS mem));
5910
5911 ins_cost(125);
5912 format %{ "MOVSX $dst,$mem\t# short" %}
5913
5914 ins_encode %{
5915 __ movswl($dst$$Register, $mem$$Address);
5916 %}
5917
5918 ins_pipe(ialu_reg_mem);
5919 %}
5920
5921 // Load Short (16 bit signed) to Byte (8 bit signed)
5922 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5923 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5924
5925 ins_cost(125);
5926 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5927 ins_encode %{
5928 __ movsbl($dst$$Register, $mem$$Address);
5929 %}
5930 ins_pipe(ialu_reg_mem);
5931 %}
5932
5933 // Load Short (16bit signed) into Long Register
5934 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5935 match(Set dst (ConvI2L (LoadS mem)));
5936 effect(KILL cr);
5937
5938 ins_cost(375);
5939 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5940 "MOV $dst.hi,$dst.lo\n\t"
5941 "SAR $dst.hi,15" %}
5942
5943 ins_encode %{
5944 __ movswl($dst$$Register, $mem$$Address);
5945 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5946 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5947 %}
5948
5949 ins_pipe(ialu_reg_mem);
5950 %}
5951
5952 // Load Unsigned Short/Char (16bit unsigned)
5953 instruct loadUS(rRegI dst, memory mem) %{
5954 match(Set dst (LoadUS mem));
5955
5956 ins_cost(125);
5957 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5958
5959 ins_encode %{
5960 __ movzwl($dst$$Register, $mem$$Address);
5961 %}
5962
5963 ins_pipe(ialu_reg_mem);
5964 %}
5965
5966 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5967 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5968 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5969
5970 ins_cost(125);
5971 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5972 ins_encode %{
5973 __ movsbl($dst$$Register, $mem$$Address);
5974 %}
5975 ins_pipe(ialu_reg_mem);
5976 %}
5977
5978 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5979 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5980 match(Set dst (ConvI2L (LoadUS mem)));
5981 effect(KILL cr);
5982
5983 ins_cost(250);
5984 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5985 "XOR $dst.hi,$dst.hi" %}
5986
5987 ins_encode %{
5988 __ movzwl($dst$$Register, $mem$$Address);
5989 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5990 %}
5991
5992 ins_pipe(ialu_reg_mem);
5993 %}
5994
5995 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5996 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5997 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5998 effect(KILL cr);
5999
6000 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6001 "XOR $dst.hi,$dst.hi" %}
6002 ins_encode %{
6003 Register Rdst = $dst$$Register;
6004 __ movzbl(Rdst, $mem$$Address);
6005 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6006 %}
6007 ins_pipe(ialu_reg_mem);
6008 %}
6009
6010 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6011 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6012 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6013 effect(KILL cr);
6014
6015 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6016 "XOR $dst.hi,$dst.hi\n\t"
6017 "AND $dst.lo,$mask" %}
6018 ins_encode %{
6019 Register Rdst = $dst$$Register;
6020 __ movzwl(Rdst, $mem$$Address);
6021 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6022 __ andl(Rdst, $mask$$constant);
6023 %}
6024 ins_pipe(ialu_reg_mem);
6025 %}
6026
6027 // Load Integer
6028 instruct loadI(rRegI dst, memory mem) %{
6029 match(Set dst (LoadI mem));
6030
6031 ins_cost(125);
6032 format %{ "MOV $dst,$mem\t# int" %}
6033
6034 ins_encode %{
6035 __ movl($dst$$Register, $mem$$Address);
6036 %}
6037
6038 ins_pipe(ialu_reg_mem);
6039 %}
6040
6041 // Load Integer (32 bit signed) to Byte (8 bit signed)
6042 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6043 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6044
6045 ins_cost(125);
6046 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6047 ins_encode %{
6048 __ movsbl($dst$$Register, $mem$$Address);
6049 %}
6050 ins_pipe(ialu_reg_mem);
6051 %}
6052
6053 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6054 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6055 match(Set dst (AndI (LoadI mem) mask));
6056
6057 ins_cost(125);
6058 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6059 ins_encode %{
6060 __ movzbl($dst$$Register, $mem$$Address);
6061 %}
6062 ins_pipe(ialu_reg_mem);
6063 %}
6064
6065 // Load Integer (32 bit signed) to Short (16 bit signed)
6066 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6067 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6068
6069 ins_cost(125);
6070 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6071 ins_encode %{
6072 __ movswl($dst$$Register, $mem$$Address);
6073 %}
6074 ins_pipe(ialu_reg_mem);
6075 %}
6076
6077 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6078 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6079 match(Set dst (AndI (LoadI mem) mask));
6080
6081 ins_cost(125);
6082 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6083 ins_encode %{
6084 __ movzwl($dst$$Register, $mem$$Address);
6085 %}
6086 ins_pipe(ialu_reg_mem);
6087 %}
6088
6089 // Load Integer into Long Register
6090 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6091 match(Set dst (ConvI2L (LoadI mem)));
6092 effect(KILL cr);
6093
6094 ins_cost(375);
6095 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6096 "MOV $dst.hi,$dst.lo\n\t"
6097 "SAR $dst.hi,31" %}
6098
6099 ins_encode %{
6100 __ movl($dst$$Register, $mem$$Address);
6101 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6102 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6103 %}
6104
6105 ins_pipe(ialu_reg_mem);
6106 %}
6107
6108 // Load Integer with mask 0xFF into Long Register
6109 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6110 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6111 effect(KILL cr);
6112
6113 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6114 "XOR $dst.hi,$dst.hi" %}
6115 ins_encode %{
6116 Register Rdst = $dst$$Register;
6117 __ movzbl(Rdst, $mem$$Address);
6118 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6119 %}
6120 ins_pipe(ialu_reg_mem);
6121 %}
6122
6123 // Load Integer with mask 0xFFFF into Long Register
6124 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6125 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6126 effect(KILL cr);
6127
6128 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6129 "XOR $dst.hi,$dst.hi" %}
6130 ins_encode %{
6131 Register Rdst = $dst$$Register;
6132 __ movzwl(Rdst, $mem$$Address);
6133 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6134 %}
6135 ins_pipe(ialu_reg_mem);
6136 %}
6137
6138 // Load Integer with 32-bit mask into Long Register
6139 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6140 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6141 effect(KILL cr);
6142
6143 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6144 "XOR $dst.hi,$dst.hi\n\t"
6145 "AND $dst.lo,$mask" %}
6146 ins_encode %{
6147 Register Rdst = $dst$$Register;
6148 __ movl(Rdst, $mem$$Address);
6149 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6150 __ andl(Rdst, $mask$$constant);
6151 %}
6152 ins_pipe(ialu_reg_mem);
6153 %}
6154
6155 // Load Unsigned Integer into Long Register
6156 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6157 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6158 effect(KILL cr);
6159
6160 ins_cost(250);
6161 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6162 "XOR $dst.hi,$dst.hi" %}
6163
6164 ins_encode %{
6165 __ movl($dst$$Register, $mem$$Address);
6166 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6167 %}
6168
6169 ins_pipe(ialu_reg_mem);
6170 %}
6171
6172 // Load Long. Cannot clobber address while loading, so restrict address
6173 // register to ESI
6174 instruct loadL(eRegL dst, load_long_memory mem) %{
6175 predicate(!((LoadLNode*)n)->require_atomic_access());
6176 match(Set dst (LoadL mem));
6177
6178 ins_cost(250);
6179 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6180 "MOV $dst.hi,$mem+4" %}
6181
6182 ins_encode %{
6183 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6184 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6185 __ movl($dst$$Register, Amemlo);
6186 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6187 %}
6188
6189 ins_pipe(ialu_reg_long_mem);
6190 %}
6191
6192 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6193 // then store it down to the stack and reload on the int
6194 // side.
6195 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6196 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6197 match(Set dst (LoadL mem));
6198
6199 ins_cost(200);
6200 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6201 "FISTp $dst" %}
6202 ins_encode(enc_loadL_volatile(mem,dst));
6203 ins_pipe( fpu_reg_mem );
6204 %}
6205
6206 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6207 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6208 match(Set dst (LoadL mem));
6209 effect(TEMP tmp);
6210 ins_cost(180);
6211 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6212 "MOVSD $dst,$tmp" %}
6213 ins_encode %{
6214 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6215 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6216 %}
6217 ins_pipe( pipe_slow );
6218 %}
6219
6220 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6221 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6222 match(Set dst (LoadL mem));
6223 effect(TEMP tmp);
6224 ins_cost(160);
6225 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6226 "MOVD $dst.lo,$tmp\n\t"
6227 "PSRLQ $tmp,32\n\t"
6228 "MOVD $dst.hi,$tmp" %}
6229 ins_encode %{
6230 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6231 __ movdl($dst$$Register, $tmp$$XMMRegister);
6232 __ psrlq($tmp$$XMMRegister, 32);
6233 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6234 %}
6235 ins_pipe( pipe_slow );
6236 %}
6237
6238 // Load Range
6239 instruct loadRange(rRegI dst, memory mem) %{
6240 match(Set dst (LoadRange mem));
6241
6242 ins_cost(125);
6243 format %{ "MOV $dst,$mem" %}
6244 opcode(0x8B);
6245 ins_encode( OpcP, RegMem(dst,mem));
6246 ins_pipe( ialu_reg_mem );
6247 %}
6248
6249
6250 // Load Pointer
6251 instruct loadP(eRegP dst, memory mem) %{
6252 match(Set dst (LoadP mem));
6253
6254 ins_cost(125);
6255 format %{ "MOV $dst,$mem" %}
6256 opcode(0x8B);
6257 ins_encode( OpcP, RegMem(dst,mem));
6258 ins_pipe( ialu_reg_mem );
6259 %}
6260
6261 // Load Klass Pointer
6262 instruct loadKlass(eRegP dst, memory mem) %{
6263 match(Set dst (LoadKlass mem));
6264
6265 ins_cost(125);
6266 format %{ "MOV $dst,$mem" %}
6267 opcode(0x8B);
6268 ins_encode( OpcP, RegMem(dst,mem));
6269 ins_pipe( ialu_reg_mem );
6270 %}
6271
6272 // Load Double
6273 instruct loadDPR(regDPR dst, memory mem) %{
6274 predicate(UseSSE<=1);
6275 match(Set dst (LoadD mem));
6276
6277 ins_cost(150);
6278 format %{ "FLD_D ST,$mem\n\t"
6279 "FSTP $dst" %}
6280 opcode(0xDD); /* DD /0 */
6281 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6282 Pop_Reg_DPR(dst) );
6283 ins_pipe( fpu_reg_mem );
6284 %}
6285
6286 // Load Double to XMM
6287 instruct loadD(regD dst, memory mem) %{
6288 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6289 match(Set dst (LoadD mem));
6290 ins_cost(145);
6291 format %{ "MOVSD $dst,$mem" %}
6292 ins_encode %{
6293 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6294 %}
6295 ins_pipe( pipe_slow );
6296 %}
6297
6298 instruct loadD_partial(regD dst, memory mem) %{
6299 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6300 match(Set dst (LoadD mem));
6301 ins_cost(145);
6302 format %{ "MOVLPD $dst,$mem" %}
6303 ins_encode %{
6304 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6305 %}
6306 ins_pipe( pipe_slow );
6307 %}
6308
6309 // Load to XMM register (single-precision floating point)
6310 // MOVSS instruction
6311 instruct loadF(regF dst, memory mem) %{
6312 predicate(UseSSE>=1);
6313 match(Set dst (LoadF mem));
6314 ins_cost(145);
6315 format %{ "MOVSS $dst,$mem" %}
6316 ins_encode %{
6317 __ movflt ($dst$$XMMRegister, $mem$$Address);
6318 %}
6319 ins_pipe( pipe_slow );
6320 %}
6321
6322 // Load Float
6323 instruct loadFPR(regFPR dst, memory mem) %{
6324 predicate(UseSSE==0);
6325 match(Set dst (LoadF mem));
6326
6327 ins_cost(150);
6328 format %{ "FLD_S ST,$mem\n\t"
6329 "FSTP $dst" %}
6330 opcode(0xD9); /* D9 /0 */
6331 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6332 Pop_Reg_FPR(dst) );
6333 ins_pipe( fpu_reg_mem );
6334 %}
6335
6336 // Load Effective Address
6337 instruct leaP8(eRegP dst, indOffset8 mem) %{
6338 match(Set dst mem);
6339
6340 ins_cost(110);
6341 format %{ "LEA $dst,$mem" %}
6342 opcode(0x8D);
6343 ins_encode( OpcP, RegMem(dst,mem));
6344 ins_pipe( ialu_reg_reg_fat );
6345 %}
6346
6347 instruct leaP32(eRegP dst, indOffset32 mem) %{
6348 match(Set dst mem);
6349
6350 ins_cost(110);
6351 format %{ "LEA $dst,$mem" %}
6352 opcode(0x8D);
6353 ins_encode( OpcP, RegMem(dst,mem));
6354 ins_pipe( ialu_reg_reg_fat );
6355 %}
6356
6357 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6358 match(Set dst mem);
6359
6360 ins_cost(110);
6361 format %{ "LEA $dst,$mem" %}
6362 opcode(0x8D);
6363 ins_encode( OpcP, RegMem(dst,mem));
6364 ins_pipe( ialu_reg_reg_fat );
6365 %}
6366
6367 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6368 match(Set dst mem);
6369
6370 ins_cost(110);
6371 format %{ "LEA $dst,$mem" %}
6372 opcode(0x8D);
6373 ins_encode( OpcP, RegMem(dst,mem));
6374 ins_pipe( ialu_reg_reg_fat );
6375 %}
6376
6377 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6378 match(Set dst mem);
6379
6380 ins_cost(110);
6381 format %{ "LEA $dst,$mem" %}
6382 opcode(0x8D);
6383 ins_encode( OpcP, RegMem(dst,mem));
6384 ins_pipe( ialu_reg_reg_fat );
6385 %}
6386
6387 // Load Constant
6388 instruct loadConI(rRegI dst, immI src) %{
6389 match(Set dst src);
6390
6391 format %{ "MOV $dst,$src" %}
6392 ins_encode( LdImmI(dst, src) );
6393 ins_pipe( ialu_reg_fat );
6394 %}
6395
6396 // Load Constant zero
6397 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6398 match(Set dst src);
6399 effect(KILL cr);
6400
6401 ins_cost(50);
6402 format %{ "XOR $dst,$dst" %}
6403 opcode(0x33); /* + rd */
6404 ins_encode( OpcP, RegReg( dst, dst ) );
6405 ins_pipe( ialu_reg );
6406 %}
6407
6408 instruct loadConP(eRegP dst, immP src) %{
6409 match(Set dst src);
6410
6411 format %{ "MOV $dst,$src" %}
6412 opcode(0xB8); /* + rd */
6413 ins_encode( LdImmP(dst, src) );
6414 ins_pipe( ialu_reg_fat );
6415 %}
6416
6417 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6418 match(Set dst src);
6419 effect(KILL cr);
6420 ins_cost(200);
6421 format %{ "MOV $dst.lo,$src.lo\n\t"
6422 "MOV $dst.hi,$src.hi" %}
6423 opcode(0xB8);
6424 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6425 ins_pipe( ialu_reg_long_fat );
6426 %}
6427
6428 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6429 match(Set dst src);
6430 effect(KILL cr);
6431 ins_cost(150);
6432 format %{ "XOR $dst.lo,$dst.lo\n\t"
6433 "XOR $dst.hi,$dst.hi" %}
6434 opcode(0x33,0x33);
6435 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6436 ins_pipe( ialu_reg_long );
6437 %}
6438
6439 // The instruction usage is guarded by predicate in operand immFPR().
6440 instruct loadConFPR(regFPR dst, immFPR con) %{
6441 match(Set dst con);
6442 ins_cost(125);
6443 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6444 "FSTP $dst" %}
6445 ins_encode %{
6446 __ fld_s($constantaddress($con));
6447 __ fstp_d($dst$$reg);
6448 %}
6449 ins_pipe(fpu_reg_con);
6450 %}
6451
6452 // The instruction usage is guarded by predicate in operand immFPR0().
6453 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6454 match(Set dst con);
6455 ins_cost(125);
6456 format %{ "FLDZ ST\n\t"
6457 "FSTP $dst" %}
6458 ins_encode %{
6459 __ fldz();
6460 __ fstp_d($dst$$reg);
6461 %}
6462 ins_pipe(fpu_reg_con);
6463 %}
6464
6465 // The instruction usage is guarded by predicate in operand immFPR1().
6466 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6467 match(Set dst con);
6468 ins_cost(125);
6469 format %{ "FLD1 ST\n\t"
6470 "FSTP $dst" %}
6471 ins_encode %{
6472 __ fld1();
6473 __ fstp_d($dst$$reg);
6474 %}
6475 ins_pipe(fpu_reg_con);
6476 %}
6477
6478 // The instruction usage is guarded by predicate in operand immF().
6479 instruct loadConF(regF dst, immF con) %{
6480 match(Set dst con);
6481 ins_cost(125);
6482 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6483 ins_encode %{
6484 __ movflt($dst$$XMMRegister, $constantaddress($con));
6485 %}
6486 ins_pipe(pipe_slow);
6487 %}
6488
6489 // The instruction usage is guarded by predicate in operand immF0().
6490 instruct loadConF0(regF dst, immF0 src) %{
6491 match(Set dst src);
6492 ins_cost(100);
6493 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6494 ins_encode %{
6495 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6496 %}
6497 ins_pipe(pipe_slow);
6498 %}
6499
6500 // The instruction usage is guarded by predicate in operand immDPR().
6501 instruct loadConDPR(regDPR dst, immDPR con) %{
6502 match(Set dst con);
6503 ins_cost(125);
6504
6505 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6506 "FSTP $dst" %}
6507 ins_encode %{
6508 __ fld_d($constantaddress($con));
6509 __ fstp_d($dst$$reg);
6510 %}
6511 ins_pipe(fpu_reg_con);
6512 %}
6513
6514 // The instruction usage is guarded by predicate in operand immDPR0().
6515 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6516 match(Set dst con);
6517 ins_cost(125);
6518
6519 format %{ "FLDZ ST\n\t"
6520 "FSTP $dst" %}
6521 ins_encode %{
6522 __ fldz();
6523 __ fstp_d($dst$$reg);
6524 %}
6525 ins_pipe(fpu_reg_con);
6526 %}
6527
6528 // The instruction usage is guarded by predicate in operand immDPR1().
6529 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6530 match(Set dst con);
6531 ins_cost(125);
6532
6533 format %{ "FLD1 ST\n\t"
6534 "FSTP $dst" %}
6535 ins_encode %{
6536 __ fld1();
6537 __ fstp_d($dst$$reg);
6538 %}
6539 ins_pipe(fpu_reg_con);
6540 %}
6541
6542 // The instruction usage is guarded by predicate in operand immD().
6543 instruct loadConD(regD dst, immD con) %{
6544 match(Set dst con);
6545 ins_cost(125);
6546 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6547 ins_encode %{
6548 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6549 %}
6550 ins_pipe(pipe_slow);
6551 %}
6552
6553 // The instruction usage is guarded by predicate in operand immD0().
6554 instruct loadConD0(regD dst, immD0 src) %{
6555 match(Set dst src);
6556 ins_cost(100);
6557 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6558 ins_encode %{
6559 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6560 %}
6561 ins_pipe( pipe_slow );
6562 %}
6563
6564 // Load Stack Slot
6565 instruct loadSSI(rRegI dst, stackSlotI src) %{
6566 match(Set dst src);
6567 ins_cost(125);
6568
6569 format %{ "MOV $dst,$src" %}
6570 opcode(0x8B);
6571 ins_encode( OpcP, RegMem(dst,src));
6572 ins_pipe( ialu_reg_mem );
6573 %}
6574
6575 instruct loadSSL(eRegL dst, stackSlotL src) %{
6576 match(Set dst src);
6577
6578 ins_cost(200);
6579 format %{ "MOV $dst,$src.lo\n\t"
6580 "MOV $dst+4,$src.hi" %}
6581 opcode(0x8B, 0x8B);
6582 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6583 ins_pipe( ialu_mem_long_reg );
6584 %}
6585
6586 // Load Stack Slot
6587 instruct loadSSP(eRegP dst, stackSlotP src) %{
6588 match(Set dst src);
6589 ins_cost(125);
6590
6591 format %{ "MOV $dst,$src" %}
6592 opcode(0x8B);
6593 ins_encode( OpcP, RegMem(dst,src));
6594 ins_pipe( ialu_reg_mem );
6595 %}
6596
6597 // Load Stack Slot
6598 instruct loadSSF(regFPR dst, stackSlotF src) %{
6599 match(Set dst src);
6600 ins_cost(125);
6601
6602 format %{ "FLD_S $src\n\t"
6603 "FSTP $dst" %}
6604 opcode(0xD9); /* D9 /0, FLD m32real */
6605 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6606 Pop_Reg_FPR(dst) );
6607 ins_pipe( fpu_reg_mem );
6608 %}
6609
6610 // Load Stack Slot
6611 instruct loadSSD(regDPR dst, stackSlotD src) %{
6612 match(Set dst src);
6613 ins_cost(125);
6614
6615 format %{ "FLD_D $src\n\t"
6616 "FSTP $dst" %}
6617 opcode(0xDD); /* DD /0, FLD m64real */
6618 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6619 Pop_Reg_DPR(dst) );
6620 ins_pipe( fpu_reg_mem );
6621 %}
6622
6623 // Prefetch instructions.
6624 // Must be safe to execute with invalid address (cannot fault).
6625
6626 instruct prefetchr0( memory mem ) %{
6627 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6628 match(PrefetchRead mem);
6629 ins_cost(0);
6630 size(0);
6631 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6632 ins_encode();
6633 ins_pipe(empty);
6634 %}
6635
6636 instruct prefetchr( memory mem ) %{
6637 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6638 match(PrefetchRead mem);
6639 ins_cost(100);
6640
6641 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6642 ins_encode %{
6643 __ prefetchr($mem$$Address);
6644 %}
6645 ins_pipe(ialu_mem);
6646 %}
6647
6648 instruct prefetchrNTA( memory mem ) %{
6649 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6650 match(PrefetchRead mem);
6651 ins_cost(100);
6652
6653 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6654 ins_encode %{
6655 __ prefetchnta($mem$$Address);
6656 %}
6657 ins_pipe(ialu_mem);
6658 %}
6659
6660 instruct prefetchrT0( memory mem ) %{
6661 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6662 match(PrefetchRead mem);
6663 ins_cost(100);
6664
6665 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6666 ins_encode %{
6667 __ prefetcht0($mem$$Address);
6668 %}
6669 ins_pipe(ialu_mem);
6670 %}
6671
6672 instruct prefetchrT2( memory mem ) %{
6673 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6674 match(PrefetchRead mem);
6675 ins_cost(100);
6676
6677 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6678 ins_encode %{
6679 __ prefetcht2($mem$$Address);
6680 %}
6681 ins_pipe(ialu_mem);
6682 %}
6683
6684 instruct prefetchw0( memory mem ) %{
6685 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6686 match(PrefetchWrite mem);
6687 ins_cost(0);
6688 size(0);
6689 format %{ "Prefetch (non-SSE is empty encoding)" %}
6690 ins_encode();
6691 ins_pipe(empty);
6692 %}
6693
6694 instruct prefetchw( memory mem ) %{
6695 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6696 match( PrefetchWrite mem );
6697 ins_cost(100);
6698
6699 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6700 ins_encode %{
6701 __ prefetchw($mem$$Address);
6702 %}
6703 ins_pipe(ialu_mem);
6704 %}
6705
6706 instruct prefetchwNTA( memory mem ) %{
6707 predicate(UseSSE>=1);
6708 match(PrefetchWrite mem);
6709 ins_cost(100);
6710
6711 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6712 ins_encode %{
6713 __ prefetchnta($mem$$Address);
6714 %}
6715 ins_pipe(ialu_mem);
6716 %}
6717
6718 // Prefetch instructions for allocation.
6719
6720 instruct prefetchAlloc0( memory mem ) %{
6721 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6722 match(PrefetchAllocation mem);
6723 ins_cost(0);
6724 size(0);
6725 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6726 ins_encode();
6727 ins_pipe(empty);
6728 %}
6729
6730 instruct prefetchAlloc( memory mem ) %{
6731 predicate(AllocatePrefetchInstr==3);
6732 match( PrefetchAllocation mem );
6733 ins_cost(100);
6734
6735 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6736 ins_encode %{
6737 __ prefetchw($mem$$Address);
6738 %}
6739 ins_pipe(ialu_mem);
6740 %}
6741
6742 instruct prefetchAllocNTA( memory mem ) %{
6743 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6744 match(PrefetchAllocation mem);
6745 ins_cost(100);
6746
6747 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6748 ins_encode %{
6749 __ prefetchnta($mem$$Address);
6750 %}
6751 ins_pipe(ialu_mem);
6752 %}
6753
6754 instruct prefetchAllocT0( memory mem ) %{
6755 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6756 match(PrefetchAllocation mem);
6757 ins_cost(100);
6758
6759 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6760 ins_encode %{
6761 __ prefetcht0($mem$$Address);
6762 %}
6763 ins_pipe(ialu_mem);
6764 %}
6765
6766 instruct prefetchAllocT2( memory mem ) %{
6767 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6768 match(PrefetchAllocation mem);
6769 ins_cost(100);
6770
6771 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6772 ins_encode %{
6773 __ prefetcht2($mem$$Address);
6774 %}
6775 ins_pipe(ialu_mem);
6776 %}
6777
6778 //----------Store Instructions-------------------------------------------------
6779
6780 // Store Byte
6781 instruct storeB(memory mem, xRegI src) %{
6782 match(Set mem (StoreB mem src));
6783
6784 ins_cost(125);
6785 format %{ "MOV8 $mem,$src" %}
6786 opcode(0x88);
6787 ins_encode( OpcP, RegMem( src, mem ) );
6788 ins_pipe( ialu_mem_reg );
6789 %}
6790
6791 // Store Char/Short
6792 instruct storeC(memory mem, rRegI src) %{
6793 match(Set mem (StoreC mem src));
6794
6795 ins_cost(125);
6796 format %{ "MOV16 $mem,$src" %}
6797 opcode(0x89, 0x66);
6798 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6799 ins_pipe( ialu_mem_reg );
6800 %}
6801
6802 // Store Integer
6803 instruct storeI(memory mem, rRegI src) %{
6804 match(Set mem (StoreI mem src));
6805
6806 ins_cost(125);
6807 format %{ "MOV $mem,$src" %}
6808 opcode(0x89);
6809 ins_encode( OpcP, RegMem( src, mem ) );
6810 ins_pipe( ialu_mem_reg );
6811 %}
6812
6813 // Store Long
6814 instruct storeL(long_memory mem, eRegL src) %{
6815 predicate(!((StoreLNode*)n)->require_atomic_access());
6816 match(Set mem (StoreL mem src));
6817
6818 ins_cost(200);
6819 format %{ "MOV $mem,$src.lo\n\t"
6820 "MOV $mem+4,$src.hi" %}
6821 opcode(0x89, 0x89);
6822 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6823 ins_pipe( ialu_mem_long_reg );
6824 %}
6825
6826 // Store Long to Integer
6827 instruct storeL2I(memory mem, eRegL src) %{
6828 match(Set mem (StoreI mem (ConvL2I src)));
6829
6830 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6831 ins_encode %{
6832 __ movl($mem$$Address, $src$$Register);
6833 %}
6834 ins_pipe(ialu_mem_reg);
6835 %}
6836
6837 // Volatile Store Long. Must be atomic, so move it into
6838 // the FP TOS and then do a 64-bit FIST. Has to probe the
6839 // target address before the store (for null-ptr checks)
6840 // so the memory operand is used twice in the encoding.
6841 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6842 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6843 match(Set mem (StoreL mem src));
6844 effect( KILL cr );
6845 ins_cost(400);
6846 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6847 "FILD $src\n\t"
6848 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6849 opcode(0x3B);
6850 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6851 ins_pipe( fpu_reg_mem );
6852 %}
6853
6854 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6855 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6856 match(Set mem (StoreL mem src));
6857 effect( TEMP tmp, KILL cr );
6858 ins_cost(380);
6859 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6860 "MOVSD $tmp,$src\n\t"
6861 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6862 ins_encode %{
6863 __ cmpl(rax, $mem$$Address);
6864 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6865 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6866 %}
6867 ins_pipe( pipe_slow );
6868 %}
6869
6870 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6871 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6872 match(Set mem (StoreL mem src));
6873 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6874 ins_cost(360);
6875 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6876 "MOVD $tmp,$src.lo\n\t"
6877 "MOVD $tmp2,$src.hi\n\t"
6878 "PUNPCKLDQ $tmp,$tmp2\n\t"
6879 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6880 ins_encode %{
6881 __ cmpl(rax, $mem$$Address);
6882 __ movdl($tmp$$XMMRegister, $src$$Register);
6883 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6884 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6885 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6886 %}
6887 ins_pipe( pipe_slow );
6888 %}
6889
6890 // Store Pointer; for storing unknown oops and raw pointers
6891 instruct storeP(memory mem, anyRegP src) %{
6892 match(Set mem (StoreP mem src));
6893
6894 ins_cost(125);
6895 format %{ "MOV $mem,$src" %}
6896 opcode(0x89);
6897 ins_encode( OpcP, RegMem( src, mem ) );
6898 ins_pipe( ialu_mem_reg );
6899 %}
6900
6901 // Store Integer Immediate
6902 instruct storeImmI(memory mem, immI src) %{
6903 match(Set mem (StoreI mem src));
6904
6905 ins_cost(150);
6906 format %{ "MOV $mem,$src" %}
6907 opcode(0xC7); /* C7 /0 */
6908 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6909 ins_pipe( ialu_mem_imm );
6910 %}
6911
6912 // Store Short/Char Immediate
6913 instruct storeImmI16(memory mem, immI16 src) %{
6914 predicate(UseStoreImmI16);
6915 match(Set mem (StoreC mem src));
6916
6917 ins_cost(150);
6918 format %{ "MOV16 $mem,$src" %}
6919 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6920 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6921 ins_pipe( ialu_mem_imm );
6922 %}
6923
6924 // Store Pointer Immediate; null pointers or constant oops that do not
6925 // need card-mark barriers.
6926 instruct storeImmP(memory mem, immP src) %{
6927 match(Set mem (StoreP mem src));
6928
6929 ins_cost(150);
6930 format %{ "MOV $mem,$src" %}
6931 opcode(0xC7); /* C7 /0 */
6932 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6933 ins_pipe( ialu_mem_imm );
6934 %}
6935
6936 // Store Byte Immediate
6937 instruct storeImmB(memory mem, immI8 src) %{
6938 match(Set mem (StoreB mem src));
6939
6940 ins_cost(150);
6941 format %{ "MOV8 $mem,$src" %}
6942 opcode(0xC6); /* C6 /0 */
6943 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6944 ins_pipe( ialu_mem_imm );
6945 %}
6946
6947 // Store CMS card-mark Immediate
6948 instruct storeImmCM(memory mem, immI8 src) %{
6949 match(Set mem (StoreCM mem src));
6950
6951 ins_cost(150);
6952 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6953 opcode(0xC6); /* C6 /0 */
6954 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6955 ins_pipe( ialu_mem_imm );
6956 %}
6957
6958 // Store Double
6959 instruct storeDPR( memory mem, regDPR1 src) %{
6960 predicate(UseSSE<=1);
6961 match(Set mem (StoreD mem src));
6962
6963 ins_cost(100);
6964 format %{ "FST_D $mem,$src" %}
6965 opcode(0xDD); /* DD /2 */
6966 ins_encode( enc_FPR_store(mem,src) );
6967 ins_pipe( fpu_mem_reg );
6968 %}
6969
6970 // Store double does rounding on x86
6971 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6972 predicate(UseSSE<=1);
6973 match(Set mem (StoreD mem (RoundDouble src)));
6974
6975 ins_cost(100);
6976 format %{ "FST_D $mem,$src\t# round" %}
6977 opcode(0xDD); /* DD /2 */
6978 ins_encode( enc_FPR_store(mem,src) );
6979 ins_pipe( fpu_mem_reg );
6980 %}
6981
6982 // Store XMM register to memory (double-precision floating points)
6983 // MOVSD instruction
6984 instruct storeD(memory mem, regD src) %{
6985 predicate(UseSSE>=2);
6986 match(Set mem (StoreD mem src));
6987 ins_cost(95);
6988 format %{ "MOVSD $mem,$src" %}
6989 ins_encode %{
6990 __ movdbl($mem$$Address, $src$$XMMRegister);
6991 %}
6992 ins_pipe( pipe_slow );
6993 %}
6994
6995 // Store XMM register to memory (single-precision floating point)
6996 // MOVSS instruction
6997 instruct storeF(memory mem, regF src) %{
6998 predicate(UseSSE>=1);
6999 match(Set mem (StoreF mem src));
7000 ins_cost(95);
7001 format %{ "MOVSS $mem,$src" %}
7002 ins_encode %{
7003 __ movflt($mem$$Address, $src$$XMMRegister);
7004 %}
7005 ins_pipe( pipe_slow );
7006 %}
7007
7008 // Store Float
7009 instruct storeFPR( memory mem, regFPR1 src) %{
7010 predicate(UseSSE==0);
7011 match(Set mem (StoreF mem src));
7012
7013 ins_cost(100);
7014 format %{ "FST_S $mem,$src" %}
7015 opcode(0xD9); /* D9 /2 */
7016 ins_encode( enc_FPR_store(mem,src) );
7017 ins_pipe( fpu_mem_reg );
7018 %}
7019
7020 // Store Float does rounding on x86
7021 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7022 predicate(UseSSE==0);
7023 match(Set mem (StoreF mem (RoundFloat src)));
7024
7025 ins_cost(100);
7026 format %{ "FST_S $mem,$src\t# round" %}
7027 opcode(0xD9); /* D9 /2 */
7028 ins_encode( enc_FPR_store(mem,src) );
7029 ins_pipe( fpu_mem_reg );
7030 %}
7031
7032 // Store Float does rounding on x86
7033 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7034 predicate(UseSSE<=1);
7035 match(Set mem (StoreF mem (ConvD2F src)));
7036
7037 ins_cost(100);
7038 format %{ "FST_S $mem,$src\t# D-round" %}
7039 opcode(0xD9); /* D9 /2 */
7040 ins_encode( enc_FPR_store(mem,src) );
7041 ins_pipe( fpu_mem_reg );
7042 %}
7043
7044 // Store immediate Float value (it is faster than store from FPU register)
7045 // The instruction usage is guarded by predicate in operand immFPR().
7046 instruct storeFPR_imm( memory mem, immFPR src) %{
7047 match(Set mem (StoreF mem src));
7048
7049 ins_cost(50);
7050 format %{ "MOV $mem,$src\t# store float" %}
7051 opcode(0xC7); /* C7 /0 */
7052 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7053 ins_pipe( ialu_mem_imm );
7054 %}
7055
7056 // Store immediate Float value (it is faster than store from XMM register)
7057 // The instruction usage is guarded by predicate in operand immF().
7058 instruct storeF_imm( memory mem, immF src) %{
7059 match(Set mem (StoreF mem src));
7060
7061 ins_cost(50);
7062 format %{ "MOV $mem,$src\t# store float" %}
7063 opcode(0xC7); /* C7 /0 */
7064 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7065 ins_pipe( ialu_mem_imm );
7066 %}
7067
7068 // Store Integer to stack slot
7069 instruct storeSSI(stackSlotI dst, rRegI src) %{
7070 match(Set dst src);
7071
7072 ins_cost(100);
7073 format %{ "MOV $dst,$src" %}
7074 opcode(0x89);
7075 ins_encode( OpcPRegSS( dst, src ) );
7076 ins_pipe( ialu_mem_reg );
7077 %}
7078
7079 // Store Integer to stack slot
7080 instruct storeSSP(stackSlotP dst, eRegP src) %{
7081 match(Set dst src);
7082
7083 ins_cost(100);
7084 format %{ "MOV $dst,$src" %}
7085 opcode(0x89);
7086 ins_encode( OpcPRegSS( dst, src ) );
7087 ins_pipe( ialu_mem_reg );
7088 %}
7089
7090 // Store Long to stack slot
7091 instruct storeSSL(stackSlotL dst, eRegL src) %{
7092 match(Set dst src);
7093
7094 ins_cost(200);
7095 format %{ "MOV $dst,$src.lo\n\t"
7096 "MOV $dst+4,$src.hi" %}
7097 opcode(0x89, 0x89);
7098 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7099 ins_pipe( ialu_mem_long_reg );
7100 %}
7101
7102 //----------MemBar Instructions-----------------------------------------------
7103 // Memory barrier flavors
7104
7105 instruct membar_acquire() %{
7106 match(MemBarAcquire);
7107 ins_cost(400);
7108
7109 size(0);
7110 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7111 ins_encode();
7112 ins_pipe(empty);
7113 %}
7114
7115 instruct membar_acquire_lock() %{
7116 match(MemBarAcquireLock);
7117 ins_cost(0);
7118
7119 size(0);
7120 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7121 ins_encode( );
7122 ins_pipe(empty);
7123 %}
7124
7125 instruct membar_release() %{
7126 match(MemBarRelease);
7127 ins_cost(400);
7128
7129 size(0);
7130 format %{ "MEMBAR-release ! (empty encoding)" %}
7131 ins_encode( );
7132 ins_pipe(empty);
7133 %}
7134
7135 instruct membar_release_lock() %{
7136 match(MemBarReleaseLock);
7137 ins_cost(0);
7138
7139 size(0);
7140 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7141 ins_encode( );
7142 ins_pipe(empty);
7143 %}
7144
7145 instruct membar_volatile(eFlagsReg cr) %{
7146 match(MemBarVolatile);
7147 effect(KILL cr);
7148 ins_cost(400);
7149
7150 format %{
7151 $$template
7152 if (os::is_MP()) {
7153 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7154 } else {
7155 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7156 }
7157 %}
7158 ins_encode %{
7159 __ membar(Assembler::StoreLoad);
7160 %}
7161 ins_pipe(pipe_slow);
7162 %}
7163
7164 instruct unnecessary_membar_volatile() %{
7165 match(MemBarVolatile);
7166 predicate(Matcher::post_store_load_barrier(n));
7167 ins_cost(0);
7168
7169 size(0);
7170 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7171 ins_encode( );
7172 ins_pipe(empty);
7173 %}
7174
7175 instruct membar_storestore() %{
7176 match(MemBarStoreStore);
7177 ins_cost(0);
7178
7179 size(0);
7180 format %{ "MEMBAR-storestore (empty encoding)" %}
7181 ins_encode( );
7182 ins_pipe(empty);
7183 %}
7184
7185 //----------Move Instructions--------------------------------------------------
7186 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7187 match(Set dst (CastX2P src));
7188 format %{ "# X2P $dst, $src" %}
7189 ins_encode( /*empty encoding*/ );
7190 ins_cost(0);
7191 ins_pipe(empty);
7192 %}
7193
7194 instruct castP2X(rRegI dst, eRegP src ) %{
7195 match(Set dst (CastP2X src));
7196 ins_cost(50);
7197 format %{ "MOV $dst, $src\t# CastP2X" %}
7198 ins_encode( enc_Copy( dst, src) );
7199 ins_pipe( ialu_reg_reg );
7200 %}
7201
7202 //----------Conditional Move---------------------------------------------------
7203 // Conditional move
7204 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7205 predicate(!VM_Version::supports_cmov() );
7206 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7207 ins_cost(200);
7208 format %{ "J$cop,us skip\t# signed cmove\n\t"
7209 "MOV $dst,$src\n"
7210 "skip:" %}
7211 ins_encode %{
7212 Label Lskip;
7213 // Invert sense of branch from sense of CMOV
7214 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7215 __ movl($dst$$Register, $src$$Register);
7216 __ bind(Lskip);
7217 %}
7218 ins_pipe( pipe_cmov_reg );
7219 %}
7220
7221 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7222 predicate(!VM_Version::supports_cmov() );
7223 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7224 ins_cost(200);
7225 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7226 "MOV $dst,$src\n"
7227 "skip:" %}
7228 ins_encode %{
7229 Label Lskip;
7230 // Invert sense of branch from sense of CMOV
7231 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7232 __ movl($dst$$Register, $src$$Register);
7233 __ bind(Lskip);
7234 %}
7235 ins_pipe( pipe_cmov_reg );
7236 %}
7237
7238 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7239 predicate(VM_Version::supports_cmov() );
7240 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7241 ins_cost(200);
7242 format %{ "CMOV$cop $dst,$src" %}
7243 opcode(0x0F,0x40);
7244 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7245 ins_pipe( pipe_cmov_reg );
7246 %}
7247
7248 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7249 predicate(VM_Version::supports_cmov() );
7250 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7251 ins_cost(200);
7252 format %{ "CMOV$cop $dst,$src" %}
7253 opcode(0x0F,0x40);
7254 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7255 ins_pipe( pipe_cmov_reg );
7256 %}
7257
7258 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7259 predicate(VM_Version::supports_cmov() );
7260 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7261 ins_cost(200);
7262 expand %{
7263 cmovI_regU(cop, cr, dst, src);
7264 %}
7265 %}
7266
7267 // Conditional move
7268 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7269 predicate(VM_Version::supports_cmov() );
7270 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7271 ins_cost(250);
7272 format %{ "CMOV$cop $dst,$src" %}
7273 opcode(0x0F,0x40);
7274 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7275 ins_pipe( pipe_cmov_mem );
7276 %}
7277
7278 // Conditional move
7279 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7280 predicate(VM_Version::supports_cmov() );
7281 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7282 ins_cost(250);
7283 format %{ "CMOV$cop $dst,$src" %}
7284 opcode(0x0F,0x40);
7285 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7286 ins_pipe( pipe_cmov_mem );
7287 %}
7288
7289 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7290 predicate(VM_Version::supports_cmov() );
7291 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7292 ins_cost(250);
7293 expand %{
7294 cmovI_memU(cop, cr, dst, src);
7295 %}
7296 %}
7297
7298 // Conditional move
7299 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7300 predicate(VM_Version::supports_cmov() );
7301 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7302 ins_cost(200);
7303 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7304 opcode(0x0F,0x40);
7305 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7306 ins_pipe( pipe_cmov_reg );
7307 %}
7308
7309 // Conditional move (non-P6 version)
7310 // Note: a CMoveP is generated for stubs and native wrappers
7311 // regardless of whether we are on a P6, so we
7312 // emulate a cmov here
7313 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7314 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7315 ins_cost(300);
7316 format %{ "Jn$cop skip\n\t"
7317 "MOV $dst,$src\t# pointer\n"
7318 "skip:" %}
7319 opcode(0x8b);
7320 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7321 ins_pipe( pipe_cmov_reg );
7322 %}
7323
7324 // Conditional move
7325 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7326 predicate(VM_Version::supports_cmov() );
7327 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7328 ins_cost(200);
7329 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7330 opcode(0x0F,0x40);
7331 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7332 ins_pipe( pipe_cmov_reg );
7333 %}
7334
7335 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7336 predicate(VM_Version::supports_cmov() );
7337 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7338 ins_cost(200);
7339 expand %{
7340 cmovP_regU(cop, cr, dst, src);
7341 %}
7342 %}
7343
7344 // DISABLED: Requires the ADLC to emit a bottom_type call that
7345 // correctly meets the two pointer arguments; one is an incoming
7346 // register but the other is a memory operand. ALSO appears to
7347 // be buggy with implicit null checks.
7348 //
7349 //// Conditional move
7350 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7351 // predicate(VM_Version::supports_cmov() );
7352 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7353 // ins_cost(250);
7354 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7355 // opcode(0x0F,0x40);
7356 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7357 // ins_pipe( pipe_cmov_mem );
7358 //%}
7359 //
7360 //// Conditional move
7361 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7362 // predicate(VM_Version::supports_cmov() );
7363 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7364 // ins_cost(250);
7365 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7366 // opcode(0x0F,0x40);
7367 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7368 // ins_pipe( pipe_cmov_mem );
7369 //%}
7370
7371 // Conditional move
7372 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7373 predicate(UseSSE<=1);
7374 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7375 ins_cost(200);
7376 format %{ "FCMOV$cop $dst,$src\t# double" %}
7377 opcode(0xDA);
7378 ins_encode( enc_cmov_dpr(cop,src) );
7379 ins_pipe( pipe_cmovDPR_reg );
7380 %}
7381
7382 // Conditional move
7383 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7384 predicate(UseSSE==0);
7385 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7386 ins_cost(200);
7387 format %{ "FCMOV$cop $dst,$src\t# float" %}
7388 opcode(0xDA);
7389 ins_encode( enc_cmov_dpr(cop,src) );
7390 ins_pipe( pipe_cmovDPR_reg );
7391 %}
7392
7393 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7394 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7395 predicate(UseSSE<=1);
7396 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7397 ins_cost(200);
7398 format %{ "Jn$cop skip\n\t"
7399 "MOV $dst,$src\t# double\n"
7400 "skip:" %}
7401 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7402 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7403 ins_pipe( pipe_cmovDPR_reg );
7404 %}
7405
7406 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7407 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7408 predicate(UseSSE==0);
7409 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7410 ins_cost(200);
7411 format %{ "Jn$cop skip\n\t"
7412 "MOV $dst,$src\t# float\n"
7413 "skip:" %}
7414 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7415 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7416 ins_pipe( pipe_cmovDPR_reg );
7417 %}
7418
7419 // No CMOVE with SSE/SSE2
7420 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7421 predicate (UseSSE>=1);
7422 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7423 ins_cost(200);
7424 format %{ "Jn$cop skip\n\t"
7425 "MOVSS $dst,$src\t# float\n"
7426 "skip:" %}
7427 ins_encode %{
7428 Label skip;
7429 // Invert sense of branch from sense of CMOV
7430 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7431 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7432 __ bind(skip);
7433 %}
7434 ins_pipe( pipe_slow );
7435 %}
7436
7437 // No CMOVE with SSE/SSE2
7438 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7439 predicate (UseSSE>=2);
7440 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7441 ins_cost(200);
7442 format %{ "Jn$cop skip\n\t"
7443 "MOVSD $dst,$src\t# float\n"
7444 "skip:" %}
7445 ins_encode %{
7446 Label skip;
7447 // Invert sense of branch from sense of CMOV
7448 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7449 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7450 __ bind(skip);
7451 %}
7452 ins_pipe( pipe_slow );
7453 %}
7454
7455 // unsigned version
7456 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7457 predicate (UseSSE>=1);
7458 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7459 ins_cost(200);
7460 format %{ "Jn$cop skip\n\t"
7461 "MOVSS $dst,$src\t# float\n"
7462 "skip:" %}
7463 ins_encode %{
7464 Label skip;
7465 // Invert sense of branch from sense of CMOV
7466 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7467 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7468 __ bind(skip);
7469 %}
7470 ins_pipe( pipe_slow );
7471 %}
7472
7473 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7474 predicate (UseSSE>=1);
7475 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7476 ins_cost(200);
7477 expand %{
7478 fcmovF_regU(cop, cr, dst, src);
7479 %}
7480 %}
7481
7482 // unsigned version
7483 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7484 predicate (UseSSE>=2);
7485 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7486 ins_cost(200);
7487 format %{ "Jn$cop skip\n\t"
7488 "MOVSD $dst,$src\t# float\n"
7489 "skip:" %}
7490 ins_encode %{
7491 Label skip;
7492 // Invert sense of branch from sense of CMOV
7493 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7494 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7495 __ bind(skip);
7496 %}
7497 ins_pipe( pipe_slow );
7498 %}
7499
7500 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7501 predicate (UseSSE>=2);
7502 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7503 ins_cost(200);
7504 expand %{
7505 fcmovD_regU(cop, cr, dst, src);
7506 %}
7507 %}
7508
7509 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7510 predicate(VM_Version::supports_cmov() );
7511 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7512 ins_cost(200);
7513 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7514 "CMOV$cop $dst.hi,$src.hi" %}
7515 opcode(0x0F,0x40);
7516 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7517 ins_pipe( pipe_cmov_reg_long );
7518 %}
7519
7520 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7521 predicate(VM_Version::supports_cmov() );
7522 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7523 ins_cost(200);
7524 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7525 "CMOV$cop $dst.hi,$src.hi" %}
7526 opcode(0x0F,0x40);
7527 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7528 ins_pipe( pipe_cmov_reg_long );
7529 %}
7530
7531 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7532 predicate(VM_Version::supports_cmov() );
7533 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7534 ins_cost(200);
7535 expand %{
7536 cmovL_regU(cop, cr, dst, src);
7537 %}
7538 %}
7539
7540 //----------Arithmetic Instructions--------------------------------------------
7541 //----------Addition Instructions----------------------------------------------
7542 // Integer Addition Instructions
7543 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7544 match(Set dst (AddI dst src));
7545 effect(KILL cr);
7546
7547 size(2);
7548 format %{ "ADD $dst,$src" %}
7549 opcode(0x03);
7550 ins_encode( OpcP, RegReg( dst, src) );
7551 ins_pipe( ialu_reg_reg );
7552 %}
7553
7554 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7555 match(Set dst (AddI dst src));
7556 effect(KILL cr);
7557
7558 format %{ "ADD $dst,$src" %}
7559 opcode(0x81, 0x00); /* /0 id */
7560 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7561 ins_pipe( ialu_reg );
7562 %}
7563
7564 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7565 predicate(UseIncDec);
7566 match(Set dst (AddI dst src));
7567 effect(KILL cr);
7568
7569 size(1);
7570 format %{ "INC $dst" %}
7571 opcode(0x40); /* */
7572 ins_encode( Opc_plus( primary, dst ) );
7573 ins_pipe( ialu_reg );
7574 %}
7575
7576 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7577 match(Set dst (AddI src0 src1));
7578 ins_cost(110);
7579
7580 format %{ "LEA $dst,[$src0 + $src1]" %}
7581 opcode(0x8D); /* 0x8D /r */
7582 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7583 ins_pipe( ialu_reg_reg );
7584 %}
7585
7586 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7587 match(Set dst (AddP src0 src1));
7588 ins_cost(110);
7589
7590 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7591 opcode(0x8D); /* 0x8D /r */
7592 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7593 ins_pipe( ialu_reg_reg );
7594 %}
7595
7596 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7597 predicate(UseIncDec);
7598 match(Set dst (AddI dst src));
7599 effect(KILL cr);
7600
7601 size(1);
7602 format %{ "DEC $dst" %}
7603 opcode(0x48); /* */
7604 ins_encode( Opc_plus( primary, dst ) );
7605 ins_pipe( ialu_reg );
7606 %}
7607
7608 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7609 match(Set dst (AddP dst src));
7610 effect(KILL cr);
7611
7612 size(2);
7613 format %{ "ADD $dst,$src" %}
7614 opcode(0x03);
7615 ins_encode( OpcP, RegReg( dst, src) );
7616 ins_pipe( ialu_reg_reg );
7617 %}
7618
7619 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7620 match(Set dst (AddP dst src));
7621 effect(KILL cr);
7622
7623 format %{ "ADD $dst,$src" %}
7624 opcode(0x81,0x00); /* Opcode 81 /0 id */
7625 // ins_encode( RegImm( dst, src) );
7626 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7627 ins_pipe( ialu_reg );
7628 %}
7629
7630 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7631 match(Set dst (AddI dst (LoadI src)));
7632 effect(KILL cr);
7633
7634 ins_cost(125);
7635 format %{ "ADD $dst,$src" %}
7636 opcode(0x03);
7637 ins_encode( OpcP, RegMem( dst, src) );
7638 ins_pipe( ialu_reg_mem );
7639 %}
7640
7641 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7642 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7643 effect(KILL cr);
7644
7645 ins_cost(150);
7646 format %{ "ADD $dst,$src" %}
7647 opcode(0x01); /* Opcode 01 /r */
7648 ins_encode( OpcP, RegMem( src, dst ) );
7649 ins_pipe( ialu_mem_reg );
7650 %}
7651
7652 // Add Memory with Immediate
7653 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7654 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7655 effect(KILL cr);
7656
7657 ins_cost(125);
7658 format %{ "ADD $dst,$src" %}
7659 opcode(0x81); /* Opcode 81 /0 id */
7660 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7661 ins_pipe( ialu_mem_imm );
7662 %}
7663
7664 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7665 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7666 effect(KILL cr);
7667
7668 ins_cost(125);
7669 format %{ "INC $dst" %}
7670 opcode(0xFF); /* Opcode FF /0 */
7671 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7672 ins_pipe( ialu_mem_imm );
7673 %}
7674
7675 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7676 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7677 effect(KILL cr);
7678
7679 ins_cost(125);
7680 format %{ "DEC $dst" %}
7681 opcode(0xFF); /* Opcode FF /1 */
7682 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7683 ins_pipe( ialu_mem_imm );
7684 %}
7685
7686
7687 instruct checkCastPP( eRegP dst ) %{
7688 match(Set dst (CheckCastPP dst));
7689
7690 size(0);
7691 format %{ "#checkcastPP of $dst" %}
7692 ins_encode( /*empty encoding*/ );
7693 ins_pipe( empty );
7694 %}
7695
7696 instruct castPP( eRegP dst ) %{
7697 match(Set dst (CastPP dst));
7698 format %{ "#castPP of $dst" %}
7699 ins_encode( /*empty encoding*/ );
7700 ins_pipe( empty );
7701 %}
7702
7703 instruct castII( rRegI dst ) %{
7704 match(Set dst (CastII dst));
7705 format %{ "#castII of $dst" %}
7706 ins_encode( /*empty encoding*/ );
7707 ins_cost(0);
7708 ins_pipe( empty );
7709 %}
7710
7711
7712 // Load-locked - same as a regular pointer load when used with compare-swap
7713 instruct loadPLocked(eRegP dst, memory mem) %{
7714 match(Set dst (LoadPLocked mem));
7715
7716 ins_cost(125);
7717 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7718 opcode(0x8B);
7719 ins_encode( OpcP, RegMem(dst,mem));
7720 ins_pipe( ialu_reg_mem );
7721 %}
7722
7723 // Conditional-store of the updated heap-top.
7724 // Used during allocation of the shared heap.
7725 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7726 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7727 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7728 // EAX is killed if there is contention, but then it's also unused.
7729 // In the common case of no contention, EAX holds the new oop address.
7730 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7731 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7732 ins_pipe( pipe_cmpxchg );
7733 %}
7734
7735 // Conditional-store of an int value.
7736 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7737 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7738 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7739 effect(KILL oldval);
7740 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7741 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7742 ins_pipe( pipe_cmpxchg );
7743 %}
7744
7745 // Conditional-store of a long value.
7746 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7747 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7748 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7749 effect(KILL oldval);
7750 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7751 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7752 "XCHG EBX,ECX"
7753 %}
7754 ins_encode %{
7755 // Note: we need to swap rbx, and rcx before and after the
7756 // cmpxchg8 instruction because the instruction uses
7757 // rcx as the high order word of the new value to store but
7758 // our register encoding uses rbx.
7759 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7760 if( os::is_MP() )
7761 __ lock();
7762 __ cmpxchg8($mem$$Address);
7763 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7764 %}
7765 ins_pipe( pipe_cmpxchg );
7766 %}
7767
7768 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7769
7770 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7771 predicate(VM_Version::supports_cx8());
7772 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7773 effect(KILL cr, KILL oldval);
7774 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7775 "MOV $res,0\n\t"
7776 "JNE,s fail\n\t"
7777 "MOV $res,1\n"
7778 "fail:" %}
7779 ins_encode( enc_cmpxchg8(mem_ptr),
7780 enc_flags_ne_to_boolean(res) );
7781 ins_pipe( pipe_cmpxchg );
7782 %}
7783
7784 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7785 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7786 effect(KILL cr, KILL oldval);
7787 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7788 "MOV $res,0\n\t"
7789 "JNE,s fail\n\t"
7790 "MOV $res,1\n"
7791 "fail:" %}
7792 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7793 ins_pipe( pipe_cmpxchg );
7794 %}
7795
7796 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7797 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7798 effect(KILL cr, KILL oldval);
7799 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7800 "MOV $res,0\n\t"
7801 "JNE,s fail\n\t"
7802 "MOV $res,1\n"
7803 "fail:" %}
7804 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7805 ins_pipe( pipe_cmpxchg );
7806 %}
7807
7808 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7809 predicate(n->as_LoadStore()->result_not_used());
7810 match(Set dummy (GetAndAddI mem add));
7811 effect(KILL cr);
7812 format %{ "ADDL [$mem],$add" %}
7813 ins_encode %{
7814 if (os::is_MP()) { __ lock(); }
7815 __ addl($mem$$Address, $add$$constant);
7816 %}
7817 ins_pipe( pipe_cmpxchg );
7818 %}
7819
7820 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7821 match(Set newval (GetAndAddI mem newval));
7822 effect(KILL cr);
7823 format %{ "XADDL [$mem],$newval" %}
7824 ins_encode %{
7825 if (os::is_MP()) { __ lock(); }
7826 __ xaddl($mem$$Address, $newval$$Register);
7827 %}
7828 ins_pipe( pipe_cmpxchg );
7829 %}
7830
7831 instruct xchgI( memory mem, rRegI newval) %{
7832 match(Set newval (GetAndSetI mem newval));
7833 format %{ "XCHGL $newval,[$mem]" %}
7834 ins_encode %{
7835 __ xchgl($newval$$Register, $mem$$Address);
7836 %}
7837 ins_pipe( pipe_cmpxchg );
7838 %}
7839
7840 instruct xchgP( memory mem, pRegP newval) %{
7841 match(Set newval (GetAndSetP mem newval));
7842 format %{ "XCHGL $newval,[$mem]" %}
7843 ins_encode %{
7844 __ xchgl($newval$$Register, $mem$$Address);
7845 %}
7846 ins_pipe( pipe_cmpxchg );
7847 %}
7848
7849 //----------Subtraction Instructions-------------------------------------------
7850 // Integer Subtraction Instructions
7851 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7852 match(Set dst (SubI dst src));
7853 effect(KILL cr);
7854
7855 size(2);
7856 format %{ "SUB $dst,$src" %}
7857 opcode(0x2B);
7858 ins_encode( OpcP, RegReg( dst, src) );
7859 ins_pipe( ialu_reg_reg );
7860 %}
7861
7862 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7863 match(Set dst (SubI dst src));
7864 effect(KILL cr);
7865
7866 format %{ "SUB $dst,$src" %}
7867 opcode(0x81,0x05); /* Opcode 81 /5 */
7868 // ins_encode( RegImm( dst, src) );
7869 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7870 ins_pipe( ialu_reg );
7871 %}
7872
7873 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7874 match(Set dst (SubI dst (LoadI src)));
7875 effect(KILL cr);
7876
7877 ins_cost(125);
7878 format %{ "SUB $dst,$src" %}
7879 opcode(0x2B);
7880 ins_encode( OpcP, RegMem( dst, src) );
7881 ins_pipe( ialu_reg_mem );
7882 %}
7883
7884 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7885 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7886 effect(KILL cr);
7887
7888 ins_cost(150);
7889 format %{ "SUB $dst,$src" %}
7890 opcode(0x29); /* Opcode 29 /r */
7891 ins_encode( OpcP, RegMem( src, dst ) );
7892 ins_pipe( ialu_mem_reg );
7893 %}
7894
7895 // Subtract from a pointer
7896 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7897 match(Set dst (AddP dst (SubI zero src)));
7898 effect(KILL cr);
7899
7900 size(2);
7901 format %{ "SUB $dst,$src" %}
7902 opcode(0x2B);
7903 ins_encode( OpcP, RegReg( dst, src) );
7904 ins_pipe( ialu_reg_reg );
7905 %}
7906
7907 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7908 match(Set dst (SubI zero dst));
7909 effect(KILL cr);
7910
7911 size(2);
7912 format %{ "NEG $dst" %}
7913 opcode(0xF7,0x03); // Opcode F7 /3
7914 ins_encode( OpcP, RegOpc( dst ) );
7915 ins_pipe( ialu_reg );
7916 %}
7917
7918
7919 //----------Multiplication/Division Instructions-------------------------------
7920 // Integer Multiplication Instructions
7921 // Multiply Register
7922 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7923 match(Set dst (MulI dst src));
7924 effect(KILL cr);
7925
7926 size(3);
7927 ins_cost(300);
7928 format %{ "IMUL $dst,$src" %}
7929 opcode(0xAF, 0x0F);
7930 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7931 ins_pipe( ialu_reg_reg_alu0 );
7932 %}
7933
7934 // Multiply 32-bit Immediate
7935 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7936 match(Set dst (MulI src imm));
7937 effect(KILL cr);
7938
7939 ins_cost(300);
7940 format %{ "IMUL $dst,$src,$imm" %}
7941 opcode(0x69); /* 69 /r id */
7942 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7943 ins_pipe( ialu_reg_reg_alu0 );
7944 %}
7945
7946 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7947 match(Set dst src);
7948 effect(KILL cr);
7949
7950 // Note that this is artificially increased to make it more expensive than loadConL
7951 ins_cost(250);
7952 format %{ "MOV EAX,$src\t// low word only" %}
7953 opcode(0xB8);
7954 ins_encode( LdImmL_Lo(dst, src) );
7955 ins_pipe( ialu_reg_fat );
7956 %}
7957
7958 // Multiply by 32-bit Immediate, taking the shifted high order results
7959 // (special case for shift by 32)
7960 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7961 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7962 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7963 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7964 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7965 effect(USE src1, KILL cr);
7966
7967 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7968 ins_cost(0*100 + 1*400 - 150);
7969 format %{ "IMUL EDX:EAX,$src1" %}
7970 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7971 ins_pipe( pipe_slow );
7972 %}
7973
7974 // Multiply by 32-bit Immediate, taking the shifted high order results
7975 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7976 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7977 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7978 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7979 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7980 effect(USE src1, KILL cr);
7981
7982 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7983 ins_cost(1*100 + 1*400 - 150);
7984 format %{ "IMUL EDX:EAX,$src1\n\t"
7985 "SAR EDX,$cnt-32" %}
7986 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7987 ins_pipe( pipe_slow );
7988 %}
7989
7990 // Multiply Memory 32-bit Immediate
7991 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7992 match(Set dst (MulI (LoadI src) imm));
7993 effect(KILL cr);
7994
7995 ins_cost(300);
7996 format %{ "IMUL $dst,$src,$imm" %}
7997 opcode(0x69); /* 69 /r id */
7998 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7999 ins_pipe( ialu_reg_mem_alu0 );
8000 %}
8001
8002 // Multiply Memory
8003 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8004 match(Set dst (MulI dst (LoadI src)));
8005 effect(KILL cr);
8006
8007 ins_cost(350);
8008 format %{ "IMUL $dst,$src" %}
8009 opcode(0xAF, 0x0F);
8010 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8011 ins_pipe( ialu_reg_mem_alu0 );
8012 %}
8013
8014 // Multiply Register Int to Long
8015 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8016 // Basic Idea: long = (long)int * (long)int
8017 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8018 effect(DEF dst, USE src, USE src1, KILL flags);
8019
8020 ins_cost(300);
8021 format %{ "IMUL $dst,$src1" %}
8022
8023 ins_encode( long_int_multiply( dst, src1 ) );
8024 ins_pipe( ialu_reg_reg_alu0 );
8025 %}
8026
8027 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8028 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8029 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8030 effect(KILL flags);
8031
8032 ins_cost(300);
8033 format %{ "MUL $dst,$src1" %}
8034
8035 ins_encode( long_uint_multiply(dst, src1) );
8036 ins_pipe( ialu_reg_reg_alu0 );
8037 %}
8038
8039 // Multiply Register Long
8040 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8041 match(Set dst (MulL dst src));
8042 effect(KILL cr, TEMP tmp);
8043 ins_cost(4*100+3*400);
8044 // Basic idea: lo(result) = lo(x_lo * y_lo)
8045 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8046 format %{ "MOV $tmp,$src.lo\n\t"
8047 "IMUL $tmp,EDX\n\t"
8048 "MOV EDX,$src.hi\n\t"
8049 "IMUL EDX,EAX\n\t"
8050 "ADD $tmp,EDX\n\t"
8051 "MUL EDX:EAX,$src.lo\n\t"
8052 "ADD EDX,$tmp" %}
8053 ins_encode( long_multiply( dst, src, tmp ) );
8054 ins_pipe( pipe_slow );
8055 %}
8056
8057 // Multiply Register Long where the left operand's high 32 bits are zero
8058 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8059 predicate(is_operand_hi32_zero(n->in(1)));
8060 match(Set dst (MulL dst src));
8061 effect(KILL cr, TEMP tmp);
8062 ins_cost(2*100+2*400);
8063 // Basic idea: lo(result) = lo(x_lo * y_lo)
8064 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8065 format %{ "MOV $tmp,$src.hi\n\t"
8066 "IMUL $tmp,EAX\n\t"
8067 "MUL EDX:EAX,$src.lo\n\t"
8068 "ADD EDX,$tmp" %}
8069 ins_encode %{
8070 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8071 __ imull($tmp$$Register, rax);
8072 __ mull($src$$Register);
8073 __ addl(rdx, $tmp$$Register);
8074 %}
8075 ins_pipe( pipe_slow );
8076 %}
8077
8078 // Multiply Register Long where the right operand's high 32 bits are zero
8079 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8080 predicate(is_operand_hi32_zero(n->in(2)));
8081 match(Set dst (MulL dst src));
8082 effect(KILL cr, TEMP tmp);
8083 ins_cost(2*100+2*400);
8084 // Basic idea: lo(result) = lo(x_lo * y_lo)
8085 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8086 format %{ "MOV $tmp,$src.lo\n\t"
8087 "IMUL $tmp,EDX\n\t"
8088 "MUL EDX:EAX,$src.lo\n\t"
8089 "ADD EDX,$tmp" %}
8090 ins_encode %{
8091 __ movl($tmp$$Register, $src$$Register);
8092 __ imull($tmp$$Register, rdx);
8093 __ mull($src$$Register);
8094 __ addl(rdx, $tmp$$Register);
8095 %}
8096 ins_pipe( pipe_slow );
8097 %}
8098
8099 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8100 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8101 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8102 match(Set dst (MulL dst src));
8103 effect(KILL cr);
8104 ins_cost(1*400);
8105 // Basic idea: lo(result) = lo(x_lo * y_lo)
8106 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8107 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8108 ins_encode %{
8109 __ mull($src$$Register);
8110 %}
8111 ins_pipe( pipe_slow );
8112 %}
8113
8114 // Multiply Register Long by small constant
8115 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8116 match(Set dst (MulL dst src));
8117 effect(KILL cr, TEMP tmp);
8118 ins_cost(2*100+2*400);
8119 size(12);
8120 // Basic idea: lo(result) = lo(src * EAX)
8121 // hi(result) = hi(src * EAX) + lo(src * EDX)
8122 format %{ "IMUL $tmp,EDX,$src\n\t"
8123 "MOV EDX,$src\n\t"
8124 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8125 "ADD EDX,$tmp" %}
8126 ins_encode( long_multiply_con( dst, src, tmp ) );
8127 ins_pipe( pipe_slow );
8128 %}
8129
8130 // Integer DIV with Register
8131 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8132 match(Set rax (DivI rax div));
8133 effect(KILL rdx, KILL cr);
8134 size(26);
8135 ins_cost(30*100+10*100);
8136 format %{ "CMP EAX,0x80000000\n\t"
8137 "JNE,s normal\n\t"
8138 "XOR EDX,EDX\n\t"
8139 "CMP ECX,-1\n\t"
8140 "JE,s done\n"
8141 "normal: CDQ\n\t"
8142 "IDIV $div\n\t"
8143 "done:" %}
8144 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8145 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8146 ins_pipe( ialu_reg_reg_alu0 );
8147 %}
8148
8149 // Divide Register Long
8150 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8151 match(Set dst (DivL src1 src2));
8152 effect( KILL cr, KILL cx, KILL bx );
8153 ins_cost(10000);
8154 format %{ "PUSH $src1.hi\n\t"
8155 "PUSH $src1.lo\n\t"
8156 "PUSH $src2.hi\n\t"
8157 "PUSH $src2.lo\n\t"
8158 "CALL SharedRuntime::ldiv\n\t"
8159 "ADD ESP,16" %}
8160 ins_encode( long_div(src1,src2) );
8161 ins_pipe( pipe_slow );
8162 %}
8163
8164 // Integer DIVMOD with Register, both quotient and mod results
8165 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8166 match(DivModI rax div);
8167 effect(KILL cr);
8168 size(26);
8169 ins_cost(30*100+10*100);
8170 format %{ "CMP EAX,0x80000000\n\t"
8171 "JNE,s normal\n\t"
8172 "XOR EDX,EDX\n\t"
8173 "CMP ECX,-1\n\t"
8174 "JE,s done\n"
8175 "normal: CDQ\n\t"
8176 "IDIV $div\n\t"
8177 "done:" %}
8178 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8179 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8180 ins_pipe( pipe_slow );
8181 %}
8182
8183 // Integer MOD with Register
8184 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8185 match(Set rdx (ModI rax div));
8186 effect(KILL rax, KILL cr);
8187
8188 size(26);
8189 ins_cost(300);
8190 format %{ "CDQ\n\t"
8191 "IDIV $div" %}
8192 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8193 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8194 ins_pipe( ialu_reg_reg_alu0 );
8195 %}
8196
8197 // Remainder Register Long
8198 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8199 match(Set dst (ModL src1 src2));
8200 effect( KILL cr, KILL cx, KILL bx );
8201 ins_cost(10000);
8202 format %{ "PUSH $src1.hi\n\t"
8203 "PUSH $src1.lo\n\t"
8204 "PUSH $src2.hi\n\t"
8205 "PUSH $src2.lo\n\t"
8206 "CALL SharedRuntime::lrem\n\t"
8207 "ADD ESP,16" %}
8208 ins_encode( long_mod(src1,src2) );
8209 ins_pipe( pipe_slow );
8210 %}
8211
8212 // Divide Register Long (no special case since divisor != -1)
8213 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8214 match(Set dst (DivL dst imm));
8215 effect( TEMP tmp, TEMP tmp2, KILL cr );
8216 ins_cost(1000);
8217 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8218 "XOR $tmp2,$tmp2\n\t"
8219 "CMP $tmp,EDX\n\t"
8220 "JA,s fast\n\t"
8221 "MOV $tmp2,EAX\n\t"
8222 "MOV EAX,EDX\n\t"
8223 "MOV EDX,0\n\t"
8224 "JLE,s pos\n\t"
8225 "LNEG EAX : $tmp2\n\t"
8226 "DIV $tmp # unsigned division\n\t"
8227 "XCHG EAX,$tmp2\n\t"
8228 "DIV $tmp\n\t"
8229 "LNEG $tmp2 : EAX\n\t"
8230 "JMP,s done\n"
8231 "pos:\n\t"
8232 "DIV $tmp\n\t"
8233 "XCHG EAX,$tmp2\n"
8234 "fast:\n\t"
8235 "DIV $tmp\n"
8236 "done:\n\t"
8237 "MOV EDX,$tmp2\n\t"
8238 "NEG EDX:EAX # if $imm < 0" %}
8239 ins_encode %{
8240 int con = (int)$imm$$constant;
8241 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8242 int pcon = (con > 0) ? con : -con;
8243 Label Lfast, Lpos, Ldone;
8244
8245 __ movl($tmp$$Register, pcon);
8246 __ xorl($tmp2$$Register,$tmp2$$Register);
8247 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8248 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8249
8250 __ movl($tmp2$$Register, $dst$$Register); // save
8251 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8252 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8253 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8254
8255 // Negative dividend.
8256 // convert value to positive to use unsigned division
8257 __ lneg($dst$$Register, $tmp2$$Register);
8258 __ divl($tmp$$Register);
8259 __ xchgl($dst$$Register, $tmp2$$Register);
8260 __ divl($tmp$$Register);
8261 // revert result back to negative
8262 __ lneg($tmp2$$Register, $dst$$Register);
8263 __ jmpb(Ldone);
8264
8265 __ bind(Lpos);
8266 __ divl($tmp$$Register); // Use unsigned division
8267 __ xchgl($dst$$Register, $tmp2$$Register);
8268 // Fallthrow for final divide, tmp2 has 32 bit hi result
8269
8270 __ bind(Lfast);
8271 // fast path: src is positive
8272 __ divl($tmp$$Register); // Use unsigned division
8273
8274 __ bind(Ldone);
8275 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8276 if (con < 0) {
8277 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8278 }
8279 %}
8280 ins_pipe( pipe_slow );
8281 %}
8282
8283 // Remainder Register Long (remainder fit into 32 bits)
8284 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8285 match(Set dst (ModL dst imm));
8286 effect( TEMP tmp, TEMP tmp2, KILL cr );
8287 ins_cost(1000);
8288 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8289 "CMP $tmp,EDX\n\t"
8290 "JA,s fast\n\t"
8291 "MOV $tmp2,EAX\n\t"
8292 "MOV EAX,EDX\n\t"
8293 "MOV EDX,0\n\t"
8294 "JLE,s pos\n\t"
8295 "LNEG EAX : $tmp2\n\t"
8296 "DIV $tmp # unsigned division\n\t"
8297 "MOV EAX,$tmp2\n\t"
8298 "DIV $tmp\n\t"
8299 "NEG EDX\n\t"
8300 "JMP,s done\n"
8301 "pos:\n\t"
8302 "DIV $tmp\n\t"
8303 "MOV EAX,$tmp2\n"
8304 "fast:\n\t"
8305 "DIV $tmp\n"
8306 "done:\n\t"
8307 "MOV EAX,EDX\n\t"
8308 "SAR EDX,31\n\t" %}
8309 ins_encode %{
8310 int con = (int)$imm$$constant;
8311 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8312 int pcon = (con > 0) ? con : -con;
8313 Label Lfast, Lpos, Ldone;
8314
8315 __ movl($tmp$$Register, pcon);
8316 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8317 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8318
8319 __ movl($tmp2$$Register, $dst$$Register); // save
8320 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8321 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8322 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8323
8324 // Negative dividend.
8325 // convert value to positive to use unsigned division
8326 __ lneg($dst$$Register, $tmp2$$Register);
8327 __ divl($tmp$$Register);
8328 __ movl($dst$$Register, $tmp2$$Register);
8329 __ divl($tmp$$Register);
8330 // revert remainder back to negative
8331 __ negl(HIGH_FROM_LOW($dst$$Register));
8332 __ jmpb(Ldone);
8333
8334 __ bind(Lpos);
8335 __ divl($tmp$$Register);
8336 __ movl($dst$$Register, $tmp2$$Register);
8337
8338 __ bind(Lfast);
8339 // fast path: src is positive
8340 __ divl($tmp$$Register);
8341
8342 __ bind(Ldone);
8343 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8344 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8345
8346 %}
8347 ins_pipe( pipe_slow );
8348 %}
8349
8350 // Integer Shift Instructions
8351 // Shift Left by one
8352 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8353 match(Set dst (LShiftI dst shift));
8354 effect(KILL cr);
8355
8356 size(2);
8357 format %{ "SHL $dst,$shift" %}
8358 opcode(0xD1, 0x4); /* D1 /4 */
8359 ins_encode( OpcP, RegOpc( dst ) );
8360 ins_pipe( ialu_reg );
8361 %}
8362
8363 // Shift Left by 8-bit immediate
8364 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8365 match(Set dst (LShiftI dst shift));
8366 effect(KILL cr);
8367
8368 size(3);
8369 format %{ "SHL $dst,$shift" %}
8370 opcode(0xC1, 0x4); /* C1 /4 ib */
8371 ins_encode( RegOpcImm( dst, shift) );
8372 ins_pipe( ialu_reg );
8373 %}
8374
8375 // Shift Left by variable
8376 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8377 match(Set dst (LShiftI dst shift));
8378 effect(KILL cr);
8379
8380 size(2);
8381 format %{ "SHL $dst,$shift" %}
8382 opcode(0xD3, 0x4); /* D3 /4 */
8383 ins_encode( OpcP, RegOpc( dst ) );
8384 ins_pipe( ialu_reg_reg );
8385 %}
8386
8387 // Arithmetic shift right by one
8388 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8389 match(Set dst (RShiftI dst shift));
8390 effect(KILL cr);
8391
8392 size(2);
8393 format %{ "SAR $dst,$shift" %}
8394 opcode(0xD1, 0x7); /* D1 /7 */
8395 ins_encode( OpcP, RegOpc( dst ) );
8396 ins_pipe( ialu_reg );
8397 %}
8398
8399 // Arithmetic shift right by one
8400 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8401 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8402 effect(KILL cr);
8403 format %{ "SAR $dst,$shift" %}
8404 opcode(0xD1, 0x7); /* D1 /7 */
8405 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8406 ins_pipe( ialu_mem_imm );
8407 %}
8408
8409 // Arithmetic Shift Right by 8-bit immediate
8410 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8411 match(Set dst (RShiftI dst shift));
8412 effect(KILL cr);
8413
8414 size(3);
8415 format %{ "SAR $dst,$shift" %}
8416 opcode(0xC1, 0x7); /* C1 /7 ib */
8417 ins_encode( RegOpcImm( dst, shift ) );
8418 ins_pipe( ialu_mem_imm );
8419 %}
8420
8421 // Arithmetic Shift Right by 8-bit immediate
8422 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8423 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8424 effect(KILL cr);
8425
8426 format %{ "SAR $dst,$shift" %}
8427 opcode(0xC1, 0x7); /* C1 /7 ib */
8428 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8429 ins_pipe( ialu_mem_imm );
8430 %}
8431
8432 // Arithmetic Shift Right by variable
8433 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8434 match(Set dst (RShiftI dst shift));
8435 effect(KILL cr);
8436
8437 size(2);
8438 format %{ "SAR $dst,$shift" %}
8439 opcode(0xD3, 0x7); /* D3 /7 */
8440 ins_encode( OpcP, RegOpc( dst ) );
8441 ins_pipe( ialu_reg_reg );
8442 %}
8443
8444 // Logical shift right by one
8445 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8446 match(Set dst (URShiftI dst shift));
8447 effect(KILL cr);
8448
8449 size(2);
8450 format %{ "SHR $dst,$shift" %}
8451 opcode(0xD1, 0x5); /* D1 /5 */
8452 ins_encode( OpcP, RegOpc( dst ) );
8453 ins_pipe( ialu_reg );
8454 %}
8455
8456 // Logical Shift Right by 8-bit immediate
8457 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8458 match(Set dst (URShiftI dst shift));
8459 effect(KILL cr);
8460
8461 size(3);
8462 format %{ "SHR $dst,$shift" %}
8463 opcode(0xC1, 0x5); /* C1 /5 ib */
8464 ins_encode( RegOpcImm( dst, shift) );
8465 ins_pipe( ialu_reg );
8466 %}
8467
8468
8469 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8470 // This idiom is used by the compiler for the i2b bytecode.
8471 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8472 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8473
8474 size(3);
8475 format %{ "MOVSX $dst,$src :8" %}
8476 ins_encode %{
8477 __ movsbl($dst$$Register, $src$$Register);
8478 %}
8479 ins_pipe(ialu_reg_reg);
8480 %}
8481
8482 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8483 // This idiom is used by the compiler the i2s bytecode.
8484 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8485 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8486
8487 size(3);
8488 format %{ "MOVSX $dst,$src :16" %}
8489 ins_encode %{
8490 __ movswl($dst$$Register, $src$$Register);
8491 %}
8492 ins_pipe(ialu_reg_reg);
8493 %}
8494
8495
8496 // Logical Shift Right by variable
8497 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8498 match(Set dst (URShiftI dst shift));
8499 effect(KILL cr);
8500
8501 size(2);
8502 format %{ "SHR $dst,$shift" %}
8503 opcode(0xD3, 0x5); /* D3 /5 */
8504 ins_encode( OpcP, RegOpc( dst ) );
8505 ins_pipe( ialu_reg_reg );
8506 %}
8507
8508
8509 //----------Logical Instructions-----------------------------------------------
8510 //----------Integer Logical Instructions---------------------------------------
8511 // And Instructions
8512 // And Register with Register
8513 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8514 match(Set dst (AndI dst src));
8515 effect(KILL cr);
8516
8517 size(2);
8518 format %{ "AND $dst,$src" %}
8519 opcode(0x23);
8520 ins_encode( OpcP, RegReg( dst, src) );
8521 ins_pipe( ialu_reg_reg );
8522 %}
8523
8524 // And Register with Immediate
8525 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8526 match(Set dst (AndI dst src));
8527 effect(KILL cr);
8528
8529 format %{ "AND $dst,$src" %}
8530 opcode(0x81,0x04); /* Opcode 81 /4 */
8531 // ins_encode( RegImm( dst, src) );
8532 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8533 ins_pipe( ialu_reg );
8534 %}
8535
8536 // And Register with Memory
8537 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8538 match(Set dst (AndI dst (LoadI src)));
8539 effect(KILL cr);
8540
8541 ins_cost(125);
8542 format %{ "AND $dst,$src" %}
8543 opcode(0x23);
8544 ins_encode( OpcP, RegMem( dst, src) );
8545 ins_pipe( ialu_reg_mem );
8546 %}
8547
8548 // And Memory with Register
8549 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8550 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8551 effect(KILL cr);
8552
8553 ins_cost(150);
8554 format %{ "AND $dst,$src" %}
8555 opcode(0x21); /* Opcode 21 /r */
8556 ins_encode( OpcP, RegMem( src, dst ) );
8557 ins_pipe( ialu_mem_reg );
8558 %}
8559
8560 // And Memory with Immediate
8561 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8562 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8563 effect(KILL cr);
8564
8565 ins_cost(125);
8566 format %{ "AND $dst,$src" %}
8567 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8568 // ins_encode( MemImm( dst, src) );
8569 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8570 ins_pipe( ialu_mem_imm );
8571 %}
8572
8573 // Or Instructions
8574 // Or Register with Register
8575 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8576 match(Set dst (OrI dst src));
8577 effect(KILL cr);
8578
8579 size(2);
8580 format %{ "OR $dst,$src" %}
8581 opcode(0x0B);
8582 ins_encode( OpcP, RegReg( dst, src) );
8583 ins_pipe( ialu_reg_reg );
8584 %}
8585
8586 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8587 match(Set dst (OrI dst (CastP2X src)));
8588 effect(KILL cr);
8589
8590 size(2);
8591 format %{ "OR $dst,$src" %}
8592 opcode(0x0B);
8593 ins_encode( OpcP, RegReg( dst, src) );
8594 ins_pipe( ialu_reg_reg );
8595 %}
8596
8597
8598 // Or Register with Immediate
8599 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8600 match(Set dst (OrI dst src));
8601 effect(KILL cr);
8602
8603 format %{ "OR $dst,$src" %}
8604 opcode(0x81,0x01); /* Opcode 81 /1 id */
8605 // ins_encode( RegImm( dst, src) );
8606 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8607 ins_pipe( ialu_reg );
8608 %}
8609
8610 // Or Register with Memory
8611 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8612 match(Set dst (OrI dst (LoadI src)));
8613 effect(KILL cr);
8614
8615 ins_cost(125);
8616 format %{ "OR $dst,$src" %}
8617 opcode(0x0B);
8618 ins_encode( OpcP, RegMem( dst, src) );
8619 ins_pipe( ialu_reg_mem );
8620 %}
8621
8622 // Or Memory with Register
8623 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8624 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8625 effect(KILL cr);
8626
8627 ins_cost(150);
8628 format %{ "OR $dst,$src" %}
8629 opcode(0x09); /* Opcode 09 /r */
8630 ins_encode( OpcP, RegMem( src, dst ) );
8631 ins_pipe( ialu_mem_reg );
8632 %}
8633
8634 // Or Memory with Immediate
8635 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8636 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8637 effect(KILL cr);
8638
8639 ins_cost(125);
8640 format %{ "OR $dst,$src" %}
8641 opcode(0x81,0x1); /* Opcode 81 /1 id */
8642 // ins_encode( MemImm( dst, src) );
8643 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8644 ins_pipe( ialu_mem_imm );
8645 %}
8646
8647 // ROL/ROR
8648 // ROL expand
8649 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8650 effect(USE_DEF dst, USE shift, KILL cr);
8651
8652 format %{ "ROL $dst, $shift" %}
8653 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8654 ins_encode( OpcP, RegOpc( dst ));
8655 ins_pipe( ialu_reg );
8656 %}
8657
8658 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8659 effect(USE_DEF dst, USE shift, KILL cr);
8660
8661 format %{ "ROL $dst, $shift" %}
8662 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8663 ins_encode( RegOpcImm(dst, shift) );
8664 ins_pipe(ialu_reg);
8665 %}
8666
8667 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8668 effect(USE_DEF dst, USE shift, KILL cr);
8669
8670 format %{ "ROL $dst, $shift" %}
8671 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8672 ins_encode(OpcP, RegOpc(dst));
8673 ins_pipe( ialu_reg_reg );
8674 %}
8675 // end of ROL expand
8676
8677 // ROL 32bit by one once
8678 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8679 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8680
8681 expand %{
8682 rolI_eReg_imm1(dst, lshift, cr);
8683 %}
8684 %}
8685
8686 // ROL 32bit var by imm8 once
8687 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8688 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8689 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8690
8691 expand %{
8692 rolI_eReg_imm8(dst, lshift, cr);
8693 %}
8694 %}
8695
8696 // ROL 32bit var by var once
8697 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8698 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8699
8700 expand %{
8701 rolI_eReg_CL(dst, shift, cr);
8702 %}
8703 %}
8704
8705 // ROL 32bit var by var once
8706 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8707 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8708
8709 expand %{
8710 rolI_eReg_CL(dst, shift, cr);
8711 %}
8712 %}
8713
8714 // ROR expand
8715 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8716 effect(USE_DEF dst, USE shift, KILL cr);
8717
8718 format %{ "ROR $dst, $shift" %}
8719 opcode(0xD1,0x1); /* Opcode D1 /1 */
8720 ins_encode( OpcP, RegOpc( dst ) );
8721 ins_pipe( ialu_reg );
8722 %}
8723
8724 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8725 effect (USE_DEF dst, USE shift, KILL cr);
8726
8727 format %{ "ROR $dst, $shift" %}
8728 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8729 ins_encode( RegOpcImm(dst, shift) );
8730 ins_pipe( ialu_reg );
8731 %}
8732
8733 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8734 effect(USE_DEF dst, USE shift, KILL cr);
8735
8736 format %{ "ROR $dst, $shift" %}
8737 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8738 ins_encode(OpcP, RegOpc(dst));
8739 ins_pipe( ialu_reg_reg );
8740 %}
8741 // end of ROR expand
8742
8743 // ROR right once
8744 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8745 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8746
8747 expand %{
8748 rorI_eReg_imm1(dst, rshift, cr);
8749 %}
8750 %}
8751
8752 // ROR 32bit by immI8 once
8753 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8754 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8755 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8756
8757 expand %{
8758 rorI_eReg_imm8(dst, rshift, cr);
8759 %}
8760 %}
8761
8762 // ROR 32bit var by var once
8763 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8764 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8765
8766 expand %{
8767 rorI_eReg_CL(dst, shift, cr);
8768 %}
8769 %}
8770
8771 // ROR 32bit var by var once
8772 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8773 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8774
8775 expand %{
8776 rorI_eReg_CL(dst, shift, cr);
8777 %}
8778 %}
8779
8780 // Xor Instructions
8781 // Xor Register with Register
8782 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8783 match(Set dst (XorI dst src));
8784 effect(KILL cr);
8785
8786 size(2);
8787 format %{ "XOR $dst,$src" %}
8788 opcode(0x33);
8789 ins_encode( OpcP, RegReg( dst, src) );
8790 ins_pipe( ialu_reg_reg );
8791 %}
8792
8793 // Xor Register with Immediate -1
8794 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8795 match(Set dst (XorI dst imm));
8796
8797 size(2);
8798 format %{ "NOT $dst" %}
8799 ins_encode %{
8800 __ notl($dst$$Register);
8801 %}
8802 ins_pipe( ialu_reg );
8803 %}
8804
8805 // Xor Register with Immediate
8806 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8807 match(Set dst (XorI dst src));
8808 effect(KILL cr);
8809
8810 format %{ "XOR $dst,$src" %}
8811 opcode(0x81,0x06); /* Opcode 81 /6 id */
8812 // ins_encode( RegImm( dst, src) );
8813 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8814 ins_pipe( ialu_reg );
8815 %}
8816
8817 // Xor Register with Memory
8818 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8819 match(Set dst (XorI dst (LoadI src)));
8820 effect(KILL cr);
8821
8822 ins_cost(125);
8823 format %{ "XOR $dst,$src" %}
8824 opcode(0x33);
8825 ins_encode( OpcP, RegMem(dst, src) );
8826 ins_pipe( ialu_reg_mem );
8827 %}
8828
8829 // Xor Memory with Register
8830 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8831 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8832 effect(KILL cr);
8833
8834 ins_cost(150);
8835 format %{ "XOR $dst,$src" %}
8836 opcode(0x31); /* Opcode 31 /r */
8837 ins_encode( OpcP, RegMem( src, dst ) );
8838 ins_pipe( ialu_mem_reg );
8839 %}
8840
8841 // Xor Memory with Immediate
8842 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8843 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8844 effect(KILL cr);
8845
8846 ins_cost(125);
8847 format %{ "XOR $dst,$src" %}
8848 opcode(0x81,0x6); /* Opcode 81 /6 id */
8849 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8850 ins_pipe( ialu_mem_imm );
8851 %}
8852
8853 //----------Convert Int to Boolean---------------------------------------------
8854
8855 instruct movI_nocopy(rRegI dst, rRegI src) %{
8856 effect( DEF dst, USE src );
8857 format %{ "MOV $dst,$src" %}
8858 ins_encode( enc_Copy( dst, src) );
8859 ins_pipe( ialu_reg_reg );
8860 %}
8861
8862 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8863 effect( USE_DEF dst, USE src, KILL cr );
8864
8865 size(4);
8866 format %{ "NEG $dst\n\t"
8867 "ADC $dst,$src" %}
8868 ins_encode( neg_reg(dst),
8869 OpcRegReg(0x13,dst,src) );
8870 ins_pipe( ialu_reg_reg_long );
8871 %}
8872
8873 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8874 match(Set dst (Conv2B src));
8875
8876 expand %{
8877 movI_nocopy(dst,src);
8878 ci2b(dst,src,cr);
8879 %}
8880 %}
8881
8882 instruct movP_nocopy(rRegI dst, eRegP src) %{
8883 effect( DEF dst, USE src );
8884 format %{ "MOV $dst,$src" %}
8885 ins_encode( enc_Copy( dst, src) );
8886 ins_pipe( ialu_reg_reg );
8887 %}
8888
8889 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8890 effect( USE_DEF dst, USE src, KILL cr );
8891 format %{ "NEG $dst\n\t"
8892 "ADC $dst,$src" %}
8893 ins_encode( neg_reg(dst),
8894 OpcRegReg(0x13,dst,src) );
8895 ins_pipe( ialu_reg_reg_long );
8896 %}
8897
8898 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8899 match(Set dst (Conv2B src));
8900
8901 expand %{
8902 movP_nocopy(dst,src);
8903 cp2b(dst,src,cr);
8904 %}
8905 %}
8906
8907 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8908 match(Set dst (CmpLTMask p q));
8909 effect( KILL cr );
8910 ins_cost(400);
8911
8912 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8913 format %{ "XOR $dst,$dst\n\t"
8914 "CMP $p,$q\n\t"
8915 "SETlt $dst\n\t"
8916 "NEG $dst" %}
8917 ins_encode( OpcRegReg(0x33,dst,dst),
8918 OpcRegReg(0x3B,p,q),
8919 setLT_reg(dst), neg_reg(dst) );
8920 ins_pipe( pipe_slow );
8921 %}
8922
8923 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8924 match(Set dst (CmpLTMask dst zero));
8925 effect( DEF dst, KILL cr );
8926 ins_cost(100);
8927
8928 format %{ "SAR $dst,31" %}
8929 opcode(0xC1, 0x7); /* C1 /7 ib */
8930 ins_encode( RegOpcImm( dst, 0x1F ) );
8931 ins_pipe( ialu_reg );
8932 %}
8933
8934
8935 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8936 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8937 effect( KILL tmp, KILL cr );
8938 ins_cost(400);
8939 // annoyingly, $tmp has no edges so you cant ask for it in
8940 // any format or encoding
8941 format %{ "SUB $p,$q\n\t"
8942 "SBB ECX,ECX\n\t"
8943 "AND ECX,$y\n\t"
8944 "ADD $p,ECX" %}
8945 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8946 ins_pipe( pipe_cmplt );
8947 %}
8948
8949 /* If I enable this, I encourage spilling in the inner loop of compress.
8950 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8951 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8952 effect( USE_KILL tmp, KILL cr );
8953 ins_cost(400);
8954
8955 format %{ "SUB $p,$q\n\t"
8956 "SBB ECX,ECX\n\t"
8957 "AND ECX,$y\n\t"
8958 "ADD $p,ECX" %}
8959 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8960 %}
8961 */
8962
8963 //----------Long Instructions------------------------------------------------
8964 // Add Long Register with Register
8965 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8966 match(Set dst (AddL dst src));
8967 effect(KILL cr);
8968 ins_cost(200);
8969 format %{ "ADD $dst.lo,$src.lo\n\t"
8970 "ADC $dst.hi,$src.hi" %}
8971 opcode(0x03, 0x13);
8972 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8973 ins_pipe( ialu_reg_reg_long );
8974 %}
8975
8976 // Add Long Register with Immediate
8977 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8978 match(Set dst (AddL dst src));
8979 effect(KILL cr);
8980 format %{ "ADD $dst.lo,$src.lo\n\t"
8981 "ADC $dst.hi,$src.hi" %}
8982 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8983 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8984 ins_pipe( ialu_reg_long );
8985 %}
8986
8987 // Add Long Register with Memory
8988 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8989 match(Set dst (AddL dst (LoadL mem)));
8990 effect(KILL cr);
8991 ins_cost(125);
8992 format %{ "ADD $dst.lo,$mem\n\t"
8993 "ADC $dst.hi,$mem+4" %}
8994 opcode(0x03, 0x13);
8995 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8996 ins_pipe( ialu_reg_long_mem );
8997 %}
8998
8999 // Subtract Long Register with Register.
9000 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9001 match(Set dst (SubL dst src));
9002 effect(KILL cr);
9003 ins_cost(200);
9004 format %{ "SUB $dst.lo,$src.lo\n\t"
9005 "SBB $dst.hi,$src.hi" %}
9006 opcode(0x2B, 0x1B);
9007 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9008 ins_pipe( ialu_reg_reg_long );
9009 %}
9010
9011 // Subtract Long Register with Immediate
9012 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9013 match(Set dst (SubL dst src));
9014 effect(KILL cr);
9015 format %{ "SUB $dst.lo,$src.lo\n\t"
9016 "SBB $dst.hi,$src.hi" %}
9017 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9018 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9019 ins_pipe( ialu_reg_long );
9020 %}
9021
9022 // Subtract Long Register with Memory
9023 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9024 match(Set dst (SubL dst (LoadL mem)));
9025 effect(KILL cr);
9026 ins_cost(125);
9027 format %{ "SUB $dst.lo,$mem\n\t"
9028 "SBB $dst.hi,$mem+4" %}
9029 opcode(0x2B, 0x1B);
9030 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9031 ins_pipe( ialu_reg_long_mem );
9032 %}
9033
9034 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9035 match(Set dst (SubL zero dst));
9036 effect(KILL cr);
9037 ins_cost(300);
9038 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9039 ins_encode( neg_long(dst) );
9040 ins_pipe( ialu_reg_reg_long );
9041 %}
9042
9043 // And Long Register with Register
9044 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9045 match(Set dst (AndL dst src));
9046 effect(KILL cr);
9047 format %{ "AND $dst.lo,$src.lo\n\t"
9048 "AND $dst.hi,$src.hi" %}
9049 opcode(0x23,0x23);
9050 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9051 ins_pipe( ialu_reg_reg_long );
9052 %}
9053
9054 // And Long Register with Immediate
9055 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9056 match(Set dst (AndL dst src));
9057 effect(KILL cr);
9058 format %{ "AND $dst.lo,$src.lo\n\t"
9059 "AND $dst.hi,$src.hi" %}
9060 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9061 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9062 ins_pipe( ialu_reg_long );
9063 %}
9064
9065 // And Long Register with Memory
9066 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9067 match(Set dst (AndL dst (LoadL mem)));
9068 effect(KILL cr);
9069 ins_cost(125);
9070 format %{ "AND $dst.lo,$mem\n\t"
9071 "AND $dst.hi,$mem+4" %}
9072 opcode(0x23, 0x23);
9073 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9074 ins_pipe( ialu_reg_long_mem );
9075 %}
9076
9077 // Or Long Register with Register
9078 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9079 match(Set dst (OrL dst src));
9080 effect(KILL cr);
9081 format %{ "OR $dst.lo,$src.lo\n\t"
9082 "OR $dst.hi,$src.hi" %}
9083 opcode(0x0B,0x0B);
9084 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9085 ins_pipe( ialu_reg_reg_long );
9086 %}
9087
9088 // Or Long Register with Immediate
9089 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9090 match(Set dst (OrL dst src));
9091 effect(KILL cr);
9092 format %{ "OR $dst.lo,$src.lo\n\t"
9093 "OR $dst.hi,$src.hi" %}
9094 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9095 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9096 ins_pipe( ialu_reg_long );
9097 %}
9098
9099 // Or Long Register with Memory
9100 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9101 match(Set dst (OrL dst (LoadL mem)));
9102 effect(KILL cr);
9103 ins_cost(125);
9104 format %{ "OR $dst.lo,$mem\n\t"
9105 "OR $dst.hi,$mem+4" %}
9106 opcode(0x0B,0x0B);
9107 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9108 ins_pipe( ialu_reg_long_mem );
9109 %}
9110
9111 // Xor Long Register with Register
9112 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9113 match(Set dst (XorL dst src));
9114 effect(KILL cr);
9115 format %{ "XOR $dst.lo,$src.lo\n\t"
9116 "XOR $dst.hi,$src.hi" %}
9117 opcode(0x33,0x33);
9118 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9119 ins_pipe( ialu_reg_reg_long );
9120 %}
9121
9122 // Xor Long Register with Immediate -1
9123 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9124 match(Set dst (XorL dst imm));
9125 format %{ "NOT $dst.lo\n\t"
9126 "NOT $dst.hi" %}
9127 ins_encode %{
9128 __ notl($dst$$Register);
9129 __ notl(HIGH_FROM_LOW($dst$$Register));
9130 %}
9131 ins_pipe( ialu_reg_long );
9132 %}
9133
9134 // Xor Long Register with Immediate
9135 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9136 match(Set dst (XorL dst src));
9137 effect(KILL cr);
9138 format %{ "XOR $dst.lo,$src.lo\n\t"
9139 "XOR $dst.hi,$src.hi" %}
9140 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9141 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9142 ins_pipe( ialu_reg_long );
9143 %}
9144
9145 // Xor Long Register with Memory
9146 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9147 match(Set dst (XorL dst (LoadL mem)));
9148 effect(KILL cr);
9149 ins_cost(125);
9150 format %{ "XOR $dst.lo,$mem\n\t"
9151 "XOR $dst.hi,$mem+4" %}
9152 opcode(0x33,0x33);
9153 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9154 ins_pipe( ialu_reg_long_mem );
9155 %}
9156
9157 // Shift Left Long by 1
9158 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9159 predicate(UseNewLongLShift);
9160 match(Set dst (LShiftL dst cnt));
9161 effect(KILL cr);
9162 ins_cost(100);
9163 format %{ "ADD $dst.lo,$dst.lo\n\t"
9164 "ADC $dst.hi,$dst.hi" %}
9165 ins_encode %{
9166 __ addl($dst$$Register,$dst$$Register);
9167 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9168 %}
9169 ins_pipe( ialu_reg_long );
9170 %}
9171
9172 // Shift Left Long by 2
9173 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9174 predicate(UseNewLongLShift);
9175 match(Set dst (LShiftL dst cnt));
9176 effect(KILL cr);
9177 ins_cost(100);
9178 format %{ "ADD $dst.lo,$dst.lo\n\t"
9179 "ADC $dst.hi,$dst.hi\n\t"
9180 "ADD $dst.lo,$dst.lo\n\t"
9181 "ADC $dst.hi,$dst.hi" %}
9182 ins_encode %{
9183 __ addl($dst$$Register,$dst$$Register);
9184 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9185 __ addl($dst$$Register,$dst$$Register);
9186 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9187 %}
9188 ins_pipe( ialu_reg_long );
9189 %}
9190
9191 // Shift Left Long by 3
9192 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9193 predicate(UseNewLongLShift);
9194 match(Set dst (LShiftL dst cnt));
9195 effect(KILL cr);
9196 ins_cost(100);
9197 format %{ "ADD $dst.lo,$dst.lo\n\t"
9198 "ADC $dst.hi,$dst.hi\n\t"
9199 "ADD $dst.lo,$dst.lo\n\t"
9200 "ADC $dst.hi,$dst.hi\n\t"
9201 "ADD $dst.lo,$dst.lo\n\t"
9202 "ADC $dst.hi,$dst.hi" %}
9203 ins_encode %{
9204 __ addl($dst$$Register,$dst$$Register);
9205 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9206 __ addl($dst$$Register,$dst$$Register);
9207 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9208 __ addl($dst$$Register,$dst$$Register);
9209 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9210 %}
9211 ins_pipe( ialu_reg_long );
9212 %}
9213
9214 // Shift Left Long by 1-31
9215 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9216 match(Set dst (LShiftL dst cnt));
9217 effect(KILL cr);
9218 ins_cost(200);
9219 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9220 "SHL $dst.lo,$cnt" %}
9221 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9222 ins_encode( move_long_small_shift(dst,cnt) );
9223 ins_pipe( ialu_reg_long );
9224 %}
9225
9226 // Shift Left Long by 32-63
9227 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9228 match(Set dst (LShiftL dst cnt));
9229 effect(KILL cr);
9230 ins_cost(300);
9231 format %{ "MOV $dst.hi,$dst.lo\n"
9232 "\tSHL $dst.hi,$cnt-32\n"
9233 "\tXOR $dst.lo,$dst.lo" %}
9234 opcode(0xC1, 0x4); /* C1 /4 ib */
9235 ins_encode( move_long_big_shift_clr(dst,cnt) );
9236 ins_pipe( ialu_reg_long );
9237 %}
9238
9239 // Shift Left Long by variable
9240 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9241 match(Set dst (LShiftL dst shift));
9242 effect(KILL cr);
9243 ins_cost(500+200);
9244 size(17);
9245 format %{ "TEST $shift,32\n\t"
9246 "JEQ,s small\n\t"
9247 "MOV $dst.hi,$dst.lo\n\t"
9248 "XOR $dst.lo,$dst.lo\n"
9249 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9250 "SHL $dst.lo,$shift" %}
9251 ins_encode( shift_left_long( dst, shift ) );
9252 ins_pipe( pipe_slow );
9253 %}
9254
9255 // Shift Right Long by 1-31
9256 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9257 match(Set dst (URShiftL dst cnt));
9258 effect(KILL cr);
9259 ins_cost(200);
9260 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9261 "SHR $dst.hi,$cnt" %}
9262 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9263 ins_encode( move_long_small_shift(dst,cnt) );
9264 ins_pipe( ialu_reg_long );
9265 %}
9266
9267 // Shift Right Long by 32-63
9268 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9269 match(Set dst (URShiftL dst cnt));
9270 effect(KILL cr);
9271 ins_cost(300);
9272 format %{ "MOV $dst.lo,$dst.hi\n"
9273 "\tSHR $dst.lo,$cnt-32\n"
9274 "\tXOR $dst.hi,$dst.hi" %}
9275 opcode(0xC1, 0x5); /* C1 /5 ib */
9276 ins_encode( move_long_big_shift_clr(dst,cnt) );
9277 ins_pipe( ialu_reg_long );
9278 %}
9279
9280 // Shift Right Long by variable
9281 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9282 match(Set dst (URShiftL dst shift));
9283 effect(KILL cr);
9284 ins_cost(600);
9285 size(17);
9286 format %{ "TEST $shift,32\n\t"
9287 "JEQ,s small\n\t"
9288 "MOV $dst.lo,$dst.hi\n\t"
9289 "XOR $dst.hi,$dst.hi\n"
9290 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9291 "SHR $dst.hi,$shift" %}
9292 ins_encode( shift_right_long( dst, shift ) );
9293 ins_pipe( pipe_slow );
9294 %}
9295
9296 // Shift Right Long by 1-31
9297 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9298 match(Set dst (RShiftL dst cnt));
9299 effect(KILL cr);
9300 ins_cost(200);
9301 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9302 "SAR $dst.hi,$cnt" %}
9303 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9304 ins_encode( move_long_small_shift(dst,cnt) );
9305 ins_pipe( ialu_reg_long );
9306 %}
9307
9308 // Shift Right Long by 32-63
9309 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9310 match(Set dst (RShiftL dst cnt));
9311 effect(KILL cr);
9312 ins_cost(300);
9313 format %{ "MOV $dst.lo,$dst.hi\n"
9314 "\tSAR $dst.lo,$cnt-32\n"
9315 "\tSAR $dst.hi,31" %}
9316 opcode(0xC1, 0x7); /* C1 /7 ib */
9317 ins_encode( move_long_big_shift_sign(dst,cnt) );
9318 ins_pipe( ialu_reg_long );
9319 %}
9320
9321 // Shift Right arithmetic Long by variable
9322 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9323 match(Set dst (RShiftL dst shift));
9324 effect(KILL cr);
9325 ins_cost(600);
9326 size(18);
9327 format %{ "TEST $shift,32\n\t"
9328 "JEQ,s small\n\t"
9329 "MOV $dst.lo,$dst.hi\n\t"
9330 "SAR $dst.hi,31\n"
9331 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9332 "SAR $dst.hi,$shift" %}
9333 ins_encode( shift_right_arith_long( dst, shift ) );
9334 ins_pipe( pipe_slow );
9335 %}
9336
9337
9338 //----------Double Instructions------------------------------------------------
9339 // Double Math
9340
9341 // Compare & branch
9342
9343 // P6 version of float compare, sets condition codes in EFLAGS
9344 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9345 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9346 match(Set cr (CmpD src1 src2));
9347 effect(KILL rax);
9348 ins_cost(150);
9349 format %{ "FLD $src1\n\t"
9350 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9351 "JNP exit\n\t"
9352 "MOV ah,1 // saw a NaN, set CF\n\t"
9353 "SAHF\n"
9354 "exit:\tNOP // avoid branch to branch" %}
9355 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9356 ins_encode( Push_Reg_DPR(src1),
9357 OpcP, RegOpc(src2),
9358 cmpF_P6_fixup );
9359 ins_pipe( pipe_slow );
9360 %}
9361
9362 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9363 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9364 match(Set cr (CmpD src1 src2));
9365 ins_cost(150);
9366 format %{ "FLD $src1\n\t"
9367 "FUCOMIP ST,$src2 // P6 instruction" %}
9368 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9369 ins_encode( Push_Reg_DPR(src1),
9370 OpcP, RegOpc(src2));
9371 ins_pipe( pipe_slow );
9372 %}
9373
9374 // Compare & branch
9375 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9376 predicate(UseSSE<=1);
9377 match(Set cr (CmpD src1 src2));
9378 effect(KILL rax);
9379 ins_cost(200);
9380 format %{ "FLD $src1\n\t"
9381 "FCOMp $src2\n\t"
9382 "FNSTSW AX\n\t"
9383 "TEST AX,0x400\n\t"
9384 "JZ,s flags\n\t"
9385 "MOV AH,1\t# unordered treat as LT\n"
9386 "flags:\tSAHF" %}
9387 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9388 ins_encode( Push_Reg_DPR(src1),
9389 OpcP, RegOpc(src2),
9390 fpu_flags);
9391 ins_pipe( pipe_slow );
9392 %}
9393
9394 // Compare vs zero into -1,0,1
9395 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9396 predicate(UseSSE<=1);
9397 match(Set dst (CmpD3 src1 zero));
9398 effect(KILL cr, KILL rax);
9399 ins_cost(280);
9400 format %{ "FTSTD $dst,$src1" %}
9401 opcode(0xE4, 0xD9);
9402 ins_encode( Push_Reg_DPR(src1),
9403 OpcS, OpcP, PopFPU,
9404 CmpF_Result(dst));
9405 ins_pipe( pipe_slow );
9406 %}
9407
9408 // Compare into -1,0,1
9409 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9410 predicate(UseSSE<=1);
9411 match(Set dst (CmpD3 src1 src2));
9412 effect(KILL cr, KILL rax);
9413 ins_cost(300);
9414 format %{ "FCMPD $dst,$src1,$src2" %}
9415 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9416 ins_encode( Push_Reg_DPR(src1),
9417 OpcP, RegOpc(src2),
9418 CmpF_Result(dst));
9419 ins_pipe( pipe_slow );
9420 %}
9421
9422 // float compare and set condition codes in EFLAGS by XMM regs
9423 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9424 predicate(UseSSE>=2);
9425 match(Set cr (CmpD src1 src2));
9426 ins_cost(145);
9427 format %{ "UCOMISD $src1,$src2\n\t"
9428 "JNP,s exit\n\t"
9429 "PUSHF\t# saw NaN, set CF\n\t"
9430 "AND [rsp], #0xffffff2b\n\t"
9431 "POPF\n"
9432 "exit:" %}
9433 ins_encode %{
9434 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9435 emit_cmpfp_fixup(_masm);
9436 %}
9437 ins_pipe( pipe_slow );
9438 %}
9439
9440 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9441 predicate(UseSSE>=2);
9442 match(Set cr (CmpD src1 src2));
9443 ins_cost(100);
9444 format %{ "UCOMISD $src1,$src2" %}
9445 ins_encode %{
9446 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9447 %}
9448 ins_pipe( pipe_slow );
9449 %}
9450
9451 // float compare and set condition codes in EFLAGS by XMM regs
9452 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9453 predicate(UseSSE>=2);
9454 match(Set cr (CmpD src1 (LoadD src2)));
9455 ins_cost(145);
9456 format %{ "UCOMISD $src1,$src2\n\t"
9457 "JNP,s exit\n\t"
9458 "PUSHF\t# saw NaN, set CF\n\t"
9459 "AND [rsp], #0xffffff2b\n\t"
9460 "POPF\n"
9461 "exit:" %}
9462 ins_encode %{
9463 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9464 emit_cmpfp_fixup(_masm);
9465 %}
9466 ins_pipe( pipe_slow );
9467 %}
9468
9469 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9470 predicate(UseSSE>=2);
9471 match(Set cr (CmpD src1 (LoadD src2)));
9472 ins_cost(100);
9473 format %{ "UCOMISD $src1,$src2" %}
9474 ins_encode %{
9475 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9476 %}
9477 ins_pipe( pipe_slow );
9478 %}
9479
9480 // Compare into -1,0,1 in XMM
9481 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9482 predicate(UseSSE>=2);
9483 match(Set dst (CmpD3 src1 src2));
9484 effect(KILL cr);
9485 ins_cost(255);
9486 format %{ "UCOMISD $src1, $src2\n\t"
9487 "MOV $dst, #-1\n\t"
9488 "JP,s done\n\t"
9489 "JB,s done\n\t"
9490 "SETNE $dst\n\t"
9491 "MOVZB $dst, $dst\n"
9492 "done:" %}
9493 ins_encode %{
9494 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9495 emit_cmpfp3(_masm, $dst$$Register);
9496 %}
9497 ins_pipe( pipe_slow );
9498 %}
9499
9500 // Compare into -1,0,1 in XMM and memory
9501 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9502 predicate(UseSSE>=2);
9503 match(Set dst (CmpD3 src1 (LoadD src2)));
9504 effect(KILL cr);
9505 ins_cost(275);
9506 format %{ "UCOMISD $src1, $src2\n\t"
9507 "MOV $dst, #-1\n\t"
9508 "JP,s done\n\t"
9509 "JB,s done\n\t"
9510 "SETNE $dst\n\t"
9511 "MOVZB $dst, $dst\n"
9512 "done:" %}
9513 ins_encode %{
9514 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9515 emit_cmpfp3(_masm, $dst$$Register);
9516 %}
9517 ins_pipe( pipe_slow );
9518 %}
9519
9520
9521 instruct subDPR_reg(regDPR dst, regDPR src) %{
9522 predicate (UseSSE <=1);
9523 match(Set dst (SubD dst src));
9524
9525 format %{ "FLD $src\n\t"
9526 "DSUBp $dst,ST" %}
9527 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9528 ins_cost(150);
9529 ins_encode( Push_Reg_DPR(src),
9530 OpcP, RegOpc(dst) );
9531 ins_pipe( fpu_reg_reg );
9532 %}
9533
9534 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9535 predicate (UseSSE <=1);
9536 match(Set dst (RoundDouble (SubD src1 src2)));
9537 ins_cost(250);
9538
9539 format %{ "FLD $src2\n\t"
9540 "DSUB ST,$src1\n\t"
9541 "FSTP_D $dst\t# D-round" %}
9542 opcode(0xD8, 0x5);
9543 ins_encode( Push_Reg_DPR(src2),
9544 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9545 ins_pipe( fpu_mem_reg_reg );
9546 %}
9547
9548
9549 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9550 predicate (UseSSE <=1);
9551 match(Set dst (SubD dst (LoadD src)));
9552 ins_cost(150);
9553
9554 format %{ "FLD $src\n\t"
9555 "DSUBp $dst,ST" %}
9556 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9557 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9558 OpcP, RegOpc(dst) );
9559 ins_pipe( fpu_reg_mem );
9560 %}
9561
9562 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9563 predicate (UseSSE<=1);
9564 match(Set dst (AbsD src));
9565 ins_cost(100);
9566 format %{ "FABS" %}
9567 opcode(0xE1, 0xD9);
9568 ins_encode( OpcS, OpcP );
9569 ins_pipe( fpu_reg_reg );
9570 %}
9571
9572 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9573 predicate(UseSSE<=1);
9574 match(Set dst (NegD src));
9575 ins_cost(100);
9576 format %{ "FCHS" %}
9577 opcode(0xE0, 0xD9);
9578 ins_encode( OpcS, OpcP );
9579 ins_pipe( fpu_reg_reg );
9580 %}
9581
9582 instruct addDPR_reg(regDPR dst, regDPR src) %{
9583 predicate(UseSSE<=1);
9584 match(Set dst (AddD dst src));
9585 format %{ "FLD $src\n\t"
9586 "DADD $dst,ST" %}
9587 size(4);
9588 ins_cost(150);
9589 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9590 ins_encode( Push_Reg_DPR(src),
9591 OpcP, RegOpc(dst) );
9592 ins_pipe( fpu_reg_reg );
9593 %}
9594
9595
9596 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9597 predicate(UseSSE<=1);
9598 match(Set dst (RoundDouble (AddD src1 src2)));
9599 ins_cost(250);
9600
9601 format %{ "FLD $src2\n\t"
9602 "DADD ST,$src1\n\t"
9603 "FSTP_D $dst\t# D-round" %}
9604 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9605 ins_encode( Push_Reg_DPR(src2),
9606 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9607 ins_pipe( fpu_mem_reg_reg );
9608 %}
9609
9610
9611 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9612 predicate(UseSSE<=1);
9613 match(Set dst (AddD dst (LoadD src)));
9614 ins_cost(150);
9615
9616 format %{ "FLD $src\n\t"
9617 "DADDp $dst,ST" %}
9618 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9619 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9620 OpcP, RegOpc(dst) );
9621 ins_pipe( fpu_reg_mem );
9622 %}
9623
9624 // add-to-memory
9625 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9626 predicate(UseSSE<=1);
9627 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9628 ins_cost(150);
9629
9630 format %{ "FLD_D $dst\n\t"
9631 "DADD ST,$src\n\t"
9632 "FST_D $dst" %}
9633 opcode(0xDD, 0x0);
9634 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9635 Opcode(0xD8), RegOpc(src),
9636 set_instruction_start,
9637 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9638 ins_pipe( fpu_reg_mem );
9639 %}
9640
9641 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9642 predicate(UseSSE<=1);
9643 match(Set dst (AddD dst con));
9644 ins_cost(125);
9645 format %{ "FLD1\n\t"
9646 "DADDp $dst,ST" %}
9647 ins_encode %{
9648 __ fld1();
9649 __ faddp($dst$$reg);
9650 %}
9651 ins_pipe(fpu_reg);
9652 %}
9653
9654 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9655 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9656 match(Set dst (AddD dst con));
9657 ins_cost(200);
9658 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9659 "DADDp $dst,ST" %}
9660 ins_encode %{
9661 __ fld_d($constantaddress($con));
9662 __ faddp($dst$$reg);
9663 %}
9664 ins_pipe(fpu_reg_mem);
9665 %}
9666
9667 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9668 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9669 match(Set dst (RoundDouble (AddD src con)));
9670 ins_cost(200);
9671 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9672 "DADD ST,$src\n\t"
9673 "FSTP_D $dst\t# D-round" %}
9674 ins_encode %{
9675 __ fld_d($constantaddress($con));
9676 __ fadd($src$$reg);
9677 __ fstp_d(Address(rsp, $dst$$disp));
9678 %}
9679 ins_pipe(fpu_mem_reg_con);
9680 %}
9681
9682 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9683 predicate(UseSSE<=1);
9684 match(Set dst (MulD dst src));
9685 format %{ "FLD $src\n\t"
9686 "DMULp $dst,ST" %}
9687 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9688 ins_cost(150);
9689 ins_encode( Push_Reg_DPR(src),
9690 OpcP, RegOpc(dst) );
9691 ins_pipe( fpu_reg_reg );
9692 %}
9693
9694 // Strict FP instruction biases argument before multiply then
9695 // biases result to avoid double rounding of subnormals.
9696 //
9697 // scale arg1 by multiplying arg1 by 2^(-15360)
9698 // load arg2
9699 // multiply scaled arg1 by arg2
9700 // rescale product by 2^(15360)
9701 //
9702 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9703 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9704 match(Set dst (MulD dst src));
9705 ins_cost(1); // Select this instruction for all strict FP double multiplies
9706
9707 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9708 "DMULp $dst,ST\n\t"
9709 "FLD $src\n\t"
9710 "DMULp $dst,ST\n\t"
9711 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9712 "DMULp $dst,ST\n\t" %}
9713 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9714 ins_encode( strictfp_bias1(dst),
9715 Push_Reg_DPR(src),
9716 OpcP, RegOpc(dst),
9717 strictfp_bias2(dst) );
9718 ins_pipe( fpu_reg_reg );
9719 %}
9720
9721 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9722 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9723 match(Set dst (MulD dst con));
9724 ins_cost(200);
9725 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9726 "DMULp $dst,ST" %}
9727 ins_encode %{
9728 __ fld_d($constantaddress($con));
9729 __ fmulp($dst$$reg);
9730 %}
9731 ins_pipe(fpu_reg_mem);
9732 %}
9733
9734
9735 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9736 predicate( UseSSE<=1 );
9737 match(Set dst (MulD dst (LoadD src)));
9738 ins_cost(200);
9739 format %{ "FLD_D $src\n\t"
9740 "DMULp $dst,ST" %}
9741 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9742 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9743 OpcP, RegOpc(dst) );
9744 ins_pipe( fpu_reg_mem );
9745 %}
9746
9747 //
9748 // Cisc-alternate to reg-reg multiply
9749 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9750 predicate( UseSSE<=1 );
9751 match(Set dst (MulD src (LoadD mem)));
9752 ins_cost(250);
9753 format %{ "FLD_D $mem\n\t"
9754 "DMUL ST,$src\n\t"
9755 "FSTP_D $dst" %}
9756 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9757 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9758 OpcReg_FPR(src),
9759 Pop_Reg_DPR(dst) );
9760 ins_pipe( fpu_reg_reg_mem );
9761 %}
9762
9763
9764 // MACRO3 -- addDPR a mulDPR
9765 // This instruction is a '2-address' instruction in that the result goes
9766 // back to src2. This eliminates a move from the macro; possibly the
9767 // register allocator will have to add it back (and maybe not).
9768 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9769 predicate( UseSSE<=1 );
9770 match(Set src2 (AddD (MulD src0 src1) src2));
9771 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9772 "DMUL ST,$src1\n\t"
9773 "DADDp $src2,ST" %}
9774 ins_cost(250);
9775 opcode(0xDD); /* LoadD DD /0 */
9776 ins_encode( Push_Reg_FPR(src0),
9777 FMul_ST_reg(src1),
9778 FAddP_reg_ST(src2) );
9779 ins_pipe( fpu_reg_reg_reg );
9780 %}
9781
9782
9783 // MACRO3 -- subDPR a mulDPR
9784 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9785 predicate( UseSSE<=1 );
9786 match(Set src2 (SubD (MulD src0 src1) src2));
9787 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9788 "DMUL ST,$src1\n\t"
9789 "DSUBRp $src2,ST" %}
9790 ins_cost(250);
9791 ins_encode( Push_Reg_FPR(src0),
9792 FMul_ST_reg(src1),
9793 Opcode(0xDE), Opc_plus(0xE0,src2));
9794 ins_pipe( fpu_reg_reg_reg );
9795 %}
9796
9797
9798 instruct divDPR_reg(regDPR dst, regDPR src) %{
9799 predicate( UseSSE<=1 );
9800 match(Set dst (DivD dst src));
9801
9802 format %{ "FLD $src\n\t"
9803 "FDIVp $dst,ST" %}
9804 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9805 ins_cost(150);
9806 ins_encode( Push_Reg_DPR(src),
9807 OpcP, RegOpc(dst) );
9808 ins_pipe( fpu_reg_reg );
9809 %}
9810
9811 // Strict FP instruction biases argument before division then
9812 // biases result, to avoid double rounding of subnormals.
9813 //
9814 // scale dividend by multiplying dividend by 2^(-15360)
9815 // load divisor
9816 // divide scaled dividend by divisor
9817 // rescale quotient by 2^(15360)
9818 //
9819 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9820 predicate (UseSSE<=1);
9821 match(Set dst (DivD dst src));
9822 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9823 ins_cost(01);
9824
9825 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9826 "DMULp $dst,ST\n\t"
9827 "FLD $src\n\t"
9828 "FDIVp $dst,ST\n\t"
9829 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9830 "DMULp $dst,ST\n\t" %}
9831 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9832 ins_encode( strictfp_bias1(dst),
9833 Push_Reg_DPR(src),
9834 OpcP, RegOpc(dst),
9835 strictfp_bias2(dst) );
9836 ins_pipe( fpu_reg_reg );
9837 %}
9838
9839 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9840 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9841 match(Set dst (RoundDouble (DivD src1 src2)));
9842
9843 format %{ "FLD $src1\n\t"
9844 "FDIV ST,$src2\n\t"
9845 "FSTP_D $dst\t# D-round" %}
9846 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9847 ins_encode( Push_Reg_DPR(src1),
9848 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9849 ins_pipe( fpu_mem_reg_reg );
9850 %}
9851
9852
9853 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9854 predicate(UseSSE<=1);
9855 match(Set dst (ModD dst src));
9856 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9857
9858 format %{ "DMOD $dst,$src" %}
9859 ins_cost(250);
9860 ins_encode(Push_Reg_Mod_DPR(dst, src),
9861 emitModDPR(),
9862 Push_Result_Mod_DPR(src),
9863 Pop_Reg_DPR(dst));
9864 ins_pipe( pipe_slow );
9865 %}
9866
9867 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9868 predicate(UseSSE>=2);
9869 match(Set dst (ModD src0 src1));
9870 effect(KILL rax, KILL cr);
9871
9872 format %{ "SUB ESP,8\t # DMOD\n"
9873 "\tMOVSD [ESP+0],$src1\n"
9874 "\tFLD_D [ESP+0]\n"
9875 "\tMOVSD [ESP+0],$src0\n"
9876 "\tFLD_D [ESP+0]\n"
9877 "loop:\tFPREM\n"
9878 "\tFWAIT\n"
9879 "\tFNSTSW AX\n"
9880 "\tSAHF\n"
9881 "\tJP loop\n"
9882 "\tFSTP_D [ESP+0]\n"
9883 "\tMOVSD $dst,[ESP+0]\n"
9884 "\tADD ESP,8\n"
9885 "\tFSTP ST0\t # Restore FPU Stack"
9886 %}
9887 ins_cost(250);
9888 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9889 ins_pipe( pipe_slow );
9890 %}
9891
9892 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9893 predicate (UseSSE<=1);
9894 match(Set dst (SinD src));
9895 ins_cost(1800);
9896 format %{ "DSIN $dst" %}
9897 opcode(0xD9, 0xFE);
9898 ins_encode( OpcP, OpcS );
9899 ins_pipe( pipe_slow );
9900 %}
9901
9902 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9903 predicate (UseSSE>=2);
9904 match(Set dst (SinD dst));
9905 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9906 ins_cost(1800);
9907 format %{ "DSIN $dst" %}
9908 opcode(0xD9, 0xFE);
9909 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9910 ins_pipe( pipe_slow );
9911 %}
9912
9913 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9914 predicate (UseSSE<=1);
9915 match(Set dst (CosD src));
9916 ins_cost(1800);
9917 format %{ "DCOS $dst" %}
9918 opcode(0xD9, 0xFF);
9919 ins_encode( OpcP, OpcS );
9920 ins_pipe( pipe_slow );
9921 %}
9922
9923 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9924 predicate (UseSSE>=2);
9925 match(Set dst (CosD dst));
9926 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9927 ins_cost(1800);
9928 format %{ "DCOS $dst" %}
9929 opcode(0xD9, 0xFF);
9930 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9931 ins_pipe( pipe_slow );
9932 %}
9933
9934 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9935 predicate (UseSSE<=1);
9936 match(Set dst(TanD src));
9937 format %{ "DTAN $dst" %}
9938 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9939 Opcode(0xDD), Opcode(0xD8)); // fstp st
9940 ins_pipe( pipe_slow );
9941 %}
9942
9943 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9944 predicate (UseSSE>=2);
9945 match(Set dst(TanD dst));
9946 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9947 format %{ "DTAN $dst" %}
9948 ins_encode( Push_SrcD(dst),
9949 Opcode(0xD9), Opcode(0xF2), // fptan
9950 Opcode(0xDD), Opcode(0xD8), // fstp st
9951 Push_ResultD(dst) );
9952 ins_pipe( pipe_slow );
9953 %}
9954
9955 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9956 predicate (UseSSE<=1);
9957 match(Set dst(AtanD dst src));
9958 format %{ "DATA $dst,$src" %}
9959 opcode(0xD9, 0xF3);
9960 ins_encode( Push_Reg_DPR(src),
9961 OpcP, OpcS, RegOpc(dst) );
9962 ins_pipe( pipe_slow );
9963 %}
9964
9965 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9966 predicate (UseSSE>=2);
9967 match(Set dst(AtanD dst src));
9968 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9969 format %{ "DATA $dst,$src" %}
9970 opcode(0xD9, 0xF3);
9971 ins_encode( Push_SrcD(src),
9972 OpcP, OpcS, Push_ResultD(dst) );
9973 ins_pipe( pipe_slow );
9974 %}
9975
9976 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9977 predicate (UseSSE<=1);
9978 match(Set dst (SqrtD src));
9979 format %{ "DSQRT $dst,$src" %}
9980 opcode(0xFA, 0xD9);
9981 ins_encode( Push_Reg_DPR(src),
9982 OpcS, OpcP, Pop_Reg_DPR(dst) );
9983 ins_pipe( pipe_slow );
9984 %}
9985
9986 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9987 predicate (UseSSE<=1);
9988 match(Set Y (PowD X Y)); // Raise X to the Yth power
9989 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9990 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9991 ins_encode %{
9992 __ subptr(rsp, 8);
9993 __ fld_s($X$$reg - 1);
9994 __ fast_pow();
9995 __ addptr(rsp, 8);
9996 %}
9997 ins_pipe( pipe_slow );
9998 %}
9999
10000 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10001 predicate (UseSSE>=2);
10002 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10003 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10004 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10005 ins_encode %{
10006 __ subptr(rsp, 8);
10007 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10008 __ fld_d(Address(rsp, 0));
10009 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10010 __ fld_d(Address(rsp, 0));
10011 __ fast_pow();
10012 __ fstp_d(Address(rsp, 0));
10013 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10014 __ addptr(rsp, 8);
10015 %}
10016 ins_pipe( pipe_slow );
10017 %}
10018
10019
10020 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10021 predicate (UseSSE<=1);
10022 match(Set dpr1 (ExpD dpr1));
10023 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10024 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10025 ins_encode %{
10026 __ fast_exp();
10027 %}
10028 ins_pipe( pipe_slow );
10029 %}
10030
10031 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10032 predicate (UseSSE>=2);
10033 match(Set dst (ExpD src));
10034 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10035 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10036 ins_encode %{
10037 __ subptr(rsp, 8);
10038 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10039 __ fld_d(Address(rsp, 0));
10040 __ fast_exp();
10041 __ fstp_d(Address(rsp, 0));
10042 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10043 __ addptr(rsp, 8);
10044 %}
10045 ins_pipe( pipe_slow );
10046 %}
10047
10048 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10049 predicate (UseSSE<=1);
10050 // The source Double operand on FPU stack
10051 match(Set dst (Log10D src));
10052 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10053 // fxch ; swap ST(0) with ST(1)
10054 // fyl2x ; compute log_10(2) * log_2(x)
10055 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10056 "FXCH \n\t"
10057 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10058 %}
10059 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10060 Opcode(0xD9), Opcode(0xC9), // fxch
10061 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10062
10063 ins_pipe( pipe_slow );
10064 %}
10065
10066 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10067 predicate (UseSSE>=2);
10068 effect(KILL cr);
10069 match(Set dst (Log10D src));
10070 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10071 // fyl2x ; compute log_10(2) * log_2(x)
10072 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10073 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10074 %}
10075 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10076 Push_SrcD(src),
10077 Opcode(0xD9), Opcode(0xF1), // fyl2x
10078 Push_ResultD(dst));
10079
10080 ins_pipe( pipe_slow );
10081 %}
10082
10083 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10084 predicate (UseSSE<=1);
10085 // The source Double operand on FPU stack
10086 match(Set dst (LogD src));
10087 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10088 // fxch ; swap ST(0) with ST(1)
10089 // fyl2x ; compute log_e(2) * log_2(x)
10090 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10091 "FXCH \n\t"
10092 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10093 %}
10094 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10095 Opcode(0xD9), Opcode(0xC9), // fxch
10096 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10097
10098 ins_pipe( pipe_slow );
10099 %}
10100
10101 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10102 predicate (UseSSE>=2);
10103 effect(KILL cr);
10104 // The source and result Double operands in XMM registers
10105 match(Set dst (LogD src));
10106 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10107 // fyl2x ; compute log_e(2) * log_2(x)
10108 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10109 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10110 %}
10111 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10112 Push_SrcD(src),
10113 Opcode(0xD9), Opcode(0xF1), // fyl2x
10114 Push_ResultD(dst));
10115 ins_pipe( pipe_slow );
10116 %}
10117
10118 //-------------Float Instructions-------------------------------
10119 // Float Math
10120
10121 // Code for float compare:
10122 // fcompp();
10123 // fwait(); fnstsw_ax();
10124 // sahf();
10125 // movl(dst, unordered_result);
10126 // jcc(Assembler::parity, exit);
10127 // movl(dst, less_result);
10128 // jcc(Assembler::below, exit);
10129 // movl(dst, equal_result);
10130 // jcc(Assembler::equal, exit);
10131 // movl(dst, greater_result);
10132 // exit:
10133
10134 // P6 version of float compare, sets condition codes in EFLAGS
10135 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10136 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10137 match(Set cr (CmpF src1 src2));
10138 effect(KILL rax);
10139 ins_cost(150);
10140 format %{ "FLD $src1\n\t"
10141 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10142 "JNP exit\n\t"
10143 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10144 "SAHF\n"
10145 "exit:\tNOP // avoid branch to branch" %}
10146 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10147 ins_encode( Push_Reg_DPR(src1),
10148 OpcP, RegOpc(src2),
10149 cmpF_P6_fixup );
10150 ins_pipe( pipe_slow );
10151 %}
10152
10153 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10154 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10155 match(Set cr (CmpF src1 src2));
10156 ins_cost(100);
10157 format %{ "FLD $src1\n\t"
10158 "FUCOMIP ST,$src2 // P6 instruction" %}
10159 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10160 ins_encode( Push_Reg_DPR(src1),
10161 OpcP, RegOpc(src2));
10162 ins_pipe( pipe_slow );
10163 %}
10164
10165
10166 // Compare & branch
10167 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10168 predicate(UseSSE == 0);
10169 match(Set cr (CmpF src1 src2));
10170 effect(KILL rax);
10171 ins_cost(200);
10172 format %{ "FLD $src1\n\t"
10173 "FCOMp $src2\n\t"
10174 "FNSTSW AX\n\t"
10175 "TEST AX,0x400\n\t"
10176 "JZ,s flags\n\t"
10177 "MOV AH,1\t# unordered treat as LT\n"
10178 "flags:\tSAHF" %}
10179 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10180 ins_encode( Push_Reg_DPR(src1),
10181 OpcP, RegOpc(src2),
10182 fpu_flags);
10183 ins_pipe( pipe_slow );
10184 %}
10185
10186 // Compare vs zero into -1,0,1
10187 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10188 predicate(UseSSE == 0);
10189 match(Set dst (CmpF3 src1 zero));
10190 effect(KILL cr, KILL rax);
10191 ins_cost(280);
10192 format %{ "FTSTF $dst,$src1" %}
10193 opcode(0xE4, 0xD9);
10194 ins_encode( Push_Reg_DPR(src1),
10195 OpcS, OpcP, PopFPU,
10196 CmpF_Result(dst));
10197 ins_pipe( pipe_slow );
10198 %}
10199
10200 // Compare into -1,0,1
10201 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10202 predicate(UseSSE == 0);
10203 match(Set dst (CmpF3 src1 src2));
10204 effect(KILL cr, KILL rax);
10205 ins_cost(300);
10206 format %{ "FCMPF $dst,$src1,$src2" %}
10207 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10208 ins_encode( Push_Reg_DPR(src1),
10209 OpcP, RegOpc(src2),
10210 CmpF_Result(dst));
10211 ins_pipe( pipe_slow );
10212 %}
10213
10214 // float compare and set condition codes in EFLAGS by XMM regs
10215 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10216 predicate(UseSSE>=1);
10217 match(Set cr (CmpF src1 src2));
10218 ins_cost(145);
10219 format %{ "UCOMISS $src1,$src2\n\t"
10220 "JNP,s exit\n\t"
10221 "PUSHF\t# saw NaN, set CF\n\t"
10222 "AND [rsp], #0xffffff2b\n\t"
10223 "POPF\n"
10224 "exit:" %}
10225 ins_encode %{
10226 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10227 emit_cmpfp_fixup(_masm);
10228 %}
10229 ins_pipe( pipe_slow );
10230 %}
10231
10232 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10233 predicate(UseSSE>=1);
10234 match(Set cr (CmpF src1 src2));
10235 ins_cost(100);
10236 format %{ "UCOMISS $src1,$src2" %}
10237 ins_encode %{
10238 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10239 %}
10240 ins_pipe( pipe_slow );
10241 %}
10242
10243 // float compare and set condition codes in EFLAGS by XMM regs
10244 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10245 predicate(UseSSE>=1);
10246 match(Set cr (CmpF src1 (LoadF src2)));
10247 ins_cost(165);
10248 format %{ "UCOMISS $src1,$src2\n\t"
10249 "JNP,s exit\n\t"
10250 "PUSHF\t# saw NaN, set CF\n\t"
10251 "AND [rsp], #0xffffff2b\n\t"
10252 "POPF\n"
10253 "exit:" %}
10254 ins_encode %{
10255 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10256 emit_cmpfp_fixup(_masm);
10257 %}
10258 ins_pipe( pipe_slow );
10259 %}
10260
10261 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10262 predicate(UseSSE>=1);
10263 match(Set cr (CmpF src1 (LoadF src2)));
10264 ins_cost(100);
10265 format %{ "UCOMISS $src1,$src2" %}
10266 ins_encode %{
10267 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10268 %}
10269 ins_pipe( pipe_slow );
10270 %}
10271
10272 // Compare into -1,0,1 in XMM
10273 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10274 predicate(UseSSE>=1);
10275 match(Set dst (CmpF3 src1 src2));
10276 effect(KILL cr);
10277 ins_cost(255);
10278 format %{ "UCOMISS $src1, $src2\n\t"
10279 "MOV $dst, #-1\n\t"
10280 "JP,s done\n\t"
10281 "JB,s done\n\t"
10282 "SETNE $dst\n\t"
10283 "MOVZB $dst, $dst\n"
10284 "done:" %}
10285 ins_encode %{
10286 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10287 emit_cmpfp3(_masm, $dst$$Register);
10288 %}
10289 ins_pipe( pipe_slow );
10290 %}
10291
10292 // Compare into -1,0,1 in XMM and memory
10293 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10294 predicate(UseSSE>=1);
10295 match(Set dst (CmpF3 src1 (LoadF src2)));
10296 effect(KILL cr);
10297 ins_cost(275);
10298 format %{ "UCOMISS $src1, $src2\n\t"
10299 "MOV $dst, #-1\n\t"
10300 "JP,s done\n\t"
10301 "JB,s done\n\t"
10302 "SETNE $dst\n\t"
10303 "MOVZB $dst, $dst\n"
10304 "done:" %}
10305 ins_encode %{
10306 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10307 emit_cmpfp3(_masm, $dst$$Register);
10308 %}
10309 ins_pipe( pipe_slow );
10310 %}
10311
10312 // Spill to obtain 24-bit precision
10313 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10314 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10315 match(Set dst (SubF src1 src2));
10316
10317 format %{ "FSUB $dst,$src1 - $src2" %}
10318 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10319 ins_encode( Push_Reg_FPR(src1),
10320 OpcReg_FPR(src2),
10321 Pop_Mem_FPR(dst) );
10322 ins_pipe( fpu_mem_reg_reg );
10323 %}
10324 //
10325 // This instruction does not round to 24-bits
10326 instruct subFPR_reg(regFPR dst, regFPR src) %{
10327 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10328 match(Set dst (SubF dst src));
10329
10330 format %{ "FSUB $dst,$src" %}
10331 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10332 ins_encode( Push_Reg_FPR(src),
10333 OpcP, RegOpc(dst) );
10334 ins_pipe( fpu_reg_reg );
10335 %}
10336
10337 // Spill to obtain 24-bit precision
10338 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10339 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10340 match(Set dst (AddF src1 src2));
10341
10342 format %{ "FADD $dst,$src1,$src2" %}
10343 opcode(0xD8, 0x0); /* D8 C0+i */
10344 ins_encode( Push_Reg_FPR(src2),
10345 OpcReg_FPR(src1),
10346 Pop_Mem_FPR(dst) );
10347 ins_pipe( fpu_mem_reg_reg );
10348 %}
10349 //
10350 // This instruction does not round to 24-bits
10351 instruct addFPR_reg(regFPR dst, regFPR src) %{
10352 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10353 match(Set dst (AddF dst src));
10354
10355 format %{ "FLD $src\n\t"
10356 "FADDp $dst,ST" %}
10357 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10358 ins_encode( Push_Reg_FPR(src),
10359 OpcP, RegOpc(dst) );
10360 ins_pipe( fpu_reg_reg );
10361 %}
10362
10363 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10364 predicate(UseSSE==0);
10365 match(Set dst (AbsF src));
10366 ins_cost(100);
10367 format %{ "FABS" %}
10368 opcode(0xE1, 0xD9);
10369 ins_encode( OpcS, OpcP );
10370 ins_pipe( fpu_reg_reg );
10371 %}
10372
10373 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10374 predicate(UseSSE==0);
10375 match(Set dst (NegF src));
10376 ins_cost(100);
10377 format %{ "FCHS" %}
10378 opcode(0xE0, 0xD9);
10379 ins_encode( OpcS, OpcP );
10380 ins_pipe( fpu_reg_reg );
10381 %}
10382
10383 // Cisc-alternate to addFPR_reg
10384 // Spill to obtain 24-bit precision
10385 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10386 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10387 match(Set dst (AddF src1 (LoadF src2)));
10388
10389 format %{ "FLD $src2\n\t"
10390 "FADD ST,$src1\n\t"
10391 "FSTP_S $dst" %}
10392 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10393 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10394 OpcReg_FPR(src1),
10395 Pop_Mem_FPR(dst) );
10396 ins_pipe( fpu_mem_reg_mem );
10397 %}
10398 //
10399 // Cisc-alternate to addFPR_reg
10400 // This instruction does not round to 24-bits
10401 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10402 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10403 match(Set dst (AddF dst (LoadF src)));
10404
10405 format %{ "FADD $dst,$src" %}
10406 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10407 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10408 OpcP, RegOpc(dst) );
10409 ins_pipe( fpu_reg_mem );
10410 %}
10411
10412 // // Following two instructions for _222_mpegaudio
10413 // Spill to obtain 24-bit precision
10414 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10415 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10416 match(Set dst (AddF src1 src2));
10417
10418 format %{ "FADD $dst,$src1,$src2" %}
10419 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10420 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10421 OpcReg_FPR(src2),
10422 Pop_Mem_FPR(dst) );
10423 ins_pipe( fpu_mem_reg_mem );
10424 %}
10425
10426 // Cisc-spill variant
10427 // Spill to obtain 24-bit precision
10428 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10429 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10430 match(Set dst (AddF src1 (LoadF src2)));
10431
10432 format %{ "FADD $dst,$src1,$src2 cisc" %}
10433 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10434 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10435 set_instruction_start,
10436 OpcP, RMopc_Mem(secondary,src1),
10437 Pop_Mem_FPR(dst) );
10438 ins_pipe( fpu_mem_mem_mem );
10439 %}
10440
10441 // Spill to obtain 24-bit precision
10442 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10443 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10444 match(Set dst (AddF src1 src2));
10445
10446 format %{ "FADD $dst,$src1,$src2" %}
10447 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10448 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10449 set_instruction_start,
10450 OpcP, RMopc_Mem(secondary,src1),
10451 Pop_Mem_FPR(dst) );
10452 ins_pipe( fpu_mem_mem_mem );
10453 %}
10454
10455
10456 // Spill to obtain 24-bit precision
10457 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10458 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10459 match(Set dst (AddF src con));
10460 format %{ "FLD $src\n\t"
10461 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10462 "FSTP_S $dst" %}
10463 ins_encode %{
10464 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10465 __ fadd_s($constantaddress($con));
10466 __ fstp_s(Address(rsp, $dst$$disp));
10467 %}
10468 ins_pipe(fpu_mem_reg_con);
10469 %}
10470 //
10471 // This instruction does not round to 24-bits
10472 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10473 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10474 match(Set dst (AddF src con));
10475 format %{ "FLD $src\n\t"
10476 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10477 "FSTP $dst" %}
10478 ins_encode %{
10479 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10480 __ fadd_s($constantaddress($con));
10481 __ fstp_d($dst$$reg);
10482 %}
10483 ins_pipe(fpu_reg_reg_con);
10484 %}
10485
10486 // Spill to obtain 24-bit precision
10487 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10488 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10489 match(Set dst (MulF src1 src2));
10490
10491 format %{ "FLD $src1\n\t"
10492 "FMUL $src2\n\t"
10493 "FSTP_S $dst" %}
10494 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10495 ins_encode( Push_Reg_FPR(src1),
10496 OpcReg_FPR(src2),
10497 Pop_Mem_FPR(dst) );
10498 ins_pipe( fpu_mem_reg_reg );
10499 %}
10500 //
10501 // This instruction does not round to 24-bits
10502 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10503 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10504 match(Set dst (MulF src1 src2));
10505
10506 format %{ "FLD $src1\n\t"
10507 "FMUL $src2\n\t"
10508 "FSTP_S $dst" %}
10509 opcode(0xD8, 0x1); /* D8 C8+i */
10510 ins_encode( Push_Reg_FPR(src2),
10511 OpcReg_FPR(src1),
10512 Pop_Reg_FPR(dst) );
10513 ins_pipe( fpu_reg_reg_reg );
10514 %}
10515
10516
10517 // Spill to obtain 24-bit precision
10518 // Cisc-alternate to reg-reg multiply
10519 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10520 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10521 match(Set dst (MulF src1 (LoadF src2)));
10522
10523 format %{ "FLD_S $src2\n\t"
10524 "FMUL $src1\n\t"
10525 "FSTP_S $dst" %}
10526 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10527 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10528 OpcReg_FPR(src1),
10529 Pop_Mem_FPR(dst) );
10530 ins_pipe( fpu_mem_reg_mem );
10531 %}
10532 //
10533 // This instruction does not round to 24-bits
10534 // Cisc-alternate to reg-reg multiply
10535 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10536 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10537 match(Set dst (MulF src1 (LoadF src2)));
10538
10539 format %{ "FMUL $dst,$src1,$src2" %}
10540 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10541 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10542 OpcReg_FPR(src1),
10543 Pop_Reg_FPR(dst) );
10544 ins_pipe( fpu_reg_reg_mem );
10545 %}
10546
10547 // Spill to obtain 24-bit precision
10548 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10549 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10550 match(Set dst (MulF src1 src2));
10551
10552 format %{ "FMUL $dst,$src1,$src2" %}
10553 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10554 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10555 set_instruction_start,
10556 OpcP, RMopc_Mem(secondary,src1),
10557 Pop_Mem_FPR(dst) );
10558 ins_pipe( fpu_mem_mem_mem );
10559 %}
10560
10561 // Spill to obtain 24-bit precision
10562 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10563 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10564 match(Set dst (MulF src con));
10565
10566 format %{ "FLD $src\n\t"
10567 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10568 "FSTP_S $dst" %}
10569 ins_encode %{
10570 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10571 __ fmul_s($constantaddress($con));
10572 __ fstp_s(Address(rsp, $dst$$disp));
10573 %}
10574 ins_pipe(fpu_mem_reg_con);
10575 %}
10576 //
10577 // This instruction does not round to 24-bits
10578 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10579 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10580 match(Set dst (MulF src con));
10581
10582 format %{ "FLD $src\n\t"
10583 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10584 "FSTP $dst" %}
10585 ins_encode %{
10586 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10587 __ fmul_s($constantaddress($con));
10588 __ fstp_d($dst$$reg);
10589 %}
10590 ins_pipe(fpu_reg_reg_con);
10591 %}
10592
10593
10594 //
10595 // MACRO1 -- subsume unshared load into mulFPR
10596 // This instruction does not round to 24-bits
10597 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10598 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10599 match(Set dst (MulF (LoadF mem1) src));
10600
10601 format %{ "FLD $mem1 ===MACRO1===\n\t"
10602 "FMUL ST,$src\n\t"
10603 "FSTP $dst" %}
10604 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10605 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10606 OpcReg_FPR(src),
10607 Pop_Reg_FPR(dst) );
10608 ins_pipe( fpu_reg_reg_mem );
10609 %}
10610 //
10611 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10612 // This instruction does not round to 24-bits
10613 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10614 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10615 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10616 ins_cost(95);
10617
10618 format %{ "FLD $mem1 ===MACRO2===\n\t"
10619 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10620 "FADD ST,$src2\n\t"
10621 "FSTP $dst" %}
10622 opcode(0xD9); /* LoadF D9 /0 */
10623 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10624 FMul_ST_reg(src1),
10625 FAdd_ST_reg(src2),
10626 Pop_Reg_FPR(dst) );
10627 ins_pipe( fpu_reg_mem_reg_reg );
10628 %}
10629
10630 // MACRO3 -- addFPR a mulFPR
10631 // This instruction does not round to 24-bits. It is a '2-address'
10632 // instruction in that the result goes back to src2. This eliminates
10633 // a move from the macro; possibly the register allocator will have
10634 // to add it back (and maybe not).
10635 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10636 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10637 match(Set src2 (AddF (MulF src0 src1) src2));
10638
10639 format %{ "FLD $src0 ===MACRO3===\n\t"
10640 "FMUL ST,$src1\n\t"
10641 "FADDP $src2,ST" %}
10642 opcode(0xD9); /* LoadF D9 /0 */
10643 ins_encode( Push_Reg_FPR(src0),
10644 FMul_ST_reg(src1),
10645 FAddP_reg_ST(src2) );
10646 ins_pipe( fpu_reg_reg_reg );
10647 %}
10648
10649 // MACRO4 -- divFPR subFPR
10650 // This instruction does not round to 24-bits
10651 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10652 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10653 match(Set dst (DivF (SubF src2 src1) src3));
10654
10655 format %{ "FLD $src2 ===MACRO4===\n\t"
10656 "FSUB ST,$src1\n\t"
10657 "FDIV ST,$src3\n\t"
10658 "FSTP $dst" %}
10659 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10660 ins_encode( Push_Reg_FPR(src2),
10661 subFPR_divFPR_encode(src1,src3),
10662 Pop_Reg_FPR(dst) );
10663 ins_pipe( fpu_reg_reg_reg_reg );
10664 %}
10665
10666 // Spill to obtain 24-bit precision
10667 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10668 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10669 match(Set dst (DivF src1 src2));
10670
10671 format %{ "FDIV $dst,$src1,$src2" %}
10672 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10673 ins_encode( Push_Reg_FPR(src1),
10674 OpcReg_FPR(src2),
10675 Pop_Mem_FPR(dst) );
10676 ins_pipe( fpu_mem_reg_reg );
10677 %}
10678 //
10679 // This instruction does not round to 24-bits
10680 instruct divFPR_reg(regFPR dst, regFPR src) %{
10681 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10682 match(Set dst (DivF dst src));
10683
10684 format %{ "FDIV $dst,$src" %}
10685 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10686 ins_encode( Push_Reg_FPR(src),
10687 OpcP, RegOpc(dst) );
10688 ins_pipe( fpu_reg_reg );
10689 %}
10690
10691
10692 // Spill to obtain 24-bit precision
10693 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10694 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10695 match(Set dst (ModF src1 src2));
10696 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10697
10698 format %{ "FMOD $dst,$src1,$src2" %}
10699 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10700 emitModDPR(),
10701 Push_Result_Mod_DPR(src2),
10702 Pop_Mem_FPR(dst));
10703 ins_pipe( pipe_slow );
10704 %}
10705 //
10706 // This instruction does not round to 24-bits
10707 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10708 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10709 match(Set dst (ModF dst src));
10710 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10711
10712 format %{ "FMOD $dst,$src" %}
10713 ins_encode(Push_Reg_Mod_DPR(dst, src),
10714 emitModDPR(),
10715 Push_Result_Mod_DPR(src),
10716 Pop_Reg_FPR(dst));
10717 ins_pipe( pipe_slow );
10718 %}
10719
10720 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10721 predicate(UseSSE>=1);
10722 match(Set dst (ModF src0 src1));
10723 effect(KILL rax, KILL cr);
10724 format %{ "SUB ESP,4\t # FMOD\n"
10725 "\tMOVSS [ESP+0],$src1\n"
10726 "\tFLD_S [ESP+0]\n"
10727 "\tMOVSS [ESP+0],$src0\n"
10728 "\tFLD_S [ESP+0]\n"
10729 "loop:\tFPREM\n"
10730 "\tFWAIT\n"
10731 "\tFNSTSW AX\n"
10732 "\tSAHF\n"
10733 "\tJP loop\n"
10734 "\tFSTP_S [ESP+0]\n"
10735 "\tMOVSS $dst,[ESP+0]\n"
10736 "\tADD ESP,4\n"
10737 "\tFSTP ST0\t # Restore FPU Stack"
10738 %}
10739 ins_cost(250);
10740 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10741 ins_pipe( pipe_slow );
10742 %}
10743
10744
10745 //----------Arithmetic Conversion Instructions---------------------------------
10746 // The conversions operations are all Alpha sorted. Please keep it that way!
10747
10748 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10749 predicate(UseSSE==0);
10750 match(Set dst (RoundFloat src));
10751 ins_cost(125);
10752 format %{ "FST_S $dst,$src\t# F-round" %}
10753 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10754 ins_pipe( fpu_mem_reg );
10755 %}
10756
10757 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10758 predicate(UseSSE<=1);
10759 match(Set dst (RoundDouble src));
10760 ins_cost(125);
10761 format %{ "FST_D $dst,$src\t# D-round" %}
10762 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10763 ins_pipe( fpu_mem_reg );
10764 %}
10765
10766 // Force rounding to 24-bit precision and 6-bit exponent
10767 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10768 predicate(UseSSE==0);
10769 match(Set dst (ConvD2F src));
10770 format %{ "FST_S $dst,$src\t# F-round" %}
10771 expand %{
10772 roundFloat_mem_reg(dst,src);
10773 %}
10774 %}
10775
10776 // Force rounding to 24-bit precision and 6-bit exponent
10777 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10778 predicate(UseSSE==1);
10779 match(Set dst (ConvD2F src));
10780 effect( KILL cr );
10781 format %{ "SUB ESP,4\n\t"
10782 "FST_S [ESP],$src\t# F-round\n\t"
10783 "MOVSS $dst,[ESP]\n\t"
10784 "ADD ESP,4" %}
10785 ins_encode %{
10786 __ subptr(rsp, 4);
10787 if ($src$$reg != FPR1L_enc) {
10788 __ fld_s($src$$reg-1);
10789 __ fstp_s(Address(rsp, 0));
10790 } else {
10791 __ fst_s(Address(rsp, 0));
10792 }
10793 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10794 __ addptr(rsp, 4);
10795 %}
10796 ins_pipe( pipe_slow );
10797 %}
10798
10799 // Force rounding double precision to single precision
10800 instruct convD2F_reg(regF dst, regD src) %{
10801 predicate(UseSSE>=2);
10802 match(Set dst (ConvD2F src));
10803 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10804 ins_encode %{
10805 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10806 %}
10807 ins_pipe( pipe_slow );
10808 %}
10809
10810 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10811 predicate(UseSSE==0);
10812 match(Set dst (ConvF2D src));
10813 format %{ "FST_S $dst,$src\t# D-round" %}
10814 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10815 ins_pipe( fpu_reg_reg );
10816 %}
10817
10818 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10819 predicate(UseSSE==1);
10820 match(Set dst (ConvF2D src));
10821 format %{ "FST_D $dst,$src\t# D-round" %}
10822 expand %{
10823 roundDouble_mem_reg(dst,src);
10824 %}
10825 %}
10826
10827 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10828 predicate(UseSSE==1);
10829 match(Set dst (ConvF2D src));
10830 effect( KILL cr );
10831 format %{ "SUB ESP,4\n\t"
10832 "MOVSS [ESP] $src\n\t"
10833 "FLD_S [ESP]\n\t"
10834 "ADD ESP,4\n\t"
10835 "FSTP $dst\t# D-round" %}
10836 ins_encode %{
10837 __ subptr(rsp, 4);
10838 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10839 __ fld_s(Address(rsp, 0));
10840 __ addptr(rsp, 4);
10841 __ fstp_d($dst$$reg);
10842 %}
10843 ins_pipe( pipe_slow );
10844 %}
10845
10846 instruct convF2D_reg(regD dst, regF src) %{
10847 predicate(UseSSE>=2);
10848 match(Set dst (ConvF2D src));
10849 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10850 ins_encode %{
10851 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10852 %}
10853 ins_pipe( pipe_slow );
10854 %}
10855
10856 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10857 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10858 predicate(UseSSE<=1);
10859 match(Set dst (ConvD2I src));
10860 effect( KILL tmp, KILL cr );
10861 format %{ "FLD $src\t# Convert double to int \n\t"
10862 "FLDCW trunc mode\n\t"
10863 "SUB ESP,4\n\t"
10864 "FISTp [ESP + #0]\n\t"
10865 "FLDCW std/24-bit mode\n\t"
10866 "POP EAX\n\t"
10867 "CMP EAX,0x80000000\n\t"
10868 "JNE,s fast\n\t"
10869 "FLD_D $src\n\t"
10870 "CALL d2i_wrapper\n"
10871 "fast:" %}
10872 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10873 ins_pipe( pipe_slow );
10874 %}
10875
10876 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10877 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10878 predicate(UseSSE>=2);
10879 match(Set dst (ConvD2I src));
10880 effect( KILL tmp, KILL cr );
10881 format %{ "CVTTSD2SI $dst, $src\n\t"
10882 "CMP $dst,0x80000000\n\t"
10883 "JNE,s fast\n\t"
10884 "SUB ESP, 8\n\t"
10885 "MOVSD [ESP], $src\n\t"
10886 "FLD_D [ESP]\n\t"
10887 "ADD ESP, 8\n\t"
10888 "CALL d2i_wrapper\n"
10889 "fast:" %}
10890 ins_encode %{
10891 Label fast;
10892 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10893 __ cmpl($dst$$Register, 0x80000000);
10894 __ jccb(Assembler::notEqual, fast);
10895 __ subptr(rsp, 8);
10896 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10897 __ fld_d(Address(rsp, 0));
10898 __ addptr(rsp, 8);
10899 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10900 __ bind(fast);
10901 %}
10902 ins_pipe( pipe_slow );
10903 %}
10904
10905 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10906 predicate(UseSSE<=1);
10907 match(Set dst (ConvD2L src));
10908 effect( KILL cr );
10909 format %{ "FLD $src\t# Convert double to long\n\t"
10910 "FLDCW trunc mode\n\t"
10911 "SUB ESP,8\n\t"
10912 "FISTp [ESP + #0]\n\t"
10913 "FLDCW std/24-bit mode\n\t"
10914 "POP EAX\n\t"
10915 "POP EDX\n\t"
10916 "CMP EDX,0x80000000\n\t"
10917 "JNE,s fast\n\t"
10918 "TEST EAX,EAX\n\t"
10919 "JNE,s fast\n\t"
10920 "FLD $src\n\t"
10921 "CALL d2l_wrapper\n"
10922 "fast:" %}
10923 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10924 ins_pipe( pipe_slow );
10925 %}
10926
10927 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10928 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10929 predicate (UseSSE>=2);
10930 match(Set dst (ConvD2L src));
10931 effect( KILL cr );
10932 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10933 "MOVSD [ESP],$src\n\t"
10934 "FLD_D [ESP]\n\t"
10935 "FLDCW trunc mode\n\t"
10936 "FISTp [ESP + #0]\n\t"
10937 "FLDCW std/24-bit mode\n\t"
10938 "POP EAX\n\t"
10939 "POP EDX\n\t"
10940 "CMP EDX,0x80000000\n\t"
10941 "JNE,s fast\n\t"
10942 "TEST EAX,EAX\n\t"
10943 "JNE,s fast\n\t"
10944 "SUB ESP,8\n\t"
10945 "MOVSD [ESP],$src\n\t"
10946 "FLD_D [ESP]\n\t"
10947 "ADD ESP,8\n\t"
10948 "CALL d2l_wrapper\n"
10949 "fast:" %}
10950 ins_encode %{
10951 Label fast;
10952 __ subptr(rsp, 8);
10953 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10954 __ fld_d(Address(rsp, 0));
10955 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10956 __ fistp_d(Address(rsp, 0));
10957 // Restore the rounding mode, mask the exception
10958 if (Compile::current()->in_24_bit_fp_mode()) {
10959 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10960 } else {
10961 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10962 }
10963 // Load the converted long, adjust CPU stack
10964 __ pop(rax);
10965 __ pop(rdx);
10966 __ cmpl(rdx, 0x80000000);
10967 __ jccb(Assembler::notEqual, fast);
10968 __ testl(rax, rax);
10969 __ jccb(Assembler::notEqual, fast);
10970 __ subptr(rsp, 8);
10971 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10972 __ fld_d(Address(rsp, 0));
10973 __ addptr(rsp, 8);
10974 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10975 __ bind(fast);
10976 %}
10977 ins_pipe( pipe_slow );
10978 %}
10979
10980 // Convert a double to an int. Java semantics require we do complex
10981 // manglations in the corner cases. So we set the rounding mode to
10982 // 'zero', store the darned double down as an int, and reset the
10983 // rounding mode to 'nearest'. The hardware stores a flag value down
10984 // if we would overflow or converted a NAN; we check for this and
10985 // and go the slow path if needed.
10986 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10987 predicate(UseSSE==0);
10988 match(Set dst (ConvF2I src));
10989 effect( KILL tmp, KILL cr );
10990 format %{ "FLD $src\t# Convert float to int \n\t"
10991 "FLDCW trunc mode\n\t"
10992 "SUB ESP,4\n\t"
10993 "FISTp [ESP + #0]\n\t"
10994 "FLDCW std/24-bit mode\n\t"
10995 "POP EAX\n\t"
10996 "CMP EAX,0x80000000\n\t"
10997 "JNE,s fast\n\t"
10998 "FLD $src\n\t"
10999 "CALL d2i_wrapper\n"
11000 "fast:" %}
11001 // DPR2I_encoding works for FPR2I
11002 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11003 ins_pipe( pipe_slow );
11004 %}
11005
11006 // Convert a float in xmm to an int reg.
11007 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11008 predicate(UseSSE>=1);
11009 match(Set dst (ConvF2I src));
11010 effect( KILL tmp, KILL cr );
11011 format %{ "CVTTSS2SI $dst, $src\n\t"
11012 "CMP $dst,0x80000000\n\t"
11013 "JNE,s fast\n\t"
11014 "SUB ESP, 4\n\t"
11015 "MOVSS [ESP], $src\n\t"
11016 "FLD [ESP]\n\t"
11017 "ADD ESP, 4\n\t"
11018 "CALL d2i_wrapper\n"
11019 "fast:" %}
11020 ins_encode %{
11021 Label fast;
11022 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11023 __ cmpl($dst$$Register, 0x80000000);
11024 __ jccb(Assembler::notEqual, fast);
11025 __ subptr(rsp, 4);
11026 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11027 __ fld_s(Address(rsp, 0));
11028 __ addptr(rsp, 4);
11029 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11030 __ bind(fast);
11031 %}
11032 ins_pipe( pipe_slow );
11033 %}
11034
11035 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11036 predicate(UseSSE==0);
11037 match(Set dst (ConvF2L src));
11038 effect( KILL cr );
11039 format %{ "FLD $src\t# Convert float to long\n\t"
11040 "FLDCW trunc mode\n\t"
11041 "SUB ESP,8\n\t"
11042 "FISTp [ESP + #0]\n\t"
11043 "FLDCW std/24-bit mode\n\t"
11044 "POP EAX\n\t"
11045 "POP EDX\n\t"
11046 "CMP EDX,0x80000000\n\t"
11047 "JNE,s fast\n\t"
11048 "TEST EAX,EAX\n\t"
11049 "JNE,s fast\n\t"
11050 "FLD $src\n\t"
11051 "CALL d2l_wrapper\n"
11052 "fast:" %}
11053 // DPR2L_encoding works for FPR2L
11054 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11055 ins_pipe( pipe_slow );
11056 %}
11057
11058 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11059 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11060 predicate (UseSSE>=1);
11061 match(Set dst (ConvF2L src));
11062 effect( KILL cr );
11063 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11064 "MOVSS [ESP],$src\n\t"
11065 "FLD_S [ESP]\n\t"
11066 "FLDCW trunc mode\n\t"
11067 "FISTp [ESP + #0]\n\t"
11068 "FLDCW std/24-bit mode\n\t"
11069 "POP EAX\n\t"
11070 "POP EDX\n\t"
11071 "CMP EDX,0x80000000\n\t"
11072 "JNE,s fast\n\t"
11073 "TEST EAX,EAX\n\t"
11074 "JNE,s fast\n\t"
11075 "SUB ESP,4\t# Convert float to long\n\t"
11076 "MOVSS [ESP],$src\n\t"
11077 "FLD_S [ESP]\n\t"
11078 "ADD ESP,4\n\t"
11079 "CALL d2l_wrapper\n"
11080 "fast:" %}
11081 ins_encode %{
11082 Label fast;
11083 __ subptr(rsp, 8);
11084 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11085 __ fld_s(Address(rsp, 0));
11086 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11087 __ fistp_d(Address(rsp, 0));
11088 // Restore the rounding mode, mask the exception
11089 if (Compile::current()->in_24_bit_fp_mode()) {
11090 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11091 } else {
11092 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11093 }
11094 // Load the converted long, adjust CPU stack
11095 __ pop(rax);
11096 __ pop(rdx);
11097 __ cmpl(rdx, 0x80000000);
11098 __ jccb(Assembler::notEqual, fast);
11099 __ testl(rax, rax);
11100 __ jccb(Assembler::notEqual, fast);
11101 __ subptr(rsp, 4);
11102 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11103 __ fld_s(Address(rsp, 0));
11104 __ addptr(rsp, 4);
11105 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11106 __ bind(fast);
11107 %}
11108 ins_pipe( pipe_slow );
11109 %}
11110
11111 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11112 predicate( UseSSE<=1 );
11113 match(Set dst (ConvI2D src));
11114 format %{ "FILD $src\n\t"
11115 "FSTP $dst" %}
11116 opcode(0xDB, 0x0); /* DB /0 */
11117 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11118 ins_pipe( fpu_reg_mem );
11119 %}
11120
11121 instruct convI2D_reg(regD dst, rRegI src) %{
11122 predicate( UseSSE>=2 && !UseXmmI2D );
11123 match(Set dst (ConvI2D src));
11124 format %{ "CVTSI2SD $dst,$src" %}
11125 ins_encode %{
11126 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11127 %}
11128 ins_pipe( pipe_slow );
11129 %}
11130
11131 instruct convI2D_mem(regD dst, memory mem) %{
11132 predicate( UseSSE>=2 );
11133 match(Set dst (ConvI2D (LoadI mem)));
11134 format %{ "CVTSI2SD $dst,$mem" %}
11135 ins_encode %{
11136 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11137 %}
11138 ins_pipe( pipe_slow );
11139 %}
11140
11141 instruct convXI2D_reg(regD dst, rRegI src)
11142 %{
11143 predicate( UseSSE>=2 && UseXmmI2D );
11144 match(Set dst (ConvI2D src));
11145
11146 format %{ "MOVD $dst,$src\n\t"
11147 "CVTDQ2PD $dst,$dst\t# i2d" %}
11148 ins_encode %{
11149 __ movdl($dst$$XMMRegister, $src$$Register);
11150 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11151 %}
11152 ins_pipe(pipe_slow); // XXX
11153 %}
11154
11155 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11156 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11157 match(Set dst (ConvI2D (LoadI mem)));
11158 format %{ "FILD $mem\n\t"
11159 "FSTP $dst" %}
11160 opcode(0xDB); /* DB /0 */
11161 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11162 Pop_Reg_DPR(dst));
11163 ins_pipe( fpu_reg_mem );
11164 %}
11165
11166 // Convert a byte to a float; no rounding step needed.
11167 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11168 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11169 match(Set dst (ConvI2F src));
11170 format %{ "FILD $src\n\t"
11171 "FSTP $dst" %}
11172
11173 opcode(0xDB, 0x0); /* DB /0 */
11174 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11175 ins_pipe( fpu_reg_mem );
11176 %}
11177
11178 // In 24-bit mode, force exponent rounding by storing back out
11179 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11180 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11181 match(Set dst (ConvI2F src));
11182 ins_cost(200);
11183 format %{ "FILD $src\n\t"
11184 "FSTP_S $dst" %}
11185 opcode(0xDB, 0x0); /* DB /0 */
11186 ins_encode( Push_Mem_I(src),
11187 Pop_Mem_FPR(dst));
11188 ins_pipe( fpu_mem_mem );
11189 %}
11190
11191 // In 24-bit mode, force exponent rounding by storing back out
11192 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11193 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11194 match(Set dst (ConvI2F (LoadI mem)));
11195 ins_cost(200);
11196 format %{ "FILD $mem\n\t"
11197 "FSTP_S $dst" %}
11198 opcode(0xDB); /* DB /0 */
11199 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11200 Pop_Mem_FPR(dst));
11201 ins_pipe( fpu_mem_mem );
11202 %}
11203
11204 // This instruction does not round to 24-bits
11205 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11206 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11207 match(Set dst (ConvI2F src));
11208 format %{ "FILD $src\n\t"
11209 "FSTP $dst" %}
11210 opcode(0xDB, 0x0); /* DB /0 */
11211 ins_encode( Push_Mem_I(src),
11212 Pop_Reg_FPR(dst));
11213 ins_pipe( fpu_reg_mem );
11214 %}
11215
11216 // This instruction does not round to 24-bits
11217 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11218 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11219 match(Set dst (ConvI2F (LoadI mem)));
11220 format %{ "FILD $mem\n\t"
11221 "FSTP $dst" %}
11222 opcode(0xDB); /* DB /0 */
11223 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11224 Pop_Reg_FPR(dst));
11225 ins_pipe( fpu_reg_mem );
11226 %}
11227
11228 // Convert an int to a float in xmm; no rounding step needed.
11229 instruct convI2F_reg(regF dst, rRegI src) %{
11230 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11231 match(Set dst (ConvI2F src));
11232 format %{ "CVTSI2SS $dst, $src" %}
11233 ins_encode %{
11234 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11235 %}
11236 ins_pipe( pipe_slow );
11237 %}
11238
11239 instruct convXI2F_reg(regF dst, rRegI src)
11240 %{
11241 predicate( UseSSE>=2 && UseXmmI2F );
11242 match(Set dst (ConvI2F src));
11243
11244 format %{ "MOVD $dst,$src\n\t"
11245 "CVTDQ2PS $dst,$dst\t# i2f" %}
11246 ins_encode %{
11247 __ movdl($dst$$XMMRegister, $src$$Register);
11248 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11249 %}
11250 ins_pipe(pipe_slow); // XXX
11251 %}
11252
11253 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11254 match(Set dst (ConvI2L src));
11255 effect(KILL cr);
11256 ins_cost(375);
11257 format %{ "MOV $dst.lo,$src\n\t"
11258 "MOV $dst.hi,$src\n\t"
11259 "SAR $dst.hi,31" %}
11260 ins_encode(convert_int_long(dst,src));
11261 ins_pipe( ialu_reg_reg_long );
11262 %}
11263
11264 // Zero-extend convert int to long
11265 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11266 match(Set dst (AndL (ConvI2L src) mask) );
11267 effect( KILL flags );
11268 ins_cost(250);
11269 format %{ "MOV $dst.lo,$src\n\t"
11270 "XOR $dst.hi,$dst.hi" %}
11271 opcode(0x33); // XOR
11272 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11273 ins_pipe( ialu_reg_reg_long );
11274 %}
11275
11276 // Zero-extend long
11277 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11278 match(Set dst (AndL src mask) );
11279 effect( KILL flags );
11280 ins_cost(250);
11281 format %{ "MOV $dst.lo,$src.lo\n\t"
11282 "XOR $dst.hi,$dst.hi\n\t" %}
11283 opcode(0x33); // XOR
11284 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11285 ins_pipe( ialu_reg_reg_long );
11286 %}
11287
11288 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11289 predicate (UseSSE<=1);
11290 match(Set dst (ConvL2D src));
11291 effect( KILL cr );
11292 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11293 "PUSH $src.lo\n\t"
11294 "FILD ST,[ESP + #0]\n\t"
11295 "ADD ESP,8\n\t"
11296 "FSTP_D $dst\t# D-round" %}
11297 opcode(0xDF, 0x5); /* DF /5 */
11298 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11299 ins_pipe( pipe_slow );
11300 %}
11301
11302 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11303 predicate (UseSSE>=2);
11304 match(Set dst (ConvL2D src));
11305 effect( KILL cr );
11306 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11307 "PUSH $src.lo\n\t"
11308 "FILD_D [ESP]\n\t"
11309 "FSTP_D [ESP]\n\t"
11310 "MOVSD $dst,[ESP]\n\t"
11311 "ADD ESP,8" %}
11312 opcode(0xDF, 0x5); /* DF /5 */
11313 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11314 ins_pipe( pipe_slow );
11315 %}
11316
11317 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11318 predicate (UseSSE>=1);
11319 match(Set dst (ConvL2F src));
11320 effect( KILL cr );
11321 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11322 "PUSH $src.lo\n\t"
11323 "FILD_D [ESP]\n\t"
11324 "FSTP_S [ESP]\n\t"
11325 "MOVSS $dst,[ESP]\n\t"
11326 "ADD ESP,8" %}
11327 opcode(0xDF, 0x5); /* DF /5 */
11328 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11329 ins_pipe( pipe_slow );
11330 %}
11331
11332 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11333 match(Set dst (ConvL2F src));
11334 effect( KILL cr );
11335 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11336 "PUSH $src.lo\n\t"
11337 "FILD ST,[ESP + #0]\n\t"
11338 "ADD ESP,8\n\t"
11339 "FSTP_S $dst\t# F-round" %}
11340 opcode(0xDF, 0x5); /* DF /5 */
11341 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11342 ins_pipe( pipe_slow );
11343 %}
11344
11345 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11346 match(Set dst (ConvL2I src));
11347 effect( DEF dst, USE src );
11348 format %{ "MOV $dst,$src.lo" %}
11349 ins_encode(enc_CopyL_Lo(dst,src));
11350 ins_pipe( ialu_reg_reg );
11351 %}
11352
11353
11354 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11355 match(Set dst (MoveF2I src));
11356 effect( DEF dst, USE src );
11357 ins_cost(100);
11358 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11359 ins_encode %{
11360 __ movl($dst$$Register, Address(rsp, $src$$disp));
11361 %}
11362 ins_pipe( ialu_reg_mem );
11363 %}
11364
11365 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11366 predicate(UseSSE==0);
11367 match(Set dst (MoveF2I src));
11368 effect( DEF dst, USE src );
11369
11370 ins_cost(125);
11371 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11372 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11373 ins_pipe( fpu_mem_reg );
11374 %}
11375
11376 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11377 predicate(UseSSE>=1);
11378 match(Set dst (MoveF2I src));
11379 effect( DEF dst, USE src );
11380
11381 ins_cost(95);
11382 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11383 ins_encode %{
11384 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11385 %}
11386 ins_pipe( pipe_slow );
11387 %}
11388
11389 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11390 predicate(UseSSE>=2);
11391 match(Set dst (MoveF2I src));
11392 effect( DEF dst, USE src );
11393 ins_cost(85);
11394 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11395 ins_encode %{
11396 __ movdl($dst$$Register, $src$$XMMRegister);
11397 %}
11398 ins_pipe( pipe_slow );
11399 %}
11400
11401 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11402 match(Set dst (MoveI2F src));
11403 effect( DEF dst, USE src );
11404
11405 ins_cost(100);
11406 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11407 ins_encode %{
11408 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11409 %}
11410 ins_pipe( ialu_mem_reg );
11411 %}
11412
11413
11414 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11415 predicate(UseSSE==0);
11416 match(Set dst (MoveI2F src));
11417 effect(DEF dst, USE src);
11418
11419 ins_cost(125);
11420 format %{ "FLD_S $src\n\t"
11421 "FSTP $dst\t# MoveI2F_stack_reg" %}
11422 opcode(0xD9); /* D9 /0, FLD m32real */
11423 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11424 Pop_Reg_FPR(dst) );
11425 ins_pipe( fpu_reg_mem );
11426 %}
11427
11428 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11429 predicate(UseSSE>=1);
11430 match(Set dst (MoveI2F src));
11431 effect( DEF dst, USE src );
11432
11433 ins_cost(95);
11434 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11435 ins_encode %{
11436 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11437 %}
11438 ins_pipe( pipe_slow );
11439 %}
11440
11441 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11442 predicate(UseSSE>=2);
11443 match(Set dst (MoveI2F src));
11444 effect( DEF dst, USE src );
11445
11446 ins_cost(85);
11447 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11448 ins_encode %{
11449 __ movdl($dst$$XMMRegister, $src$$Register);
11450 %}
11451 ins_pipe( pipe_slow );
11452 %}
11453
11454 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11455 match(Set dst (MoveD2L src));
11456 effect(DEF dst, USE src);
11457
11458 ins_cost(250);
11459 format %{ "MOV $dst.lo,$src\n\t"
11460 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11461 opcode(0x8B, 0x8B);
11462 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11463 ins_pipe( ialu_mem_long_reg );
11464 %}
11465
11466 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11467 predicate(UseSSE<=1);
11468 match(Set dst (MoveD2L src));
11469 effect(DEF dst, USE src);
11470
11471 ins_cost(125);
11472 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11473 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11474 ins_pipe( fpu_mem_reg );
11475 %}
11476
11477 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11478 predicate(UseSSE>=2);
11479 match(Set dst (MoveD2L src));
11480 effect(DEF dst, USE src);
11481 ins_cost(95);
11482 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11483 ins_encode %{
11484 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11485 %}
11486 ins_pipe( pipe_slow );
11487 %}
11488
11489 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11490 predicate(UseSSE>=2);
11491 match(Set dst (MoveD2L src));
11492 effect(DEF dst, USE src, TEMP tmp);
11493 ins_cost(85);
11494 format %{ "MOVD $dst.lo,$src\n\t"
11495 "PSHUFLW $tmp,$src,0x4E\n\t"
11496 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11497 ins_encode %{
11498 __ movdl($dst$$Register, $src$$XMMRegister);
11499 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11500 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11501 %}
11502 ins_pipe( pipe_slow );
11503 %}
11504
11505 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11506 match(Set dst (MoveL2D src));
11507 effect(DEF dst, USE src);
11508
11509 ins_cost(200);
11510 format %{ "MOV $dst,$src.lo\n\t"
11511 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11512 opcode(0x89, 0x89);
11513 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11514 ins_pipe( ialu_mem_long_reg );
11515 %}
11516
11517
11518 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11519 predicate(UseSSE<=1);
11520 match(Set dst (MoveL2D src));
11521 effect(DEF dst, USE src);
11522 ins_cost(125);
11523
11524 format %{ "FLD_D $src\n\t"
11525 "FSTP $dst\t# MoveL2D_stack_reg" %}
11526 opcode(0xDD); /* DD /0, FLD m64real */
11527 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11528 Pop_Reg_DPR(dst) );
11529 ins_pipe( fpu_reg_mem );
11530 %}
11531
11532
11533 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11534 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11535 match(Set dst (MoveL2D src));
11536 effect(DEF dst, USE src);
11537
11538 ins_cost(95);
11539 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11540 ins_encode %{
11541 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11542 %}
11543 ins_pipe( pipe_slow );
11544 %}
11545
11546 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11547 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11548 match(Set dst (MoveL2D src));
11549 effect(DEF dst, USE src);
11550
11551 ins_cost(95);
11552 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11553 ins_encode %{
11554 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11555 %}
11556 ins_pipe( pipe_slow );
11557 %}
11558
11559 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11560 predicate(UseSSE>=2);
11561 match(Set dst (MoveL2D src));
11562 effect(TEMP dst, USE src, TEMP tmp);
11563 ins_cost(85);
11564 format %{ "MOVD $dst,$src.lo\n\t"
11565 "MOVD $tmp,$src.hi\n\t"
11566 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11567 ins_encode %{
11568 __ movdl($dst$$XMMRegister, $src$$Register);
11569 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11570 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11571 %}
11572 ins_pipe( pipe_slow );
11573 %}
11574
11575
11576 // =======================================================================
11577 // fast clearing of an array
11578 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11579 match(Set dummy (ClearArray cnt base));
11580 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11581 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11582 "XOR EAX,EAX\n\t"
11583 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11584 opcode(0,0x4);
11585 ins_encode( Opcode(0xD1), RegOpc(ECX),
11586 OpcRegReg(0x33,EAX,EAX),
11587 Opcode(0xF3), Opcode(0xAB) );
11588 ins_pipe( pipe_slow );
11589 %}
11590
11591 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11592 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11593 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11594 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11595
11596 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11597 ins_encode %{
11598 __ string_compare($str1$$Register, $str2$$Register,
11599 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11600 $tmp1$$XMMRegister);
11601 %}
11602 ins_pipe( pipe_slow );
11603 %}
11604
11605 // fast string equals
11606 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11607 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11608 match(Set result (StrEquals (Binary str1 str2) cnt));
11609 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11610
11611 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11612 ins_encode %{
11613 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11614 $cnt$$Register, $result$$Register, $tmp3$$Register,
11615 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11616 %}
11617 ins_pipe( pipe_slow );
11618 %}
11619
11620 // fast search of substring with known size.
11621 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11622 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11623 predicate(UseSSE42Intrinsics);
11624 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11625 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11626
11627 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11628 ins_encode %{
11629 int icnt2 = (int)$int_cnt2$$constant;
11630 if (icnt2 >= 8) {
11631 // IndexOf for constant substrings with size >= 8 elements
11632 // which don't need to be loaded through stack.
11633 __ string_indexofC8($str1$$Register, $str2$$Register,
11634 $cnt1$$Register, $cnt2$$Register,
11635 icnt2, $result$$Register,
11636 $vec$$XMMRegister, $tmp$$Register);
11637 } else {
11638 // Small strings are loaded through stack if they cross page boundary.
11639 __ string_indexof($str1$$Register, $str2$$Register,
11640 $cnt1$$Register, $cnt2$$Register,
11641 icnt2, $result$$Register,
11642 $vec$$XMMRegister, $tmp$$Register);
11643 }
11644 %}
11645 ins_pipe( pipe_slow );
11646 %}
11647
11648 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11649 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11650 predicate(UseSSE42Intrinsics);
11651 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11652 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11653
11654 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11655 ins_encode %{
11656 __ string_indexof($str1$$Register, $str2$$Register,
11657 $cnt1$$Register, $cnt2$$Register,
11658 (-1), $result$$Register,
11659 $vec$$XMMRegister, $tmp$$Register);
11660 %}
11661 ins_pipe( pipe_slow );
11662 %}
11663
11664 // fast array equals
11665 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11666 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11667 %{
11668 match(Set result (AryEq ary1 ary2));
11669 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11670 //ins_cost(300);
11671
11672 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11673 ins_encode %{
11674 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11675 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11676 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11677 %}
11678 ins_pipe( pipe_slow );
11679 %}
11680
11681 //----------Control Flow Instructions------------------------------------------
11682 // Signed compare Instructions
11683 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11684 match(Set cr (CmpI op1 op2));
11685 effect( DEF cr, USE op1, USE op2 );
11686 format %{ "CMP $op1,$op2" %}
11687 opcode(0x3B); /* Opcode 3B /r */
11688 ins_encode( OpcP, RegReg( op1, op2) );
11689 ins_pipe( ialu_cr_reg_reg );
11690 %}
11691
11692 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11693 match(Set cr (CmpI op1 op2));
11694 effect( DEF cr, USE op1 );
11695 format %{ "CMP $op1,$op2" %}
11696 opcode(0x81,0x07); /* Opcode 81 /7 */
11697 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11698 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11699 ins_pipe( ialu_cr_reg_imm );
11700 %}
11701
11702 // Cisc-spilled version of cmpI_eReg
11703 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11704 match(Set cr (CmpI op1 (LoadI op2)));
11705
11706 format %{ "CMP $op1,$op2" %}
11707 ins_cost(500);
11708 opcode(0x3B); /* Opcode 3B /r */
11709 ins_encode( OpcP, RegMem( op1, op2) );
11710 ins_pipe( ialu_cr_reg_mem );
11711 %}
11712
11713 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11714 match(Set cr (CmpI src zero));
11715 effect( DEF cr, USE src );
11716
11717 format %{ "TEST $src,$src" %}
11718 opcode(0x85);
11719 ins_encode( OpcP, RegReg( src, src ) );
11720 ins_pipe( ialu_cr_reg_imm );
11721 %}
11722
11723 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11724 match(Set cr (CmpI (AndI src con) zero));
11725
11726 format %{ "TEST $src,$con" %}
11727 opcode(0xF7,0x00);
11728 ins_encode( OpcP, RegOpc(src), Con32(con) );
11729 ins_pipe( ialu_cr_reg_imm );
11730 %}
11731
11732 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11733 match(Set cr (CmpI (AndI src mem) zero));
11734
11735 format %{ "TEST $src,$mem" %}
11736 opcode(0x85);
11737 ins_encode( OpcP, RegMem( src, mem ) );
11738 ins_pipe( ialu_cr_reg_mem );
11739 %}
11740
11741 // Unsigned compare Instructions; really, same as signed except they
11742 // produce an eFlagsRegU instead of eFlagsReg.
11743 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11744 match(Set cr (CmpU op1 op2));
11745
11746 format %{ "CMPu $op1,$op2" %}
11747 opcode(0x3B); /* Opcode 3B /r */
11748 ins_encode( OpcP, RegReg( op1, op2) );
11749 ins_pipe( ialu_cr_reg_reg );
11750 %}
11751
11752 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11753 match(Set cr (CmpU op1 op2));
11754
11755 format %{ "CMPu $op1,$op2" %}
11756 opcode(0x81,0x07); /* Opcode 81 /7 */
11757 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11758 ins_pipe( ialu_cr_reg_imm );
11759 %}
11760
11761 // // Cisc-spilled version of cmpU_eReg
11762 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11763 match(Set cr (CmpU op1 (LoadI op2)));
11764
11765 format %{ "CMPu $op1,$op2" %}
11766 ins_cost(500);
11767 opcode(0x3B); /* Opcode 3B /r */
11768 ins_encode( OpcP, RegMem( op1, op2) );
11769 ins_pipe( ialu_cr_reg_mem );
11770 %}
11771
11772 // // Cisc-spilled version of cmpU_eReg
11773 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11774 // match(Set cr (CmpU (LoadI op1) op2));
11775 //
11776 // format %{ "CMPu $op1,$op2" %}
11777 // ins_cost(500);
11778 // opcode(0x39); /* Opcode 39 /r */
11779 // ins_encode( OpcP, RegMem( op1, op2) );
11780 //%}
11781
11782 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11783 match(Set cr (CmpU src zero));
11784
11785 format %{ "TESTu $src,$src" %}
11786 opcode(0x85);
11787 ins_encode( OpcP, RegReg( src, src ) );
11788 ins_pipe( ialu_cr_reg_imm );
11789 %}
11790
11791 // Unsigned pointer compare Instructions
11792 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11793 match(Set cr (CmpP op1 op2));
11794
11795 format %{ "CMPu $op1,$op2" %}
11796 opcode(0x3B); /* Opcode 3B /r */
11797 ins_encode( OpcP, RegReg( op1, op2) );
11798 ins_pipe( ialu_cr_reg_reg );
11799 %}
11800
11801 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11802 match(Set cr (CmpP op1 op2));
11803
11804 format %{ "CMPu $op1,$op2" %}
11805 opcode(0x81,0x07); /* Opcode 81 /7 */
11806 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11807 ins_pipe( ialu_cr_reg_imm );
11808 %}
11809
11810 // // Cisc-spilled version of cmpP_eReg
11811 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11812 match(Set cr (CmpP op1 (LoadP op2)));
11813
11814 format %{ "CMPu $op1,$op2" %}
11815 ins_cost(500);
11816 opcode(0x3B); /* Opcode 3B /r */
11817 ins_encode( OpcP, RegMem( op1, op2) );
11818 ins_pipe( ialu_cr_reg_mem );
11819 %}
11820
11821 // // Cisc-spilled version of cmpP_eReg
11822 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11823 // match(Set cr (CmpP (LoadP op1) op2));
11824 //
11825 // format %{ "CMPu $op1,$op2" %}
11826 // ins_cost(500);
11827 // opcode(0x39); /* Opcode 39 /r */
11828 // ins_encode( OpcP, RegMem( op1, op2) );
11829 //%}
11830
11831 // Compare raw pointer (used in out-of-heap check).
11832 // Only works because non-oop pointers must be raw pointers
11833 // and raw pointers have no anti-dependencies.
11834 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11835 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11836 match(Set cr (CmpP op1 (LoadP op2)));
11837
11838 format %{ "CMPu $op1,$op2" %}
11839 opcode(0x3B); /* Opcode 3B /r */
11840 ins_encode( OpcP, RegMem( op1, op2) );
11841 ins_pipe( ialu_cr_reg_mem );
11842 %}
11843
11844 //
11845 // This will generate a signed flags result. This should be ok
11846 // since any compare to a zero should be eq/neq.
11847 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11848 match(Set cr (CmpP src zero));
11849
11850 format %{ "TEST $src,$src" %}
11851 opcode(0x85);
11852 ins_encode( OpcP, RegReg( src, src ) );
11853 ins_pipe( ialu_cr_reg_imm );
11854 %}
11855
11856 // Cisc-spilled version of testP_reg
11857 // This will generate a signed flags result. This should be ok
11858 // since any compare to a zero should be eq/neq.
11859 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11860 match(Set cr (CmpP (LoadP op) zero));
11861
11862 format %{ "TEST $op,0xFFFFFFFF" %}
11863 ins_cost(500);
11864 opcode(0xF7); /* Opcode F7 /0 */
11865 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11866 ins_pipe( ialu_cr_reg_imm );
11867 %}
11868
11869 // Yanked all unsigned pointer compare operations.
11870 // Pointer compares are done with CmpP which is already unsigned.
11871
11872 //----------Max and Min--------------------------------------------------------
11873 // Min Instructions
11874 ////
11875 // *** Min and Max using the conditional move are slower than the
11876 // *** branch version on a Pentium III.
11877 // // Conditional move for min
11878 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11879 // effect( USE_DEF op2, USE op1, USE cr );
11880 // format %{ "CMOVlt $op2,$op1\t! min" %}
11881 // opcode(0x4C,0x0F);
11882 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11883 // ins_pipe( pipe_cmov_reg );
11884 //%}
11885 //
11886 //// Min Register with Register (P6 version)
11887 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11888 // predicate(VM_Version::supports_cmov() );
11889 // match(Set op2 (MinI op1 op2));
11890 // ins_cost(200);
11891 // expand %{
11892 // eFlagsReg cr;
11893 // compI_eReg(cr,op1,op2);
11894 // cmovI_reg_lt(op2,op1,cr);
11895 // %}
11896 //%}
11897
11898 // Min Register with Register (generic version)
11899 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11900 match(Set dst (MinI dst src));
11901 effect(KILL flags);
11902 ins_cost(300);
11903
11904 format %{ "MIN $dst,$src" %}
11905 opcode(0xCC);
11906 ins_encode( min_enc(dst,src) );
11907 ins_pipe( pipe_slow );
11908 %}
11909
11910 // Max Register with Register
11911 // *** Min and Max using the conditional move are slower than the
11912 // *** branch version on a Pentium III.
11913 // // Conditional move for max
11914 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11915 // effect( USE_DEF op2, USE op1, USE cr );
11916 // format %{ "CMOVgt $op2,$op1\t! max" %}
11917 // opcode(0x4F,0x0F);
11918 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11919 // ins_pipe( pipe_cmov_reg );
11920 //%}
11921 //
11922 // // Max Register with Register (P6 version)
11923 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11924 // predicate(VM_Version::supports_cmov() );
11925 // match(Set op2 (MaxI op1 op2));
11926 // ins_cost(200);
11927 // expand %{
11928 // eFlagsReg cr;
11929 // compI_eReg(cr,op1,op2);
11930 // cmovI_reg_gt(op2,op1,cr);
11931 // %}
11932 //%}
11933
11934 // Max Register with Register (generic version)
11935 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11936 match(Set dst (MaxI dst src));
11937 effect(KILL flags);
11938 ins_cost(300);
11939
11940 format %{ "MAX $dst,$src" %}
11941 opcode(0xCC);
11942 ins_encode( max_enc(dst,src) );
11943 ins_pipe( pipe_slow );
11944 %}
11945
11946 // ============================================================================
11947 // Counted Loop limit node which represents exact final iterator value.
11948 // Note: the resulting value should fit into integer range since
11949 // counted loops have limit check on overflow.
11950 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11951 match(Set limit (LoopLimit (Binary init limit) stride));
11952 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11953 ins_cost(300);
11954
11955 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11956 ins_encode %{
11957 int strd = (int)$stride$$constant;
11958 assert(strd != 1 && strd != -1, "sanity");
11959 int m1 = (strd > 0) ? 1 : -1;
11960 // Convert limit to long (EAX:EDX)
11961 __ cdql();
11962 // Convert init to long (init:tmp)
11963 __ movl($tmp$$Register, $init$$Register);
11964 __ sarl($tmp$$Register, 31);
11965 // $limit - $init
11966 __ subl($limit$$Register, $init$$Register);
11967 __ sbbl($limit_hi$$Register, $tmp$$Register);
11968 // + ($stride - 1)
11969 if (strd > 0) {
11970 __ addl($limit$$Register, (strd - 1));
11971 __ adcl($limit_hi$$Register, 0);
11972 __ movl($tmp$$Register, strd);
11973 } else {
11974 __ addl($limit$$Register, (strd + 1));
11975 __ adcl($limit_hi$$Register, -1);
11976 __ lneg($limit_hi$$Register, $limit$$Register);
11977 __ movl($tmp$$Register, -strd);
11978 }
11979 // signed devision: (EAX:EDX) / pos_stride
11980 __ idivl($tmp$$Register);
11981 if (strd < 0) {
11982 // restore sign
11983 __ negl($tmp$$Register);
11984 }
11985 // (EAX) * stride
11986 __ mull($tmp$$Register);
11987 // + init (ignore upper bits)
11988 __ addl($limit$$Register, $init$$Register);
11989 %}
11990 ins_pipe( pipe_slow );
11991 %}
11992
11993 // ============================================================================
11994 // Branch Instructions
11995 // Jump Table
11996 instruct jumpXtnd(rRegI switch_val) %{
11997 match(Jump switch_val);
11998 ins_cost(350);
11999 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12000 ins_encode %{
12001 // Jump to Address(table_base + switch_reg)
12002 Address index(noreg, $switch_val$$Register, Address::times_1);
12003 __ jump(ArrayAddress($constantaddress, index));
12004 %}
12005 ins_pipe(pipe_jmp);
12006 %}
12007
12008 // Jump Direct - Label defines a relative address from JMP+1
12009 instruct jmpDir(label labl) %{
12010 match(Goto);
12011 effect(USE labl);
12012
12013 ins_cost(300);
12014 format %{ "JMP $labl" %}
12015 size(5);
12016 ins_encode %{
12017 Label* L = $labl$$label;
12018 __ jmp(*L, false); // Always long jump
12019 %}
12020 ins_pipe( pipe_jmp );
12021 %}
12022
12023 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12024 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12025 match(If cop cr);
12026 effect(USE labl);
12027
12028 ins_cost(300);
12029 format %{ "J$cop $labl" %}
12030 size(6);
12031 ins_encode %{
12032 Label* L = $labl$$label;
12033 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12034 %}
12035 ins_pipe( pipe_jcc );
12036 %}
12037
12038 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12039 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12040 match(CountedLoopEnd cop cr);
12041 effect(USE labl);
12042
12043 ins_cost(300);
12044 format %{ "J$cop $labl\t# Loop end" %}
12045 size(6);
12046 ins_encode %{
12047 Label* L = $labl$$label;
12048 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12049 %}
12050 ins_pipe( pipe_jcc );
12051 %}
12052
12053 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12054 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12055 match(CountedLoopEnd cop cmp);
12056 effect(USE labl);
12057
12058 ins_cost(300);
12059 format %{ "J$cop,u $labl\t# Loop end" %}
12060 size(6);
12061 ins_encode %{
12062 Label* L = $labl$$label;
12063 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12064 %}
12065 ins_pipe( pipe_jcc );
12066 %}
12067
12068 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12069 match(CountedLoopEnd cop cmp);
12070 effect(USE labl);
12071
12072 ins_cost(200);
12073 format %{ "J$cop,u $labl\t# Loop end" %}
12074 size(6);
12075 ins_encode %{
12076 Label* L = $labl$$label;
12077 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12078 %}
12079 ins_pipe( pipe_jcc );
12080 %}
12081
12082 // Jump Direct Conditional - using unsigned comparison
12083 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12084 match(If cop cmp);
12085 effect(USE labl);
12086
12087 ins_cost(300);
12088 format %{ "J$cop,u $labl" %}
12089 size(6);
12090 ins_encode %{
12091 Label* L = $labl$$label;
12092 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12093 %}
12094 ins_pipe(pipe_jcc);
12095 %}
12096
12097 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12098 match(If cop cmp);
12099 effect(USE labl);
12100
12101 ins_cost(200);
12102 format %{ "J$cop,u $labl" %}
12103 size(6);
12104 ins_encode %{
12105 Label* L = $labl$$label;
12106 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12107 %}
12108 ins_pipe(pipe_jcc);
12109 %}
12110
12111 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12112 match(If cop cmp);
12113 effect(USE labl);
12114
12115 ins_cost(200);
12116 format %{ $$template
12117 if ($cop$$cmpcode == Assembler::notEqual) {
12118 $$emit$$"JP,u $labl\n\t"
12119 $$emit$$"J$cop,u $labl"
12120 } else {
12121 $$emit$$"JP,u done\n\t"
12122 $$emit$$"J$cop,u $labl\n\t"
12123 $$emit$$"done:"
12124 }
12125 %}
12126 ins_encode %{
12127 Label* l = $labl$$label;
12128 if ($cop$$cmpcode == Assembler::notEqual) {
12129 __ jcc(Assembler::parity, *l, false);
12130 __ jcc(Assembler::notEqual, *l, false);
12131 } else if ($cop$$cmpcode == Assembler::equal) {
12132 Label done;
12133 __ jccb(Assembler::parity, done);
12134 __ jcc(Assembler::equal, *l, false);
12135 __ bind(done);
12136 } else {
12137 ShouldNotReachHere();
12138 }
12139 %}
12140 ins_pipe(pipe_jcc);
12141 %}
12142
12143 // ============================================================================
12144 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12145 // array for an instance of the superklass. Set a hidden internal cache on a
12146 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12147 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12148 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12149 match(Set result (PartialSubtypeCheck sub super));
12150 effect( KILL rcx, KILL cr );
12151
12152 ins_cost(1100); // slightly larger than the next version
12153 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12154 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12155 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12156 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12157 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12158 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12159 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12160 "miss:\t" %}
12161
12162 opcode(0x1); // Force a XOR of EDI
12163 ins_encode( enc_PartialSubtypeCheck() );
12164 ins_pipe( pipe_slow );
12165 %}
12166
12167 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12168 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12169 effect( KILL rcx, KILL result );
12170
12171 ins_cost(1000);
12172 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12173 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12174 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12175 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12176 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12177 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12178 "miss:\t" %}
12179
12180 opcode(0x0); // No need to XOR EDI
12181 ins_encode( enc_PartialSubtypeCheck() );
12182 ins_pipe( pipe_slow );
12183 %}
12184
12185 // ============================================================================
12186 // Branch Instructions -- short offset versions
12187 //
12188 // These instructions are used to replace jumps of a long offset (the default
12189 // match) with jumps of a shorter offset. These instructions are all tagged
12190 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12191 // match rules in general matching. Instead, the ADLC generates a conversion
12192 // method in the MachNode which can be used to do in-place replacement of the
12193 // long variant with the shorter variant. The compiler will determine if a
12194 // branch can be taken by the is_short_branch_offset() predicate in the machine
12195 // specific code section of the file.
12196
12197 // Jump Direct - Label defines a relative address from JMP+1
12198 instruct jmpDir_short(label labl) %{
12199 match(Goto);
12200 effect(USE labl);
12201
12202 ins_cost(300);
12203 format %{ "JMP,s $labl" %}
12204 size(2);
12205 ins_encode %{
12206 Label* L = $labl$$label;
12207 __ jmpb(*L);
12208 %}
12209 ins_pipe( pipe_jmp );
12210 ins_short_branch(1);
12211 %}
12212
12213 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12214 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12215 match(If cop cr);
12216 effect(USE labl);
12217
12218 ins_cost(300);
12219 format %{ "J$cop,s $labl" %}
12220 size(2);
12221 ins_encode %{
12222 Label* L = $labl$$label;
12223 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12224 %}
12225 ins_pipe( pipe_jcc );
12226 ins_short_branch(1);
12227 %}
12228
12229 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12230 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12231 match(CountedLoopEnd cop cr);
12232 effect(USE labl);
12233
12234 ins_cost(300);
12235 format %{ "J$cop,s $labl\t# Loop end" %}
12236 size(2);
12237 ins_encode %{
12238 Label* L = $labl$$label;
12239 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12240 %}
12241 ins_pipe( pipe_jcc );
12242 ins_short_branch(1);
12243 %}
12244
12245 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12246 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12247 match(CountedLoopEnd cop cmp);
12248 effect(USE labl);
12249
12250 ins_cost(300);
12251 format %{ "J$cop,us $labl\t# Loop end" %}
12252 size(2);
12253 ins_encode %{
12254 Label* L = $labl$$label;
12255 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12256 %}
12257 ins_pipe( pipe_jcc );
12258 ins_short_branch(1);
12259 %}
12260
12261 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12262 match(CountedLoopEnd cop cmp);
12263 effect(USE labl);
12264
12265 ins_cost(300);
12266 format %{ "J$cop,us $labl\t# Loop end" %}
12267 size(2);
12268 ins_encode %{
12269 Label* L = $labl$$label;
12270 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12271 %}
12272 ins_pipe( pipe_jcc );
12273 ins_short_branch(1);
12274 %}
12275
12276 // Jump Direct Conditional - using unsigned comparison
12277 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12278 match(If cop cmp);
12279 effect(USE labl);
12280
12281 ins_cost(300);
12282 format %{ "J$cop,us $labl" %}
12283 size(2);
12284 ins_encode %{
12285 Label* L = $labl$$label;
12286 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12287 %}
12288 ins_pipe( pipe_jcc );
12289 ins_short_branch(1);
12290 %}
12291
12292 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12293 match(If cop cmp);
12294 effect(USE labl);
12295
12296 ins_cost(300);
12297 format %{ "J$cop,us $labl" %}
12298 size(2);
12299 ins_encode %{
12300 Label* L = $labl$$label;
12301 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12302 %}
12303 ins_pipe( pipe_jcc );
12304 ins_short_branch(1);
12305 %}
12306
12307 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12308 match(If cop cmp);
12309 effect(USE labl);
12310
12311 ins_cost(300);
12312 format %{ $$template
12313 if ($cop$$cmpcode == Assembler::notEqual) {
12314 $$emit$$"JP,u,s $labl\n\t"
12315 $$emit$$"J$cop,u,s $labl"
12316 } else {
12317 $$emit$$"JP,u,s done\n\t"
12318 $$emit$$"J$cop,u,s $labl\n\t"
12319 $$emit$$"done:"
12320 }
12321 %}
12322 size(4);
12323 ins_encode %{
12324 Label* l = $labl$$label;
12325 if ($cop$$cmpcode == Assembler::notEqual) {
12326 __ jccb(Assembler::parity, *l);
12327 __ jccb(Assembler::notEqual, *l);
12328 } else if ($cop$$cmpcode == Assembler::equal) {
12329 Label done;
12330 __ jccb(Assembler::parity, done);
12331 __ jccb(Assembler::equal, *l);
12332 __ bind(done);
12333 } else {
12334 ShouldNotReachHere();
12335 }
12336 %}
12337 ins_pipe(pipe_jcc);
12338 ins_short_branch(1);
12339 %}
12340
12341 // ============================================================================
12342 // Long Compare
12343 //
12344 // Currently we hold longs in 2 registers. Comparing such values efficiently
12345 // is tricky. The flavor of compare used depends on whether we are testing
12346 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12347 // The GE test is the negated LT test. The LE test can be had by commuting
12348 // the operands (yielding a GE test) and then negating; negate again for the
12349 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12350 // NE test is negated from that.
12351
12352 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12353 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12354 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12355 // are collapsed internally in the ADLC's dfa-gen code. The match for
12356 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12357 // foo match ends up with the wrong leaf. One fix is to not match both
12358 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12359 // both forms beat the trinary form of long-compare and both are very useful
12360 // on Intel which has so few registers.
12361
12362 // Manifest a CmpL result in an integer register. Very painful.
12363 // This is the test to avoid.
12364 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12365 match(Set dst (CmpL3 src1 src2));
12366 effect( KILL flags );
12367 ins_cost(1000);
12368 format %{ "XOR $dst,$dst\n\t"
12369 "CMP $src1.hi,$src2.hi\n\t"
12370 "JLT,s m_one\n\t"
12371 "JGT,s p_one\n\t"
12372 "CMP $src1.lo,$src2.lo\n\t"
12373 "JB,s m_one\n\t"
12374 "JEQ,s done\n"
12375 "p_one:\tINC $dst\n\t"
12376 "JMP,s done\n"
12377 "m_one:\tDEC $dst\n"
12378 "done:" %}
12379 ins_encode %{
12380 Label p_one, m_one, done;
12381 __ xorptr($dst$$Register, $dst$$Register);
12382 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12383 __ jccb(Assembler::less, m_one);
12384 __ jccb(Assembler::greater, p_one);
12385 __ cmpl($src1$$Register, $src2$$Register);
12386 __ jccb(Assembler::below, m_one);
12387 __ jccb(Assembler::equal, done);
12388 __ bind(p_one);
12389 __ incrementl($dst$$Register);
12390 __ jmpb(done);
12391 __ bind(m_one);
12392 __ decrementl($dst$$Register);
12393 __ bind(done);
12394 %}
12395 ins_pipe( pipe_slow );
12396 %}
12397
12398 //======
12399 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12400 // compares. Can be used for LE or GT compares by reversing arguments.
12401 // NOT GOOD FOR EQ/NE tests.
12402 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12403 match( Set flags (CmpL src zero ));
12404 ins_cost(100);
12405 format %{ "TEST $src.hi,$src.hi" %}
12406 opcode(0x85);
12407 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12408 ins_pipe( ialu_cr_reg_reg );
12409 %}
12410
12411 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12412 // compares. Can be used for LE or GT compares by reversing arguments.
12413 // NOT GOOD FOR EQ/NE tests.
12414 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12415 match( Set flags (CmpL src1 src2 ));
12416 effect( TEMP tmp );
12417 ins_cost(300);
12418 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12419 "MOV $tmp,$src1.hi\n\t"
12420 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12421 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12422 ins_pipe( ialu_cr_reg_reg );
12423 %}
12424
12425 // Long compares reg < zero/req OR reg >= zero/req.
12426 // Just a wrapper for a normal branch, plus the predicate test.
12427 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12428 match(If cmp flags);
12429 effect(USE labl);
12430 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12431 expand %{
12432 jmpCon(cmp,flags,labl); // JLT or JGE...
12433 %}
12434 %}
12435
12436 // Compare 2 longs and CMOVE longs.
12437 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12438 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12439 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12440 ins_cost(400);
12441 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12442 "CMOV$cmp $dst.hi,$src.hi" %}
12443 opcode(0x0F,0x40);
12444 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12445 ins_pipe( pipe_cmov_reg_long );
12446 %}
12447
12448 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12449 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12450 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12451 ins_cost(500);
12452 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12453 "CMOV$cmp $dst.hi,$src.hi" %}
12454 opcode(0x0F,0x40);
12455 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12456 ins_pipe( pipe_cmov_reg_long );
12457 %}
12458
12459 // Compare 2 longs and CMOVE ints.
12460 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12461 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12462 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12463 ins_cost(200);
12464 format %{ "CMOV$cmp $dst,$src" %}
12465 opcode(0x0F,0x40);
12466 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12467 ins_pipe( pipe_cmov_reg );
12468 %}
12469
12470 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12471 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12472 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12473 ins_cost(250);
12474 format %{ "CMOV$cmp $dst,$src" %}
12475 opcode(0x0F,0x40);
12476 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12477 ins_pipe( pipe_cmov_mem );
12478 %}
12479
12480 // Compare 2 longs and CMOVE ints.
12481 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12482 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12483 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12484 ins_cost(200);
12485 format %{ "CMOV$cmp $dst,$src" %}
12486 opcode(0x0F,0x40);
12487 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12488 ins_pipe( pipe_cmov_reg );
12489 %}
12490
12491 // Compare 2 longs and CMOVE doubles
12492 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12493 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12494 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12495 ins_cost(200);
12496 expand %{
12497 fcmovDPR_regS(cmp,flags,dst,src);
12498 %}
12499 %}
12500
12501 // Compare 2 longs and CMOVE doubles
12502 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12503 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12504 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12505 ins_cost(200);
12506 expand %{
12507 fcmovD_regS(cmp,flags,dst,src);
12508 %}
12509 %}
12510
12511 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12512 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12513 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12514 ins_cost(200);
12515 expand %{
12516 fcmovFPR_regS(cmp,flags,dst,src);
12517 %}
12518 %}
12519
12520 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12521 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12522 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12523 ins_cost(200);
12524 expand %{
12525 fcmovF_regS(cmp,flags,dst,src);
12526 %}
12527 %}
12528
12529 //======
12530 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12531 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12532 match( Set flags (CmpL src zero ));
12533 effect(TEMP tmp);
12534 ins_cost(200);
12535 format %{ "MOV $tmp,$src.lo\n\t"
12536 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12537 ins_encode( long_cmp_flags0( src, tmp ) );
12538 ins_pipe( ialu_reg_reg_long );
12539 %}
12540
12541 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12542 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12543 match( Set flags (CmpL src1 src2 ));
12544 ins_cost(200+300);
12545 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12546 "JNE,s skip\n\t"
12547 "CMP $src1.hi,$src2.hi\n\t"
12548 "skip:\t" %}
12549 ins_encode( long_cmp_flags1( src1, src2 ) );
12550 ins_pipe( ialu_cr_reg_reg );
12551 %}
12552
12553 // Long compare reg == zero/reg OR reg != zero/reg
12554 // Just a wrapper for a normal branch, plus the predicate test.
12555 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12556 match(If cmp flags);
12557 effect(USE labl);
12558 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12559 expand %{
12560 jmpCon(cmp,flags,labl); // JEQ or JNE...
12561 %}
12562 %}
12563
12564 // Compare 2 longs and CMOVE longs.
12565 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12566 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12567 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12568 ins_cost(400);
12569 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12570 "CMOV$cmp $dst.hi,$src.hi" %}
12571 opcode(0x0F,0x40);
12572 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12573 ins_pipe( pipe_cmov_reg_long );
12574 %}
12575
12576 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12577 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12578 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12579 ins_cost(500);
12580 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12581 "CMOV$cmp $dst.hi,$src.hi" %}
12582 opcode(0x0F,0x40);
12583 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12584 ins_pipe( pipe_cmov_reg_long );
12585 %}
12586
12587 // Compare 2 longs and CMOVE ints.
12588 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12589 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12590 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12591 ins_cost(200);
12592 format %{ "CMOV$cmp $dst,$src" %}
12593 opcode(0x0F,0x40);
12594 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12595 ins_pipe( pipe_cmov_reg );
12596 %}
12597
12598 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12599 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12600 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12601 ins_cost(250);
12602 format %{ "CMOV$cmp $dst,$src" %}
12603 opcode(0x0F,0x40);
12604 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12605 ins_pipe( pipe_cmov_mem );
12606 %}
12607
12608 // Compare 2 longs and CMOVE ints.
12609 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12610 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12611 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12612 ins_cost(200);
12613 format %{ "CMOV$cmp $dst,$src" %}
12614 opcode(0x0F,0x40);
12615 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12616 ins_pipe( pipe_cmov_reg );
12617 %}
12618
12619 // Compare 2 longs and CMOVE doubles
12620 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12621 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12622 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12623 ins_cost(200);
12624 expand %{
12625 fcmovDPR_regS(cmp,flags,dst,src);
12626 %}
12627 %}
12628
12629 // Compare 2 longs and CMOVE doubles
12630 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12631 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12632 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12633 ins_cost(200);
12634 expand %{
12635 fcmovD_regS(cmp,flags,dst,src);
12636 %}
12637 %}
12638
12639 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12640 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12641 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12642 ins_cost(200);
12643 expand %{
12644 fcmovFPR_regS(cmp,flags,dst,src);
12645 %}
12646 %}
12647
12648 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12649 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12650 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12651 ins_cost(200);
12652 expand %{
12653 fcmovF_regS(cmp,flags,dst,src);
12654 %}
12655 %}
12656
12657 //======
12658 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12659 // Same as cmpL_reg_flags_LEGT except must negate src
12660 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12661 match( Set flags (CmpL src zero ));
12662 effect( TEMP tmp );
12663 ins_cost(300);
12664 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12665 "CMP $tmp,$src.lo\n\t"
12666 "SBB $tmp,$src.hi\n\t" %}
12667 ins_encode( long_cmp_flags3(src, tmp) );
12668 ins_pipe( ialu_reg_reg_long );
12669 %}
12670
12671 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12672 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12673 // requires a commuted test to get the same result.
12674 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12675 match( Set flags (CmpL src1 src2 ));
12676 effect( TEMP tmp );
12677 ins_cost(300);
12678 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12679 "MOV $tmp,$src2.hi\n\t"
12680 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12681 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12682 ins_pipe( ialu_cr_reg_reg );
12683 %}
12684
12685 // Long compares reg < zero/req OR reg >= zero/req.
12686 // Just a wrapper for a normal branch, plus the predicate test
12687 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12688 match(If cmp flags);
12689 effect(USE labl);
12690 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12691 ins_cost(300);
12692 expand %{
12693 jmpCon(cmp,flags,labl); // JGT or JLE...
12694 %}
12695 %}
12696
12697 // Compare 2 longs and CMOVE longs.
12698 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12699 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12700 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12701 ins_cost(400);
12702 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12703 "CMOV$cmp $dst.hi,$src.hi" %}
12704 opcode(0x0F,0x40);
12705 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12706 ins_pipe( pipe_cmov_reg_long );
12707 %}
12708
12709 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12710 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12711 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12712 ins_cost(500);
12713 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12714 "CMOV$cmp $dst.hi,$src.hi+4" %}
12715 opcode(0x0F,0x40);
12716 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12717 ins_pipe( pipe_cmov_reg_long );
12718 %}
12719
12720 // Compare 2 longs and CMOVE ints.
12721 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12722 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12723 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12724 ins_cost(200);
12725 format %{ "CMOV$cmp $dst,$src" %}
12726 opcode(0x0F,0x40);
12727 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12728 ins_pipe( pipe_cmov_reg );
12729 %}
12730
12731 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12732 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12733 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12734 ins_cost(250);
12735 format %{ "CMOV$cmp $dst,$src" %}
12736 opcode(0x0F,0x40);
12737 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12738 ins_pipe( pipe_cmov_mem );
12739 %}
12740
12741 // Compare 2 longs and CMOVE ptrs.
12742 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12743 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12744 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12745 ins_cost(200);
12746 format %{ "CMOV$cmp $dst,$src" %}
12747 opcode(0x0F,0x40);
12748 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12749 ins_pipe( pipe_cmov_reg );
12750 %}
12751
12752 // Compare 2 longs and CMOVE doubles
12753 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12754 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12755 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12756 ins_cost(200);
12757 expand %{
12758 fcmovDPR_regS(cmp,flags,dst,src);
12759 %}
12760 %}
12761
12762 // Compare 2 longs and CMOVE doubles
12763 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12764 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12765 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12766 ins_cost(200);
12767 expand %{
12768 fcmovD_regS(cmp,flags,dst,src);
12769 %}
12770 %}
12771
12772 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12773 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12774 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12775 ins_cost(200);
12776 expand %{
12777 fcmovFPR_regS(cmp,flags,dst,src);
12778 %}
12779 %}
12780
12781
12782 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12783 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12784 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12785 ins_cost(200);
12786 expand %{
12787 fcmovF_regS(cmp,flags,dst,src);
12788 %}
12789 %}
12790
12791
12792 // ============================================================================
12793 // Procedure Call/Return Instructions
12794 // Call Java Static Instruction
12795 // Note: If this code changes, the corresponding ret_addr_offset() and
12796 // compute_padding() functions will have to be adjusted.
12797 instruct CallStaticJavaDirect(method meth) %{
12798 match(CallStaticJava);
12799 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12800 effect(USE meth);
12801
12802 ins_cost(300);
12803 format %{ "CALL,static " %}
12804 opcode(0xE8); /* E8 cd */
12805 ins_encode( pre_call_FPU,
12806 Java_Static_Call( meth ),
12807 call_epilog,
12808 post_call_FPU );
12809 ins_pipe( pipe_slow );
12810 ins_alignment(4);
12811 %}
12812
12813 // Call Java Static Instruction (method handle version)
12814 // Note: If this code changes, the corresponding ret_addr_offset() and
12815 // compute_padding() functions will have to be adjusted.
12816 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12817 match(CallStaticJava);
12818 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12819 effect(USE meth);
12820 // EBP is saved by all callees (for interpreter stack correction).
12821 // We use it here for a similar purpose, in {preserve,restore}_SP.
12822
12823 ins_cost(300);
12824 format %{ "CALL,static/MethodHandle " %}
12825 opcode(0xE8); /* E8 cd */
12826 ins_encode( pre_call_FPU,
12827 preserve_SP,
12828 Java_Static_Call( meth ),
12829 restore_SP,
12830 call_epilog,
12831 post_call_FPU );
12832 ins_pipe( pipe_slow );
12833 ins_alignment(4);
12834 %}
12835
12836 // Call Java Dynamic Instruction
12837 // Note: If this code changes, the corresponding ret_addr_offset() and
12838 // compute_padding() functions will have to be adjusted.
12839 instruct CallDynamicJavaDirect(method meth) %{
12840 match(CallDynamicJava);
12841 effect(USE meth);
12842
12843 ins_cost(300);
12844 format %{ "MOV EAX,(oop)-1\n\t"
12845 "CALL,dynamic" %}
12846 opcode(0xE8); /* E8 cd */
12847 ins_encode( pre_call_FPU,
12848 Java_Dynamic_Call( meth ),
12849 call_epilog,
12850 post_call_FPU );
12851 ins_pipe( pipe_slow );
12852 ins_alignment(4);
12853 %}
12854
12855 // Call Runtime Instruction
12856 instruct CallRuntimeDirect(method meth) %{
12857 match(CallRuntime );
12858 effect(USE meth);
12859
12860 ins_cost(300);
12861 format %{ "CALL,runtime " %}
12862 opcode(0xE8); /* E8 cd */
12863 // Use FFREEs to clear entries in float stack
12864 ins_encode( pre_call_FPU,
12865 FFree_Float_Stack_All,
12866 Java_To_Runtime( meth ),
12867 post_call_FPU );
12868 ins_pipe( pipe_slow );
12869 %}
12870
12871 // Call runtime without safepoint
12872 instruct CallLeafDirect(method meth) %{
12873 match(CallLeaf);
12874 effect(USE meth);
12875
12876 ins_cost(300);
12877 format %{ "CALL_LEAF,runtime " %}
12878 opcode(0xE8); /* E8 cd */
12879 ins_encode( pre_call_FPU,
12880 FFree_Float_Stack_All,
12881 Java_To_Runtime( meth ),
12882 Verify_FPU_For_Leaf, post_call_FPU );
12883 ins_pipe( pipe_slow );
12884 %}
12885
12886 instruct CallLeafNoFPDirect(method meth) %{
12887 match(CallLeafNoFP);
12888 effect(USE meth);
12889
12890 ins_cost(300);
12891 format %{ "CALL_LEAF_NOFP,runtime " %}
12892 opcode(0xE8); /* E8 cd */
12893 ins_encode(Java_To_Runtime(meth));
12894 ins_pipe( pipe_slow );
12895 %}
12896
12897
12898 // Return Instruction
12899 // Remove the return address & jump to it.
12900 instruct Ret() %{
12901 match(Return);
12902 format %{ "RET" %}
12903 opcode(0xC3);
12904 ins_encode(OpcP);
12905 ins_pipe( pipe_jmp );
12906 %}
12907
12908 // Tail Call; Jump from runtime stub to Java code.
12909 // Also known as an 'interprocedural jump'.
12910 // Target of jump will eventually return to caller.
12911 // TailJump below removes the return address.
12912 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12913 match(TailCall jump_target method_oop );
12914 ins_cost(300);
12915 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12916 opcode(0xFF, 0x4); /* Opcode FF /4 */
12917 ins_encode( OpcP, RegOpc(jump_target) );
12918 ins_pipe( pipe_jmp );
12919 %}
12920
12921
12922 // Tail Jump; remove the return address; jump to target.
12923 // TailCall above leaves the return address around.
12924 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12925 match( TailJump jump_target ex_oop );
12926 ins_cost(300);
12927 format %{ "POP EDX\t# pop return address into dummy\n\t"
12928 "JMP $jump_target " %}
12929 opcode(0xFF, 0x4); /* Opcode FF /4 */
12930 ins_encode( enc_pop_rdx,
12931 OpcP, RegOpc(jump_target) );
12932 ins_pipe( pipe_jmp );
12933 %}
12934
12935 // Create exception oop: created by stack-crawling runtime code.
12936 // Created exception is now available to this handler, and is setup
12937 // just prior to jumping to this handler. No code emitted.
12938 instruct CreateException( eAXRegP ex_oop )
12939 %{
12940 match(Set ex_oop (CreateEx));
12941
12942 size(0);
12943 // use the following format syntax
12944 format %{ "# exception oop is in EAX; no code emitted" %}
12945 ins_encode();
12946 ins_pipe( empty );
12947 %}
12948
12949
12950 // Rethrow exception:
12951 // The exception oop will come in the first argument position.
12952 // Then JUMP (not call) to the rethrow stub code.
12953 instruct RethrowException()
12954 %{
12955 match(Rethrow);
12956
12957 // use the following format syntax
12958 format %{ "JMP rethrow_stub" %}
12959 ins_encode(enc_rethrow);
12960 ins_pipe( pipe_jmp );
12961 %}
12962
12963 // inlined locking and unlocking
12964
12965
12966 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12967 match( Set cr (FastLock object box) );
12968 effect( TEMP tmp, TEMP scr, USE_KILL box );
12969 ins_cost(300);
12970 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12971 ins_encode( Fast_Lock(object,box,tmp,scr) );
12972 ins_pipe( pipe_slow );
12973 %}
12974
12975 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12976 match( Set cr (FastUnlock object box) );
12977 effect( TEMP tmp, USE_KILL box );
12978 ins_cost(300);
12979 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12980 ins_encode( Fast_Unlock(object,box,tmp) );
12981 ins_pipe( pipe_slow );
12982 %}
12983
12984
12985
12986 // ============================================================================
12987 // Safepoint Instruction
12988 instruct safePoint_poll(eFlagsReg cr) %{
12989 match(SafePoint);
12990 effect(KILL cr);
12991
12992 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12993 // On SPARC that might be acceptable as we can generate the address with
12994 // just a sethi, saving an or. By polling at offset 0 we can end up
12995 // putting additional pressure on the index-0 in the D$. Because of
12996 // alignment (just like the situation at hand) the lower indices tend
12997 // to see more traffic. It'd be better to change the polling address
12998 // to offset 0 of the last $line in the polling page.
12999
13000 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13001 ins_cost(125);
13002 size(6) ;
13003 ins_encode( Safepoint_Poll() );
13004 ins_pipe( ialu_reg_mem );
13005 %}
13006
13007
13008 // ============================================================================
13009 // This name is KNOWN by the ADLC and cannot be changed.
13010 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13011 // for this guy.
13012 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13013 match(Set dst (ThreadLocal));
13014 effect(DEF dst, KILL cr);
13015
13016 format %{ "MOV $dst, Thread::current()" %}
13017 ins_encode %{
13018 Register dstReg = as_Register($dst$$reg);
13019 __ get_thread(dstReg);
13020 %}
13021 ins_pipe( ialu_reg_fat );
13022 %}
13023
13024
13025
13026 //----------PEEPHOLE RULES-----------------------------------------------------
13027 // These must follow all instruction definitions as they use the names
13028 // defined in the instructions definitions.
13029 //
13030 // peepmatch ( root_instr_name [preceding_instruction]* );
13031 //
13032 // peepconstraint %{
13033 // (instruction_number.operand_name relational_op instruction_number.operand_name
13034 // [, ...] );
13035 // // instruction numbers are zero-based using left to right order in peepmatch
13036 //
13037 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13038 // // provide an instruction_number.operand_name for each operand that appears
13039 // // in the replacement instruction's match rule
13040 //
13041 // ---------VM FLAGS---------------------------------------------------------
13042 //
13043 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13044 //
13045 // Each peephole rule is given an identifying number starting with zero and
13046 // increasing by one in the order seen by the parser. An individual peephole
13047 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13048 // on the command-line.
13049 //
13050 // ---------CURRENT LIMITATIONS----------------------------------------------
13051 //
13052 // Only match adjacent instructions in same basic block
13053 // Only equality constraints
13054 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13055 // Only one replacement instruction
13056 //
13057 // ---------EXAMPLE----------------------------------------------------------
13058 //
13059 // // pertinent parts of existing instructions in architecture description
13060 // instruct movI(rRegI dst, rRegI src) %{
13061 // match(Set dst (CopyI src));
13062 // %}
13063 //
13064 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13065 // match(Set dst (AddI dst src));
13066 // effect(KILL cr);
13067 // %}
13068 //
13069 // // Change (inc mov) to lea
13070 // peephole %{
13071 // // increment preceeded by register-register move
13072 // peepmatch ( incI_eReg movI );
13073 // // require that the destination register of the increment
13074 // // match the destination register of the move
13075 // peepconstraint ( 0.dst == 1.dst );
13076 // // construct a replacement instruction that sets
13077 // // the destination to ( move's source register + one )
13078 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13079 // %}
13080 //
13081 // Implementation no longer uses movX instructions since
13082 // machine-independent system no longer uses CopyX nodes.
13083 //
13084 // peephole %{
13085 // peepmatch ( incI_eReg movI );
13086 // peepconstraint ( 0.dst == 1.dst );
13087 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13088 // %}
13089 //
13090 // peephole %{
13091 // peepmatch ( decI_eReg movI );
13092 // peepconstraint ( 0.dst == 1.dst );
13093 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13094 // %}
13095 //
13096 // peephole %{
13097 // peepmatch ( addI_eReg_imm movI );
13098 // peepconstraint ( 0.dst == 1.dst );
13099 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13100 // %}
13101 //
13102 // peephole %{
13103 // peepmatch ( addP_eReg_imm movP );
13104 // peepconstraint ( 0.dst == 1.dst );
13105 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13106 // %}
13107
13108 // // Change load of spilled value to only a spill
13109 // instruct storeI(memory mem, rRegI src) %{
13110 // match(Set mem (StoreI mem src));
13111 // %}
13112 //
13113 // instruct loadI(rRegI dst, memory mem) %{
13114 // match(Set dst (LoadI mem));
13115 // %}
13116 //
13117 peephole %{
13118 peepmatch ( loadI storeI );
13119 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13120 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13121 %}
13122
13123 //----------SMARTSPILL RULES---------------------------------------------------
13124 // These must follow all instruction definitions as they use the names
13125 // defined in the instructions definitions.