1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 OptoReg::Name OptoReg::c_frame_pointer;
45
46 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
47 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
48 RegMask Matcher::STACK_ONLY_mask;
49 RegMask Matcher::c_frame_ptr_mask;
50 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
51 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
52
53 //---------------------------Matcher-------------------------------------------
54 Matcher::Matcher()
55 : PhaseTransform( Phase::Ins_Select ),
56 #ifdef ASSERT
57 _old2new_map(C->comp_arena()),
58 _new2old_map(C->comp_arena()),
59 #endif
60 _shared_nodes(C->comp_arena()),
61 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
62 _swallowed(swallowed),
63 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
64 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
65 _must_clone(must_clone),
66 _register_save_policy(register_save_policy),
67 _c_reg_save_policy(c_reg_save_policy),
68 _register_save_type(register_save_type),
69 _ruleName(ruleName),
70 _allocation_started(false),
71 _states_arena(Chunk::medium_size),
72 _visited(&_states_arena),
73 _shared(&_states_arena),
74 _dontcare(&_states_arena) {
75 C->set_matcher(this);
76
77 idealreg2spillmask [Op_RegI] = NULL;
78 idealreg2spillmask [Op_RegN] = NULL;
79 idealreg2spillmask [Op_RegL] = NULL;
80 idealreg2spillmask [Op_RegF] = NULL;
81 idealreg2spillmask [Op_RegD] = NULL;
82 idealreg2spillmask [Op_RegP] = NULL;
83 idealreg2spillmask [Op_VecS] = NULL;
84 idealreg2spillmask [Op_VecD] = NULL;
85 idealreg2spillmask [Op_VecX] = NULL;
86 idealreg2spillmask [Op_VecY] = NULL;
87 idealreg2spillmask [Op_VecZ] = NULL;
88
89 idealreg2debugmask [Op_RegI] = NULL;
90 idealreg2debugmask [Op_RegN] = NULL;
91 idealreg2debugmask [Op_RegL] = NULL;
92 idealreg2debugmask [Op_RegF] = NULL;
93 idealreg2debugmask [Op_RegD] = NULL;
94 idealreg2debugmask [Op_RegP] = NULL;
95 idealreg2debugmask [Op_VecS] = NULL;
96 idealreg2debugmask [Op_VecD] = NULL;
97 idealreg2debugmask [Op_VecX] = NULL;
98 idealreg2debugmask [Op_VecY] = NULL;
99 idealreg2debugmask [Op_VecZ] = NULL;
100
101 idealreg2mhdebugmask[Op_RegI] = NULL;
102 idealreg2mhdebugmask[Op_RegN] = NULL;
103 idealreg2mhdebugmask[Op_RegL] = NULL;
104 idealreg2mhdebugmask[Op_RegF] = NULL;
105 idealreg2mhdebugmask[Op_RegD] = NULL;
106 idealreg2mhdebugmask[Op_RegP] = NULL;
107 idealreg2mhdebugmask[Op_VecS] = NULL;
108 idealreg2mhdebugmask[Op_VecD] = NULL;
109 idealreg2mhdebugmask[Op_VecX] = NULL;
110 idealreg2mhdebugmask[Op_VecY] = NULL;
111 idealreg2mhdebugmask[Op_VecZ] = NULL;
112
113 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
114 }
115
116 //------------------------------warp_incoming_stk_arg------------------------
117 // This warps a VMReg into an OptoReg::Name
118 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
119 OptoReg::Name warped;
120 if( reg->is_stack() ) { // Stack slot argument?
121 warped = OptoReg::add(_old_SP, reg->reg2stack() );
122 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
123 if( warped >= _in_arg_limit )
124 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
125 if (!RegMask::can_represent_arg(warped)) {
126 // the compiler cannot represent this method's calling sequence
127 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
128 return OptoReg::Bad;
129 }
130 return warped;
131 }
132 return OptoReg::as_OptoReg(reg);
133 }
134
135 //---------------------------compute_old_SP------------------------------------
136 OptoReg::Name Compile::compute_old_SP() {
137 int fixed = fixed_slots();
138 int preserve = in_preserve_stack_slots();
139 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
140 }
141
142
143
144 #ifdef ASSERT
145 void Matcher::verify_new_nodes_only(Node* xroot) {
146 // Make sure that the new graph only references new nodes
147 ResourceMark rm;
148 Unique_Node_List worklist;
149 VectorSet visited(Thread::current()->resource_area());
150 worklist.push(xroot);
151 while (worklist.size() > 0) {
152 Node* n = worklist.pop();
153 visited <<= n->_idx;
154 assert(C->node_arena()->contains(n), "dead node");
155 for (uint j = 0; j < n->req(); j++) {
156 Node* in = n->in(j);
157 if (in != NULL) {
158 assert(C->node_arena()->contains(in), "dead node");
159 if (!visited.test(in->_idx)) {
160 worklist.push(in);
161 }
162 }
163 }
164 }
165 }
166 #endif
167
168
169 //---------------------------match---------------------------------------------
170 void Matcher::match( ) {
171 if( MaxLabelRootDepth < 100 ) { // Too small?
172 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
173 MaxLabelRootDepth = 100;
174 }
175 // One-time initialization of some register masks.
176 init_spill_mask( C->root()->in(1) );
177 _return_addr_mask = return_addr();
178 #ifdef _LP64
179 // Pointers take 2 slots in 64-bit land
180 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
181 #endif
182
183 // Map a Java-signature return type into return register-value
184 // machine registers for 0, 1 and 2 returned values.
185 const TypeTuple *range = C->tf()->range();
186 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
187 // Get ideal-register return type
188 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
189 // Get machine return register
190 uint sop = C->start()->Opcode();
191 OptoRegPair regs = return_value(ireg, false);
192
193 // And mask for same
194 _return_value_mask = RegMask(regs.first());
195 if( OptoReg::is_valid(regs.second()) )
196 _return_value_mask.Insert(regs.second());
197 }
198
199 // ---------------
200 // Frame Layout
201
202 // Need the method signature to determine the incoming argument types,
203 // because the types determine which registers the incoming arguments are
204 // in, and this affects the matched code.
205 const TypeTuple *domain = C->tf()->domain();
206 uint argcnt = domain->cnt() - TypeFunc::Parms;
207 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
208 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
209 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
210 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
211 uint i;
212 for( i = 0; i<argcnt; i++ ) {
213 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
214 }
215
216 // Pass array of ideal registers and length to USER code (from the AD file)
217 // that will convert this to an array of register numbers.
218 const StartNode *start = C->start();
219 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
220 #ifdef ASSERT
221 // Sanity check users' calling convention. Real handy while trying to
222 // get the initial port correct.
223 { for (uint i = 0; i<argcnt; i++) {
224 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
225 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
226 _parm_regs[i].set_bad();
227 continue;
228 }
229 VMReg parm_reg = vm_parm_regs[i].first();
230 assert(parm_reg->is_valid(), "invalid arg?");
231 if (parm_reg->is_reg()) {
232 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
233 assert(can_be_java_arg(opto_parm_reg) ||
234 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
235 opto_parm_reg == inline_cache_reg(),
236 "parameters in register must be preserved by runtime stubs");
237 }
238 for (uint j = 0; j < i; j++) {
239 assert(parm_reg != vm_parm_regs[j].first(),
240 "calling conv. must produce distinct regs");
241 }
242 }
243 }
244 #endif
245
246 // Do some initial frame layout.
247
248 // Compute the old incoming SP (may be called FP) as
249 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
250 _old_SP = C->compute_old_SP();
251 assert( is_even(_old_SP), "must be even" );
252
253 // Compute highest incoming stack argument as
254 // _old_SP + out_preserve_stack_slots + incoming argument size.
255 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
256 assert( is_even(_in_arg_limit), "out_preserve must be even" );
257 for( i = 0; i < argcnt; i++ ) {
258 // Permit args to have no register
259 _calling_convention_mask[i].Clear();
260 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
261 continue;
262 }
263 // calling_convention returns stack arguments as a count of
264 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
265 // the allocators point of view, taking into account all the
266 // preserve area, locks & pad2.
267
268 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
269 if( OptoReg::is_valid(reg1))
270 _calling_convention_mask[i].Insert(reg1);
271
272 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
273 if( OptoReg::is_valid(reg2))
274 _calling_convention_mask[i].Insert(reg2);
275
276 // Saved biased stack-slot register number
277 _parm_regs[i].set_pair(reg2, reg1);
278 }
279
280 // Finally, make sure the incoming arguments take up an even number of
281 // words, in case the arguments or locals need to contain doubleword stack
282 // slots. The rest of the system assumes that stack slot pairs (in
283 // particular, in the spill area) which look aligned will in fact be
284 // aligned relative to the stack pointer in the target machine. Double
285 // stack slots will always be allocated aligned.
286 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
287
288 // Compute highest outgoing stack argument as
289 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
290 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
291 assert( is_even(_out_arg_limit), "out_preserve must be even" );
292
293 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
294 // the compiler cannot represent this method's calling sequence
295 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
296 }
297
298 if (C->failing()) return; // bailed out on incoming arg failure
299
300 // ---------------
301 // Collect roots of matcher trees. Every node for which
302 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
303 // can be a valid interior of some tree.
304 find_shared( C->root() );
305 find_shared( C->top() );
306
307 C->print_method(PHASE_BEFORE_MATCHING);
308
309 // Create new ideal node ConP #NULL even if it does exist in old space
310 // to avoid false sharing if the corresponding mach node is not used.
311 // The corresponding mach node is only used in rare cases for derived
312 // pointers.
313 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
314
315 // Swap out to old-space; emptying new-space
316 Arena *old = C->node_arena()->move_contents(C->old_arena());
317
318 // Save debug and profile information for nodes in old space:
319 _old_node_note_array = C->node_note_array();
320 if (_old_node_note_array != NULL) {
321 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
322 (C->comp_arena(), _old_node_note_array->length(),
323 0, NULL));
324 }
325
326 // Pre-size the new_node table to avoid the need for range checks.
327 grow_new_node_array(C->unique());
328
329 // Reset node counter so MachNodes start with _idx at 0
330 int live_nodes = C->live_nodes();
331 C->set_unique(0);
332 C->reset_dead_node_list();
333
334 // Recursively match trees from old space into new space.
335 // Correct leaves of new-space Nodes; they point to old-space.
336 _visited.Clear(); // Clear visit bits for xform call
337 C->set_cached_top_node(xform( C->top(), live_nodes ));
338 if (!C->failing()) {
339 Node* xroot = xform( C->root(), 1 );
340 if (xroot == NULL) {
341 Matcher::soft_match_failure(); // recursive matching process failed
342 C->record_method_not_compilable("instruction match failed");
343 } else {
344 // During matching shared constants were attached to C->root()
345 // because xroot wasn't available yet, so transfer the uses to
346 // the xroot.
347 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
348 Node* n = C->root()->fast_out(j);
349 if (C->node_arena()->contains(n)) {
350 assert(n->in(0) == C->root(), "should be control user");
351 n->set_req(0, xroot);
352 --j;
353 --jmax;
354 }
355 }
356
357 // Generate new mach node for ConP #NULL
358 assert(new_ideal_null != NULL, "sanity");
359 _mach_null = match_tree(new_ideal_null);
360 // Don't set control, it will confuse GCM since there are no uses.
361 // The control will be set when this node is used first time
362 // in find_base_for_derived().
363 assert(_mach_null != NULL, "");
364
365 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
366
367 #ifdef ASSERT
368 verify_new_nodes_only(xroot);
369 #endif
370 }
371 }
372 if (C->top() == NULL || C->root() == NULL) {
373 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
374 }
375 if (C->failing()) {
376 // delete old;
377 old->destruct_contents();
378 return;
379 }
380 assert( C->top(), "" );
381 assert( C->root(), "" );
382 validate_null_checks();
383
384 // Now smoke old-space
385 NOT_DEBUG( old->destruct_contents() );
386
387 // ------------------------
388 // Set up save-on-entry registers
389 Fixup_Save_On_Entry( );
390 }
391
392
393 //------------------------------Fixup_Save_On_Entry----------------------------
394 // The stated purpose of this routine is to take care of save-on-entry
395 // registers. However, the overall goal of the Match phase is to convert into
396 // machine-specific instructions which have RegMasks to guide allocation.
397 // So what this procedure really does is put a valid RegMask on each input
398 // to the machine-specific variations of all Return, TailCall and Halt
399 // instructions. It also adds edgs to define the save-on-entry values (and of
400 // course gives them a mask).
401
402 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
403 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
404 // Do all the pre-defined register masks
405 rms[TypeFunc::Control ] = RegMask::Empty;
406 rms[TypeFunc::I_O ] = RegMask::Empty;
407 rms[TypeFunc::Memory ] = RegMask::Empty;
408 rms[TypeFunc::ReturnAdr] = ret_adr;
409 rms[TypeFunc::FramePtr ] = fp;
410 return rms;
411 }
412
413 //---------------------------init_first_stack_mask-----------------------------
414 // Create the initial stack mask used by values spilling to the stack.
415 // Disallow any debug info in outgoing argument areas by setting the
416 // initial mask accordingly.
417 void Matcher::init_first_stack_mask() {
418
419 // Allocate storage for spill masks as masks for the appropriate load type.
420 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
421
422 idealreg2spillmask [Op_RegN] = &rms[0];
423 idealreg2spillmask [Op_RegI] = &rms[1];
424 idealreg2spillmask [Op_RegL] = &rms[2];
425 idealreg2spillmask [Op_RegF] = &rms[3];
426 idealreg2spillmask [Op_RegD] = &rms[4];
427 idealreg2spillmask [Op_RegP] = &rms[5];
428
429 idealreg2debugmask [Op_RegN] = &rms[6];
430 idealreg2debugmask [Op_RegI] = &rms[7];
431 idealreg2debugmask [Op_RegL] = &rms[8];
432 idealreg2debugmask [Op_RegF] = &rms[9];
433 idealreg2debugmask [Op_RegD] = &rms[10];
434 idealreg2debugmask [Op_RegP] = &rms[11];
435
436 idealreg2mhdebugmask[Op_RegN] = &rms[12];
437 idealreg2mhdebugmask[Op_RegI] = &rms[13];
438 idealreg2mhdebugmask[Op_RegL] = &rms[14];
439 idealreg2mhdebugmask[Op_RegF] = &rms[15];
440 idealreg2mhdebugmask[Op_RegD] = &rms[16];
441 idealreg2mhdebugmask[Op_RegP] = &rms[17];
442
443 idealreg2spillmask [Op_VecS] = &rms[18];
444 idealreg2spillmask [Op_VecD] = &rms[19];
445 idealreg2spillmask [Op_VecX] = &rms[20];
446 idealreg2spillmask [Op_VecY] = &rms[21];
447 idealreg2spillmask [Op_VecZ] = &rms[22];
448
449 OptoReg::Name i;
450
451 // At first, start with the empty mask
452 C->FIRST_STACK_mask().Clear();
453
454 // Add in the incoming argument area
455 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
456 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
457 C->FIRST_STACK_mask().Insert(i);
458 }
459 // Add in all bits past the outgoing argument area
460 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
461 "must be able to represent all call arguments in reg mask");
462 OptoReg::Name init = _out_arg_limit;
463 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
464 C->FIRST_STACK_mask().Insert(i);
465 }
466 // Finally, set the "infinite stack" bit.
467 C->FIRST_STACK_mask().set_AllStack();
468
469 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
470 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
471 // Keep spill masks aligned.
472 aligned_stack_mask.clear_to_pairs();
473 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
474
475 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
476 #ifdef _LP64
477 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
478 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
479 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
480 #else
481 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
482 #endif
483 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
484 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
485 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
486 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
487 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
488 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
489 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
490 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
491
492 if (Matcher::vector_size_supported(T_BYTE,4)) {
493 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
494 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
495 }
496 if (Matcher::vector_size_supported(T_FLOAT,2)) {
497 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
498 // RA guarantees such alignment since it is needed for Double and Long values.
499 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
500 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
501 }
502 if (Matcher::vector_size_supported(T_FLOAT,4)) {
503 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
504 //
505 // RA can use input arguments stack slots for spills but until RA
506 // we don't know frame size and offset of input arg stack slots.
507 //
508 // Exclude last input arg stack slots to avoid spilling vectors there
509 // otherwise vector spills could stomp over stack slots in caller frame.
510 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
511 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
512 aligned_stack_mask.Remove(in);
513 in = OptoReg::add(in, -1);
514 }
515 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
516 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
517 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
518 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
519 }
520 if (Matcher::vector_size_supported(T_FLOAT,8)) {
521 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
522 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
523 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
524 aligned_stack_mask.Remove(in);
525 in = OptoReg::add(in, -1);
526 }
527 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
528 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
529 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
530 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
531 }
532 if (Matcher::vector_size_supported(T_FLOAT,16)) {
533 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
534 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
535 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
536 aligned_stack_mask.Remove(in);
537 in = OptoReg::add(in, -1);
538 }
539 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
540 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
541 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
542 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
543 }
544 if (UseFPUForSpilling) {
545 // This mask logic assumes that the spill operations are
546 // symmetric and that the registers involved are the same size.
547 // On sparc for instance we may have to use 64 bit moves will
548 // kill 2 registers when used with F0-F31.
549 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
550 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
551 #ifdef _LP64
552 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
553 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
554 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
555 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
556 #else
557 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
558 #ifdef ARM
559 // ARM has support for moving 64bit values between a pair of
560 // integer registers and a double register
561 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
562 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
563 #endif
564 #endif
565 }
566
567 // Make up debug masks. Any spill slot plus callee-save registers.
568 // Caller-save registers are assumed to be trashable by the various
569 // inline-cache fixup routines.
570 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
571 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
572 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
573 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
574 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
575 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
576
577 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
578 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
579 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
580 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
581 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
582 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
583
584 // Prevent stub compilations from attempting to reference
585 // callee-saved registers from debug info
586 bool exclude_soe = !Compile::current()->is_method_compilation();
587
588 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
589 // registers the caller has to save do not work
590 if( _register_save_policy[i] == 'C' ||
591 _register_save_policy[i] == 'A' ||
592 (_register_save_policy[i] == 'E' && exclude_soe) ) {
593 idealreg2debugmask [Op_RegN]->Remove(i);
594 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
595 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
596 idealreg2debugmask [Op_RegF]->Remove(i); // masks
597 idealreg2debugmask [Op_RegD]->Remove(i);
598 idealreg2debugmask [Op_RegP]->Remove(i);
599
600 idealreg2mhdebugmask[Op_RegN]->Remove(i);
601 idealreg2mhdebugmask[Op_RegI]->Remove(i);
602 idealreg2mhdebugmask[Op_RegL]->Remove(i);
603 idealreg2mhdebugmask[Op_RegF]->Remove(i);
604 idealreg2mhdebugmask[Op_RegD]->Remove(i);
605 idealreg2mhdebugmask[Op_RegP]->Remove(i);
606 }
607 }
608
609 // Subtract the register we use to save the SP for MethodHandle
610 // invokes to from the debug mask.
611 const RegMask save_mask = method_handle_invoke_SP_save_mask();
612 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
618 }
619
620 //---------------------------is_save_on_entry----------------------------------
621 bool Matcher::is_save_on_entry( int reg ) {
622 return
623 _register_save_policy[reg] == 'E' ||
624 _register_save_policy[reg] == 'A' || // Save-on-entry register?
625 // Also save argument registers in the trampolining stubs
626 (C->save_argument_registers() && is_spillable_arg(reg));
627 }
628
629 //---------------------------Fixup_Save_On_Entry-------------------------------
630 void Matcher::Fixup_Save_On_Entry( ) {
631 init_first_stack_mask();
632
633 Node *root = C->root(); // Short name for root
634 // Count number of save-on-entry registers.
635 uint soe_cnt = number_of_saved_registers();
636 uint i;
637
638 // Find the procedure Start Node
639 StartNode *start = C->start();
640 assert( start, "Expect a start node" );
641
642 // Save argument registers in the trampolining stubs
643 if( C->save_argument_registers() )
644 for( i = 0; i < _last_Mach_Reg; i++ )
645 if( is_spillable_arg(i) )
646 soe_cnt++;
647
648 // Input RegMask array shared by all Returns.
649 // The type for doubles and longs has a count of 2, but
650 // there is only 1 returned value
651 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
652 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
653 // Returns have 0 or 1 returned values depending on call signature.
654 // Return register is specified by return_value in the AD file.
655 if (ret_edge_cnt > TypeFunc::Parms)
656 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
657
658 // Input RegMask array shared by all Rethrows.
659 uint reth_edge_cnt = TypeFunc::Parms+1;
660 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
661 // Rethrow takes exception oop only, but in the argument 0 slot.
662 OptoReg::Name reg = find_receiver(false);
663 if (reg >= 0) {
664 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
665 #ifdef _LP64
666 // Need two slots for ptrs in 64-bit land
667 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
668 #endif
669 }
670
671 // Input RegMask array shared by all TailCalls
672 uint tail_call_edge_cnt = TypeFunc::Parms+2;
673 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
674
675 // Input RegMask array shared by all TailJumps
676 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
677 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
678
679 // TailCalls have 2 returned values (target & moop), whose masks come
680 // from the usual MachNode/MachOper mechanism. Find a sample
681 // TailCall to extract these masks and put the correct masks into
682 // the tail_call_rms array.
683 for( i=1; i < root->req(); i++ ) {
684 MachReturnNode *m = root->in(i)->as_MachReturn();
685 if( m->ideal_Opcode() == Op_TailCall ) {
686 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
687 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
688 break;
689 }
690 }
691
692 // TailJumps have 2 returned values (target & ex_oop), whose masks come
693 // from the usual MachNode/MachOper mechanism. Find a sample
694 // TailJump to extract these masks and put the correct masks into
695 // the tail_jump_rms array.
696 for( i=1; i < root->req(); i++ ) {
697 MachReturnNode *m = root->in(i)->as_MachReturn();
698 if( m->ideal_Opcode() == Op_TailJump ) {
699 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
700 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
701 break;
702 }
703 }
704
705 // Input RegMask array shared by all Halts
706 uint halt_edge_cnt = TypeFunc::Parms;
707 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
708
709 // Capture the return input masks into each exit flavor
710 for( i=1; i < root->req(); i++ ) {
711 MachReturnNode *exit = root->in(i)->as_MachReturn();
712 switch( exit->ideal_Opcode() ) {
713 case Op_Return : exit->_in_rms = ret_rms; break;
714 case Op_Rethrow : exit->_in_rms = reth_rms; break;
715 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
716 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
717 case Op_Halt : exit->_in_rms = halt_rms; break;
718 default : ShouldNotReachHere();
719 }
720 }
721
722 // Next unused projection number from Start.
723 int proj_cnt = C->tf()->domain()->cnt();
724
725 // Do all the save-on-entry registers. Make projections from Start for
726 // them, and give them a use at the exit points. To the allocator, they
727 // look like incoming register arguments.
728 for( i = 0; i < _last_Mach_Reg; i++ ) {
729 if( is_save_on_entry(i) ) {
730
731 // Add the save-on-entry to the mask array
732 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
733 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
734 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
735 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
736 // Halts need the SOE registers, but only in the stack as debug info.
737 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
738 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
739
740 Node *mproj;
741
742 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
743 // into a single RegD.
744 if( (i&1) == 0 &&
745 _register_save_type[i ] == Op_RegF &&
746 _register_save_type[i+1] == Op_RegF &&
747 is_save_on_entry(i+1) ) {
748 // Add other bit for double
749 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
750 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
751 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
752 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
753 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
754 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
755 proj_cnt += 2; // Skip 2 for doubles
756 }
757 else if( (i&1) == 1 && // Else check for high half of double
758 _register_save_type[i-1] == Op_RegF &&
759 _register_save_type[i ] == Op_RegF &&
760 is_save_on_entry(i-1) ) {
761 ret_rms [ ret_edge_cnt] = RegMask::Empty;
762 reth_rms [ reth_edge_cnt] = RegMask::Empty;
763 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
764 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
765 halt_rms [ halt_edge_cnt] = RegMask::Empty;
766 mproj = C->top();
767 }
768 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
769 // into a single RegL.
770 else if( (i&1) == 0 &&
771 _register_save_type[i ] == Op_RegI &&
772 _register_save_type[i+1] == Op_RegI &&
773 is_save_on_entry(i+1) ) {
774 // Add other bit for long
775 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
776 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
777 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
778 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
779 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
780 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
781 proj_cnt += 2; // Skip 2 for longs
782 }
783 else if( (i&1) == 1 && // Else check for high half of long
784 _register_save_type[i-1] == Op_RegI &&
785 _register_save_type[i ] == Op_RegI &&
786 is_save_on_entry(i-1) ) {
787 ret_rms [ ret_edge_cnt] = RegMask::Empty;
788 reth_rms [ reth_edge_cnt] = RegMask::Empty;
789 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
790 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
791 halt_rms [ halt_edge_cnt] = RegMask::Empty;
792 mproj = C->top();
793 } else {
794 // Make a projection for it off the Start
795 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
796 }
797
798 ret_edge_cnt ++;
799 reth_edge_cnt ++;
800 tail_call_edge_cnt ++;
801 tail_jump_edge_cnt ++;
802 halt_edge_cnt ++;
803
804 // Add a use of the SOE register to all exit paths
805 for( uint j=1; j < root->req(); j++ )
806 root->in(j)->add_req(mproj);
807 } // End of if a save-on-entry register
808 } // End of for all machine registers
809 }
810
811 //------------------------------init_spill_mask--------------------------------
812 void Matcher::init_spill_mask( Node *ret ) {
813 if( idealreg2regmask[Op_RegI] ) return; // One time only init
814
815 OptoReg::c_frame_pointer = c_frame_pointer();
816 c_frame_ptr_mask = c_frame_pointer();
817 #ifdef _LP64
818 // pointers are twice as big
819 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
820 #endif
821
822 // Start at OptoReg::stack0()
823 STACK_ONLY_mask.Clear();
824 OptoReg::Name init = OptoReg::stack2reg(0);
825 // STACK_ONLY_mask is all stack bits
826 OptoReg::Name i;
827 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
828 STACK_ONLY_mask.Insert(i);
829 // Also set the "infinite stack" bit.
830 STACK_ONLY_mask.set_AllStack();
831
832 // Copy the register names over into the shared world
833 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
834 // SharedInfo::regName[i] = regName[i];
835 // Handy RegMasks per machine register
836 mreg2regmask[i].Insert(i);
837 }
838
839 // Grab the Frame Pointer
840 Node *fp = ret->in(TypeFunc::FramePtr);
841 Node *mem = ret->in(TypeFunc::Memory);
842 const TypePtr* atp = TypePtr::BOTTOM;
843 // Share frame pointer while making spill ops
844 set_shared(fp);
845
846 // Compute generic short-offset Loads
847 #ifdef _LP64
848 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
849 #endif
850 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
851 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
852 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
853 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
854 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
855 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
856 spillD != NULL && spillP != NULL, "");
857 // Get the ADLC notion of the right regmask, for each basic type.
858 #ifdef _LP64
859 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
860 #endif
861 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
862 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
863 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
864 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
865 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
866
867 // Vector regmasks.
868 if (Matcher::vector_size_supported(T_BYTE,4)) {
869 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
870 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
871 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
872 }
873 if (Matcher::vector_size_supported(T_FLOAT,2)) {
874 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
875 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
876 }
877 if (Matcher::vector_size_supported(T_FLOAT,4)) {
878 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
879 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
880 }
881 if (Matcher::vector_size_supported(T_FLOAT,8)) {
882 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
883 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
884 }
885 if (Matcher::vector_size_supported(T_FLOAT,16)) {
886 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
887 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
888 }
889 }
890
891 #ifdef ASSERT
892 static void match_alias_type(Compile* C, Node* n, Node* m) {
893 if (!VerifyAliases) return; // do not go looking for trouble by default
894 const TypePtr* nat = n->adr_type();
895 const TypePtr* mat = m->adr_type();
896 int nidx = C->get_alias_index(nat);
897 int midx = C->get_alias_index(mat);
898 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
899 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
900 for (uint i = 1; i < n->req(); i++) {
901 Node* n1 = n->in(i);
902 const TypePtr* n1at = n1->adr_type();
903 if (n1at != NULL) {
904 nat = n1at;
905 nidx = C->get_alias_index(n1at);
906 }
907 }
908 }
909 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
910 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
911 switch (n->Opcode()) {
912 case Op_PrefetchAllocation:
913 nidx = Compile::AliasIdxRaw;
914 nat = TypeRawPtr::BOTTOM;
915 break;
916 }
917 }
918 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
919 switch (n->Opcode()) {
920 case Op_ClearArray:
921 midx = Compile::AliasIdxRaw;
922 mat = TypeRawPtr::BOTTOM;
923 break;
924 }
925 }
926 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
927 switch (n->Opcode()) {
928 case Op_Return:
929 case Op_Rethrow:
930 case Op_Halt:
931 case Op_TailCall:
932 case Op_TailJump:
933 nidx = Compile::AliasIdxBot;
934 nat = TypePtr::BOTTOM;
935 break;
936 }
937 }
938 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
939 switch (n->Opcode()) {
940 case Op_StrComp:
941 case Op_StrEquals:
942 case Op_StrIndexOf:
943 case Op_StrIndexOfChar:
944 case Op_AryEq:
945 case Op_HasNegatives:
946 case Op_MemBarVolatile:
947 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
948 case Op_StrInflatedCopy:
949 case Op_StrCompressedCopy:
950 case Op_OnSpinWait:
951 case Op_EncodeISOArray:
952 nidx = Compile::AliasIdxTop;
953 nat = NULL;
954 break;
955 }
956 }
957 if (nidx != midx) {
958 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
959 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
960 n->dump();
961 m->dump();
962 }
963 assert(C->subsume_loads() && C->must_alias(nat, midx),
964 "must not lose alias info when matching");
965 }
966 }
967 #endif
968
969
970 //------------------------------MStack-----------------------------------------
971 // State and MStack class used in xform() and find_shared() iterative methods.
972 enum Node_State { Pre_Visit, // node has to be pre-visited
973 Visit, // visit node
974 Post_Visit, // post-visit node
975 Alt_Post_Visit // alternative post-visit path
976 };
977
978 class MStack: public Node_Stack {
979 public:
980 MStack(int size) : Node_Stack(size) { }
981
982 void push(Node *n, Node_State ns) {
983 Node_Stack::push(n, (uint)ns);
984 }
985 void push(Node *n, Node_State ns, Node *parent, int indx) {
986 ++_inode_top;
987 if ((_inode_top + 1) >= _inode_max) grow();
988 _inode_top->node = parent;
989 _inode_top->indx = (uint)indx;
990 ++_inode_top;
991 _inode_top->node = n;
992 _inode_top->indx = (uint)ns;
993 }
994 Node *parent() {
995 pop();
996 return node();
997 }
998 Node_State state() const {
999 return (Node_State)index();
1000 }
1001 void set_state(Node_State ns) {
1002 set_index((uint)ns);
1003 }
1004 };
1005
1006
1007 //------------------------------xform------------------------------------------
1008 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1009 // Node in new-space. Given a new-space Node, recursively walk his children.
1010 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1011 Node *Matcher::xform( Node *n, int max_stack ) {
1012 // Use one stack to keep both: child's node/state and parent's node/index
1013 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1014 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1015
1016 while (mstack.is_nonempty()) {
1017 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1018 if (C->failing()) return NULL;
1019 n = mstack.node(); // Leave node on stack
1020 Node_State nstate = mstack.state();
1021 if (nstate == Visit) {
1022 mstack.set_state(Post_Visit);
1023 Node *oldn = n;
1024 // Old-space or new-space check
1025 if (!C->node_arena()->contains(n)) {
1026 // Old space!
1027 Node* m;
1028 if (has_new_node(n)) { // Not yet Label/Reduced
1029 m = new_node(n);
1030 } else {
1031 if (!is_dontcare(n)) { // Matcher can match this guy
1032 // Calls match special. They match alone with no children.
1033 // Their children, the incoming arguments, match normally.
1034 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1035 if (C->failing()) return NULL;
1036 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1037 } else { // Nothing the matcher cares about
1038 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1039 // Convert to machine-dependent projection
1040 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1041 #ifdef ASSERT
1042 _new2old_map.map(m->_idx, n);
1043 #endif
1044 if (m->in(0) != NULL) // m might be top
1045 collect_null_checks(m, n);
1046 } else { // Else just a regular 'ol guy
1047 m = n->clone(); // So just clone into new-space
1048 #ifdef ASSERT
1049 _new2old_map.map(m->_idx, n);
1050 #endif
1051 // Def-Use edges will be added incrementally as Uses
1052 // of this node are matched.
1053 assert(m->outcnt() == 0, "no Uses of this clone yet");
1054 }
1055 }
1056
1057 set_new_node(n, m); // Map old to new
1058 if (_old_node_note_array != NULL) {
1059 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1060 n->_idx);
1061 C->set_node_notes_at(m->_idx, nn);
1062 }
1063 debug_only(match_alias_type(C, n, m));
1064 }
1065 n = m; // n is now a new-space node
1066 mstack.set_node(n);
1067 }
1068
1069 // New space!
1070 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1071
1072 int i;
1073 // Put precedence edges on stack first (match them last).
1074 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1075 Node *m = oldn->in(i);
1076 if (m == NULL) break;
1077 // set -1 to call add_prec() instead of set_req() during Step1
1078 mstack.push(m, Visit, n, -1);
1079 }
1080
1081 // Handle precedence edges for interior nodes
1082 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1083 Node *m = n->in(i);
1084 if (m == NULL || C->node_arena()->contains(m)) continue;
1085 n->rm_prec(i);
1086 // set -1 to call add_prec() instead of set_req() during Step1
1087 mstack.push(m, Visit, n, -1);
1088 }
1089
1090 // For constant debug info, I'd rather have unmatched constants.
1091 int cnt = n->req();
1092 JVMState* jvms = n->jvms();
1093 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1094
1095 // Now do only debug info. Clone constants rather than matching.
1096 // Constants are represented directly in the debug info without
1097 // the need for executable machine instructions.
1098 // Monitor boxes are also represented directly.
1099 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1100 Node *m = n->in(i); // Get input
1101 int op = m->Opcode();
1102 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1103 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1104 op == Op_ConF || op == Op_ConD || op == Op_ConL
1105 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1106 ) {
1107 m = m->clone();
1108 #ifdef ASSERT
1109 _new2old_map.map(m->_idx, n);
1110 #endif
1111 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1112 mstack.push(m->in(0), Visit, m, 0);
1113 } else {
1114 mstack.push(m, Visit, n, i);
1115 }
1116 }
1117
1118 // And now walk his children, and convert his inputs to new-space.
1119 for( ; i >= 0; --i ) { // For all normal inputs do
1120 Node *m = n->in(i); // Get input
1121 if(m != NULL)
1122 mstack.push(m, Visit, n, i);
1123 }
1124
1125 }
1126 else if (nstate == Post_Visit) {
1127 // Set xformed input
1128 Node *p = mstack.parent();
1129 if (p != NULL) { // root doesn't have parent
1130 int i = (int)mstack.index();
1131 if (i >= 0)
1132 p->set_req(i, n); // required input
1133 else if (i == -1)
1134 p->add_prec(n); // precedence input
1135 else
1136 ShouldNotReachHere();
1137 }
1138 mstack.pop(); // remove processed node from stack
1139 }
1140 else {
1141 ShouldNotReachHere();
1142 }
1143 } // while (mstack.is_nonempty())
1144 return n; // Return new-space Node
1145 }
1146
1147 //------------------------------warp_outgoing_stk_arg------------------------
1148 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1149 // Convert outgoing argument location to a pre-biased stack offset
1150 if (reg->is_stack()) {
1151 OptoReg::Name warped = reg->reg2stack();
1152 // Adjust the stack slot offset to be the register number used
1153 // by the allocator.
1154 warped = OptoReg::add(begin_out_arg_area, warped);
1155 // Keep track of the largest numbered stack slot used for an arg.
1156 // Largest used slot per call-site indicates the amount of stack
1157 // that is killed by the call.
1158 if( warped >= out_arg_limit_per_call )
1159 out_arg_limit_per_call = OptoReg::add(warped,1);
1160 if (!RegMask::can_represent_arg(warped)) {
1161 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1162 return OptoReg::Bad;
1163 }
1164 return warped;
1165 }
1166 return OptoReg::as_OptoReg(reg);
1167 }
1168
1169
1170 //------------------------------match_sfpt-------------------------------------
1171 // Helper function to match call instructions. Calls match special.
1172 // They match alone with no children. Their children, the incoming
1173 // arguments, match normally.
1174 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1175 MachSafePointNode *msfpt = NULL;
1176 MachCallNode *mcall = NULL;
1177 uint cnt;
1178 // Split out case for SafePoint vs Call
1179 CallNode *call;
1180 const TypeTuple *domain;
1181 ciMethod* method = NULL;
1182 bool is_method_handle_invoke = false; // for special kill effects
1183 if( sfpt->is_Call() ) {
1184 call = sfpt->as_Call();
1185 domain = call->tf()->domain();
1186 cnt = domain->cnt();
1187
1188 // Match just the call, nothing else
1189 MachNode *m = match_tree(call);
1190 if (C->failing()) return NULL;
1191 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1192
1193 // Copy data from the Ideal SafePoint to the machine version
1194 mcall = m->as_MachCall();
1195
1196 mcall->set_tf( call->tf());
1197 mcall->set_entry_point(call->entry_point());
1198 mcall->set_cnt( call->cnt());
1199
1200 if( mcall->is_MachCallJava() ) {
1201 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1202 const CallJavaNode *call_java = call->as_CallJava();
1203 method = call_java->method();
1204 mcall_java->_method = method;
1205 mcall_java->_bci = call_java->_bci;
1206 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1207 is_method_handle_invoke = call_java->is_method_handle_invoke();
1208 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1209 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1210 if (is_method_handle_invoke) {
1211 C->set_has_method_handle_invokes(true);
1212 }
1213 if( mcall_java->is_MachCallStaticJava() )
1214 mcall_java->as_MachCallStaticJava()->_name =
1215 call_java->as_CallStaticJava()->_name;
1216 if( mcall_java->is_MachCallDynamicJava() )
1217 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1218 call_java->as_CallDynamicJava()->_vtable_index;
1219 }
1220 else if( mcall->is_MachCallRuntime() ) {
1221 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1222 }
1223 msfpt = mcall;
1224 }
1225 // This is a non-call safepoint
1226 else {
1227 call = NULL;
1228 domain = NULL;
1229 MachNode *mn = match_tree(sfpt);
1230 if (C->failing()) return NULL;
1231 msfpt = mn->as_MachSafePoint();
1232 cnt = TypeFunc::Parms;
1233 }
1234
1235 // Advertise the correct memory effects (for anti-dependence computation).
1236 msfpt->set_adr_type(sfpt->adr_type());
1237
1238 // Allocate a private array of RegMasks. These RegMasks are not shared.
1239 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1240 // Empty them all.
1241 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1242
1243 // Do all the pre-defined non-Empty register masks
1244 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1245 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1246
1247 // Place first outgoing argument can possibly be put.
1248 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1249 assert( is_even(begin_out_arg_area), "" );
1250 // Compute max outgoing register number per call site.
1251 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1252 // Calls to C may hammer extra stack slots above and beyond any arguments.
1253 // These are usually backing store for register arguments for varargs.
1254 if( call != NULL && call->is_CallRuntime() )
1255 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1256
1257
1258 // Do the normal argument list (parameters) register masks
1259 int argcnt = cnt - TypeFunc::Parms;
1260 if( argcnt > 0 ) { // Skip it all if we have no args
1261 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1262 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1263 int i;
1264 for( i = 0; i < argcnt; i++ ) {
1265 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1266 }
1267 // V-call to pick proper calling convention
1268 call->calling_convention( sig_bt, parm_regs, argcnt );
1269
1270 #ifdef ASSERT
1271 // Sanity check users' calling convention. Really handy during
1272 // the initial porting effort. Fairly expensive otherwise.
1273 { for (int i = 0; i<argcnt; i++) {
1274 if( !parm_regs[i].first()->is_valid() &&
1275 !parm_regs[i].second()->is_valid() ) continue;
1276 VMReg reg1 = parm_regs[i].first();
1277 VMReg reg2 = parm_regs[i].second();
1278 for (int j = 0; j < i; j++) {
1279 if( !parm_regs[j].first()->is_valid() &&
1280 !parm_regs[j].second()->is_valid() ) continue;
1281 VMReg reg3 = parm_regs[j].first();
1282 VMReg reg4 = parm_regs[j].second();
1283 if( !reg1->is_valid() ) {
1284 assert( !reg2->is_valid(), "valid halvsies" );
1285 } else if( !reg3->is_valid() ) {
1286 assert( !reg4->is_valid(), "valid halvsies" );
1287 } else {
1288 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1289 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1290 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1291 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1292 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1293 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1294 }
1295 }
1296 }
1297 }
1298 #endif
1299
1300 // Visit each argument. Compute its outgoing register mask.
1301 // Return results now can have 2 bits returned.
1302 // Compute max over all outgoing arguments both per call-site
1303 // and over the entire method.
1304 for( i = 0; i < argcnt; i++ ) {
1305 // Address of incoming argument mask to fill in
1306 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1307 if( !parm_regs[i].first()->is_valid() &&
1308 !parm_regs[i].second()->is_valid() ) {
1309 continue; // Avoid Halves
1310 }
1311 // Grab first register, adjust stack slots and insert in mask.
1312 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1313 if (OptoReg::is_valid(reg1))
1314 rm->Insert( reg1 );
1315 // Grab second register (if any), adjust stack slots and insert in mask.
1316 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1317 if (OptoReg::is_valid(reg2))
1318 rm->Insert( reg2 );
1319 } // End of for all arguments
1320
1321 // Compute number of stack slots needed to restore stack in case of
1322 // Pascal-style argument popping.
1323 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1324 }
1325
1326 // Compute the max stack slot killed by any call. These will not be
1327 // available for debug info, and will be used to adjust FIRST_STACK_mask
1328 // after all call sites have been visited.
1329 if( _out_arg_limit < out_arg_limit_per_call)
1330 _out_arg_limit = out_arg_limit_per_call;
1331
1332 if (mcall) {
1333 // Kill the outgoing argument area, including any non-argument holes and
1334 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1335 // Since the max-per-method covers the max-per-call-site and debug info
1336 // is excluded on the max-per-method basis, debug info cannot land in
1337 // this killed area.
1338 uint r_cnt = mcall->tf()->range()->cnt();
1339 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1340 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1341 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1342 } else {
1343 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1344 proj->_rout.Insert(OptoReg::Name(i));
1345 }
1346 if (proj->_rout.is_NotEmpty()) {
1347 push_projection(proj);
1348 }
1349 }
1350 // Transfer the safepoint information from the call to the mcall
1351 // Move the JVMState list
1352 msfpt->set_jvms(sfpt->jvms());
1353 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1354 jvms->set_map(sfpt);
1355 }
1356
1357 // Debug inputs begin just after the last incoming parameter
1358 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1359 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1360
1361 // Move the OopMap
1362 msfpt->_oop_map = sfpt->_oop_map;
1363
1364 // Add additional edges.
1365 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1366 // For these calls we can not add MachConstantBase in expand(), as the
1367 // ins are not complete then.
1368 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1369 if (msfpt->jvms() &&
1370 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1371 // We added an edge before jvms, so we must adapt the position of the ins.
1372 msfpt->jvms()->adapt_position(+1);
1373 }
1374 }
1375
1376 // Registers killed by the call are set in the local scheduling pass
1377 // of Global Code Motion.
1378 return msfpt;
1379 }
1380
1381 //---------------------------match_tree----------------------------------------
1382 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1383 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1384 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1385 // a Load's result RegMask for memoization in idealreg2regmask[]
1386 MachNode *Matcher::match_tree( const Node *n ) {
1387 assert( n->Opcode() != Op_Phi, "cannot match" );
1388 assert( !n->is_block_start(), "cannot match" );
1389 // Set the mark for all locally allocated State objects.
1390 // When this call returns, the _states_arena arena will be reset
1391 // freeing all State objects.
1392 ResourceMark rm( &_states_arena );
1393
1394 LabelRootDepth = 0;
1395
1396 // StoreNodes require their Memory input to match any LoadNodes
1397 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1398 #ifdef ASSERT
1399 Node* save_mem_node = _mem_node;
1400 _mem_node = n->is_Store() ? (Node*)n : NULL;
1401 #endif
1402 // State object for root node of match tree
1403 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1404 State *s = new (&_states_arena) State;
1405 s->_kids[0] = NULL;
1406 s->_kids[1] = NULL;
1407 s->_leaf = (Node*)n;
1408 // Label the input tree, allocating labels from top-level arena
1409 Label_Root( n, s, n->in(0), mem );
1410 if (C->failing()) return NULL;
1411
1412 // The minimum cost match for the whole tree is found at the root State
1413 uint mincost = max_juint;
1414 uint cost = max_juint;
1415 uint i;
1416 for( i = 0; i < NUM_OPERANDS; i++ ) {
1417 if( s->valid(i) && // valid entry and
1418 s->_cost[i] < cost && // low cost and
1419 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1420 cost = s->_cost[mincost=i];
1421 }
1422 if (mincost == max_juint) {
1423 #ifndef PRODUCT
1424 tty->print("No matching rule for:");
1425 s->dump();
1426 #endif
1427 Matcher::soft_match_failure();
1428 return NULL;
1429 }
1430 // Reduce input tree based upon the state labels to machine Nodes
1431 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1432 #ifdef ASSERT
1433 _old2new_map.map(n->_idx, m);
1434 _new2old_map.map(m->_idx, (Node*)n);
1435 #endif
1436
1437 // Add any Matcher-ignored edges
1438 uint cnt = n->req();
1439 uint start = 1;
1440 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1441 if( n->is_AddP() ) {
1442 assert( mem == (Node*)1, "" );
1443 start = AddPNode::Base+1;
1444 }
1445 for( i = start; i < cnt; i++ ) {
1446 if( !n->match_edge(i) ) {
1447 if( i < m->req() )
1448 m->ins_req( i, n->in(i) );
1449 else
1450 m->add_req( n->in(i) );
1451 }
1452 }
1453
1454 debug_only( _mem_node = save_mem_node; )
1455 return m;
1456 }
1457
1458
1459 //------------------------------match_into_reg---------------------------------
1460 // Choose to either match this Node in a register or part of the current
1461 // match tree. Return true for requiring a register and false for matching
1462 // as part of the current match tree.
1463 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1464
1465 const Type *t = m->bottom_type();
1466
1467 if (t->singleton()) {
1468 // Never force constants into registers. Allow them to match as
1469 // constants or registers. Copies of the same value will share
1470 // the same register. See find_shared_node.
1471 return false;
1472 } else { // Not a constant
1473 // Stop recursion if they have different Controls.
1474 Node* m_control = m->in(0);
1475 // Control of load's memory can post-dominates load's control.
1476 // So use it since load can't float above its memory.
1477 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1478 if (control && m_control && control != m_control && control != mem_control) {
1479
1480 // Actually, we can live with the most conservative control we
1481 // find, if it post-dominates the others. This allows us to
1482 // pick up load/op/store trees where the load can float a little
1483 // above the store.
1484 Node *x = control;
1485 const uint max_scan = 6; // Arbitrary scan cutoff
1486 uint j;
1487 for (j=0; j<max_scan; j++) {
1488 if (x->is_Region()) // Bail out at merge points
1489 return true;
1490 x = x->in(0);
1491 if (x == m_control) // Does 'control' post-dominate
1492 break; // m->in(0)? If so, we can use it
1493 if (x == mem_control) // Does 'control' post-dominate
1494 break; // mem_control? If so, we can use it
1495 }
1496 if (j == max_scan) // No post-domination before scan end?
1497 return true; // Then break the match tree up
1498 }
1499 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1500 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1501 // These are commonly used in address expressions and can
1502 // efficiently fold into them on X64 in some cases.
1503 return false;
1504 }
1505 }
1506
1507 // Not forceable cloning. If shared, put it into a register.
1508 return shared;
1509 }
1510
1511
1512 //------------------------------Instruction Selection--------------------------
1513 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1514 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1515 // things the Matcher does not match (e.g., Memory), and things with different
1516 // Controls (hence forced into different blocks). We pass in the Control
1517 // selected for this entire State tree.
1518
1519 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1520 // Store and the Load must have identical Memories (as well as identical
1521 // pointers). Since the Matcher does not have anything for Memory (and
1522 // does not handle DAGs), I have to match the Memory input myself. If the
1523 // Tree root is a Store, I require all Loads to have the identical memory.
1524 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1525 // Since Label_Root is a recursive function, its possible that we might run
1526 // out of stack space. See bugs 6272980 & 6227033 for more info.
1527 LabelRootDepth++;
1528 if (LabelRootDepth > MaxLabelRootDepth) {
1529 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1530 return NULL;
1531 }
1532 uint care = 0; // Edges matcher cares about
1533 uint cnt = n->req();
1534 uint i = 0;
1535
1536 // Examine children for memory state
1537 // Can only subsume a child into your match-tree if that child's memory state
1538 // is not modified along the path to another input.
1539 // It is unsafe even if the other inputs are separate roots.
1540 Node *input_mem = NULL;
1541 for( i = 1; i < cnt; i++ ) {
1542 if( !n->match_edge(i) ) continue;
1543 Node *m = n->in(i); // Get ith input
1544 assert( m, "expect non-null children" );
1545 if( m->is_Load() ) {
1546 if( input_mem == NULL ) {
1547 input_mem = m->in(MemNode::Memory);
1548 } else if( input_mem != m->in(MemNode::Memory) ) {
1549 input_mem = NodeSentinel;
1550 }
1551 }
1552 }
1553
1554 for( i = 1; i < cnt; i++ ){// For my children
1555 if( !n->match_edge(i) ) continue;
1556 Node *m = n->in(i); // Get ith input
1557 // Allocate states out of a private arena
1558 State *s = new (&_states_arena) State;
1559 svec->_kids[care++] = s;
1560 assert( care <= 2, "binary only for now" );
1561
1562 // Recursively label the State tree.
1563 s->_kids[0] = NULL;
1564 s->_kids[1] = NULL;
1565 s->_leaf = m;
1566
1567 // Check for leaves of the State Tree; things that cannot be a part of
1568 // the current tree. If it finds any, that value is matched as a
1569 // register operand. If not, then the normal matching is used.
1570 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1571 //
1572 // Stop recursion if this is LoadNode and the root of this tree is a
1573 // StoreNode and the load & store have different memories.
1574 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1575 // Can NOT include the match of a subtree when its memory state
1576 // is used by any of the other subtrees
1577 (input_mem == NodeSentinel) ) {
1578 // Print when we exclude matching due to different memory states at input-loads
1579 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1580 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1581 tty->print_cr("invalid input_mem");
1582 }
1583 // Switch to a register-only opcode; this value must be in a register
1584 // and cannot be subsumed as part of a larger instruction.
1585 s->DFA( m->ideal_reg(), m );
1586
1587 } else {
1588 // If match tree has no control and we do, adopt it for entire tree
1589 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1590 control = m->in(0); // Pick up control
1591 // Else match as a normal part of the match tree.
1592 control = Label_Root(m,s,control,mem);
1593 if (C->failing()) return NULL;
1594 }
1595 }
1596
1597
1598 // Call DFA to match this node, and return
1599 svec->DFA( n->Opcode(), n );
1600
1601 #ifdef ASSERT
1602 uint x;
1603 for( x = 0; x < _LAST_MACH_OPER; x++ )
1604 if( svec->valid(x) )
1605 break;
1606
1607 if (x >= _LAST_MACH_OPER) {
1608 n->dump();
1609 svec->dump();
1610 assert( false, "bad AD file" );
1611 }
1612 #endif
1613 return control;
1614 }
1615
1616
1617 // Con nodes reduced using the same rule can share their MachNode
1618 // which reduces the number of copies of a constant in the final
1619 // program. The register allocator is free to split uses later to
1620 // split live ranges.
1621 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1622 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1623
1624 // See if this Con has already been reduced using this rule.
1625 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1626 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1627 if (last != NULL && rule == last->rule()) {
1628 // Don't expect control change for DecodeN
1629 if (leaf->is_DecodeNarrowPtr())
1630 return last;
1631 // Get the new space root.
1632 Node* xroot = new_node(C->root());
1633 if (xroot == NULL) {
1634 // This shouldn't happen give the order of matching.
1635 return NULL;
1636 }
1637
1638 // Shared constants need to have their control be root so they
1639 // can be scheduled properly.
1640 Node* control = last->in(0);
1641 if (control != xroot) {
1642 if (control == NULL || control == C->root()) {
1643 last->set_req(0, xroot);
1644 } else {
1645 assert(false, "unexpected control");
1646 return NULL;
1647 }
1648 }
1649 return last;
1650 }
1651 return NULL;
1652 }
1653
1654
1655 //------------------------------ReduceInst-------------------------------------
1656 // Reduce a State tree (with given Control) into a tree of MachNodes.
1657 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1658 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1659 // Each MachNode has a number of complicated MachOper operands; each
1660 // MachOper also covers a further tree of Ideal Nodes.
1661
1662 // The root of the Ideal match tree is always an instruction, so we enter
1663 // the recursion here. After building the MachNode, we need to recurse
1664 // the tree checking for these cases:
1665 // (1) Child is an instruction -
1666 // Build the instruction (recursively), add it as an edge.
1667 // Build a simple operand (register) to hold the result of the instruction.
1668 // (2) Child is an interior part of an instruction -
1669 // Skip over it (do nothing)
1670 // (3) Child is the start of a operand -
1671 // Build the operand, place it inside the instruction
1672 // Call ReduceOper.
1673 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1674 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1675
1676 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1677 if (shared_node != NULL) {
1678 return shared_node;
1679 }
1680
1681 // Build the object to represent this state & prepare for recursive calls
1682 MachNode *mach = s->MachNodeGenerator(rule);
1683 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1684 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1685 Node *leaf = s->_leaf;
1686 // Check for instruction or instruction chain rule
1687 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1688 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1689 "duplicating node that's already been matched");
1690 // Instruction
1691 mach->add_req( leaf->in(0) ); // Set initial control
1692 // Reduce interior of complex instruction
1693 ReduceInst_Interior( s, rule, mem, mach, 1 );
1694 } else {
1695 // Instruction chain rules are data-dependent on their inputs
1696 mach->add_req(0); // Set initial control to none
1697 ReduceInst_Chain_Rule( s, rule, mem, mach );
1698 }
1699
1700 // If a Memory was used, insert a Memory edge
1701 if( mem != (Node*)1 ) {
1702 mach->ins_req(MemNode::Memory,mem);
1703 #ifdef ASSERT
1704 // Verify adr type after matching memory operation
1705 const MachOper* oper = mach->memory_operand();
1706 if (oper != NULL && oper != (MachOper*)-1) {
1707 // It has a unique memory operand. Find corresponding ideal mem node.
1708 Node* m = NULL;
1709 if (leaf->is_Mem()) {
1710 m = leaf;
1711 } else {
1712 m = _mem_node;
1713 assert(m != NULL && m->is_Mem(), "expecting memory node");
1714 }
1715 const Type* mach_at = mach->adr_type();
1716 // DecodeN node consumed by an address may have different type
1717 // then its input. Don't compare types for such case.
1718 if (m->adr_type() != mach_at &&
1719 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1720 m->in(MemNode::Address)->is_AddP() &&
1721 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1722 m->in(MemNode::Address)->is_AddP() &&
1723 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1724 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1725 mach_at = m->adr_type();
1726 }
1727 if (m->adr_type() != mach_at) {
1728 m->dump();
1729 tty->print_cr("mach:");
1730 mach->dump(1);
1731 }
1732 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1733 }
1734 #endif
1735 }
1736
1737 // If the _leaf is an AddP, insert the base edge
1738 if (leaf->is_AddP()) {
1739 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1740 }
1741
1742 uint number_of_projections_prior = number_of_projections();
1743
1744 // Perform any 1-to-many expansions required
1745 MachNode *ex = mach->Expand(s, _projection_list, mem);
1746 if (ex != mach) {
1747 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1748 if( ex->in(1)->is_Con() )
1749 ex->in(1)->set_req(0, C->root());
1750 // Remove old node from the graph
1751 for( uint i=0; i<mach->req(); i++ ) {
1752 mach->set_req(i,NULL);
1753 }
1754 #ifdef ASSERT
1755 _new2old_map.map(ex->_idx, s->_leaf);
1756 #endif
1757 }
1758
1759 // PhaseChaitin::fixup_spills will sometimes generate spill code
1760 // via the matcher. By the time, nodes have been wired into the CFG,
1761 // and any further nodes generated by expand rules will be left hanging
1762 // in space, and will not get emitted as output code. Catch this.
1763 // Also, catch any new register allocation constraints ("projections")
1764 // generated belatedly during spill code generation.
1765 if (_allocation_started) {
1766 guarantee(ex == mach, "no expand rules during spill generation");
1767 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1768 }
1769
1770 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1771 // Record the con for sharing
1772 _shared_nodes.map(leaf->_idx, ex);
1773 }
1774
1775 return ex;
1776 }
1777
1778 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1779 for (uint i = n->req(); i < n->len(); i++) {
1780 if (n->in(i) != NULL) {
1781 mach->add_prec(n->in(i));
1782 }
1783 }
1784 }
1785
1786 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1787 // 'op' is what I am expecting to receive
1788 int op = _leftOp[rule];
1789 // Operand type to catch childs result
1790 // This is what my child will give me.
1791 int opnd_class_instance = s->_rule[op];
1792 // Choose between operand class or not.
1793 // This is what I will receive.
1794 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1795 // New rule for child. Chase operand classes to get the actual rule.
1796 int newrule = s->_rule[catch_op];
1797
1798 if( newrule < NUM_OPERANDS ) {
1799 // Chain from operand or operand class, may be output of shared node
1800 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1801 "Bad AD file: Instruction chain rule must chain from operand");
1802 // Insert operand into array of operands for this instruction
1803 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1804
1805 ReduceOper( s, newrule, mem, mach );
1806 } else {
1807 // Chain from the result of an instruction
1808 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1809 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1810 Node *mem1 = (Node*)1;
1811 debug_only(Node *save_mem_node = _mem_node;)
1812 mach->add_req( ReduceInst(s, newrule, mem1) );
1813 debug_only(_mem_node = save_mem_node;)
1814 }
1815 return;
1816 }
1817
1818
1819 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1820 handle_precedence_edges(s->_leaf, mach);
1821
1822 if( s->_leaf->is_Load() ) {
1823 Node *mem2 = s->_leaf->in(MemNode::Memory);
1824 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1825 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1826 mem = mem2;
1827 }
1828 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1829 if( mach->in(0) == NULL )
1830 mach->set_req(0, s->_leaf->in(0));
1831 }
1832
1833 // Now recursively walk the state tree & add operand list.
1834 for( uint i=0; i<2; i++ ) { // binary tree
1835 State *newstate = s->_kids[i];
1836 if( newstate == NULL ) break; // Might only have 1 child
1837 // 'op' is what I am expecting to receive
1838 int op;
1839 if( i == 0 ) {
1840 op = _leftOp[rule];
1841 } else {
1842 op = _rightOp[rule];
1843 }
1844 // Operand type to catch childs result
1845 // This is what my child will give me.
1846 int opnd_class_instance = newstate->_rule[op];
1847 // Choose between operand class or not.
1848 // This is what I will receive.
1849 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1850 // New rule for child. Chase operand classes to get the actual rule.
1851 int newrule = newstate->_rule[catch_op];
1852
1853 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1854 // Operand/operandClass
1855 // Insert operand into array of operands for this instruction
1856 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1857 ReduceOper( newstate, newrule, mem, mach );
1858
1859 } else { // Child is internal operand or new instruction
1860 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1861 // internal operand --> call ReduceInst_Interior
1862 // Interior of complex instruction. Do nothing but recurse.
1863 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1864 } else {
1865 // instruction --> call build operand( ) to catch result
1866 // --> ReduceInst( newrule )
1867 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1868 Node *mem1 = (Node*)1;
1869 debug_only(Node *save_mem_node = _mem_node;)
1870 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1871 debug_only(_mem_node = save_mem_node;)
1872 }
1873 }
1874 assert( mach->_opnds[num_opnds-1], "" );
1875 }
1876 return num_opnds;
1877 }
1878
1879 // This routine walks the interior of possible complex operands.
1880 // At each point we check our children in the match tree:
1881 // (1) No children -
1882 // We are a leaf; add _leaf field as an input to the MachNode
1883 // (2) Child is an internal operand -
1884 // Skip over it ( do nothing )
1885 // (3) Child is an instruction -
1886 // Call ReduceInst recursively and
1887 // and instruction as an input to the MachNode
1888 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1889 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1890 State *kid = s->_kids[0];
1891 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1892
1893 // Leaf? And not subsumed?
1894 if( kid == NULL && !_swallowed[rule] ) {
1895 mach->add_req( s->_leaf ); // Add leaf pointer
1896 return; // Bail out
1897 }
1898
1899 if( s->_leaf->is_Load() ) {
1900 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1901 mem = s->_leaf->in(MemNode::Memory);
1902 debug_only(_mem_node = s->_leaf;)
1903 }
1904
1905 handle_precedence_edges(s->_leaf, mach);
1906
1907 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1908 if( !mach->in(0) )
1909 mach->set_req(0,s->_leaf->in(0));
1910 else {
1911 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1912 }
1913 }
1914
1915 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1916 int newrule;
1917 if( i == 0)
1918 newrule = kid->_rule[_leftOp[rule]];
1919 else
1920 newrule = kid->_rule[_rightOp[rule]];
1921
1922 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1923 // Internal operand; recurse but do nothing else
1924 ReduceOper( kid, newrule, mem, mach );
1925
1926 } else { // Child is a new instruction
1927 // Reduce the instruction, and add a direct pointer from this
1928 // machine instruction to the newly reduced one.
1929 Node *mem1 = (Node*)1;
1930 debug_only(Node *save_mem_node = _mem_node;)
1931 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1932 debug_only(_mem_node = save_mem_node;)
1933 }
1934 }
1935 }
1936
1937
1938 // -------------------------------------------------------------------------
1939 // Java-Java calling convention
1940 // (what you use when Java calls Java)
1941
1942 //------------------------------find_receiver----------------------------------
1943 // For a given signature, return the OptoReg for parameter 0.
1944 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1945 VMRegPair regs;
1946 BasicType sig_bt = T_OBJECT;
1947 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1948 // Return argument 0 register. In the LP64 build pointers
1949 // take 2 registers, but the VM wants only the 'main' name.
1950 return OptoReg::as_OptoReg(regs.first());
1951 }
1952
1953 // This function identifies sub-graphs in which a 'load' node is
1954 // input to two different nodes, and such that it can be matched
1955 // with BMI instructions like blsi, blsr, etc.
1956 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1957 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1958 // refers to the same node.
1959 #ifdef X86
1960 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1961 // This is a temporary solution until we make DAGs expressible in ADL.
1962 template<typename ConType>
1963 class FusedPatternMatcher {
1964 Node* _op1_node;
1965 Node* _mop_node;
1966 int _con_op;
1967
1968 static int match_next(Node* n, int next_op, int next_op_idx) {
1969 if (n->in(1) == NULL || n->in(2) == NULL) {
1970 return -1;
1971 }
1972
1973 if (next_op_idx == -1) { // n is commutative, try rotations
1974 if (n->in(1)->Opcode() == next_op) {
1975 return 1;
1976 } else if (n->in(2)->Opcode() == next_op) {
1977 return 2;
1978 }
1979 } else {
1980 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1981 if (n->in(next_op_idx)->Opcode() == next_op) {
1982 return next_op_idx;
1983 }
1984 }
1985 return -1;
1986 }
1987 public:
1988 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1989 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1990
1991 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1992 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1993 typename ConType::NativeType con_value) {
1994 if (_op1_node->Opcode() != op1) {
1995 return false;
1996 }
1997 if (_mop_node->outcnt() > 2) {
1998 return false;
1999 }
2000 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
2001 if (op1_op2_idx == -1) {
2002 return false;
2003 }
2004 // Memory operation must be the other edge
2005 int op1_mop_idx = (op1_op2_idx & 1) + 1;
2006
2007 // Check that the mop node is really what we want
2008 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2009 Node *op2_node = _op1_node->in(op1_op2_idx);
2010 if (op2_node->outcnt() > 1) {
2011 return false;
2012 }
2013 assert(op2_node->Opcode() == op2, "Should be");
2014 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2015 if (op2_con_idx == -1) {
2016 return false;
2017 }
2018 // Memory operation must be the other edge
2019 int op2_mop_idx = (op2_con_idx & 1) + 1;
2020 // Check that the memory operation is the same node
2021 if (op2_node->in(op2_mop_idx) == _mop_node) {
2022 // Now check the constant
2023 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2024 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2025 return true;
2026 }
2027 }
2028 }
2029 return false;
2030 }
2031 };
2032
2033
2034 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2035 if (n != NULL && m != NULL) {
2036 if (m->Opcode() == Op_LoadI) {
2037 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2038 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2039 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2040 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2041 } else if (m->Opcode() == Op_LoadL) {
2042 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2043 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2044 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2045 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2046 }
2047 }
2048 return false;
2049 }
2050 #endif // X86
2051
2052 // A method-klass-holder may be passed in the inline_cache_reg
2053 // and then expanded into the inline_cache_reg and a method_oop register
2054 // defined in ad_<arch>.cpp
2055
2056 // Check for shift by small constant as well
2057 static bool clone_shift(Node* shift, Matcher* matcher, MStack& mstack, VectorSet& address_visited) {
2058 if (shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2059 shift->in(2)->get_int() <= 3 &&
2060 // Are there other uses besides address expressions?
2061 !matcher->is_visited(shift)) {
2062 address_visited.set(shift->_idx); // Flag as address_visited
2063 mstack.push(shift->in(2), Visit);
2064 Node *conv = shift->in(1);
2065 #ifdef _LP64
2066 // Allow Matcher to match the rule which bypass
2067 // ConvI2L operation for an array index on LP64
2068 // if the index value is positive.
2069 if (conv->Opcode() == Op_ConvI2L &&
2070 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2071 // Are there other uses besides address expressions?
2072 !matcher->is_visited(conv)) {
2073 address_visited.set(conv->_idx); // Flag as address_visited
2074 mstack.push(conv->in(1), Pre_Visit);
2075 } else
2076 #endif
2077 mstack.push(conv, Pre_Visit);
2078 return true;
2079 }
2080 return false;
2081 }
2082
2083
2084 //------------------------------find_shared------------------------------------
2085 // Set bits if Node is shared or otherwise a root
2086 void Matcher::find_shared( Node *n ) {
2087 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2088 MStack mstack(C->live_nodes() * 2);
2089 // Mark nodes as address_visited if they are inputs to an address expression
2090 VectorSet address_visited(Thread::current()->resource_area());
2091 mstack.push(n, Visit); // Don't need to pre-visit root node
2092 while (mstack.is_nonempty()) {
2093 n = mstack.node(); // Leave node on stack
2094 Node_State nstate = mstack.state();
2095 uint nop = n->Opcode();
2096 if (nstate == Pre_Visit) {
2097 if (address_visited.test(n->_idx)) { // Visited in address already?
2098 // Flag as visited and shared now.
2099 set_visited(n);
2100 }
2101 if (is_visited(n)) { // Visited already?
2102 // Node is shared and has no reason to clone. Flag it as shared.
2103 // This causes it to match into a register for the sharing.
2104 set_shared(n); // Flag as shared and
2105 mstack.pop(); // remove node from stack
2106 continue;
2107 }
2108 nstate = Visit; // Not already visited; so visit now
2109 }
2110 if (nstate == Visit) {
2111 mstack.set_state(Post_Visit);
2112 set_visited(n); // Flag as visited now
2113 bool mem_op = false;
2114
2115 switch( nop ) { // Handle some opcodes special
2116 case Op_Phi: // Treat Phis as shared roots
2117 case Op_Parm:
2118 case Op_Proj: // All handled specially during matching
2119 case Op_SafePointScalarObject:
2120 set_shared(n);
2121 set_dontcare(n);
2122 break;
2123 case Op_If:
2124 case Op_CountedLoopEnd:
2125 mstack.set_state(Alt_Post_Visit); // Alternative way
2126 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2127 // with matching cmp/branch in 1 instruction. The Matcher needs the
2128 // Bool and CmpX side-by-side, because it can only get at constants
2129 // that are at the leaves of Match trees, and the Bool's condition acts
2130 // as a constant here.
2131 mstack.push(n->in(1), Visit); // Clone the Bool
2132 mstack.push(n->in(0), Pre_Visit); // Visit control input
2133 continue; // while (mstack.is_nonempty())
2134 case Op_ConvI2D: // These forms efficiently match with a prior
2135 case Op_ConvI2F: // Load but not a following Store
2136 if( n->in(1)->is_Load() && // Prior load
2137 n->outcnt() == 1 && // Not already shared
2138 n->unique_out()->is_Store() ) // Following store
2139 set_shared(n); // Force it to be a root
2140 break;
2141 case Op_ReverseBytesI:
2142 case Op_ReverseBytesL:
2143 if( n->in(1)->is_Load() && // Prior load
2144 n->outcnt() == 1 ) // Not already shared
2145 set_shared(n); // Force it to be a root
2146 break;
2147 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2148 case Op_IfFalse:
2149 case Op_IfTrue:
2150 case Op_MachProj:
2151 case Op_MergeMem:
2152 case Op_Catch:
2153 case Op_CatchProj:
2154 case Op_CProj:
2155 case Op_JumpProj:
2156 case Op_JProj:
2157 case Op_NeverBranch:
2158 set_dontcare(n);
2159 break;
2160 case Op_Jump:
2161 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2162 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2163 continue; // while (mstack.is_nonempty())
2164 case Op_StrComp:
2165 case Op_StrEquals:
2166 case Op_StrIndexOf:
2167 case Op_StrIndexOfChar:
2168 case Op_AryEq:
2169 case Op_HasNegatives:
2170 case Op_StrInflatedCopy:
2171 case Op_StrCompressedCopy:
2172 case Op_EncodeISOArray:
2173 set_shared(n); // Force result into register (it will be anyways)
2174 break;
2175 case Op_ConP: { // Convert pointers above the centerline to NUL
2176 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2177 const TypePtr* tp = tn->type()->is_ptr();
2178 if (tp->_ptr == TypePtr::AnyNull) {
2179 tn->set_type(TypePtr::NULL_PTR);
2180 }
2181 break;
2182 }
2183 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2184 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2185 const TypePtr* tp = tn->type()->make_ptr();
2186 if (tp && tp->_ptr == TypePtr::AnyNull) {
2187 tn->set_type(TypeNarrowOop::NULL_PTR);
2188 }
2189 break;
2190 }
2191 case Op_Binary: // These are introduced in the Post_Visit state.
2192 ShouldNotReachHere();
2193 break;
2194 case Op_ClearArray:
2195 case Op_SafePoint:
2196 mem_op = true;
2197 break;
2198 default:
2199 if( n->is_Store() ) {
2200 // Do match stores, despite no ideal reg
2201 mem_op = true;
2202 break;
2203 }
2204 if( n->is_Mem() ) { // Loads and LoadStores
2205 mem_op = true;
2206 // Loads must be root of match tree due to prior load conflict
2207 if( C->subsume_loads() == false )
2208 set_shared(n);
2209 }
2210 // Fall into default case
2211 if( !n->ideal_reg() )
2212 set_dontcare(n); // Unmatchable Nodes
2213 } // end_switch
2214
2215 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2216 Node *m = n->in(i); // Get ith input
2217 if (m == NULL) continue; // Ignore NULLs
2218 uint mop = m->Opcode();
2219
2220 // Must clone all producers of flags, or we will not match correctly.
2221 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2222 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2223 // are also there, so we may match a float-branch to int-flags and
2224 // expect the allocator to haul the flags from the int-side to the
2225 // fp-side. No can do.
2226 if( _must_clone[mop] ) {
2227 mstack.push(m, Visit);
2228 continue; // for(int i = ...)
2229 }
2230
2231 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2232 // Bases used in addresses must be shared but since
2233 // they are shared through a DecodeN they may appear
2234 // to have a single use so force sharing here.
2235 set_shared(m->in(AddPNode::Base)->in(1));
2236 }
2237
2238 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2239 #ifdef X86
2240 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2241 mstack.push(m, Visit);
2242 continue;
2243 }
2244 #endif
2245
2246 // Clone addressing expressions as they are "free" in memory access instructions
2247 if (mem_op && i == MemNode::Address && mop == Op_AddP &&
2248 // When there are other uses besides address expressions
2249 // put it on stack and mark as shared.
2250 !is_visited(m)) {
2251 // Some inputs for address expression are not put on stack
2252 // to avoid marking them as shared and forcing them into register
2253 // if they are used only in address expressions.
2254 // But they should be marked as shared if there are other uses
2255 // besides address expressions.
2256
2257 Node *off = m->in(AddPNode::Offset);
2258 if (off->is_Con()) {
2259 address_visited.test_set(m->_idx); // Flag as address_visited
2260 Node *adr = m->in(AddPNode::Address);
2261
2262 // Intel, ARM and friends can handle 2 adds in addressing mode
2263 if( clone_shift_expressions && adr->is_AddP() &&
2264 // AtomicAdd is not an addressing expression.
2265 // Cheap to find it by looking for screwy base.
2266 !adr->in(AddPNode::Base)->is_top() &&
2267 // Are there other uses besides address expressions?
2268 !is_visited(adr) ) {
2269 address_visited.set(adr->_idx); // Flag as address_visited
2270 Node *shift = adr->in(AddPNode::Offset);
2271 if (!clone_shift(shift, this, mstack, address_visited)) {
2272 mstack.push(shift, Pre_Visit);
2273 }
2274 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2275 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2276 } else { // Sparc, Alpha, PPC and friends
2277 mstack.push(adr, Pre_Visit);
2278 }
2279
2280 // Clone X+offset as it also folds into most addressing expressions
2281 mstack.push(off, Visit);
2282 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2283 continue; // for(int i = ...)
2284 } else if (clone_shift_expressions &&
2285 clone_shift(off, this, mstack, address_visited)) {
2286 address_visited.test_set(m->_idx); // Flag as address_visited
2287 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2288 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2289 continue;
2290 } // if( off->is_Con() )
2291 } // if( mem_op &&
2292 mstack.push(m, Pre_Visit);
2293 } // for(int i = ...)
2294 }
2295 else if (nstate == Alt_Post_Visit) {
2296 mstack.pop(); // Remove node from stack
2297 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2298 // shared and all users of the Bool need to move the Cmp in parallel.
2299 // This leaves both the Bool and the If pointing at the Cmp. To
2300 // prevent the Matcher from trying to Match the Cmp along both paths
2301 // BoolNode::match_edge always returns a zero.
2302
2303 // We reorder the Op_If in a pre-order manner, so we can visit without
2304 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2305 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2306 }
2307 else if (nstate == Post_Visit) {
2308 mstack.pop(); // Remove node from stack
2309
2310 // Now hack a few special opcodes
2311 switch( n->Opcode() ) { // Handle some opcodes special
2312 case Op_StorePConditional:
2313 case Op_StoreIConditional:
2314 case Op_StoreLConditional:
2315 case Op_CompareAndExchangeI:
2316 case Op_CompareAndExchangeL:
2317 case Op_CompareAndExchangeP:
2318 case Op_CompareAndExchangeN:
2319 case Op_WeakCompareAndSwapI:
2320 case Op_WeakCompareAndSwapL:
2321 case Op_WeakCompareAndSwapP:
2322 case Op_WeakCompareAndSwapN:
2323 case Op_CompareAndSwapI:
2324 case Op_CompareAndSwapL:
2325 case Op_CompareAndSwapP:
2326 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2327 Node *newval = n->in(MemNode::ValueIn );
2328 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2329 Node *pair = new BinaryNode( oldval, newval );
2330 n->set_req(MemNode::ValueIn,pair);
2331 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2332 break;
2333 }
2334 case Op_CMoveD: // Convert trinary to binary-tree
2335 case Op_CMoveF:
2336 case Op_CMoveI:
2337 case Op_CMoveL:
2338 case Op_CMoveN:
2339 case Op_CMoveP:
2340 case Op_CMoveVD: {
2341 // Restructure into a binary tree for Matching. It's possible that
2342 // we could move this code up next to the graph reshaping for IfNodes
2343 // or vice-versa, but I do not want to debug this for Ladybird.
2344 // 10/2/2000 CNC.
2345 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2346 n->set_req(1,pair1);
2347 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2348 n->set_req(2,pair2);
2349 n->del_req(3);
2350 break;
2351 }
2352 case Op_LoopLimit: {
2353 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2354 n->set_req(1,pair1);
2355 n->set_req(2,n->in(3));
2356 n->del_req(3);
2357 break;
2358 }
2359 case Op_StrEquals:
2360 case Op_StrIndexOfChar: {
2361 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2362 n->set_req(2,pair1);
2363 n->set_req(3,n->in(4));
2364 n->del_req(4);
2365 break;
2366 }
2367 case Op_StrComp:
2368 case Op_StrIndexOf: {
2369 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2370 n->set_req(2,pair1);
2371 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2372 n->set_req(3,pair2);
2373 n->del_req(5);
2374 n->del_req(4);
2375 break;
2376 }
2377 case Op_StrCompressedCopy:
2378 case Op_StrInflatedCopy:
2379 case Op_EncodeISOArray: {
2380 // Restructure into a binary tree for Matching.
2381 Node* pair = new BinaryNode(n->in(3), n->in(4));
2382 n->set_req(3, pair);
2383 n->del_req(4);
2384 break;
2385 }
2386 default:
2387 break;
2388 }
2389 }
2390 else {
2391 ShouldNotReachHere();
2392 }
2393 } // end of while (mstack.is_nonempty())
2394 }
2395
2396 #ifdef ASSERT
2397 // machine-independent root to machine-dependent root
2398 void Matcher::dump_old2new_map() {
2399 _old2new_map.dump();
2400 }
2401 #endif
2402
2403 //---------------------------collect_null_checks-------------------------------
2404 // Find null checks in the ideal graph; write a machine-specific node for
2405 // it. Used by later implicit-null-check handling. Actually collects
2406 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2407 // value being tested.
2408 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2409 Node *iff = proj->in(0);
2410 if( iff->Opcode() == Op_If ) {
2411 // During matching If's have Bool & Cmp side-by-side
2412 BoolNode *b = iff->in(1)->as_Bool();
2413 Node *cmp = iff->in(2);
2414 int opc = cmp->Opcode();
2415 if (opc != Op_CmpP && opc != Op_CmpN) return;
2416
2417 const Type* ct = cmp->in(2)->bottom_type();
2418 if (ct == TypePtr::NULL_PTR ||
2419 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2420
2421 bool push_it = false;
2422 if( proj->Opcode() == Op_IfTrue ) {
2423 #ifndef PRODUCT
2424 extern int all_null_checks_found;
2425 all_null_checks_found++;
2426 #endif
2427 if( b->_test._test == BoolTest::ne ) {
2428 push_it = true;
2429 }
2430 } else {
2431 assert( proj->Opcode() == Op_IfFalse, "" );
2432 if( b->_test._test == BoolTest::eq ) {
2433 push_it = true;
2434 }
2435 }
2436 if( push_it ) {
2437 _null_check_tests.push(proj);
2438 Node* val = cmp->in(1);
2439 #ifdef _LP64
2440 if (val->bottom_type()->isa_narrowoop() &&
2441 !Matcher::narrow_oop_use_complex_address()) {
2442 //
2443 // Look for DecodeN node which should be pinned to orig_proj.
2444 // On platforms (Sparc) which can not handle 2 adds
2445 // in addressing mode we have to keep a DecodeN node and
2446 // use it to do implicit NULL check in address.
2447 //
2448 // DecodeN node was pinned to non-null path (orig_proj) during
2449 // CastPP transformation in final_graph_reshaping_impl().
2450 //
2451 uint cnt = orig_proj->outcnt();
2452 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2453 Node* d = orig_proj->raw_out(i);
2454 if (d->is_DecodeN() && d->in(1) == val) {
2455 val = d;
2456 val->set_req(0, NULL); // Unpin now.
2457 // Mark this as special case to distinguish from
2458 // a regular case: CmpP(DecodeN, NULL).
2459 val = (Node*)(((intptr_t)val) | 1);
2460 break;
2461 }
2462 }
2463 }
2464 #endif
2465 _null_check_tests.push(val);
2466 }
2467 }
2468 }
2469 }
2470
2471 //---------------------------validate_null_checks------------------------------
2472 // Its possible that the value being NULL checked is not the root of a match
2473 // tree. If so, I cannot use the value in an implicit null check.
2474 void Matcher::validate_null_checks( ) {
2475 uint cnt = _null_check_tests.size();
2476 for( uint i=0; i < cnt; i+=2 ) {
2477 Node *test = _null_check_tests[i];
2478 Node *val = _null_check_tests[i+1];
2479 bool is_decoden = ((intptr_t)val) & 1;
2480 val = (Node*)(((intptr_t)val) & ~1);
2481 if (has_new_node(val)) {
2482 Node* new_val = new_node(val);
2483 if (is_decoden) {
2484 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2485 // Note: new_val may have a control edge if
2486 // the original ideal node DecodeN was matched before
2487 // it was unpinned in Matcher::collect_null_checks().
2488 // Unpin the mach node and mark it.
2489 new_val->set_req(0, NULL);
2490 new_val = (Node*)(((intptr_t)new_val) | 1);
2491 }
2492 // Is a match-tree root, so replace with the matched value
2493 _null_check_tests.map(i+1, new_val);
2494 } else {
2495 // Yank from candidate list
2496 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2497 _null_check_tests.map(i,_null_check_tests[--cnt]);
2498 _null_check_tests.pop();
2499 _null_check_tests.pop();
2500 i-=2;
2501 }
2502 }
2503 }
2504
2505 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2506 // atomic instruction acting as a store_load barrier without any
2507 // intervening volatile load, and thus we don't need a barrier here.
2508 // We retain the Node to act as a compiler ordering barrier.
2509 bool Matcher::post_store_load_barrier(const Node* vmb) {
2510 Compile* C = Compile::current();
2511 assert(vmb->is_MemBar(), "");
2512 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2513 const MemBarNode* membar = vmb->as_MemBar();
2514
2515 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2516 Node* ctrl = NULL;
2517 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2518 Node* p = membar->fast_out(i);
2519 assert(p->is_Proj(), "only projections here");
2520 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2521 !C->node_arena()->contains(p)) { // Unmatched old-space only
2522 ctrl = p;
2523 break;
2524 }
2525 }
2526 assert((ctrl != NULL), "missing control projection");
2527
2528 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2529 Node *x = ctrl->fast_out(j);
2530 int xop = x->Opcode();
2531
2532 // We don't need current barrier if we see another or a lock
2533 // before seeing volatile load.
2534 //
2535 // Op_Fastunlock previously appeared in the Op_* list below.
2536 // With the advent of 1-0 lock operations we're no longer guaranteed
2537 // that a monitor exit operation contains a serializing instruction.
2538
2539 if (xop == Op_MemBarVolatile ||
2540 xop == Op_CompareAndExchangeI ||
2541 xop == Op_CompareAndExchangeL ||
2542 xop == Op_CompareAndExchangeP ||
2543 xop == Op_CompareAndExchangeN ||
2544 xop == Op_WeakCompareAndSwapL ||
2545 xop == Op_WeakCompareAndSwapP ||
2546 xop == Op_WeakCompareAndSwapN ||
2547 xop == Op_WeakCompareAndSwapI ||
2548 xop == Op_CompareAndSwapL ||
2549 xop == Op_CompareAndSwapP ||
2550 xop == Op_CompareAndSwapN ||
2551 xop == Op_CompareAndSwapI) {
2552 return true;
2553 }
2554
2555 // Op_FastLock previously appeared in the Op_* list above.
2556 // With biased locking we're no longer guaranteed that a monitor
2557 // enter operation contains a serializing instruction.
2558 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2559 return true;
2560 }
2561
2562 if (x->is_MemBar()) {
2563 // We must retain this membar if there is an upcoming volatile
2564 // load, which will be followed by acquire membar.
2565 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2566 return false;
2567 } else {
2568 // For other kinds of barriers, check by pretending we
2569 // are them, and seeing if we can be removed.
2570 return post_store_load_barrier(x->as_MemBar());
2571 }
2572 }
2573
2574 // probably not necessary to check for these
2575 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2576 return false;
2577 }
2578 }
2579 return false;
2580 }
2581
2582 // Check whether node n is a branch to an uncommon trap that we could
2583 // optimize as test with very high branch costs in case of going to
2584 // the uncommon trap. The code must be able to be recompiled to use
2585 // a cheaper test.
2586 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2587 // Don't do it for natives, adapters, or runtime stubs
2588 Compile *C = Compile::current();
2589 if (!C->is_method_compilation()) return false;
2590
2591 assert(n->is_If(), "You should only call this on if nodes.");
2592 IfNode *ifn = n->as_If();
2593
2594 Node *ifFalse = NULL;
2595 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2596 if (ifn->fast_out(i)->is_IfFalse()) {
2597 ifFalse = ifn->fast_out(i);
2598 break;
2599 }
2600 }
2601 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2602
2603 Node *reg = ifFalse;
2604 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2605 // Alternatively use visited set? Seems too expensive.
2606 while (reg != NULL && cnt > 0) {
2607 CallNode *call = NULL;
2608 RegionNode *nxt_reg = NULL;
2609 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2610 Node *o = reg->fast_out(i);
2611 if (o->is_Call()) {
2612 call = o->as_Call();
2613 }
2614 if (o->is_Region()) {
2615 nxt_reg = o->as_Region();
2616 }
2617 }
2618
2619 if (call &&
2620 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2621 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2622 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2623 jint tr_con = trtype->is_int()->get_con();
2624 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2625 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2626 assert((int)reason < (int)BitsPerInt, "recode bit map");
2627
2628 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2629 && action != Deoptimization::Action_none) {
2630 // This uncommon trap is sure to recompile, eventually.
2631 // When that happens, C->too_many_traps will prevent
2632 // this transformation from happening again.
2633 return true;
2634 }
2635 }
2636 }
2637
2638 reg = nxt_reg;
2639 cnt--;
2640 }
2641
2642 return false;
2643 }
2644
2645 //=============================================================================
2646 //---------------------------State---------------------------------------------
2647 State::State(void) {
2648 #ifdef ASSERT
2649 _id = 0;
2650 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2651 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2652 //memset(_cost, -1, sizeof(_cost));
2653 //memset(_rule, -1, sizeof(_rule));
2654 #endif
2655 memset(_valid, 0, sizeof(_valid));
2656 }
2657
2658 #ifdef ASSERT
2659 State::~State() {
2660 _id = 99;
2661 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2662 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2663 memset(_cost, -3, sizeof(_cost));
2664 memset(_rule, -3, sizeof(_rule));
2665 }
2666 #endif
2667
2668 #ifndef PRODUCT
2669 //---------------------------dump----------------------------------------------
2670 void State::dump() {
2671 tty->print("\n");
2672 dump(0);
2673 }
2674
2675 void State::dump(int depth) {
2676 for( int j = 0; j < depth; j++ )
2677 tty->print(" ");
2678 tty->print("--N: ");
2679 _leaf->dump();
2680 uint i;
2681 for( i = 0; i < _LAST_MACH_OPER; i++ )
2682 // Check for valid entry
2683 if( valid(i) ) {
2684 for( int j = 0; j < depth; j++ )
2685 tty->print(" ");
2686 assert(_cost[i] != max_juint, "cost must be a valid value");
2687 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2688 tty->print_cr("%s %d %s",
2689 ruleName[i], _cost[i], ruleName[_rule[i]] );
2690 }
2691 tty->cr();
2692
2693 for( i=0; i<2; i++ )
2694 if( _kids[i] )
2695 _kids[i]->dump(depth+1);
2696 }
2697 #endif