1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2015 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 bool VM_Version::_is_determine_features_test_running = false;
41
42
43 #define MSG(flag) \
44 if (flag && !FLAG_IS_DEFAULT(flag)) \
45 jio_fprintf(defaultStream::error_stream(), \
46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
47 " -XX:+" #flag " will be disabled!\n");
48
49 void VM_Version::initialize() {
50
51 // Test which instructions are supported and measure cache line size.
52 determine_features();
53
54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
56 if (VM_Version::has_tcheck() && VM_Version::has_lqarx()) {
57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
58 } else if (VM_Version::has_popcntw()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
60 } else if (VM_Version::has_cmpb()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
62 } else if (VM_Version::has_popcntb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
64 } else {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
66 }
67 }
68
69 bool PowerArchitecturePPC64_ok = false;
70 switch (PowerArchitecturePPC64) {
71 case 8: if (!VM_Version::has_tcheck() ) break;
72 if (!VM_Version::has_lqarx() ) break;
73 case 7: if (!VM_Version::has_popcntw()) break;
74 case 6: if (!VM_Version::has_cmpb() ) break;
75 case 5: if (!VM_Version::has_popcntb()) break;
76 case 0: PowerArchitecturePPC64_ok = true; break;
77 default: break;
78 }
79 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
80 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
81
82 // Power 8: Configure Data Stream Control Register.
83 if (PowerArchitecturePPC64 >= 8) {
84 config_dscr();
85 }
86
87 if (!UseSIGTRAP) {
88 MSG(TrapBasedICMissChecks);
89 MSG(TrapBasedNotEntrantChecks);
90 MSG(TrapBasedNullChecks);
91 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
92 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
93 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
94 }
95
96 #ifdef COMPILER2
97 if (!UseSIGTRAP) {
98 MSG(TrapBasedRangeChecks);
99 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
100 }
101
102 // On Power6 test for section size.
103 if (PowerArchitecturePPC64 == 6) {
104 determine_section_size();
105 // TODO: PPC port } else {
106 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
107 }
108
109 MaxVectorSize = 8;
110 #endif
111
112 // Create and print feature-string.
113 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
114 jio_snprintf(buf, sizeof(buf),
115 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s",
116 (has_fsqrt() ? " fsqrt" : ""),
117 (has_isel() ? " isel" : ""),
118 (has_lxarxeh() ? " lxarxeh" : ""),
119 (has_cmpb() ? " cmpb" : ""),
120 //(has_mftgpr()? " mftgpr" : ""),
121 (has_popcntb() ? " popcntb" : ""),
122 (has_popcntw() ? " popcntw" : ""),
123 (has_fcfids() ? " fcfids" : ""),
124 (has_vand() ? " vand" : ""),
125 (has_lqarx() ? " lqarx" : ""),
126 (has_vcipher() ? " vcipher" : ""),
127 (has_vpmsumb() ? " vpmsumb" : ""),
128 (has_tcheck() ? " tcheck" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_string = os::strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
135
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
140
141 // Used by C1.
142 _supports_atomic_getset4 = true;
143 _supports_atomic_getadd4 = true;
144 _supports_atomic_getset8 = true;
145 _supports_atomic_getadd8 = true;
146
147 UseSSE = 0; // Only on x86 and x64
148
149 intx cache_line_size = L1_data_cache_line_size();
150
151 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
152
153 if (AllocatePrefetchStyle == 4) {
154 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
155 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
156 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
157 } else {
158 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
159 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
160 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
161 }
162
163 assert(AllocatePrefetchLines > 0, "invalid value");
164 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
165 AllocatePrefetchLines = 1; // Conservative value.
166 }
167
168 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
169 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
170 }
171
172 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
173
174 // Implementation does not use any of the vector instructions
175 // available with Power8. Their exploitation is still pending.
176 if (!UseCRC32Intrinsics) {
177 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
178 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
179 }
180 }
181
182 if (UseCRC32CIntrinsics) {
183 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
184 warning("CRC32C intrinsics are not available on this CPU");
185 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
186 }
187
188 // The AES intrinsic stubs require AES instruction support.
189 if (UseAES) {
190 warning("AES instructions are not available on this CPU");
191 FLAG_SET_DEFAULT(UseAES, false);
192 }
193 if (UseAESIntrinsics) {
194 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
195 warning("AES intrinsics are not available on this CPU");
196 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
197 }
198
199 if (UseAESCTRIntrinsics) {
200 warning("AES/CTR intrinsics are not available on this CPU");
201 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
202 }
203
204 if (UseGHASHIntrinsics) {
205 warning("GHASH intrinsics are not available on this CPU");
206 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
207 }
208
209 if (UseSHA) {
210 warning("SHA instructions are not available on this CPU");
211 FLAG_SET_DEFAULT(UseSHA, false);
212 }
213 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
214 warning("SHA intrinsics are not available on this CPU");
215 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
216 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
217 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
218 }
219
220 if (UseAdler32Intrinsics) {
221 warning("Adler32Intrinsics not available on this CPU.");
222 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
223 }
224
225 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
226 UseMultiplyToLenIntrinsic = true;
227 }
228 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
229 UseMontgomeryMultiplyIntrinsic = true;
230 }
231 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
232 UseMontgomerySquareIntrinsic = true;
233 }
234
235 if (UseVectorizedMismatchIntrinsic) {
236 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
237 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
238 }
239
240
241 // Adjust RTM (Restricted Transactional Memory) flags.
242 if (UseRTMLocking) {
243 // If CPU or OS are too old:
244 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
245 // setting during arguments processing. See use_biased_locking().
246 // VM_Version_init() is executed after UseBiasedLocking is used
247 // in Thread::allocate().
248 if (!has_tcheck()) {
249 vm_exit_during_initialization("RTM instructions are not available on this CPU");
250 }
251 bool os_too_old = true;
252 #ifdef AIX
253 if (os::Aix::os_version() >= 0x0701031e) { // at least AIX 7.1.3.30
254 os_too_old = false;
255 }
256 #endif
257 #ifdef linux
258 // TODO: check kernel version (we currently have too old versions only)
259 #endif
260 if (os_too_old) {
261 vm_exit_during_initialization("RTM is not supported on this OS version.");
262 }
263 }
264
265 if (UseRTMLocking) {
266 #if INCLUDE_RTM_OPT
267 if (!UnlockExperimentalVMOptions) {
268 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
269 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
270 } else {
271 warning("UseRTMLocking is only available as experimental option on this platform.");
272 }
273 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
274 // RTM locking should be used only for applications with
275 // high lock contention. For now we do not use it by default.
276 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
277 }
278 if (!is_power_of_2(RTMTotalCountIncrRate)) {
279 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
280 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
281 }
282 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
283 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
284 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
285 }
286 guarantee(RTMSpinLoopCount > 0, "unsupported");
287 #else
288 // Only C2 does RTM locking optimization.
289 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
290 // setting during arguments processing. See use_biased_locking().
291 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
292 #endif
293 } else { // !UseRTMLocking
294 if (UseRTMForStackLocks) {
295 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
296 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
297 }
298 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
299 }
300 if (UseRTMDeopt) {
301 FLAG_SET_DEFAULT(UseRTMDeopt, false);
302 }
303 if (PrintPreciseRTMLockingStatistics) {
304 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
305 }
306 }
307
308 // This machine allows unaligned memory accesses
309 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
310 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
311 }
312 }
313
314 bool VM_Version::use_biased_locking() {
315 #if INCLUDE_RTM_OPT
316 // RTM locking is most useful when there is high lock contention and
317 // low data contention. With high lock contention the lock is usually
318 // inflated and biased locking is not suitable for that case.
319 // RTM locking code requires that biased locking is off.
320 // Note: we can't switch off UseBiasedLocking in get_processor_features()
321 // because it is used by Thread::allocate() which is called before
322 // VM_Version::initialize().
323 if (UseRTMLocking && UseBiasedLocking) {
324 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
325 FLAG_SET_DEFAULT(UseBiasedLocking, false);
326 } else {
327 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
328 UseBiasedLocking = false;
329 }
330 }
331 #endif
332 return UseBiasedLocking;
333 }
334
335 void VM_Version::print_features() {
336 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
337 }
338
339 #ifdef COMPILER2
340 // Determine section size on power6: If section size is 8 instructions,
341 // there should be a difference between the two testloops of ~15 %. If
342 // no difference is detected the section is assumed to be 32 instructions.
343 void VM_Version::determine_section_size() {
344
345 int unroll = 80;
346
347 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
348
349 // Allocate space for the code.
350 ResourceMark rm;
351 CodeBuffer cb("detect_section_size", code_size, 0);
352 MacroAssembler* a = new MacroAssembler(&cb);
353
354 uint32_t *code = (uint32_t *)a->pc();
355 // Emit code.
356 void (*test1)() = (void(*)())(void *)a->function_entry();
357
358 Label l1;
359
360 a->li(R4, 1);
361 a->sldi(R4, R4, 28);
362 a->b(l1);
363 a->align(CodeEntryAlignment);
364
365 a->bind(l1);
366
367 for (int i = 0; i < unroll; i++) {
368 // Schleife 1
369 // ------- sector 0 ------------
370 // ;; 0
371 a->nop(); // 1
372 a->fpnop0(); // 2
373 a->fpnop1(); // 3
374 a->addi(R4,R4, -1); // 4
375
376 // ;; 1
377 a->nop(); // 5
378 a->fmr(F6, F6); // 6
379 a->fmr(F7, F7); // 7
380 a->endgroup(); // 8
381 // ------- sector 8 ------------
382
383 // ;; 2
384 a->nop(); // 9
385 a->nop(); // 10
386 a->fmr(F8, F8); // 11
387 a->fmr(F9, F9); // 12
388
389 // ;; 3
390 a->nop(); // 13
391 a->fmr(F10, F10); // 14
392 a->fmr(F11, F11); // 15
393 a->endgroup(); // 16
394 // -------- sector 16 -------------
395
396 // ;; 4
397 a->nop(); // 17
398 a->nop(); // 18
399 a->fmr(F15, F15); // 19
400 a->fmr(F16, F16); // 20
401
402 // ;; 5
403 a->nop(); // 21
404 a->fmr(F17, F17); // 22
405 a->fmr(F18, F18); // 23
406 a->endgroup(); // 24
407 // ------- sector 24 ------------
408
409 // ;; 6
410 a->nop(); // 25
411 a->nop(); // 26
412 a->fmr(F19, F19); // 27
413 a->fmr(F20, F20); // 28
414
415 // ;; 7
416 a->nop(); // 29
417 a->fmr(F21, F21); // 30
418 a->fmr(F22, F22); // 31
419 a->brnop0(); // 32
420
421 // ------- sector 32 ------------
422 }
423
424 // ;; 8
425 a->cmpdi(CCR0, R4, unroll); // 33
426 a->bge(CCR0, l1); // 34
427 a->blr();
428
429 // Emit code.
430 void (*test2)() = (void(*)())(void *)a->function_entry();
431 // uint32_t *code = (uint32_t *)a->pc();
432
433 Label l2;
434
435 a->li(R4, 1);
436 a->sldi(R4, R4, 28);
437 a->b(l2);
438 a->align(CodeEntryAlignment);
439
440 a->bind(l2);
441
442 for (int i = 0; i < unroll; i++) {
443 // Schleife 2
444 // ------- sector 0 ------------
445 // ;; 0
446 a->brnop0(); // 1
447 a->nop(); // 2
448 //a->cmpdi(CCR0, R4, unroll);
449 a->fpnop0(); // 3
450 a->fpnop1(); // 4
451 a->addi(R4,R4, -1); // 5
452
453 // ;; 1
454
455 a->nop(); // 6
456 a->fmr(F6, F6); // 7
457 a->fmr(F7, F7); // 8
458 // ------- sector 8 ---------------
459
460 // ;; 2
461 a->endgroup(); // 9
462
463 // ;; 3
464 a->nop(); // 10
465 a->nop(); // 11
466 a->fmr(F8, F8); // 12
467
468 // ;; 4
469 a->fmr(F9, F9); // 13
470 a->nop(); // 14
471 a->fmr(F10, F10); // 15
472
473 // ;; 5
474 a->fmr(F11, F11); // 16
475 // -------- sector 16 -------------
476
477 // ;; 6
478 a->endgroup(); // 17
479
480 // ;; 7
481 a->nop(); // 18
482 a->nop(); // 19
483 a->fmr(F15, F15); // 20
484
485 // ;; 8
486 a->fmr(F16, F16); // 21
487 a->nop(); // 22
488 a->fmr(F17, F17); // 23
489
490 // ;; 9
491 a->fmr(F18, F18); // 24
492 // -------- sector 24 -------------
493
494 // ;; 10
495 a->endgroup(); // 25
496
497 // ;; 11
498 a->nop(); // 26
499 a->nop(); // 27
500 a->fmr(F19, F19); // 28
501
502 // ;; 12
503 a->fmr(F20, F20); // 29
504 a->nop(); // 30
505 a->fmr(F21, F21); // 31
506
507 // ;; 13
508 a->fmr(F22, F22); // 32
509 }
510
511 // -------- sector 32 -------------
512 // ;; 14
513 a->cmpdi(CCR0, R4, unroll); // 33
514 a->bge(CCR0, l2); // 34
515
516 a->blr();
517 uint32_t *code_end = (uint32_t *)a->pc();
518 a->flush();
519
520 double loop1_seconds,loop2_seconds, rel_diff;
521 uint64_t start1, stop1;
522
523 start1 = os::current_thread_cpu_time(false);
524 (*test1)();
525 stop1 = os::current_thread_cpu_time(false);
526 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
527
528
529 start1 = os::current_thread_cpu_time(false);
530 (*test2)();
531 stop1 = os::current_thread_cpu_time(false);
532
533 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
534
535 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
536
537 if (PrintAssembly) {
538 ttyLocker ttyl;
539 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
540 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
541 tty->print_cr("Time loop1 :%f", loop1_seconds);
542 tty->print_cr("Time loop2 :%f", loop2_seconds);
543 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
544
545 if (rel_diff > 12.0) {
546 tty->print_cr("Section Size 8 Instructions");
547 } else{
548 tty->print_cr("Section Size 32 Instructions or Power5");
549 }
550 }
551
552 #if 0 // TODO: PPC port
553 // Set sector size (if not set explicitly).
554 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
555 if (rel_diff > 12.0) {
556 PdScheduling::power6SectorSize = 0x20;
557 } else {
558 PdScheduling::power6SectorSize = 0x80;
559 }
560 } else if (Power6SectorSize128PPC64) {
561 PdScheduling::power6SectorSize = 0x80;
562 } else {
563 PdScheduling::power6SectorSize = 0x20;
564 }
565 #endif
566 if (UsePower6SchedulerPPC64) Unimplemented();
567 }
568 #endif // COMPILER2
569
570 void VM_Version::determine_features() {
571 #if defined(ABI_ELFv2)
572 // 1 InstWord per call for the blr instruction.
573 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
574 #else
575 // 7 InstWords for each call (function descriptor + blr instruction).
576 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
577 #endif
578 int features = 0;
579
580 // create test area
581 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
582 char test_area[BUFFER_SIZE];
583 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
584
585 // Allocate space for the code.
586 ResourceMark rm;
587 CodeBuffer cb("detect_cpu_features", code_size, 0);
588 MacroAssembler* a = new MacroAssembler(&cb);
589
590 // Must be set to true so we can generate the test code.
591 _features = VM_Version::all_features_m;
592
593 // Emit code.
594 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
595 uint32_t *code = (uint32_t *)a->pc();
596 // Don't use R0 in ldarx.
597 // Keep R3_ARG1 unmodified, it contains &field (see below).
598 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
599 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
600 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
601 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
602 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
603 a->cmpb(R7, R5, R6); // code[4] -> cmpb
604 a->popcntb(R7, R5); // code[5] -> popcntb
605 a->popcntw(R7, R5); // code[6] -> popcntw
606 a->fcfids(F3, F4); // code[7] -> fcfids
607 a->vand(VR0, VR0, VR0); // code[8] -> vand
608 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
609 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
610 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
611 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
612 a->tcheck(0); // code[12] -> tcheck
613 a->blr();
614
615 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
616 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
617 a->dcbz(R3_ARG1); // R3_ARG1 = addr
618 a->blr();
619
620 uint32_t *code_end = (uint32_t *)a->pc();
621 a->flush();
622 _features = VM_Version::unknown_m;
623
624 // Print the detection code.
625 if (PrintAssembly) {
626 ttyLocker ttyl;
627 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
628 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
629 }
630
631 // Measure cache line size.
632 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
633 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
634 int count = 0; // count zeroed bytes
635 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
636 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
637 _L1_data_cache_line_size = count;
638
639 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
640 VM_Version::_is_determine_features_test_running = true;
641 // We must align the first argument to 16 bytes because of the lqarx check.
642 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
643 VM_Version::_is_determine_features_test_running = false;
644
645 // determine which instructions are legal.
646 int feature_cntr = 0;
647 if (code[feature_cntr++]) features |= fsqrt_m;
648 if (code[feature_cntr++]) features |= fsqrts_m;
649 if (code[feature_cntr++]) features |= isel_m;
650 if (code[feature_cntr++]) features |= lxarxeh_m;
651 if (code[feature_cntr++]) features |= cmpb_m;
652 if (code[feature_cntr++]) features |= popcntb_m;
653 if (code[feature_cntr++]) features |= popcntw_m;
654 if (code[feature_cntr++]) features |= fcfids_m;
655 if (code[feature_cntr++]) features |= vand_m;
656 if (code[feature_cntr++]) features |= lqarx_m;
657 if (code[feature_cntr++]) features |= vcipher_m;
658 if (code[feature_cntr++]) features |= vpmsumb_m;
659 if (code[feature_cntr++]) features |= tcheck_m;
660
661 // Print the detection code.
662 if (PrintAssembly) {
663 ttyLocker ttyl;
664 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
665 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
666 }
667
668 _features = features;
669 }
670
671 // Power 8: Configure Data Stream Control Register.
672 void VM_Version::config_dscr() {
673 assert(has_tcheck(), "Only execute on Power 8 or later!");
674
675 // 7 InstWords for each call (function descriptor + blr instruction).
676 const int code_size = (2+2*7)*BytesPerInstWord;
677
678 // Allocate space for the code.
679 ResourceMark rm;
680 CodeBuffer cb("config_dscr", code_size, 0);
681 MacroAssembler* a = new MacroAssembler(&cb);
682
683 // Emit code.
684 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
685 uint32_t *code = (uint32_t *)a->pc();
686 a->mfdscr(R3);
687 a->blr();
688
689 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
690 a->mtdscr(R3);
691 a->blr();
692
693 uint32_t *code_end = (uint32_t *)a->pc();
694 a->flush();
695
696 // Print the detection code.
697 if (PrintAssembly) {
698 ttyLocker ttyl;
699 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
700 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
701 }
702
703 // Apply the configuration if needed.
704 uint64_t dscr_val = (*get_dscr)();
705 if (Verbose) {
706 tty->print_cr("dscr value was 0x%lx" , dscr_val);
707 }
708 bool change_requested = false;
709 if (DSCR_PPC64 != (uintx)-1) {
710 dscr_val = DSCR_PPC64;
711 change_requested = true;
712 }
713 if (DSCR_DPFD_PPC64 <= 7) {
714 uint64_t mask = 0x7;
715 if ((dscr_val & mask) != DSCR_DPFD_PPC64) {
716 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64);
717 change_requested = true;
718 }
719 }
720 if (DSCR_URG_PPC64 <= 7) {
721 uint64_t mask = 0x7 << 6;
722 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
723 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
724 change_requested = true;
725 }
726 }
727 if (change_requested) {
728 (*set_dscr)(dscr_val);
729 if (Verbose) {
730 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
731 }
732 }
733 }
734
735 static uint64_t saved_features = 0;
736
737 void VM_Version::allow_all() {
738 saved_features = _features;
739 _features = all_features_m;
740 }
741
742 void VM_Version::revert() {
743 _features = saved_features;
744 }