1 //
2 // Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29,*/ // global TOC
451 R30,
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29,*/
488 R30,
489 R31
490 );
491
492 reg_class rscratch1_bits32_reg(R11);
493 reg_class rscratch2_bits32_reg(R12);
494 reg_class rarg1_bits32_reg(R3);
495 reg_class rarg2_bits32_reg(R4);
496 reg_class rarg3_bits32_reg(R5);
497 reg_class rarg4_bits32_reg(R6);
498
499 // ----------------------------
500 // 64 Bit Register Classes
501 // ----------------------------
502 // 64-bit build means 64-bit pointers means hi/lo pairs
503
504 reg_class rscratch1_bits64_reg(R11_H, R11);
505 reg_class rscratch2_bits64_reg(R12_H, R12);
506 reg_class rarg1_bits64_reg(R3_H, R3);
507 reg_class rarg2_bits64_reg(R4_H, R4);
508 reg_class rarg3_bits64_reg(R5_H, R5);
509 reg_class rarg4_bits64_reg(R6_H, R6);
510 // Thread register, 'written' by tlsLoadP, see there.
511 reg_class thread_bits64_reg(R16_H, R16);
512
513 reg_class r19_bits64_reg(R19_H, R19);
514
515 // 64 bit registers that can be read and written i.e. these registers
516 // can be dest (or src) of normal instructions.
517 reg_class bits64_reg_rw(
518 /*R0_H, R0*/ // R0
519 /*R1_H, R1*/ // SP
520 R2_H, R2, // TOC
521 R3_H, R3,
522 R4_H, R4,
523 R5_H, R5,
524 R6_H, R6,
525 R7_H, R7,
526 R8_H, R8,
527 R9_H, R9,
528 R10_H, R10,
529 R11_H, R11,
530 R12_H, R12,
531 /*R13_H, R13*/ // system thread id
532 R14_H, R14,
533 R15_H, R15,
534 /*R16_H, R16*/ // R16_thread
535 R17_H, R17,
536 R18_H, R18,
537 R19_H, R19,
538 R20_H, R20,
539 R21_H, R21,
540 R22_H, R22,
541 R23_H, R23,
542 R24_H, R24,
543 R25_H, R25,
544 R26_H, R26,
545 R27_H, R27,
546 R28_H, R28,
547 /*R29_H, R29,*/
548 R30_H, R30,
549 R31_H, R31
550 );
551
552 // 64 bit registers used excluding r2, r11 and r12
553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
554 // r2, r11 and r12 internally.
555 reg_class bits64_reg_leaf_call(
556 /*R0_H, R0*/ // R0
557 /*R1_H, R1*/ // SP
558 /*R2_H, R2*/ // TOC
559 R3_H, R3,
560 R4_H, R4,
561 R5_H, R5,
562 R6_H, R6,
563 R7_H, R7,
564 R8_H, R8,
565 R9_H, R9,
566 R10_H, R10,
567 /*R11_H, R11*/
568 /*R12_H, R12*/
569 /*R13_H, R13*/ // system thread id
570 R14_H, R14,
571 R15_H, R15,
572 /*R16_H, R16*/ // R16_thread
573 R17_H, R17,
574 R18_H, R18,
575 R19_H, R19,
576 R20_H, R20,
577 R21_H, R21,
578 R22_H, R22,
579 R23_H, R23,
580 R24_H, R24,
581 R25_H, R25,
582 R26_H, R26,
583 R27_H, R27,
584 R28_H, R28,
585 /*R29_H, R29,*/
586 R30_H, R30,
587 R31_H, R31
588 );
589
590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
591 // which uses r19 as inline cache internally and expanded LeafCall which uses
592 // r2, r11 and r12 internally.
593 reg_class bits64_constant_table_base(
594 /*R0_H, R0*/ // R0
595 /*R1_H, R1*/ // SP
596 /*R2_H, R2*/ // TOC
597 R3_H, R3,
598 R4_H, R4,
599 R5_H, R5,
600 R6_H, R6,
601 R7_H, R7,
602 R8_H, R8,
603 R9_H, R9,
604 R10_H, R10,
605 /*R11_H, R11*/
606 /*R12_H, R12*/
607 /*R13_H, R13*/ // system thread id
608 R14_H, R14,
609 R15_H, R15,
610 /*R16_H, R16*/ // R16_thread
611 R17_H, R17,
612 R18_H, R18,
613 /*R19_H, R19*/
614 R20_H, R20,
615 R21_H, R21,
616 R22_H, R22,
617 R23_H, R23,
618 R24_H, R24,
619 R25_H, R25,
620 R26_H, R26,
621 R27_H, R27,
622 R28_H, R28,
623 /*R29_H, R29,*/
624 R30_H, R30,
625 R31_H, R31
626 );
627
628 // 64 bit registers that can only be read i.e. these registers can
629 // only be src of all instructions.
630 reg_class bits64_reg_ro(
631 /*R0_H, R0*/ // R0
632 R1_H, R1,
633 R2_H, R2, // TOC
634 R3_H, R3,
635 R4_H, R4,
636 R5_H, R5,
637 R6_H, R6,
638 R7_H, R7,
639 R8_H, R8,
640 R9_H, R9,
641 R10_H, R10,
642 R11_H, R11,
643 R12_H, R12,
644 /*R13_H, R13*/ // system thread id
645 R14_H, R14,
646 R15_H, R15,
647 R16_H, R16, // R16_thread
648 R17_H, R17,
649 R18_H, R18,
650 R19_H, R19,
651 R20_H, R20,
652 R21_H, R21,
653 R22_H, R22,
654 R23_H, R23,
655 R24_H, R24,
656 R25_H, R25,
657 R26_H, R26,
658 R27_H, R27,
659 R28_H, R28,
660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
661 R30_H, R30,
662 R31_H, R31
663 );
664
665
666 // ----------------------------
667 // Special Class for Condition Code Flags Register
668
669 reg_class int_flags(
670 /*CCR0*/ // scratch
671 /*CCR1*/ // scratch
672 /*CCR2*/ // nv!
673 /*CCR3*/ // nv!
674 /*CCR4*/ // nv!
675 CCR5,
676 CCR6,
677 CCR7
678 );
679
680 reg_class int_flags_ro(
681 CCR0,
682 CCR1,
683 CCR2,
684 CCR3,
685 CCR4,
686 CCR5,
687 CCR6,
688 CCR7
689 );
690
691 reg_class int_flags_CR0(CCR0);
692 reg_class int_flags_CR1(CCR1);
693 reg_class int_flags_CR6(CCR6);
694 reg_class ctr_reg(SR_CTR);
695
696 // ----------------------------
697 // Float Register Classes
698 // ----------------------------
699
700 reg_class flt_reg(
701 F0,
702 F1,
703 F2,
704 F3,
705 F4,
706 F5,
707 F6,
708 F7,
709 F8,
710 F9,
711 F10,
712 F11,
713 F12,
714 F13,
715 F14, // nv!
716 F15, // nv!
717 F16, // nv!
718 F17, // nv!
719 F18, // nv!
720 F19, // nv!
721 F20, // nv!
722 F21, // nv!
723 F22, // nv!
724 F23, // nv!
725 F24, // nv!
726 F25, // nv!
727 F26, // nv!
728 F27, // nv!
729 F28, // nv!
730 F29, // nv!
731 F30, // nv!
732 F31 // nv!
733 );
734
735 // Double precision float registers have virtual `high halves' that
736 // are needed by the allocator.
737 reg_class dbl_reg(
738 F0, F0_H,
739 F1, F1_H,
740 F2, F2_H,
741 F3, F3_H,
742 F4, F4_H,
743 F5, F5_H,
744 F6, F6_H,
745 F7, F7_H,
746 F8, F8_H,
747 F9, F9_H,
748 F10, F10_H,
749 F11, F11_H,
750 F12, F12_H,
751 F13, F13_H,
752 F14, F14_H, // nv!
753 F15, F15_H, // nv!
754 F16, F16_H, // nv!
755 F17, F17_H, // nv!
756 F18, F18_H, // nv!
757 F19, F19_H, // nv!
758 F20, F20_H, // nv!
759 F21, F21_H, // nv!
760 F22, F22_H, // nv!
761 F23, F23_H, // nv!
762 F24, F24_H, // nv!
763 F25, F25_H, // nv!
764 F26, F26_H, // nv!
765 F27, F27_H, // nv!
766 F28, F28_H, // nv!
767 F29, F29_H, // nv!
768 F30, F30_H, // nv!
769 F31, F31_H // nv!
770 );
771
772 %}
773
774 //----------DEFINITION BLOCK---------------------------------------------------
775 // Define name --> value mappings to inform the ADLC of an integer valued name
776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
777 // Format:
778 // int_def <name> ( <int_value>, <expression>);
779 // Generated Code in ad_<arch>.hpp
780 // #define <name> (<expression>)
781 // // value == <int_value>
782 // Generated code in ad_<arch>.cpp adlc_verification()
783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
784 //
785 definitions %{
786 // The default cost (of an ALU instruction).
787 int_def DEFAULT_COST_LOW ( 30, 30);
788 int_def DEFAULT_COST ( 100, 100);
789 int_def HUGE_COST (1000000, 1000000);
790
791 // Memory refs
792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
794
795 // Branches are even more expensive.
796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
797 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
798 %}
799
800
801 //----------SOURCE BLOCK-------------------------------------------------------
802 // This is a block of C++ code which provides values, functions, and
803 // definitions necessary in the rest of the architecture description.
804 source_hpp %{
805 // Header information of the source block.
806 // Method declarations/definitions which are used outside
807 // the ad-scope can conveniently be defined here.
808 //
809 // To keep related declarations/definitions/uses close together,
810 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
811
812 // Returns true if Node n is followed by a MemBar node that
813 // will do an acquire. If so, this node must not do the acquire
814 // operation.
815 bool followed_by_acquire(const Node *n);
816 %}
817
818 source %{
819
820 // Optimize load-acquire.
821 //
822 // Check if acquire is unnecessary due to following operation that does
823 // acquire anyways.
824 // Walk the pattern:
825 //
826 // n: Load.acq
827 // |
828 // MemBarAcquire
829 // | |
830 // Proj(ctrl) Proj(mem)
831 // | |
832 // MemBarRelease/Volatile
833 //
834 bool followed_by_acquire(const Node *load) {
835 assert(load->is_Load(), "So far implemented only for loads.");
836
837 // Find MemBarAcquire.
838 const Node *mba = NULL;
839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
840 const Node *out = load->fast_out(i);
841 if (out->Opcode() == Op_MemBarAcquire) {
842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
843 mba = out;
844 break;
845 }
846 }
847 if (!mba) return false;
848
849 // Find following MemBar node.
850 //
851 // The following node must be reachable by control AND memory
852 // edge to assure no other operations are in between the two nodes.
853 //
854 // So first get the Proj node, mem_proj, to use it to iterate forward.
855 Node *mem_proj = NULL;
856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
858 assert(mem_proj->is_Proj(), "only projections here");
859 ProjNode *proj = mem_proj->as_Proj();
860 if (proj->_con == TypeFunc::Memory &&
861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
862 break;
863 }
864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
865
866 // Search MemBar behind Proj. If there are other memory operations
867 // behind the Proj we lost.
868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
869 Node *x = mem_proj->fast_out(j);
870 // Proj might have an edge to a store or load node which precedes the membar.
871 if (x->is_Mem()) return false;
872
873 // On PPC64 release and volatile are implemented by an instruction
874 // that also has acquire semantics. I.e. there is no need for an
875 // acquire before these.
876 int xop = x->Opcode();
877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
878 // Make sure we're not missing Call/Phi/MergeMem by checking
879 // control edges. The control edge must directly lead back
880 // to the MemBarAcquire
881 Node *ctrl_proj = x->in(0);
882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
883 return true;
884 }
885 }
886 }
887
888 return false;
889 }
890
891 #define __ _masm.
892
893 // Tertiary op of a LoadP or StoreP encoding.
894 #define REGP_OP true
895
896 // ****************************************************************************
897
898 // REQUIRED FUNCTIONALITY
899
900 // !!!!! Special hack to get all type of calls to specify the byte offset
901 // from the start of the call to the point where the return address
902 // will point.
903
904 // PPC port: Removed use of lazy constant construct.
905
906 int MachCallStaticJavaNode::ret_addr_offset() {
907 // It's only a single branch-and-link instruction.
908 return 4;
909 }
910
911 int MachCallDynamicJavaNode::ret_addr_offset() {
912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
913 // postalloc expanded calls if we use inline caches and do not update method data.
914 if (UseInlineCaches)
915 return 4;
916
917 int vtable_index = this->_vtable_index;
918 if (vtable_index < 0) {
919 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
921 return 12;
922 } else {
923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
924 return 24;
925 }
926 }
927
928 int MachCallRuntimeNode::ret_addr_offset() {
929 #if defined(ABI_ELFv2)
930 return 28;
931 #else
932 return 40;
933 #endif
934 }
935
936 //=============================================================================
937
938 // condition code conversions
939
940 static int cc_to_boint(int cc) {
941 return Assembler::bcondCRbiIs0 | (cc & 8);
942 }
943
944 static int cc_to_inverse_boint(int cc) {
945 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
946 }
947
948 static int cc_to_biint(int cc, int flags_reg) {
949 return (flags_reg << 2) | (cc & 3);
950 }
951
952 //=============================================================================
953
954 // Compute padding required for nodes which need alignment. The padding
955 // is the number of bytes (not instructions) which will be inserted before
956 // the instruction. The padding must match the size of a NOP instruction.
957
958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
959 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1
960 }
961
962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
963 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1
964 }
965
966 int string_indexOfCharNode::compute_padding(int current_offset) const {
967 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1
968 }
969
970 int string_indexOf_immNode::compute_padding(int current_offset) const {
971 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof(constant needlecount)
972 }
973
974 int string_indexOfNode::compute_padding(int current_offset) const {
975 return (1*4-current_offset)&31; // see MacroAssembler::string_indexof(variable needlecount)
976 }
977
978 int string_compareNode::compute_padding(int current_offset) const {
979 return (2*4-current_offset)&31; // see MacroAssembler::string_compare
980 }
981
982 int string_equals_immNode::compute_padding(int current_offset) const {
983 if (opnd_array(3)->constant() < 16) return 0; // For strlen < 16 no nops because loop completely unrolled
984 return (2*4-current_offset)&31; // Genral case - see MacroAssembler::char_arrays_equalsImm
985 }
986
987 int string_equalsNode::compute_padding(int current_offset) const {
988 return (7*4-current_offset)&31; // see MacroAssembler::char_arrays_equals
989 }
990
991 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
992 return (2*4-current_offset)&31; // see MacroAssembler::clear_memory_doubleword
993 }
994
995 //=============================================================================
996
997 // Indicate if the safepoint node needs the polling page as an input.
998 bool SafePointNode::needs_polling_address_input() {
999 // The address is loaded from thread by a seperate node.
1000 return true;
1001 }
1002
1003 //=============================================================================
1004
1005 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1006 void emit_break(CodeBuffer &cbuf) {
1007 MacroAssembler _masm(&cbuf);
1008 __ illtrap();
1009 }
1010
1011 #ifndef PRODUCT
1012 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1013 st->print("BREAKPOINT");
1014 }
1015 #endif
1016
1017 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1018 emit_break(cbuf);
1019 }
1020
1021 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1022 return MachNode::size(ra_);
1023 }
1024
1025 //=============================================================================
1026
1027 void emit_nop(CodeBuffer &cbuf) {
1028 MacroAssembler _masm(&cbuf);
1029 __ nop();
1030 }
1031
1032 static inline void emit_long(CodeBuffer &cbuf, int value) {
1033 *((int*)(cbuf.insts_end())) = value;
1034 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1035 }
1036
1037 //=============================================================================
1038
1039 %} // interrupt source
1040
1041 source_hpp %{ // Header information of the source block.
1042
1043 //--------------------------------------------------------------
1044 //---< Used for optimization in Compile::Shorten_branches >---
1045 //--------------------------------------------------------------
1046
1047 class CallStubImpl {
1048
1049 public:
1050
1051 // Emit call stub, compiled java to interpreter.
1052 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1053
1054 // Size of call trampoline stub.
1055 // This doesn't need to be accurate to the byte, but it
1056 // must be larger than or equal to the real size of the stub.
1057 static uint size_call_trampoline() {
1058 return MacroAssembler::trampoline_stub_size;
1059 }
1060
1061 // number of relocations needed by a call trampoline stub
1062 static uint reloc_call_trampoline() {
1063 return 5;
1064 }
1065
1066 };
1067
1068 %} // end source_hpp
1069
1070 source %{
1071
1072 // Emit a trampoline stub for a call to a target which is too far away.
1073 //
1074 // code sequences:
1075 //
1076 // call-site:
1077 // branch-and-link to <destination> or <trampoline stub>
1078 //
1079 // Related trampoline stub for this call-site in the stub section:
1080 // load the call target from the constant pool
1081 // branch via CTR (LR/link still points to the call-site above)
1082
1083 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1084 address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset);
1085 if (stub == NULL) {
1086 ciEnv::current()->record_out_of_memory_failure();
1087 }
1088 }
1089
1090 //=============================================================================
1091
1092 // Emit an inline branch-and-link call and a related trampoline stub.
1093 //
1094 // code sequences:
1095 //
1096 // call-site:
1097 // branch-and-link to <destination> or <trampoline stub>
1098 //
1099 // Related trampoline stub for this call-site in the stub section:
1100 // load the call target from the constant pool
1101 // branch via CTR (LR/link still points to the call-site above)
1102 //
1103
1104 typedef struct {
1105 int insts_call_instruction_offset;
1106 int ret_addr_offset;
1107 } EmitCallOffsets;
1108
1109 // Emit a branch-and-link instruction that branches to a trampoline.
1110 // - Remember the offset of the branch-and-link instruction.
1111 // - Add a relocation at the branch-and-link instruction.
1112 // - Emit a branch-and-link.
1113 // - Remember the return pc offset.
1114 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1115 EmitCallOffsets offsets = { -1, -1 };
1116 const int start_offset = __ offset();
1117 offsets.insts_call_instruction_offset = __ offset();
1118
1119 // No entry point given, use the current pc.
1120 if (entry_point == NULL) entry_point = __ pc();
1121
1122 if (!Compile::current()->in_scratch_emit_size()) {
1123 // Put the entry point as a constant into the constant pool.
1124 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1125 if (entry_point_toc_addr == NULL) {
1126 ciEnv::current()->record_out_of_memory_failure();
1127 return offsets;
1128 }
1129 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1130
1131 // Emit the trampoline stub which will be related to the branch-and-link below.
1132 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1133 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1134 __ relocate(rtype);
1135 }
1136
1137 // Note: At this point we do not have the address of the trampoline
1138 // stub, and the entry point might be too far away for bl, so __ pc()
1139 // serves as dummy and the bl will be patched later.
1140 __ bl((address) __ pc());
1141
1142 offsets.ret_addr_offset = __ offset() - start_offset;
1143
1144 return offsets;
1145 }
1146
1147 //=============================================================================
1148
1149 // Factory for creating loadConL* nodes for large/small constant pool.
1150
1151 static inline jlong replicate_immF(float con) {
1152 // Replicate float con 2 times and pack into vector.
1153 int val = *((int*)&con);
1154 jlong lval = val;
1155 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1156 return lval;
1157 }
1158
1159 //=============================================================================
1160
1161 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1162 int Compile::ConstantTable::calculate_table_base_offset() const {
1163 return 0; // absolute addressing, no offset
1164 }
1165
1166 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1167 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1168 iRegPdstOper *op_dst = new iRegPdstOper();
1169 MachNode *m1 = new loadToc_hiNode();
1170 MachNode *m2 = new loadToc_loNode();
1171
1172 m1->add_req(NULL);
1173 m2->add_req(NULL, m1);
1174 m1->_opnds[0] = op_dst;
1175 m2->_opnds[0] = op_dst;
1176 m2->_opnds[1] = op_dst;
1177 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1178 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1179 nodes->push(m1);
1180 nodes->push(m2);
1181 }
1182
1183 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1184 // Is postalloc expanded.
1185 ShouldNotReachHere();
1186 }
1187
1188 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1189 return 0;
1190 }
1191
1192 #ifndef PRODUCT
1193 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1194 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1195 }
1196 #endif
1197
1198 //=============================================================================
1199
1200 #ifndef PRODUCT
1201 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1202 Compile* C = ra_->C;
1203 const long framesize = C->frame_slots() << LogBytesPerInt;
1204
1205 st->print("PROLOG\n\t");
1206 if (C->need_stack_bang(framesize)) {
1207 st->print("stack_overflow_check\n\t");
1208 }
1209
1210 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1211 st->print("save return pc\n\t");
1212 st->print("push frame %ld\n\t", -framesize);
1213 }
1214 }
1215 #endif
1216
1217 // Macro used instead of the common __ to emulate the pipes of PPC.
1218 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1219 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1220 // still no scheduling of this code is possible, the micro scheduler is aware of the
1221 // code and can update its internal data. The following mechanism is used to achieve this:
1222 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1223 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1224 #if 0 // TODO: PPC port
1225 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1226 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1227 _masm.
1228 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1229 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1230 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1231 C->hb_scheduling()->_pdScheduling->advance_offset
1232 #else
1233 #define ___(op) if (UsePower6SchedulerPPC64) \
1234 Unimplemented(); \
1235 _masm.
1236 #define ___stop if (UsePower6SchedulerPPC64) \
1237 Unimplemented()
1238 #define ___advance if (UsePower6SchedulerPPC64) \
1239 Unimplemented()
1240 #endif
1241
1242 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1243 Compile* C = ra_->C;
1244 MacroAssembler _masm(&cbuf);
1245
1246 const long framesize = C->frame_size_in_bytes();
1247 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1248
1249 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1250
1251 const Register return_pc = R20; // Must match return_addr() in frame section.
1252 const Register callers_sp = R21;
1253 const Register push_frame_temp = R22;
1254 const Register toc_temp = R23;
1255 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1256
1257 if (method_is_frameless) {
1258 // Add nop at beginning of all frameless methods to prevent any
1259 // oop instructions from getting overwritten by make_not_entrant
1260 // (patching attempt would fail).
1261 ___(nop) nop();
1262 } else {
1263 // Get return pc.
1264 ___(mflr) mflr(return_pc);
1265 }
1266
1267 // Calls to C2R adapters often do not accept exceptional returns.
1268 // We require that their callers must bang for them. But be
1269 // careful, because some VM calls (such as call site linkage) can
1270 // use several kilobytes of stack. But the stack safety zone should
1271 // account for that. See bugs 4446381, 4468289, 4497237.
1272
1273 int bangsize = C->bang_size_in_bytes();
1274 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1275 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1276 // Unfortunately we cannot use the function provided in
1277 // assembler.cpp as we have to emulate the pipes. So I had to
1278 // insert the code of generate_stack_overflow_check(), see
1279 // assembler.cpp for some illuminative comments.
1280 const int page_size = os::vm_page_size();
1281 int bang_end = JavaThread::stack_shadow_zone_size();
1282
1283 // This is how far the previous frame's stack banging extended.
1284 const int bang_end_safe = bang_end;
1285
1286 if (bangsize > page_size) {
1287 bang_end += bangsize;
1288 }
1289
1290 int bang_offset = bang_end_safe;
1291
1292 while (bang_offset <= bang_end) {
1293 // Need at least one stack bang at end of shadow zone.
1294
1295 // Again I had to copy code, this time from assembler_ppc.cpp,
1296 // bang_stack_with_offset - see there for comments.
1297
1298 // Stack grows down, caller passes positive offset.
1299 assert(bang_offset > 0, "must bang with positive offset");
1300
1301 long stdoffset = -bang_offset;
1302
1303 if (Assembler::is_simm(stdoffset, 16)) {
1304 // Signed 16 bit offset, a simple std is ok.
1305 if (UseLoadInstructionsForStackBangingPPC64) {
1306 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1307 } else {
1308 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1309 }
1310 } else if (Assembler::is_simm(stdoffset, 31)) {
1311 // Use largeoffset calculations for addis & ld/std.
1312 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1313 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1314
1315 Register tmp = R11;
1316 ___(addis) addis(tmp, R1_SP, hi);
1317 if (UseLoadInstructionsForStackBangingPPC64) {
1318 ___(ld) ld(R0, lo, tmp);
1319 } else {
1320 ___(std) std(R0, lo, tmp);
1321 }
1322 } else {
1323 ShouldNotReachHere();
1324 }
1325
1326 bang_offset += page_size;
1327 }
1328 // R11 trashed
1329 } // C->need_stack_bang(framesize) && UseStackBanging
1330
1331 unsigned int bytes = (unsigned int)framesize;
1332 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1333 ciMethod *currMethod = C->method();
1334
1335 // Optimized version for most common case.
1336 if (UsePower6SchedulerPPC64 &&
1337 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1338 !(false /* ConstantsALot TODO: PPC port*/)) {
1339 ___(or) mr(callers_sp, R1_SP);
1340 ___(std) std(return_pc, _abi(lr), R1_SP);
1341 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1342 return;
1343 }
1344
1345 if (!method_is_frameless) {
1346 // Get callers sp.
1347 ___(or) mr(callers_sp, R1_SP);
1348
1349 // Push method's frame, modifies SP.
1350 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1351 // The ABI is already accounted for in 'framesize' via the
1352 // 'out_preserve' area.
1353 Register tmp = push_frame_temp;
1354 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1355 if (Assembler::is_simm(-offset, 16)) {
1356 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1357 } else {
1358 long x = -offset;
1359 // Had to insert load_const(tmp, -offset).
1360 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1361 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1362 ___(rldicr) sldi(tmp, tmp, 32);
1363 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1364 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1365
1366 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1367 }
1368 }
1369 #if 0 // TODO: PPC port
1370 // For testing large constant pools, emit a lot of constants to constant pool.
1371 // "Randomize" const_size.
1372 if (ConstantsALot) {
1373 const int num_consts = const_size();
1374 for (int i = 0; i < num_consts; i++) {
1375 __ long_constant(0xB0B5B00BBABE);
1376 }
1377 }
1378 #endif
1379 if (!method_is_frameless) {
1380 // Save return pc.
1381 ___(std) std(return_pc, _abi(lr), callers_sp);
1382 }
1383 }
1384 #undef ___
1385 #undef ___stop
1386 #undef ___advance
1387
1388 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1389 // Variable size. determine dynamically.
1390 return MachNode::size(ra_);
1391 }
1392
1393 int MachPrologNode::reloc() const {
1394 // Return number of relocatable values contained in this instruction.
1395 return 1; // 1 reloc entry for load_const(toc).
1396 }
1397
1398 //=============================================================================
1399
1400 #ifndef PRODUCT
1401 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1402 Compile* C = ra_->C;
1403
1404 st->print("EPILOG\n\t");
1405 st->print("restore return pc\n\t");
1406 st->print("pop frame\n\t");
1407
1408 if (do_polling() && C->is_method_compilation()) {
1409 st->print("touch polling page\n\t");
1410 }
1411 }
1412 #endif
1413
1414 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1415 Compile* C = ra_->C;
1416 MacroAssembler _masm(&cbuf);
1417
1418 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1419 assert(framesize >= 0, "negative frame-size?");
1420
1421 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1422 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1423 const Register return_pc = R11;
1424 const Register polling_page = R12;
1425
1426 if (!method_is_frameless) {
1427 // Restore return pc relative to callers' sp.
1428 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1429 }
1430
1431 if (method_needs_polling) {
1432 if (LoadPollAddressFromThread) {
1433 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1434 Unimplemented();
1435 } else {
1436 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1437 }
1438 }
1439
1440 if (!method_is_frameless) {
1441 // Move return pc to LR.
1442 __ mtlr(return_pc);
1443 // Pop frame (fixed frame-size).
1444 __ addi(R1_SP, R1_SP, (int)framesize);
1445 }
1446
1447 if (method_needs_polling) {
1448 // We need to mark the code position where the load from the safepoint
1449 // polling page was emitted as relocInfo::poll_return_type here.
1450 __ relocate(relocInfo::poll_return_type);
1451 __ load_from_polling_page(polling_page);
1452 }
1453 }
1454
1455 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1456 // Variable size. Determine dynamically.
1457 return MachNode::size(ra_);
1458 }
1459
1460 int MachEpilogNode::reloc() const {
1461 // Return number of relocatable values contained in this instruction.
1462 return 1; // 1 for load_from_polling_page.
1463 }
1464
1465 const Pipeline * MachEpilogNode::pipeline() const {
1466 return MachNode::pipeline_class();
1467 }
1468
1469 // This method seems to be obsolete. It is declared in machnode.hpp
1470 // and defined in all *.ad files, but it is never called. Should we
1471 // get rid of it?
1472 int MachEpilogNode::safepoint_offset() const {
1473 assert(do_polling(), "no return for this epilog node");
1474 return 0;
1475 }
1476
1477 #if 0 // TODO: PPC port
1478 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1479 MacroAssembler _masm(&cbuf);
1480 if (LoadPollAddressFromThread) {
1481 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1482 } else {
1483 _masm.nop();
1484 }
1485 }
1486
1487 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1488 if (LoadPollAddressFromThread) {
1489 return 4;
1490 } else {
1491 return 4;
1492 }
1493 }
1494
1495 #ifndef PRODUCT
1496 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1497 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1498 }
1499 #endif
1500
1501 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1502 return RSCRATCH1_BITS64_REG_mask();
1503 }
1504 #endif // PPC port
1505
1506 // =============================================================================
1507
1508 // Figure out which register class each belongs in: rc_int, rc_float or
1509 // rc_stack.
1510 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1511
1512 static enum RC rc_class(OptoReg::Name reg) {
1513 // Return the register class for the given register. The given register
1514 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1515 // enumeration in adGlobals_ppc.hpp.
1516
1517 if (reg == OptoReg::Bad) return rc_bad;
1518
1519 // We have 64 integer register halves, starting at index 0.
1520 if (reg < 64) return rc_int;
1521
1522 // We have 64 floating-point register halves, starting at index 64.
1523 if (reg < 64+64) return rc_float;
1524
1525 // Between float regs & stack are the flags regs.
1526 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1527
1528 return rc_stack;
1529 }
1530
1531 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1532 bool do_print, Compile* C, outputStream *st) {
1533
1534 assert(opcode == Assembler::LD_OPCODE ||
1535 opcode == Assembler::STD_OPCODE ||
1536 opcode == Assembler::LWZ_OPCODE ||
1537 opcode == Assembler::STW_OPCODE ||
1538 opcode == Assembler::LFD_OPCODE ||
1539 opcode == Assembler::STFD_OPCODE ||
1540 opcode == Assembler::LFS_OPCODE ||
1541 opcode == Assembler::STFS_OPCODE,
1542 "opcode not supported");
1543
1544 if (cbuf) {
1545 int d =
1546 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1547 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1548 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1549 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1550 }
1551 #ifndef PRODUCT
1552 else if (do_print) {
1553 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1554 op_str,
1555 Matcher::regName[reg],
1556 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1557 }
1558 #endif
1559 return 4; // size
1560 }
1561
1562 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1563 Compile* C = ra_->C;
1564
1565 // Get registers to move.
1566 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1567 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1568 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1569 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1570
1571 enum RC src_hi_rc = rc_class(src_hi);
1572 enum RC src_lo_rc = rc_class(src_lo);
1573 enum RC dst_hi_rc = rc_class(dst_hi);
1574 enum RC dst_lo_rc = rc_class(dst_lo);
1575
1576 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1577 if (src_hi != OptoReg::Bad)
1578 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1579 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1580 "expected aligned-adjacent pairs");
1581 // Generate spill code!
1582 int size = 0;
1583
1584 if (src_lo == dst_lo && src_hi == dst_hi)
1585 return size; // Self copy, no move.
1586
1587 // --------------------------------------
1588 // Memory->Memory Spill. Use R0 to hold the value.
1589 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1590 int src_offset = ra_->reg2offset(src_lo);
1591 int dst_offset = ra_->reg2offset(dst_lo);
1592 if (src_hi != OptoReg::Bad) {
1593 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1594 "expected same type of move for high parts");
1595 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1596 if (!cbuf && !do_size) st->print("\n\t");
1597 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1598 } else {
1599 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1600 if (!cbuf && !do_size) st->print("\n\t");
1601 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1602 }
1603 return size;
1604 }
1605
1606 // --------------------------------------
1607 // Check for float->int copy; requires a trip through memory.
1608 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1609 Unimplemented();
1610 }
1611
1612 // --------------------------------------
1613 // Check for integer reg-reg copy.
1614 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1615 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1616 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1617 size = (Rsrc != Rdst) ? 4 : 0;
1618
1619 if (cbuf) {
1620 MacroAssembler _masm(cbuf);
1621 if (size) {
1622 __ mr(Rdst, Rsrc);
1623 }
1624 }
1625 #ifndef PRODUCT
1626 else if (!do_size) {
1627 if (size) {
1628 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1629 } else {
1630 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1631 }
1632 }
1633 #endif
1634 return size;
1635 }
1636
1637 // Check for integer store.
1638 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1639 int dst_offset = ra_->reg2offset(dst_lo);
1640 if (src_hi != OptoReg::Bad) {
1641 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1642 "expected same type of move for high parts");
1643 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1644 } else {
1645 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1646 }
1647 return size;
1648 }
1649
1650 // Check for integer load.
1651 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1652 int src_offset = ra_->reg2offset(src_lo);
1653 if (src_hi != OptoReg::Bad) {
1654 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1655 "expected same type of move for high parts");
1656 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1657 } else {
1658 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1659 }
1660 return size;
1661 }
1662
1663 // Check for float reg-reg copy.
1664 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1665 if (cbuf) {
1666 MacroAssembler _masm(cbuf);
1667 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1668 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1669 __ fmr(Rdst, Rsrc);
1670 }
1671 #ifndef PRODUCT
1672 else if (!do_size) {
1673 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1674 }
1675 #endif
1676 return 4;
1677 }
1678
1679 // Check for float store.
1680 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1681 int dst_offset = ra_->reg2offset(dst_lo);
1682 if (src_hi != OptoReg::Bad) {
1683 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1684 "expected same type of move for high parts");
1685 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1686 } else {
1687 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1688 }
1689 return size;
1690 }
1691
1692 // Check for float load.
1693 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1694 int src_offset = ra_->reg2offset(src_lo);
1695 if (src_hi != OptoReg::Bad) {
1696 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1697 "expected same type of move for high parts");
1698 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1699 } else {
1700 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1701 }
1702 return size;
1703 }
1704
1705 // --------------------------------------------------------------------
1706 // Check for hi bits still needing moving. Only happens for misaligned
1707 // arguments to native calls.
1708 if (src_hi == dst_hi)
1709 return size; // Self copy; no move.
1710
1711 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1712 ShouldNotReachHere(); // Unimplemented
1713 return 0;
1714 }
1715
1716 #ifndef PRODUCT
1717 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1718 if (!ra_)
1719 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1720 else
1721 implementation(NULL, ra_, false, st);
1722 }
1723 #endif
1724
1725 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1726 implementation(&cbuf, ra_, false, NULL);
1727 }
1728
1729 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1730 return implementation(NULL, ra_, true, NULL);
1731 }
1732
1733 #if 0 // TODO: PPC port
1734 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1735 #ifndef PRODUCT
1736 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1737 #endif
1738 assert(ra_->node_regs_max_index() != 0, "");
1739
1740 // Get registers to move.
1741 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1742 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1743 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1744 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1745
1746 enum RC src_lo_rc = rc_class(src_lo);
1747 enum RC dst_lo_rc = rc_class(dst_lo);
1748
1749 if (src_lo == dst_lo && src_hi == dst_hi)
1750 return ppc64Opcode_none; // Self copy, no move.
1751
1752 // --------------------------------------
1753 // Memory->Memory Spill. Use R0 to hold the value.
1754 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1755 return ppc64Opcode_compound;
1756 }
1757
1758 // --------------------------------------
1759 // Check for float->int copy; requires a trip through memory.
1760 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1761 Unimplemented();
1762 }
1763
1764 // --------------------------------------
1765 // Check for integer reg-reg copy.
1766 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1767 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1768 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1769 if (Rsrc == Rdst) {
1770 return ppc64Opcode_none;
1771 } else {
1772 return ppc64Opcode_or;
1773 }
1774 }
1775
1776 // Check for integer store.
1777 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1778 if (src_hi != OptoReg::Bad) {
1779 return ppc64Opcode_std;
1780 } else {
1781 return ppc64Opcode_stw;
1782 }
1783 }
1784
1785 // Check for integer load.
1786 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1787 if (src_hi != OptoReg::Bad) {
1788 return ppc64Opcode_ld;
1789 } else {
1790 return ppc64Opcode_lwz;
1791 }
1792 }
1793
1794 // Check for float reg-reg copy.
1795 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1796 return ppc64Opcode_fmr;
1797 }
1798
1799 // Check for float store.
1800 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1801 if (src_hi != OptoReg::Bad) {
1802 return ppc64Opcode_stfd;
1803 } else {
1804 return ppc64Opcode_stfs;
1805 }
1806 }
1807
1808 // Check for float load.
1809 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1810 if (src_hi != OptoReg::Bad) {
1811 return ppc64Opcode_lfd;
1812 } else {
1813 return ppc64Opcode_lfs;
1814 }
1815 }
1816
1817 // --------------------------------------------------------------------
1818 // Check for hi bits still needing moving. Only happens for misaligned
1819 // arguments to native calls.
1820 if (src_hi == dst_hi) {
1821 return ppc64Opcode_none; // Self copy; no move.
1822 }
1823
1824 ShouldNotReachHere();
1825 return ppc64Opcode_undefined;
1826 }
1827 #endif // PPC port
1828
1829 #ifndef PRODUCT
1830 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1831 st->print("NOP \t// %d nops to pad for loops.", _count);
1832 }
1833 #endif
1834
1835 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1836 MacroAssembler _masm(&cbuf);
1837 // _count contains the number of nops needed for padding.
1838 for (int i = 0; i < _count; i++) {
1839 __ nop();
1840 }
1841 }
1842
1843 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1844 return _count * 4;
1845 }
1846
1847 #ifndef PRODUCT
1848 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1849 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1850 char reg_str[128];
1851 ra_->dump_register(this, reg_str);
1852 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1853 }
1854 #endif
1855
1856 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1857 MacroAssembler _masm(&cbuf);
1858
1859 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1860 int reg = ra_->get_encode(this);
1861
1862 if (Assembler::is_simm(offset, 16)) {
1863 __ addi(as_Register(reg), R1, offset);
1864 } else {
1865 ShouldNotReachHere();
1866 }
1867 }
1868
1869 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1870 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1871 return 4;
1872 }
1873
1874 #ifndef PRODUCT
1875 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1876 st->print_cr("---- MachUEPNode ----");
1877 st->print_cr("...");
1878 }
1879 #endif
1880
1881 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1882 // This is the unverified entry point.
1883 MacroAssembler _masm(&cbuf);
1884
1885 // Inline_cache contains a klass.
1886 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1887 Register receiver_klass = R12_scratch2; // tmp
1888
1889 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1890 assert(R11_scratch1 == R11, "need prologue scratch register");
1891
1892 // Check for NULL argument if we don't have implicit null checks.
1893 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1894 if (TrapBasedNullChecks) {
1895 __ trap_null_check(R3_ARG1);
1896 } else {
1897 Label valid;
1898 __ cmpdi(CCR0, R3_ARG1, 0);
1899 __ bne_predict_taken(CCR0, valid);
1900 // We have a null argument, branch to ic_miss_stub.
1901 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1902 relocInfo::runtime_call_type);
1903 __ bind(valid);
1904 }
1905 }
1906 // Assume argument is not NULL, load klass from receiver.
1907 __ load_klass(receiver_klass, R3_ARG1);
1908
1909 if (TrapBasedICMissChecks) {
1910 __ trap_ic_miss_check(receiver_klass, ic_klass);
1911 } else {
1912 Label valid;
1913 __ cmpd(CCR0, receiver_klass, ic_klass);
1914 __ beq_predict_taken(CCR0, valid);
1915 // We have an unexpected klass, branch to ic_miss_stub.
1916 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1917 relocInfo::runtime_call_type);
1918 __ bind(valid);
1919 }
1920
1921 // Argument is valid and klass is as expected, continue.
1922 }
1923
1924 #if 0 // TODO: PPC port
1925 // Optimize UEP code on z (save a load_const() call in main path).
1926 int MachUEPNode::ep_offset() {
1927 return 0;
1928 }
1929 #endif
1930
1931 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1932 // Variable size. Determine dynamically.
1933 return MachNode::size(ra_);
1934 }
1935
1936 //=============================================================================
1937
1938 %} // interrupt source
1939
1940 source_hpp %{ // Header information of the source block.
1941
1942 class HandlerImpl {
1943
1944 public:
1945
1946 static int emit_exception_handler(CodeBuffer &cbuf);
1947 static int emit_deopt_handler(CodeBuffer& cbuf);
1948
1949 static uint size_exception_handler() {
1950 // The exception_handler is a b64_patchable.
1951 return MacroAssembler::b64_patchable_size;
1952 }
1953
1954 static uint size_deopt_handler() {
1955 // The deopt_handler is a bl64_patchable.
1956 return MacroAssembler::bl64_patchable_size;
1957 }
1958
1959 };
1960
1961 %} // end source_hpp
1962
1963 source %{
1964
1965 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1966 MacroAssembler _masm(&cbuf);
1967
1968 address base = __ start_a_stub(size_exception_handler());
1969 if (base == NULL) return 0; // CodeBuffer::expand failed
1970
1971 int offset = __ offset();
1972 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
1973 relocInfo::runtime_call_type);
1974 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
1975 __ end_a_stub();
1976
1977 return offset;
1978 }
1979
1980 // The deopt_handler is like the exception handler, but it calls to
1981 // the deoptimization blob instead of jumping to the exception blob.
1982 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1983 MacroAssembler _masm(&cbuf);
1984
1985 address base = __ start_a_stub(size_deopt_handler());
1986 if (base == NULL) return 0; // CodeBuffer::expand failed
1987
1988 int offset = __ offset();
1989 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
1990 relocInfo::runtime_call_type);
1991 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1992 __ end_a_stub();
1993
1994 return offset;
1995 }
1996
1997 //=============================================================================
1998
1999 // Use a frame slots bias for frameless methods if accessing the stack.
2000 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2001 if (as_Register(reg_enc) == R1_SP) {
2002 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2003 }
2004 return 0;
2005 }
2006
2007 const bool Matcher::match_rule_supported(int opcode) {
2008 if (!has_match_rule(opcode))
2009 return false;
2010
2011 switch (opcode) {
2012 case Op_SqrtD:
2013 return VM_Version::has_fsqrt();
2014 case Op_CountLeadingZerosI:
2015 case Op_CountLeadingZerosL:
2016 case Op_CountTrailingZerosI:
2017 case Op_CountTrailingZerosL:
2018 if (!UseCountLeadingZerosInstructionsPPC64)
2019 return false;
2020 break;
2021
2022 case Op_PopCountI:
2023 case Op_PopCountL:
2024 return (UsePopCountInstruction && VM_Version::has_popcntw());
2025
2026 case Op_StrComp:
2027 return SpecialStringCompareTo;
2028 case Op_StrEquals:
2029 return SpecialStringEquals;
2030 case Op_StrIndexOf:
2031 return SpecialStringIndexOf;
2032 case Op_StrIndexOfChar:
2033 return SpecialStringIndexOf;
2034 }
2035
2036 return true; // Per default match rules are supported.
2037 }
2038
2039 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2040
2041 // TODO
2042 // identify extra cases that we might want to provide match rules for
2043 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2044 bool ret_value = match_rule_supported(opcode);
2045 // Add rules here.
2046
2047 return ret_value; // Per default match rules are supported.
2048 }
2049
2050 const bool Matcher::has_predicated_vectors(void) {
2051 return false;
2052 }
2053
2054 const int Matcher::float_pressure(int default_pressure_threshold) {
2055 return default_pressure_threshold;
2056 }
2057
2058 int Matcher::regnum_to_fpu_offset(int regnum) {
2059 // No user for this method?
2060 Unimplemented();
2061 return 999;
2062 }
2063
2064 const bool Matcher::convL2FSupported(void) {
2065 // fcfids can do the conversion (>= Power7).
2066 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2067 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2068 }
2069
2070 // Vector width in bytes.
2071 const int Matcher::vector_width_in_bytes(BasicType bt) {
2072 assert(MaxVectorSize == 8, "");
2073 return 8;
2074 }
2075
2076 // Vector ideal reg.
2077 const int Matcher::vector_ideal_reg(int size) {
2078 assert(MaxVectorSize == 8 && size == 8, "");
2079 return Op_RegL;
2080 }
2081
2082 const int Matcher::vector_shift_count_ideal_reg(int size) {
2083 fatal("vector shift is not supported");
2084 return Node::NotAMachineReg;
2085 }
2086
2087 // Limits on vector size (number of elements) loaded into vector.
2088 const int Matcher::max_vector_size(const BasicType bt) {
2089 assert(is_java_primitive(bt), "only primitive type vectors");
2090 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2091 }
2092
2093 const int Matcher::min_vector_size(const BasicType bt) {
2094 return max_vector_size(bt); // Same as max.
2095 }
2096
2097 // PPC doesn't support misaligned vectors store/load.
2098 const bool Matcher::misaligned_vectors_ok() {
2099 return false;
2100 }
2101
2102 // PPC AES support not yet implemented
2103 const bool Matcher::pass_original_key_for_aes() {
2104 return false;
2105 }
2106
2107 // RETURNS: whether this branch offset is short enough that a short
2108 // branch can be used.
2109 //
2110 // If the platform does not provide any short branch variants, then
2111 // this method should return `false' for offset 0.
2112 //
2113 // `Compile::Fill_buffer' will decide on basis of this information
2114 // whether to do the pass `Compile::Shorten_branches' at all.
2115 //
2116 // And `Compile::Shorten_branches' will decide on basis of this
2117 // information whether to replace particular branch sites by short
2118 // ones.
2119 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2120 // Is the offset within the range of a ppc64 pc relative branch?
2121 bool b;
2122
2123 const int safety_zone = 3 * BytesPerInstWord;
2124 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2125 29 - 16 + 1 + 2);
2126 return b;
2127 }
2128
2129 const bool Matcher::isSimpleConstant64(jlong value) {
2130 // Probably always true, even if a temp register is required.
2131 return true;
2132 }
2133 /* TODO: PPC port
2134 // Make a new machine dependent decode node (with its operands).
2135 MachTypeNode *Matcher::make_decode_node() {
2136 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2137 "This method is only implemented for unscaled cOops mode so far");
2138 MachTypeNode *decode = new decodeN_unscaledNode();
2139 decode->set_opnd_array(0, new iRegPdstOper());
2140 decode->set_opnd_array(1, new iRegNsrcOper());
2141 return decode;
2142 }
2143 */
2144
2145 // false => size gets scaled to BytesPerLong, ok.
2146 const bool Matcher::init_array_count_is_in_bytes = false;
2147
2148 // Use conditional move (CMOVL) on Power7.
2149 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2150
2151 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2152 // fsel doesn't accept a condition register as input, so this would be slightly different.
2153 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2154
2155 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2156 const bool Matcher::require_postalloc_expand = true;
2157
2158 // Should the Matcher clone shifts on addressing modes, expecting them to
2159 // be subsumed into complex addressing expressions or compute them into
2160 // registers? True for Intel but false for most RISCs.
2161 const bool Matcher::clone_shift_expressions = false;
2162
2163 // Do we need to mask the count passed to shift instructions or does
2164 // the cpu only look at the lower 5/6 bits anyway?
2165 // PowerPC requires masked shift counts.
2166 const bool Matcher::need_masked_shift_count = true;
2167
2168 // This affects two different things:
2169 // - how Decode nodes are matched
2170 // - how ImplicitNullCheck opportunities are recognized
2171 // If true, the matcher will try to remove all Decodes and match them
2172 // (as operands) into nodes. NullChecks are not prepared to deal with
2173 // Decodes by final_graph_reshaping().
2174 // If false, final_graph_reshaping() forces the decode behind the Cmp
2175 // for a NullCheck. The matcher matches the Decode node into a register.
2176 // Implicit_null_check optimization moves the Decode along with the
2177 // memory operation back up before the NullCheck.
2178 bool Matcher::narrow_oop_use_complex_address() {
2179 // TODO: PPC port if (MatchDecodeNodes) return true;
2180 return false;
2181 }
2182
2183 bool Matcher::narrow_klass_use_complex_address() {
2184 NOT_LP64(ShouldNotCallThis());
2185 assert(UseCompressedClassPointers, "only for compressed klass code");
2186 // TODO: PPC port if (MatchDecodeNodes) return true;
2187 return false;
2188 }
2189
2190 // Is it better to copy float constants, or load them directly from memory?
2191 // Intel can load a float constant from a direct address, requiring no
2192 // extra registers. Most RISCs will have to materialize an address into a
2193 // register first, so they would do better to copy the constant from stack.
2194 const bool Matcher::rematerialize_float_constants = false;
2195
2196 // If CPU can load and store mis-aligned doubles directly then no fixup is
2197 // needed. Else we split the double into 2 integer pieces and move it
2198 // piece-by-piece. Only happens when passing doubles into C code as the
2199 // Java calling convention forces doubles to be aligned.
2200 const bool Matcher::misaligned_doubles_ok = true;
2201
2202 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2203 Unimplemented();
2204 }
2205
2206 // Advertise here if the CPU requires explicit rounding operations
2207 // to implement the UseStrictFP mode.
2208 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2209
2210 // Do floats take an entire double register or just half?
2211 //
2212 // A float occupies a ppc64 double register. For the allocator, a
2213 // ppc64 double register appears as a pair of float registers.
2214 bool Matcher::float_in_double() { return true; }
2215
2216 // Do ints take an entire long register or just half?
2217 // The relevant question is how the int is callee-saved:
2218 // the whole long is written but de-opt'ing will have to extract
2219 // the relevant 32 bits.
2220 const bool Matcher::int_in_long = true;
2221
2222 // Constants for c2c and c calling conventions.
2223
2224 const MachRegisterNumbers iarg_reg[8] = {
2225 R3_num, R4_num, R5_num, R6_num,
2226 R7_num, R8_num, R9_num, R10_num
2227 };
2228
2229 const MachRegisterNumbers farg_reg[13] = {
2230 F1_num, F2_num, F3_num, F4_num,
2231 F5_num, F6_num, F7_num, F8_num,
2232 F9_num, F10_num, F11_num, F12_num,
2233 F13_num
2234 };
2235
2236 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2237
2238 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2239
2240 // Return whether or not this register is ever used as an argument. This
2241 // function is used on startup to build the trampoline stubs in generateOptoStub.
2242 // Registers not mentioned will be killed by the VM call in the trampoline, and
2243 // arguments in those registers not be available to the callee.
2244 bool Matcher::can_be_java_arg(int reg) {
2245 // We return true for all registers contained in iarg_reg[] and
2246 // farg_reg[] and their virtual halves.
2247 // We must include the virtual halves in order to get STDs and LDs
2248 // instead of STWs and LWs in the trampoline stubs.
2249
2250 if ( reg == R3_num || reg == R3_H_num
2251 || reg == R4_num || reg == R4_H_num
2252 || reg == R5_num || reg == R5_H_num
2253 || reg == R6_num || reg == R6_H_num
2254 || reg == R7_num || reg == R7_H_num
2255 || reg == R8_num || reg == R8_H_num
2256 || reg == R9_num || reg == R9_H_num
2257 || reg == R10_num || reg == R10_H_num)
2258 return true;
2259
2260 if ( reg == F1_num || reg == F1_H_num
2261 || reg == F2_num || reg == F2_H_num
2262 || reg == F3_num || reg == F3_H_num
2263 || reg == F4_num || reg == F4_H_num
2264 || reg == F5_num || reg == F5_H_num
2265 || reg == F6_num || reg == F6_H_num
2266 || reg == F7_num || reg == F7_H_num
2267 || reg == F8_num || reg == F8_H_num
2268 || reg == F9_num || reg == F9_H_num
2269 || reg == F10_num || reg == F10_H_num
2270 || reg == F11_num || reg == F11_H_num
2271 || reg == F12_num || reg == F12_H_num
2272 || reg == F13_num || reg == F13_H_num)
2273 return true;
2274
2275 return false;
2276 }
2277
2278 bool Matcher::is_spillable_arg(int reg) {
2279 return can_be_java_arg(reg);
2280 }
2281
2282 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2283 return false;
2284 }
2285
2286 // Register for DIVI projection of divmodI.
2287 RegMask Matcher::divI_proj_mask() {
2288 ShouldNotReachHere();
2289 return RegMask();
2290 }
2291
2292 // Register for MODI projection of divmodI.
2293 RegMask Matcher::modI_proj_mask() {
2294 ShouldNotReachHere();
2295 return RegMask();
2296 }
2297
2298 // Register for DIVL projection of divmodL.
2299 RegMask Matcher::divL_proj_mask() {
2300 ShouldNotReachHere();
2301 return RegMask();
2302 }
2303
2304 // Register for MODL projection of divmodL.
2305 RegMask Matcher::modL_proj_mask() {
2306 ShouldNotReachHere();
2307 return RegMask();
2308 }
2309
2310 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2311 return RegMask();
2312 }
2313
2314 %}
2315
2316 //----------ENCODING BLOCK-----------------------------------------------------
2317 // This block specifies the encoding classes used by the compiler to output
2318 // byte streams. Encoding classes are parameterized macros used by
2319 // Machine Instruction Nodes in order to generate the bit encoding of the
2320 // instruction. Operands specify their base encoding interface with the
2321 // interface keyword. There are currently supported four interfaces,
2322 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2323 // operand to generate a function which returns its register number when
2324 // queried. CONST_INTER causes an operand to generate a function which
2325 // returns the value of the constant when queried. MEMORY_INTER causes an
2326 // operand to generate four functions which return the Base Register, the
2327 // Index Register, the Scale Value, and the Offset Value of the operand when
2328 // queried. COND_INTER causes an operand to generate six functions which
2329 // return the encoding code (ie - encoding bits for the instruction)
2330 // associated with each basic boolean condition for a conditional instruction.
2331 //
2332 // Instructions specify two basic values for encoding. Again, a function
2333 // is available to check if the constant displacement is an oop. They use the
2334 // ins_encode keyword to specify their encoding classes (which must be
2335 // a sequence of enc_class names, and their parameters, specified in
2336 // the encoding block), and they use the
2337 // opcode keyword to specify, in order, their primary, secondary, and
2338 // tertiary opcode. Only the opcode sections which a particular instruction
2339 // needs for encoding need to be specified.
2340 encode %{
2341 enc_class enc_unimplemented %{
2342 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2343 MacroAssembler _masm(&cbuf);
2344 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2345 %}
2346
2347 enc_class enc_untested %{
2348 #ifdef ASSERT
2349 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2350 MacroAssembler _masm(&cbuf);
2351 __ untested("Untested mach node encoding in AD file.");
2352 #else
2353 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2354 #endif
2355 %}
2356
2357 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2358 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2359 MacroAssembler _masm(&cbuf);
2360 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2361 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2362 %}
2363
2364 // Load acquire.
2365 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2366 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2367 MacroAssembler _masm(&cbuf);
2368 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2369 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2370 __ twi_0($dst$$Register);
2371 __ isync();
2372 %}
2373
2374 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2375 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2376
2377 MacroAssembler _masm(&cbuf);
2378 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2379 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2380 %}
2381
2382 // Load acquire.
2383 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2384 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2385
2386 MacroAssembler _masm(&cbuf);
2387 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2388 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2389 __ twi_0($dst$$Register);
2390 __ isync();
2391 %}
2392
2393 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2394 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2395
2396 MacroAssembler _masm(&cbuf);
2397 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2398 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2399 %}
2400
2401 // Load acquire.
2402 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2403 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2404
2405 MacroAssembler _masm(&cbuf);
2406 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2407 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2408 __ twi_0($dst$$Register);
2409 __ isync();
2410 %}
2411
2412 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2413 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2414 MacroAssembler _masm(&cbuf);
2415 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2416 // Operand 'ds' requires 4-alignment.
2417 assert((Idisp & 0x3) == 0, "unaligned offset");
2418 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2419 %}
2420
2421 // Load acquire.
2422 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2423 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2424 MacroAssembler _masm(&cbuf);
2425 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2426 // Operand 'ds' requires 4-alignment.
2427 assert((Idisp & 0x3) == 0, "unaligned offset");
2428 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2429 __ twi_0($dst$$Register);
2430 __ isync();
2431 %}
2432
2433 enc_class enc_lfd(RegF dst, memory mem) %{
2434 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2435 MacroAssembler _masm(&cbuf);
2436 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2437 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2438 %}
2439
2440 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2441 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2442
2443 MacroAssembler _masm(&cbuf);
2444 int toc_offset = 0;
2445
2446 if (!ra_->C->in_scratch_emit_size()) {
2447 address const_toc_addr;
2448 // Create a non-oop constant, no relocation needed.
2449 // If it is an IC, it has a virtual_call_Relocation.
2450 const_toc_addr = __ long_constant((jlong)$src$$constant);
2451 if (const_toc_addr == NULL) {
2452 ciEnv::current()->record_out_of_memory_failure();
2453 return;
2454 }
2455
2456 // Get the constant's TOC offset.
2457 toc_offset = __ offset_to_method_toc(const_toc_addr);
2458
2459 // Keep the current instruction offset in mind.
2460 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2461 }
2462
2463 __ ld($dst$$Register, toc_offset, $toc$$Register);
2464 %}
2465
2466 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2467 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2468
2469 MacroAssembler _masm(&cbuf);
2470
2471 if (!ra_->C->in_scratch_emit_size()) {
2472 address const_toc_addr;
2473 // Create a non-oop constant, no relocation needed.
2474 // If it is an IC, it has a virtual_call_Relocation.
2475 const_toc_addr = __ long_constant((jlong)$src$$constant);
2476 if (const_toc_addr == NULL) {
2477 ciEnv::current()->record_out_of_memory_failure();
2478 return;
2479 }
2480
2481 // Get the constant's TOC offset.
2482 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2483 // Store the toc offset of the constant.
2484 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2485
2486 // Also keep the current instruction offset in mind.
2487 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2488 }
2489
2490 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2491 %}
2492
2493 %} // encode
2494
2495 source %{
2496
2497 typedef struct {
2498 loadConL_hiNode *_large_hi;
2499 loadConL_loNode *_large_lo;
2500 loadConLNode *_small;
2501 MachNode *_last;
2502 } loadConLNodesTuple;
2503
2504 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2505 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2506 loadConLNodesTuple nodes;
2507
2508 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2509 if (large_constant_pool) {
2510 // Create new nodes.
2511 loadConL_hiNode *m1 = new loadConL_hiNode();
2512 loadConL_loNode *m2 = new loadConL_loNode();
2513
2514 // inputs for new nodes
2515 m1->add_req(NULL, toc);
2516 m2->add_req(NULL, m1);
2517
2518 // operands for new nodes
2519 m1->_opnds[0] = new iRegLdstOper(); // dst
2520 m1->_opnds[1] = immSrc; // src
2521 m1->_opnds[2] = new iRegPdstOper(); // toc
2522 m2->_opnds[0] = new iRegLdstOper(); // dst
2523 m2->_opnds[1] = immSrc; // src
2524 m2->_opnds[2] = new iRegLdstOper(); // base
2525
2526 // Initialize ins_attrib TOC fields.
2527 m1->_const_toc_offset = -1;
2528 m2->_const_toc_offset_hi_node = m1;
2529
2530 // Initialize ins_attrib instruction offset.
2531 m1->_cbuf_insts_offset = -1;
2532
2533 // register allocation for new nodes
2534 ra_->set_pair(m1->_idx, reg_second, reg_first);
2535 ra_->set_pair(m2->_idx, reg_second, reg_first);
2536
2537 // Create result.
2538 nodes._large_hi = m1;
2539 nodes._large_lo = m2;
2540 nodes._small = NULL;
2541 nodes._last = nodes._large_lo;
2542 assert(m2->bottom_type()->isa_long(), "must be long");
2543 } else {
2544 loadConLNode *m2 = new loadConLNode();
2545
2546 // inputs for new nodes
2547 m2->add_req(NULL, toc);
2548
2549 // operands for new nodes
2550 m2->_opnds[0] = new iRegLdstOper(); // dst
2551 m2->_opnds[1] = immSrc; // src
2552 m2->_opnds[2] = new iRegPdstOper(); // toc
2553
2554 // Initialize ins_attrib instruction offset.
2555 m2->_cbuf_insts_offset = -1;
2556
2557 // register allocation for new nodes
2558 ra_->set_pair(m2->_idx, reg_second, reg_first);
2559
2560 // Create result.
2561 nodes._large_hi = NULL;
2562 nodes._large_lo = NULL;
2563 nodes._small = m2;
2564 nodes._last = nodes._small;
2565 assert(m2->bottom_type()->isa_long(), "must be long");
2566 }
2567
2568 return nodes;
2569 }
2570
2571 %} // source
2572
2573 encode %{
2574 // Postalloc expand emitter for loading a long constant from the method's TOC.
2575 // Enc_class needed as consttanttablebase is not supported by postalloc
2576 // expand.
2577 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2578 // Create new nodes.
2579 loadConLNodesTuple loadConLNodes =
2580 loadConLNodesTuple_create(ra_, n_toc, op_src,
2581 ra_->get_reg_second(this), ra_->get_reg_first(this));
2582
2583 // Push new nodes.
2584 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2585 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2586
2587 // some asserts
2588 assert(nodes->length() >= 1, "must have created at least 1 node");
2589 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2590 %}
2591
2592 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2593 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2594
2595 MacroAssembler _masm(&cbuf);
2596 int toc_offset = 0;
2597
2598 if (!ra_->C->in_scratch_emit_size()) {
2599 intptr_t val = $src$$constant;
2600 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2601 address const_toc_addr;
2602 if (constant_reloc == relocInfo::oop_type) {
2603 // Create an oop constant and a corresponding relocation.
2604 AddressLiteral a = __ allocate_oop_address((jobject)val);
2605 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2606 __ relocate(a.rspec());
2607 } else if (constant_reloc == relocInfo::metadata_type) {
2608 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2609 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2610 __ relocate(a.rspec());
2611 } else {
2612 // Create a non-oop constant, no relocation needed.
2613 const_toc_addr = __ long_constant((jlong)$src$$constant);
2614 }
2615
2616 if (const_toc_addr == NULL) {
2617 ciEnv::current()->record_out_of_memory_failure();
2618 return;
2619 }
2620 // Get the constant's TOC offset.
2621 toc_offset = __ offset_to_method_toc(const_toc_addr);
2622 }
2623
2624 __ ld($dst$$Register, toc_offset, $toc$$Register);
2625 %}
2626
2627 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2628 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2629
2630 MacroAssembler _masm(&cbuf);
2631 if (!ra_->C->in_scratch_emit_size()) {
2632 intptr_t val = $src$$constant;
2633 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2634 address const_toc_addr;
2635 if (constant_reloc == relocInfo::oop_type) {
2636 // Create an oop constant and a corresponding relocation.
2637 AddressLiteral a = __ allocate_oop_address((jobject)val);
2638 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2639 __ relocate(a.rspec());
2640 } else if (constant_reloc == relocInfo::metadata_type) {
2641 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2642 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2643 __ relocate(a.rspec());
2644 } else { // non-oop pointers, e.g. card mark base, heap top
2645 // Create a non-oop constant, no relocation needed.
2646 const_toc_addr = __ long_constant((jlong)$src$$constant);
2647 }
2648
2649 if (const_toc_addr == NULL) {
2650 ciEnv::current()->record_out_of_memory_failure();
2651 return;
2652 }
2653 // Get the constant's TOC offset.
2654 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2655 // Store the toc offset of the constant.
2656 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2657 }
2658
2659 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2660 %}
2661
2662 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2663 // Enc_class needed as consttanttablebase is not supported by postalloc
2664 // expand.
2665 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2666 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2667 if (large_constant_pool) {
2668 // Create new nodes.
2669 loadConP_hiNode *m1 = new loadConP_hiNode();
2670 loadConP_loNode *m2 = new loadConP_loNode();
2671
2672 // inputs for new nodes
2673 m1->add_req(NULL, n_toc);
2674 m2->add_req(NULL, m1);
2675
2676 // operands for new nodes
2677 m1->_opnds[0] = new iRegPdstOper(); // dst
2678 m1->_opnds[1] = op_src; // src
2679 m1->_opnds[2] = new iRegPdstOper(); // toc
2680 m2->_opnds[0] = new iRegPdstOper(); // dst
2681 m2->_opnds[1] = op_src; // src
2682 m2->_opnds[2] = new iRegLdstOper(); // base
2683
2684 // Initialize ins_attrib TOC fields.
2685 m1->_const_toc_offset = -1;
2686 m2->_const_toc_offset_hi_node = m1;
2687
2688 // Register allocation for new nodes.
2689 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2690 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2691
2692 nodes->push(m1);
2693 nodes->push(m2);
2694 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2695 } else {
2696 loadConPNode *m2 = new loadConPNode();
2697
2698 // inputs for new nodes
2699 m2->add_req(NULL, n_toc);
2700
2701 // operands for new nodes
2702 m2->_opnds[0] = new iRegPdstOper(); // dst
2703 m2->_opnds[1] = op_src; // src
2704 m2->_opnds[2] = new iRegPdstOper(); // toc
2705
2706 // Register allocation for new nodes.
2707 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2708
2709 nodes->push(m2);
2710 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2711 }
2712 %}
2713
2714 // Enc_class needed as consttanttablebase is not supported by postalloc
2715 // expand.
2716 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2717 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2718
2719 MachNode *m2;
2720 if (large_constant_pool) {
2721 m2 = new loadConFCompNode();
2722 } else {
2723 m2 = new loadConFNode();
2724 }
2725 // inputs for new nodes
2726 m2->add_req(NULL, n_toc);
2727
2728 // operands for new nodes
2729 m2->_opnds[0] = op_dst;
2730 m2->_opnds[1] = op_src;
2731 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2732
2733 // register allocation for new nodes
2734 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2735 nodes->push(m2);
2736 %}
2737
2738 // Enc_class needed as consttanttablebase is not supported by postalloc
2739 // expand.
2740 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2741 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2742
2743 MachNode *m2;
2744 if (large_constant_pool) {
2745 m2 = new loadConDCompNode();
2746 } else {
2747 m2 = new loadConDNode();
2748 }
2749 // inputs for new nodes
2750 m2->add_req(NULL, n_toc);
2751
2752 // operands for new nodes
2753 m2->_opnds[0] = op_dst;
2754 m2->_opnds[1] = op_src;
2755 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2756
2757 // register allocation for new nodes
2758 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2759 nodes->push(m2);
2760 %}
2761
2762 enc_class enc_stw(iRegIsrc src, memory mem) %{
2763 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2764 MacroAssembler _masm(&cbuf);
2765 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2766 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2767 %}
2768
2769 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2770 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2771 MacroAssembler _masm(&cbuf);
2772 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2773 // Operand 'ds' requires 4-alignment.
2774 assert((Idisp & 0x3) == 0, "unaligned offset");
2775 __ std($src$$Register, Idisp, $mem$$base$$Register);
2776 %}
2777
2778 enc_class enc_stfs(RegF src, memory mem) %{
2779 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2780 MacroAssembler _masm(&cbuf);
2781 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2782 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2783 %}
2784
2785 enc_class enc_stfd(RegF src, memory mem) %{
2786 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2787 MacroAssembler _masm(&cbuf);
2788 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2789 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2790 %}
2791
2792 // Use release_store for card-marking to ensure that previous
2793 // oop-stores are visible before the card-mark change.
2794 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2795 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2796 // FIXME: Implement this as a cmove and use a fixed condition code
2797 // register which is written on every transition to compiled code,
2798 // e.g. in call-stub and when returning from runtime stubs.
2799 //
2800 // Proposed code sequence for the cmove implementation:
2801 //
2802 // Label skip_release;
2803 // __ beq(CCRfixed, skip_release);
2804 // __ release();
2805 // __ bind(skip_release);
2806 // __ stb(card mark);
2807
2808 MacroAssembler _masm(&cbuf);
2809 Label skip_storestore;
2810
2811 #if 0 // TODO: PPC port
2812 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2813 // StoreStore barrier conditionally.
2814 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2815 __ cmpwi($crx$$CondRegister, R0, 0);
2816 __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2817 #endif
2818 __ li(R0, 0);
2819 __ membar(Assembler::StoreStore);
2820 #if 0 // TODO: PPC port
2821 __ bind(skip_storestore);
2822 #endif
2823
2824 // Do the store.
2825 if ($mem$$index == 0) {
2826 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2827 } else {
2828 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2829 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2830 }
2831 %}
2832
2833 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2834
2835 if (VM_Version::has_isel()) {
2836 // use isel instruction with Power 7
2837 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2838 encodeP_subNode *n_sub_base = new encodeP_subNode();
2839 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2840 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2841
2842 n_compare->add_req(n_region, n_src);
2843 n_compare->_opnds[0] = op_crx;
2844 n_compare->_opnds[1] = op_src;
2845 n_compare->_opnds[2] = new immL16Oper(0);
2846
2847 n_sub_base->add_req(n_region, n_src);
2848 n_sub_base->_opnds[0] = op_dst;
2849 n_sub_base->_opnds[1] = op_src;
2850 n_sub_base->_bottom_type = _bottom_type;
2851
2852 n_shift->add_req(n_region, n_sub_base);
2853 n_shift->_opnds[0] = op_dst;
2854 n_shift->_opnds[1] = op_dst;
2855 n_shift->_bottom_type = _bottom_type;
2856
2857 n_cond_set->add_req(n_region, n_compare, n_shift);
2858 n_cond_set->_opnds[0] = op_dst;
2859 n_cond_set->_opnds[1] = op_crx;
2860 n_cond_set->_opnds[2] = op_dst;
2861 n_cond_set->_bottom_type = _bottom_type;
2862
2863 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2864 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2865 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2866 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2867
2868 nodes->push(n_compare);
2869 nodes->push(n_sub_base);
2870 nodes->push(n_shift);
2871 nodes->push(n_cond_set);
2872
2873 } else {
2874 // before Power 7
2875 moveRegNode *n_move = new moveRegNode();
2876 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2877 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2878 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2879
2880 n_move->add_req(n_region, n_src);
2881 n_move->_opnds[0] = op_dst;
2882 n_move->_opnds[1] = op_src;
2883 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2884
2885 n_compare->add_req(n_region, n_src);
2886 n_compare->add_prec(n_move);
2887
2888 n_compare->_opnds[0] = op_crx;
2889 n_compare->_opnds[1] = op_src;
2890 n_compare->_opnds[2] = new immL16Oper(0);
2891
2892 n_sub_base->add_req(n_region, n_compare, n_src);
2893 n_sub_base->_opnds[0] = op_dst;
2894 n_sub_base->_opnds[1] = op_crx;
2895 n_sub_base->_opnds[2] = op_src;
2896 n_sub_base->_bottom_type = _bottom_type;
2897
2898 n_shift->add_req(n_region, n_sub_base);
2899 n_shift->_opnds[0] = op_dst;
2900 n_shift->_opnds[1] = op_dst;
2901 n_shift->_bottom_type = _bottom_type;
2902
2903 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2904 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2905 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2906 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2907
2908 nodes->push(n_move);
2909 nodes->push(n_compare);
2910 nodes->push(n_sub_base);
2911 nodes->push(n_shift);
2912 }
2913
2914 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2915 %}
2916
2917 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2918
2919 encodeP_subNode *n1 = new encodeP_subNode();
2920 n1->add_req(n_region, n_src);
2921 n1->_opnds[0] = op_dst;
2922 n1->_opnds[1] = op_src;
2923 n1->_bottom_type = _bottom_type;
2924
2925 encodeP_shiftNode *n2 = new encodeP_shiftNode();
2926 n2->add_req(n_region, n1);
2927 n2->_opnds[0] = op_dst;
2928 n2->_opnds[1] = op_dst;
2929 n2->_bottom_type = _bottom_type;
2930 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2931 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2932
2933 nodes->push(n1);
2934 nodes->push(n2);
2935 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2936 %}
2937
2938 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2939 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
2940 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
2941
2942 n_compare->add_req(n_region, n_src);
2943 n_compare->_opnds[0] = op_crx;
2944 n_compare->_opnds[1] = op_src;
2945 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2946
2947 n_shift->add_req(n_region, n_src);
2948 n_shift->_opnds[0] = op_dst;
2949 n_shift->_opnds[1] = op_src;
2950 n_shift->_bottom_type = _bottom_type;
2951
2952 if (VM_Version::has_isel()) {
2953 // use isel instruction with Power 7
2954
2955 decodeN_addNode *n_add_base = new decodeN_addNode();
2956 n_add_base->add_req(n_region, n_shift);
2957 n_add_base->_opnds[0] = op_dst;
2958 n_add_base->_opnds[1] = op_dst;
2959 n_add_base->_bottom_type = _bottom_type;
2960
2961 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2962 n_cond_set->add_req(n_region, n_compare, n_add_base);
2963 n_cond_set->_opnds[0] = op_dst;
2964 n_cond_set->_opnds[1] = op_crx;
2965 n_cond_set->_opnds[2] = op_dst;
2966 n_cond_set->_bottom_type = _bottom_type;
2967
2968 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2969 ra_->set_oop(n_cond_set, true);
2970
2971 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2972 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2973 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2974 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2975
2976 nodes->push(n_compare);
2977 nodes->push(n_shift);
2978 nodes->push(n_add_base);
2979 nodes->push(n_cond_set);
2980
2981 } else {
2982 // before Power 7
2983 cond_add_baseNode *n_add_base = new cond_add_baseNode();
2984
2985 n_add_base->add_req(n_region, n_compare, n_shift);
2986 n_add_base->_opnds[0] = op_dst;
2987 n_add_base->_opnds[1] = op_crx;
2988 n_add_base->_opnds[2] = op_dst;
2989 n_add_base->_bottom_type = _bottom_type;
2990
2991 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2992 ra_->set_oop(n_add_base, true);
2993
2994 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2995 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2996 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2997
2998 nodes->push(n_compare);
2999 nodes->push(n_shift);
3000 nodes->push(n_add_base);
3001 }
3002 %}
3003
3004 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3005 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3006 n1->add_req(n_region, n_src);
3007 n1->_opnds[0] = op_dst;
3008 n1->_opnds[1] = op_src;
3009 n1->_bottom_type = _bottom_type;
3010
3011 decodeN_addNode *n2 = new decodeN_addNode();
3012 n2->add_req(n_region, n1);
3013 n2->_opnds[0] = op_dst;
3014 n2->_opnds[1] = op_dst;
3015 n2->_bottom_type = _bottom_type;
3016 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3018
3019 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3020 ra_->set_oop(n2, true);
3021
3022 nodes->push(n1);
3023 nodes->push(n2);
3024 %}
3025
3026 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3027 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3028
3029 MacroAssembler _masm(&cbuf);
3030 int cc = $cmp$$cmpcode;
3031 int flags_reg = $crx$$reg;
3032 Label done;
3033 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3034 // Branch if not (cmp crx).
3035 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3036 __ mr($dst$$Register, $src$$Register);
3037 // TODO PPC port __ endgroup_if_needed(_size == 12);
3038 __ bind(done);
3039 %}
3040
3041 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3042 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3043
3044 MacroAssembler _masm(&cbuf);
3045 Label done;
3046 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3047 // Branch if not (cmp crx).
3048 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3049 __ li($dst$$Register, $src$$constant);
3050 // TODO PPC port __ endgroup_if_needed(_size == 12);
3051 __ bind(done);
3052 %}
3053
3054 // New atomics.
3055 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3056 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3057
3058 MacroAssembler _masm(&cbuf);
3059 Register Rtmp = R0;
3060 Register Rres = $res$$Register;
3061 Register Rsrc = $src$$Register;
3062 Register Rptr = $mem_ptr$$Register;
3063 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3064 Register Rold = RegCollision ? Rtmp : Rres;
3065
3066 Label Lretry;
3067 __ bind(Lretry);
3068 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3069 __ add(Rtmp, Rsrc, Rold);
3070 __ stwcx_(Rtmp, Rptr);
3071 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3072 __ bne_predict_not_taken(CCR0, Lretry);
3073 } else {
3074 __ bne( CCR0, Lretry);
3075 }
3076 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3077 __ fence();
3078 %}
3079
3080 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3081 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3082
3083 MacroAssembler _masm(&cbuf);
3084 Register Rtmp = R0;
3085 Register Rres = $res$$Register;
3086 Register Rsrc = $src$$Register;
3087 Register Rptr = $mem_ptr$$Register;
3088 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3089 Register Rold = RegCollision ? Rtmp : Rres;
3090
3091 Label Lretry;
3092 __ bind(Lretry);
3093 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3094 __ add(Rtmp, Rsrc, Rold);
3095 __ stdcx_(Rtmp, Rptr);
3096 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3097 __ bne_predict_not_taken(CCR0, Lretry);
3098 } else {
3099 __ bne( CCR0, Lretry);
3100 }
3101 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3102 __ fence();
3103 %}
3104
3105 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3106 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3107
3108 MacroAssembler _masm(&cbuf);
3109 Register Rtmp = R0;
3110 Register Rres = $res$$Register;
3111 Register Rsrc = $src$$Register;
3112 Register Rptr = $mem_ptr$$Register;
3113 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3114 Register Rold = RegCollision ? Rtmp : Rres;
3115
3116 Label Lretry;
3117 __ bind(Lretry);
3118 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3119 __ stwcx_(Rsrc, Rptr);
3120 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3121 __ bne_predict_not_taken(CCR0, Lretry);
3122 } else {
3123 __ bne( CCR0, Lretry);
3124 }
3125 if (RegCollision) __ mr(Rres, Rtmp);
3126 __ fence();
3127 %}
3128
3129 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3130 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3131
3132 MacroAssembler _masm(&cbuf);
3133 Register Rtmp = R0;
3134 Register Rres = $res$$Register;
3135 Register Rsrc = $src$$Register;
3136 Register Rptr = $mem_ptr$$Register;
3137 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3138 Register Rold = RegCollision ? Rtmp : Rres;
3139
3140 Label Lretry;
3141 __ bind(Lretry);
3142 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3143 __ stdcx_(Rsrc, Rptr);
3144 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3145 __ bne_predict_not_taken(CCR0, Lretry);
3146 } else {
3147 __ bne( CCR0, Lretry);
3148 }
3149 if (RegCollision) __ mr(Rres, Rtmp);
3150 __ fence();
3151 %}
3152
3153 // This enc_class is needed so that scheduler gets proper
3154 // input mapping for latency computation.
3155 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3156 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3157 MacroAssembler _masm(&cbuf);
3158 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3159 %}
3160
3161 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3162 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3163
3164 MacroAssembler _masm(&cbuf);
3165
3166 Label done;
3167 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3168 __ li($dst$$Register, $zero$$constant);
3169 __ beq($crx$$CondRegister, done);
3170 __ li($dst$$Register, $notzero$$constant);
3171 __ bind(done);
3172 %}
3173
3174 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3175 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3176
3177 MacroAssembler _masm(&cbuf);
3178
3179 Label done;
3180 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3181 __ li($dst$$Register, $zero$$constant);
3182 __ beq($crx$$CondRegister, done);
3183 __ li($dst$$Register, $notzero$$constant);
3184 __ bind(done);
3185 %}
3186
3187 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3188 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3189
3190 MacroAssembler _masm(&cbuf);
3191 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3192 Label done;
3193 __ bso($crx$$CondRegister, done);
3194 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3195 // TODO PPC port __ endgroup_if_needed(_size == 12);
3196 __ bind(done);
3197 %}
3198
3199 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3200 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3201
3202 MacroAssembler _masm(&cbuf);
3203 Label d; // dummy
3204 __ bind(d);
3205 Label* p = ($lbl$$label);
3206 // `p' is `NULL' when this encoding class is used only to
3207 // determine the size of the encoded instruction.
3208 Label& l = (NULL == p)? d : *(p);
3209 int cc = $cmp$$cmpcode;
3210 int flags_reg = $crx$$reg;
3211 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3212 int bhint = Assembler::bhintNoHint;
3213
3214 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3215 if (_prob <= PROB_NEVER) {
3216 bhint = Assembler::bhintIsNotTaken;
3217 } else if (_prob >= PROB_ALWAYS) {
3218 bhint = Assembler::bhintIsTaken;
3219 }
3220 }
3221
3222 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3223 cc_to_biint(cc, flags_reg),
3224 l);
3225 %}
3226
3227 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3228 // The scheduler doesn't know about branch shortening, so we set the opcode
3229 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3230 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3231
3232 MacroAssembler _masm(&cbuf);
3233 Label d; // dummy
3234 __ bind(d);
3235 Label* p = ($lbl$$label);
3236 // `p' is `NULL' when this encoding class is used only to
3237 // determine the size of the encoded instruction.
3238 Label& l = (NULL == p)? d : *(p);
3239 int cc = $cmp$$cmpcode;
3240 int flags_reg = $crx$$reg;
3241 int bhint = Assembler::bhintNoHint;
3242
3243 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3244 if (_prob <= PROB_NEVER) {
3245 bhint = Assembler::bhintIsNotTaken;
3246 } else if (_prob >= PROB_ALWAYS) {
3247 bhint = Assembler::bhintIsTaken;
3248 }
3249 }
3250
3251 // Tell the conditional far branch to optimize itself when being relocated.
3252 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3253 cc_to_biint(cc, flags_reg),
3254 l,
3255 MacroAssembler::bc_far_optimize_on_relocate);
3256 %}
3257
3258 // Branch used with Power6 scheduling (can be shortened without changing the node).
3259 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3260 // The scheduler doesn't know about branch shortening, so we set the opcode
3261 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3262 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3263
3264 MacroAssembler _masm(&cbuf);
3265 Label d; // dummy
3266 __ bind(d);
3267 Label* p = ($lbl$$label);
3268 // `p' is `NULL' when this encoding class is used only to
3269 // determine the size of the encoded instruction.
3270 Label& l = (NULL == p)? d : *(p);
3271 int cc = $cmp$$cmpcode;
3272 int flags_reg = $crx$$reg;
3273 int bhint = Assembler::bhintNoHint;
3274
3275 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3276 if (_prob <= PROB_NEVER) {
3277 bhint = Assembler::bhintIsNotTaken;
3278 } else if (_prob >= PROB_ALWAYS) {
3279 bhint = Assembler::bhintIsTaken;
3280 }
3281 }
3282
3283 #if 0 // TODO: PPC port
3284 if (_size == 8) {
3285 // Tell the conditional far branch to optimize itself when being relocated.
3286 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3287 cc_to_biint(cc, flags_reg),
3288 l,
3289 MacroAssembler::bc_far_optimize_on_relocate);
3290 } else {
3291 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3292 cc_to_biint(cc, flags_reg),
3293 l);
3294 }
3295 #endif
3296 Unimplemented();
3297 %}
3298
3299 // Postalloc expand emitter for loading a replicatef float constant from
3300 // the method's TOC.
3301 // Enc_class needed as consttanttablebase is not supported by postalloc
3302 // expand.
3303 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3304 // Create new nodes.
3305
3306 // Make an operand with the bit pattern to load as float.
3307 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3308
3309 loadConLNodesTuple loadConLNodes =
3310 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3311 ra_->get_reg_second(this), ra_->get_reg_first(this));
3312
3313 // Push new nodes.
3314 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3315 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3316
3317 assert(nodes->length() >= 1, "must have created at least 1 node");
3318 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3319 %}
3320
3321 // This enc_class is needed so that scheduler gets proper
3322 // input mapping for latency computation.
3323 enc_class enc_poll(immI dst, iRegLdst poll) %{
3324 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3325 // Fake operand dst needed for PPC scheduler.
3326 assert($dst$$constant == 0x0, "dst must be 0x0");
3327
3328 MacroAssembler _masm(&cbuf);
3329 // Mark the code position where the load from the safepoint
3330 // polling page was emitted as relocInfo::poll_type.
3331 __ relocate(relocInfo::poll_type);
3332 __ load_from_polling_page($poll$$Register);
3333 %}
3334
3335 // A Java static call or a runtime call.
3336 //
3337 // Branch-and-link relative to a trampoline.
3338 // The trampoline loads the target address and does a long branch to there.
3339 // In case we call java, the trampoline branches to a interpreter_stub
3340 // which loads the inline cache and the real call target from the constant pool.
3341 //
3342 // This basically looks like this:
3343 //
3344 // >>>> consts -+ -+
3345 // | |- offset1
3346 // [call target1] | <-+
3347 // [IC cache] |- offset2
3348 // [call target2] <--+
3349 //
3350 // <<<< consts
3351 // >>>> insts
3352 //
3353 // bl offset16 -+ -+ ??? // How many bits available?
3354 // | |
3355 // <<<< insts | |
3356 // >>>> stubs | |
3357 // | |- trampoline_stub_Reloc
3358 // trampoline stub: | <-+
3359 // r2 = toc |
3360 // r2 = [r2 + offset1] | // Load call target1 from const section
3361 // mtctr r2 |
3362 // bctr |- static_stub_Reloc
3363 // comp_to_interp_stub: <---+
3364 // r1 = toc
3365 // ICreg = [r1 + IC_offset] // Load IC from const section
3366 // r1 = [r1 + offset2] // Load call target2 from const section
3367 // mtctr r1
3368 // bctr
3369 //
3370 // <<<< stubs
3371 //
3372 // The call instruction in the code either
3373 // - Branches directly to a compiled method if the offset is encodable in instruction.
3374 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3375 // - Branches to the compiled_to_interp stub if the target is interpreted.
3376 //
3377 // Further there are three relocations from the loads to the constants in
3378 // the constant section.
3379 //
3380 // Usage of r1 and r2 in the stubs allows to distinguish them.
3381 enc_class enc_java_static_call(method meth) %{
3382 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3383
3384 MacroAssembler _masm(&cbuf);
3385 address entry_point = (address)$meth$$method;
3386
3387 if (!_method) {
3388 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3389 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3390 } else {
3391 // Remember the offset not the address.
3392 const int start_offset = __ offset();
3393 // The trampoline stub.
3394 if (!Compile::current()->in_scratch_emit_size()) {
3395 // No entry point given, use the current pc.
3396 // Make sure branch fits into
3397 if (entry_point == 0) entry_point = __ pc();
3398
3399 // Put the entry point as a constant into the constant pool.
3400 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3401 if (entry_point_toc_addr == NULL) {
3402 ciEnv::current()->record_out_of_memory_failure();
3403 return;
3404 }
3405 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3406
3407
3408 // Emit the trampoline stub which will be related to the branch-and-link below.
3409 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3410 if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3411 int method_index = resolved_method_index(cbuf);
3412 __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3413 : static_call_Relocation::spec(method_index));
3414 }
3415
3416 // The real call.
3417 // Note: At this point we do not have the address of the trampoline
3418 // stub, and the entry point might be too far away for bl, so __ pc()
3419 // serves as dummy and the bl will be patched later.
3420 cbuf.set_insts_mark();
3421 __ bl(__ pc()); // Emits a relocation.
3422
3423 // The stub for call to interpreter.
3424 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3425 if (stub == NULL) {
3426 ciEnv::current()->record_failure("CodeCache is full");
3427 return;
3428 }
3429 }
3430 %}
3431
3432 // Second node of expanded dynamic call - the call.
3433 enc_class enc_java_dynamic_call_sched(method meth) %{
3434 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3435
3436 MacroAssembler _masm(&cbuf);
3437
3438 if (!ra_->C->in_scratch_emit_size()) {
3439 // Create a call trampoline stub for the given method.
3440 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3441 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3442 if (entry_point_const == NULL) {
3443 ciEnv::current()->record_out_of_memory_failure();
3444 return;
3445 }
3446 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3447 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3448 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3449
3450 // Build relocation at call site with ic position as data.
3451 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3452 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3453 "must have one, but can't have both");
3454 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3455 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3456 "must contain instruction offset");
3457 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3458 ? _load_ic_hi_node->_cbuf_insts_offset
3459 : _load_ic_node->_cbuf_insts_offset;
3460 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3461 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3462 "should be load from TOC");
3463 int method_index = resolved_method_index(cbuf);
3464 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
3465 }
3466
3467 // At this point I do not have the address of the trampoline stub,
3468 // and the entry point might be too far away for bl. Pc() serves
3469 // as dummy and bl will be patched later.
3470 __ bl((address) __ pc());
3471 %}
3472
3473 // postalloc expand emitter for virtual calls.
3474 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3475
3476 // Create the nodes for loading the IC from the TOC.
3477 loadConLNodesTuple loadConLNodes_IC =
3478 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3479 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3480
3481 // Create the call node.
3482 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3483 call->_method_handle_invoke = _method_handle_invoke;
3484 call->_vtable_index = _vtable_index;
3485 call->_method = _method;
3486 call->_bci = _bci;
3487 call->_optimized_virtual = _optimized_virtual;
3488 call->_tf = _tf;
3489 call->_entry_point = _entry_point;
3490 call->_cnt = _cnt;
3491 call->_argsize = _argsize;
3492 call->_oop_map = _oop_map;
3493 call->_jvms = _jvms;
3494 call->_jvmadj = _jvmadj;
3495 call->_in_rms = _in_rms;
3496 call->_nesting = _nesting;
3497 call->_override_symbolic_info = _override_symbolic_info;
3498
3499 // New call needs all inputs of old call.
3500 // Req...
3501 for (uint i = 0; i < req(); ++i) {
3502 // The expanded node does not need toc any more.
3503 // Add the inline cache constant here instead. This expresses the
3504 // register of the inline cache must be live at the call.
3505 // Else we would have to adapt JVMState by -1.
3506 if (i == mach_constant_base_node_input()) {
3507 call->add_req(loadConLNodes_IC._last);
3508 } else {
3509 call->add_req(in(i));
3510 }
3511 }
3512 // ...as well as prec
3513 for (uint i = req(); i < len(); ++i) {
3514 call->add_prec(in(i));
3515 }
3516
3517 // Remember nodes loading the inline cache into r19.
3518 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3519 call->_load_ic_node = loadConLNodes_IC._small;
3520
3521 // Operands for new nodes.
3522 call->_opnds[0] = _opnds[0];
3523 call->_opnds[1] = _opnds[1];
3524
3525 // Only the inline cache is associated with a register.
3526 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3527
3528 // Push new nodes.
3529 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3530 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3531 nodes->push(call);
3532 %}
3533
3534 // Compound version of call dynamic
3535 // Toc is only passed so that it can be used in ins_encode statement.
3536 // In the code we have to use $constanttablebase.
3537 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3538 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3539 MacroAssembler _masm(&cbuf);
3540 int start_offset = __ offset();
3541
3542 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3543 #if 0
3544 int vtable_index = this->_vtable_index;
3545 if (_vtable_index < 0) {
3546 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3547 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3548 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3549
3550 // Virtual call relocation will point to ic load.
3551 address virtual_call_meta_addr = __ pc();
3552 // Load a clear inline cache.
3553 AddressLiteral empty_ic((address) Universe::non_oop_word());
3554 bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true);
3555 if (!success) {
3556 ciEnv::current()->record_out_of_memory_failure();
3557 return;
3558 }
3559 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3560 // to determine who we intended to call.
3561 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3562 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3563 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3564 "Fix constant in ret_addr_offset()");
3565 } else {
3566 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3567 // Go thru the vtable. Get receiver klass. Receiver already
3568 // checked for non-null. If we'll go thru a C2I adapter, the
3569 // interpreter expects method in R19_method.
3570
3571 __ load_klass(R11_scratch1, R3);
3572
3573 int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes();
3574 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
3575 __ li(R19_method, v_off);
3576 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3577 // NOTE: for vtable dispatches, the vtable entry will never be
3578 // null. However it may very well end up in handle_wrong_method
3579 // if the method is abstract for the particular class.
3580 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3581 // Call target. Either compiled code or C2I adapter.
3582 __ mtctr(R11_scratch1);
3583 __ bctrl();
3584 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3585 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3586 }
3587 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3588 "Fix constant in ret_addr_offset()");
3589 }
3590 #endif
3591 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3592 %}
3593
3594 // a runtime call
3595 enc_class enc_java_to_runtime_call (method meth) %{
3596 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3597
3598 MacroAssembler _masm(&cbuf);
3599 const address start_pc = __ pc();
3600
3601 #if defined(ABI_ELFv2)
3602 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3603 __ call_c(entry, relocInfo::runtime_call_type);
3604 #else
3605 // The function we're going to call.
3606 FunctionDescriptor fdtemp;
3607 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3608
3609 Register Rtoc = R12_scratch2;
3610 // Calculate the method's TOC.
3611 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3612 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3613 // pool entries; call_c_using_toc will optimize the call.
3614 bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3615 if (!success) {
3616 ciEnv::current()->record_out_of_memory_failure();
3617 return;
3618 }
3619 #endif
3620
3621 // Check the ret_addr_offset.
3622 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3623 "Fix constant in ret_addr_offset()");
3624 %}
3625
3626 // Move to ctr for leaf call.
3627 // This enc_class is needed so that scheduler gets proper
3628 // input mapping for latency computation.
3629 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3630 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3631 MacroAssembler _masm(&cbuf);
3632 __ mtctr($src$$Register);
3633 %}
3634
3635 // Postalloc expand emitter for runtime leaf calls.
3636 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3637 loadConLNodesTuple loadConLNodes_Entry;
3638 #if defined(ABI_ELFv2)
3639 jlong entry_address = (jlong) this->entry_point();
3640 assert(entry_address, "need address here");
3641 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3642 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3643 #else
3644 // Get the struct that describes the function we are about to call.
3645 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3646 assert(fd, "need fd here");
3647 jlong entry_address = (jlong) fd->entry();
3648 // new nodes
3649 loadConLNodesTuple loadConLNodes_Env;
3650 loadConLNodesTuple loadConLNodes_Toc;
3651
3652 // Create nodes and operands for loading the entry point.
3653 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3654 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3655
3656
3657 // Create nodes and operands for loading the env pointer.
3658 if (fd->env() != NULL) {
3659 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3660 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3661 } else {
3662 loadConLNodes_Env._large_hi = NULL;
3663 loadConLNodes_Env._large_lo = NULL;
3664 loadConLNodes_Env._small = NULL;
3665 loadConLNodes_Env._last = new loadConL16Node();
3666 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3667 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3668 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3669 }
3670
3671 // Create nodes and operands for loading the Toc point.
3672 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3673 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3674 #endif // ABI_ELFv2
3675 // mtctr node
3676 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3677
3678 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3679 mtctr->add_req(0, loadConLNodes_Entry._last);
3680
3681 mtctr->_opnds[0] = new iRegLdstOper();
3682 mtctr->_opnds[1] = new iRegLdstOper();
3683
3684 // call node
3685 MachCallLeafNode *call = new CallLeafDirectNode();
3686
3687 call->_opnds[0] = _opnds[0];
3688 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3689
3690 // Make the new call node look like the old one.
3691 call->_name = _name;
3692 call->_tf = _tf;
3693 call->_entry_point = _entry_point;
3694 call->_cnt = _cnt;
3695 call->_argsize = _argsize;
3696 call->_oop_map = _oop_map;
3697 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3698 call->_jvms = NULL;
3699 call->_jvmadj = _jvmadj;
3700 call->_in_rms = _in_rms;
3701 call->_nesting = _nesting;
3702
3703
3704 // New call needs all inputs of old call.
3705 // Req...
3706 for (uint i = 0; i < req(); ++i) {
3707 if (i != mach_constant_base_node_input()) {
3708 call->add_req(in(i));
3709 }
3710 }
3711
3712 // These must be reqired edges, as the registers are live up to
3713 // the call. Else the constants are handled as kills.
3714 call->add_req(mtctr);
3715 #if !defined(ABI_ELFv2)
3716 call->add_req(loadConLNodes_Env._last);
3717 call->add_req(loadConLNodes_Toc._last);
3718 #endif
3719
3720 // ...as well as prec
3721 for (uint i = req(); i < len(); ++i) {
3722 call->add_prec(in(i));
3723 }
3724
3725 // registers
3726 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3727
3728 // Insert the new nodes.
3729 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3730 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3731 #if !defined(ABI_ELFv2)
3732 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3733 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3734 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3735 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3736 #endif
3737 nodes->push(mtctr);
3738 nodes->push(call);
3739 %}
3740 %}
3741
3742 //----------FRAME--------------------------------------------------------------
3743 // Definition of frame structure and management information.
3744
3745 frame %{
3746 // What direction does stack grow in (assumed to be same for native & Java).
3747 stack_direction(TOWARDS_LOW);
3748
3749 // These two registers define part of the calling convention between
3750 // compiled code and the interpreter.
3751
3752 // Inline Cache Register or method for I2C.
3753 inline_cache_reg(R19); // R19_method
3754
3755 // Method Oop Register when calling interpreter.
3756 interpreter_method_oop_reg(R19); // R19_method
3757
3758 // Optional: name the operand used by cisc-spilling to access
3759 // [stack_pointer + offset].
3760 cisc_spilling_operand_name(indOffset);
3761
3762 // Number of stack slots consumed by a Monitor enter.
3763 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3764
3765 // Compiled code's Frame Pointer.
3766 frame_pointer(R1); // R1_SP
3767
3768 // Interpreter stores its frame pointer in a register which is
3769 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3770 // interpreted java to compiled java.
3771 //
3772 // R14_state holds pointer to caller's cInterpreter.
3773 interpreter_frame_pointer(R14); // R14_state
3774
3775 stack_alignment(frame::alignment_in_bytes);
3776
3777 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3778
3779 // Number of outgoing stack slots killed above the
3780 // out_preserve_stack_slots for calls to C. Supports the var-args
3781 // backing area for register parms.
3782 //
3783 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3784
3785 // The after-PROLOG location of the return address. Location of
3786 // return address specifies a type (REG or STACK) and a number
3787 // representing the register number (i.e. - use a register name) or
3788 // stack slot.
3789 //
3790 // A: Link register is stored in stack slot ...
3791 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3792 // J: Therefore, we make sure that the link register is also in R11_scratch1
3793 // at the end of the prolog.
3794 // B: We use R20, now.
3795 //return_addr(REG R20);
3796
3797 // G: After reading the comments made by all the luminaries on their
3798 // failure to tell the compiler where the return address really is,
3799 // I hardly dare to try myself. However, I'm convinced it's in slot
3800 // 4 what apparently works and saves us some spills.
3801 return_addr(STACK 4);
3802
3803 // This is the body of the function
3804 //
3805 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3806 // uint length, // length of array
3807 // bool is_outgoing)
3808 //
3809 // The `sig' array is to be updated. sig[j] represents the location
3810 // of the j-th argument, either a register or a stack slot.
3811
3812 // Comment taken from i486.ad:
3813 // Body of function which returns an integer array locating
3814 // arguments either in registers or in stack slots. Passed an array
3815 // of ideal registers called "sig" and a "length" count. Stack-slot
3816 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3817 // arguments for a CALLEE. Incoming stack arguments are
3818 // automatically biased by the preserve_stack_slots field above.
3819 calling_convention %{
3820 // No difference between ingoing/outgoing. Just pass false.
3821 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3822 %}
3823
3824 // Comment taken from i486.ad:
3825 // Body of function which returns an integer array locating
3826 // arguments either in registers or in stack slots. Passed an array
3827 // of ideal registers called "sig" and a "length" count. Stack-slot
3828 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3829 // arguments for a CALLEE. Incoming stack arguments are
3830 // automatically biased by the preserve_stack_slots field above.
3831 c_calling_convention %{
3832 // This is obviously always outgoing.
3833 // C argument in register AND stack slot.
3834 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3835 %}
3836
3837 // Location of native (C/C++) and interpreter return values. This
3838 // is specified to be the same as Java. In the 32-bit VM, long
3839 // values are actually returned from native calls in O0:O1 and
3840 // returned to the interpreter in I0:I1. The copying to and from
3841 // the register pairs is done by the appropriate call and epilog
3842 // opcodes. This simplifies the register allocator.
3843 c_return_value %{
3844 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3845 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3846 "only return normal values");
3847 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3848 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3849 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3850 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3851 %}
3852
3853 // Location of compiled Java return values. Same as C
3854 return_value %{
3855 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3856 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3857 "only return normal values");
3858 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3859 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3860 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3861 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3862 %}
3863 %}
3864
3865
3866 //----------ATTRIBUTES---------------------------------------------------------
3867
3868 //----------Operand Attributes-------------------------------------------------
3869 op_attrib op_cost(1); // Required cost attribute.
3870
3871 //----------Instruction Attributes---------------------------------------------
3872
3873 // Cost attribute. required.
3874 ins_attrib ins_cost(DEFAULT_COST);
3875
3876 // Is this instruction a non-matching short branch variant of some
3877 // long branch? Not required.
3878 ins_attrib ins_short_branch(0);
3879
3880 ins_attrib ins_is_TrapBasedCheckNode(true);
3881
3882 // Number of constants.
3883 // This instruction uses the given number of constants
3884 // (optional attribute).
3885 // This is needed to determine in time whether the constant pool will
3886 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3887 // is determined. It's also used to compute the constant pool size
3888 // in Output().
3889 ins_attrib ins_num_consts(0);
3890
3891 // Required alignment attribute (must be a power of 2) specifies the
3892 // alignment that some part of the instruction (not necessarily the
3893 // start) requires. If > 1, a compute_padding() function must be
3894 // provided for the instruction.
3895 ins_attrib ins_alignment(1);
3896
3897 // Enforce/prohibit rematerializations.
3898 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3899 // then rematerialization of that instruction is prohibited and the
3900 // instruction's value will be spilled if necessary.
3901 // Causes that MachNode::rematerialize() returns false.
3902 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3903 // then rematerialization should be enforced and a copy of the instruction
3904 // should be inserted if possible; rematerialization is not guaranteed.
3905 // Note: this may result in rematerializations in front of every use.
3906 // Causes that MachNode::rematerialize() can return true.
3907 // (optional attribute)
3908 ins_attrib ins_cannot_rematerialize(false);
3909 ins_attrib ins_should_rematerialize(false);
3910
3911 // Instruction has variable size depending on alignment.
3912 ins_attrib ins_variable_size_depending_on_alignment(false);
3913
3914 // Instruction is a nop.
3915 ins_attrib ins_is_nop(false);
3916
3917 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3918 ins_attrib ins_use_mach_if_fast_lock_node(false);
3919
3920 // Field for the toc offset of a constant.
3921 //
3922 // This is needed if the toc offset is not encodable as an immediate in
3923 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3924 // added to the toc, and from this a load with immediate is performed.
3925 // With postalloc expand, we get two nodes that require the same offset
3926 // but which don't know about each other. The offset is only known
3927 // when the constant is added to the constant pool during emitting.
3928 // It is generated in the 'hi'-node adding the upper bits, and saved
3929 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3930 // the offset from there when it gets encoded.
3931 ins_attrib ins_field_const_toc_offset(0);
3932 ins_attrib ins_field_const_toc_offset_hi_node(0);
3933
3934 // A field that can hold the instructions offset in the code buffer.
3935 // Set in the nodes emitter.
3936 ins_attrib ins_field_cbuf_insts_offset(-1);
3937
3938 // Fields for referencing a call's load-IC-node.
3939 // If the toc offset can not be encoded as an immediate in a load, we
3940 // use two nodes.
3941 ins_attrib ins_field_load_ic_hi_node(0);
3942 ins_attrib ins_field_load_ic_node(0);
3943
3944 //----------OPERANDS-----------------------------------------------------------
3945 // Operand definitions must precede instruction definitions for correct
3946 // parsing in the ADLC because operands constitute user defined types
3947 // which are used in instruction definitions.
3948 //
3949 // Formats are generated automatically for constants and base registers.
3950
3951 //----------Simple Operands----------------------------------------------------
3952 // Immediate Operands
3953
3954 // Integer Immediate: 32-bit
3955 operand immI() %{
3956 match(ConI);
3957 op_cost(40);
3958 format %{ %}
3959 interface(CONST_INTER);
3960 %}
3961
3962 operand immI8() %{
3963 predicate(Assembler::is_simm(n->get_int(), 8));
3964 op_cost(0);
3965 match(ConI);
3966 format %{ %}
3967 interface(CONST_INTER);
3968 %}
3969
3970 // Integer Immediate: 16-bit
3971 operand immI16() %{
3972 predicate(Assembler::is_simm(n->get_int(), 16));
3973 op_cost(0);
3974 match(ConI);
3975 format %{ %}
3976 interface(CONST_INTER);
3977 %}
3978
3979 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
3980 operand immIhi16() %{
3981 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
3982 match(ConI);
3983 op_cost(0);
3984 format %{ %}
3985 interface(CONST_INTER);
3986 %}
3987
3988 operand immInegpow2() %{
3989 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
3990 match(ConI);
3991 op_cost(0);
3992 format %{ %}
3993 interface(CONST_INTER);
3994 %}
3995
3996 operand immIpow2minus1() %{
3997 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
3998 match(ConI);
3999 op_cost(0);
4000 format %{ %}
4001 interface(CONST_INTER);
4002 %}
4003
4004 operand immIpowerOf2() %{
4005 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4006 match(ConI);
4007 op_cost(0);
4008 format %{ %}
4009 interface(CONST_INTER);
4010 %}
4011
4012 // Unsigned Integer Immediate: the values 0-31
4013 operand uimmI5() %{
4014 predicate(Assembler::is_uimm(n->get_int(), 5));
4015 match(ConI);
4016 op_cost(0);
4017 format %{ %}
4018 interface(CONST_INTER);
4019 %}
4020
4021 // Unsigned Integer Immediate: 6-bit
4022 operand uimmI6() %{
4023 predicate(Assembler::is_uimm(n->get_int(), 6));
4024 match(ConI);
4025 op_cost(0);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4029
4030 // Unsigned Integer Immediate: 6-bit int, greater than 32
4031 operand uimmI6_ge32() %{
4032 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4033 match(ConI);
4034 op_cost(0);
4035 format %{ %}
4036 interface(CONST_INTER);
4037 %}
4038
4039 // Unsigned Integer Immediate: 15-bit
4040 operand uimmI15() %{
4041 predicate(Assembler::is_uimm(n->get_int(), 15));
4042 match(ConI);
4043 op_cost(0);
4044 format %{ %}
4045 interface(CONST_INTER);
4046 %}
4047
4048 // Unsigned Integer Immediate: 16-bit
4049 operand uimmI16() %{
4050 predicate(Assembler::is_uimm(n->get_int(), 16));
4051 match(ConI);
4052 op_cost(0);
4053 format %{ %}
4054 interface(CONST_INTER);
4055 %}
4056
4057 // constant 'int 0'.
4058 operand immI_0() %{
4059 predicate(n->get_int() == 0);
4060 match(ConI);
4061 op_cost(0);
4062 format %{ %}
4063 interface(CONST_INTER);
4064 %}
4065
4066 // constant 'int 1'.
4067 operand immI_1() %{
4068 predicate(n->get_int() == 1);
4069 match(ConI);
4070 op_cost(0);
4071 format %{ %}
4072 interface(CONST_INTER);
4073 %}
4074
4075 // constant 'int -1'.
4076 operand immI_minus1() %{
4077 predicate(n->get_int() == -1);
4078 match(ConI);
4079 op_cost(0);
4080 format %{ %}
4081 interface(CONST_INTER);
4082 %}
4083
4084 // int value 16.
4085 operand immI_16() %{
4086 predicate(n->get_int() == 16);
4087 match(ConI);
4088 op_cost(0);
4089 format %{ %}
4090 interface(CONST_INTER);
4091 %}
4092
4093 // int value 24.
4094 operand immI_24() %{
4095 predicate(n->get_int() == 24);
4096 match(ConI);
4097 op_cost(0);
4098 format %{ %}
4099 interface(CONST_INTER);
4100 %}
4101
4102 // Compressed oops constants
4103 // Pointer Immediate
4104 operand immN() %{
4105 match(ConN);
4106
4107 op_cost(10);
4108 format %{ %}
4109 interface(CONST_INTER);
4110 %}
4111
4112 // NULL Pointer Immediate
4113 operand immN_0() %{
4114 predicate(n->get_narrowcon() == 0);
4115 match(ConN);
4116
4117 op_cost(0);
4118 format %{ %}
4119 interface(CONST_INTER);
4120 %}
4121
4122 // Compressed klass constants
4123 operand immNKlass() %{
4124 match(ConNKlass);
4125
4126 op_cost(0);
4127 format %{ %}
4128 interface(CONST_INTER);
4129 %}
4130
4131 // This operand can be used to avoid matching of an instruct
4132 // with chain rule.
4133 operand immNKlass_NM() %{
4134 match(ConNKlass);
4135 predicate(false);
4136 op_cost(0);
4137 format %{ %}
4138 interface(CONST_INTER);
4139 %}
4140
4141 // Pointer Immediate: 64-bit
4142 operand immP() %{
4143 match(ConP);
4144 op_cost(0);
4145 format %{ %}
4146 interface(CONST_INTER);
4147 %}
4148
4149 // Operand to avoid match of loadConP.
4150 // This operand can be used to avoid matching of an instruct
4151 // with chain rule.
4152 operand immP_NM() %{
4153 match(ConP);
4154 predicate(false);
4155 op_cost(0);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4159
4160 // costant 'pointer 0'.
4161 operand immP_0() %{
4162 predicate(n->get_ptr() == 0);
4163 match(ConP);
4164 op_cost(0);
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4168
4169 // pointer 0x0 or 0x1
4170 operand immP_0or1() %{
4171 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4172 match(ConP);
4173 op_cost(0);
4174 format %{ %}
4175 interface(CONST_INTER);
4176 %}
4177
4178 operand immL() %{
4179 match(ConL);
4180 op_cost(40);
4181 format %{ %}
4182 interface(CONST_INTER);
4183 %}
4184
4185 // Long Immediate: 16-bit
4186 operand immL16() %{
4187 predicate(Assembler::is_simm(n->get_long(), 16));
4188 match(ConL);
4189 op_cost(0);
4190 format %{ %}
4191 interface(CONST_INTER);
4192 %}
4193
4194 // Long Immediate: 16-bit, 4-aligned
4195 operand immL16Alg4() %{
4196 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4197 match(ConL);
4198 op_cost(0);
4199 format %{ %}
4200 interface(CONST_INTER);
4201 %}
4202
4203 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4204 operand immL32hi16() %{
4205 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4206 match(ConL);
4207 op_cost(0);
4208 format %{ %}
4209 interface(CONST_INTER);
4210 %}
4211
4212 // Long Immediate: 32-bit
4213 operand immL32() %{
4214 predicate(Assembler::is_simm(n->get_long(), 32));
4215 match(ConL);
4216 op_cost(0);
4217 format %{ %}
4218 interface(CONST_INTER);
4219 %}
4220
4221 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4222 operand immLhighest16() %{
4223 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4224 match(ConL);
4225 op_cost(0);
4226 format %{ %}
4227 interface(CONST_INTER);
4228 %}
4229
4230 operand immLnegpow2() %{
4231 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4232 match(ConL);
4233 op_cost(0);
4234 format %{ %}
4235 interface(CONST_INTER);
4236 %}
4237
4238 operand immLpow2minus1() %{
4239 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4240 (n->get_long() != (jlong)0xffffffffffffffffL));
4241 match(ConL);
4242 op_cost(0);
4243 format %{ %}
4244 interface(CONST_INTER);
4245 %}
4246
4247 // constant 'long 0'.
4248 operand immL_0() %{
4249 predicate(n->get_long() == 0L);
4250 match(ConL);
4251 op_cost(0);
4252 format %{ %}
4253 interface(CONST_INTER);
4254 %}
4255
4256 // constat ' long -1'.
4257 operand immL_minus1() %{
4258 predicate(n->get_long() == -1L);
4259 match(ConL);
4260 op_cost(0);
4261 format %{ %}
4262 interface(CONST_INTER);
4263 %}
4264
4265 // Long Immediate: low 32-bit mask
4266 operand immL_32bits() %{
4267 predicate(n->get_long() == 0xFFFFFFFFL);
4268 match(ConL);
4269 op_cost(0);
4270 format %{ %}
4271 interface(CONST_INTER);
4272 %}
4273
4274 // Unsigned Long Immediate: 16-bit
4275 operand uimmL16() %{
4276 predicate(Assembler::is_uimm(n->get_long(), 16));
4277 match(ConL);
4278 op_cost(0);
4279 format %{ %}
4280 interface(CONST_INTER);
4281 %}
4282
4283 // Float Immediate
4284 operand immF() %{
4285 match(ConF);
4286 op_cost(40);
4287 format %{ %}
4288 interface(CONST_INTER);
4289 %}
4290
4291 // Float Immediate: +0.0f.
4292 operand immF_0() %{
4293 predicate(jint_cast(n->getf()) == 0);
4294 match(ConF);
4295
4296 op_cost(0);
4297 format %{ %}
4298 interface(CONST_INTER);
4299 %}
4300
4301 // Double Immediate
4302 operand immD() %{
4303 match(ConD);
4304 op_cost(40);
4305 format %{ %}
4306 interface(CONST_INTER);
4307 %}
4308
4309 // Integer Register Operands
4310 // Integer Destination Register
4311 // See definition of reg_class bits32_reg_rw.
4312 operand iRegIdst() %{
4313 constraint(ALLOC_IN_RC(bits32_reg_rw));
4314 match(RegI);
4315 match(rscratch1RegI);
4316 match(rscratch2RegI);
4317 match(rarg1RegI);
4318 match(rarg2RegI);
4319 match(rarg3RegI);
4320 match(rarg4RegI);
4321 format %{ %}
4322 interface(REG_INTER);
4323 %}
4324
4325 // Integer Source Register
4326 // See definition of reg_class bits32_reg_ro.
4327 operand iRegIsrc() %{
4328 constraint(ALLOC_IN_RC(bits32_reg_ro));
4329 match(RegI);
4330 match(rscratch1RegI);
4331 match(rscratch2RegI);
4332 match(rarg1RegI);
4333 match(rarg2RegI);
4334 match(rarg3RegI);
4335 match(rarg4RegI);
4336 format %{ %}
4337 interface(REG_INTER);
4338 %}
4339
4340 operand rscratch1RegI() %{
4341 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4342 match(iRegIdst);
4343 format %{ %}
4344 interface(REG_INTER);
4345 %}
4346
4347 operand rscratch2RegI() %{
4348 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4349 match(iRegIdst);
4350 format %{ %}
4351 interface(REG_INTER);
4352 %}
4353
4354 operand rarg1RegI() %{
4355 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4356 match(iRegIdst);
4357 format %{ %}
4358 interface(REG_INTER);
4359 %}
4360
4361 operand rarg2RegI() %{
4362 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4363 match(iRegIdst);
4364 format %{ %}
4365 interface(REG_INTER);
4366 %}
4367
4368 operand rarg3RegI() %{
4369 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4370 match(iRegIdst);
4371 format %{ %}
4372 interface(REG_INTER);
4373 %}
4374
4375 operand rarg4RegI() %{
4376 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4377 match(iRegIdst);
4378 format %{ %}
4379 interface(REG_INTER);
4380 %}
4381
4382 operand rarg1RegL() %{
4383 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4384 match(iRegLdst);
4385 format %{ %}
4386 interface(REG_INTER);
4387 %}
4388
4389 operand rarg2RegL() %{
4390 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4391 match(iRegLdst);
4392 format %{ %}
4393 interface(REG_INTER);
4394 %}
4395
4396 operand rarg3RegL() %{
4397 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4398 match(iRegLdst);
4399 format %{ %}
4400 interface(REG_INTER);
4401 %}
4402
4403 operand rarg4RegL() %{
4404 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4405 match(iRegLdst);
4406 format %{ %}
4407 interface(REG_INTER);
4408 %}
4409
4410 // Pointer Destination Register
4411 // See definition of reg_class bits64_reg_rw.
4412 operand iRegPdst() %{
4413 constraint(ALLOC_IN_RC(bits64_reg_rw));
4414 match(RegP);
4415 match(rscratch1RegP);
4416 match(rscratch2RegP);
4417 match(rarg1RegP);
4418 match(rarg2RegP);
4419 match(rarg3RegP);
4420 match(rarg4RegP);
4421 format %{ %}
4422 interface(REG_INTER);
4423 %}
4424
4425 // Pointer Destination Register
4426 // Operand not using r11 and r12 (killed in epilog).
4427 operand iRegPdstNoScratch() %{
4428 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4429 match(RegP);
4430 match(rarg1RegP);
4431 match(rarg2RegP);
4432 match(rarg3RegP);
4433 match(rarg4RegP);
4434 format %{ %}
4435 interface(REG_INTER);
4436 %}
4437
4438 // Pointer Source Register
4439 // See definition of reg_class bits64_reg_ro.
4440 operand iRegPsrc() %{
4441 constraint(ALLOC_IN_RC(bits64_reg_ro));
4442 match(RegP);
4443 match(iRegPdst);
4444 match(rscratch1RegP);
4445 match(rscratch2RegP);
4446 match(rarg1RegP);
4447 match(rarg2RegP);
4448 match(rarg3RegP);
4449 match(rarg4RegP);
4450 match(threadRegP);
4451 format %{ %}
4452 interface(REG_INTER);
4453 %}
4454
4455 // Thread operand.
4456 operand threadRegP() %{
4457 constraint(ALLOC_IN_RC(thread_bits64_reg));
4458 match(iRegPdst);
4459 format %{ "R16" %}
4460 interface(REG_INTER);
4461 %}
4462
4463 operand rscratch1RegP() %{
4464 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4465 match(iRegPdst);
4466 format %{ "R11" %}
4467 interface(REG_INTER);
4468 %}
4469
4470 operand rscratch2RegP() %{
4471 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4472 match(iRegPdst);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4476
4477 operand rarg1RegP() %{
4478 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4479 match(iRegPdst);
4480 format %{ %}
4481 interface(REG_INTER);
4482 %}
4483
4484 operand rarg2RegP() %{
4485 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4486 match(iRegPdst);
4487 format %{ %}
4488 interface(REG_INTER);
4489 %}
4490
4491 operand rarg3RegP() %{
4492 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4493 match(iRegPdst);
4494 format %{ %}
4495 interface(REG_INTER);
4496 %}
4497
4498 operand rarg4RegP() %{
4499 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4500 match(iRegPdst);
4501 format %{ %}
4502 interface(REG_INTER);
4503 %}
4504
4505 operand iRegNsrc() %{
4506 constraint(ALLOC_IN_RC(bits32_reg_ro));
4507 match(RegN);
4508 match(iRegNdst);
4509
4510 format %{ %}
4511 interface(REG_INTER);
4512 %}
4513
4514 operand iRegNdst() %{
4515 constraint(ALLOC_IN_RC(bits32_reg_rw));
4516 match(RegN);
4517
4518 format %{ %}
4519 interface(REG_INTER);
4520 %}
4521
4522 // Long Destination Register
4523 // See definition of reg_class bits64_reg_rw.
4524 operand iRegLdst() %{
4525 constraint(ALLOC_IN_RC(bits64_reg_rw));
4526 match(RegL);
4527 match(rscratch1RegL);
4528 match(rscratch2RegL);
4529 format %{ %}
4530 interface(REG_INTER);
4531 %}
4532
4533 // Long Source Register
4534 // See definition of reg_class bits64_reg_ro.
4535 operand iRegLsrc() %{
4536 constraint(ALLOC_IN_RC(bits64_reg_ro));
4537 match(RegL);
4538 match(iRegLdst);
4539 match(rscratch1RegL);
4540 match(rscratch2RegL);
4541 format %{ %}
4542 interface(REG_INTER);
4543 %}
4544
4545 // Special operand for ConvL2I.
4546 operand iRegL2Isrc(iRegLsrc reg) %{
4547 constraint(ALLOC_IN_RC(bits64_reg_ro));
4548 match(ConvL2I reg);
4549 format %{ "ConvL2I($reg)" %}
4550 interface(REG_INTER)
4551 %}
4552
4553 operand rscratch1RegL() %{
4554 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4555 match(RegL);
4556 format %{ %}
4557 interface(REG_INTER);
4558 %}
4559
4560 operand rscratch2RegL() %{
4561 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4562 match(RegL);
4563 format %{ %}
4564 interface(REG_INTER);
4565 %}
4566
4567 // Condition Code Flag Registers
4568 operand flagsReg() %{
4569 constraint(ALLOC_IN_RC(int_flags));
4570 match(RegFlags);
4571 format %{ %}
4572 interface(REG_INTER);
4573 %}
4574
4575 operand flagsRegSrc() %{
4576 constraint(ALLOC_IN_RC(int_flags_ro));
4577 match(RegFlags);
4578 match(flagsReg);
4579 match(flagsRegCR0);
4580 format %{ %}
4581 interface(REG_INTER);
4582 %}
4583
4584 // Condition Code Flag Register CR0
4585 operand flagsRegCR0() %{
4586 constraint(ALLOC_IN_RC(int_flags_CR0));
4587 match(RegFlags);
4588 format %{ "CR0" %}
4589 interface(REG_INTER);
4590 %}
4591
4592 operand flagsRegCR1() %{
4593 constraint(ALLOC_IN_RC(int_flags_CR1));
4594 match(RegFlags);
4595 format %{ "CR1" %}
4596 interface(REG_INTER);
4597 %}
4598
4599 operand flagsRegCR6() %{
4600 constraint(ALLOC_IN_RC(int_flags_CR6));
4601 match(RegFlags);
4602 format %{ "CR6" %}
4603 interface(REG_INTER);
4604 %}
4605
4606 operand regCTR() %{
4607 constraint(ALLOC_IN_RC(ctr_reg));
4608 // RegFlags should work. Introducing a RegSpecial type would cause a
4609 // lot of changes.
4610 match(RegFlags);
4611 format %{"SR_CTR" %}
4612 interface(REG_INTER);
4613 %}
4614
4615 operand regD() %{
4616 constraint(ALLOC_IN_RC(dbl_reg));
4617 match(RegD);
4618 format %{ %}
4619 interface(REG_INTER);
4620 %}
4621
4622 operand regF() %{
4623 constraint(ALLOC_IN_RC(flt_reg));
4624 match(RegF);
4625 format %{ %}
4626 interface(REG_INTER);
4627 %}
4628
4629 // Special Registers
4630
4631 // Method Register
4632 operand inline_cache_regP(iRegPdst reg) %{
4633 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4634 match(reg);
4635 format %{ %}
4636 interface(REG_INTER);
4637 %}
4638
4639 operand compiler_method_oop_regP(iRegPdst reg) %{
4640 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4641 match(reg);
4642 format %{ %}
4643 interface(REG_INTER);
4644 %}
4645
4646 operand interpreter_method_oop_regP(iRegPdst reg) %{
4647 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4648 match(reg);
4649 format %{ %}
4650 interface(REG_INTER);
4651 %}
4652
4653 // Operands to remove register moves in unscaled mode.
4654 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4655 operand iRegP2N(iRegPsrc reg) %{
4656 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4657 constraint(ALLOC_IN_RC(bits64_reg_ro));
4658 match(EncodeP reg);
4659 format %{ "$reg" %}
4660 interface(REG_INTER)
4661 %}
4662
4663 operand iRegN2P(iRegNsrc reg) %{
4664 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4665 constraint(ALLOC_IN_RC(bits32_reg_ro));
4666 match(DecodeN reg);
4667 format %{ "$reg" %}
4668 interface(REG_INTER)
4669 %}
4670
4671 operand iRegN2P_klass(iRegNsrc reg) %{
4672 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4673 constraint(ALLOC_IN_RC(bits32_reg_ro));
4674 match(DecodeNKlass reg);
4675 format %{ "$reg" %}
4676 interface(REG_INTER)
4677 %}
4678
4679 //----------Complex Operands---------------------------------------------------
4680 // Indirect Memory Reference
4681 operand indirect(iRegPsrc reg) %{
4682 constraint(ALLOC_IN_RC(bits64_reg_ro));
4683 match(reg);
4684 op_cost(100);
4685 format %{ "[$reg]" %}
4686 interface(MEMORY_INTER) %{
4687 base($reg);
4688 index(0x0);
4689 scale(0x0);
4690 disp(0x0);
4691 %}
4692 %}
4693
4694 // Indirect with Offset
4695 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4696 constraint(ALLOC_IN_RC(bits64_reg_ro));
4697 match(AddP reg offset);
4698 op_cost(100);
4699 format %{ "[$reg + $offset]" %}
4700 interface(MEMORY_INTER) %{
4701 base($reg);
4702 index(0x0);
4703 scale(0x0);
4704 disp($offset);
4705 %}
4706 %}
4707
4708 // Indirect with 4-aligned Offset
4709 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4710 constraint(ALLOC_IN_RC(bits64_reg_ro));
4711 match(AddP reg offset);
4712 op_cost(100);
4713 format %{ "[$reg + $offset]" %}
4714 interface(MEMORY_INTER) %{
4715 base($reg);
4716 index(0x0);
4717 scale(0x0);
4718 disp($offset);
4719 %}
4720 %}
4721
4722 //----------Complex Operands for Compressed OOPs-------------------------------
4723 // Compressed OOPs with narrow_oop_shift == 0.
4724
4725 // Indirect Memory Reference, compressed OOP
4726 operand indirectNarrow(iRegNsrc reg) %{
4727 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4728 constraint(ALLOC_IN_RC(bits64_reg_ro));
4729 match(DecodeN reg);
4730 op_cost(100);
4731 format %{ "[$reg]" %}
4732 interface(MEMORY_INTER) %{
4733 base($reg);
4734 index(0x0);
4735 scale(0x0);
4736 disp(0x0);
4737 %}
4738 %}
4739
4740 operand indirectNarrow_klass(iRegNsrc reg) %{
4741 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4742 constraint(ALLOC_IN_RC(bits64_reg_ro));
4743 match(DecodeNKlass reg);
4744 op_cost(100);
4745 format %{ "[$reg]" %}
4746 interface(MEMORY_INTER) %{
4747 base($reg);
4748 index(0x0);
4749 scale(0x0);
4750 disp(0x0);
4751 %}
4752 %}
4753
4754 // Indirect with Offset, compressed OOP
4755 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4756 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4757 constraint(ALLOC_IN_RC(bits64_reg_ro));
4758 match(AddP (DecodeN reg) offset);
4759 op_cost(100);
4760 format %{ "[$reg + $offset]" %}
4761 interface(MEMORY_INTER) %{
4762 base($reg);
4763 index(0x0);
4764 scale(0x0);
4765 disp($offset);
4766 %}
4767 %}
4768
4769 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4770 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4771 constraint(ALLOC_IN_RC(bits64_reg_ro));
4772 match(AddP (DecodeNKlass reg) offset);
4773 op_cost(100);
4774 format %{ "[$reg + $offset]" %}
4775 interface(MEMORY_INTER) %{
4776 base($reg);
4777 index(0x0);
4778 scale(0x0);
4779 disp($offset);
4780 %}
4781 %}
4782
4783 // Indirect with 4-aligned Offset, compressed OOP
4784 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4785 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4786 constraint(ALLOC_IN_RC(bits64_reg_ro));
4787 match(AddP (DecodeN reg) offset);
4788 op_cost(100);
4789 format %{ "[$reg + $offset]" %}
4790 interface(MEMORY_INTER) %{
4791 base($reg);
4792 index(0x0);
4793 scale(0x0);
4794 disp($offset);
4795 %}
4796 %}
4797
4798 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4799 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4800 constraint(ALLOC_IN_RC(bits64_reg_ro));
4801 match(AddP (DecodeNKlass reg) offset);
4802 op_cost(100);
4803 format %{ "[$reg + $offset]" %}
4804 interface(MEMORY_INTER) %{
4805 base($reg);
4806 index(0x0);
4807 scale(0x0);
4808 disp($offset);
4809 %}
4810 %}
4811
4812 //----------Special Memory Operands--------------------------------------------
4813 // Stack Slot Operand
4814 //
4815 // This operand is used for loading and storing temporary values on
4816 // the stack where a match requires a value to flow through memory.
4817 operand stackSlotI(sRegI reg) %{
4818 constraint(ALLOC_IN_RC(stack_slots));
4819 op_cost(100);
4820 //match(RegI);
4821 format %{ "[sp+$reg]" %}
4822 interface(MEMORY_INTER) %{
4823 base(0x1); // R1_SP
4824 index(0x0);
4825 scale(0x0);
4826 disp($reg); // Stack Offset
4827 %}
4828 %}
4829
4830 operand stackSlotL(sRegL reg) %{
4831 constraint(ALLOC_IN_RC(stack_slots));
4832 op_cost(100);
4833 //match(RegL);
4834 format %{ "[sp+$reg]" %}
4835 interface(MEMORY_INTER) %{
4836 base(0x1); // R1_SP
4837 index(0x0);
4838 scale(0x0);
4839 disp($reg); // Stack Offset
4840 %}
4841 %}
4842
4843 operand stackSlotP(sRegP reg) %{
4844 constraint(ALLOC_IN_RC(stack_slots));
4845 op_cost(100);
4846 //match(RegP);
4847 format %{ "[sp+$reg]" %}
4848 interface(MEMORY_INTER) %{
4849 base(0x1); // R1_SP
4850 index(0x0);
4851 scale(0x0);
4852 disp($reg); // Stack Offset
4853 %}
4854 %}
4855
4856 operand stackSlotF(sRegF reg) %{
4857 constraint(ALLOC_IN_RC(stack_slots));
4858 op_cost(100);
4859 //match(RegF);
4860 format %{ "[sp+$reg]" %}
4861 interface(MEMORY_INTER) %{
4862 base(0x1); // R1_SP
4863 index(0x0);
4864 scale(0x0);
4865 disp($reg); // Stack Offset
4866 %}
4867 %}
4868
4869 operand stackSlotD(sRegD reg) %{
4870 constraint(ALLOC_IN_RC(stack_slots));
4871 op_cost(100);
4872 //match(RegD);
4873 format %{ "[sp+$reg]" %}
4874 interface(MEMORY_INTER) %{
4875 base(0x1); // R1_SP
4876 index(0x0);
4877 scale(0x0);
4878 disp($reg); // Stack Offset
4879 %}
4880 %}
4881
4882 // Operands for expressing Control Flow
4883 // NOTE: Label is a predefined operand which should not be redefined in
4884 // the AD file. It is generically handled within the ADLC.
4885
4886 //----------Conditional Branch Operands----------------------------------------
4887 // Comparison Op
4888 //
4889 // This is the operation of the comparison, and is limited to the
4890 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4891 // (!=).
4892 //
4893 // Other attributes of the comparison, such as unsignedness, are specified
4894 // by the comparison instruction that sets a condition code flags register.
4895 // That result is represented by a flags operand whose subtype is appropriate
4896 // to the unsignedness (etc.) of the comparison.
4897 //
4898 // Later, the instruction which matches both the Comparison Op (a Bool) and
4899 // the flags (produced by the Cmp) specifies the coding of the comparison op
4900 // by matching a specific subtype of Bool operand below.
4901
4902 // When used for floating point comparisons: unordered same as less.
4903 operand cmpOp() %{
4904 match(Bool);
4905 format %{ "" %}
4906 interface(COND_INTER) %{
4907 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4908 // BO & BI
4909 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4910 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4911 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4912 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4913 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4914 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4915 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4916 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4917 %}
4918 %}
4919
4920 //----------OPERAND CLASSES----------------------------------------------------
4921 // Operand Classes are groups of operands that are used to simplify
4922 // instruction definitions by not requiring the AD writer to specify
4923 // seperate instructions for every form of operand when the
4924 // instruction accepts multiple operand types with the same basic
4925 // encoding and format. The classic case of this is memory operands.
4926 // Indirect is not included since its use is limited to Compare & Swap.
4927
4928 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4929 // Memory operand where offsets are 4-aligned. Required for ld, std.
4930 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4931 opclass indirectMemory(indirect, indirectNarrow);
4932
4933 // Special opclass for I and ConvL2I.
4934 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4935
4936 // Operand classes to match encode and decode. iRegN_P2N is only used
4937 // for storeN. I have never seen an encode node elsewhere.
4938 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4939 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4940
4941 //----------PIPELINE-----------------------------------------------------------
4942
4943 pipeline %{
4944
4945 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4946 // J. Res. & Dev., No. 1, Jan. 2002.
4947
4948 //----------ATTRIBUTES---------------------------------------------------------
4949 attributes %{
4950
4951 // Power4 instructions are of fixed length.
4952 fixed_size_instructions;
4953
4954 // TODO: if `bundle' means number of instructions fetched
4955 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4956 // max instructions issued per cycle, this is 5.
4957 max_instructions_per_bundle = 8;
4958
4959 // A Power4 instruction is 4 bytes long.
4960 instruction_unit_size = 4;
4961
4962 // The Power4 processor fetches 64 bytes...
4963 instruction_fetch_unit_size = 64;
4964
4965 // ...in one line
4966 instruction_fetch_units = 1
4967
4968 // Unused, list one so that array generated by adlc is not empty.
4969 // Aix compiler chokes if _nop_count = 0.
4970 nops(fxNop);
4971 %}
4972
4973 //----------RESOURCES----------------------------------------------------------
4974 // Resources are the functional units available to the machine
4975 resources(
4976 PPC_BR, // branch unit
4977 PPC_CR, // condition unit
4978 PPC_FX1, // integer arithmetic unit 1
4979 PPC_FX2, // integer arithmetic unit 2
4980 PPC_LDST1, // load/store unit 1
4981 PPC_LDST2, // load/store unit 2
4982 PPC_FP1, // float arithmetic unit 1
4983 PPC_FP2, // float arithmetic unit 2
4984 PPC_LDST = PPC_LDST1 | PPC_LDST2,
4985 PPC_FX = PPC_FX1 | PPC_FX2,
4986 PPC_FP = PPC_FP1 | PPC_FP2
4987 );
4988
4989 //----------PIPELINE DESCRIPTION-----------------------------------------------
4990 // Pipeline Description specifies the stages in the machine's pipeline
4991 pipe_desc(
4992 // Power4 longest pipeline path
4993 PPC_IF, // instruction fetch
4994 PPC_IC,
4995 //PPC_BP, // branch prediction
4996 PPC_D0, // decode
4997 PPC_D1, // decode
4998 PPC_D2, // decode
4999 PPC_D3, // decode
5000 PPC_Xfer1,
5001 PPC_GD, // group definition
5002 PPC_MP, // map
5003 PPC_ISS, // issue
5004 PPC_RF, // resource fetch
5005 PPC_EX1, // execute (all units)
5006 PPC_EX2, // execute (FP, LDST)
5007 PPC_EX3, // execute (FP, LDST)
5008 PPC_EX4, // execute (FP)
5009 PPC_EX5, // execute (FP)
5010 PPC_EX6, // execute (FP)
5011 PPC_WB, // write back
5012 PPC_Xfer2,
5013 PPC_CP
5014 );
5015
5016 //----------PIPELINE CLASSES---------------------------------------------------
5017 // Pipeline Classes describe the stages in which input and output are
5018 // referenced by the hardware pipeline.
5019
5020 // Simple pipeline classes.
5021
5022 // Default pipeline class.
5023 pipe_class pipe_class_default() %{
5024 single_instruction;
5025 fixed_latency(2);
5026 %}
5027
5028 // Pipeline class for empty instructions.
5029 pipe_class pipe_class_empty() %{
5030 single_instruction;
5031 fixed_latency(0);
5032 %}
5033
5034 // Pipeline class for compares.
5035 pipe_class pipe_class_compare() %{
5036 single_instruction;
5037 fixed_latency(16);
5038 %}
5039
5040 // Pipeline class for traps.
5041 pipe_class pipe_class_trap() %{
5042 single_instruction;
5043 fixed_latency(100);
5044 %}
5045
5046 // Pipeline class for memory operations.
5047 pipe_class pipe_class_memory() %{
5048 single_instruction;
5049 fixed_latency(16);
5050 %}
5051
5052 // Pipeline class for call.
5053 pipe_class pipe_class_call() %{
5054 single_instruction;
5055 fixed_latency(100);
5056 %}
5057
5058 // Define the class for the Nop node.
5059 define %{
5060 MachNop = pipe_class_default;
5061 %}
5062
5063 %}
5064
5065 //----------INSTRUCTIONS-------------------------------------------------------
5066
5067 // Naming of instructions:
5068 // opA_operB / opA_operB_operC:
5069 // Operation 'op' with one or two source operands 'oper'. Result
5070 // type is A, source operand types are B and C.
5071 // Iff A == B == C, B and C are left out.
5072 //
5073 // The instructions are ordered according to the following scheme:
5074 // - loads
5075 // - load constants
5076 // - prefetch
5077 // - store
5078 // - encode/decode
5079 // - membar
5080 // - conditional moves
5081 // - compare & swap
5082 // - arithmetic and logic operations
5083 // * int: Add, Sub, Mul, Div, Mod
5084 // * int: lShift, arShift, urShift, rot
5085 // * float: Add, Sub, Mul, Div
5086 // * and, or, xor ...
5087 // - register moves: float <-> int, reg <-> stack, repl
5088 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5089 // - conv (low level type cast requiring bit changes (sign extend etc)
5090 // - compares, range & zero checks.
5091 // - branches
5092 // - complex operations, intrinsics, min, max, replicate
5093 // - lock
5094 // - Calls
5095 //
5096 // If there are similar instructions with different types they are sorted:
5097 // int before float
5098 // small before big
5099 // signed before unsigned
5100 // e.g., loadS before loadUS before loadI before loadF.
5101
5102
5103 //----------Load/Store Instructions--------------------------------------------
5104
5105 //----------Load Instructions--------------------------------------------------
5106
5107 // Converts byte to int.
5108 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5109 // reuses the 'amount' operand, but adlc expects that operand specification
5110 // and operands in match rule are equivalent.
5111 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5112 effect(DEF dst, USE src);
5113 format %{ "EXTSB $dst, $src \t// byte->int" %}
5114 size(4);
5115 ins_encode %{
5116 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5117 __ extsb($dst$$Register, $src$$Register);
5118 %}
5119 ins_pipe(pipe_class_default);
5120 %}
5121
5122 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5123 // match-rule, false predicate
5124 match(Set dst (LoadB mem));
5125 predicate(false);
5126
5127 format %{ "LBZ $dst, $mem" %}
5128 size(4);
5129 ins_encode( enc_lbz(dst, mem) );
5130 ins_pipe(pipe_class_memory);
5131 %}
5132
5133 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5134 // match-rule, false predicate
5135 match(Set dst (LoadB mem));
5136 predicate(false);
5137
5138 format %{ "LBZ $dst, $mem\n\t"
5139 "TWI $dst\n\t"
5140 "ISYNC" %}
5141 size(12);
5142 ins_encode( enc_lbz_ac(dst, mem) );
5143 ins_pipe(pipe_class_memory);
5144 %}
5145
5146 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5147 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5148 match(Set dst (LoadB mem));
5149 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5150 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5151 expand %{
5152 iRegIdst tmp;
5153 loadUB_indirect(tmp, mem);
5154 convB2I_reg_2(dst, tmp);
5155 %}
5156 %}
5157
5158 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5159 match(Set dst (LoadB mem));
5160 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5161 expand %{
5162 iRegIdst tmp;
5163 loadUB_indirect_ac(tmp, mem);
5164 convB2I_reg_2(dst, tmp);
5165 %}
5166 %}
5167
5168 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5169 // match-rule, false predicate
5170 match(Set dst (LoadB mem));
5171 predicate(false);
5172
5173 format %{ "LBZ $dst, $mem" %}
5174 size(4);
5175 ins_encode( enc_lbz(dst, mem) );
5176 ins_pipe(pipe_class_memory);
5177 %}
5178
5179 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5180 // match-rule, false predicate
5181 match(Set dst (LoadB mem));
5182 predicate(false);
5183
5184 format %{ "LBZ $dst, $mem\n\t"
5185 "TWI $dst\n\t"
5186 "ISYNC" %}
5187 size(12);
5188 ins_encode( enc_lbz_ac(dst, mem) );
5189 ins_pipe(pipe_class_memory);
5190 %}
5191
5192 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5193 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5194 match(Set dst (LoadB mem));
5195 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5196 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5197
5198 expand %{
5199 iRegIdst tmp;
5200 loadUB_indOffset16(tmp, mem);
5201 convB2I_reg_2(dst, tmp);
5202 %}
5203 %}
5204
5205 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5206 match(Set dst (LoadB mem));
5207 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5208
5209 expand %{
5210 iRegIdst tmp;
5211 loadUB_indOffset16_ac(tmp, mem);
5212 convB2I_reg_2(dst, tmp);
5213 %}
5214 %}
5215
5216 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5217 instruct loadUB(iRegIdst dst, memory mem) %{
5218 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5219 match(Set dst (LoadUB mem));
5220 ins_cost(MEMORY_REF_COST);
5221
5222 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5223 size(4);
5224 ins_encode( enc_lbz(dst, mem) );
5225 ins_pipe(pipe_class_memory);
5226 %}
5227
5228 // Load Unsigned Byte (8bit UNsigned) acquire.
5229 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5230 match(Set dst (LoadUB mem));
5231 ins_cost(3*MEMORY_REF_COST);
5232
5233 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5234 "TWI $dst\n\t"
5235 "ISYNC" %}
5236 size(12);
5237 ins_encode( enc_lbz_ac(dst, mem) );
5238 ins_pipe(pipe_class_memory);
5239 %}
5240
5241 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5242 instruct loadUB2L(iRegLdst dst, memory mem) %{
5243 match(Set dst (ConvI2L (LoadUB mem)));
5244 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5245 ins_cost(MEMORY_REF_COST);
5246
5247 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5248 size(4);
5249 ins_encode( enc_lbz(dst, mem) );
5250 ins_pipe(pipe_class_memory);
5251 %}
5252
5253 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5254 match(Set dst (ConvI2L (LoadUB mem)));
5255 ins_cost(3*MEMORY_REF_COST);
5256
5257 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5258 "TWI $dst\n\t"
5259 "ISYNC" %}
5260 size(12);
5261 ins_encode( enc_lbz_ac(dst, mem) );
5262 ins_pipe(pipe_class_memory);
5263 %}
5264
5265 // Load Short (16bit signed)
5266 instruct loadS(iRegIdst dst, memory mem) %{
5267 match(Set dst (LoadS mem));
5268 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5269 ins_cost(MEMORY_REF_COST);
5270
5271 format %{ "LHA $dst, $mem" %}
5272 size(4);
5273 ins_encode %{
5274 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5275 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5276 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5277 %}
5278 ins_pipe(pipe_class_memory);
5279 %}
5280
5281 // Load Short (16bit signed) acquire.
5282 instruct loadS_ac(iRegIdst dst, memory mem) %{
5283 match(Set dst (LoadS mem));
5284 ins_cost(3*MEMORY_REF_COST);
5285
5286 format %{ "LHA $dst, $mem\t acquire\n\t"
5287 "TWI $dst\n\t"
5288 "ISYNC" %}
5289 size(12);
5290 ins_encode %{
5291 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5292 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5293 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5294 __ twi_0($dst$$Register);
5295 __ isync();
5296 %}
5297 ins_pipe(pipe_class_memory);
5298 %}
5299
5300 // Load Char (16bit unsigned)
5301 instruct loadUS(iRegIdst dst, memory mem) %{
5302 match(Set dst (LoadUS mem));
5303 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5304 ins_cost(MEMORY_REF_COST);
5305
5306 format %{ "LHZ $dst, $mem" %}
5307 size(4);
5308 ins_encode( enc_lhz(dst, mem) );
5309 ins_pipe(pipe_class_memory);
5310 %}
5311
5312 // Load Char (16bit unsigned) acquire.
5313 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5314 match(Set dst (LoadUS mem));
5315 ins_cost(3*MEMORY_REF_COST);
5316
5317 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5318 "TWI $dst\n\t"
5319 "ISYNC" %}
5320 size(12);
5321 ins_encode( enc_lhz_ac(dst, mem) );
5322 ins_pipe(pipe_class_memory);
5323 %}
5324
5325 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5326 instruct loadUS2L(iRegLdst dst, memory mem) %{
5327 match(Set dst (ConvI2L (LoadUS mem)));
5328 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5329 ins_cost(MEMORY_REF_COST);
5330
5331 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5332 size(4);
5333 ins_encode( enc_lhz(dst, mem) );
5334 ins_pipe(pipe_class_memory);
5335 %}
5336
5337 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5338 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5339 match(Set dst (ConvI2L (LoadUS mem)));
5340 ins_cost(3*MEMORY_REF_COST);
5341
5342 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5343 "TWI $dst\n\t"
5344 "ISYNC" %}
5345 size(12);
5346 ins_encode( enc_lhz_ac(dst, mem) );
5347 ins_pipe(pipe_class_memory);
5348 %}
5349
5350 // Load Integer.
5351 instruct loadI(iRegIdst dst, memory mem) %{
5352 match(Set dst (LoadI mem));
5353 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5354 ins_cost(MEMORY_REF_COST);
5355
5356 format %{ "LWZ $dst, $mem" %}
5357 size(4);
5358 ins_encode( enc_lwz(dst, mem) );
5359 ins_pipe(pipe_class_memory);
5360 %}
5361
5362 // Load Integer acquire.
5363 instruct loadI_ac(iRegIdst dst, memory mem) %{
5364 match(Set dst (LoadI mem));
5365 ins_cost(3*MEMORY_REF_COST);
5366
5367 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5368 "TWI $dst\n\t"
5369 "ISYNC" %}
5370 size(12);
5371 ins_encode( enc_lwz_ac(dst, mem) );
5372 ins_pipe(pipe_class_memory);
5373 %}
5374
5375 // Match loading integer and casting it to unsigned int in
5376 // long register.
5377 // LoadI + ConvI2L + AndL 0xffffffff.
5378 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5379 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5380 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5381 ins_cost(MEMORY_REF_COST);
5382
5383 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5384 size(4);
5385 ins_encode( enc_lwz(dst, mem) );
5386 ins_pipe(pipe_class_memory);
5387 %}
5388
5389 // Match loading integer and casting it to long.
5390 instruct loadI2L(iRegLdst dst, memory mem) %{
5391 match(Set dst (ConvI2L (LoadI mem)));
5392 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5393 ins_cost(MEMORY_REF_COST);
5394
5395 format %{ "LWA $dst, $mem \t// loadI2L" %}
5396 size(4);
5397 ins_encode %{
5398 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5399 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5400 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5401 %}
5402 ins_pipe(pipe_class_memory);
5403 %}
5404
5405 // Match loading integer and casting it to long - acquire.
5406 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5407 match(Set dst (ConvI2L (LoadI mem)));
5408 ins_cost(3*MEMORY_REF_COST);
5409
5410 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5411 "TWI $dst\n\t"
5412 "ISYNC" %}
5413 size(12);
5414 ins_encode %{
5415 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5416 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5417 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5418 __ twi_0($dst$$Register);
5419 __ isync();
5420 %}
5421 ins_pipe(pipe_class_memory);
5422 %}
5423
5424 // Load Long - aligned
5425 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5426 match(Set dst (LoadL mem));
5427 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5428 ins_cost(MEMORY_REF_COST);
5429
5430 format %{ "LD $dst, $mem \t// long" %}
5431 size(4);
5432 ins_encode( enc_ld(dst, mem) );
5433 ins_pipe(pipe_class_memory);
5434 %}
5435
5436 // Load Long - aligned acquire.
5437 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5438 match(Set dst (LoadL mem));
5439 ins_cost(3*MEMORY_REF_COST);
5440
5441 format %{ "LD $dst, $mem \t// long acquire\n\t"
5442 "TWI $dst\n\t"
5443 "ISYNC" %}
5444 size(12);
5445 ins_encode( enc_ld_ac(dst, mem) );
5446 ins_pipe(pipe_class_memory);
5447 %}
5448
5449 // Load Long - UNaligned
5450 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5451 match(Set dst (LoadL_unaligned mem));
5452 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5453 ins_cost(MEMORY_REF_COST);
5454
5455 format %{ "LD $dst, $mem \t// unaligned long" %}
5456 size(4);
5457 ins_encode( enc_ld(dst, mem) );
5458 ins_pipe(pipe_class_memory);
5459 %}
5460
5461 // Load nodes for superwords
5462
5463 // Load Aligned Packed Byte
5464 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5465 predicate(n->as_LoadVector()->memory_size() == 8);
5466 match(Set dst (LoadVector mem));
5467 ins_cost(MEMORY_REF_COST);
5468
5469 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5470 size(4);
5471 ins_encode( enc_ld(dst, mem) );
5472 ins_pipe(pipe_class_memory);
5473 %}
5474
5475 // Load Range, range = array length (=jint)
5476 instruct loadRange(iRegIdst dst, memory mem) %{
5477 match(Set dst (LoadRange mem));
5478 ins_cost(MEMORY_REF_COST);
5479
5480 format %{ "LWZ $dst, $mem \t// range" %}
5481 size(4);
5482 ins_encode( enc_lwz(dst, mem) );
5483 ins_pipe(pipe_class_memory);
5484 %}
5485
5486 // Load Compressed Pointer
5487 instruct loadN(iRegNdst dst, memory mem) %{
5488 match(Set dst (LoadN mem));
5489 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5490 ins_cost(MEMORY_REF_COST);
5491
5492 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5493 size(4);
5494 ins_encode( enc_lwz(dst, mem) );
5495 ins_pipe(pipe_class_memory);
5496 %}
5497
5498 // Load Compressed Pointer acquire.
5499 instruct loadN_ac(iRegNdst dst, memory mem) %{
5500 match(Set dst (LoadN mem));
5501 ins_cost(3*MEMORY_REF_COST);
5502
5503 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5504 "TWI $dst\n\t"
5505 "ISYNC" %}
5506 size(12);
5507 ins_encode( enc_lwz_ac(dst, mem) );
5508 ins_pipe(pipe_class_memory);
5509 %}
5510
5511 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5512 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5513 match(Set dst (DecodeN (LoadN mem)));
5514 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5515 ins_cost(MEMORY_REF_COST);
5516
5517 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5518 size(4);
5519 ins_encode( enc_lwz(dst, mem) );
5520 ins_pipe(pipe_class_memory);
5521 %}
5522
5523 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5524 match(Set dst (DecodeNKlass (LoadNKlass mem)));
5525 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5526 _kids[0]->_leaf->as_Load()->is_unordered());
5527 ins_cost(MEMORY_REF_COST);
5528
5529 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5530 size(4);
5531 ins_encode( enc_lwz(dst, mem) );
5532 ins_pipe(pipe_class_memory);
5533 %}
5534
5535 // Load Pointer
5536 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5537 match(Set dst (LoadP mem));
5538 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5539 ins_cost(MEMORY_REF_COST);
5540
5541 format %{ "LD $dst, $mem \t// ptr" %}
5542 size(4);
5543 ins_encode( enc_ld(dst, mem) );
5544 ins_pipe(pipe_class_memory);
5545 %}
5546
5547 // Load Pointer acquire.
5548 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5549 match(Set dst (LoadP mem));
5550 ins_cost(3*MEMORY_REF_COST);
5551
5552 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5553 "TWI $dst\n\t"
5554 "ISYNC" %}
5555 size(12);
5556 ins_encode( enc_ld_ac(dst, mem) );
5557 ins_pipe(pipe_class_memory);
5558 %}
5559
5560 // LoadP + CastP2L
5561 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5562 match(Set dst (CastP2X (LoadP mem)));
5563 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5564 ins_cost(MEMORY_REF_COST);
5565
5566 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5567 size(4);
5568 ins_encode( enc_ld(dst, mem) );
5569 ins_pipe(pipe_class_memory);
5570 %}
5571
5572 // Load compressed klass pointer.
5573 instruct loadNKlass(iRegNdst dst, memory mem) %{
5574 match(Set dst (LoadNKlass mem));
5575 ins_cost(MEMORY_REF_COST);
5576
5577 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5578 size(4);
5579 ins_encode( enc_lwz(dst, mem) );
5580 ins_pipe(pipe_class_memory);
5581 %}
5582
5583 // Load Klass Pointer
5584 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5585 match(Set dst (LoadKlass mem));
5586 ins_cost(MEMORY_REF_COST);
5587
5588 format %{ "LD $dst, $mem \t// klass ptr" %}
5589 size(4);
5590 ins_encode( enc_ld(dst, mem) );
5591 ins_pipe(pipe_class_memory);
5592 %}
5593
5594 // Load Float
5595 instruct loadF(regF dst, memory mem) %{
5596 match(Set dst (LoadF mem));
5597 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5598 ins_cost(MEMORY_REF_COST);
5599
5600 format %{ "LFS $dst, $mem" %}
5601 size(4);
5602 ins_encode %{
5603 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5604 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5605 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5606 %}
5607 ins_pipe(pipe_class_memory);
5608 %}
5609
5610 // Load Float acquire.
5611 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5612 match(Set dst (LoadF mem));
5613 effect(TEMP cr0);
5614 ins_cost(3*MEMORY_REF_COST);
5615
5616 format %{ "LFS $dst, $mem \t// acquire\n\t"
5617 "FCMPU cr0, $dst, $dst\n\t"
5618 "BNE cr0, next\n"
5619 "next:\n\t"
5620 "ISYNC" %}
5621 size(16);
5622 ins_encode %{
5623 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5624 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5625 Label next;
5626 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5627 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5628 __ bne(CCR0, next);
5629 __ bind(next);
5630 __ isync();
5631 %}
5632 ins_pipe(pipe_class_memory);
5633 %}
5634
5635 // Load Double - aligned
5636 instruct loadD(regD dst, memory mem) %{
5637 match(Set dst (LoadD mem));
5638 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5639 ins_cost(MEMORY_REF_COST);
5640
5641 format %{ "LFD $dst, $mem" %}
5642 size(4);
5643 ins_encode( enc_lfd(dst, mem) );
5644 ins_pipe(pipe_class_memory);
5645 %}
5646
5647 // Load Double - aligned acquire.
5648 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5649 match(Set dst (LoadD mem));
5650 effect(TEMP cr0);
5651 ins_cost(3*MEMORY_REF_COST);
5652
5653 format %{ "LFD $dst, $mem \t// acquire\n\t"
5654 "FCMPU cr0, $dst, $dst\n\t"
5655 "BNE cr0, next\n"
5656 "next:\n\t"
5657 "ISYNC" %}
5658 size(16);
5659 ins_encode %{
5660 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5661 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5662 Label next;
5663 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5664 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5665 __ bne(CCR0, next);
5666 __ bind(next);
5667 __ isync();
5668 %}
5669 ins_pipe(pipe_class_memory);
5670 %}
5671
5672 // Load Double - UNaligned
5673 instruct loadD_unaligned(regD dst, memory mem) %{
5674 match(Set dst (LoadD_unaligned mem));
5675 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5676 ins_cost(MEMORY_REF_COST);
5677
5678 format %{ "LFD $dst, $mem" %}
5679 size(4);
5680 ins_encode( enc_lfd(dst, mem) );
5681 ins_pipe(pipe_class_memory);
5682 %}
5683
5684 //----------Constants--------------------------------------------------------
5685
5686 // Load MachConstantTableBase: add hi offset to global toc.
5687 // TODO: Handle hidden register r29 in bundler!
5688 instruct loadToc_hi(iRegLdst dst) %{
5689 effect(DEF dst);
5690 ins_cost(DEFAULT_COST);
5691
5692 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5693 size(4);
5694 ins_encode %{
5695 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5696 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5697 %}
5698 ins_pipe(pipe_class_default);
5699 %}
5700
5701 // Load MachConstantTableBase: add lo offset to global toc.
5702 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5703 effect(DEF dst, USE src);
5704 ins_cost(DEFAULT_COST);
5705
5706 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5707 size(4);
5708 ins_encode %{
5709 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5710 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5711 %}
5712 ins_pipe(pipe_class_default);
5713 %}
5714
5715 // Load 16-bit integer constant 0xssss????
5716 instruct loadConI16(iRegIdst dst, immI16 src) %{
5717 match(Set dst src);
5718
5719 format %{ "LI $dst, $src" %}
5720 size(4);
5721 ins_encode %{
5722 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5723 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5724 %}
5725 ins_pipe(pipe_class_default);
5726 %}
5727
5728 // Load integer constant 0x????0000
5729 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5730 match(Set dst src);
5731 ins_cost(DEFAULT_COST);
5732
5733 format %{ "LIS $dst, $src.hi" %}
5734 size(4);
5735 ins_encode %{
5736 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5737 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5738 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5739 %}
5740 ins_pipe(pipe_class_default);
5741 %}
5742
5743 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5744 // and sign extended), this adds the low 16 bits.
5745 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5746 // no match-rule, false predicate
5747 effect(DEF dst, USE src1, USE src2);
5748 predicate(false);
5749
5750 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5751 size(4);
5752 ins_encode %{
5753 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5754 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5755 %}
5756 ins_pipe(pipe_class_default);
5757 %}
5758
5759 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5760 match(Set dst src);
5761 ins_cost(DEFAULT_COST*2);
5762
5763 expand %{
5764 // Would like to use $src$$constant.
5765 immI16 srcLo %{ _opnds[1]->constant() %}
5766 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5767 immIhi16 srcHi %{ _opnds[1]->constant() %}
5768 iRegIdst tmpI;
5769 loadConIhi16(tmpI, srcHi);
5770 loadConI32_lo16(dst, tmpI, srcLo);
5771 %}
5772 %}
5773
5774 // No constant pool entries required.
5775 instruct loadConL16(iRegLdst dst, immL16 src) %{
5776 match(Set dst src);
5777
5778 format %{ "LI $dst, $src \t// long" %}
5779 size(4);
5780 ins_encode %{
5781 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5782 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5783 %}
5784 ins_pipe(pipe_class_default);
5785 %}
5786
5787 // Load long constant 0xssssssss????0000
5788 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5789 match(Set dst src);
5790 ins_cost(DEFAULT_COST);
5791
5792 format %{ "LIS $dst, $src.hi \t// long" %}
5793 size(4);
5794 ins_encode %{
5795 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5796 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5797 %}
5798 ins_pipe(pipe_class_default);
5799 %}
5800
5801 // To load a 32 bit constant: merge lower 16 bits into already loaded
5802 // high 16 bits.
5803 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5804 // no match-rule, false predicate
5805 effect(DEF dst, USE src1, USE src2);
5806 predicate(false);
5807
5808 format %{ "ORI $dst, $src1, $src2.lo" %}
5809 size(4);
5810 ins_encode %{
5811 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5812 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5813 %}
5814 ins_pipe(pipe_class_default);
5815 %}
5816
5817 // Load 32-bit long constant
5818 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5819 match(Set dst src);
5820 ins_cost(DEFAULT_COST*2);
5821
5822 expand %{
5823 // Would like to use $src$$constant.
5824 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5825 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5826 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5827 iRegLdst tmpL;
5828 loadConL32hi16(tmpL, srcHi);
5829 loadConL32_lo16(dst, tmpL, srcLo);
5830 %}
5831 %}
5832
5833 // Load long constant 0x????000000000000.
5834 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5835 match(Set dst src);
5836 ins_cost(DEFAULT_COST);
5837
5838 expand %{
5839 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5840 immI shift32 %{ 32 %}
5841 iRegLdst tmpL;
5842 loadConL32hi16(tmpL, srcHi);
5843 lshiftL_regL_immI(dst, tmpL, shift32);
5844 %}
5845 %}
5846
5847 // Expand node for constant pool load: small offset.
5848 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5849 effect(DEF dst, USE src, USE toc);
5850 ins_cost(MEMORY_REF_COST);
5851
5852 ins_num_consts(1);
5853 // Needed so that CallDynamicJavaDirect can compute the address of this
5854 // instruction for relocation.
5855 ins_field_cbuf_insts_offset(int);
5856
5857 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5858 size(4);
5859 ins_encode( enc_load_long_constL(dst, src, toc) );
5860 ins_pipe(pipe_class_memory);
5861 %}
5862
5863 // Expand node for constant pool load: large offset.
5864 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5865 effect(DEF dst, USE src, USE toc);
5866 predicate(false);
5867
5868 ins_num_consts(1);
5869 ins_field_const_toc_offset(int);
5870 // Needed so that CallDynamicJavaDirect can compute the address of this
5871 // instruction for relocation.
5872 ins_field_cbuf_insts_offset(int);
5873
5874 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5875 size(4);
5876 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5877 ins_pipe(pipe_class_default);
5878 %}
5879
5880 // Expand node for constant pool load: large offset.
5881 // No constant pool entries required.
5882 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5883 effect(DEF dst, USE src, USE base);
5884 predicate(false);
5885
5886 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5887
5888 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5889 size(4);
5890 ins_encode %{
5891 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5892 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5893 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5894 %}
5895 ins_pipe(pipe_class_memory);
5896 %}
5897
5898 // Load long constant from constant table. Expand in case of
5899 // offset > 16 bit is needed.
5900 // Adlc adds toc node MachConstantTableBase.
5901 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5902 match(Set dst src);
5903 ins_cost(MEMORY_REF_COST);
5904
5905 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5906 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5907 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5908 %}
5909
5910 // Load NULL as compressed oop.
5911 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5912 match(Set dst src);
5913 ins_cost(DEFAULT_COST);
5914
5915 format %{ "LI $dst, $src \t// compressed ptr" %}
5916 size(4);
5917 ins_encode %{
5918 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5919 __ li($dst$$Register, 0);
5920 %}
5921 ins_pipe(pipe_class_default);
5922 %}
5923
5924 // Load hi part of compressed oop constant.
5925 instruct loadConN_hi(iRegNdst dst, immN src) %{
5926 effect(DEF dst, USE src);
5927 ins_cost(DEFAULT_COST);
5928
5929 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5930 size(4);
5931 ins_encode %{
5932 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5933 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5934 %}
5935 ins_pipe(pipe_class_default);
5936 %}
5937
5938 // Add lo part of compressed oop constant to already loaded hi part.
5939 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5940 effect(DEF dst, USE src1, USE src2);
5941 ins_cost(DEFAULT_COST);
5942
5943 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5944 size(4);
5945 ins_encode %{
5946 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5947 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5948 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5949 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5950 __ relocate(rspec, 1);
5951 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5952 %}
5953 ins_pipe(pipe_class_default);
5954 %}
5955
5956 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5957 // leaving the upper 32 bits with sign-extension bits.
5958 // This clears these bits: dst = src & 0xFFFFFFFF.
5959 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5960 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5961 effect(DEF dst, USE src);
5962 predicate(false);
5963
5964 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
5965 size(4);
5966 ins_encode %{
5967 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5968 __ clrldi($dst$$Register, $src$$Register, 0x20);
5969 %}
5970 ins_pipe(pipe_class_default);
5971 %}
5972
5973 // Optimize DecodeN for disjoint base.
5974 // Load base of compressed oops into a register
5975 instruct loadBase(iRegLdst dst) %{
5976 effect(DEF dst);
5977
5978 format %{ "LoadConst $dst, heapbase" %}
5979 ins_encode %{
5980 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5981 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
5982 %}
5983 ins_pipe(pipe_class_default);
5984 %}
5985
5986 // Loading ConN must be postalloc expanded so that edges between
5987 // the nodes are safe. They may not interfere with a safepoint.
5988 // GL TODO: This needs three instructions: better put this into the constant pool.
5989 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5990 match(Set dst src);
5991 ins_cost(DEFAULT_COST*2);
5992
5993 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
5994 postalloc_expand %{
5995 MachNode *m1 = new loadConN_hiNode();
5996 MachNode *m2 = new loadConN_loNode();
5997 MachNode *m3 = new clearMs32bNode();
5998 m1->add_req(NULL);
5999 m2->add_req(NULL, m1);
6000 m3->add_req(NULL, m2);
6001 m1->_opnds[0] = op_dst;
6002 m1->_opnds[1] = op_src;
6003 m2->_opnds[0] = op_dst;
6004 m2->_opnds[1] = op_dst;
6005 m2->_opnds[2] = op_src;
6006 m3->_opnds[0] = op_dst;
6007 m3->_opnds[1] = op_dst;
6008 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6009 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6010 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6011 nodes->push(m1);
6012 nodes->push(m2);
6013 nodes->push(m3);
6014 %}
6015 %}
6016
6017 // We have seen a safepoint between the hi and lo parts, and this node was handled
6018 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6019 // not a narrow oop.
6020 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6021 match(Set dst src);
6022 effect(DEF dst, USE src);
6023 ins_cost(DEFAULT_COST);
6024
6025 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6026 size(4);
6027 ins_encode %{
6028 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6029 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6030 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6031 %}
6032 ins_pipe(pipe_class_default);
6033 %}
6034
6035 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6036 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6037 match(Set dst src1);
6038 effect(TEMP src2);
6039 ins_cost(DEFAULT_COST);
6040
6041 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6042 size(4);
6043 ins_encode %{
6044 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6045 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6046 %}
6047 ins_pipe(pipe_class_default);
6048 %}
6049
6050 // This needs a match rule so that build_oop_map knows this is
6051 // not a narrow oop.
6052 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6053 match(Set dst src1);
6054 effect(TEMP src2);
6055 ins_cost(DEFAULT_COST);
6056
6057 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6058 size(4);
6059 ins_encode %{
6060 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6061 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6062 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6063 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6064 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6065
6066 __ relocate(rspec, 1);
6067 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6068 %}
6069 ins_pipe(pipe_class_default);
6070 %}
6071
6072 // Loading ConNKlass must be postalloc expanded so that edges between
6073 // the nodes are safe. They may not interfere with a safepoint.
6074 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6075 match(Set dst src);
6076 ins_cost(DEFAULT_COST*2);
6077
6078 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6079 postalloc_expand %{
6080 // Load high bits into register. Sign extended.
6081 MachNode *m1 = new loadConNKlass_hiNode();
6082 m1->add_req(NULL);
6083 m1->_opnds[0] = op_dst;
6084 m1->_opnds[1] = op_src;
6085 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6086 nodes->push(m1);
6087
6088 MachNode *m2 = m1;
6089 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6090 // Value might be 1-extended. Mask out these bits.
6091 m2 = new loadConNKlass_maskNode();
6092 m2->add_req(NULL, m1);
6093 m2->_opnds[0] = op_dst;
6094 m2->_opnds[1] = op_src;
6095 m2->_opnds[2] = op_dst;
6096 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6097 nodes->push(m2);
6098 }
6099
6100 MachNode *m3 = new loadConNKlass_loNode();
6101 m3->add_req(NULL, m2);
6102 m3->_opnds[0] = op_dst;
6103 m3->_opnds[1] = op_src;
6104 m3->_opnds[2] = op_dst;
6105 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6106 nodes->push(m3);
6107 %}
6108 %}
6109
6110 // 0x1 is used in object initialization (initial object header).
6111 // No constant pool entries required.
6112 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6113 match(Set dst src);
6114
6115 format %{ "LI $dst, $src \t// ptr" %}
6116 size(4);
6117 ins_encode %{
6118 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6119 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6120 %}
6121 ins_pipe(pipe_class_default);
6122 %}
6123
6124 // Expand node for constant pool load: small offset.
6125 // The match rule is needed to generate the correct bottom_type(),
6126 // however this node should never match. The use of predicate is not
6127 // possible since ADLC forbids predicates for chain rules. The higher
6128 // costs do not prevent matching in this case. For that reason the
6129 // operand immP_NM with predicate(false) is used.
6130 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6131 match(Set dst src);
6132 effect(TEMP toc);
6133
6134 ins_num_consts(1);
6135
6136 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6137 size(4);
6138 ins_encode( enc_load_long_constP(dst, src, toc) );
6139 ins_pipe(pipe_class_memory);
6140 %}
6141
6142 // Expand node for constant pool load: large offset.
6143 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6144 effect(DEF dst, USE src, USE toc);
6145 predicate(false);
6146
6147 ins_num_consts(1);
6148 ins_field_const_toc_offset(int);
6149
6150 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6151 size(4);
6152 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6153 ins_pipe(pipe_class_default);
6154 %}
6155
6156 // Expand node for constant pool load: large offset.
6157 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6158 match(Set dst src);
6159 effect(TEMP base);
6160
6161 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6162
6163 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6164 size(4);
6165 ins_encode %{
6166 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6167 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6168 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6169 %}
6170 ins_pipe(pipe_class_memory);
6171 %}
6172
6173 // Load pointer constant from constant table. Expand in case an
6174 // offset > 16 bit is needed.
6175 // Adlc adds toc node MachConstantTableBase.
6176 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6177 match(Set dst src);
6178 ins_cost(MEMORY_REF_COST);
6179
6180 // This rule does not use "expand" because then
6181 // the result type is not known to be an Oop. An ADLC
6182 // enhancement will be needed to make that work - not worth it!
6183
6184 // If this instruction rematerializes, it prolongs the live range
6185 // of the toc node, causing illegal graphs.
6186 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6187 ins_cannot_rematerialize(true);
6188
6189 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6190 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6191 %}
6192
6193 // Expand node for constant pool load: small offset.
6194 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6195 effect(DEF dst, USE src, USE toc);
6196 ins_cost(MEMORY_REF_COST);
6197
6198 ins_num_consts(1);
6199
6200 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6201 size(4);
6202 ins_encode %{
6203 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6204 address float_address = __ float_constant($src$$constant);
6205 if (float_address == NULL) {
6206 ciEnv::current()->record_out_of_memory_failure();
6207 return;
6208 }
6209 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6210 %}
6211 ins_pipe(pipe_class_memory);
6212 %}
6213
6214 // Expand node for constant pool load: large offset.
6215 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6216 effect(DEF dst, USE src, USE toc);
6217 ins_cost(MEMORY_REF_COST);
6218
6219 ins_num_consts(1);
6220
6221 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6222 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6223 "ADDIS $toc, $toc, -offset_hi"%}
6224 size(12);
6225 ins_encode %{
6226 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6227 FloatRegister Rdst = $dst$$FloatRegister;
6228 Register Rtoc = $toc$$Register;
6229 address float_address = __ float_constant($src$$constant);
6230 if (float_address == NULL) {
6231 ciEnv::current()->record_out_of_memory_failure();
6232 return;
6233 }
6234 int offset = __ offset_to_method_toc(float_address);
6235 int hi = (offset + (1<<15))>>16;
6236 int lo = offset - hi * (1<<16);
6237
6238 __ addis(Rtoc, Rtoc, hi);
6239 __ lfs(Rdst, lo, Rtoc);
6240 __ addis(Rtoc, Rtoc, -hi);
6241 %}
6242 ins_pipe(pipe_class_memory);
6243 %}
6244
6245 // Adlc adds toc node MachConstantTableBase.
6246 instruct loadConF_Ex(regF dst, immF src) %{
6247 match(Set dst src);
6248 ins_cost(MEMORY_REF_COST);
6249
6250 // See loadConP.
6251 ins_cannot_rematerialize(true);
6252
6253 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6254 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6255 %}
6256
6257 // Expand node for constant pool load: small offset.
6258 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6259 effect(DEF dst, USE src, USE toc);
6260 ins_cost(MEMORY_REF_COST);
6261
6262 ins_num_consts(1);
6263
6264 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6265 size(4);
6266 ins_encode %{
6267 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6268 address float_address = __ double_constant($src$$constant);
6269 if (float_address == NULL) {
6270 ciEnv::current()->record_out_of_memory_failure();
6271 return;
6272 }
6273 int offset = __ offset_to_method_toc(float_address);
6274 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6275 %}
6276 ins_pipe(pipe_class_memory);
6277 %}
6278
6279 // Expand node for constant pool load: large offset.
6280 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6281 effect(DEF dst, USE src, USE toc);
6282 ins_cost(MEMORY_REF_COST);
6283
6284 ins_num_consts(1);
6285
6286 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6287 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6288 "ADDIS $toc, $toc, -offset_hi" %}
6289 size(12);
6290 ins_encode %{
6291 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6292 FloatRegister Rdst = $dst$$FloatRegister;
6293 Register Rtoc = $toc$$Register;
6294 address float_address = __ double_constant($src$$constant);
6295 if (float_address == NULL) {
6296 ciEnv::current()->record_out_of_memory_failure();
6297 return;
6298 }
6299 int offset = __ offset_to_method_toc(float_address);
6300 int hi = (offset + (1<<15))>>16;
6301 int lo = offset - hi * (1<<16);
6302
6303 __ addis(Rtoc, Rtoc, hi);
6304 __ lfd(Rdst, lo, Rtoc);
6305 __ addis(Rtoc, Rtoc, -hi);
6306 %}
6307 ins_pipe(pipe_class_memory);
6308 %}
6309
6310 // Adlc adds toc node MachConstantTableBase.
6311 instruct loadConD_Ex(regD dst, immD src) %{
6312 match(Set dst src);
6313 ins_cost(MEMORY_REF_COST);
6314
6315 // See loadConP.
6316 ins_cannot_rematerialize(true);
6317
6318 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6319 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6320 %}
6321
6322 // Prefetch instructions.
6323 // Must be safe to execute with invalid address (cannot fault).
6324
6325 // Special prefetch versions which use the dcbz instruction.
6326 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6327 match(PrefetchAllocation (AddP mem src));
6328 predicate(AllocatePrefetchStyle == 3);
6329 ins_cost(MEMORY_REF_COST);
6330
6331 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6332 size(4);
6333 ins_encode %{
6334 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6335 __ dcbz($src$$Register, $mem$$base$$Register);
6336 %}
6337 ins_pipe(pipe_class_memory);
6338 %}
6339
6340 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6341 match(PrefetchAllocation mem);
6342 predicate(AllocatePrefetchStyle == 3);
6343 ins_cost(MEMORY_REF_COST);
6344
6345 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6346 size(4);
6347 ins_encode %{
6348 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6349 __ dcbz($mem$$base$$Register);
6350 %}
6351 ins_pipe(pipe_class_memory);
6352 %}
6353
6354 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6355 match(PrefetchAllocation (AddP mem src));
6356 predicate(AllocatePrefetchStyle != 3);
6357 ins_cost(MEMORY_REF_COST);
6358
6359 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6360 size(4);
6361 ins_encode %{
6362 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6363 __ dcbtst($src$$Register, $mem$$base$$Register);
6364 %}
6365 ins_pipe(pipe_class_memory);
6366 %}
6367
6368 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6369 match(PrefetchAllocation mem);
6370 predicate(AllocatePrefetchStyle != 3);
6371 ins_cost(MEMORY_REF_COST);
6372
6373 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6374 size(4);
6375 ins_encode %{
6376 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6377 __ dcbtst($mem$$base$$Register);
6378 %}
6379 ins_pipe(pipe_class_memory);
6380 %}
6381
6382 //----------Store Instructions-------------------------------------------------
6383
6384 // Store Byte
6385 instruct storeB(memory mem, iRegIsrc src) %{
6386 match(Set mem (StoreB mem src));
6387 ins_cost(MEMORY_REF_COST);
6388
6389 format %{ "STB $src, $mem \t// byte" %}
6390 size(4);
6391 ins_encode %{
6392 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6393 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6394 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6395 %}
6396 ins_pipe(pipe_class_memory);
6397 %}
6398
6399 // Store Char/Short
6400 instruct storeC(memory mem, iRegIsrc src) %{
6401 match(Set mem (StoreC mem src));
6402 ins_cost(MEMORY_REF_COST);
6403
6404 format %{ "STH $src, $mem \t// short" %}
6405 size(4);
6406 ins_encode %{
6407 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6408 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6409 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6410 %}
6411 ins_pipe(pipe_class_memory);
6412 %}
6413
6414 // Store Integer
6415 instruct storeI(memory mem, iRegIsrc src) %{
6416 match(Set mem (StoreI mem src));
6417 ins_cost(MEMORY_REF_COST);
6418
6419 format %{ "STW $src, $mem" %}
6420 size(4);
6421 ins_encode( enc_stw(src, mem) );
6422 ins_pipe(pipe_class_memory);
6423 %}
6424
6425 // ConvL2I + StoreI.
6426 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6427 match(Set mem (StoreI mem (ConvL2I src)));
6428 ins_cost(MEMORY_REF_COST);
6429
6430 format %{ "STW l2i($src), $mem" %}
6431 size(4);
6432 ins_encode( enc_stw(src, mem) );
6433 ins_pipe(pipe_class_memory);
6434 %}
6435
6436 // Store Long
6437 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6438 match(Set mem (StoreL mem src));
6439 ins_cost(MEMORY_REF_COST);
6440
6441 format %{ "STD $src, $mem \t// long" %}
6442 size(4);
6443 ins_encode( enc_std(src, mem) );
6444 ins_pipe(pipe_class_memory);
6445 %}
6446
6447 // Store super word nodes.
6448
6449 // Store Aligned Packed Byte long register to memory
6450 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6451 predicate(n->as_StoreVector()->memory_size() == 8);
6452 match(Set mem (StoreVector mem src));
6453 ins_cost(MEMORY_REF_COST);
6454
6455 format %{ "STD $mem, $src \t// packed8B" %}
6456 size(4);
6457 ins_encode( enc_std(src, mem) );
6458 ins_pipe(pipe_class_memory);
6459 %}
6460
6461 // Store Compressed Oop
6462 instruct storeN(memory dst, iRegN_P2N src) %{
6463 match(Set dst (StoreN dst src));
6464 ins_cost(MEMORY_REF_COST);
6465
6466 format %{ "STW $src, $dst \t// compressed oop" %}
6467 size(4);
6468 ins_encode( enc_stw(src, dst) );
6469 ins_pipe(pipe_class_memory);
6470 %}
6471
6472 // Store Compressed KLass
6473 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6474 match(Set dst (StoreNKlass dst src));
6475 ins_cost(MEMORY_REF_COST);
6476
6477 format %{ "STW $src, $dst \t// compressed klass" %}
6478 size(4);
6479 ins_encode( enc_stw(src, dst) );
6480 ins_pipe(pipe_class_memory);
6481 %}
6482
6483 // Store Pointer
6484 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6485 match(Set dst (StoreP dst src));
6486 ins_cost(MEMORY_REF_COST);
6487
6488 format %{ "STD $src, $dst \t// ptr" %}
6489 size(4);
6490 ins_encode( enc_std(src, dst) );
6491 ins_pipe(pipe_class_memory);
6492 %}
6493
6494 // Store Float
6495 instruct storeF(memory mem, regF src) %{
6496 match(Set mem (StoreF mem src));
6497 ins_cost(MEMORY_REF_COST);
6498
6499 format %{ "STFS $src, $mem" %}
6500 size(4);
6501 ins_encode( enc_stfs(src, mem) );
6502 ins_pipe(pipe_class_memory);
6503 %}
6504
6505 // Store Double
6506 instruct storeD(memory mem, regD src) %{
6507 match(Set mem (StoreD mem src));
6508 ins_cost(MEMORY_REF_COST);
6509
6510 format %{ "STFD $src, $mem" %}
6511 size(4);
6512 ins_encode( enc_stfd(src, mem) );
6513 ins_pipe(pipe_class_memory);
6514 %}
6515
6516 //----------Store Instructions With Zeros--------------------------------------
6517
6518 // Card-mark for CMS garbage collection.
6519 // This cardmark does an optimization so that it must not always
6520 // do a releasing store. For this, it gets the address of
6521 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6522 // (Using releaseFieldAddr in the match rule is a hack.)
6523 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6524 match(Set mem (StoreCM mem releaseFieldAddr));
6525 effect(TEMP crx);
6526 predicate(false);
6527 ins_cost(MEMORY_REF_COST);
6528
6529 // See loadConP.
6530 ins_cannot_rematerialize(true);
6531
6532 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6533 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6534 ins_pipe(pipe_class_memory);
6535 %}
6536
6537 // Card-mark for CMS garbage collection.
6538 // This cardmark does an optimization so that it must not always
6539 // do a releasing store. For this, it needs the constant address of
6540 // CMSCollectorCardTableModRefBSExt::_requires_release.
6541 // This constant address is split off here by expand so we can use
6542 // adlc / matcher functionality to load it from the constant section.
6543 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6544 match(Set mem (StoreCM mem zero));
6545 predicate(UseConcMarkSweepGC);
6546
6547 expand %{
6548 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6549 iRegLdst releaseFieldAddress;
6550 flagsReg crx;
6551 loadConL_Ex(releaseFieldAddress, baseImm);
6552 storeCM_CMS(mem, releaseFieldAddress, crx);
6553 %}
6554 %}
6555
6556 instruct storeCM_G1(memory mem, immI_0 zero) %{
6557 match(Set mem (StoreCM mem zero));
6558 predicate(UseG1GC);
6559 ins_cost(MEMORY_REF_COST);
6560
6561 ins_cannot_rematerialize(true);
6562
6563 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6564 size(8);
6565 ins_encode %{
6566 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6567 __ li(R0, 0);
6568 //__ release(); // G1: oops are allowed to get visible after dirty marking
6569 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6570 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6571 %}
6572 ins_pipe(pipe_class_memory);
6573 %}
6574
6575 // Convert oop pointer into compressed form.
6576
6577 // Nodes for postalloc expand.
6578
6579 // Shift node for expand.
6580 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6581 // The match rule is needed to make it a 'MachTypeNode'!
6582 match(Set dst (EncodeP src));
6583 predicate(false);
6584
6585 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6586 size(4);
6587 ins_encode %{
6588 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6589 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6590 %}
6591 ins_pipe(pipe_class_default);
6592 %}
6593
6594 // Add node for expand.
6595 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6596 // The match rule is needed to make it a 'MachTypeNode'!
6597 match(Set dst (EncodeP src));
6598 predicate(false);
6599
6600 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6601 ins_encode %{
6602 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6603 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6604 %}
6605 ins_pipe(pipe_class_default);
6606 %}
6607
6608 // Conditional sub base.
6609 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6610 // The match rule is needed to make it a 'MachTypeNode'!
6611 match(Set dst (EncodeP (Binary crx src1)));
6612 predicate(false);
6613
6614 format %{ "BEQ $crx, done\n\t"
6615 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6616 "done:" %}
6617 ins_encode %{
6618 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6619 Label done;
6620 __ beq($crx$$CondRegister, done);
6621 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6622 __ bind(done);
6623 %}
6624 ins_pipe(pipe_class_default);
6625 %}
6626
6627 // Power 7 can use isel instruction
6628 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6629 // The match rule is needed to make it a 'MachTypeNode'!
6630 match(Set dst (EncodeP (Binary crx src1)));
6631 predicate(false);
6632
6633 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6634 size(4);
6635 ins_encode %{
6636 // This is a Power7 instruction for which no machine description exists.
6637 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6638 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6639 %}
6640 ins_pipe(pipe_class_default);
6641 %}
6642
6643 // Disjoint narrow oop base.
6644 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6645 match(Set dst (EncodeP src));
6646 predicate(Universe::narrow_oop_base_disjoint());
6647
6648 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6649 size(4);
6650 ins_encode %{
6651 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6652 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6653 %}
6654 ins_pipe(pipe_class_default);
6655 %}
6656
6657 // shift != 0, base != 0
6658 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6659 match(Set dst (EncodeP src));
6660 effect(TEMP crx);
6661 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6662 Universe::narrow_oop_shift() != 0 &&
6663 Universe::narrow_oop_base_overlaps());
6664
6665 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6666 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6667 %}
6668
6669 // shift != 0, base != 0
6670 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6671 match(Set dst (EncodeP src));
6672 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6673 Universe::narrow_oop_shift() != 0 &&
6674 Universe::narrow_oop_base_overlaps());
6675
6676 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6677 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6678 %}
6679
6680 // shift != 0, base == 0
6681 // TODO: This is the same as encodeP_shift. Merge!
6682 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6683 match(Set dst (EncodeP src));
6684 predicate(Universe::narrow_oop_shift() != 0 &&
6685 Universe::narrow_oop_base() ==0);
6686
6687 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6688 size(4);
6689 ins_encode %{
6690 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6691 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6692 %}
6693 ins_pipe(pipe_class_default);
6694 %}
6695
6696 // Compressed OOPs with narrow_oop_shift == 0.
6697 // shift == 0, base == 0
6698 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6699 match(Set dst (EncodeP src));
6700 predicate(Universe::narrow_oop_shift() == 0);
6701
6702 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6703 // variable size, 0 or 4.
6704 ins_encode %{
6705 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6706 __ mr_if_needed($dst$$Register, $src$$Register);
6707 %}
6708 ins_pipe(pipe_class_default);
6709 %}
6710
6711 // Decode nodes.
6712
6713 // Shift node for expand.
6714 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6715 // The match rule is needed to make it a 'MachTypeNode'!
6716 match(Set dst (DecodeN src));
6717 predicate(false);
6718
6719 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6720 size(4);
6721 ins_encode %{
6722 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6723 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6724 %}
6725 ins_pipe(pipe_class_default);
6726 %}
6727
6728 // Add node for expand.
6729 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6730 // The match rule is needed to make it a 'MachTypeNode'!
6731 match(Set dst (DecodeN src));
6732 predicate(false);
6733
6734 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %}
6735 ins_encode %{
6736 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6737 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6738 %}
6739 ins_pipe(pipe_class_default);
6740 %}
6741
6742 // conditianal add base for expand
6743 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6744 // The match rule is needed to make it a 'MachTypeNode'!
6745 // NOTICE that the rule is nonsense - we just have to make sure that:
6746 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6747 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6748 match(Set dst (DecodeN (Binary crx src)));
6749 predicate(false);
6750
6751 format %{ "BEQ $crx, done\n\t"
6752 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6753 "done:" %}
6754 ins_encode %{
6755 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6756 Label done;
6757 __ beq($crx$$CondRegister, done);
6758 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6759 __ bind(done);
6760 %}
6761 ins_pipe(pipe_class_default);
6762 %}
6763
6764 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6765 // The match rule is needed to make it a 'MachTypeNode'!
6766 // NOTICE that the rule is nonsense - we just have to make sure that:
6767 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6768 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6769 match(Set dst (DecodeN (Binary crx src1)));
6770 predicate(false);
6771
6772 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6773 size(4);
6774 ins_encode %{
6775 // This is a Power7 instruction for which no machine description exists.
6776 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6777 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6778 %}
6779 ins_pipe(pipe_class_default);
6780 %}
6781
6782 // shift != 0, base != 0
6783 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6784 match(Set dst (DecodeN src));
6785 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6786 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6787 Universe::narrow_oop_shift() != 0 &&
6788 Universe::narrow_oop_base() != 0);
6789 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6790 effect(TEMP crx);
6791
6792 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6793 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6794 %}
6795
6796 // shift != 0, base == 0
6797 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6798 match(Set dst (DecodeN src));
6799 predicate(Universe::narrow_oop_shift() != 0 &&
6800 Universe::narrow_oop_base() == 0);
6801
6802 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6803 size(4);
6804 ins_encode %{
6805 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6806 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6807 %}
6808 ins_pipe(pipe_class_default);
6809 %}
6810
6811 // Optimize DecodeN for disjoint base.
6812 // Shift narrow oop and or it into register that already contains the heap base.
6813 // Base == dst must hold, and is assured by construction in postaloc_expand.
6814 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6815 match(Set dst (DecodeN src));
6816 effect(TEMP base);
6817 predicate(false);
6818
6819 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6820 size(4);
6821 ins_encode %{
6822 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6823 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6824 %}
6825 ins_pipe(pipe_class_default);
6826 %}
6827
6828 // Optimize DecodeN for disjoint base.
6829 // This node requires only one cycle on the critical path.
6830 // We must postalloc_expand as we can not express use_def effects where
6831 // the used register is L and the def'ed register P.
6832 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6833 match(Set dst (DecodeN src));
6834 effect(TEMP_DEF dst);
6835 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6836 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6837 Universe::narrow_oop_base_disjoint());
6838 ins_cost(DEFAULT_COST);
6839
6840 format %{ "MOV $dst, heapbase \t\n"
6841 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6842 postalloc_expand %{
6843 loadBaseNode *n1 = new loadBaseNode();
6844 n1->add_req(NULL);
6845 n1->_opnds[0] = op_dst;
6846
6847 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6848 n2->add_req(n_region, n_src, n1);
6849 n2->_opnds[0] = op_dst;
6850 n2->_opnds[1] = op_src;
6851 n2->_opnds[2] = op_dst;
6852 n2->_bottom_type = _bottom_type;
6853
6854 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6855 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6856
6857 nodes->push(n1);
6858 nodes->push(n2);
6859 %}
6860 %}
6861
6862 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6863 match(Set dst (DecodeN src));
6864 effect(TEMP_DEF dst, TEMP crx);
6865 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6866 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6867 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6868 ins_cost(3 * DEFAULT_COST);
6869
6870 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %}
6871 postalloc_expand %{
6872 loadBaseNode *n1 = new loadBaseNode();
6873 n1->add_req(NULL);
6874 n1->_opnds[0] = op_dst;
6875
6876 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
6877 n_compare->add_req(n_region, n_src);
6878 n_compare->_opnds[0] = op_crx;
6879 n_compare->_opnds[1] = op_src;
6880 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6881
6882 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6883 n2->add_req(n_region, n_src, n1);
6884 n2->_opnds[0] = op_dst;
6885 n2->_opnds[1] = op_src;
6886 n2->_opnds[2] = op_dst;
6887 n2->_bottom_type = _bottom_type;
6888
6889 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6890 n_cond_set->add_req(n_region, n_compare, n2);
6891 n_cond_set->_opnds[0] = op_dst;
6892 n_cond_set->_opnds[1] = op_crx;
6893 n_cond_set->_opnds[2] = op_dst;
6894 n_cond_set->_bottom_type = _bottom_type;
6895
6896 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6897 ra_->set_oop(n_cond_set, true);
6898
6899 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6900 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6901 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6902 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6903
6904 nodes->push(n1);
6905 nodes->push(n_compare);
6906 nodes->push(n2);
6907 nodes->push(n_cond_set);
6908 %}
6909 %}
6910
6911 // src != 0, shift != 0, base != 0
6912 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6913 match(Set dst (DecodeN src));
6914 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6915 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6916 Universe::narrow_oop_shift() != 0 &&
6917 Universe::narrow_oop_base() != 0);
6918 ins_cost(2 * DEFAULT_COST);
6919
6920 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6921 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6922 %}
6923
6924 // Compressed OOPs with narrow_oop_shift == 0.
6925 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6926 match(Set dst (DecodeN src));
6927 predicate(Universe::narrow_oop_shift() == 0);
6928 ins_cost(DEFAULT_COST);
6929
6930 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6931 // variable size, 0 or 4.
6932 ins_encode %{
6933 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6934 __ mr_if_needed($dst$$Register, $src$$Register);
6935 %}
6936 ins_pipe(pipe_class_default);
6937 %}
6938
6939 // Convert compressed oop into int for vectors alignment masking.
6940 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6941 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6942 predicate(Universe::narrow_oop_shift() == 0);
6943 ins_cost(DEFAULT_COST);
6944
6945 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6946 // variable size, 0 or 4.
6947 ins_encode %{
6948 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6949 __ mr_if_needed($dst$$Register, $src$$Register);
6950 %}
6951 ins_pipe(pipe_class_default);
6952 %}
6953
6954 // Convert klass pointer into compressed form.
6955
6956 // Nodes for postalloc expand.
6957
6958 // Shift node for expand.
6959 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6960 // The match rule is needed to make it a 'MachTypeNode'!
6961 match(Set dst (EncodePKlass src));
6962 predicate(false);
6963
6964 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6965 size(4);
6966 ins_encode %{
6967 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6968 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6969 %}
6970 ins_pipe(pipe_class_default);
6971 %}
6972
6973 // Add node for expand.
6974 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6975 // The match rule is needed to make it a 'MachTypeNode'!
6976 match(Set dst (EncodePKlass (Binary base src)));
6977 predicate(false);
6978
6979 format %{ "SUB $dst, $base, $src \t// encode" %}
6980 size(4);
6981 ins_encode %{
6982 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6983 __ subf($dst$$Register, $base$$Register, $src$$Register);
6984 %}
6985 ins_pipe(pipe_class_default);
6986 %}
6987
6988 // Disjoint narrow oop base.
6989 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
6990 match(Set dst (EncodePKlass src));
6991 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6992
6993 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6994 size(4);
6995 ins_encode %{
6996 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6997 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
6998 %}
6999 ins_pipe(pipe_class_default);
7000 %}
7001
7002 // shift != 0, base != 0
7003 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7004 match(Set dst (EncodePKlass (Binary base src)));
7005 predicate(false);
7006
7007 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7008 postalloc_expand %{
7009 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7010 n1->add_req(n_region, n_base, n_src);
7011 n1->_opnds[0] = op_dst;
7012 n1->_opnds[1] = op_base;
7013 n1->_opnds[2] = op_src;
7014 n1->_bottom_type = _bottom_type;
7015
7016 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7017 n2->add_req(n_region, n1);
7018 n2->_opnds[0] = op_dst;
7019 n2->_opnds[1] = op_dst;
7020 n2->_bottom_type = _bottom_type;
7021 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7022 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7023
7024 nodes->push(n1);
7025 nodes->push(n2);
7026 %}
7027 %}
7028
7029 // shift != 0, base != 0
7030 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7031 match(Set dst (EncodePKlass src));
7032 //predicate(Universe::narrow_klass_shift() != 0 &&
7033 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7034
7035 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7036 ins_cost(DEFAULT_COST*2); // Don't count constant.
7037 expand %{
7038 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7039 iRegLdst base;
7040 loadConL_Ex(base, baseImm);
7041 encodePKlass_not_null_Ex(dst, base, src);
7042 %}
7043 %}
7044
7045 // Decode nodes.
7046
7047 // Shift node for expand.
7048 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7049 // The match rule is needed to make it a 'MachTypeNode'!
7050 match(Set dst (DecodeNKlass src));
7051 predicate(false);
7052
7053 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7054 size(4);
7055 ins_encode %{
7056 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7057 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7058 %}
7059 ins_pipe(pipe_class_default);
7060 %}
7061
7062 // Add node for expand.
7063
7064 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7065 // The match rule is needed to make it a 'MachTypeNode'!
7066 match(Set dst (DecodeNKlass (Binary base src)));
7067 predicate(false);
7068
7069 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7070 size(4);
7071 ins_encode %{
7072 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7073 __ add($dst$$Register, $base$$Register, $src$$Register);
7074 %}
7075 ins_pipe(pipe_class_default);
7076 %}
7077
7078 // src != 0, shift != 0, base != 0
7079 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7080 match(Set dst (DecodeNKlass (Binary base src)));
7081 //effect(kill src); // We need a register for the immediate result after shifting.
7082 predicate(false);
7083
7084 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7085 postalloc_expand %{
7086 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7087 n1->add_req(n_region, n_base, n_src);
7088 n1->_opnds[0] = op_dst;
7089 n1->_opnds[1] = op_base;
7090 n1->_opnds[2] = op_src;
7091 n1->_bottom_type = _bottom_type;
7092
7093 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7094 n2->add_req(n_region, n1);
7095 n2->_opnds[0] = op_dst;
7096 n2->_opnds[1] = op_dst;
7097 n2->_bottom_type = _bottom_type;
7098
7099 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7100 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7101
7102 nodes->push(n1);
7103 nodes->push(n2);
7104 %}
7105 %}
7106
7107 // src != 0, shift != 0, base != 0
7108 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7109 match(Set dst (DecodeNKlass src));
7110 // predicate(Universe::narrow_klass_shift() != 0 &&
7111 // Universe::narrow_klass_base() != 0);
7112
7113 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7114
7115 ins_cost(DEFAULT_COST*2); // Don't count constant.
7116 expand %{
7117 // We add first, then we shift. Like this, we can get along with one register less.
7118 // But we have to load the base pre-shifted.
7119 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7120 iRegLdst base;
7121 loadConL_Ex(base, baseImm);
7122 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7123 %}
7124 %}
7125
7126 //----------MemBar Instructions-----------------------------------------------
7127 // Memory barrier flavors
7128
7129 instruct membar_acquire() %{
7130 match(LoadFence);
7131 ins_cost(4*MEMORY_REF_COST);
7132
7133 format %{ "MEMBAR-acquire" %}
7134 size(4);
7135 ins_encode %{
7136 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7137 __ acquire();
7138 %}
7139 ins_pipe(pipe_class_default);
7140 %}
7141
7142 instruct unnecessary_membar_acquire() %{
7143 match(MemBarAcquire);
7144 ins_cost(0);
7145
7146 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7147 size(0);
7148 ins_encode( /*empty*/ );
7149 ins_pipe(pipe_class_default);
7150 %}
7151
7152 instruct membar_acquire_lock() %{
7153 match(MemBarAcquireLock);
7154 ins_cost(0);
7155
7156 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7157 size(0);
7158 ins_encode( /*empty*/ );
7159 ins_pipe(pipe_class_default);
7160 %}
7161
7162 instruct membar_release() %{
7163 match(MemBarRelease);
7164 match(StoreFence);
7165 ins_cost(4*MEMORY_REF_COST);
7166
7167 format %{ "MEMBAR-release" %}
7168 size(4);
7169 ins_encode %{
7170 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7171 __ release();
7172 %}
7173 ins_pipe(pipe_class_default);
7174 %}
7175
7176 instruct membar_storestore() %{
7177 match(MemBarStoreStore);
7178 ins_cost(4*MEMORY_REF_COST);
7179
7180 format %{ "MEMBAR-store-store" %}
7181 size(4);
7182 ins_encode %{
7183 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7184 __ membar(Assembler::StoreStore);
7185 %}
7186 ins_pipe(pipe_class_default);
7187 %}
7188
7189 instruct membar_release_lock() %{
7190 match(MemBarReleaseLock);
7191 ins_cost(0);
7192
7193 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7194 size(0);
7195 ins_encode( /*empty*/ );
7196 ins_pipe(pipe_class_default);
7197 %}
7198
7199 instruct membar_volatile() %{
7200 match(MemBarVolatile);
7201 ins_cost(4*MEMORY_REF_COST);
7202
7203 format %{ "MEMBAR-volatile" %}
7204 size(4);
7205 ins_encode %{
7206 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7207 __ fence();
7208 %}
7209 ins_pipe(pipe_class_default);
7210 %}
7211
7212 // This optimization is wrong on PPC. The following pattern is not supported:
7213 // MemBarVolatile
7214 // ^ ^
7215 // | |
7216 // CtrlProj MemProj
7217 // ^ ^
7218 // | |
7219 // | Load
7220 // |
7221 // MemBarVolatile
7222 //
7223 // The first MemBarVolatile could get optimized out! According to
7224 // Vladimir, this pattern can not occur on Oracle platforms.
7225 // However, it does occur on PPC64 (because of membars in
7226 // inline_unsafe_load_store).
7227 //
7228 // Add this node again if we found a good solution for inline_unsafe_load_store().
7229 // Don't forget to look at the implementation of post_store_load_barrier again,
7230 // we did other fixes in that method.
7231 //instruct unnecessary_membar_volatile() %{
7232 // match(MemBarVolatile);
7233 // predicate(Matcher::post_store_load_barrier(n));
7234 // ins_cost(0);
7235 //
7236 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7237 // size(0);
7238 // ins_encode( /*empty*/ );
7239 // ins_pipe(pipe_class_default);
7240 //%}
7241
7242 instruct membar_CPUOrder() %{
7243 match(MemBarCPUOrder);
7244 ins_cost(0);
7245
7246 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7247 size(0);
7248 ins_encode( /*empty*/ );
7249 ins_pipe(pipe_class_default);
7250 %}
7251
7252 //----------Conditional Move---------------------------------------------------
7253
7254 // Cmove using isel.
7255 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7256 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7257 predicate(VM_Version::has_isel());
7258 ins_cost(DEFAULT_COST);
7259
7260 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7261 size(4);
7262 ins_encode %{
7263 // This is a Power7 instruction for which no machine description
7264 // exists. Anyways, the scheduler should be off on Power7.
7265 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7266 int cc = $cmp$$cmpcode;
7267 __ isel($dst$$Register, $crx$$CondRegister,
7268 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7269 %}
7270 ins_pipe(pipe_class_default);
7271 %}
7272
7273 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7274 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7275 predicate(!VM_Version::has_isel());
7276 ins_cost(DEFAULT_COST+BRANCH_COST);
7277
7278 ins_variable_size_depending_on_alignment(true);
7279
7280 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7281 // Worst case is branch + move + stop, no stop without scheduler
7282 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7283 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7284 ins_pipe(pipe_class_default);
7285 %}
7286
7287 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7288 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7289 ins_cost(DEFAULT_COST+BRANCH_COST);
7290
7291 ins_variable_size_depending_on_alignment(true);
7292
7293 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7294 // Worst case is branch + move + stop, no stop without scheduler
7295 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7296 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7297 ins_pipe(pipe_class_default);
7298 %}
7299
7300 // Cmove using isel.
7301 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7302 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7303 predicate(VM_Version::has_isel());
7304 ins_cost(DEFAULT_COST);
7305
7306 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7307 size(4);
7308 ins_encode %{
7309 // This is a Power7 instruction for which no machine description
7310 // exists. Anyways, the scheduler should be off on Power7.
7311 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7312 int cc = $cmp$$cmpcode;
7313 __ isel($dst$$Register, $crx$$CondRegister,
7314 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7315 %}
7316 ins_pipe(pipe_class_default);
7317 %}
7318
7319 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7320 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7321 predicate(!VM_Version::has_isel());
7322 ins_cost(DEFAULT_COST+BRANCH_COST);
7323
7324 ins_variable_size_depending_on_alignment(true);
7325
7326 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7327 // Worst case is branch + move + stop, no stop without scheduler.
7328 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7329 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7330 ins_pipe(pipe_class_default);
7331 %}
7332
7333 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7334 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7335 ins_cost(DEFAULT_COST+BRANCH_COST);
7336
7337 ins_variable_size_depending_on_alignment(true);
7338
7339 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7340 // Worst case is branch + move + stop, no stop without scheduler.
7341 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7342 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7343 ins_pipe(pipe_class_default);
7344 %}
7345
7346 // Cmove using isel.
7347 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7348 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7349 predicate(VM_Version::has_isel());
7350 ins_cost(DEFAULT_COST);
7351
7352 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7353 size(4);
7354 ins_encode %{
7355 // This is a Power7 instruction for which no machine description
7356 // exists. Anyways, the scheduler should be off on Power7.
7357 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7358 int cc = $cmp$$cmpcode;
7359 __ isel($dst$$Register, $crx$$CondRegister,
7360 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7361 %}
7362 ins_pipe(pipe_class_default);
7363 %}
7364
7365 // Conditional move for RegN. Only cmov(reg, reg).
7366 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7367 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7368 predicate(!VM_Version::has_isel());
7369 ins_cost(DEFAULT_COST+BRANCH_COST);
7370
7371 ins_variable_size_depending_on_alignment(true);
7372
7373 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7374 // Worst case is branch + move + stop, no stop without scheduler.
7375 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7376 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7377 ins_pipe(pipe_class_default);
7378 %}
7379
7380 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7381 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7382 ins_cost(DEFAULT_COST+BRANCH_COST);
7383
7384 ins_variable_size_depending_on_alignment(true);
7385
7386 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7387 // Worst case is branch + move + stop, no stop without scheduler.
7388 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7389 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7390 ins_pipe(pipe_class_default);
7391 %}
7392
7393 // Cmove using isel.
7394 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7395 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7396 predicate(VM_Version::has_isel());
7397 ins_cost(DEFAULT_COST);
7398
7399 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7400 size(4);
7401 ins_encode %{
7402 // This is a Power7 instruction for which no machine description
7403 // exists. Anyways, the scheduler should be off on Power7.
7404 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7405 int cc = $cmp$$cmpcode;
7406 __ isel($dst$$Register, $crx$$CondRegister,
7407 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7408 %}
7409 ins_pipe(pipe_class_default);
7410 %}
7411
7412 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7413 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7414 predicate(!VM_Version::has_isel());
7415 ins_cost(DEFAULT_COST+BRANCH_COST);
7416
7417 ins_variable_size_depending_on_alignment(true);
7418
7419 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7420 // Worst case is branch + move + stop, no stop without scheduler.
7421 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7422 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7423 ins_pipe(pipe_class_default);
7424 %}
7425
7426 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7427 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7428 ins_cost(DEFAULT_COST+BRANCH_COST);
7429
7430 ins_variable_size_depending_on_alignment(true);
7431
7432 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7433 // Worst case is branch + move + stop, no stop without scheduler.
7434 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7435 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7436 ins_pipe(pipe_class_default);
7437 %}
7438
7439 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7440 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7441 ins_cost(DEFAULT_COST+BRANCH_COST);
7442
7443 ins_variable_size_depending_on_alignment(true);
7444
7445 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7446 // Worst case is branch + move + stop, no stop without scheduler.
7447 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7448 ins_encode %{
7449 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7450 Label done;
7451 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7452 // Branch if not (cmp crx).
7453 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7454 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7455 // TODO PPC port __ endgroup_if_needed(_size == 12);
7456 __ bind(done);
7457 %}
7458 ins_pipe(pipe_class_default);
7459 %}
7460
7461 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7462 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7463 ins_cost(DEFAULT_COST+BRANCH_COST);
7464
7465 ins_variable_size_depending_on_alignment(true);
7466
7467 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7468 // Worst case is branch + move + stop, no stop without scheduler.
7469 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7470 ins_encode %{
7471 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7472 Label done;
7473 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7474 // Branch if not (cmp crx).
7475 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7476 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7477 // TODO PPC port __ endgroup_if_needed(_size == 12);
7478 __ bind(done);
7479 %}
7480 ins_pipe(pipe_class_default);
7481 %}
7482
7483 //----------Conditional_store--------------------------------------------------
7484 // Conditional-store of the updated heap-top.
7485 // Used during allocation of the shared heap.
7486 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7487
7488 // As compareAndSwapL, but return flag register instead of boolean value in
7489 // int register.
7490 // Used by sun/misc/AtomicLongCSImpl.java.
7491 // Mem_ptr must be a memory operand, else this node does not get
7492 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7493 // can be rematerialized which leads to errors.
7494 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7495 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7496 effect(TEMP cr0);
7497 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7498 ins_encode %{
7499 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7500 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7501 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7502 noreg, NULL, true);
7503 %}
7504 ins_pipe(pipe_class_default);
7505 %}
7506
7507 // As compareAndSwapP, but return flag register instead of boolean value in
7508 // int register.
7509 // This instruction is matched if UseTLAB is off.
7510 // Mem_ptr must be a memory operand, else this node does not get
7511 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7512 // can be rematerialized which leads to errors.
7513 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7514 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7515 ins_cost(2*MEMORY_REF_COST);
7516
7517 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7518 ins_encode %{
7519 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7520 __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7521 %}
7522 ins_pipe(pipe_class_memory);
7523 %}
7524
7525 // Implement LoadPLocked. Must be ordered against changes of the memory location
7526 // by storePConditional.
7527 // Don't know whether this is ever used.
7528 instruct loadPLocked(iRegPdst dst, memory mem) %{
7529 match(Set dst (LoadPLocked mem));
7530 ins_cost(2*MEMORY_REF_COST);
7531
7532 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %}
7533 size(4);
7534 ins_encode %{
7535 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7536 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7537 %}
7538 ins_pipe(pipe_class_memory);
7539 %}
7540
7541 //----------Compare-And-Swap---------------------------------------------------
7542
7543 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7544 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7545 // matched.
7546
7547 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7548 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7549 effect(TEMP cr0);
7550 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7551 // Variable size: instruction count smaller if regs are disjoint.
7552 ins_encode %{
7553 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7554 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7555 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7556 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7557 $res$$Register, true);
7558 %}
7559 ins_pipe(pipe_class_default);
7560 %}
7561
7562 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7563 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7564 effect(TEMP cr0);
7565 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7566 // Variable size: instruction count smaller if regs are disjoint.
7567 ins_encode %{
7568 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7569 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7570 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7571 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7572 $res$$Register, true);
7573 %}
7574 ins_pipe(pipe_class_default);
7575 %}
7576
7577 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7578 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7579 effect(TEMP cr0);
7580 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7581 // Variable size: instruction count smaller if regs are disjoint.
7582 ins_encode %{
7583 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7584 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7585 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7586 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7587 $res$$Register, NULL, true);
7588 %}
7589 ins_pipe(pipe_class_default);
7590 %}
7591
7592 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7593 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7594 effect(TEMP cr0);
7595 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7596 // Variable size: instruction count smaller if regs are disjoint.
7597 ins_encode %{
7598 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7599 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7600 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7601 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7602 $res$$Register, NULL, true);
7603 %}
7604 ins_pipe(pipe_class_default);
7605 %}
7606
7607 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7608 match(Set res (GetAndAddI mem_ptr src));
7609 effect(TEMP cr0);
7610 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7611 // Variable size: instruction count smaller if regs are disjoint.
7612 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7613 ins_pipe(pipe_class_default);
7614 %}
7615
7616 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7617 match(Set res (GetAndAddL mem_ptr src));
7618 effect(TEMP cr0);
7619 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7620 // Variable size: instruction count smaller if regs are disjoint.
7621 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7622 ins_pipe(pipe_class_default);
7623 %}
7624
7625 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7626 match(Set res (GetAndSetI mem_ptr src));
7627 effect(TEMP cr0);
7628 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7629 // Variable size: instruction count smaller if regs are disjoint.
7630 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7631 ins_pipe(pipe_class_default);
7632 %}
7633
7634 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7635 match(Set res (GetAndSetL mem_ptr src));
7636 effect(TEMP cr0);
7637 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7638 // Variable size: instruction count smaller if regs are disjoint.
7639 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7640 ins_pipe(pipe_class_default);
7641 %}
7642
7643 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7644 match(Set res (GetAndSetP mem_ptr src));
7645 effect(TEMP cr0);
7646 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7647 // Variable size: instruction count smaller if regs are disjoint.
7648 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7649 ins_pipe(pipe_class_default);
7650 %}
7651
7652 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7653 match(Set res (GetAndSetN mem_ptr src));
7654 effect(TEMP cr0);
7655 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7656 // Variable size: instruction count smaller if regs are disjoint.
7657 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7658 ins_pipe(pipe_class_default);
7659 %}
7660
7661 //----------Arithmetic Instructions--------------------------------------------
7662 // Addition Instructions
7663
7664 // Register Addition
7665 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7666 match(Set dst (AddI src1 src2));
7667 format %{ "ADD $dst, $src1, $src2" %}
7668 size(4);
7669 ins_encode %{
7670 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7671 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7672 %}
7673 ins_pipe(pipe_class_default);
7674 %}
7675
7676 // Expand does not work with above instruct. (??)
7677 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7678 // no match-rule
7679 effect(DEF dst, USE src1, USE src2);
7680 format %{ "ADD $dst, $src1, $src2" %}
7681 size(4);
7682 ins_encode %{
7683 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7684 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7685 %}
7686 ins_pipe(pipe_class_default);
7687 %}
7688
7689 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7690 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7691 ins_cost(DEFAULT_COST*3);
7692
7693 expand %{
7694 // FIXME: we should do this in the ideal world.
7695 iRegIdst tmp1;
7696 iRegIdst tmp2;
7697 addI_reg_reg(tmp1, src1, src2);
7698 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7699 addI_reg_reg(dst, tmp1, tmp2);
7700 %}
7701 %}
7702
7703 // Immediate Addition
7704 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7705 match(Set dst (AddI src1 src2));
7706 format %{ "ADDI $dst, $src1, $src2" %}
7707 size(4);
7708 ins_encode %{
7709 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7710 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7711 %}
7712 ins_pipe(pipe_class_default);
7713 %}
7714
7715 // Immediate Addition with 16-bit shifted operand
7716 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7717 match(Set dst (AddI src1 src2));
7718 format %{ "ADDIS $dst, $src1, $src2" %}
7719 size(4);
7720 ins_encode %{
7721 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7722 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7723 %}
7724 ins_pipe(pipe_class_default);
7725 %}
7726
7727 // Long Addition
7728 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7729 match(Set dst (AddL src1 src2));
7730 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7731 size(4);
7732 ins_encode %{
7733 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7734 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7735 %}
7736 ins_pipe(pipe_class_default);
7737 %}
7738
7739 // Expand does not work with above instruct. (??)
7740 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7741 // no match-rule
7742 effect(DEF dst, USE src1, USE src2);
7743 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7744 size(4);
7745 ins_encode %{
7746 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7747 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7748 %}
7749 ins_pipe(pipe_class_default);
7750 %}
7751
7752 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7753 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7754 ins_cost(DEFAULT_COST*3);
7755
7756 expand %{
7757 // FIXME: we should do this in the ideal world.
7758 iRegLdst tmp1;
7759 iRegLdst tmp2;
7760 addL_reg_reg(tmp1, src1, src2);
7761 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7762 addL_reg_reg(dst, tmp1, tmp2);
7763 %}
7764 %}
7765
7766 // AddL + ConvL2I.
7767 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7768 match(Set dst (ConvL2I (AddL src1 src2)));
7769
7770 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7771 size(4);
7772 ins_encode %{
7773 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7774 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7775 %}
7776 ins_pipe(pipe_class_default);
7777 %}
7778
7779 // No constant pool entries required.
7780 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7781 match(Set dst (AddL src1 src2));
7782
7783 format %{ "ADDI $dst, $src1, $src2" %}
7784 size(4);
7785 ins_encode %{
7786 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7787 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7788 %}
7789 ins_pipe(pipe_class_default);
7790 %}
7791
7792 // Long Immediate Addition with 16-bit shifted operand.
7793 // No constant pool entries required.
7794 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7795 match(Set dst (AddL src1 src2));
7796
7797 format %{ "ADDIS $dst, $src1, $src2" %}
7798 size(4);
7799 ins_encode %{
7800 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7801 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7802 %}
7803 ins_pipe(pipe_class_default);
7804 %}
7805
7806 // Pointer Register Addition
7807 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7808 match(Set dst (AddP src1 src2));
7809 format %{ "ADD $dst, $src1, $src2" %}
7810 size(4);
7811 ins_encode %{
7812 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7813 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7814 %}
7815 ins_pipe(pipe_class_default);
7816 %}
7817
7818 // Pointer Immediate Addition
7819 // No constant pool entries required.
7820 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7821 match(Set dst (AddP src1 src2));
7822
7823 format %{ "ADDI $dst, $src1, $src2" %}
7824 size(4);
7825 ins_encode %{
7826 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7827 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7828 %}
7829 ins_pipe(pipe_class_default);
7830 %}
7831
7832 // Pointer Immediate Addition with 16-bit shifted operand.
7833 // No constant pool entries required.
7834 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7835 match(Set dst (AddP src1 src2));
7836
7837 format %{ "ADDIS $dst, $src1, $src2" %}
7838 size(4);
7839 ins_encode %{
7840 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7841 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7842 %}
7843 ins_pipe(pipe_class_default);
7844 %}
7845
7846 //---------------------
7847 // Subtraction Instructions
7848
7849 // Register Subtraction
7850 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7851 match(Set dst (SubI src1 src2));
7852 format %{ "SUBF $dst, $src2, $src1" %}
7853 size(4);
7854 ins_encode %{
7855 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7856 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7857 %}
7858 ins_pipe(pipe_class_default);
7859 %}
7860
7861 // Immediate Subtraction
7862 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7863 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7864
7865 // SubI from constant (using subfic).
7866 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7867 match(Set dst (SubI src1 src2));
7868 format %{ "SUBI $dst, $src1, $src2" %}
7869
7870 size(4);
7871 ins_encode %{
7872 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7873 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7874 %}
7875 ins_pipe(pipe_class_default);
7876 %}
7877
7878 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7879 // positive integers and 0xF...F for negative ones.
7880 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7881 // no match-rule, false predicate
7882 effect(DEF dst, USE src);
7883 predicate(false);
7884
7885 format %{ "SRAWI $dst, $src, #31" %}
7886 size(4);
7887 ins_encode %{
7888 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7889 __ srawi($dst$$Register, $src$$Register, 0x1f);
7890 %}
7891 ins_pipe(pipe_class_default);
7892 %}
7893
7894 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7895 match(Set dst (AbsI src));
7896 ins_cost(DEFAULT_COST*3);
7897
7898 expand %{
7899 iRegIdst tmp1;
7900 iRegIdst tmp2;
7901 signmask32I_regI(tmp1, src);
7902 xorI_reg_reg(tmp2, tmp1, src);
7903 subI_reg_reg(dst, tmp2, tmp1);
7904 %}
7905 %}
7906
7907 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7908 match(Set dst (SubI zero src2));
7909 format %{ "NEG $dst, $src2" %}
7910 size(4);
7911 ins_encode %{
7912 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7913 __ neg($dst$$Register, $src2$$Register);
7914 %}
7915 ins_pipe(pipe_class_default);
7916 %}
7917
7918 // Long subtraction
7919 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7920 match(Set dst (SubL src1 src2));
7921 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7922 size(4);
7923 ins_encode %{
7924 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7925 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7926 %}
7927 ins_pipe(pipe_class_default);
7928 %}
7929
7930 // SubL + convL2I.
7931 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7932 match(Set dst (ConvL2I (SubL src1 src2)));
7933
7934 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7935 size(4);
7936 ins_encode %{
7937 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7938 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7939 %}
7940 ins_pipe(pipe_class_default);
7941 %}
7942
7943 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7944 // positive longs and 0xF...F for negative ones.
7945 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7946 // no match-rule, false predicate
7947 effect(DEF dst, USE src);
7948 predicate(false);
7949
7950 format %{ "SRADI $dst, $src, #63" %}
7951 size(4);
7952 ins_encode %{
7953 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7954 __ sradi($dst$$Register, $src$$Register, 0x3f);
7955 %}
7956 ins_pipe(pipe_class_default);
7957 %}
7958
7959 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7960 // positive longs and 0xF...F for negative ones.
7961 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7962 // no match-rule, false predicate
7963 effect(DEF dst, USE src);
7964 predicate(false);
7965
7966 format %{ "SRADI $dst, $src, #63" %}
7967 size(4);
7968 ins_encode %{
7969 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7970 __ sradi($dst$$Register, $src$$Register, 0x3f);
7971 %}
7972 ins_pipe(pipe_class_default);
7973 %}
7974
7975 // Long negation
7976 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7977 match(Set dst (SubL zero src2));
7978 format %{ "NEG $dst, $src2 \t// long" %}
7979 size(4);
7980 ins_encode %{
7981 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7982 __ neg($dst$$Register, $src2$$Register);
7983 %}
7984 ins_pipe(pipe_class_default);
7985 %}
7986
7987 // NegL + ConvL2I.
7988 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7989 match(Set dst (ConvL2I (SubL zero src2)));
7990
7991 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7992 size(4);
7993 ins_encode %{
7994 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7995 __ neg($dst$$Register, $src2$$Register);
7996 %}
7997 ins_pipe(pipe_class_default);
7998 %}
7999
8000 // Multiplication Instructions
8001 // Integer Multiplication
8002
8003 // Register Multiplication
8004 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8005 match(Set dst (MulI src1 src2));
8006 ins_cost(DEFAULT_COST);
8007
8008 format %{ "MULLW $dst, $src1, $src2" %}
8009 size(4);
8010 ins_encode %{
8011 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8012 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8013 %}
8014 ins_pipe(pipe_class_default);
8015 %}
8016
8017 // Immediate Multiplication
8018 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8019 match(Set dst (MulI src1 src2));
8020 ins_cost(DEFAULT_COST);
8021
8022 format %{ "MULLI $dst, $src1, $src2" %}
8023 size(4);
8024 ins_encode %{
8025 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8026 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8027 %}
8028 ins_pipe(pipe_class_default);
8029 %}
8030
8031 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8032 match(Set dst (MulL src1 src2));
8033 ins_cost(DEFAULT_COST);
8034
8035 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8036 size(4);
8037 ins_encode %{
8038 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8039 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8040 %}
8041 ins_pipe(pipe_class_default);
8042 %}
8043
8044 // Multiply high for optimized long division by constant.
8045 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8046 match(Set dst (MulHiL src1 src2));
8047 ins_cost(DEFAULT_COST);
8048
8049 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8050 size(4);
8051 ins_encode %{
8052 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8053 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8054 %}
8055 ins_pipe(pipe_class_default);
8056 %}
8057
8058 // Immediate Multiplication
8059 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8060 match(Set dst (MulL src1 src2));
8061 ins_cost(DEFAULT_COST);
8062
8063 format %{ "MULLI $dst, $src1, $src2" %}
8064 size(4);
8065 ins_encode %{
8066 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8067 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8068 %}
8069 ins_pipe(pipe_class_default);
8070 %}
8071
8072 // Integer Division with Immediate -1: Negate.
8073 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8074 match(Set dst (DivI src1 src2));
8075 ins_cost(DEFAULT_COST);
8076
8077 format %{ "NEG $dst, $src1 \t// /-1" %}
8078 size(4);
8079 ins_encode %{
8080 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8081 __ neg($dst$$Register, $src1$$Register);
8082 %}
8083 ins_pipe(pipe_class_default);
8084 %}
8085
8086 // Integer Division with constant, but not -1.
8087 // We should be able to improve this by checking the type of src2.
8088 // It might well be that src2 is known to be positive.
8089 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8090 match(Set dst (DivI src1 src2));
8091 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8092 ins_cost(2*DEFAULT_COST);
8093
8094 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8095 size(4);
8096 ins_encode %{
8097 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8098 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8099 %}
8100 ins_pipe(pipe_class_default);
8101 %}
8102
8103 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8104 effect(USE_DEF dst, USE src1, USE crx);
8105 predicate(false);
8106
8107 ins_variable_size_depending_on_alignment(true);
8108
8109 format %{ "CMOVE $dst, neg($src1), $crx" %}
8110 // Worst case is branch + move + stop, no stop without scheduler.
8111 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8112 ins_encode %{
8113 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8114 Label done;
8115 __ bne($crx$$CondRegister, done);
8116 __ neg($dst$$Register, $src1$$Register);
8117 // TODO PPC port __ endgroup_if_needed(_size == 12);
8118 __ bind(done);
8119 %}
8120 ins_pipe(pipe_class_default);
8121 %}
8122
8123 // Integer Division with Registers not containing constants.
8124 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8125 match(Set dst (DivI src1 src2));
8126 ins_cost(10*DEFAULT_COST);
8127
8128 expand %{
8129 immI16 imm %{ (int)-1 %}
8130 flagsReg tmp1;
8131 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8132 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8133 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8134 %}
8135 %}
8136
8137 // Long Division with Immediate -1: Negate.
8138 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8139 match(Set dst (DivL src1 src2));
8140 ins_cost(DEFAULT_COST);
8141
8142 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8143 size(4);
8144 ins_encode %{
8145 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8146 __ neg($dst$$Register, $src1$$Register);
8147 %}
8148 ins_pipe(pipe_class_default);
8149 %}
8150
8151 // Long Division with constant, but not -1.
8152 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8153 match(Set dst (DivL src1 src2));
8154 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8155 ins_cost(2*DEFAULT_COST);
8156
8157 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8158 size(4);
8159 ins_encode %{
8160 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8161 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8162 %}
8163 ins_pipe(pipe_class_default);
8164 %}
8165
8166 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8167 effect(USE_DEF dst, USE src1, USE crx);
8168 predicate(false);
8169
8170 ins_variable_size_depending_on_alignment(true);
8171
8172 format %{ "CMOVE $dst, neg($src1), $crx" %}
8173 // Worst case is branch + move + stop, no stop without scheduler.
8174 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8175 ins_encode %{
8176 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8177 Label done;
8178 __ bne($crx$$CondRegister, done);
8179 __ neg($dst$$Register, $src1$$Register);
8180 // TODO PPC port __ endgroup_if_needed(_size == 12);
8181 __ bind(done);
8182 %}
8183 ins_pipe(pipe_class_default);
8184 %}
8185
8186 // Long Division with Registers not containing constants.
8187 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8188 match(Set dst (DivL src1 src2));
8189 ins_cost(10*DEFAULT_COST);
8190
8191 expand %{
8192 immL16 imm %{ (int)-1 %}
8193 flagsReg tmp1;
8194 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8195 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8196 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8197 %}
8198 %}
8199
8200 // Integer Remainder with registers.
8201 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8202 match(Set dst (ModI src1 src2));
8203 ins_cost(10*DEFAULT_COST);
8204
8205 expand %{
8206 immI16 imm %{ (int)-1 %}
8207 flagsReg tmp1;
8208 iRegIdst tmp2;
8209 iRegIdst tmp3;
8210 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8211 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8212 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8213 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8214 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8215 %}
8216 %}
8217
8218 // Long Remainder with registers
8219 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8220 match(Set dst (ModL src1 src2));
8221 ins_cost(10*DEFAULT_COST);
8222
8223 expand %{
8224 immL16 imm %{ (int)-1 %}
8225 flagsReg tmp1;
8226 iRegLdst tmp2;
8227 iRegLdst tmp3;
8228 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8229 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8230 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8231 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8232 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8233 %}
8234 %}
8235
8236 // Integer Shift Instructions
8237
8238 // Register Shift Left
8239
8240 // Clear all but the lowest #mask bits.
8241 // Used to normalize shift amounts in registers.
8242 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8243 // no match-rule, false predicate
8244 effect(DEF dst, USE src, USE mask);
8245 predicate(false);
8246
8247 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8248 size(4);
8249 ins_encode %{
8250 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8251 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8252 %}
8253 ins_pipe(pipe_class_default);
8254 %}
8255
8256 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8257 // no match-rule, false predicate
8258 effect(DEF dst, USE src1, USE src2);
8259 predicate(false);
8260
8261 format %{ "SLW $dst, $src1, $src2" %}
8262 size(4);
8263 ins_encode %{
8264 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8265 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8266 %}
8267 ins_pipe(pipe_class_default);
8268 %}
8269
8270 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8271 match(Set dst (LShiftI src1 src2));
8272 ins_cost(DEFAULT_COST*2);
8273 expand %{
8274 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8275 iRegIdst tmpI;
8276 maskI_reg_imm(tmpI, src2, mask);
8277 lShiftI_reg_reg(dst, src1, tmpI);
8278 %}
8279 %}
8280
8281 // Register Shift Left Immediate
8282 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8283 match(Set dst (LShiftI src1 src2));
8284
8285 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8286 size(4);
8287 ins_encode %{
8288 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8289 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8290 %}
8291 ins_pipe(pipe_class_default);
8292 %}
8293
8294 // AndI with negpow2-constant + LShiftI
8295 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8296 match(Set dst (LShiftI (AndI src1 src2) src3));
8297 predicate(UseRotateAndMaskInstructionsPPC64);
8298
8299 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8300 size(4);
8301 ins_encode %{
8302 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8303 long src2 = $src2$$constant;
8304 long src3 = $src3$$constant;
8305 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8306 if (maskbits >= 32) {
8307 __ li($dst$$Register, 0); // addi
8308 } else {
8309 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8310 }
8311 %}
8312 ins_pipe(pipe_class_default);
8313 %}
8314
8315 // RShiftI + AndI with negpow2-constant + LShiftI
8316 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8317 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8318 predicate(UseRotateAndMaskInstructionsPPC64);
8319
8320 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8321 size(4);
8322 ins_encode %{
8323 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8324 long src2 = $src2$$constant;
8325 long src3 = $src3$$constant;
8326 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8327 if (maskbits >= 32) {
8328 __ li($dst$$Register, 0); // addi
8329 } else {
8330 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8331 }
8332 %}
8333 ins_pipe(pipe_class_default);
8334 %}
8335
8336 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8337 // no match-rule, false predicate
8338 effect(DEF dst, USE src1, USE src2);
8339 predicate(false);
8340
8341 format %{ "SLD $dst, $src1, $src2" %}
8342 size(4);
8343 ins_encode %{
8344 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8345 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8346 %}
8347 ins_pipe(pipe_class_default);
8348 %}
8349
8350 // Register Shift Left
8351 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8352 match(Set dst (LShiftL src1 src2));
8353 ins_cost(DEFAULT_COST*2);
8354 expand %{
8355 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8356 iRegIdst tmpI;
8357 maskI_reg_imm(tmpI, src2, mask);
8358 lShiftL_regL_regI(dst, src1, tmpI);
8359 %}
8360 %}
8361
8362 // Register Shift Left Immediate
8363 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8364 match(Set dst (LShiftL src1 src2));
8365 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8366 size(4);
8367 ins_encode %{
8368 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8369 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8370 %}
8371 ins_pipe(pipe_class_default);
8372 %}
8373
8374 // If we shift more than 32 bits, we need not convert I2L.
8375 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8376 match(Set dst (LShiftL (ConvI2L src1) src2));
8377 ins_cost(DEFAULT_COST);
8378
8379 size(4);
8380 format %{ "SLDI $dst, i2l($src1), $src2" %}
8381 ins_encode %{
8382 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8383 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8384 %}
8385 ins_pipe(pipe_class_default);
8386 %}
8387
8388 // Shift a postivie int to the left.
8389 // Clrlsldi clears the upper 32 bits and shifts.
8390 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8391 match(Set dst (LShiftL (ConvI2L src1) src2));
8392 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8393
8394 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8395 size(4);
8396 ins_encode %{
8397 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8398 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8399 %}
8400 ins_pipe(pipe_class_default);
8401 %}
8402
8403 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8404 // no match-rule, false predicate
8405 effect(DEF dst, USE src1, USE src2);
8406 predicate(false);
8407
8408 format %{ "SRAW $dst, $src1, $src2" %}
8409 size(4);
8410 ins_encode %{
8411 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8412 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8413 %}
8414 ins_pipe(pipe_class_default);
8415 %}
8416
8417 // Register Arithmetic Shift Right
8418 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8419 match(Set dst (RShiftI src1 src2));
8420 ins_cost(DEFAULT_COST*2);
8421 expand %{
8422 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8423 iRegIdst tmpI;
8424 maskI_reg_imm(tmpI, src2, mask);
8425 arShiftI_reg_reg(dst, src1, tmpI);
8426 %}
8427 %}
8428
8429 // Register Arithmetic Shift Right Immediate
8430 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8431 match(Set dst (RShiftI src1 src2));
8432
8433 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8434 size(4);
8435 ins_encode %{
8436 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8437 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8438 %}
8439 ins_pipe(pipe_class_default);
8440 %}
8441
8442 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8443 // no match-rule, false predicate
8444 effect(DEF dst, USE src1, USE src2);
8445 predicate(false);
8446
8447 format %{ "SRAD $dst, $src1, $src2" %}
8448 size(4);
8449 ins_encode %{
8450 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8451 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8452 %}
8453 ins_pipe(pipe_class_default);
8454 %}
8455
8456 // Register Shift Right Arithmetic Long
8457 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8458 match(Set dst (RShiftL src1 src2));
8459 ins_cost(DEFAULT_COST*2);
8460
8461 expand %{
8462 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8463 iRegIdst tmpI;
8464 maskI_reg_imm(tmpI, src2, mask);
8465 arShiftL_regL_regI(dst, src1, tmpI);
8466 %}
8467 %}
8468
8469 // Register Shift Right Immediate
8470 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8471 match(Set dst (RShiftL src1 src2));
8472
8473 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8474 size(4);
8475 ins_encode %{
8476 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8477 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8478 %}
8479 ins_pipe(pipe_class_default);
8480 %}
8481
8482 // RShiftL + ConvL2I
8483 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8484 match(Set dst (ConvL2I (RShiftL src1 src2)));
8485
8486 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8487 size(4);
8488 ins_encode %{
8489 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8490 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8491 %}
8492 ins_pipe(pipe_class_default);
8493 %}
8494
8495 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8496 // no match-rule, false predicate
8497 effect(DEF dst, USE src1, USE src2);
8498 predicate(false);
8499
8500 format %{ "SRW $dst, $src1, $src2" %}
8501 size(4);
8502 ins_encode %{
8503 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8504 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8505 %}
8506 ins_pipe(pipe_class_default);
8507 %}
8508
8509 // Register Shift Right
8510 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8511 match(Set dst (URShiftI src1 src2));
8512 ins_cost(DEFAULT_COST*2);
8513
8514 expand %{
8515 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8516 iRegIdst tmpI;
8517 maskI_reg_imm(tmpI, src2, mask);
8518 urShiftI_reg_reg(dst, src1, tmpI);
8519 %}
8520 %}
8521
8522 // Register Shift Right Immediate
8523 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8524 match(Set dst (URShiftI src1 src2));
8525
8526 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8527 size(4);
8528 ins_encode %{
8529 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8530 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8531 %}
8532 ins_pipe(pipe_class_default);
8533 %}
8534
8535 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8536 // no match-rule, false predicate
8537 effect(DEF dst, USE src1, USE src2);
8538 predicate(false);
8539
8540 format %{ "SRD $dst, $src1, $src2" %}
8541 size(4);
8542 ins_encode %{
8543 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8544 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8545 %}
8546 ins_pipe(pipe_class_default);
8547 %}
8548
8549 // Register Shift Right
8550 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8551 match(Set dst (URShiftL src1 src2));
8552 ins_cost(DEFAULT_COST*2);
8553
8554 expand %{
8555 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8556 iRegIdst tmpI;
8557 maskI_reg_imm(tmpI, src2, mask);
8558 urShiftL_regL_regI(dst, src1, tmpI);
8559 %}
8560 %}
8561
8562 // Register Shift Right Immediate
8563 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8564 match(Set dst (URShiftL src1 src2));
8565
8566 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8567 size(4);
8568 ins_encode %{
8569 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8570 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8571 %}
8572 ins_pipe(pipe_class_default);
8573 %}
8574
8575 // URShiftL + ConvL2I.
8576 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8577 match(Set dst (ConvL2I (URShiftL src1 src2)));
8578
8579 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8580 size(4);
8581 ins_encode %{
8582 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8583 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8584 %}
8585 ins_pipe(pipe_class_default);
8586 %}
8587
8588 // Register Shift Right Immediate with a CastP2X
8589 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8590 match(Set dst (URShiftL (CastP2X src1) src2));
8591
8592 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8593 size(4);
8594 ins_encode %{
8595 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8596 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8597 %}
8598 ins_pipe(pipe_class_default);
8599 %}
8600
8601 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8602 match(Set dst (ConvL2I (ConvI2L src)));
8603
8604 format %{ "EXTSW $dst, $src \t// int->int" %}
8605 size(4);
8606 ins_encode %{
8607 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8608 __ extsw($dst$$Register, $src$$Register);
8609 %}
8610 ins_pipe(pipe_class_default);
8611 %}
8612
8613 //----------Rotate Instructions------------------------------------------------
8614
8615 // Rotate Left by 8-bit immediate
8616 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8617 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8618 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8619
8620 format %{ "ROTLWI $dst, $src, $lshift" %}
8621 size(4);
8622 ins_encode %{
8623 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8624 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8625 %}
8626 ins_pipe(pipe_class_default);
8627 %}
8628
8629 // Rotate Right by 8-bit immediate
8630 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8631 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8632 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8633
8634 format %{ "ROTRWI $dst, $rshift" %}
8635 size(4);
8636 ins_encode %{
8637 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8638 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8639 %}
8640 ins_pipe(pipe_class_default);
8641 %}
8642
8643 //----------Floating Point Arithmetic Instructions-----------------------------
8644
8645 // Add float single precision
8646 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8647 match(Set dst (AddF src1 src2));
8648
8649 format %{ "FADDS $dst, $src1, $src2" %}
8650 size(4);
8651 ins_encode %{
8652 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8653 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8654 %}
8655 ins_pipe(pipe_class_default);
8656 %}
8657
8658 // Add float double precision
8659 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8660 match(Set dst (AddD src1 src2));
8661
8662 format %{ "FADD $dst, $src1, $src2" %}
8663 size(4);
8664 ins_encode %{
8665 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8666 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8667 %}
8668 ins_pipe(pipe_class_default);
8669 %}
8670
8671 // Sub float single precision
8672 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8673 match(Set dst (SubF src1 src2));
8674
8675 format %{ "FSUBS $dst, $src1, $src2" %}
8676 size(4);
8677 ins_encode %{
8678 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8679 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8680 %}
8681 ins_pipe(pipe_class_default);
8682 %}
8683
8684 // Sub float double precision
8685 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8686 match(Set dst (SubD src1 src2));
8687 format %{ "FSUB $dst, $src1, $src2" %}
8688 size(4);
8689 ins_encode %{
8690 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8691 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8692 %}
8693 ins_pipe(pipe_class_default);
8694 %}
8695
8696 // Mul float single precision
8697 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8698 match(Set dst (MulF src1 src2));
8699 format %{ "FMULS $dst, $src1, $src2" %}
8700 size(4);
8701 ins_encode %{
8702 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8703 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8704 %}
8705 ins_pipe(pipe_class_default);
8706 %}
8707
8708 // Mul float double precision
8709 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8710 match(Set dst (MulD src1 src2));
8711 format %{ "FMUL $dst, $src1, $src2" %}
8712 size(4);
8713 ins_encode %{
8714 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8715 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8716 %}
8717 ins_pipe(pipe_class_default);
8718 %}
8719
8720 // Div float single precision
8721 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8722 match(Set dst (DivF src1 src2));
8723 format %{ "FDIVS $dst, $src1, $src2" %}
8724 size(4);
8725 ins_encode %{
8726 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8727 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8728 %}
8729 ins_pipe(pipe_class_default);
8730 %}
8731
8732 // Div float double precision
8733 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8734 match(Set dst (DivD src1 src2));
8735 format %{ "FDIV $dst, $src1, $src2" %}
8736 size(4);
8737 ins_encode %{
8738 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8739 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8740 %}
8741 ins_pipe(pipe_class_default);
8742 %}
8743
8744 // Absolute float single precision
8745 instruct absF_reg(regF dst, regF src) %{
8746 match(Set dst (AbsF src));
8747 format %{ "FABS $dst, $src \t// float" %}
8748 size(4);
8749 ins_encode %{
8750 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8751 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8752 %}
8753 ins_pipe(pipe_class_default);
8754 %}
8755
8756 // Absolute float double precision
8757 instruct absD_reg(regD dst, regD src) %{
8758 match(Set dst (AbsD src));
8759 format %{ "FABS $dst, $src \t// double" %}
8760 size(4);
8761 ins_encode %{
8762 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8763 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8764 %}
8765 ins_pipe(pipe_class_default);
8766 %}
8767
8768 instruct negF_reg(regF dst, regF src) %{
8769 match(Set dst (NegF src));
8770 format %{ "FNEG $dst, $src \t// float" %}
8771 size(4);
8772 ins_encode %{
8773 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8774 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8775 %}
8776 ins_pipe(pipe_class_default);
8777 %}
8778
8779 instruct negD_reg(regD dst, regD src) %{
8780 match(Set dst (NegD src));
8781 format %{ "FNEG $dst, $src \t// double" %}
8782 size(4);
8783 ins_encode %{
8784 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8785 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8786 %}
8787 ins_pipe(pipe_class_default);
8788 %}
8789
8790 // AbsF + NegF.
8791 instruct negF_absF_reg(regF dst, regF src) %{
8792 match(Set dst (NegF (AbsF src)));
8793 format %{ "FNABS $dst, $src \t// float" %}
8794 size(4);
8795 ins_encode %{
8796 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8797 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8798 %}
8799 ins_pipe(pipe_class_default);
8800 %}
8801
8802 // AbsD + NegD.
8803 instruct negD_absD_reg(regD dst, regD src) %{
8804 match(Set dst (NegD (AbsD src)));
8805 format %{ "FNABS $dst, $src \t// double" %}
8806 size(4);
8807 ins_encode %{
8808 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8809 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8810 %}
8811 ins_pipe(pipe_class_default);
8812 %}
8813
8814 // VM_Version::has_fsqrt() decides if this node will be used.
8815 // Sqrt float double precision
8816 instruct sqrtD_reg(regD dst, regD src) %{
8817 match(Set dst (SqrtD src));
8818 format %{ "FSQRT $dst, $src" %}
8819 size(4);
8820 ins_encode %{
8821 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8822 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8823 %}
8824 ins_pipe(pipe_class_default);
8825 %}
8826
8827 // Single-precision sqrt.
8828 instruct sqrtF_reg(regF dst, regF src) %{
8829 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8830 predicate(VM_Version::has_fsqrts());
8831 ins_cost(DEFAULT_COST);
8832
8833 format %{ "FSQRTS $dst, $src" %}
8834 size(4);
8835 ins_encode %{
8836 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8837 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8838 %}
8839 ins_pipe(pipe_class_default);
8840 %}
8841
8842 instruct roundDouble_nop(regD dst) %{
8843 match(Set dst (RoundDouble dst));
8844 ins_cost(0);
8845
8846 format %{ " -- \t// RoundDouble not needed - empty" %}
8847 size(0);
8848 // PPC results are already "rounded" (i.e., normal-format IEEE).
8849 ins_encode( /*empty*/ );
8850 ins_pipe(pipe_class_default);
8851 %}
8852
8853 instruct roundFloat_nop(regF dst) %{
8854 match(Set dst (RoundFloat dst));
8855 ins_cost(0);
8856
8857 format %{ " -- \t// RoundFloat not needed - empty" %}
8858 size(0);
8859 // PPC results are already "rounded" (i.e., normal-format IEEE).
8860 ins_encode( /*empty*/ );
8861 ins_pipe(pipe_class_default);
8862 %}
8863
8864 //----------Logical Instructions-----------------------------------------------
8865
8866 // And Instructions
8867
8868 // Register And
8869 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8870 match(Set dst (AndI src1 src2));
8871 format %{ "AND $dst, $src1, $src2" %}
8872 size(4);
8873 ins_encode %{
8874 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8875 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8876 %}
8877 ins_pipe(pipe_class_default);
8878 %}
8879
8880 // Immediate And
8881 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8882 match(Set dst (AndI src1 src2));
8883 effect(KILL cr0);
8884
8885 format %{ "ANDI $dst, $src1, $src2" %}
8886 size(4);
8887 ins_encode %{
8888 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8889 // FIXME: avoid andi_ ?
8890 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8891 %}
8892 ins_pipe(pipe_class_default);
8893 %}
8894
8895 // Immediate And where the immediate is a negative power of 2.
8896 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8897 match(Set dst (AndI src1 src2));
8898 format %{ "ANDWI $dst, $src1, $src2" %}
8899 size(4);
8900 ins_encode %{
8901 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8902 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8903 %}
8904 ins_pipe(pipe_class_default);
8905 %}
8906
8907 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8908 match(Set dst (AndI src1 src2));
8909 format %{ "ANDWI $dst, $src1, $src2" %}
8910 size(4);
8911 ins_encode %{
8912 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8913 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8914 %}
8915 ins_pipe(pipe_class_default);
8916 %}
8917
8918 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8919 match(Set dst (AndI src1 src2));
8920 predicate(UseRotateAndMaskInstructionsPPC64);
8921 format %{ "ANDWI $dst, $src1, $src2" %}
8922 size(4);
8923 ins_encode %{
8924 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8925 __ rlwinm($dst$$Register, $src1$$Register, 0,
8926 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8927 %}
8928 ins_pipe(pipe_class_default);
8929 %}
8930
8931 // Register And Long
8932 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8933 match(Set dst (AndL src1 src2));
8934 ins_cost(DEFAULT_COST);
8935
8936 format %{ "AND $dst, $src1, $src2 \t// long" %}
8937 size(4);
8938 ins_encode %{
8939 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8940 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8941 %}
8942 ins_pipe(pipe_class_default);
8943 %}
8944
8945 // Immediate And long
8946 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8947 match(Set dst (AndL src1 src2));
8948 effect(KILL cr0);
8949
8950 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8951 size(4);
8952 ins_encode %{
8953 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8954 // FIXME: avoid andi_ ?
8955 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8956 %}
8957 ins_pipe(pipe_class_default);
8958 %}
8959
8960 // Immediate And Long where the immediate is a negative power of 2.
8961 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8962 match(Set dst (AndL src1 src2));
8963 format %{ "ANDDI $dst, $src1, $src2" %}
8964 size(4);
8965 ins_encode %{
8966 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8967 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8968 %}
8969 ins_pipe(pipe_class_default);
8970 %}
8971
8972 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8973 match(Set dst (AndL src1 src2));
8974 format %{ "ANDDI $dst, $src1, $src2" %}
8975 size(4);
8976 ins_encode %{
8977 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8978 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8979 %}
8980 ins_pipe(pipe_class_default);
8981 %}
8982
8983 // AndL + ConvL2I.
8984 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8985 match(Set dst (ConvL2I (AndL src1 src2)));
8986 ins_cost(DEFAULT_COST);
8987
8988 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8989 size(4);
8990 ins_encode %{
8991 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8992 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8993 %}
8994 ins_pipe(pipe_class_default);
8995 %}
8996
8997 // Or Instructions
8998
8999 // Register Or
9000 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9001 match(Set dst (OrI src1 src2));
9002 format %{ "OR $dst, $src1, $src2" %}
9003 size(4);
9004 ins_encode %{
9005 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9006 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9007 %}
9008 ins_pipe(pipe_class_default);
9009 %}
9010
9011 // Expand does not work with above instruct. (??)
9012 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9013 // no match-rule
9014 effect(DEF dst, USE src1, USE src2);
9015 format %{ "OR $dst, $src1, $src2" %}
9016 size(4);
9017 ins_encode %{
9018 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9019 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9020 %}
9021 ins_pipe(pipe_class_default);
9022 %}
9023
9024 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9025 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9026 ins_cost(DEFAULT_COST*3);
9027
9028 expand %{
9029 // FIXME: we should do this in the ideal world.
9030 iRegIdst tmp1;
9031 iRegIdst tmp2;
9032 orI_reg_reg(tmp1, src1, src2);
9033 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9034 orI_reg_reg(dst, tmp1, tmp2);
9035 %}
9036 %}
9037
9038 // Immediate Or
9039 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9040 match(Set dst (OrI src1 src2));
9041 format %{ "ORI $dst, $src1, $src2" %}
9042 size(4);
9043 ins_encode %{
9044 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9045 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9046 %}
9047 ins_pipe(pipe_class_default);
9048 %}
9049
9050 // Register Or Long
9051 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9052 match(Set dst (OrL src1 src2));
9053 ins_cost(DEFAULT_COST);
9054
9055 size(4);
9056 format %{ "OR $dst, $src1, $src2 \t// long" %}
9057 ins_encode %{
9058 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9059 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9060 %}
9061 ins_pipe(pipe_class_default);
9062 %}
9063
9064 // OrL + ConvL2I.
9065 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9066 match(Set dst (ConvL2I (OrL src1 src2)));
9067 ins_cost(DEFAULT_COST);
9068
9069 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9070 size(4);
9071 ins_encode %{
9072 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9073 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9074 %}
9075 ins_pipe(pipe_class_default);
9076 %}
9077
9078 // Immediate Or long
9079 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9080 match(Set dst (OrL src1 con));
9081 ins_cost(DEFAULT_COST);
9082
9083 format %{ "ORI $dst, $src1, $con \t// long" %}
9084 size(4);
9085 ins_encode %{
9086 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9087 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9088 %}
9089 ins_pipe(pipe_class_default);
9090 %}
9091
9092 // Xor Instructions
9093
9094 // Register Xor
9095 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9096 match(Set dst (XorI src1 src2));
9097 format %{ "XOR $dst, $src1, $src2" %}
9098 size(4);
9099 ins_encode %{
9100 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9101 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9102 %}
9103 ins_pipe(pipe_class_default);
9104 %}
9105
9106 // Expand does not work with above instruct. (??)
9107 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9108 // no match-rule
9109 effect(DEF dst, USE src1, USE src2);
9110 format %{ "XOR $dst, $src1, $src2" %}
9111 size(4);
9112 ins_encode %{
9113 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9114 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9115 %}
9116 ins_pipe(pipe_class_default);
9117 %}
9118
9119 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9120 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9121 ins_cost(DEFAULT_COST*3);
9122
9123 expand %{
9124 // FIXME: we should do this in the ideal world.
9125 iRegIdst tmp1;
9126 iRegIdst tmp2;
9127 xorI_reg_reg(tmp1, src1, src2);
9128 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9129 xorI_reg_reg(dst, tmp1, tmp2);
9130 %}
9131 %}
9132
9133 // Immediate Xor
9134 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9135 match(Set dst (XorI src1 src2));
9136 format %{ "XORI $dst, $src1, $src2" %}
9137 size(4);
9138 ins_encode %{
9139 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9140 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9141 %}
9142 ins_pipe(pipe_class_default);
9143 %}
9144
9145 // Register Xor Long
9146 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9147 match(Set dst (XorL src1 src2));
9148 ins_cost(DEFAULT_COST);
9149
9150 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9151 size(4);
9152 ins_encode %{
9153 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9154 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9155 %}
9156 ins_pipe(pipe_class_default);
9157 %}
9158
9159 // XorL + ConvL2I.
9160 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9161 match(Set dst (ConvL2I (XorL src1 src2)));
9162 ins_cost(DEFAULT_COST);
9163
9164 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9165 size(4);
9166 ins_encode %{
9167 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9168 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9169 %}
9170 ins_pipe(pipe_class_default);
9171 %}
9172
9173 // Immediate Xor Long
9174 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9175 match(Set dst (XorL src1 src2));
9176 ins_cost(DEFAULT_COST);
9177
9178 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9179 size(4);
9180 ins_encode %{
9181 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9182 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9183 %}
9184 ins_pipe(pipe_class_default);
9185 %}
9186
9187 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9188 match(Set dst (XorI src1 src2));
9189 ins_cost(DEFAULT_COST);
9190
9191 format %{ "NOT $dst, $src1 ($src2)" %}
9192 size(4);
9193 ins_encode %{
9194 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9195 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9196 %}
9197 ins_pipe(pipe_class_default);
9198 %}
9199
9200 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9201 match(Set dst (XorL src1 src2));
9202 ins_cost(DEFAULT_COST);
9203
9204 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9205 size(4);
9206 ins_encode %{
9207 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9208 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9209 %}
9210 ins_pipe(pipe_class_default);
9211 %}
9212
9213 // And-complement
9214 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9215 match(Set dst (AndI (XorI src1 src2) src3));
9216 ins_cost(DEFAULT_COST);
9217
9218 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9219 size(4);
9220 ins_encode( enc_andc(dst, src3, src1) );
9221 ins_pipe(pipe_class_default);
9222 %}
9223
9224 // And-complement
9225 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9226 // no match-rule, false predicate
9227 effect(DEF dst, USE src1, USE src2);
9228 predicate(false);
9229
9230 format %{ "ANDC $dst, $src1, $src2" %}
9231 size(4);
9232 ins_encode %{
9233 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9234 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9235 %}
9236 ins_pipe(pipe_class_default);
9237 %}
9238
9239 //----------Moves between int/long and float/double----------------------------
9240 //
9241 // The following rules move values from int/long registers/stack-locations
9242 // to float/double registers/stack-locations and vice versa, without doing any
9243 // conversions. These rules are used to implement the bit-conversion methods
9244 // of java.lang.Float etc., e.g.
9245 // int floatToIntBits(float value)
9246 // float intBitsToFloat(int bits)
9247 //
9248 // Notes on the implementation on ppc64:
9249 // We only provide rules which move between a register and a stack-location,
9250 // because we always have to go through memory when moving between a float
9251 // register and an integer register.
9252
9253 //---------- Chain stack slots between similar types --------
9254
9255 // These are needed so that the rules below can match.
9256
9257 // Load integer from stack slot
9258 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9259 match(Set dst src);
9260 ins_cost(MEMORY_REF_COST);
9261
9262 format %{ "LWZ $dst, $src" %}
9263 size(4);
9264 ins_encode( enc_lwz(dst, src) );
9265 ins_pipe(pipe_class_memory);
9266 %}
9267
9268 // Store integer to stack slot
9269 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9270 match(Set dst src);
9271 ins_cost(MEMORY_REF_COST);
9272
9273 format %{ "STW $src, $dst \t// stk" %}
9274 size(4);
9275 ins_encode( enc_stw(src, dst) ); // rs=rt
9276 ins_pipe(pipe_class_memory);
9277 %}
9278
9279 // Load long from stack slot
9280 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9281 match(Set dst src);
9282 ins_cost(MEMORY_REF_COST);
9283
9284 format %{ "LD $dst, $src \t// long" %}
9285 size(4);
9286 ins_encode( enc_ld(dst, src) );
9287 ins_pipe(pipe_class_memory);
9288 %}
9289
9290 // Store long to stack slot
9291 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9292 match(Set dst src);
9293 ins_cost(MEMORY_REF_COST);
9294
9295 format %{ "STD $src, $dst \t// long" %}
9296 size(4);
9297 ins_encode( enc_std(src, dst) ); // rs=rt
9298 ins_pipe(pipe_class_memory);
9299 %}
9300
9301 //----------Moves between int and float
9302
9303 // Move float value from float stack-location to integer register.
9304 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9305 match(Set dst (MoveF2I src));
9306 ins_cost(MEMORY_REF_COST);
9307
9308 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9309 size(4);
9310 ins_encode( enc_lwz(dst, src) );
9311 ins_pipe(pipe_class_memory);
9312 %}
9313
9314 // Move float value from float register to integer stack-location.
9315 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9316 match(Set dst (MoveF2I src));
9317 ins_cost(MEMORY_REF_COST);
9318
9319 format %{ "STFS $src, $dst \t// MoveF2I" %}
9320 size(4);
9321 ins_encode( enc_stfs(src, dst) );
9322 ins_pipe(pipe_class_memory);
9323 %}
9324
9325 // Move integer value from integer stack-location to float register.
9326 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9327 match(Set dst (MoveI2F src));
9328 ins_cost(MEMORY_REF_COST);
9329
9330 format %{ "LFS $dst, $src \t// MoveI2F" %}
9331 size(4);
9332 ins_encode %{
9333 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9334 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9335 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9336 %}
9337 ins_pipe(pipe_class_memory);
9338 %}
9339
9340 // Move integer value from integer register to float stack-location.
9341 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9342 match(Set dst (MoveI2F src));
9343 ins_cost(MEMORY_REF_COST);
9344
9345 format %{ "STW $src, $dst \t// MoveI2F" %}
9346 size(4);
9347 ins_encode( enc_stw(src, dst) );
9348 ins_pipe(pipe_class_memory);
9349 %}
9350
9351 //----------Moves between long and float
9352
9353 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9354 // no match-rule, false predicate
9355 effect(DEF dst, USE src);
9356 predicate(false);
9357
9358 format %{ "storeD $src, $dst \t// STACK" %}
9359 size(4);
9360 ins_encode( enc_stfd(src, dst) );
9361 ins_pipe(pipe_class_default);
9362 %}
9363
9364 //----------Moves between long and double
9365
9366 // Move double value from double stack-location to long register.
9367 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9368 match(Set dst (MoveD2L src));
9369 ins_cost(MEMORY_REF_COST);
9370 size(4);
9371 format %{ "LD $dst, $src \t// MoveD2L" %}
9372 ins_encode( enc_ld(dst, src) );
9373 ins_pipe(pipe_class_memory);
9374 %}
9375
9376 // Move double value from double register to long stack-location.
9377 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9378 match(Set dst (MoveD2L src));
9379 effect(DEF dst, USE src);
9380 ins_cost(MEMORY_REF_COST);
9381
9382 format %{ "STFD $src, $dst \t// MoveD2L" %}
9383 size(4);
9384 ins_encode( enc_stfd(src, dst) );
9385 ins_pipe(pipe_class_memory);
9386 %}
9387
9388 // Move long value from long stack-location to double register.
9389 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9390 match(Set dst (MoveL2D src));
9391 ins_cost(MEMORY_REF_COST);
9392
9393 format %{ "LFD $dst, $src \t// MoveL2D" %}
9394 size(4);
9395 ins_encode( enc_lfd(dst, src) );
9396 ins_pipe(pipe_class_memory);
9397 %}
9398
9399 // Move long value from long register to double stack-location.
9400 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9401 match(Set dst (MoveL2D src));
9402 ins_cost(MEMORY_REF_COST);
9403
9404 format %{ "STD $src, $dst \t// MoveL2D" %}
9405 size(4);
9406 ins_encode( enc_std(src, dst) );
9407 ins_pipe(pipe_class_memory);
9408 %}
9409
9410 //----------Register Move Instructions-----------------------------------------
9411
9412 // Replicate for Superword
9413
9414 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9415 predicate(false);
9416 effect(DEF dst, USE src);
9417
9418 format %{ "MR $dst, $src \t// replicate " %}
9419 // variable size, 0 or 4.
9420 ins_encode %{
9421 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9422 __ mr_if_needed($dst$$Register, $src$$Register);
9423 %}
9424 ins_pipe(pipe_class_default);
9425 %}
9426
9427 //----------Cast instructions (Java-level type cast)---------------------------
9428
9429 // Cast Long to Pointer for unsafe natives.
9430 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9431 match(Set dst (CastX2P src));
9432
9433 format %{ "MR $dst, $src \t// Long->Ptr" %}
9434 // variable size, 0 or 4.
9435 ins_encode %{
9436 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9437 __ mr_if_needed($dst$$Register, $src$$Register);
9438 %}
9439 ins_pipe(pipe_class_default);
9440 %}
9441
9442 // Cast Pointer to Long for unsafe natives.
9443 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9444 match(Set dst (CastP2X src));
9445
9446 format %{ "MR $dst, $src \t// Ptr->Long" %}
9447 // variable size, 0 or 4.
9448 ins_encode %{
9449 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9450 __ mr_if_needed($dst$$Register, $src$$Register);
9451 %}
9452 ins_pipe(pipe_class_default);
9453 %}
9454
9455 instruct castPP(iRegPdst dst) %{
9456 match(Set dst (CastPP dst));
9457 format %{ " -- \t// castPP of $dst" %}
9458 size(0);
9459 ins_encode( /*empty*/ );
9460 ins_pipe(pipe_class_default);
9461 %}
9462
9463 instruct castII(iRegIdst dst) %{
9464 match(Set dst (CastII dst));
9465 format %{ " -- \t// castII of $dst" %}
9466 size(0);
9467 ins_encode( /*empty*/ );
9468 ins_pipe(pipe_class_default);
9469 %}
9470
9471 instruct checkCastPP(iRegPdst dst) %{
9472 match(Set dst (CheckCastPP dst));
9473 format %{ " -- \t// checkcastPP of $dst" %}
9474 size(0);
9475 ins_encode( /*empty*/ );
9476 ins_pipe(pipe_class_default);
9477 %}
9478
9479 //----------Convert instructions-----------------------------------------------
9480
9481 // Convert to boolean.
9482
9483 // int_to_bool(src) : { 1 if src != 0
9484 // { 0 else
9485 //
9486 // strategy:
9487 // 1) Count leading zeros of 32 bit-value src,
9488 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9489 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9490 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9491
9492 // convI2Bool
9493 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9494 match(Set dst (Conv2B src));
9495 predicate(UseCountLeadingZerosInstructionsPPC64);
9496 ins_cost(DEFAULT_COST);
9497
9498 expand %{
9499 immI shiftAmount %{ 0x5 %}
9500 uimmI16 mask %{ 0x1 %}
9501 iRegIdst tmp1;
9502 iRegIdst tmp2;
9503 countLeadingZerosI(tmp1, src);
9504 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9505 xorI_reg_uimm16(dst, tmp2, mask);
9506 %}
9507 %}
9508
9509 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9510 match(Set dst (Conv2B src));
9511 effect(TEMP crx);
9512 predicate(!UseCountLeadingZerosInstructionsPPC64);
9513 ins_cost(DEFAULT_COST);
9514
9515 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9516 "LI $dst, #0\n\t"
9517 "BEQ $crx, done\n\t"
9518 "LI $dst, #1\n"
9519 "done:" %}
9520 size(16);
9521 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9522 ins_pipe(pipe_class_compare);
9523 %}
9524
9525 // ConvI2B + XorI
9526 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9527 match(Set dst (XorI (Conv2B src) mask));
9528 predicate(UseCountLeadingZerosInstructionsPPC64);
9529 ins_cost(DEFAULT_COST);
9530
9531 expand %{
9532 immI shiftAmount %{ 0x5 %}
9533 iRegIdst tmp1;
9534 countLeadingZerosI(tmp1, src);
9535 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9536 %}
9537 %}
9538
9539 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9540 match(Set dst (XorI (Conv2B src) mask));
9541 effect(TEMP crx);
9542 predicate(!UseCountLeadingZerosInstructionsPPC64);
9543 ins_cost(DEFAULT_COST);
9544
9545 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9546 "LI $dst, #1\n\t"
9547 "BEQ $crx, done\n\t"
9548 "LI $dst, #0\n"
9549 "done:" %}
9550 size(16);
9551 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9552 ins_pipe(pipe_class_compare);
9553 %}
9554
9555 // AndI 0b0..010..0 + ConvI2B
9556 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9557 match(Set dst (Conv2B (AndI src mask)));
9558 predicate(UseRotateAndMaskInstructionsPPC64);
9559 ins_cost(DEFAULT_COST);
9560
9561 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9562 size(4);
9563 ins_encode %{
9564 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9565 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9566 %}
9567 ins_pipe(pipe_class_default);
9568 %}
9569
9570 // Convert pointer to boolean.
9571 //
9572 // ptr_to_bool(src) : { 1 if src != 0
9573 // { 0 else
9574 //
9575 // strategy:
9576 // 1) Count leading zeros of 64 bit-value src,
9577 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9578 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9579 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9580
9581 // ConvP2B
9582 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9583 match(Set dst (Conv2B src));
9584 predicate(UseCountLeadingZerosInstructionsPPC64);
9585 ins_cost(DEFAULT_COST);
9586
9587 expand %{
9588 immI shiftAmount %{ 0x6 %}
9589 uimmI16 mask %{ 0x1 %}
9590 iRegIdst tmp1;
9591 iRegIdst tmp2;
9592 countLeadingZerosP(tmp1, src);
9593 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9594 xorI_reg_uimm16(dst, tmp2, mask);
9595 %}
9596 %}
9597
9598 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9599 match(Set dst (Conv2B src));
9600 effect(TEMP crx);
9601 predicate(!UseCountLeadingZerosInstructionsPPC64);
9602 ins_cost(DEFAULT_COST);
9603
9604 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9605 "LI $dst, #0\n\t"
9606 "BEQ $crx, done\n\t"
9607 "LI $dst, #1\n"
9608 "done:" %}
9609 size(16);
9610 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9611 ins_pipe(pipe_class_compare);
9612 %}
9613
9614 // ConvP2B + XorI
9615 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9616 match(Set dst (XorI (Conv2B src) mask));
9617 predicate(UseCountLeadingZerosInstructionsPPC64);
9618 ins_cost(DEFAULT_COST);
9619
9620 expand %{
9621 immI shiftAmount %{ 0x6 %}
9622 iRegIdst tmp1;
9623 countLeadingZerosP(tmp1, src);
9624 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9625 %}
9626 %}
9627
9628 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9629 match(Set dst (XorI (Conv2B src) mask));
9630 effect(TEMP crx);
9631 predicate(!UseCountLeadingZerosInstructionsPPC64);
9632 ins_cost(DEFAULT_COST);
9633
9634 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9635 "LI $dst, #1\n\t"
9636 "BEQ $crx, done\n\t"
9637 "LI $dst, #0\n"
9638 "done:" %}
9639 size(16);
9640 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9641 ins_pipe(pipe_class_compare);
9642 %}
9643
9644 // if src1 < src2, return -1 else return 0
9645 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9646 match(Set dst (CmpLTMask src1 src2));
9647 ins_cost(DEFAULT_COST*4);
9648
9649 expand %{
9650 iRegLdst src1s;
9651 iRegLdst src2s;
9652 iRegLdst diff;
9653 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9654 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9655 subL_reg_reg(diff, src1s, src2s);
9656 // Need to consider >=33 bit result, therefore we need signmaskL.
9657 signmask64I_regL(dst, diff);
9658 %}
9659 %}
9660
9661 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9662 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9663 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9664 size(4);
9665 ins_encode %{
9666 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9667 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9668 %}
9669 ins_pipe(pipe_class_default);
9670 %}
9671
9672 //----------Arithmetic Conversion Instructions---------------------------------
9673
9674 // Convert to Byte -- nop
9675 // Convert to Short -- nop
9676
9677 // Convert to Int
9678
9679 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9680 match(Set dst (RShiftI (LShiftI src amount) amount));
9681 format %{ "EXTSB $dst, $src \t// byte->int" %}
9682 size(4);
9683 ins_encode %{
9684 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9685 __ extsb($dst$$Register, $src$$Register);
9686 %}
9687 ins_pipe(pipe_class_default);
9688 %}
9689
9690 // LShiftI 16 + RShiftI 16 converts short to int.
9691 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9692 match(Set dst (RShiftI (LShiftI src amount) amount));
9693 format %{ "EXTSH $dst, $src \t// short->int" %}
9694 size(4);
9695 ins_encode %{
9696 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9697 __ extsh($dst$$Register, $src$$Register);
9698 %}
9699 ins_pipe(pipe_class_default);
9700 %}
9701
9702 // ConvL2I + ConvI2L: Sign extend int in long register.
9703 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9704 match(Set dst (ConvI2L (ConvL2I src)));
9705
9706 format %{ "EXTSW $dst, $src \t// long->long" %}
9707 size(4);
9708 ins_encode %{
9709 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9710 __ extsw($dst$$Register, $src$$Register);
9711 %}
9712 ins_pipe(pipe_class_default);
9713 %}
9714
9715 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9716 match(Set dst (ConvL2I src));
9717 format %{ "MR $dst, $src \t// long->int" %}
9718 // variable size, 0 or 4
9719 ins_encode %{
9720 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9721 __ mr_if_needed($dst$$Register, $src$$Register);
9722 %}
9723 ins_pipe(pipe_class_default);
9724 %}
9725
9726 instruct convD2IRaw_regD(regD dst, regD src) %{
9727 // no match-rule, false predicate
9728 effect(DEF dst, USE src);
9729 predicate(false);
9730
9731 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9732 size(4);
9733 ins_encode %{
9734 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9735 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9736 %}
9737 ins_pipe(pipe_class_default);
9738 %}
9739
9740 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9741 // no match-rule, false predicate
9742 effect(DEF dst, USE crx, USE src);
9743 predicate(false);
9744
9745 ins_variable_size_depending_on_alignment(true);
9746
9747 format %{ "cmovI $crx, $dst, $src" %}
9748 // Worst case is branch + move + stop, no stop without scheduler.
9749 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9750 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9751 ins_pipe(pipe_class_default);
9752 %}
9753
9754 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9755 // no match-rule, false predicate
9756 effect(DEF dst, USE crx, USE mem);
9757 predicate(false);
9758
9759 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9760 postalloc_expand %{
9761 //
9762 // replaces
9763 //
9764 // region dst crx mem
9765 // \ | | /
9766 // dst=cmovI_bso_stackSlotL_conLvalue0
9767 //
9768 // with
9769 //
9770 // region dst
9771 // \ /
9772 // dst=loadConI16(0)
9773 // |
9774 // ^ region dst crx mem
9775 // | \ | | /
9776 // dst=cmovI_bso_stackSlotL
9777 //
9778
9779 // Create new nodes.
9780 MachNode *m1 = new loadConI16Node();
9781 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9782
9783 // inputs for new nodes
9784 m1->add_req(n_region);
9785 m2->add_req(n_region, n_crx, n_mem);
9786
9787 // precedences for new nodes
9788 m2->add_prec(m1);
9789
9790 // operands for new nodes
9791 m1->_opnds[0] = op_dst;
9792 m1->_opnds[1] = new immI16Oper(0);
9793
9794 m2->_opnds[0] = op_dst;
9795 m2->_opnds[1] = op_crx;
9796 m2->_opnds[2] = op_mem;
9797
9798 // registers for new nodes
9799 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9800 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9801
9802 // Insert new nodes.
9803 nodes->push(m1);
9804 nodes->push(m2);
9805 %}
9806 %}
9807
9808 // Double to Int conversion, NaN is mapped to 0.
9809 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9810 match(Set dst (ConvD2I src));
9811 ins_cost(DEFAULT_COST);
9812
9813 expand %{
9814 regD tmpD;
9815 stackSlotL tmpS;
9816 flagsReg crx;
9817 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9818 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9819 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9820 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9821 %}
9822 %}
9823
9824 instruct convF2IRaw_regF(regF dst, regF src) %{
9825 // no match-rule, false predicate
9826 effect(DEF dst, USE src);
9827 predicate(false);
9828
9829 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9830 size(4);
9831 ins_encode %{
9832 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9833 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9834 %}
9835 ins_pipe(pipe_class_default);
9836 %}
9837
9838 // Float to Int conversion, NaN is mapped to 0.
9839 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9840 match(Set dst (ConvF2I src));
9841 ins_cost(DEFAULT_COST);
9842
9843 expand %{
9844 regF tmpF;
9845 stackSlotL tmpS;
9846 flagsReg crx;
9847 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9848 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9849 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9850 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9851 %}
9852 %}
9853
9854 // Convert to Long
9855
9856 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9857 match(Set dst (ConvI2L src));
9858 format %{ "EXTSW $dst, $src \t// int->long" %}
9859 size(4);
9860 ins_encode %{
9861 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9862 __ extsw($dst$$Register, $src$$Register);
9863 %}
9864 ins_pipe(pipe_class_default);
9865 %}
9866
9867 // Zero-extend: convert unsigned int to long (convUI2L).
9868 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9869 match(Set dst (AndL (ConvI2L src) mask));
9870 ins_cost(DEFAULT_COST);
9871
9872 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9873 size(4);
9874 ins_encode %{
9875 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9876 __ clrldi($dst$$Register, $src$$Register, 32);
9877 %}
9878 ins_pipe(pipe_class_default);
9879 %}
9880
9881 // Zero-extend: convert unsigned int to long in long register.
9882 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9883 match(Set dst (AndL src mask));
9884 ins_cost(DEFAULT_COST);
9885
9886 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9887 size(4);
9888 ins_encode %{
9889 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9890 __ clrldi($dst$$Register, $src$$Register, 32);
9891 %}
9892 ins_pipe(pipe_class_default);
9893 %}
9894
9895 instruct convF2LRaw_regF(regF dst, regF src) %{
9896 // no match-rule, false predicate
9897 effect(DEF dst, USE src);
9898 predicate(false);
9899
9900 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9901 size(4);
9902 ins_encode %{
9903 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9904 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9905 %}
9906 ins_pipe(pipe_class_default);
9907 %}
9908
9909 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9910 // no match-rule, false predicate
9911 effect(DEF dst, USE crx, USE src);
9912 predicate(false);
9913
9914 ins_variable_size_depending_on_alignment(true);
9915
9916 format %{ "cmovL $crx, $dst, $src" %}
9917 // Worst case is branch + move + stop, no stop without scheduler.
9918 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9919 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9920 ins_pipe(pipe_class_default);
9921 %}
9922
9923 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9924 // no match-rule, false predicate
9925 effect(DEF dst, USE crx, USE mem);
9926 predicate(false);
9927
9928 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9929 postalloc_expand %{
9930 //
9931 // replaces
9932 //
9933 // region dst crx mem
9934 // \ | | /
9935 // dst=cmovL_bso_stackSlotL_conLvalue0
9936 //
9937 // with
9938 //
9939 // region dst
9940 // \ /
9941 // dst=loadConL16(0)
9942 // |
9943 // ^ region dst crx mem
9944 // | \ | | /
9945 // dst=cmovL_bso_stackSlotL
9946 //
9947
9948 // Create new nodes.
9949 MachNode *m1 = new loadConL16Node();
9950 MachNode *m2 = new cmovL_bso_stackSlotLNode();
9951
9952 // inputs for new nodes
9953 m1->add_req(n_region);
9954 m2->add_req(n_region, n_crx, n_mem);
9955 m2->add_prec(m1);
9956
9957 // operands for new nodes
9958 m1->_opnds[0] = op_dst;
9959 m1->_opnds[1] = new immL16Oper(0);
9960 m2->_opnds[0] = op_dst;
9961 m2->_opnds[1] = op_crx;
9962 m2->_opnds[2] = op_mem;
9963
9964 // registers for new nodes
9965 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9966 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9967
9968 // Insert new nodes.
9969 nodes->push(m1);
9970 nodes->push(m2);
9971 %}
9972 %}
9973
9974 // Float to Long conversion, NaN is mapped to 0.
9975 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9976 match(Set dst (ConvF2L src));
9977 ins_cost(DEFAULT_COST);
9978
9979 expand %{
9980 regF tmpF;
9981 stackSlotL tmpS;
9982 flagsReg crx;
9983 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9984 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9985 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9986 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9987 %}
9988 %}
9989
9990 instruct convD2LRaw_regD(regD dst, regD src) %{
9991 // no match-rule, false predicate
9992 effect(DEF dst, USE src);
9993 predicate(false);
9994
9995 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9996 size(4);
9997 ins_encode %{
9998 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9999 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10000 %}
10001 ins_pipe(pipe_class_default);
10002 %}
10003
10004 // Double to Long conversion, NaN is mapped to 0.
10005 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10006 match(Set dst (ConvD2L src));
10007 ins_cost(DEFAULT_COST);
10008
10009 expand %{
10010 regD tmpD;
10011 stackSlotL tmpS;
10012 flagsReg crx;
10013 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10014 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10015 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10016 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10017 %}
10018 %}
10019
10020 // Convert to Float
10021
10022 // Placed here as needed in expand.
10023 instruct convL2DRaw_regD(regD dst, regD src) %{
10024 // no match-rule, false predicate
10025 effect(DEF dst, USE src);
10026 predicate(false);
10027
10028 format %{ "FCFID $dst, $src \t// convL2D" %}
10029 size(4);
10030 ins_encode %{
10031 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10032 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10033 %}
10034 ins_pipe(pipe_class_default);
10035 %}
10036
10037 // Placed here as needed in expand.
10038 instruct convD2F_reg(regF dst, regD src) %{
10039 match(Set dst (ConvD2F src));
10040 format %{ "FRSP $dst, $src \t// convD2F" %}
10041 size(4);
10042 ins_encode %{
10043 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10044 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10045 %}
10046 ins_pipe(pipe_class_default);
10047 %}
10048
10049 // Integer to Float conversion.
10050 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10051 match(Set dst (ConvI2F src));
10052 predicate(!VM_Version::has_fcfids());
10053 ins_cost(DEFAULT_COST);
10054
10055 expand %{
10056 iRegLdst tmpL;
10057 stackSlotL tmpS;
10058 regD tmpD;
10059 regD tmpD2;
10060 convI2L_reg(tmpL, src); // Sign-extension int to long.
10061 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10062 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10063 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10064 convD2F_reg(dst, tmpD2); // Convert double to float.
10065 %}
10066 %}
10067
10068 instruct convL2FRaw_regF(regF dst, regD src) %{
10069 // no match-rule, false predicate
10070 effect(DEF dst, USE src);
10071 predicate(false);
10072
10073 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10074 size(4);
10075 ins_encode %{
10076 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10077 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10078 %}
10079 ins_pipe(pipe_class_default);
10080 %}
10081
10082 // Integer to Float conversion. Special version for Power7.
10083 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10084 match(Set dst (ConvI2F src));
10085 predicate(VM_Version::has_fcfids());
10086 ins_cost(DEFAULT_COST);
10087
10088 expand %{
10089 iRegLdst tmpL;
10090 stackSlotL tmpS;
10091 regD tmpD;
10092 convI2L_reg(tmpL, src); // Sign-extension int to long.
10093 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10094 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10095 convL2FRaw_regF(dst, tmpD); // Convert to float.
10096 %}
10097 %}
10098
10099 // L2F to avoid runtime call.
10100 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10101 match(Set dst (ConvL2F src));
10102 predicate(VM_Version::has_fcfids());
10103 ins_cost(DEFAULT_COST);
10104
10105 expand %{
10106 stackSlotL tmpS;
10107 regD tmpD;
10108 regL_to_stkL(tmpS, src); // Store long to stack.
10109 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10110 convL2FRaw_regF(dst, tmpD); // Convert to float.
10111 %}
10112 %}
10113
10114 // Moved up as used in expand.
10115 //instruct convD2F_reg(regF dst, regD src) %{%}
10116
10117 // Convert to Double
10118
10119 // Integer to Double conversion.
10120 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10121 match(Set dst (ConvI2D src));
10122 ins_cost(DEFAULT_COST);
10123
10124 expand %{
10125 iRegLdst tmpL;
10126 stackSlotL tmpS;
10127 regD tmpD;
10128 convI2L_reg(tmpL, src); // Sign-extension int to long.
10129 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10130 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10131 convL2DRaw_regD(dst, tmpD); // Convert to double.
10132 %}
10133 %}
10134
10135 // Long to Double conversion
10136 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10137 match(Set dst (ConvL2D src));
10138 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10139
10140 expand %{
10141 regD tmpD;
10142 moveL2D_stack_reg(tmpD, src);
10143 convL2DRaw_regD(dst, tmpD);
10144 %}
10145 %}
10146
10147 instruct convF2D_reg(regD dst, regF src) %{
10148 match(Set dst (ConvF2D src));
10149 format %{ "FMR $dst, $src \t// float->double" %}
10150 // variable size, 0 or 4
10151 ins_encode %{
10152 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10153 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10154 %}
10155 ins_pipe(pipe_class_default);
10156 %}
10157
10158 //----------Control Flow Instructions------------------------------------------
10159 // Compare Instructions
10160
10161 // Compare Integers
10162 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10163 match(Set crx (CmpI src1 src2));
10164 size(4);
10165 format %{ "CMPW $crx, $src1, $src2" %}
10166 ins_encode %{
10167 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10168 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10169 %}
10170 ins_pipe(pipe_class_compare);
10171 %}
10172
10173 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10174 match(Set crx (CmpI src1 src2));
10175 format %{ "CMPWI $crx, $src1, $src2" %}
10176 size(4);
10177 ins_encode %{
10178 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10179 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10180 %}
10181 ins_pipe(pipe_class_compare);
10182 %}
10183
10184 // (src1 & src2) == 0?
10185 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10186 match(Set cr0 (CmpI (AndI src1 src2) zero));
10187 // r0 is killed
10188 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10189 size(4);
10190 ins_encode %{
10191 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10192 __ andi_(R0, $src1$$Register, $src2$$constant);
10193 %}
10194 ins_pipe(pipe_class_compare);
10195 %}
10196
10197 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10198 match(Set crx (CmpL src1 src2));
10199 format %{ "CMPD $crx, $src1, $src2" %}
10200 size(4);
10201 ins_encode %{
10202 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10203 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10204 %}
10205 ins_pipe(pipe_class_compare);
10206 %}
10207
10208 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10209 match(Set crx (CmpL src1 src2));
10210 format %{ "CMPDI $crx, $src1, $src2" %}
10211 size(4);
10212 ins_encode %{
10213 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10214 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10215 %}
10216 ins_pipe(pipe_class_compare);
10217 %}
10218
10219 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10220 match(Set cr0 (CmpL (AndL src1 src2) zero));
10221 // r0 is killed
10222 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10223 size(4);
10224 ins_encode %{
10225 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10226 __ and_(R0, $src1$$Register, $src2$$Register);
10227 %}
10228 ins_pipe(pipe_class_compare);
10229 %}
10230
10231 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10232 match(Set cr0 (CmpL (AndL src1 src2) zero));
10233 // r0 is killed
10234 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10235 size(4);
10236 ins_encode %{
10237 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10238 __ andi_(R0, $src1$$Register, $src2$$constant);
10239 %}
10240 ins_pipe(pipe_class_compare);
10241 %}
10242
10243 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10244 // no match-rule, false predicate
10245 effect(DEF dst, USE crx);
10246 predicate(false);
10247
10248 ins_variable_size_depending_on_alignment(true);
10249
10250 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10251 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10252 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10253 ins_encode %{
10254 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10255 Label done;
10256 // li(Rdst, 0); // equal -> 0
10257 __ beq($crx$$CondRegister, done);
10258 __ li($dst$$Register, 1); // greater -> +1
10259 __ bgt($crx$$CondRegister, done);
10260 __ li($dst$$Register, -1); // unordered or less -> -1
10261 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10262 __ bind(done);
10263 %}
10264 ins_pipe(pipe_class_compare);
10265 %}
10266
10267 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10268 // no match-rule, false predicate
10269 effect(DEF dst, USE crx);
10270 predicate(false);
10271
10272 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10273 postalloc_expand %{
10274 //
10275 // replaces
10276 //
10277 // region crx
10278 // \ |
10279 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10280 //
10281 // with
10282 //
10283 // region
10284 // \
10285 // dst=loadConI16(0)
10286 // |
10287 // ^ region crx
10288 // | \ |
10289 // dst=cmovI_conIvalueMinus1_conIvalue1
10290 //
10291
10292 // Create new nodes.
10293 MachNode *m1 = new loadConI16Node();
10294 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10295
10296 // inputs for new nodes
10297 m1->add_req(n_region);
10298 m2->add_req(n_region, n_crx);
10299 m2->add_prec(m1);
10300
10301 // operands for new nodes
10302 m1->_opnds[0] = op_dst;
10303 m1->_opnds[1] = new immI16Oper(0);
10304 m2->_opnds[0] = op_dst;
10305 m2->_opnds[1] = op_crx;
10306
10307 // registers for new nodes
10308 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10309 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10310
10311 // Insert new nodes.
10312 nodes->push(m1);
10313 nodes->push(m2);
10314 %}
10315 %}
10316
10317 // Manifest a CmpL3 result in an integer register. Very painful.
10318 // This is the test to avoid.
10319 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10320 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10321 match(Set dst (CmpL3 src1 src2));
10322 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10323
10324 expand %{
10325 flagsReg tmp1;
10326 cmpL_reg_reg(tmp1, src1, src2);
10327 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10328 %}
10329 %}
10330
10331 // Implicit range checks.
10332 // A range check in the ideal world has one of the following shapes:
10333 // - (If le (CmpU length index)), (IfTrue throw exception)
10334 // - (If lt (CmpU index length)), (IfFalse throw exception)
10335 //
10336 // Match range check 'If le (CmpU length index)'.
10337 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10338 match(If cmp (CmpU src_length index));
10339 effect(USE labl);
10340 predicate(TrapBasedRangeChecks &&
10341 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10342 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10343 (Matcher::branches_to_uncommon_trap(_leaf)));
10344
10345 ins_is_TrapBasedCheckNode(true);
10346
10347 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10348 size(4);
10349 ins_encode %{
10350 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10351 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10352 __ trap_range_check_le($src_length$$Register, $index$$constant);
10353 } else {
10354 // Both successors are uncommon traps, probability is 0.
10355 // Node got flipped during fixup flow.
10356 assert($cmp$$cmpcode == 0x9, "must be greater");
10357 __ trap_range_check_g($src_length$$Register, $index$$constant);
10358 }
10359 %}
10360 ins_pipe(pipe_class_trap);
10361 %}
10362
10363 // Match range check 'If lt (CmpU index length)'.
10364 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10365 match(If cmp (CmpU src_index src_length));
10366 effect(USE labl);
10367 predicate(TrapBasedRangeChecks &&
10368 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10369 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10370 (Matcher::branches_to_uncommon_trap(_leaf)));
10371
10372 ins_is_TrapBasedCheckNode(true);
10373
10374 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10375 size(4);
10376 ins_encode %{
10377 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10378 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10379 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10380 } else {
10381 // Both successors are uncommon traps, probability is 0.
10382 // Node got flipped during fixup flow.
10383 assert($cmp$$cmpcode == 0x8, "must be less");
10384 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10385 }
10386 %}
10387 ins_pipe(pipe_class_trap);
10388 %}
10389
10390 // Match range check 'If lt (CmpU index length)'.
10391 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10392 match(If cmp (CmpU src_index length));
10393 effect(USE labl);
10394 predicate(TrapBasedRangeChecks &&
10395 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10396 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10397 (Matcher::branches_to_uncommon_trap(_leaf)));
10398
10399 ins_is_TrapBasedCheckNode(true);
10400
10401 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10402 size(4);
10403 ins_encode %{
10404 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10405 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10406 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10407 } else {
10408 // Both successors are uncommon traps, probability is 0.
10409 // Node got flipped during fixup flow.
10410 assert($cmp$$cmpcode == 0x8, "must be less");
10411 __ trap_range_check_l($src_index$$Register, $length$$constant);
10412 }
10413 %}
10414 ins_pipe(pipe_class_trap);
10415 %}
10416
10417 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10418 match(Set crx (CmpU src1 src2));
10419 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10420 size(4);
10421 ins_encode %{
10422 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10423 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10424 %}
10425 ins_pipe(pipe_class_compare);
10426 %}
10427
10428 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10429 match(Set crx (CmpU src1 src2));
10430 size(4);
10431 format %{ "CMPLWI $crx, $src1, $src2" %}
10432 ins_encode %{
10433 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10434 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10435 %}
10436 ins_pipe(pipe_class_compare);
10437 %}
10438
10439 // Implicit zero checks (more implicit null checks).
10440 // No constant pool entries required.
10441 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10442 match(If cmp (CmpN value zero));
10443 effect(USE labl);
10444 predicate(TrapBasedNullChecks &&
10445 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10446 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10447 Matcher::branches_to_uncommon_trap(_leaf));
10448 ins_cost(1);
10449
10450 ins_is_TrapBasedCheckNode(true);
10451
10452 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10453 size(4);
10454 ins_encode %{
10455 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10456 if ($cmp$$cmpcode == 0xA) {
10457 __ trap_null_check($value$$Register);
10458 } else {
10459 // Both successors are uncommon traps, probability is 0.
10460 // Node got flipped during fixup flow.
10461 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10462 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10463 }
10464 %}
10465 ins_pipe(pipe_class_trap);
10466 %}
10467
10468 // Compare narrow oops.
10469 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10470 match(Set crx (CmpN src1 src2));
10471
10472 size(4);
10473 ins_cost(2);
10474 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10475 ins_encode %{
10476 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10477 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10478 %}
10479 ins_pipe(pipe_class_compare);
10480 %}
10481
10482 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10483 match(Set crx (CmpN src1 src2));
10484 // Make this more expensive than zeroCheckN_iReg_imm0.
10485 ins_cost(2);
10486
10487 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10488 size(4);
10489 ins_encode %{
10490 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10491 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10492 %}
10493 ins_pipe(pipe_class_compare);
10494 %}
10495
10496 // Implicit zero checks (more implicit null checks).
10497 // No constant pool entries required.
10498 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10499 match(If cmp (CmpP value zero));
10500 effect(USE labl);
10501 predicate(TrapBasedNullChecks &&
10502 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10503 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10504 Matcher::branches_to_uncommon_trap(_leaf));
10505 ins_cost(1); // Should not be cheaper than zeroCheckN.
10506
10507 ins_is_TrapBasedCheckNode(true);
10508
10509 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10510 size(4);
10511 ins_encode %{
10512 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10513 if ($cmp$$cmpcode == 0xA) {
10514 __ trap_null_check($value$$Register);
10515 } else {
10516 // Both successors are uncommon traps, probability is 0.
10517 // Node got flipped during fixup flow.
10518 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10519 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10520 }
10521 %}
10522 ins_pipe(pipe_class_trap);
10523 %}
10524
10525 // Compare Pointers
10526 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10527 match(Set crx (CmpP src1 src2));
10528 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10529 size(4);
10530 ins_encode %{
10531 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10532 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10533 %}
10534 ins_pipe(pipe_class_compare);
10535 %}
10536
10537 // Used in postalloc expand.
10538 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10539 // This match rule prevents reordering of node before a safepoint.
10540 // This only makes sense if this instructions is used exclusively
10541 // for the expansion of EncodeP!
10542 match(Set crx (CmpP src1 src2));
10543 predicate(false);
10544
10545 format %{ "CMPDI $crx, $src1, $src2" %}
10546 size(4);
10547 ins_encode %{
10548 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10549 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10550 %}
10551 ins_pipe(pipe_class_compare);
10552 %}
10553
10554 //----------Float Compares----------------------------------------------------
10555
10556 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10557 // Needs matchrule, see cmpDUnordered.
10558 match(Set crx (CmpF src1 src2));
10559 // no match-rule, false predicate
10560 predicate(false);
10561
10562 format %{ "cmpFUrd $crx, $src1, $src2" %}
10563 size(4);
10564 ins_encode %{
10565 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10566 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10567 %}
10568 ins_pipe(pipe_class_default);
10569 %}
10570
10571 instruct cmov_bns_less(flagsReg crx) %{
10572 // no match-rule, false predicate
10573 effect(DEF crx);
10574 predicate(false);
10575
10576 ins_variable_size_depending_on_alignment(true);
10577
10578 format %{ "cmov $crx" %}
10579 // Worst case is branch + move + stop, no stop without scheduler.
10580 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10581 ins_encode %{
10582 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10583 Label done;
10584 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10585 __ li(R0, 0);
10586 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10587 // TODO PPC port __ endgroup_if_needed(_size == 16);
10588 __ bind(done);
10589 %}
10590 ins_pipe(pipe_class_default);
10591 %}
10592
10593 // Compare floating, generate condition code.
10594 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10595 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10596 //
10597 // The following code sequence occurs a lot in mpegaudio:
10598 //
10599 // block BXX:
10600 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10601 // cmpFUrd CCR6, F11, F9
10602 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10603 // cmov CCR6
10604 // 8: instruct branchConSched:
10605 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10606 match(Set crx (CmpF src1 src2));
10607 ins_cost(DEFAULT_COST+BRANCH_COST);
10608
10609 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10610 postalloc_expand %{
10611 //
10612 // replaces
10613 //
10614 // region src1 src2
10615 // \ | |
10616 // crx=cmpF_reg_reg
10617 //
10618 // with
10619 //
10620 // region src1 src2
10621 // \ | |
10622 // crx=cmpFUnordered_reg_reg
10623 // |
10624 // ^ region
10625 // | \
10626 // crx=cmov_bns_less
10627 //
10628
10629 // Create new nodes.
10630 MachNode *m1 = new cmpFUnordered_reg_regNode();
10631 MachNode *m2 = new cmov_bns_lessNode();
10632
10633 // inputs for new nodes
10634 m1->add_req(n_region, n_src1, n_src2);
10635 m2->add_req(n_region);
10636 m2->add_prec(m1);
10637
10638 // operands for new nodes
10639 m1->_opnds[0] = op_crx;
10640 m1->_opnds[1] = op_src1;
10641 m1->_opnds[2] = op_src2;
10642 m2->_opnds[0] = op_crx;
10643
10644 // registers for new nodes
10645 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10646 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10647
10648 // Insert new nodes.
10649 nodes->push(m1);
10650 nodes->push(m2);
10651 %}
10652 %}
10653
10654 // Compare float, generate -1,0,1
10655 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10656 match(Set dst (CmpF3 src1 src2));
10657 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10658
10659 expand %{
10660 flagsReg tmp1;
10661 cmpFUnordered_reg_reg(tmp1, src1, src2);
10662 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10663 %}
10664 %}
10665
10666 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10667 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10668 // node right before the conditional move using it.
10669 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10670 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10671 // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10672 // conditional move was supposed to be spilled.
10673 match(Set crx (CmpD src1 src2));
10674 // False predicate, shall not be matched.
10675 predicate(false);
10676
10677 format %{ "cmpFUrd $crx, $src1, $src2" %}
10678 size(4);
10679 ins_encode %{
10680 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10681 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10682 %}
10683 ins_pipe(pipe_class_default);
10684 %}
10685
10686 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10687 match(Set crx (CmpD src1 src2));
10688 ins_cost(DEFAULT_COST+BRANCH_COST);
10689
10690 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10691 postalloc_expand %{
10692 //
10693 // replaces
10694 //
10695 // region src1 src2
10696 // \ | |
10697 // crx=cmpD_reg_reg
10698 //
10699 // with
10700 //
10701 // region src1 src2
10702 // \ | |
10703 // crx=cmpDUnordered_reg_reg
10704 // |
10705 // ^ region
10706 // | \
10707 // crx=cmov_bns_less
10708 //
10709
10710 // create new nodes
10711 MachNode *m1 = new cmpDUnordered_reg_regNode();
10712 MachNode *m2 = new cmov_bns_lessNode();
10713
10714 // inputs for new nodes
10715 m1->add_req(n_region, n_src1, n_src2);
10716 m2->add_req(n_region);
10717 m2->add_prec(m1);
10718
10719 // operands for new nodes
10720 m1->_opnds[0] = op_crx;
10721 m1->_opnds[1] = op_src1;
10722 m1->_opnds[2] = op_src2;
10723 m2->_opnds[0] = op_crx;
10724
10725 // registers for new nodes
10726 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10727 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10728
10729 // Insert new nodes.
10730 nodes->push(m1);
10731 nodes->push(m2);
10732 %}
10733 %}
10734
10735 // Compare double, generate -1,0,1
10736 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10737 match(Set dst (CmpD3 src1 src2));
10738 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10739
10740 expand %{
10741 flagsReg tmp1;
10742 cmpDUnordered_reg_reg(tmp1, src1, src2);
10743 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10744 %}
10745 %}
10746
10747 //----------Branches---------------------------------------------------------
10748 // Jump
10749
10750 // Direct Branch.
10751 instruct branch(label labl) %{
10752 match(Goto);
10753 effect(USE labl);
10754 ins_cost(BRANCH_COST);
10755
10756 format %{ "B $labl" %}
10757 size(4);
10758 ins_encode %{
10759 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10760 Label d; // dummy
10761 __ bind(d);
10762 Label* p = $labl$$label;
10763 // `p' is `NULL' when this encoding class is used only to
10764 // determine the size of the encoded instruction.
10765 Label& l = (NULL == p)? d : *(p);
10766 __ b(l);
10767 %}
10768 ins_pipe(pipe_class_default);
10769 %}
10770
10771 // Conditional Near Branch
10772 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10773 // Same match rule as `branchConFar'.
10774 match(If cmp crx);
10775 effect(USE lbl);
10776 ins_cost(BRANCH_COST);
10777
10778 // If set to 1 this indicates that the current instruction is a
10779 // short variant of a long branch. This avoids using this
10780 // instruction in first-pass matching. It will then only be used in
10781 // the `Shorten_branches' pass.
10782 ins_short_branch(1);
10783
10784 format %{ "B$cmp $crx, $lbl" %}
10785 size(4);
10786 ins_encode( enc_bc(crx, cmp, lbl) );
10787 ins_pipe(pipe_class_default);
10788 %}
10789
10790 // This is for cases when the ppc64 `bc' instruction does not
10791 // reach far enough. So we emit a far branch here, which is more
10792 // expensive.
10793 //
10794 // Conditional Far Branch
10795 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10796 // Same match rule as `branchCon'.
10797 match(If cmp crx);
10798 effect(USE crx, USE lbl);
10799 predicate(!false /* TODO: PPC port HB_Schedule*/);
10800 // Higher cost than `branchCon'.
10801 ins_cost(5*BRANCH_COST);
10802
10803 // This is not a short variant of a branch, but the long variant.
10804 ins_short_branch(0);
10805
10806 format %{ "B_FAR$cmp $crx, $lbl" %}
10807 size(8);
10808 ins_encode( enc_bc_far(crx, cmp, lbl) );
10809 ins_pipe(pipe_class_default);
10810 %}
10811
10812 // Conditional Branch used with Power6 scheduler (can be far or short).
10813 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10814 // Same match rule as `branchCon'.
10815 match(If cmp crx);
10816 effect(USE crx, USE lbl);
10817 predicate(false /* TODO: PPC port HB_Schedule*/);
10818 // Higher cost than `branchCon'.
10819 ins_cost(5*BRANCH_COST);
10820
10821 // Actually size doesn't depend on alignment but on shortening.
10822 ins_variable_size_depending_on_alignment(true);
10823 // long variant.
10824 ins_short_branch(0);
10825
10826 format %{ "B_FAR$cmp $crx, $lbl" %}
10827 size(8); // worst case
10828 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10829 ins_pipe(pipe_class_default);
10830 %}
10831
10832 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10833 match(CountedLoopEnd cmp crx);
10834 effect(USE labl);
10835 ins_cost(BRANCH_COST);
10836
10837 // short variant.
10838 ins_short_branch(1);
10839
10840 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10841 size(4);
10842 ins_encode( enc_bc(crx, cmp, labl) );
10843 ins_pipe(pipe_class_default);
10844 %}
10845
10846 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10847 match(CountedLoopEnd cmp crx);
10848 effect(USE labl);
10849 predicate(!false /* TODO: PPC port HB_Schedule */);
10850 ins_cost(BRANCH_COST);
10851
10852 // Long variant.
10853 ins_short_branch(0);
10854
10855 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10856 size(8);
10857 ins_encode( enc_bc_far(crx, cmp, labl) );
10858 ins_pipe(pipe_class_default);
10859 %}
10860
10861 // Conditional Branch used with Power6 scheduler (can be far or short).
10862 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10863 match(CountedLoopEnd cmp crx);
10864 effect(USE labl);
10865 predicate(false /* TODO: PPC port HB_Schedule */);
10866 // Higher cost than `branchCon'.
10867 ins_cost(5*BRANCH_COST);
10868
10869 // Actually size doesn't depend on alignment but on shortening.
10870 ins_variable_size_depending_on_alignment(true);
10871 // Long variant.
10872 ins_short_branch(0);
10873
10874 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10875 size(8); // worst case
10876 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10877 ins_pipe(pipe_class_default);
10878 %}
10879
10880 // ============================================================================
10881 // Java runtime operations, intrinsics and other complex operations.
10882
10883 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10884 // array for an instance of the superklass. Set a hidden internal cache on a
10885 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10886 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10887 //
10888 // GL TODO: Improve this.
10889 // - result should not be a TEMP
10890 // - Add match rule as on sparc avoiding additional Cmp.
10891 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10892 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10893 match(Set result (PartialSubtypeCheck subklass superklass));
10894 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10895 ins_cost(DEFAULT_COST*10);
10896
10897 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10898 ins_encode %{
10899 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10900 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10901 $tmp_klass$$Register, NULL, $result$$Register);
10902 %}
10903 ins_pipe(pipe_class_default);
10904 %}
10905
10906 // inlined locking and unlocking
10907
10908 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{
10909 match(Set crx (FastLock oop box));
10910 effect(TEMP tmp1, TEMP tmp2);
10911 predicate(!Compile::current()->use_rtm());
10912
10913 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2" %}
10914 ins_encode %{
10915 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10916 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10917 $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0,
10918 UseBiasedLocking && !UseOptoBiasInlining);
10919 // If locking was successfull, crx should indicate 'EQ'.
10920 // The compiler generates a branch to the runtime call to
10921 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10922 %}
10923 ins_pipe(pipe_class_compare);
10924 %}
10925
10926 // Separate version for TM. Use bound register for box to enable USE_KILL.
10927 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10928 match(Set crx (FastLock oop box));
10929 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10930 predicate(Compile::current()->use_rtm());
10931
10932 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10933 ins_encode %{
10934 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10935 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10936 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10937 /*Biased Locking*/ false,
10938 _rtm_counters, _stack_rtm_counters,
10939 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10940 /*TM*/ true, ra_->C->profile_rtm());
10941 // If locking was successfull, crx should indicate 'EQ'.
10942 // The compiler generates a branch to the runtime call to
10943 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10944 %}
10945 ins_pipe(pipe_class_compare);
10946 %}
10947
10948 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10949 match(Set crx (FastUnlock oop box));
10950 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10951 predicate(!Compile::current()->use_rtm());
10952
10953 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10954 ins_encode %{
10955 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10956 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10957 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10958 UseBiasedLocking && !UseOptoBiasInlining,
10959 false);
10960 // If unlocking was successfull, crx should indicate 'EQ'.
10961 // The compiler generates a branch to the runtime call to
10962 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10963 %}
10964 ins_pipe(pipe_class_compare);
10965 %}
10966
10967 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10968 match(Set crx (FastUnlock oop box));
10969 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10970 predicate(Compile::current()->use_rtm());
10971
10972 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %}
10973 ins_encode %{
10974 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10975 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10976 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10977 /*Biased Locking*/ false, /*TM*/ true);
10978 // If unlocking was successfull, crx should indicate 'EQ'.
10979 // The compiler generates a branch to the runtime call to
10980 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10981 %}
10982 ins_pipe(pipe_class_compare);
10983 %}
10984
10985 // Align address.
10986 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10987 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10988
10989 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10990 size(4);
10991 ins_encode %{
10992 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10993 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10994 %}
10995 ins_pipe(pipe_class_default);
10996 %}
10997
10998 // Array size computation.
10999 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11000 match(Set dst (SubL (CastP2X end) (CastP2X start)));
11001
11002 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
11003 size(4);
11004 ins_encode %{
11005 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11006 __ subf($dst$$Register, $start$$Register, $end$$Register);
11007 %}
11008 ins_pipe(pipe_class_default);
11009 %}
11010
11011 // Clear-array with dynamic array-size.
11012 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11013 match(Set dummy (ClearArray cnt base));
11014 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11015 ins_cost(MEMORY_REF_COST);
11016
11017 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11018
11019 format %{ "ClearArray $cnt, $base" %}
11020 ins_encode %{
11021 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11022 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11023 %}
11024 ins_pipe(pipe_class_default);
11025 %}
11026
11027 instruct string_compareL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11028 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11029 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11030 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11031 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11032 ins_cost(300);
11033 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11034 ins_encode %{
11035 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11036 __ string_compare($str1$$Register, $str2$$Register,
11037 $cnt1$$Register, $cnt2$$Register,
11038 $tmp$$Register,
11039 $result$$Register, StrIntrinsicNode::LL);
11040 %}
11041 ins_pipe(pipe_class_default);
11042 %}
11043
11044 instruct string_compareU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11045 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11046 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11047 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11048 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11049 ins_cost(300);
11050 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11051 ins_encode %{
11052 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11053 __ string_compare($str1$$Register, $str2$$Register,
11054 $cnt1$$Register, $cnt2$$Register,
11055 $tmp$$Register,
11056 $result$$Register, StrIntrinsicNode::UU);
11057 %}
11058 ins_pipe(pipe_class_default);
11059 %}
11060
11061 instruct string_compareLU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11062 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11063 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11064 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11065 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11066 ins_cost(300);
11067 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11068 ins_encode %{
11069 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11070 __ string_compare($str1$$Register, $str2$$Register,
11071 $cnt1$$Register, $cnt2$$Register,
11072 $tmp$$Register,
11073 $result$$Register, StrIntrinsicNode::LU);
11074 %}
11075 ins_pipe(pipe_class_default);
11076 %}
11077
11078 instruct string_compareUL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11079 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11080 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11081 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11082 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11083 ins_cost(300);
11084 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11085 ins_encode %{
11086 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11087 __ string_compare($str2$$Register, $str1$$Register,
11088 $cnt2$$Register, $cnt1$$Register,
11089 $tmp$$Register,
11090 $result$$Register, StrIntrinsicNode::UL);
11091 %}
11092 ins_pipe(pipe_class_default);
11093 %}
11094
11095 instruct string_equalsL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
11096 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11097 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11098 match(Set result (StrEquals (Binary str1 str2) cnt));
11099 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
11100 ins_cost(300);
11101 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
11102 ins_encode %{
11103 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11104 __ array_equals(false, $str1$$Register, $str2$$Register,
11105 $cnt$$Register, $tmp$$Register,
11106 $result$$Register, true /* byte */);
11107 %}
11108 ins_pipe(pipe_class_default);
11109 %}
11110
11111 instruct string_equalsU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
11112 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11113 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
11114 match(Set result (StrEquals (Binary str1 str2) cnt));
11115 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
11116 ins_cost(300);
11117 format %{ "String Equals char[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
11118 ins_encode %{
11119 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11120 __ array_equals(false, $str1$$Register, $str2$$Register,
11121 $cnt$$Register, $tmp$$Register,
11122 $result$$Register, false /* byte */);
11123 %}
11124 ins_pipe(pipe_class_default);
11125 %}
11126
11127 instruct array_equalsB(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
11128 iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
11129 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11130 match(Set result (AryEq ary1 ary2));
11131 effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
11132 ins_cost(300);
11133 format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
11134 ins_encode %{
11135 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11136 __ array_equals(true, $ary1$$Register, $ary2$$Register,
11137 $tmp1$$Register, $tmp2$$Register,
11138 $result$$Register, true /* byte */);
11139 %}
11140 ins_pipe(pipe_class_default);
11141 %}
11142
11143 instruct array_equalsC(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
11144 iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
11145 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11146 match(Set result (AryEq ary1 ary2));
11147 effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
11148 ins_cost(300);
11149 format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
11150 ins_encode %{
11151 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11152 __ array_equals(true, $ary1$$Register, $ary2$$Register,
11153 $tmp1$$Register, $tmp2$$Register,
11154 $result$$Register, false /* byte */);
11155 %}
11156 ins_pipe(pipe_class_default);
11157 %}
11158
11159 instruct indexOf_imm1_char_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11160 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11161 iRegIdst tmp1, iRegIdst tmp2,
11162 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11163 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11164 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11165 // Required for EA: check if it is still a type_array.
11166 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11167 ins_cost(150);
11168
11169 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11170 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11171
11172 ins_encode %{
11173 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11174 immPOper *needleOper = (immPOper *)$needleImm;
11175 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11176 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11177 jchar chr;
11178 #ifdef VM_LITTLE_ENDIAN
11179 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11180 ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11181 #else
11182 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11183 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11184 #endif
11185 __ string_indexof_char($result$$Register,
11186 $haystack$$Register, $haycnt$$Register,
11187 R0, chr,
11188 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11189 %}
11190 ins_pipe(pipe_class_compare);
11191 %}
11192
11193 instruct indexOf_imm1_char_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11194 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11195 iRegIdst tmp1, iRegIdst tmp2,
11196 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11197 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11198 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11199 // Required for EA: check if it is still a type_array.
11200 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11201 ins_cost(150);
11202
11203 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11204 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11205
11206 ins_encode %{
11207 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11208 immPOper *needleOper = (immPOper *)$needleImm;
11209 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11210 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11211 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11212 __ string_indexof_char($result$$Register,
11213 $haystack$$Register, $haycnt$$Register,
11214 R0, chr,
11215 $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
11216 %}
11217 ins_pipe(pipe_class_compare);
11218 %}
11219
11220 instruct indexOf_imm1_char_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11221 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11222 iRegIdst tmp1, iRegIdst tmp2,
11223 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11224 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11225 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11226 // Required for EA: check if it is still a type_array.
11227 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11228 ins_cost(150);
11229
11230 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11231 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11232
11233 ins_encode %{
11234 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11235 immPOper *needleOper = (immPOper *)$needleImm;
11236 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11237 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11238 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11239 __ string_indexof_char($result$$Register,
11240 $haystack$$Register, $haycnt$$Register,
11241 R0, chr,
11242 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11243 %}
11244 ins_pipe(pipe_class_compare);
11245 %}
11246
11247 instruct indexOf_imm1_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11248 rscratch2RegP needle, immI_1 needlecntImm,
11249 iRegIdst tmp1, iRegIdst tmp2,
11250 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11251 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11252 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11253 // Required for EA: check if it is still a type_array.
11254 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
11255 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11256 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11257 ins_cost(180);
11258
11259 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11260 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11261 ins_encode %{
11262 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11263 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11264 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11265 guarantee(needle_values, "sanity");
11266 jchar chr;
11267 #ifdef VM_LITTLE_ENDIAN
11268 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11269 ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11270 #else
11271 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11272 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11273 #endif
11274 __ string_indexof_char($result$$Register,
11275 $haystack$$Register, $haycnt$$Register,
11276 R0, chr,
11277 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11278 %}
11279 ins_pipe(pipe_class_compare);
11280 %}
11281
11282 instruct indexOf_imm1_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11283 rscratch2RegP needle, immI_1 needlecntImm,
11284 iRegIdst tmp1, iRegIdst tmp2,
11285 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11286 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11287 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11288 // Required for EA: check if it is still a type_array.
11289 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
11290 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11291 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11292 ins_cost(180);
11293
11294 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11295 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11296 ins_encode %{
11297 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11298 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11299 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11300 guarantee(needle_values, "sanity");
11301 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11302 __ string_indexof_char($result$$Register,
11303 $haystack$$Register, $haycnt$$Register,
11304 R0, chr,
11305 $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
11306 %}
11307 ins_pipe(pipe_class_compare);
11308 %}
11309
11310 instruct indexOf_imm1_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11311 rscratch2RegP needle, immI_1 needlecntImm,
11312 iRegIdst tmp1, iRegIdst tmp2,
11313 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11314 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11315 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11316 // Required for EA: check if it is still a type_array.
11317 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
11318 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11319 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11320 ins_cost(180);
11321
11322 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11323 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11324 ins_encode %{
11325 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11326 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11327 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11328 guarantee(needle_values, "sanity");
11329 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11330 __ string_indexof_char($result$$Register,
11331 $haystack$$Register, $haycnt$$Register,
11332 R0, chr,
11333 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11334 %}
11335 ins_pipe(pipe_class_compare);
11336 %}
11337
11338 instruct indexOfChar_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11339 iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
11340 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11341 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
11342 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11343 predicate(CompactStrings);
11344 ins_cost(180);
11345
11346 format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
11347 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11348 ins_encode %{
11349 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11350 __ string_indexof_char($result$$Register,
11351 $haystack$$Register, $haycnt$$Register,
11352 $ch$$Register, 0 /* this is not used if the character is already in a register */,
11353 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11354 %}
11355 ins_pipe(pipe_class_compare);
11356 %}
11357
11358 instruct indexOf_imm_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11359 iRegPsrc needle, uimmI15 needlecntImm,
11360 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11361 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11362 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11363 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11364 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11365 // Required for EA: check if it is still a type_array.
11366 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
11367 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11368 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11369 ins_cost(250);
11370
11371 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11372 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11373 ins_encode %{
11374 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11375 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11376 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11377
11378 __ string_indexof($result$$Register,
11379 $haystack$$Register, $haycnt$$Register,
11380 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11381 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
11382 %}
11383 ins_pipe(pipe_class_compare);
11384 %}
11385
11386 instruct indexOf_imm_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11387 iRegPsrc needle, uimmI15 needlecntImm,
11388 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11389 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11390 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11391 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11392 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11393 // Required for EA: check if it is still a type_array.
11394 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
11395 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11396 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11397 ins_cost(250);
11398
11399 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11400 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11401 ins_encode %{
11402 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11403 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11404 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11405
11406 __ string_indexof($result$$Register,
11407 $haystack$$Register, $haycnt$$Register,
11408 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11409 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
11410 %}
11411 ins_pipe(pipe_class_compare);
11412 %}
11413
11414 instruct indexOf_imm_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11415 iRegPsrc needle, uimmI15 needlecntImm,
11416 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11417 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11418 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11419 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11420 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11421 // Required for EA: check if it is still a type_array.
11422 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
11423 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11424 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11425 ins_cost(250);
11426
11427 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11428 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11429 ins_encode %{
11430 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11431 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11432 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11433
11434 __ string_indexof($result$$Register,
11435 $haystack$$Register, $haycnt$$Register,
11436 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11437 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
11438 %}
11439 ins_pipe(pipe_class_compare);
11440 %}
11441
11442 instruct indexOf_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11443 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11444 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11445 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11446 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11447 TEMP_DEF result,
11448 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11449 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11450 ins_cost(300);
11451
11452 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11453 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11454 ins_encode %{
11455 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11456 __ string_indexof($result$$Register,
11457 $haystack$$Register, $haycnt$$Register,
11458 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11459 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
11460 %}
11461 ins_pipe(pipe_class_compare);
11462 %}
11463
11464 instruct indexOf_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11465 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11466 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11467 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11468 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11469 TEMP_DEF result,
11470 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11471 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11472 ins_cost(300);
11473
11474 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11475 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11476 ins_encode %{
11477 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11478 __ string_indexof($result$$Register,
11479 $haystack$$Register, $haycnt$$Register,
11480 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11481 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
11482 %}
11483 ins_pipe(pipe_class_compare);
11484 %}
11485
11486 instruct indexOf_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11487 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11488 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11489 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11490 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11491 TEMP_DEF result,
11492 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11493 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11494 ins_cost(300);
11495
11496 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11497 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11498 ins_encode %{
11499 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11500 __ string_indexof($result$$Register,
11501 $haystack$$Register, $haycnt$$Register,
11502 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11503 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
11504 %}
11505 ins_pipe(pipe_class_compare);
11506 %}
11507
11508 // char[] to byte[] compression
11509 instruct string_compress(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
11510 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11511 match(Set result (StrCompressedCopy src (Binary dst len)));
11512 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11513 USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11514 ins_cost(300);
11515 format %{ "String Compress $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11516 ins_encode %{
11517 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11518 Label Lskip, Ldone;
11519 __ li($result$$Register, 0);
11520 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
11521 $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Ldone);
11522 __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
11523 __ beq(CCR0, Lskip);
11524 __ string_compress($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register, Ldone);
11525 __ bind(Lskip);
11526 __ mr($result$$Register, $len$$Register);
11527 __ bind(Ldone);
11528 %}
11529 ins_pipe(pipe_class_default);
11530 %}
11531
11532 // byte[] to char[] inflation
11533 instruct string_inflate(Universe dummy, rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegLdst tmp1,
11534 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11535 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11536 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11537 ins_cost(300);
11538 format %{ "String Inflate $src,$dst,$len \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11539 ins_encode %{
11540 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11541 Label Ldone;
11542 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
11543 $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11544 __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
11545 __ beq(CCR0, Ldone);
11546 __ string_inflate($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register);
11547 __ bind(Ldone);
11548 %}
11549 ins_pipe(pipe_class_default);
11550 %}
11551
11552 // StringCoding.java intrinsics
11553 instruct has_negatives(rarg1RegP ary1, iRegIsrc len, iRegIdst result, iRegLdst tmp1, iRegLdst tmp2,
11554 regCTR ctr, flagsRegCR0 cr0)
11555 %{
11556 match(Set result (HasNegatives ary1 len));
11557 effect(TEMP_DEF result, USE_KILL ary1, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0);
11558 ins_cost(300);
11559 format %{ "has negatives byte[] $ary1,$len -> $result \t// KILL $tmp1, $tmp2" %}
11560 ins_encode %{
11561 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11562 __ has_negatives($ary1$$Register, $len$$Register, $result$$Register,
11563 $tmp1$$Register, $tmp2$$Register);
11564 %}
11565 ins_pipe(pipe_class_default);
11566 %}
11567
11568 // encode char[] to byte[] in ISO_8859_1
11569 instruct encode_iso_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
11570 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11571 match(Set result (EncodeISOArray src (Binary dst len)));
11572 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11573 USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11574 ins_cost(300);
11575 format %{ "Encode array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11576 ins_encode %{
11577 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11578 Label Lslow, Lfailure1, Lfailure2, Ldone;
11579 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
11580 $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Lfailure1);
11581 __ rldicl_($result$$Register, $len$$Register, 0, 64-3); // Remaining characters.
11582 __ beq(CCR0, Ldone);
11583 __ bind(Lslow);
11584 __ string_compress($src$$Register, $dst$$Register, $result$$Register, $tmp2$$Register, Lfailure2);
11585 __ li($result$$Register, 0);
11586 __ b(Ldone);
11587
11588 __ bind(Lfailure1);
11589 __ mr($result$$Register, $len$$Register);
11590 __ mfctr($tmp1$$Register);
11591 __ rldimi_($result$$Register, $tmp1$$Register, 3, 0); // Remaining characters.
11592 __ beq(CCR0, Ldone);
11593 __ b(Lslow);
11594
11595 __ bind(Lfailure2);
11596 __ mfctr($result$$Register); // Remaining characters.
11597
11598 __ bind(Ldone);
11599 __ subf($result$$Register, $result$$Register, $len$$Register);
11600 %}
11601 ins_pipe(pipe_class_default);
11602 %}
11603
11604
11605 // String_IndexOf for needle of length 1.
11606 //
11607 // Match needle into immediate operands: no loadConP node needed. Saves one
11608 // register and two instructions over string_indexOf_imm1Node.
11609 //
11610 // Assumes register result differs from all input registers.
11611 //
11612 // Preserves registers haystack, haycnt
11613 // Kills registers tmp1, tmp2
11614 // Defines registers result
11615 //
11616 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11617 //
11618 // Unfortunately this does not match too often. In many situations the AddP is used
11619 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11620 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11621 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11622 iRegIdst tmp1, iRegIdst tmp2,
11623 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11624 predicate(SpecialStringIndexOf && !CompactStrings); // type check implicit by parameter type, See Matcher::match_rule_supported
11625 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11626
11627 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11628
11629 ins_cost(150);
11630 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11631 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11632
11633 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11634 ins_encode %{
11635 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11636 immPOper *needleOper = (immPOper *)$needleImm;
11637 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11638 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11639 jchar chr;
11640 if (java_lang_String::has_coder_field()) {
11641 // New compact strings byte array strings
11642 #ifdef VM_LITTLE_ENDIAN
11643 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11644 ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11645 #else
11646 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11647 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11648 #endif
11649 } else {
11650 // Old char array strings
11651 chr = needle_values->char_at(0);
11652 }
11653 __ string_indexof_1($result$$Register,
11654 $haystack$$Register, $haycnt$$Register,
11655 R0, chr,
11656 $tmp1$$Register, $tmp2$$Register);
11657 %}
11658 ins_pipe(pipe_class_compare);
11659 %}
11660
11661 // String_IndexOf for needle of length 1.
11662 //
11663 // Special case requires less registers and emits less instructions.
11664 //
11665 // Assumes register result differs from all input registers.
11666 //
11667 // Preserves registers haystack, haycnt
11668 // Kills registers tmp1, tmp2, needle
11669 // Defines registers result
11670 //
11671 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11672 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11673 rscratch2RegP needle, immI_1 needlecntImm,
11674 iRegIdst tmp1, iRegIdst tmp2,
11675 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11676 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11677 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11678 TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11679 // Required for EA: check if it is still a type_array.
11680 predicate(SpecialStringIndexOf && !CompactStrings &&
11681 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11682 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11683 ins_cost(180);
11684
11685 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11686
11687 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11688 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11689 ins_encode %{
11690 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11691 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11692 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11693 guarantee(needle_values, "sanity");
11694 jchar chr;
11695 if (java_lang_String::has_coder_field()) {
11696 // New compact strings byte array strings
11697 #ifdef VM_LITTLE_ENDIAN
11698 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11699 ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11700 #else
11701 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11702 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11703 #endif
11704 } else {
11705 // Old char array strings
11706 chr = needle_values->char_at(0);
11707 }
11708 __ string_indexof_1($result$$Register,
11709 $haystack$$Register, $haycnt$$Register,
11710 R0, chr,
11711 $tmp1$$Register, $tmp2$$Register);
11712 %}
11713 ins_pipe(pipe_class_compare);
11714 %}
11715
11716 // String_IndexOfChar
11717 //
11718 // Assumes register result differs from all input registers.
11719 //
11720 // Preserves registers haystack, haycnt
11721 // Kills registers tmp1, tmp2
11722 // Defines registers result
11723 //
11724 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11725 instruct string_indexOfChar(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11726 iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
11727 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11728 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
11729 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11730 predicate(SpecialStringIndexOf && !CompactStrings);
11731 ins_cost(180);
11732
11733 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11734
11735 format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
11736 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11737 ins_encode %{
11738 __ string_indexof_1($result$$Register,
11739 $haystack$$Register, $haycnt$$Register,
11740 $ch$$Register, 0 /* this is not used if the character is already in a register */,
11741 $tmp1$$Register, $tmp2$$Register);
11742 %}
11743 ins_pipe(pipe_class_compare);
11744 %}
11745
11746 // String_IndexOf.
11747 //
11748 // Length of needle as immediate. This saves instruction loading constant needle
11749 // length.
11750 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11751 // completely or do it in vector instruction. This should save registers for
11752 // needlecnt and needle.
11753 //
11754 // Assumes register result differs from all input registers.
11755 // Overwrites haycnt, needlecnt.
11756 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11757 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11758 iRegPsrc needle, uimmI15 needlecntImm,
11759 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11760 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11761 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11762 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11763 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11764 // Required for EA: check if it is still a type_array.
11765 predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11766 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11767 ins_cost(250);
11768
11769 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11770
11771 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11772 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11773 ins_encode %{
11774 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11775 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11776 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11777
11778 __ string_indexof($result$$Register,
11779 $haystack$$Register, $haycnt$$Register,
11780 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11781 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11782 %}
11783 ins_pipe(pipe_class_compare);
11784 %}
11785
11786 // StrIndexOf node.
11787 //
11788 // Assumes register result differs from all input registers.
11789 // Overwrites haycnt, needlecnt.
11790 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11791 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11792 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11793 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11794 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11795 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11796 TEMP_DEF result,
11797 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11798 predicate(SpecialStringIndexOf && !CompactStrings); // See Matcher::match_rule_supported.
11799 ins_cost(300);
11800
11801 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11802
11803 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11804 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11805 ins_encode %{
11806 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11807 __ string_indexof($result$$Register,
11808 $haystack$$Register, $haycnt$$Register,
11809 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11810 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11811 %}
11812 ins_pipe(pipe_class_compare);
11813 %}
11814
11815 // String equals with immediate.
11816 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11817 iRegPdst tmp1, iRegPdst tmp2,
11818 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11819 match(Set result (StrEquals (Binary str1 str2) cntImm));
11820 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11821 KILL cr0, KILL cr6, KILL ctr);
11822 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported.
11823 ins_cost(250);
11824
11825 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11826
11827 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11828 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11829 ins_encode %{
11830 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11831 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11832 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11833 %}
11834 ins_pipe(pipe_class_compare);
11835 %}
11836
11837 // String equals.
11838 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11839 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11840 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11841 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11842 match(Set result (StrEquals (Binary str1 str2) cnt));
11843 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11844 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11845 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported.
11846 ins_cost(300);
11847
11848 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11849
11850 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11851 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11852 ins_encode %{
11853 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11854 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11855 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11856 %}
11857 ins_pipe(pipe_class_compare);
11858 %}
11859
11860 // String compare.
11861 // Char[] pointers are passed in.
11862 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11863 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11864 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11865 predicate(!CompactStrings);
11866 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11867 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11868 ins_cost(300);
11869
11870 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11871
11872 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11873 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11874 ins_encode %{
11875 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11876 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11877 $result$$Register, $tmp$$Register);
11878 %}
11879 ins_pipe(pipe_class_compare);
11880 %}
11881
11882 //---------- Min/Max Instructions ---------------------------------------------
11883
11884 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11885 match(Set dst (MinI src1 src2));
11886 ins_cost(DEFAULT_COST*6);
11887
11888 expand %{
11889 iRegLdst src1s;
11890 iRegLdst src2s;
11891 iRegLdst diff;
11892 iRegLdst sm;
11893 iRegLdst doz; // difference or zero
11894 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11895 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11896 subL_reg_reg(diff, src2s, src1s);
11897 // Need to consider >=33 bit result, therefore we need signmaskL.
11898 signmask64L_regL(sm, diff);
11899 andL_reg_reg(doz, diff, sm); // <=0
11900 addI_regL_regL(dst, doz, src1s);
11901 %}
11902 %}
11903
11904 instruct minI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
11905 match(Set dst (MinI src1 src2));
11906 effect(KILL cr0);
11907 predicate(VM_Version::has_isel());
11908 ins_cost(DEFAULT_COST*2);
11909
11910 ins_encode %{
11911 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11912 __ cmpw(CCR0, $src1$$Register, $src2$$Register);
11913 __ isel($dst$$Register, CCR0, Assembler::less, /*invert*/false, $src1$$Register, $src2$$Register);
11914 %}
11915 ins_pipe(pipe_class_default);
11916 %}
11917
11918 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11919 match(Set dst (MaxI src1 src2));
11920 ins_cost(DEFAULT_COST*6);
11921
11922 expand %{
11923 iRegLdst src1s;
11924 iRegLdst src2s;
11925 iRegLdst diff;
11926 iRegLdst sm;
11927 iRegLdst doz; // difference or zero
11928 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11929 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11930 subL_reg_reg(diff, src2s, src1s);
11931 // Need to consider >=33 bit result, therefore we need signmaskL.
11932 signmask64L_regL(sm, diff);
11933 andcL_reg_reg(doz, diff, sm); // >=0
11934 addI_regL_regL(dst, doz, src1s);
11935 %}
11936 %}
11937
11938 instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
11939 match(Set dst (MaxI src1 src2));
11940 effect(KILL cr0);
11941 predicate(VM_Version::has_isel());
11942 ins_cost(DEFAULT_COST*2);
11943
11944 ins_encode %{
11945 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11946 __ cmpw(CCR0, $src1$$Register, $src2$$Register);
11947 __ isel($dst$$Register, CCR0, Assembler::greater, /*invert*/false, $src1$$Register, $src2$$Register);
11948 %}
11949 ins_pipe(pipe_class_default);
11950 %}
11951
11952 //---------- Population Count Instructions ------------------------------------
11953
11954 // Popcnt for Power7.
11955 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11956 match(Set dst (PopCountI src));
11957 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11958 ins_cost(DEFAULT_COST);
11959
11960 format %{ "POPCNTW $dst, $src" %}
11961 size(4);
11962 ins_encode %{
11963 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11964 __ popcntw($dst$$Register, $src$$Register);
11965 %}
11966 ins_pipe(pipe_class_default);
11967 %}
11968
11969 // Popcnt for Power7.
11970 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11971 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11972 match(Set dst (PopCountL src));
11973 ins_cost(DEFAULT_COST);
11974
11975 format %{ "POPCNTD $dst, $src" %}
11976 size(4);
11977 ins_encode %{
11978 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11979 __ popcntd($dst$$Register, $src$$Register);
11980 %}
11981 ins_pipe(pipe_class_default);
11982 %}
11983
11984 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11985 match(Set dst (CountLeadingZerosI src));
11986 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11987 ins_cost(DEFAULT_COST);
11988
11989 format %{ "CNTLZW $dst, $src" %}
11990 size(4);
11991 ins_encode %{
11992 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11993 __ cntlzw($dst$$Register, $src$$Register);
11994 %}
11995 ins_pipe(pipe_class_default);
11996 %}
11997
11998 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11999 match(Set dst (CountLeadingZerosL src));
12000 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
12001 ins_cost(DEFAULT_COST);
12002
12003 format %{ "CNTLZD $dst, $src" %}
12004 size(4);
12005 ins_encode %{
12006 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12007 __ cntlzd($dst$$Register, $src$$Register);
12008 %}
12009 ins_pipe(pipe_class_default);
12010 %}
12011
12012 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
12013 // no match-rule, false predicate
12014 effect(DEF dst, USE src);
12015 predicate(false);
12016
12017 format %{ "CNTLZD $dst, $src" %}
12018 size(4);
12019 ins_encode %{
12020 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12021 __ cntlzd($dst$$Register, $src$$Register);
12022 %}
12023 ins_pipe(pipe_class_default);
12024 %}
12025
12026 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
12027 match(Set dst (CountTrailingZerosI src));
12028 predicate(UseCountLeadingZerosInstructionsPPC64);
12029 ins_cost(DEFAULT_COST);
12030
12031 expand %{
12032 immI16 imm1 %{ (int)-1 %}
12033 immI16 imm2 %{ (int)32 %}
12034 immI_minus1 m1 %{ -1 %}
12035 iRegIdst tmpI1;
12036 iRegIdst tmpI2;
12037 iRegIdst tmpI3;
12038 addI_reg_imm16(tmpI1, src, imm1);
12039 andcI_reg_reg(tmpI2, src, m1, tmpI1);
12040 countLeadingZerosI(tmpI3, tmpI2);
12041 subI_imm16_reg(dst, imm2, tmpI3);
12042 %}
12043 %}
12044
12045 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
12046 match(Set dst (CountTrailingZerosL src));
12047 predicate(UseCountLeadingZerosInstructionsPPC64);
12048 ins_cost(DEFAULT_COST);
12049
12050 expand %{
12051 immL16 imm1 %{ (long)-1 %}
12052 immI16 imm2 %{ (int)64 %}
12053 iRegLdst tmpL1;
12054 iRegLdst tmpL2;
12055 iRegIdst tmpL3;
12056 addL_reg_imm16(tmpL1, src, imm1);
12057 andcL_reg_reg(tmpL2, tmpL1, src);
12058 countLeadingZerosL(tmpL3, tmpL2);
12059 subI_imm16_reg(dst, imm2, tmpL3);
12060 %}
12061 %}
12062
12063 // Expand nodes for byte_reverse_int.
12064 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
12065 effect(DEF dst, USE src, USE pos, USE shift);
12066 predicate(false);
12067
12068 format %{ "INSRWI $dst, $src, $pos, $shift" %}
12069 size(4);
12070 ins_encode %{
12071 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
12072 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
12073 %}
12074 ins_pipe(pipe_class_default);
12075 %}
12076
12077 // As insrwi_a, but with USE_DEF.
12078 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
12079 effect(USE_DEF dst, USE src, USE pos, USE shift);
12080 predicate(false);
12081
12082 format %{ "INSRWI $dst, $src, $pos, $shift" %}
12083 size(4);
12084 ins_encode %{
12085 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
12086 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
12087 %}
12088 ins_pipe(pipe_class_default);
12089 %}
12090
12091 // Just slightly faster than java implementation.
12092 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
12093 match(Set dst (ReverseBytesI src));
12094 predicate(UseCountLeadingZerosInstructionsPPC64);
12095 ins_cost(DEFAULT_COST);
12096
12097 expand %{
12098 immI16 imm24 %{ (int) 24 %}
12099 immI16 imm16 %{ (int) 16 %}
12100 immI16 imm8 %{ (int) 8 %}
12101 immI16 imm4 %{ (int) 4 %}
12102 immI16 imm0 %{ (int) 0 %}
12103 iRegLdst tmpI1;
12104 iRegLdst tmpI2;
12105 iRegLdst tmpI3;
12106
12107 urShiftI_reg_imm(tmpI1, src, imm24);
12108 insrwi_a(dst, tmpI1, imm24, imm8);
12109 urShiftI_reg_imm(tmpI2, src, imm16);
12110 insrwi(dst, tmpI2, imm8, imm16);
12111 urShiftI_reg_imm(tmpI3, src, imm8);
12112 insrwi(dst, tmpI3, imm8, imm8);
12113 insrwi(dst, src, imm0, imm8);
12114 %}
12115 %}
12116
12117 //---------- Replicate Vector Instructions ------------------------------------
12118
12119 // Insrdi does replicate if src == dst.
12120 instruct repl32(iRegLdst dst) %{
12121 predicate(false);
12122 effect(USE_DEF dst);
12123
12124 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
12125 size(4);
12126 ins_encode %{
12127 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
12128 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
12129 %}
12130 ins_pipe(pipe_class_default);
12131 %}
12132
12133 // Insrdi does replicate if src == dst.
12134 instruct repl48(iRegLdst dst) %{
12135 predicate(false);
12136 effect(USE_DEF dst);
12137
12138 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
12139 size(4);
12140 ins_encode %{
12141 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
12142 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
12143 %}
12144 ins_pipe(pipe_class_default);
12145 %}
12146
12147 // Insrdi does replicate if src == dst.
12148 instruct repl56(iRegLdst dst) %{
12149 predicate(false);
12150 effect(USE_DEF dst);
12151
12152 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
12153 size(4);
12154 ins_encode %{
12155 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
12156 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
12157 %}
12158 ins_pipe(pipe_class_default);
12159 %}
12160
12161 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12162 match(Set dst (ReplicateB src));
12163 predicate(n->as_Vector()->length() == 8);
12164 expand %{
12165 moveReg(dst, src);
12166 repl56(dst);
12167 repl48(dst);
12168 repl32(dst);
12169 %}
12170 %}
12171
12172 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
12173 match(Set dst (ReplicateB zero));
12174 predicate(n->as_Vector()->length() == 8);
12175 format %{ "LI $dst, #0 \t// replicate8B" %}
12176 size(4);
12177 ins_encode %{
12178 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12179 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12180 %}
12181 ins_pipe(pipe_class_default);
12182 %}
12183
12184 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
12185 match(Set dst (ReplicateB src));
12186 predicate(n->as_Vector()->length() == 8);
12187 format %{ "LI $dst, #-1 \t// replicate8B" %}
12188 size(4);
12189 ins_encode %{
12190 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12191 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12192 %}
12193 ins_pipe(pipe_class_default);
12194 %}
12195
12196 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12197 match(Set dst (ReplicateS src));
12198 predicate(n->as_Vector()->length() == 4);
12199 expand %{
12200 moveReg(dst, src);
12201 repl48(dst);
12202 repl32(dst);
12203 %}
12204 %}
12205
12206 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
12207 match(Set dst (ReplicateS zero));
12208 predicate(n->as_Vector()->length() == 4);
12209 format %{ "LI $dst, #0 \t// replicate4C" %}
12210 size(4);
12211 ins_encode %{
12212 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12213 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12214 %}
12215 ins_pipe(pipe_class_default);
12216 %}
12217
12218 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
12219 match(Set dst (ReplicateS src));
12220 predicate(n->as_Vector()->length() == 4);
12221 format %{ "LI $dst, -1 \t// replicate4C" %}
12222 size(4);
12223 ins_encode %{
12224 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12225 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12226 %}
12227 ins_pipe(pipe_class_default);
12228 %}
12229
12230 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12231 match(Set dst (ReplicateI src));
12232 predicate(n->as_Vector()->length() == 2);
12233 ins_cost(2 * DEFAULT_COST);
12234 expand %{
12235 moveReg(dst, src);
12236 repl32(dst);
12237 %}
12238 %}
12239
12240 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
12241 match(Set dst (ReplicateI zero));
12242 predicate(n->as_Vector()->length() == 2);
12243 format %{ "LI $dst, #0 \t// replicate4C" %}
12244 size(4);
12245 ins_encode %{
12246 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12247 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12248 %}
12249 ins_pipe(pipe_class_default);
12250 %}
12251
12252 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
12253 match(Set dst (ReplicateI src));
12254 predicate(n->as_Vector()->length() == 2);
12255 format %{ "LI $dst, -1 \t// replicate4C" %}
12256 size(4);
12257 ins_encode %{
12258 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12259 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12260 %}
12261 ins_pipe(pipe_class_default);
12262 %}
12263
12264 // Move float to int register via stack, replicate.
12265 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
12266 match(Set dst (ReplicateF src));
12267 predicate(n->as_Vector()->length() == 2);
12268 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
12269 expand %{
12270 stackSlotL tmpS;
12271 iRegIdst tmpI;
12272 moveF2I_reg_stack(tmpS, src); // Move float to stack.
12273 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
12274 moveReg(dst, tmpI); // Move int to long reg.
12275 repl32(dst); // Replicate bitpattern.
12276 %}
12277 %}
12278
12279 // Replicate scalar constant to packed float values in Double register
12280 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
12281 match(Set dst (ReplicateF src));
12282 predicate(n->as_Vector()->length() == 2);
12283 ins_cost(5 * DEFAULT_COST);
12284
12285 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
12286 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
12287 %}
12288
12289 // Replicate scalar zero constant to packed float values in Double register
12290 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
12291 match(Set dst (ReplicateF zero));
12292 predicate(n->as_Vector()->length() == 2);
12293
12294 format %{ "LI $dst, #0 \t// replicate2F" %}
12295 ins_encode %{
12296 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12297 __ li($dst$$Register, 0x0);
12298 %}
12299 ins_pipe(pipe_class_default);
12300 %}
12301
12302
12303 //----------Overflow Math Instructions-----------------------------------------
12304
12305 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
12306 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
12307 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
12308
12309 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
12310 match(Set cr0 (OverflowAddL op1 op2));
12311
12312 format %{ "add_ $op1, $op2\t# overflow check long" %}
12313 ins_encode %{
12314 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12315 __ li(R0, 0);
12316 __ mtxer(R0); // clear XER.SO
12317 __ addo_(R0, $op1$$Register, $op2$$Register);
12318 %}
12319 ins_pipe(pipe_class_default);
12320 %}
12321
12322 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
12323 match(Set cr0 (OverflowSubL op1 op2));
12324
12325 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %}
12326 ins_encode %{
12327 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12328 __ li(R0, 0);
12329 __ mtxer(R0); // clear XER.SO
12330 __ subfo_(R0, $op2$$Register, $op1$$Register);
12331 %}
12332 ins_pipe(pipe_class_default);
12333 %}
12334
12335 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
12336 match(Set cr0 (OverflowSubL zero op2));
12337
12338 format %{ "nego_ R0, $op2\t# overflow check long" %}
12339 ins_encode %{
12340 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12341 __ li(R0, 0);
12342 __ mtxer(R0); // clear XER.SO
12343 __ nego_(R0, $op2$$Register);
12344 %}
12345 ins_pipe(pipe_class_default);
12346 %}
12347
12348 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
12349 match(Set cr0 (OverflowMulL op1 op2));
12350
12351 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
12352 ins_encode %{
12353 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12354 __ li(R0, 0);
12355 __ mtxer(R0); // clear XER.SO
12356 __ mulldo_(R0, $op1$$Register, $op2$$Register);
12357 %}
12358 ins_pipe(pipe_class_default);
12359 %}
12360
12361
12362 // ============================================================================
12363 // Safepoint Instruction
12364
12365 instruct safePoint_poll(iRegPdst poll) %{
12366 match(SafePoint poll);
12367 predicate(LoadPollAddressFromThread);
12368
12369 // It caused problems to add the effect that r0 is killed, but this
12370 // effect no longer needs to be mentioned, since r0 is not contained
12371 // in a reg_class.
12372
12373 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
12374 size(4);
12375 ins_encode( enc_poll(0x0, poll) );
12376 ins_pipe(pipe_class_default);
12377 %}
12378
12379 // Safepoint without per-thread support. Load address of page to poll
12380 // as constant.
12381 // Rscratch2RegP is R12.
12382 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
12383 // a seperate node so that the oop map is at the right location.
12384 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
12385 match(SafePoint poll);
12386 predicate(!LoadPollAddressFromThread);
12387
12388 // It caused problems to add the effect that r0 is killed, but this
12389 // effect no longer needs to be mentioned, since r0 is not contained
12390 // in a reg_class.
12391
12392 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
12393 ins_encode( enc_poll(0x0, poll) );
12394 ins_pipe(pipe_class_default);
12395 %}
12396
12397 // ============================================================================
12398 // Call Instructions
12399
12400 // Call Java Static Instruction
12401
12402 // Schedulable version of call static node.
12403 instruct CallStaticJavaDirect(method meth) %{
12404 match(CallStaticJava);
12405 effect(USE meth);
12406 ins_cost(CALL_COST);
12407
12408 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
12409
12410 format %{ "CALL,static $meth \t// ==> " %}
12411 size(4);
12412 ins_encode( enc_java_static_call(meth) );
12413 ins_pipe(pipe_class_call);
12414 %}
12415
12416 // Call Java Dynamic Instruction
12417
12418 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
12419 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
12420 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
12421 // The call destination must still be placed in the constant pool.
12422 instruct CallDynamicJavaDirectSched(method meth) %{
12423 match(CallDynamicJava); // To get all the data fields we need ...
12424 effect(USE meth);
12425 predicate(false); // ... but never match.
12426
12427 ins_field_load_ic_hi_node(loadConL_hiNode*);
12428 ins_field_load_ic_node(loadConLNode*);
12429 ins_num_consts(1 /* 1 patchable constant: call destination */);
12430
12431 format %{ "BL \t// dynamic $meth ==> " %}
12432 size(4);
12433 ins_encode( enc_java_dynamic_call_sched(meth) );
12434 ins_pipe(pipe_class_call);
12435 %}
12436
12437 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
12438 // We use postalloc expanded calls if we use inline caches
12439 // and do not update method data.
12440 //
12441 // This instruction has two constants: inline cache (IC) and call destination.
12442 // Loading the inline cache will be postalloc expanded, thus leaving a call with
12443 // one constant.
12444 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
12445 match(CallDynamicJava);
12446 effect(USE meth);
12447 predicate(UseInlineCaches);
12448 ins_cost(CALL_COST);
12449
12450 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
12451
12452 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
12453 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
12454 %}
12455
12456 // Compound version of call dynamic java
12457 // We use postalloc expanded calls if we use inline caches
12458 // and do not update method data.
12459 instruct CallDynamicJavaDirect(method meth) %{
12460 match(CallDynamicJava);
12461 effect(USE meth);
12462 predicate(!UseInlineCaches);
12463 ins_cost(CALL_COST);
12464
12465 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
12466 ins_num_consts(4);
12467
12468 format %{ "CALL,dynamic $meth \t// ==> " %}
12469 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
12470 ins_pipe(pipe_class_call);
12471 %}
12472
12473 // Call Runtime Instruction
12474
12475 instruct CallRuntimeDirect(method meth) %{
12476 match(CallRuntime);
12477 effect(USE meth);
12478 ins_cost(CALL_COST);
12479
12480 // Enc_java_to_runtime_call needs up to 3 constants: call target,
12481 // env for callee, C-toc.
12482 ins_num_consts(3);
12483
12484 format %{ "CALL,runtime" %}
12485 ins_encode( enc_java_to_runtime_call(meth) );
12486 ins_pipe(pipe_class_call);
12487 %}
12488
12489 // Call Leaf
12490
12491 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
12492 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
12493 effect(DEF dst, USE src);
12494
12495 ins_num_consts(1);
12496
12497 format %{ "MTCTR $src" %}
12498 size(4);
12499 ins_encode( enc_leaf_call_mtctr(src) );
12500 ins_pipe(pipe_class_default);
12501 %}
12502
12503 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
12504 instruct CallLeafDirect(method meth) %{
12505 match(CallLeaf); // To get the data all the data fields we need ...
12506 effect(USE meth);
12507 predicate(false); // but never match.
12508
12509 format %{ "BCTRL \t// leaf call $meth ==> " %}
12510 size(4);
12511 ins_encode %{
12512 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
12513 __ bctrl();
12514 %}
12515 ins_pipe(pipe_class_call);
12516 %}
12517
12518 // postalloc expand of CallLeafDirect.
12519 // Load adress to call from TOC, then bl to it.
12520 instruct CallLeafDirect_Ex(method meth) %{
12521 match(CallLeaf);
12522 effect(USE meth);
12523 ins_cost(CALL_COST);
12524
12525 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
12526 // env for callee, C-toc.
12527 ins_num_consts(3);
12528
12529 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
12530 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
12531 %}
12532
12533 // Call runtime without safepoint - same as CallLeaf.
12534 // postalloc expand of CallLeafNoFPDirect.
12535 // Load adress to call from TOC, then bl to it.
12536 instruct CallLeafNoFPDirect_Ex(method meth) %{
12537 match(CallLeafNoFP);
12538 effect(USE meth);
12539 ins_cost(CALL_COST);
12540
12541 // Enc_java_to_runtime_call needs up to 3 constants: call target,
12542 // env for callee, C-toc.
12543 ins_num_consts(3);
12544
12545 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
12546 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
12547 %}
12548
12549 // Tail Call; Jump from runtime stub to Java code.
12550 // Also known as an 'interprocedural jump'.
12551 // Target of jump will eventually return to caller.
12552 // TailJump below removes the return address.
12553 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
12554 match(TailCall jump_target method_oop);
12555 ins_cost(CALL_COST);
12556
12557 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
12558 "BCTR \t// tail call" %}
12559 size(8);
12560 ins_encode %{
12561 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12562 __ mtctr($jump_target$$Register);
12563 __ bctr();
12564 %}
12565 ins_pipe(pipe_class_call);
12566 %}
12567
12568 // Return Instruction
12569 instruct Ret() %{
12570 match(Return);
12571 format %{ "BLR \t// branch to link register" %}
12572 size(4);
12573 ins_encode %{
12574 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
12575 // LR is restored in MachEpilogNode. Just do the RET here.
12576 __ blr();
12577 %}
12578 ins_pipe(pipe_class_default);
12579 %}
12580
12581 // Tail Jump; remove the return address; jump to target.
12582 // TailCall above leaves the return address around.
12583 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
12584 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
12585 // "restore" before this instruction (in Epilogue), we need to materialize it
12586 // in %i0.
12587 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
12588 match(TailJump jump_target ex_oop);
12589 ins_cost(CALL_COST);
12590
12591 format %{ "LD R4_ARG2 = LR\n\t"
12592 "MTCTR $jump_target\n\t"
12593 "BCTR \t// TailJump, exception oop: $ex_oop" %}
12594 size(12);
12595 ins_encode %{
12596 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12597 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
12598 __ mtctr($jump_target$$Register);
12599 __ bctr();
12600 %}
12601 ins_pipe(pipe_class_call);
12602 %}
12603
12604 // Create exception oop: created by stack-crawling runtime code.
12605 // Created exception is now available to this handler, and is setup
12606 // just prior to jumping to this handler. No code emitted.
12607 instruct CreateException(rarg1RegP ex_oop) %{
12608 match(Set ex_oop (CreateEx));
12609 ins_cost(0);
12610
12611 format %{ " -- \t// exception oop; no code emitted" %}
12612 size(0);
12613 ins_encode( /*empty*/ );
12614 ins_pipe(pipe_class_default);
12615 %}
12616
12617 // Rethrow exception: The exception oop will come in the first
12618 // argument position. Then JUMP (not call) to the rethrow stub code.
12619 instruct RethrowException() %{
12620 match(Rethrow);
12621 ins_cost(CALL_COST);
12622
12623 format %{ "Jmp rethrow_stub" %}
12624 ins_encode %{
12625 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12626 cbuf.set_insts_mark();
12627 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12628 %}
12629 ins_pipe(pipe_class_call);
12630 %}
12631
12632 // Die now.
12633 instruct ShouldNotReachHere() %{
12634 match(Halt);
12635 ins_cost(CALL_COST);
12636
12637 format %{ "ShouldNotReachHere" %}
12638 size(4);
12639 ins_encode %{
12640 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12641 __ trap_should_not_reach_here();
12642 %}
12643 ins_pipe(pipe_class_default);
12644 %}
12645
12646 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
12647 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12648 // Get a DEF on threadRegP, no costs, no encoding, use
12649 // 'ins_should_rematerialize(true)' to avoid spilling.
12650 instruct tlsLoadP(threadRegP dst) %{
12651 match(Set dst (ThreadLocal));
12652 ins_cost(0);
12653
12654 ins_should_rematerialize(true);
12655
12656 format %{ " -- \t// $dst=Thread::current(), empty" %}
12657 size(0);
12658 ins_encode( /*empty*/ );
12659 ins_pipe(pipe_class_empty);
12660 %}
12661
12662 //---Some PPC specific nodes---------------------------------------------------
12663
12664 // Stop a group.
12665 instruct endGroup() %{
12666 ins_cost(0);
12667
12668 ins_is_nop(true);
12669
12670 format %{ "End Bundle (ori r1, r1, 0)" %}
12671 size(4);
12672 ins_encode %{
12673 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12674 __ endgroup();
12675 %}
12676 ins_pipe(pipe_class_default);
12677 %}
12678
12679 // Nop instructions
12680
12681 instruct fxNop() %{
12682 ins_cost(0);
12683
12684 ins_is_nop(true);
12685
12686 format %{ "fxNop" %}
12687 size(4);
12688 ins_encode %{
12689 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12690 __ nop();
12691 %}
12692 ins_pipe(pipe_class_default);
12693 %}
12694
12695 instruct fpNop0() %{
12696 ins_cost(0);
12697
12698 ins_is_nop(true);
12699
12700 format %{ "fpNop0" %}
12701 size(4);
12702 ins_encode %{
12703 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12704 __ fpnop0();
12705 %}
12706 ins_pipe(pipe_class_default);
12707 %}
12708
12709 instruct fpNop1() %{
12710 ins_cost(0);
12711
12712 ins_is_nop(true);
12713
12714 format %{ "fpNop1" %}
12715 size(4);
12716 ins_encode %{
12717 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12718 __ fpnop1();
12719 %}
12720 ins_pipe(pipe_class_default);
12721 %}
12722
12723 instruct brNop0() %{
12724 ins_cost(0);
12725 size(4);
12726 format %{ "brNop0" %}
12727 ins_encode %{
12728 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12729 __ brnop0();
12730 %}
12731 ins_is_nop(true);
12732 ins_pipe(pipe_class_default);
12733 %}
12734
12735 instruct brNop1() %{
12736 ins_cost(0);
12737
12738 ins_is_nop(true);
12739
12740 format %{ "brNop1" %}
12741 size(4);
12742 ins_encode %{
12743 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12744 __ brnop1();
12745 %}
12746 ins_pipe(pipe_class_default);
12747 %}
12748
12749 instruct brNop2() %{
12750 ins_cost(0);
12751
12752 ins_is_nop(true);
12753
12754 format %{ "brNop2" %}
12755 size(4);
12756 ins_encode %{
12757 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12758 __ brnop2();
12759 %}
12760 ins_pipe(pipe_class_default);
12761 %}
12762
12763 //----------PEEPHOLE RULES-----------------------------------------------------
12764 // These must follow all instruction definitions as they use the names
12765 // defined in the instructions definitions.
12766 //
12767 // peepmatch ( root_instr_name [preceeding_instruction]* );
12768 //
12769 // peepconstraint %{
12770 // (instruction_number.operand_name relational_op instruction_number.operand_name
12771 // [, ...] );
12772 // // instruction numbers are zero-based using left to right order in peepmatch
12773 //
12774 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12775 // // provide an instruction_number.operand_name for each operand that appears
12776 // // in the replacement instruction's match rule
12777 //
12778 // ---------VM FLAGS---------------------------------------------------------
12779 //
12780 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12781 //
12782 // Each peephole rule is given an identifying number starting with zero and
12783 // increasing by one in the order seen by the parser. An individual peephole
12784 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12785 // on the command-line.
12786 //
12787 // ---------CURRENT LIMITATIONS----------------------------------------------
12788 //
12789 // Only match adjacent instructions in same basic block
12790 // Only equality constraints
12791 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12792 // Only one replacement instruction
12793 //
12794 // ---------EXAMPLE----------------------------------------------------------
12795 //
12796 // // pertinent parts of existing instructions in architecture description
12797 // instruct movI(eRegI dst, eRegI src) %{
12798 // match(Set dst (CopyI src));
12799 // %}
12800 //
12801 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12802 // match(Set dst (AddI dst src));
12803 // effect(KILL cr);
12804 // %}
12805 //
12806 // // Change (inc mov) to lea
12807 // peephole %{
12808 // // increment preceeded by register-register move
12809 // peepmatch ( incI_eReg movI );
12810 // // require that the destination register of the increment
12811 // // match the destination register of the move
12812 // peepconstraint ( 0.dst == 1.dst );
12813 // // construct a replacement instruction that sets
12814 // // the destination to ( move's source register + one )
12815 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12816 // %}
12817 //
12818 // Implementation no longer uses movX instructions since
12819 // machine-independent system no longer uses CopyX nodes.
12820 //
12821 // peephole %{
12822 // peepmatch ( incI_eReg movI );
12823 // peepconstraint ( 0.dst == 1.dst );
12824 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12825 // %}
12826 //
12827 // peephole %{
12828 // peepmatch ( decI_eReg movI );
12829 // peepconstraint ( 0.dst == 1.dst );
12830 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12831 // %}
12832 //
12833 // peephole %{
12834 // peepmatch ( addI_eReg_imm movI );
12835 // peepconstraint ( 0.dst == 1.dst );
12836 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12837 // %}
12838 //
12839 // peephole %{
12840 // peepmatch ( addP_eReg_imm movP );
12841 // peepconstraint ( 0.dst == 1.dst );
12842 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12843 // %}
12844
12845 // // Change load of spilled value to only a spill
12846 // instruct storeI(memory mem, eRegI src) %{
12847 // match(Set mem (StoreI mem src));
12848 // %}
12849 //
12850 // instruct loadI(eRegI dst, memory mem) %{
12851 // match(Set dst (LoadI mem));
12852 // %}
12853 //
12854 peephole %{
12855 peepmatch ( loadI storeI );
12856 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12857 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12858 %}
12859
12860 peephole %{
12861 peepmatch ( loadL storeL );
12862 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12863 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12864 %}
12865
12866 peephole %{
12867 peepmatch ( loadP storeP );
12868 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12869 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12870 %}
12871
12872 //----------SMARTSPILL RULES---------------------------------------------------
12873 // These must follow all instruction definitions as they use the names
12874 // defined in the instructions definitions.