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src/share/vm/c1/c1_LIR.hpp
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rev 11567 : 8160245: C1: Clean up platform #defines in c1_LIR.hpp.
Summary: Also add fnoreg on x86, LIR_Address constructor without scale, and clean up templateInterpreterGenerator.hpp.
@@ -26,10 +26,11 @@
#define SHARE_VM_C1_C1_LIR_HPP
#include "c1/c1_Defs.hpp"
#include "c1/c1_ValueType.hpp"
#include "oops/method.hpp"
+#include "utilities/globalDefinitions.hpp"
class BlockBegin;
class BlockList;
class LIR_Assembler;
class CodeEmitInfo;
@@ -436,19 +437,17 @@
}
#endif
return as_register();
}
+ FloatRegister as_float_reg () const;
+ FloatRegister as_double_reg () const;
#ifdef X86
- XMMRegister as_xmm_float_reg() const;
+ XMMRegister as_xmm_float_reg () const;
XMMRegister as_xmm_double_reg() const;
// for compatibility with RInfo
- int fpu () const { return lo_reg_half(); }
-#endif
-#if defined(SPARC) || defined(ARM) || defined(PPC) || defined(AARCH64)
- FloatRegister as_float_reg () const;
- FloatRegister as_double_reg () const;
+ int fpu() const { return lo_reg_half(); }
#endif
jint as_jint() const { return as_constant_ptr()->as_jint(); }
jlong as_jlong() const { return as_constant_ptr()->as_jlong(); }
jfloat as_jfloat() const { return as_constant_ptr()->as_jfloat(); }
@@ -532,18 +531,23 @@
, _index(LIR_OprDesc::illegalOpr())
, _scale(times_1)
, _type(type)
, _disp(0) { verify(); }
-#if defined(X86) || defined(ARM) || defined(AARCH64)
+ LIR_Address(LIR_Opr base, LIR_Opr index, intx disp, BasicType type):
+ _base(base)
+ , _index(index)
+ , _scale(times_1)
+ , _type(type)
+ , _disp(disp) { verify(); }
+
LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
_base(base)
, _index(index)
, _scale(scale)
, _type(type)
, _disp(disp) { verify(); }
-#endif // X86 || ARM
LIR_Opr base() const { return _base; }
LIR_Opr index() const { return _index; }
Scale scale() const { return _scale; }
intx disp() const { return _disp; }
@@ -552,17 +556,11 @@
virtual LIR_Address* as_address() { return this; }
virtual BasicType type() const { return _type; }
virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
- void verify0() const PRODUCT_RETURN;
-#if defined(LIR_ADDRESS_PD_VERIFY) && !defined(PRODUCT)
- void pd_verify() const;
- void verify() const { pd_verify(); }
-#else
- void verify() const { verify0(); }
-#endif
+ void verify() const PRODUCT_RETURN;
static Scale scale(BasicType type);
};
@@ -603,63 +601,54 @@
LIR_OprDesc::long_type |
LIR_OprDesc::cpu_register |
LIR_OprDesc::double_size);
}
- static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+ static LIR_Opr single_fpu(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
LIR_OprDesc::float_type |
LIR_OprDesc::fpu_register |
- LIR_OprDesc::single_size); }
-#if defined(ARM32)
- static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
- static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
- static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }
-#endif
-#ifdef SPARC
- static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+ LIR_OprDesc::single_size);
+ }
+
+ // Platform dependant.
+ static LIR_Opr double_fpu(int reg1, int reg2 = -1 /*fnoreg*/);
+
+#ifdef __SOFTFP__
+ static LIR_Opr single_softfp(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+ LIR_OprDesc::float_type |
+ LIR_OprDesc::cpu_register |
+ LIR_OprDesc::single_size);
+ }
+ static LIR_Opr double_softfp(int reg1, int reg2) {
+ PPC32_ONLY(swap(reg1, reg2);)
+ return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
(reg2 << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::double_size); }
-#endif
-#if defined(X86) || defined(AARCH64)
- static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
- (reg << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::double_size); }
+ LIR_OprDesc::cpu_register |
+ LIR_OprDesc::double_size);
+ }
+#endif // __SOFTFP__
- static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+#if defined(X86)
+ static LIR_Opr single_xmm(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
LIR_OprDesc::float_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::single_size |
- LIR_OprDesc::is_xmm_mask); }
- static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+ LIR_OprDesc::is_xmm_mask);
+ }
+ static LIR_Opr double_xmm(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
(reg << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size |
- LIR_OprDesc::is_xmm_mask); }
+ LIR_OprDesc::is_xmm_mask);
+ }
#endif // X86
-#if defined(PPC)
- static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
- (reg << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::double_size); }
-#endif
-#ifdef PPC32
- static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
- LIR_OprDesc::float_type |
- LIR_OprDesc::cpu_register |
- LIR_OprDesc::single_size); }
- static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) |
- (reg1 << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::cpu_register |
- LIR_OprDesc::double_size); }
-#endif // PPC32
static LIR_Opr virtual_register(int index, BasicType type) {
LIR_Opr res;
switch (type) {
case T_OBJECT: // fall through
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