src/share/vm/c1/c1_LIR.cpp

rev 11572 : 8160245: C1: Clean up platform #defines in c1_LIR.hpp.
Summary: Also add fnoreg on x86, LIR_Address constructor without scale, and clean up templateInterpreterGenerator.hpp.
Reviewed-by: coleenp

*** 40,85 ****
  
  Register LIR_OprDesc::as_register_hi() const {
    return FrameMap::cpu_rnr2reg(cpu_regnrHi());
  }
  
! #if defined(X86)
! 
! XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
!   return FrameMap::nr2xmmreg(xmm_regnr());
! }
! 
! XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
!   assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
!   return FrameMap::nr2xmmreg(xmm_regnrLo());
! }
! 
! #endif // X86
! 
! #if defined(SPARC) || defined(PPC32)
! 
  FloatRegister LIR_OprDesc::as_float_reg() const {
    return FrameMap::nr2floatreg(fpu_regnr());
  }
  
  FloatRegister LIR_OprDesc::as_double_reg() const {
    return FrameMap::nr2floatreg(fpu_regnrHi());
  }
  
! #endif
! 
! #if defined(ARM) || defined(AARCH64) || defined(PPC64)
! 
  FloatRegister LIR_OprDesc::as_float_reg() const {
    return as_FloatRegister(fpu_regnr());
  }
- 
  FloatRegister LIR_OprDesc::as_double_reg() const {
    return as_FloatRegister(fpu_regnrLo());
  }
! 
! #endif
  
  
  LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  
  LIR_Opr LIR_OprFact::value_type(ValueType* type) {
--- 40,114 ----
  
  Register LIR_OprDesc::as_register_hi() const {
    return FrameMap::cpu_rnr2reg(cpu_regnrHi());
  }
  
! #ifdef PPC32
  FloatRegister LIR_OprDesc::as_float_reg() const {
    return FrameMap::nr2floatreg(fpu_regnr());
  }
  
  FloatRegister LIR_OprDesc::as_double_reg() const {
    return FrameMap::nr2floatreg(fpu_regnrHi());
  }
+ // Reg2 unused.
+ LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
+   assert(reg2 == -1 /*fnoreg*/, "Not used on this platform");
+   return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+                              (reg << LIR_OprDesc::reg2_shift) |
+                              LIR_OprDesc::double_type         |
+                              LIR_OprDesc::fpu_register        |
+                              LIR_OprDesc::double_size);
+ }
+ #ifndef PRODUCT
+ #if defined(LIR_ADDRESS_PD_VERIFY)
+   void LIR_Address::verify() const { pd_verify(); }
+ #else
+ void LIR_Address::verify() const {
+   assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
+   assert(disp() == 0 || index()->is_illegal(), "can't have both");
+   assert(base()->is_single_cpu(), "wrong base operand");
+   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
+   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
+          "wrong type for addresses");
+ }
+ #endif // (LIR_ADDRESS_PD_VERIFY
+ #endif // PRODUCT
+ #endif // PPC32
  
! #ifdef ARM
  FloatRegister LIR_OprDesc::as_float_reg() const {
    return as_FloatRegister(fpu_regnr());
  }
  FloatRegister LIR_OprDesc::as_double_reg() const {
    return as_FloatRegister(fpu_regnrLo());
  }
! #ifndef PRODUCT
! #if defined(LIR_ADDRESS_PD_VERIFY)
!   void verify() const { pd_verify(); }
! #else
! void LIR_Address::verify() const {
!   assert(base()->is_single_cpu(), "wrong base operand");
!   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
!   assert(scale() == times_1, "Scaled addressing mode not available on PPC and should not be used");
!   assert(disp() == 0 || index()->is_illegal(), "can't have both");
!   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
!          "wrong type for addresses");
! }
! #endif // LIR_ADDRESS_PD_VERIFY
! #endif // PRODUCT
! #endif // ARM
! #ifdef ARM32
! LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
!   assert(reg2 != -1 /*fnoreg*/, "Arm32 holds double in two regs.");
!   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
!                              (reg2 << LIR_OprDesc::reg2_shift) |
!                              LIR_OprDesc::double_type          |
!                              LIR_OprDesc::fpu_register         |
!                              LIR_OprDesc::double_size);
! }
! #endif // ARM32
  
  
  LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  
  LIR_Opr LIR_OprFact::value_type(ValueType* type) {
*** 138,173 ****
    }
    ShouldNotReachHere();
    return LIR_Address::times_1;
  }
  
- 
- #ifndef PRODUCT
- void LIR_Address::verify0() const {
- #if defined(SPARC) || defined(PPC)
-   assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
-   assert(disp() == 0 || index()->is_illegal(), "can't have both");
- #endif
- #ifdef _LP64
-   assert(base()->is_cpu_register(), "wrong base operand");
- #ifndef AARCH64
-   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
- #else
-   assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
- #endif
-   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
-          "wrong type for addresses");
- #else
-   assert(base()->is_single_cpu(), "wrong base operand");
-   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
-   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
-          "wrong type for addresses");
- #endif
- }
- #endif
- 
- 
  //---------------------------------------------------
  
  char LIR_OprDesc::type_char(BasicType t) {
    switch (t) {
      case T_ARRAY:
--- 167,176 ----