11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_VM_C1_C1_LIR_HPP
26 #define SHARE_VM_C1_C1_LIR_HPP
27
28 #include "c1/c1_Defs.hpp"
29 #include "c1/c1_ValueType.hpp"
30 #include "oops/method.hpp"
31
32 class BlockBegin;
33 class BlockList;
34 class LIR_Assembler;
35 class CodeEmitInfo;
36 class CodeStub;
37 class CodeStubList;
38 class ArrayCopyStub;
39 class LIR_Op;
40 class ciType;
41 class ValueType;
42 class LIR_OpVisitState;
43 class FpuStackSim;
44
45 //---------------------------------------------------------------------
46 // LIR Operands
47 // LIR_OprDesc
48 // LIR_OprPtr
49 // LIR_Const
50 // LIR_Address
421 int vreg_number() const { assert(is_virtual(), "type check"); return (RegNr)data(); }
422
423 LIR_OprPtr* pointer() const { assert(is_pointer(), "type check"); return (LIR_OprPtr*)this; }
424 LIR_Const* as_constant_ptr() const { return pointer()->as_constant(); }
425 LIR_Address* as_address_ptr() const { return pointer()->as_address(); }
426
427 Register as_register() const;
428 Register as_register_lo() const;
429 Register as_register_hi() const;
430
431 Register as_pointer_register() {
432 #ifdef _LP64
433 if (is_double_cpu()) {
434 assert(as_register_lo() == as_register_hi(), "should be a single register");
435 return as_register_lo();
436 }
437 #endif
438 return as_register();
439 }
440
441 #ifdef X86
442 XMMRegister as_xmm_float_reg() const;
443 XMMRegister as_xmm_double_reg() const;
444 // for compatibility with RInfo
445 int fpu () const { return lo_reg_half(); }
446 #endif
447 #if defined(SPARC) || defined(ARM) || defined(PPC) || defined(AARCH64)
448 FloatRegister as_float_reg () const;
449 FloatRegister as_double_reg () const;
450 #endif
451
452 jint as_jint() const { return as_constant_ptr()->as_jint(); }
453 jlong as_jlong() const { return as_constant_ptr()->as_jlong(); }
454 jfloat as_jfloat() const { return as_constant_ptr()->as_jfloat(); }
455 jdouble as_jdouble() const { return as_constant_ptr()->as_jdouble(); }
456 jobject as_jobject() const { return as_constant_ptr()->as_jobject(); }
457
458 void print() const PRODUCT_RETURN;
459 void print(outputStream* out) const PRODUCT_RETURN;
460 };
461
462
463 inline LIR_OprDesc::OprType as_OprType(BasicType type) {
464 switch (type) {
465 case T_INT: return LIR_OprDesc::int_type;
466 case T_LONG: return LIR_OprDesc::long_type;
467 case T_FLOAT: return LIR_OprDesc::float_type;
468 case T_DOUBLE: return LIR_OprDesc::double_type;
469 case T_OBJECT:
517 _base(base)
518 , _index(index)
519 , _scale(times_1)
520 , _type(type)
521 , _disp(0) { verify(); }
522
523 LIR_Address(LIR_Opr base, intx disp, BasicType type):
524 _base(base)
525 , _index(LIR_OprDesc::illegalOpr())
526 , _scale(times_1)
527 , _type(type)
528 , _disp(disp) { verify(); }
529
530 LIR_Address(LIR_Opr base, BasicType type):
531 _base(base)
532 , _index(LIR_OprDesc::illegalOpr())
533 , _scale(times_1)
534 , _type(type)
535 , _disp(0) { verify(); }
536
537 #if defined(X86) || defined(ARM) || defined(AARCH64)
538 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
539 _base(base)
540 , _index(index)
541 , _scale(scale)
542 , _type(type)
543 , _disp(disp) { verify(); }
544 #endif // X86 || ARM
545
546 LIR_Opr base() const { return _base; }
547 LIR_Opr index() const { return _index; }
548 Scale scale() const { return _scale; }
549 intx disp() const { return _disp; }
550
551 bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
552
553 virtual LIR_Address* as_address() { return this; }
554 virtual BasicType type() const { return _type; }
555 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
556
557 void verify0() const PRODUCT_RETURN;
558 #if defined(LIR_ADDRESS_PD_VERIFY) && !defined(PRODUCT)
559 void pd_verify() const;
560 void verify() const { pd_verify(); }
561 #else
562 void verify() const { verify0(); }
563 #endif
564
565 static Scale scale(BasicType type);
566 };
567
568
569 // operand factory
570 class LIR_OprFact: public AllStatic {
571 public:
572
573 static LIR_Opr illegalOpr;
574
575 static LIR_Opr single_cpu(int reg) {
576 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
577 LIR_OprDesc::int_type |
578 LIR_OprDesc::cpu_register |
579 LIR_OprDesc::single_size);
580 }
581 static LIR_Opr single_cpu_oop(int reg) {
582 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
583 LIR_OprDesc::object_type |
588 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
589 LIR_OprDesc::address_type |
590 LIR_OprDesc::cpu_register |
591 LIR_OprDesc::single_size);
592 }
593 static LIR_Opr single_cpu_metadata(int reg) {
594 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
595 LIR_OprDesc::metadata_type |
596 LIR_OprDesc::cpu_register |
597 LIR_OprDesc::single_size);
598 }
599 static LIR_Opr double_cpu(int reg1, int reg2) {
600 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
601 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
602 (reg2 << LIR_OprDesc::reg2_shift) |
603 LIR_OprDesc::long_type |
604 LIR_OprDesc::cpu_register |
605 LIR_OprDesc::double_size);
606 }
607
608 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
609 LIR_OprDesc::float_type |
610 LIR_OprDesc::fpu_register |
611 LIR_OprDesc::single_size); }
612 #if defined(ARM32)
613 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
614 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
615 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }
616 #endif
617 #ifdef SPARC
618 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
619 (reg2 << LIR_OprDesc::reg2_shift) |
620 LIR_OprDesc::double_type |
621 LIR_OprDesc::fpu_register |
622 LIR_OprDesc::double_size); }
623 #endif
624 #if defined(X86) || defined(AARCH64)
625 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
626 (reg << LIR_OprDesc::reg2_shift) |
627 LIR_OprDesc::double_type |
628 LIR_OprDesc::fpu_register |
629 LIR_OprDesc::double_size); }
630
631 static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
632 LIR_OprDesc::float_type |
633 LIR_OprDesc::fpu_register |
634 LIR_OprDesc::single_size |
635 LIR_OprDesc::is_xmm_mask); }
636 static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
637 (reg << LIR_OprDesc::reg2_shift) |
638 LIR_OprDesc::double_type |
639 LIR_OprDesc::fpu_register |
640 LIR_OprDesc::double_size |
641 LIR_OprDesc::is_xmm_mask); }
642 #endif // X86
643 #if defined(PPC)
644 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
645 (reg << LIR_OprDesc::reg2_shift) |
646 LIR_OprDesc::double_type |
647 LIR_OprDesc::fpu_register |
648 LIR_OprDesc::double_size); }
649 #endif
650 #ifdef PPC32
651 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
652 LIR_OprDesc::float_type |
653 LIR_OprDesc::cpu_register |
654 LIR_OprDesc::single_size); }
655 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) |
656 (reg1 << LIR_OprDesc::reg2_shift) |
657 LIR_OprDesc::double_type |
658 LIR_OprDesc::cpu_register |
659 LIR_OprDesc::double_size); }
660 #endif // PPC32
661
662 static LIR_Opr virtual_register(int index, BasicType type) {
663 LIR_Opr res;
664 switch (type) {
665 case T_OBJECT: // fall through
666 case T_ARRAY:
667 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
668 LIR_OprDesc::object_type |
669 LIR_OprDesc::cpu_register |
670 LIR_OprDesc::single_size |
671 LIR_OprDesc::virtual_mask);
672 break;
673
674 case T_METADATA:
675 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
676 LIR_OprDesc::metadata_type|
677 LIR_OprDesc::cpu_register |
678 LIR_OprDesc::single_size |
679 LIR_OprDesc::virtual_mask);
680 break;
|
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_VM_C1_C1_LIR_HPP
26 #define SHARE_VM_C1_C1_LIR_HPP
27
28 #include "c1/c1_Defs.hpp"
29 #include "c1/c1_ValueType.hpp"
30 #include "oops/method.hpp"
31 #include "utilities/globalDefinitions.hpp"
32
33 class BlockBegin;
34 class BlockList;
35 class LIR_Assembler;
36 class CodeEmitInfo;
37 class CodeStub;
38 class CodeStubList;
39 class ArrayCopyStub;
40 class LIR_Op;
41 class ciType;
42 class ValueType;
43 class LIR_OpVisitState;
44 class FpuStackSim;
45
46 //---------------------------------------------------------------------
47 // LIR Operands
48 // LIR_OprDesc
49 // LIR_OprPtr
50 // LIR_Const
51 // LIR_Address
422 int vreg_number() const { assert(is_virtual(), "type check"); return (RegNr)data(); }
423
424 LIR_OprPtr* pointer() const { assert(is_pointer(), "type check"); return (LIR_OprPtr*)this; }
425 LIR_Const* as_constant_ptr() const { return pointer()->as_constant(); }
426 LIR_Address* as_address_ptr() const { return pointer()->as_address(); }
427
428 Register as_register() const;
429 Register as_register_lo() const;
430 Register as_register_hi() const;
431
432 Register as_pointer_register() {
433 #ifdef _LP64
434 if (is_double_cpu()) {
435 assert(as_register_lo() == as_register_hi(), "should be a single register");
436 return as_register_lo();
437 }
438 #endif
439 return as_register();
440 }
441
442 FloatRegister as_float_reg () const;
443 FloatRegister as_double_reg () const;
444 #ifdef X86
445 XMMRegister as_xmm_float_reg () const;
446 XMMRegister as_xmm_double_reg() const;
447 // for compatibility with RInfo
448 int fpu() const { return lo_reg_half(); }
449 #endif
450
451 jint as_jint() const { return as_constant_ptr()->as_jint(); }
452 jlong as_jlong() const { return as_constant_ptr()->as_jlong(); }
453 jfloat as_jfloat() const { return as_constant_ptr()->as_jfloat(); }
454 jdouble as_jdouble() const { return as_constant_ptr()->as_jdouble(); }
455 jobject as_jobject() const { return as_constant_ptr()->as_jobject(); }
456
457 void print() const PRODUCT_RETURN;
458 void print(outputStream* out) const PRODUCT_RETURN;
459 };
460
461
462 inline LIR_OprDesc::OprType as_OprType(BasicType type) {
463 switch (type) {
464 case T_INT: return LIR_OprDesc::int_type;
465 case T_LONG: return LIR_OprDesc::long_type;
466 case T_FLOAT: return LIR_OprDesc::float_type;
467 case T_DOUBLE: return LIR_OprDesc::double_type;
468 case T_OBJECT:
516 _base(base)
517 , _index(index)
518 , _scale(times_1)
519 , _type(type)
520 , _disp(0) { verify(); }
521
522 LIR_Address(LIR_Opr base, intx disp, BasicType type):
523 _base(base)
524 , _index(LIR_OprDesc::illegalOpr())
525 , _scale(times_1)
526 , _type(type)
527 , _disp(disp) { verify(); }
528
529 LIR_Address(LIR_Opr base, BasicType type):
530 _base(base)
531 , _index(LIR_OprDesc::illegalOpr())
532 , _scale(times_1)
533 , _type(type)
534 , _disp(0) { verify(); }
535
536 LIR_Address(LIR_Opr base, LIR_Opr index, intx disp, BasicType type):
537 _base(base)
538 , _index(index)
539 , _scale(times_1)
540 , _type(type)
541 , _disp(disp) { verify(); }
542
543 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
544 _base(base)
545 , _index(index)
546 , _scale(scale)
547 , _type(type)
548 , _disp(disp) { verify(); }
549
550 LIR_Opr base() const { return _base; }
551 LIR_Opr index() const { return _index; }
552 Scale scale() const { return _scale; }
553 intx disp() const { return _disp; }
554
555 bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
556
557 virtual LIR_Address* as_address() { return this; }
558 virtual BasicType type() const { return _type; }
559 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
560
561 void verify() const PRODUCT_RETURN;
562
563 static Scale scale(BasicType type);
564 };
565
566
567 // operand factory
568 class LIR_OprFact: public AllStatic {
569 public:
570
571 static LIR_Opr illegalOpr;
572
573 static LIR_Opr single_cpu(int reg) {
574 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
575 LIR_OprDesc::int_type |
576 LIR_OprDesc::cpu_register |
577 LIR_OprDesc::single_size);
578 }
579 static LIR_Opr single_cpu_oop(int reg) {
580 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
581 LIR_OprDesc::object_type |
586 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
587 LIR_OprDesc::address_type |
588 LIR_OprDesc::cpu_register |
589 LIR_OprDesc::single_size);
590 }
591 static LIR_Opr single_cpu_metadata(int reg) {
592 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
593 LIR_OprDesc::metadata_type |
594 LIR_OprDesc::cpu_register |
595 LIR_OprDesc::single_size);
596 }
597 static LIR_Opr double_cpu(int reg1, int reg2) {
598 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
599 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
600 (reg2 << LIR_OprDesc::reg2_shift) |
601 LIR_OprDesc::long_type |
602 LIR_OprDesc::cpu_register |
603 LIR_OprDesc::double_size);
604 }
605
606 static LIR_Opr single_fpu(int reg) {
607 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
608 LIR_OprDesc::float_type |
609 LIR_OprDesc::fpu_register |
610 LIR_OprDesc::single_size);
611 }
612
613 // Platform dependant.
614 static LIR_Opr double_fpu(int reg1, int reg2 = -1 /*fnoreg*/);
615
616 #ifdef __SOFTFP__
617 static LIR_Opr single_softfp(int reg) {
618 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
619 LIR_OprDesc::float_type |
620 LIR_OprDesc::cpu_register |
621 LIR_OprDesc::single_size);
622 }
623 static LIR_Opr double_softfp(int reg1, int reg2) {
624 PPC32_ONLY(swap(reg1, reg2);)
625 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
626 (reg2 << LIR_OprDesc::reg2_shift) |
627 LIR_OprDesc::double_type |
628 LIR_OprDesc::cpu_register |
629 LIR_OprDesc::double_size);
630 }
631 #endif // __SOFTFP__
632
633 #if defined(X86)
634 static LIR_Opr single_xmm(int reg) {
635 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
636 LIR_OprDesc::float_type |
637 LIR_OprDesc::fpu_register |
638 LIR_OprDesc::single_size |
639 LIR_OprDesc::is_xmm_mask);
640 }
641 static LIR_Opr double_xmm(int reg) {
642 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
643 (reg << LIR_OprDesc::reg2_shift) |
644 LIR_OprDesc::double_type |
645 LIR_OprDesc::fpu_register |
646 LIR_OprDesc::double_size |
647 LIR_OprDesc::is_xmm_mask);
648 }
649 #endif // X86
650
651 static LIR_Opr virtual_register(int index, BasicType type) {
652 LIR_Opr res;
653 switch (type) {
654 case T_OBJECT: // fall through
655 case T_ARRAY:
656 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
657 LIR_OprDesc::object_type |
658 LIR_OprDesc::cpu_register |
659 LIR_OprDesc::single_size |
660 LIR_OprDesc::virtual_mask);
661 break;
662
663 case T_METADATA:
664 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
665 LIR_OprDesc::metadata_type|
666 LIR_OprDesc::cpu_register |
667 LIR_OprDesc::single_size |
668 LIR_OprDesc::virtual_mask);
669 break;
|