1 /*
   2  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP
  26 #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP
  27 
  28 #include "c1/c1_CodeStubs.hpp"
  29 #include "ci/ciMethodData.hpp"
  30 #include "oops/methodData.hpp"
  31 
  32 class Compilation;
  33 class ScopeValue;
  34 class BarrierSet;
  35 
  36 class LIR_Assembler: public CompilationResourceObj {
  37  private:
  38   C1_MacroAssembler* _masm;
  39   CodeStubList*      _slow_case_stubs;
  40   BarrierSet*        _bs;
  41 
  42   Compilation*       _compilation;
  43   FrameMap*          _frame_map;
  44   BlockBegin*        _current_block;
  45 
  46   Instruction*       _pending_non_safepoint;
  47   int                _pending_non_safepoint_offset;
  48 
  49   Label              _unwind_handler_entry;
  50 
  51 #ifdef ASSERT
  52   BlockList          _branch_target_blocks;
  53   void check_no_unbound_labels();
  54 #endif
  55 
  56   FrameMap* frame_map() const { return _frame_map; }
  57 
  58   void set_current_block(BlockBegin* b) { _current_block = b; }
  59   BlockBegin* current_block() const { return _current_block; }
  60 
  61   // non-safepoint debug info management
  62   void flush_debug_info(int before_pc_offset) {
  63     if (_pending_non_safepoint != NULL) {
  64       if (_pending_non_safepoint_offset < before_pc_offset)
  65         record_non_safepoint_debug_info();
  66       _pending_non_safepoint = NULL;
  67     }
  68   }
  69   void process_debug_info(LIR_Op* op);
  70   void record_non_safepoint_debug_info();
  71 
  72   // unified bailout support
  73   void bailout(const char* msg) const            { compilation()->bailout(msg); }
  74   bool bailed_out() const                        { return compilation()->bailed_out(); }
  75 
  76   // code emission patterns and accessors
  77   void check_codespace();
  78   bool needs_icache(ciMethod* method) const;
  79 
  80   // returns offset of icache check
  81   int check_icache();
  82 
  83   void jobject2reg(jobject o, Register reg);
  84   void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);
  85 
  86   void metadata2reg(Metadata* o, Register reg);
  87   void klass2reg_with_patching(Register reg, CodeEmitInfo* info);
  88 
  89   void emit_stubs(CodeStubList* stub_list);
  90 
  91   // addresses
  92   Address as_Address(LIR_Address* addr);
  93   Address as_Address_lo(LIR_Address* addr);
  94   Address as_Address_hi(LIR_Address* addr);
  95 
  96   // debug information
  97   void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
  98   void add_debug_info_for_branch(CodeEmitInfo* info);
  99   void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
 100   void add_debug_info_for_div0_here(CodeEmitInfo* info);
 101   ImplicitNullCheckStub* add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
 102   ImplicitNullCheckStub* add_debug_info_for_null_check_here(CodeEmitInfo* info);
 103 
 104   void set_24bit_FPU();
 105   void reset_FPU();
 106   void fpop();
 107   void fxch(int i);
 108   void fld(int i);
 109   void ffree(int i);
 110 
 111   void breakpoint();
 112   void push(LIR_Opr opr);
 113   void pop(LIR_Opr opr);
 114 
 115   // patching
 116   void append_patching_stub(PatchingStub* stub);
 117   void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);
 118 
 119   void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);
 120 
 121   PatchingStub::PatchID patching_id(CodeEmitInfo* info);
 122 
 123  public:
 124   LIR_Assembler(Compilation* c);
 125   ~LIR_Assembler();
 126   C1_MacroAssembler* masm() const                { return _masm; }
 127   Compilation* compilation() const               { return _compilation; }
 128   ciMethod* method() const                       { return compilation()->method(); }
 129 
 130   CodeOffsets* offsets() const                   { return _compilation->offsets(); }
 131   int code_offset() const;
 132   address pc() const;
 133 
 134   int  initial_frame_size_in_bytes() const;
 135   int  bang_size_in_bytes() const;
 136 
 137   // test for constants which can be encoded directly in instructions
 138   static bool is_small_constant(LIR_Opr opr);
 139 
 140   static LIR_Opr receiverOpr();
 141   static LIR_Opr osrBufferPointer();
 142 
 143   // stubs
 144   void emit_slow_case_stubs();
 145   void emit_static_call_stub();
 146   void append_code_stub(CodeStub* op);
 147   void add_call_info_here(CodeEmitInfo* info)                              { add_call_info(code_offset(), info); }
 148 
 149   // code patterns
 150   int  emit_exception_handler();
 151   int  emit_unwind_handler();
 152   void emit_exception_entries(ExceptionInfoList* info_list);
 153   int  emit_deopt_handler();
 154 
 155   void emit_code(BlockList* hir);
 156   void emit_block(BlockBegin* block);
 157   void emit_lir_list(LIR_List* list);
 158 
 159   // any last minute peephole optimizations are performed here.  In
 160   // particular sparc uses this for delay slot filling.
 161   void peephole(LIR_List* list);
 162 
 163   void return_op(LIR_Opr result);
 164 
 165   // returns offset of poll instruction
 166   int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);
 167 
 168   void const2reg  (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);
 169   void const2stack(LIR_Opr src, LIR_Opr dest);
 170   void const2mem  (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide);
 171   void reg2stack  (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);
 172   void reg2reg    (LIR_Opr src, LIR_Opr dest);
 173   void reg2mem    (LIR_Opr src, LIR_Opr dest, BasicType type,
 174                    LIR_PatchCode patch_code, CodeEmitInfo* info,
 175                    bool pop_fpu_stack, bool wide, bool unaligned);
 176   void stack2reg  (LIR_Opr src, LIR_Opr dest, BasicType type);
 177   void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);
 178   void mem2reg    (LIR_Opr src, LIR_Opr dest, BasicType type,
 179                    LIR_PatchCode patch_code,
 180                    CodeEmitInfo* info, bool wide, bool unaligned);
 181 
 182   void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);
 183   void shift_op(LIR_Code code, LIR_Opr left, jint  count, LIR_Opr dest);
 184 
 185   void move_regs(Register from_reg, Register to_reg);
 186   void swap_reg(Register a, Register b);
 187 
 188   void emit_op0(LIR_Op0* op);
 189   void emit_op1(LIR_Op1* op);
 190   void emit_op2(LIR_Op2* op);
 191   void emit_op3(LIR_Op3* op);
 192   void emit_opBranch(LIR_OpBranch* op);
 193   void emit_opLabel(LIR_OpLabel* op);
 194   void emit_arraycopy(LIR_OpArrayCopy* op);
 195   void emit_updatecrc32(LIR_OpUpdateCRC32* op);
 196   void emit_opConvert(LIR_OpConvert* op);
 197   void emit_alloc_obj(LIR_OpAllocObj* op);
 198   void emit_alloc_array(LIR_OpAllocArray* op);
 199   void emit_opTypeCheck(LIR_OpTypeCheck* op);
 200   void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null);
 201   void emit_compare_and_swap(LIR_OpCompareAndSwap* op);
 202   void emit_lock(LIR_OpLock* op);
 203   void emit_call(LIR_OpJavaCall* op);
 204   void emit_rtcall(LIR_OpRTCall* op);
 205   void emit_profile_call(LIR_OpProfileCall* op);
 206   void emit_profile_type(LIR_OpProfileType* op);
 207   void emit_delay(LIR_OpDelay* op);
 208 
 209   void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
 210   void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
 211   void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
 212 #ifdef ASSERT
 213   void emit_assert(LIR_OpAssert* op);
 214 #endif
 215 
 216   void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
 217 
 218   void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);
 219   void move_op(LIR_Opr src, LIR_Opr result, BasicType type,
 220                LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide);
 221   void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
 222   void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);  // info set for null exceptions
 223   void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
 224   void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);
 225 
 226   void call(        LIR_OpJavaCall* op, relocInfo::relocType rtype);
 227   void ic_call(     LIR_OpJavaCall* op);
 228   void vtable_call( LIR_OpJavaCall* op);
 229 
 230   void osr_entry();
 231 
 232   void build_frame();
 233 
 234   void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info);
 235   void unwind_op(LIR_Opr exceptionOop);
 236   void monitor_address(int monitor_ix, LIR_Opr dst);
 237 
 238   void align_backward_branch_target();
 239   void align_call(LIR_Code code);
 240 
 241   void negate(LIR_Opr left, LIR_Opr dest);
 242   void leal(LIR_Opr left, LIR_Opr dest);
 243 
 244   void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);
 245 
 246   void membar();
 247   void membar_acquire();
 248   void membar_release();
 249   void membar_loadload();
 250   void membar_storestore();
 251   void membar_loadstore();
 252   void membar_storeload();
 253   void on_spin_wait();
 254   void get_thread(LIR_Opr result);
 255 
 256   void verify_oop_map(CodeEmitInfo* info);
 257 
 258   void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp);
 259 
 260 #ifdef TARGET_ARCH_x86
 261 # include "c1_LIRAssembler_x86.hpp"
 262 #endif
 263 #ifdef TARGET_ARCH_sparc
 264 # include "c1_LIRAssembler_sparc.hpp"
 265 #endif
 266 #ifdef TARGET_ARCH_arm
 267 # include "c1_LIRAssembler_arm.hpp"
 268 #endif
 269 #ifdef TARGET_ARCH_ppc
 270 # include "c1_LIRAssembler_ppc.hpp"
 271 #endif
 272 #ifdef TARGET_ARCH_aarch64
 273 # include "c1_LIRAssembler_aarch64.hpp"
 274 #endif
 275 
 276 };
 277 
 278 #endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP