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src/share/vm/utilities/globalDefinitions.hpp

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rev 11647 : 8161258: Simplify including platform files.
Summary: Include patform files with macros cpu_header() etc. Do various cleanups of macro usages. Remove _64/_32 from adlc generated files and platform .hpp files. Merge stubRoutines_x86*.hpp. Remove empty mutex_<os>* files.
Reviewed-by: dholmes, coleenp, kbarrett


  56 #endif
  57 #ifndef PRAGMA_FORMAT_NONLITERAL_IGNORED
  58 #define PRAGMA_FORMAT_NONLITERAL_IGNORED
  59 #endif
  60 #ifndef PRAGMA_FORMAT_IGNORED
  61 #define PRAGMA_FORMAT_IGNORED
  62 #endif
  63 #ifndef PRAGMA_FORMAT_NONLITERAL_IGNORED_INTERNAL
  64 #define PRAGMA_FORMAT_NONLITERAL_IGNORED_INTERNAL
  65 #endif
  66 #ifndef PRAGMA_FORMAT_NONLITERAL_IGNORED_EXTERNAL
  67 #define PRAGMA_FORMAT_NONLITERAL_IGNORED_EXTERNAL
  68 #endif
  69 #ifndef ATTRIBUTE_PRINTF
  70 #define ATTRIBUTE_PRINTF(fmt, vargs)
  71 #endif
  72 #ifndef ATTRIBUTE_SCANF
  73 #define ATTRIBUTE_SCANF(fmt, vargs)
  74 #endif
  75 
  76 
  77 #include "utilities/macros.hpp"
  78 
  79 // This file holds all globally used constants & types, class (forward)
  80 // declarations and a few frequently used utility functions.
  81 
  82 //----------------------------------------------------------------------------------------------------
  83 // Constants
  84 
  85 const int LogBytesPerShort   = 1;
  86 const int LogBytesPerInt     = 2;
  87 #ifdef _LP64
  88 const int LogBytesPerWord    = 3;
  89 #else
  90 const int LogBytesPerWord    = 2;
  91 #endif
  92 const int LogBytesPerLong    = 3;
  93 
  94 const int BytesPerShort      = 1 << LogBytesPerShort;
  95 const int BytesPerInt        = 1 << LogBytesPerInt;
  96 const int BytesPerWord       = 1 << LogBytesPerWord;


 439 
 440 // Maximal size of compressed class space. Above this limit compression is not possible.
 441 // Also upper bound for placement of zero based class space. (Class space is further limited
 442 // to be < 3G, see arguments.cpp.)
 443 const  uint64_t KlassEncodingMetaspaceMax = (uint64_t(max_juint) + 1) << LogKlassAlignmentInBytes;
 444 
 445 // Machine dependent stuff
 446 
 447 // States of Restricted Transactional Memory usage.
 448 enum RTMState {
 449   NoRTM      = 0x2, // Don't use RTM
 450   UseRTM     = 0x1, // Use RTM
 451   ProfileRTM = 0x0  // Use RTM with abort ratio calculation
 452 };
 453 
 454 // The maximum size of the code cache.  Can be overridden by targets.
 455 #define CODE_CACHE_SIZE_LIMIT (2*G)
 456 // Allow targets to reduce the default size of the code cache.
 457 #define CODE_CACHE_DEFAULT_LIMIT CODE_CACHE_SIZE_LIMIT
 458 
 459 #ifdef TARGET_ARCH_x86
 460 # include "globalDefinitions_x86.hpp"
 461 #endif
 462 #ifdef TARGET_ARCH_sparc
 463 # include "globalDefinitions_sparc.hpp"
 464 #endif
 465 #ifdef TARGET_ARCH_zero
 466 # include "globalDefinitions_zero.hpp"
 467 #endif
 468 #ifdef TARGET_ARCH_arm
 469 # include "globalDefinitions_arm.hpp"
 470 #endif
 471 #ifdef TARGET_ARCH_ppc
 472 # include "globalDefinitions_ppc.hpp"
 473 #endif
 474 #ifdef TARGET_ARCH_aarch64
 475 # include "globalDefinitions_aarch64.hpp"
 476 #endif
 477 
 478 #ifndef INCLUDE_RTM_OPT
 479 #define INCLUDE_RTM_OPT 0
 480 #endif
 481 #if INCLUDE_RTM_OPT
 482 #define RTM_OPT_ONLY(code) code
 483 #else
 484 #define RTM_OPT_ONLY(code)
 485 #endif
 486 
 487 // To assure the IRIW property on processors that are not multiple copy
 488 // atomic, sync instructions must be issued between volatile reads to
 489 // assure their ordering, instead of after volatile stores.
 490 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
 491 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
 492 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
 493 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
 494 #else
 495 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
 496 #endif




  56 #endif
  57 #ifndef PRAGMA_FORMAT_NONLITERAL_IGNORED
  58 #define PRAGMA_FORMAT_NONLITERAL_IGNORED
  59 #endif
  60 #ifndef PRAGMA_FORMAT_IGNORED
  61 #define PRAGMA_FORMAT_IGNORED
  62 #endif
  63 #ifndef PRAGMA_FORMAT_NONLITERAL_IGNORED_INTERNAL
  64 #define PRAGMA_FORMAT_NONLITERAL_IGNORED_INTERNAL
  65 #endif
  66 #ifndef PRAGMA_FORMAT_NONLITERAL_IGNORED_EXTERNAL
  67 #define PRAGMA_FORMAT_NONLITERAL_IGNORED_EXTERNAL
  68 #endif
  69 #ifndef ATTRIBUTE_PRINTF
  70 #define ATTRIBUTE_PRINTF(fmt, vargs)
  71 #endif
  72 #ifndef ATTRIBUTE_SCANF
  73 #define ATTRIBUTE_SCANF(fmt, vargs)
  74 #endif
  75 

  76 #include "utilities/macros.hpp"
  77 
  78 // This file holds all globally used constants & types, class (forward)
  79 // declarations and a few frequently used utility functions.
  80 
  81 //----------------------------------------------------------------------------------------------------
  82 // Constants
  83 
  84 const int LogBytesPerShort   = 1;
  85 const int LogBytesPerInt     = 2;
  86 #ifdef _LP64
  87 const int LogBytesPerWord    = 3;
  88 #else
  89 const int LogBytesPerWord    = 2;
  90 #endif
  91 const int LogBytesPerLong    = 3;
  92 
  93 const int BytesPerShort      = 1 << LogBytesPerShort;
  94 const int BytesPerInt        = 1 << LogBytesPerInt;
  95 const int BytesPerWord       = 1 << LogBytesPerWord;


 438 
 439 // Maximal size of compressed class space. Above this limit compression is not possible.
 440 // Also upper bound for placement of zero based class space. (Class space is further limited
 441 // to be < 3G, see arguments.cpp.)
 442 const  uint64_t KlassEncodingMetaspaceMax = (uint64_t(max_juint) + 1) << LogKlassAlignmentInBytes;
 443 
 444 // Machine dependent stuff
 445 
 446 // States of Restricted Transactional Memory usage.
 447 enum RTMState {
 448   NoRTM      = 0x2, // Don't use RTM
 449   UseRTM     = 0x1, // Use RTM
 450   ProfileRTM = 0x0  // Use RTM with abort ratio calculation
 451 };
 452 
 453 // The maximum size of the code cache.  Can be overridden by targets.
 454 #define CODE_CACHE_SIZE_LIMIT (2*G)
 455 // Allow targets to reduce the default size of the code cache.
 456 #define CODE_CACHE_DEFAULT_LIMIT CODE_CACHE_SIZE_LIMIT
 457 
 458 #include CPU_HEADER(globalDefinitions)

















 459 
 460 #ifndef INCLUDE_RTM_OPT
 461 #define INCLUDE_RTM_OPT 0
 462 #endif
 463 #if INCLUDE_RTM_OPT
 464 #define RTM_OPT_ONLY(code) code
 465 #else
 466 #define RTM_OPT_ONLY(code)
 467 #endif
 468 
 469 // To assure the IRIW property on processors that are not multiple copy
 470 // atomic, sync instructions must be issued between volatile reads to
 471 // assure their ordering, instead of after volatile stores.
 472 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
 473 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
 474 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
 475 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
 476 #else
 477 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
 478 #endif


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