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src/share/vm/c1/c1_LIRGenerator.hpp
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rev 12113 : 8166561: [s390] Adaptions needed for s390 port in C1 and C2.
@@ -26,10 +26,11 @@
#define SHARE_VM_C1_C1_LIRGENERATOR_HPP
#include "c1/c1_Instruction.hpp"
#include "c1/c1_LIR.hpp"
#include "ci/ciMethodData.hpp"
+#include "utilities/macros.hpp"
#include "utilities/sizes.hpp"
// The classes responsible for code emission and register allocation
@@ -358,11 +359,11 @@
// the helper for generate_address
void add_large_constant(LIR_Opr src, int c, LIR_Opr dest);
// machine preferences and characteristics
- bool can_inline_as_constant(Value i) const;
+ bool can_inline_as_constant(Value i S390_ONLY(COMMA int bits = 20)) const;
bool can_inline_as_constant(LIR_Const* c) const;
bool can_store_as_constant(Value i, BasicType type) const;
LIR_Opr safepoint_poll_register();
@@ -494,10 +495,16 @@
static LIR_Opr exceptionOopOpr();
static LIR_Opr exceptionPcOpr();
static LIR_Opr divInOpr();
static LIR_Opr divOutOpr();
static LIR_Opr remOutOpr();
+#ifdef S390
+ // On S390 we can do ldiv, lrem without RT call.
+ static LIR_Opr ldivInOpr();
+ static LIR_Opr ldivOutOpr();
+ static LIR_Opr lremOutOpr();
+#endif
static LIR_Opr shiftCountOpr();
LIR_Opr syncLockOpr();
LIR_Opr syncTempOpr();
LIR_Opr atomicLockOpr();
@@ -619,11 +626,11 @@
void set_result(LIR_Opr opr);
void load_item();
void load_byte_item();
- void load_nonconstant();
+ void load_nonconstant(S390_ONLY(int bits = 20));
// load any values which can't be expressed as part of a single store instruction
void load_for_store(BasicType store_type);
void load_item_force(LIR_Opr reg);
void dont_load_item() {
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