1 /*
   2  * Copyright (c) 2005, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "runtime/timerTrace.hpp"
  36 #include "utilities/bitMap.inline.hpp"
  37 
  38 #ifndef PRODUCT
  39 
  40   static LinearScanStatistic _stat_before_alloc;
  41   static LinearScanStatistic _stat_after_asign;
  42   static LinearScanStatistic _stat_final;
  43 
  44   static LinearScanTimers _total_timer;
  45 
  46   // helper macro for short definition of timer
  47   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  48 
  49   // helper macro for short definition of trace-output inside code
  50   #define TRACE_LINEAR_SCAN(level, code)       \
  51     if (TraceLinearScanLevel >= level) {       \
  52       code;                                    \
  53     }
  54 
  55 #else
  56 
  57   #define TIME_LINEAR_SCAN(timer_name)
  58   #define TRACE_LINEAR_SCAN(level, code)
  59 
  60 #endif
  61 
  62 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  63 #ifdef _LP64
  64 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  65 #else
  66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  67 #endif
  68 
  69 
  70 // Implementation of LinearScan
  71 
  72 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  73  : _compilation(ir->compilation())
  74  , _ir(ir)
  75  , _gen(gen)
  76  , _frame_map(frame_map)
  77  , _num_virtual_regs(gen->max_virtual_register_number())
  78  , _has_fpu_registers(false)
  79  , _num_calls(-1)
  80  , _max_spills(0)
  81  , _unused_spill_slot(-1)
  82  , _intervals(0)   // initialized later with correct length
  83  , _new_intervals_from_allocation(new IntervalList())
  84  , _sorted_intervals(NULL)
  85  , _needs_full_resort(false)
  86  , _lir_ops(0)     // initialized later with correct length
  87  , _block_of_op(0) // initialized later with correct length
  88  , _has_info(0)
  89  , _has_call(0)
  90  , _scope_value_cache(0) // initialized later with correct length
  91  , _interval_in_loop(0)  // initialized later with correct length
  92  , _cached_blocks(*ir->linear_scan_order())
  93 #ifdef X86
  94  , _fpu_stack_allocator(NULL)
  95 #endif
  96 {
  97   assert(this->ir() != NULL,          "check if valid");
  98   assert(this->compilation() != NULL, "check if valid");
  99   assert(this->gen() != NULL,         "check if valid");
 100   assert(this->frame_map() != NULL,   "check if valid");
 101 }
 102 
 103 
 104 // ********** functions for converting LIR-Operands to register numbers
 105 //
 106 // Emulate a flat register file comprising physical integer registers,
 107 // physical floating-point registers and virtual registers, in that order.
 108 // Virtual registers already have appropriate numbers, since V0 is
 109 // the number of physical registers.
 110 // Returns -1 for hi word if opr is a single word operand.
 111 //
 112 // Note: the inverse operation (calculating an operand for register numbers)
 113 //       is done in calc_operand_for_interval()
 114 
 115 int LinearScan::reg_num(LIR_Opr opr) {
 116   assert(opr->is_register(), "should not call this otherwise");
 117 
 118   if (opr->is_virtual_register()) {
 119     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 120     return opr->vreg_number();
 121   } else if (opr->is_single_cpu()) {
 122     return opr->cpu_regnr();
 123   } else if (opr->is_double_cpu()) {
 124     return opr->cpu_regnrLo();
 125 #ifdef X86
 126   } else if (opr->is_single_xmm()) {
 127     return opr->fpu_regnr() + pd_first_xmm_reg;
 128   } else if (opr->is_double_xmm()) {
 129     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 130 #endif
 131   } else if (opr->is_single_fpu()) {
 132     return opr->fpu_regnr() + pd_first_fpu_reg;
 133   } else if (opr->is_double_fpu()) {
 134     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 135   } else {
 136     ShouldNotReachHere();
 137     return -1;
 138   }
 139 }
 140 
 141 int LinearScan::reg_numHi(LIR_Opr opr) {
 142   assert(opr->is_register(), "should not call this otherwise");
 143 
 144   if (opr->is_virtual_register()) {
 145     return -1;
 146   } else if (opr->is_single_cpu()) {
 147     return -1;
 148   } else if (opr->is_double_cpu()) {
 149     return opr->cpu_regnrHi();
 150 #ifdef X86
 151   } else if (opr->is_single_xmm()) {
 152     return -1;
 153   } else if (opr->is_double_xmm()) {
 154     return -1;
 155 #endif
 156   } else if (opr->is_single_fpu()) {
 157     return -1;
 158   } else if (opr->is_double_fpu()) {
 159     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 160   } else {
 161     ShouldNotReachHere();
 162     return -1;
 163   }
 164 }
 165 
 166 
 167 // ********** functions for classification of intervals
 168 
 169 bool LinearScan::is_precolored_interval(const Interval* i) {
 170   return i->reg_num() < LinearScan::nof_regs;
 171 }
 172 
 173 bool LinearScan::is_virtual_interval(const Interval* i) {
 174   return i->reg_num() >= LIR_OprDesc::vreg_base;
 175 }
 176 
 177 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 178   return i->reg_num() < LinearScan::nof_cpu_regs;
 179 }
 180 
 181 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 182 #if defined(__SOFTFP__) || defined(E500V2)
 183   return i->reg_num() >= LIR_OprDesc::vreg_base;
 184 #else
 185   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 186 #endif // __SOFTFP__ or E500V2
 187 }
 188 
 189 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 190   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 191 }
 192 
 193 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 194 #if defined(__SOFTFP__) || defined(E500V2)
 195   return false;
 196 #else
 197   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 198 #endif // __SOFTFP__ or E500V2
 199 }
 200 
 201 bool LinearScan::is_in_fpu_register(const Interval* i) {
 202   // fixed intervals not needed for FPU stack allocation
 203   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 204 }
 205 
 206 bool LinearScan::is_oop_interval(const Interval* i) {
 207   // fixed intervals never contain oops
 208   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 209 }
 210 
 211 
 212 // ********** General helper functions
 213 
 214 // compute next unused stack index that can be used for spilling
 215 int LinearScan::allocate_spill_slot(bool double_word) {
 216   int spill_slot;
 217   if (double_word) {
 218     if ((_max_spills & 1) == 1) {
 219       // alignment of double-word values
 220       // the hole because of the alignment is filled with the next single-word value
 221       assert(_unused_spill_slot == -1, "wasting a spill slot");
 222       _unused_spill_slot = _max_spills;
 223       _max_spills++;
 224     }
 225     spill_slot = _max_spills;
 226     _max_spills += 2;
 227 
 228   } else if (_unused_spill_slot != -1) {
 229     // re-use hole that was the result of a previous double-word alignment
 230     spill_slot = _unused_spill_slot;
 231     _unused_spill_slot = -1;
 232 
 233   } else {
 234     spill_slot = _max_spills;
 235     _max_spills++;
 236   }
 237 
 238   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 239 
 240   // the class OopMapValue uses only 11 bits for storing the name of the
 241   // oop location. So a stack slot bigger than 2^11 leads to an overflow
 242   // that is not reported in product builds. Prevent this by checking the
 243   // spill slot here (altough this value and the later used location name
 244   // are slightly different)
 245   if (result > 2000) {
 246     bailout("too many stack slots used");
 247   }
 248 
 249   return result;
 250 }
 251 
 252 void LinearScan::assign_spill_slot(Interval* it) {
 253   // assign the canonical spill slot of the parent (if a part of the interval
 254   // is already spilled) or allocate a new spill slot
 255   if (it->canonical_spill_slot() >= 0) {
 256     it->assign_reg(it->canonical_spill_slot());
 257   } else {
 258     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 259     it->set_canonical_spill_slot(spill);
 260     it->assign_reg(spill);
 261   }
 262 }
 263 
 264 void LinearScan::propagate_spill_slots() {
 265   if (!frame_map()->finalize_frame(max_spills())) {
 266     bailout("frame too large");
 267   }
 268 }
 269 
 270 // create a new interval with a predefined reg_num
 271 // (only used for parent intervals that are created during the building phase)
 272 Interval* LinearScan::create_interval(int reg_num) {
 273   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 274 
 275   Interval* interval = new Interval(reg_num);
 276   _intervals.at_put(reg_num, interval);
 277 
 278   // assign register number for precolored intervals
 279   if (reg_num < LIR_OprDesc::vreg_base) {
 280     interval->assign_reg(reg_num);
 281   }
 282   return interval;
 283 }
 284 
 285 // assign a new reg_num to the interval and append it to the list of intervals
 286 // (only used for child intervals that are created during register allocation)
 287 void LinearScan::append_interval(Interval* it) {
 288   it->set_reg_num(_intervals.length());
 289   _intervals.append(it);
 290   _new_intervals_from_allocation->append(it);
 291 }
 292 
 293 // copy the vreg-flags if an interval is split
 294 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 295   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 296     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 297   }
 298   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 299     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 300   }
 301 
 302   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 303   //       intervals (only the very beginning of the interval must be in memory)
 304 }
 305 
 306 
 307 // ********** spill move optimization
 308 // eliminate moves from register to stack if stack slot is known to be correct
 309 
 310 // called during building of intervals
 311 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 312   assert(interval->is_split_parent(), "can only be called for split parents");
 313 
 314   switch (interval->spill_state()) {
 315     case noDefinitionFound:
 316       assert(interval->spill_definition_pos() == -1, "must no be set before");
 317       interval->set_spill_definition_pos(def_pos);
 318       interval->set_spill_state(oneDefinitionFound);
 319       break;
 320 
 321     case oneDefinitionFound:
 322       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 323       if (def_pos < interval->spill_definition_pos() - 2) {
 324         // second definition found, so no spill optimization possible for this interval
 325         interval->set_spill_state(noOptimization);
 326       } else {
 327         // two consecutive definitions (because of two-operand LIR form)
 328         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 329       }
 330       break;
 331 
 332     case noOptimization:
 333       // nothing to do
 334       break;
 335 
 336     default:
 337       assert(false, "other states not allowed at this time");
 338   }
 339 }
 340 
 341 // called during register allocation
 342 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 343   switch (interval->spill_state()) {
 344     case oneDefinitionFound: {
 345       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 346       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 347 
 348       if (def_loop_depth < spill_loop_depth) {
 349         // the loop depth of the spilling position is higher then the loop depth
 350         // at the definition of the interval -> move write to memory out of loop
 351         // by storing at definitin of the interval
 352         interval->set_spill_state(storeAtDefinition);
 353       } else {
 354         // the interval is currently spilled only once, so for now there is no
 355         // reason to store the interval at the definition
 356         interval->set_spill_state(oneMoveInserted);
 357       }
 358       break;
 359     }
 360 
 361     case oneMoveInserted: {
 362       // the interval is spilled more then once, so it is better to store it to
 363       // memory at the definition
 364       interval->set_spill_state(storeAtDefinition);
 365       break;
 366     }
 367 
 368     case storeAtDefinition:
 369     case startInMemory:
 370     case noOptimization:
 371     case noDefinitionFound:
 372       // nothing to do
 373       break;
 374 
 375     default:
 376       assert(false, "other states not allowed at this time");
 377   }
 378 }
 379 
 380 
 381 bool LinearScan::must_store_at_definition(const Interval* i) {
 382   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 383 }
 384 
 385 // called once before asignment of register numbers
 386 void LinearScan::eliminate_spill_moves() {
 387   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 388   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 389 
 390   // collect all intervals that must be stored after their definion.
 391   // the list is sorted by Interval::spill_definition_pos
 392   Interval* interval;
 393   Interval* temp_list;
 394   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 395 
 396 #ifdef ASSERT
 397   Interval* prev = NULL;
 398   Interval* temp = interval;
 399   while (temp != Interval::end()) {
 400     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 401     if (prev != NULL) {
 402       assert(temp->from() >= prev->from(), "intervals not sorted");
 403       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 404     }
 405 
 406     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 407     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 408     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 409 
 410     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 411 
 412     temp = temp->next();
 413   }
 414 #endif
 415 
 416   LIR_InsertionBuffer insertion_buffer;
 417   int num_blocks = block_count();
 418   for (int i = 0; i < num_blocks; i++) {
 419     BlockBegin* block = block_at(i);
 420     LIR_OpList* instructions = block->lir()->instructions_list();
 421     int         num_inst = instructions->length();
 422     bool        has_new = false;
 423 
 424     // iterate all instructions of the block. skip the first because it is always a label
 425     for (int j = 1; j < num_inst; j++) {
 426       LIR_Op* op = instructions->at(j);
 427       int op_id = op->id();
 428 
 429       if (op_id == -1) {
 430         // remove move from register to stack if the stack slot is guaranteed to be correct.
 431         // only moves that have been inserted by LinearScan can be removed.
 432         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 433         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 434         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 435 
 436         LIR_Op1* op1 = (LIR_Op1*)op;
 437         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 438 
 439         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 440           // move target is a stack slot that is always correct, so eliminate instruction
 441           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 442           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 443         }
 444 
 445       } else {
 446         // insert move from register to stack just after the beginning of the interval
 447         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 448         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 449 
 450         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 451           if (!has_new) {
 452             // prepare insertion buffer (appended when all instructions of the block are processed)
 453             insertion_buffer.init(block->lir());
 454             has_new = true;
 455           }
 456 
 457           LIR_Opr from_opr = operand_for_interval(interval);
 458           LIR_Opr to_opr = canonical_spill_opr(interval);
 459           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 460           assert(to_opr->is_stack(), "to operand must be a stack slot");
 461 
 462           insertion_buffer.move(j, from_opr, to_opr);
 463           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 464 
 465           interval = interval->next();
 466         }
 467       }
 468     } // end of instruction iteration
 469 
 470     if (has_new) {
 471       block->lir()->append(&insertion_buffer);
 472     }
 473   } // end of block iteration
 474 
 475   assert(interval == Interval::end(), "missed an interval");
 476 }
 477 
 478 
 479 // ********** Phase 1: number all instructions in all blocks
 480 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 481 
 482 void LinearScan::number_instructions() {
 483   {
 484     // dummy-timer to measure the cost of the timer itself
 485     // (this time is then subtracted from all other timers to get the real value)
 486     TIME_LINEAR_SCAN(timer_do_nothing);
 487   }
 488   TIME_LINEAR_SCAN(timer_number_instructions);
 489 
 490   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 491   int num_blocks = block_count();
 492   int num_instructions = 0;
 493   int i;
 494   for (i = 0; i < num_blocks; i++) {
 495     num_instructions += block_at(i)->lir()->instructions_list()->length();
 496   }
 497 
 498   // initialize with correct length
 499   _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
 500   _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
 501 
 502   int op_id = 0;
 503   int idx = 0;
 504 
 505   for (i = 0; i < num_blocks; i++) {
 506     BlockBegin* block = block_at(i);
 507     block->set_first_lir_instruction_id(op_id);
 508     LIR_OpList* instructions = block->lir()->instructions_list();
 509 
 510     int num_inst = instructions->length();
 511     for (int j = 0; j < num_inst; j++) {
 512       LIR_Op* op = instructions->at(j);
 513       op->set_id(op_id);
 514 
 515       _lir_ops.at_put(idx, op);
 516       _block_of_op.at_put(idx, block);
 517       assert(lir_op_with_id(op_id) == op, "must match");
 518 
 519       idx++;
 520       op_id += 2; // numbering of lir_ops by two
 521     }
 522     block->set_last_lir_instruction_id(op_id - 2);
 523   }
 524   assert(idx == num_instructions, "must match");
 525   assert(idx * 2 == op_id, "must match");
 526 
 527   _has_call.initialize(num_instructions);
 528   _has_info.initialize(num_instructions);
 529 }
 530 
 531 
 532 // ********** Phase 2: compute local live sets separately for each block
 533 // (sets live_gen and live_kill for each block)
 534 
 535 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 536   LIR_Opr opr = value->operand();
 537   Constant* con = value->as_Constant();
 538 
 539   // check some asumptions about debug information
 540   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 541   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 542   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 543 
 544   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 545     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 546     int reg = opr->vreg_number();
 547     if (!live_kill.at(reg)) {
 548       live_gen.set_bit(reg);
 549       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 550     }
 551   }
 552 }
 553 
 554 
 555 void LinearScan::compute_local_live_sets() {
 556   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 557 
 558   int  num_blocks = block_count();
 559   int  live_size = live_set_size();
 560   bool local_has_fpu_registers = false;
 561   int  local_num_calls = 0;
 562   LIR_OpVisitState visitor;
 563 
 564   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 565 
 566   // iterate all blocks
 567   for (int i = 0; i < num_blocks; i++) {
 568     BlockBegin* block = block_at(i);
 569 
 570     ResourceBitMap live_gen(live_size);
 571     ResourceBitMap live_kill(live_size);
 572 
 573     if (block->is_set(BlockBegin::exception_entry_flag)) {
 574       // Phi functions at the begin of an exception handler are
 575       // implicitly defined (= killed) at the beginning of the block.
 576       for_each_phi_fun(block, phi,
 577         live_kill.set_bit(phi->operand()->vreg_number())
 578       );
 579     }
 580 
 581     LIR_OpList* instructions = block->lir()->instructions_list();
 582     int num_inst = instructions->length();
 583 
 584     // iterate all instructions of the block. skip the first because it is always a label
 585     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 586     for (int j = 1; j < num_inst; j++) {
 587       LIR_Op* op = instructions->at(j);
 588 
 589       // visit operation to collect all operands
 590       visitor.visit(op);
 591 
 592       if (visitor.has_call()) {
 593         _has_call.set_bit(op->id() >> 1);
 594         local_num_calls++;
 595       }
 596       if (visitor.info_count() > 0) {
 597         _has_info.set_bit(op->id() >> 1);
 598       }
 599 
 600       // iterate input operands of instruction
 601       int k, n, reg;
 602       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 603       for (k = 0; k < n; k++) {
 604         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 605         assert(opr->is_register(), "visitor should only return register operands");
 606 
 607         if (opr->is_virtual_register()) {
 608           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 609           reg = opr->vreg_number();
 610           if (!live_kill.at(reg)) {
 611             live_gen.set_bit(reg);
 612             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 613           }
 614           if (block->loop_index() >= 0) {
 615             local_interval_in_loop.set_bit(reg, block->loop_index());
 616           }
 617           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 618         }
 619 
 620 #ifdef ASSERT
 621         // fixed intervals are never live at block boundaries, so
 622         // they need not be processed in live sets.
 623         // this is checked by these assertions to be sure about it.
 624         // the entry block may have incoming values in registers, which is ok.
 625         if (!opr->is_virtual_register() && block != ir()->start()) {
 626           reg = reg_num(opr);
 627           if (is_processed_reg_num(reg)) {
 628             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 629           }
 630           reg = reg_numHi(opr);
 631           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 632             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 633           }
 634         }
 635 #endif
 636       }
 637 
 638       // Add uses of live locals from interpreter's point of view for proper debug information generation
 639       n = visitor.info_count();
 640       for (k = 0; k < n; k++) {
 641         CodeEmitInfo* info = visitor.info_at(k);
 642         ValueStack* stack = info->stack();
 643         for_each_state_value(stack, value,
 644           set_live_gen_kill(value, op, live_gen, live_kill)
 645         );
 646       }
 647 
 648       // iterate temp operands of instruction
 649       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 650       for (k = 0; k < n; k++) {
 651         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 652         assert(opr->is_register(), "visitor should only return register operands");
 653 
 654         if (opr->is_virtual_register()) {
 655           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 656           reg = opr->vreg_number();
 657           live_kill.set_bit(reg);
 658           if (block->loop_index() >= 0) {
 659             local_interval_in_loop.set_bit(reg, block->loop_index());
 660           }
 661           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 662         }
 663 
 664 #ifdef ASSERT
 665         // fixed intervals are never live at block boundaries, so
 666         // they need not be processed in live sets
 667         // process them only in debug mode so that this can be checked
 668         if (!opr->is_virtual_register()) {
 669           reg = reg_num(opr);
 670           if (is_processed_reg_num(reg)) {
 671             live_kill.set_bit(reg_num(opr));
 672           }
 673           reg = reg_numHi(opr);
 674           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 675             live_kill.set_bit(reg);
 676           }
 677         }
 678 #endif
 679       }
 680 
 681       // iterate output operands of instruction
 682       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 683       for (k = 0; k < n; k++) {
 684         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 685         assert(opr->is_register(), "visitor should only return register operands");
 686 
 687         if (opr->is_virtual_register()) {
 688           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 689           reg = opr->vreg_number();
 690           live_kill.set_bit(reg);
 691           if (block->loop_index() >= 0) {
 692             local_interval_in_loop.set_bit(reg, block->loop_index());
 693           }
 694           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 695         }
 696 
 697 #ifdef ASSERT
 698         // fixed intervals are never live at block boundaries, so
 699         // they need not be processed in live sets
 700         // process them only in debug mode so that this can be checked
 701         if (!opr->is_virtual_register()) {
 702           reg = reg_num(opr);
 703           if (is_processed_reg_num(reg)) {
 704             live_kill.set_bit(reg_num(opr));
 705           }
 706           reg = reg_numHi(opr);
 707           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 708             live_kill.set_bit(reg);
 709           }
 710         }
 711 #endif
 712       }
 713     } // end of instruction iteration
 714 
 715     block->set_live_gen (live_gen);
 716     block->set_live_kill(live_kill);
 717     block->set_live_in  (ResourceBitMap(live_size));
 718     block->set_live_out (ResourceBitMap(live_size));
 719 
 720     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 721     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 722   } // end of block iteration
 723 
 724   // propagate local calculated information into LinearScan object
 725   _has_fpu_registers = local_has_fpu_registers;
 726   compilation()->set_has_fpu_code(local_has_fpu_registers);
 727 
 728   _num_calls = local_num_calls;
 729   _interval_in_loop = local_interval_in_loop;
 730 }
 731 
 732 
 733 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 734 // (sets live_in and live_out for each block)
 735 
 736 void LinearScan::compute_global_live_sets() {
 737   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 738 
 739   int  num_blocks = block_count();
 740   bool change_occurred;
 741   bool change_occurred_in_block;
 742   int  iteration_count = 0;
 743   ResourceBitMap live_out(live_set_size()); // scratch set for calculations
 744 
 745   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 746   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 747   // Exception handlers must be processed because not all live values are
 748   // present in the state array, e.g. because of global value numbering
 749   do {
 750     change_occurred = false;
 751 
 752     // iterate all blocks in reverse order
 753     for (int i = num_blocks - 1; i >= 0; i--) {
 754       BlockBegin* block = block_at(i);
 755 
 756       change_occurred_in_block = false;
 757 
 758       // live_out(block) is the union of live_in(sux), for successors sux of block
 759       int n = block->number_of_sux();
 760       int e = block->number_of_exception_handlers();
 761       if (n + e > 0) {
 762         // block has successors
 763         if (n > 0) {
 764           live_out.set_from(block->sux_at(0)->live_in());
 765           for (int j = 1; j < n; j++) {
 766             live_out.set_union(block->sux_at(j)->live_in());
 767           }
 768         } else {
 769           live_out.clear();
 770         }
 771         for (int j = 0; j < e; j++) {
 772           live_out.set_union(block->exception_handler_at(j)->live_in());
 773         }
 774 
 775         if (!block->live_out().is_same(live_out)) {
 776           // A change occurred.  Swap the old and new live out sets to avoid copying.
 777           ResourceBitMap temp = block->live_out();
 778           block->set_live_out(live_out);
 779           live_out = temp;
 780 
 781           change_occurred = true;
 782           change_occurred_in_block = true;
 783         }
 784       }
 785 
 786       if (iteration_count == 0 || change_occurred_in_block) {
 787         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 788         // note: live_in has to be computed only in first iteration or if live_out has changed!
 789         ResourceBitMap live_in = block->live_in();
 790         live_in.set_from(block->live_out());
 791         live_in.set_difference(block->live_kill());
 792         live_in.set_union(block->live_gen());
 793       }
 794 
 795 #ifndef PRODUCT
 796       if (TraceLinearScanLevel >= 4) {
 797         char c = ' ';
 798         if (iteration_count == 0 || change_occurred_in_block) {
 799           c = '*';
 800         }
 801         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 802         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 803       }
 804 #endif
 805     }
 806     iteration_count++;
 807 
 808     if (change_occurred && iteration_count > 50) {
 809       BAILOUT("too many iterations in compute_global_live_sets");
 810     }
 811   } while (change_occurred);
 812 
 813 
 814 #ifdef ASSERT
 815   // check that fixed intervals are not live at block boundaries
 816   // (live set must be empty at fixed intervals)
 817   for (int i = 0; i < num_blocks; i++) {
 818     BlockBegin* block = block_at(i);
 819     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 820       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 821       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 822       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 823     }
 824   }
 825 #endif
 826 
 827   // check that the live_in set of the first block is empty
 828   ResourceBitMap live_in_args(ir()->start()->live_in().size());
 829   if (!ir()->start()->live_in().is_same(live_in_args)) {
 830 #ifdef ASSERT
 831     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 832     tty->print_cr("affected registers:");
 833     print_bitmap(ir()->start()->live_in());
 834 
 835     // print some additional information to simplify debugging
 836     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 837       if (ir()->start()->live_in().at(i)) {
 838         Instruction* instr = gen()->instruction_for_vreg(i);
 839         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 840 
 841         for (int j = 0; j < num_blocks; j++) {
 842           BlockBegin* block = block_at(j);
 843           if (block->live_gen().at(i)) {
 844             tty->print_cr("  used in block B%d", block->block_id());
 845           }
 846           if (block->live_kill().at(i)) {
 847             tty->print_cr("  defined in block B%d", block->block_id());
 848           }
 849         }
 850       }
 851     }
 852 
 853 #endif
 854     // when this fails, virtual registers are used before they are defined.
 855     assert(false, "live_in set of first block must be empty");
 856     // bailout of if this occurs in product mode.
 857     bailout("live_in set of first block not empty");
 858   }
 859 }
 860 
 861 
 862 // ********** Phase 4: build intervals
 863 // (fills the list _intervals)
 864 
 865 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 866   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 867   LIR_Opr opr = value->operand();
 868   Constant* con = value->as_Constant();
 869 
 870   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 871     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 872     add_use(opr, from, to, use_kind);
 873   }
 874 }
 875 
 876 
 877 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 878   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 879   assert(opr->is_register(), "should not be called otherwise");
 880 
 881   if (opr->is_virtual_register()) {
 882     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 883     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 884 
 885   } else {
 886     int reg = reg_num(opr);
 887     if (is_processed_reg_num(reg)) {
 888       add_def(reg, def_pos, use_kind, opr->type_register());
 889     }
 890     reg = reg_numHi(opr);
 891     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 892       add_def(reg, def_pos, use_kind, opr->type_register());
 893     }
 894   }
 895 }
 896 
 897 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 898   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 899   assert(opr->is_register(), "should not be called otherwise");
 900 
 901   if (opr->is_virtual_register()) {
 902     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 903     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 904 
 905   } else {
 906     int reg = reg_num(opr);
 907     if (is_processed_reg_num(reg)) {
 908       add_use(reg, from, to, use_kind, opr->type_register());
 909     }
 910     reg = reg_numHi(opr);
 911     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 912       add_use(reg, from, to, use_kind, opr->type_register());
 913     }
 914   }
 915 }
 916 
 917 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 918   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 919   assert(opr->is_register(), "should not be called otherwise");
 920 
 921   if (opr->is_virtual_register()) {
 922     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 923     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 924 
 925   } else {
 926     int reg = reg_num(opr);
 927     if (is_processed_reg_num(reg)) {
 928       add_temp(reg, temp_pos, use_kind, opr->type_register());
 929     }
 930     reg = reg_numHi(opr);
 931     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 932       add_temp(reg, temp_pos, use_kind, opr->type_register());
 933     }
 934   }
 935 }
 936 
 937 
 938 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 939   Interval* interval = interval_at(reg_num);
 940   if (interval != NULL) {
 941     assert(interval->reg_num() == reg_num, "wrong interval");
 942 
 943     if (type != T_ILLEGAL) {
 944       interval->set_type(type);
 945     }
 946 
 947     Range* r = interval->first();
 948     if (r->from() <= def_pos) {
 949       // Update the starting point (when a range is first created for a use, its
 950       // start is the beginning of the current block until a def is encountered.)
 951       r->set_from(def_pos);
 952       interval->add_use_pos(def_pos, use_kind);
 953 
 954     } else {
 955       // Dead value - make vacuous interval
 956       // also add use_kind for dead intervals
 957       interval->add_range(def_pos, def_pos + 1);
 958       interval->add_use_pos(def_pos, use_kind);
 959       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 960     }
 961 
 962   } else {
 963     // Dead value - make vacuous interval
 964     // also add use_kind for dead intervals
 965     interval = create_interval(reg_num);
 966     if (type != T_ILLEGAL) {
 967       interval->set_type(type);
 968     }
 969 
 970     interval->add_range(def_pos, def_pos + 1);
 971     interval->add_use_pos(def_pos, use_kind);
 972     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 973   }
 974 
 975   change_spill_definition_pos(interval, def_pos);
 976   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 977         // detection of method-parameters and roundfp-results
 978         // TODO: move this directly to position where use-kind is computed
 979     interval->set_spill_state(startInMemory);
 980   }
 981 }
 982 
 983 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 984   Interval* interval = interval_at(reg_num);
 985   if (interval == NULL) {
 986     interval = create_interval(reg_num);
 987   }
 988   assert(interval->reg_num() == reg_num, "wrong interval");
 989 
 990   if (type != T_ILLEGAL) {
 991     interval->set_type(type);
 992   }
 993 
 994   interval->add_range(from, to);
 995   interval->add_use_pos(to, use_kind);
 996 }
 997 
 998 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
 999   Interval* interval = interval_at(reg_num);
1000   if (interval == NULL) {
1001     interval = create_interval(reg_num);
1002   }
1003   assert(interval->reg_num() == reg_num, "wrong interval");
1004 
1005   if (type != T_ILLEGAL) {
1006     interval->set_type(type);
1007   }
1008 
1009   interval->add_range(temp_pos, temp_pos + 1);
1010   interval->add_use_pos(temp_pos, use_kind);
1011 }
1012 
1013 
1014 // the results of this functions are used for optimizing spilling and reloading
1015 // if the functions return shouldHaveRegister and the interval is spilled,
1016 // it is not reloaded to a register.
1017 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1018   if (op->code() == lir_move) {
1019     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1020     LIR_Op1* move = (LIR_Op1*)op;
1021     LIR_Opr res = move->result_opr();
1022     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1023 
1024     if (result_in_memory) {
1025       // Begin of an interval with must_start_in_memory set.
1026       // This interval will always get a stack slot first, so return noUse.
1027       return noUse;
1028 
1029     } else if (move->in_opr()->is_stack()) {
1030       // method argument (condition must be equal to handle_method_arguments)
1031       return noUse;
1032 
1033     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1034       // Move from register to register
1035       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1036         // special handling of phi-function moves inside osr-entry blocks
1037         // input operand must have a register instead of output operand (leads to better register allocation)
1038         return shouldHaveRegister;
1039       }
1040     }
1041   }
1042 
1043   if (opr->is_virtual() &&
1044       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1045     // result is a stack-slot, so prevent immediate reloading
1046     return noUse;
1047   }
1048 
1049   // all other operands require a register
1050   return mustHaveRegister;
1051 }
1052 
1053 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1054   if (op->code() == lir_move) {
1055     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1056     LIR_Op1* move = (LIR_Op1*)op;
1057     LIR_Opr res = move->result_opr();
1058     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1059 
1060     if (result_in_memory) {
1061       // Move to an interval with must_start_in_memory set.
1062       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1063       return mustHaveRegister;
1064 
1065     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1066       // Move from register to register
1067       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1068         // special handling of phi-function moves inside osr-entry blocks
1069         // input operand must have a register instead of output operand (leads to better register allocation)
1070         return mustHaveRegister;
1071       }
1072 
1073       // The input operand is not forced to a register (moves from stack to register are allowed),
1074       // but it is faster if the input operand is in a register
1075       return shouldHaveRegister;
1076     }
1077   }
1078 
1079 
1080 #if defined(X86) || defined(S390)
1081   if (op->code() == lir_cmove) {
1082     // conditional moves can handle stack operands
1083     assert(op->result_opr()->is_register(), "result must always be in a register");
1084     return shouldHaveRegister;
1085   }
1086 
1087   // optimizations for second input operand of arithmehtic operations on Intel
1088   // this operand is allowed to be on the stack in some cases
1089   BasicType opr_type = opr->type_register();
1090   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091     if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 S390_ONLY(|| true)) {
1092       // SSE float instruction (T_DOUBLE only supported with SSE2)
1093       switch (op->code()) {
1094         case lir_cmp:
1095         case lir_add:
1096         case lir_sub:
1097         case lir_mul:
1098         case lir_div:
1099         {
1100           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1101           LIR_Op2* op2 = (LIR_Op2*)op;
1102           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1103             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1104             return shouldHaveRegister;
1105           }
1106         }
1107       }
1108     } else {
1109       // FPU stack float instruction
1110       switch (op->code()) {
1111         case lir_add:
1112         case lir_sub:
1113         case lir_mul:
1114         case lir_div:
1115         {
1116           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1117           LIR_Op2* op2 = (LIR_Op2*)op;
1118           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1119             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1120             return shouldHaveRegister;
1121           }
1122         }
1123       }
1124     }
1125     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1126     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1127     // T_OBJECT doesn't get spilled along with T_LONG.
1128   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1129     // integer instruction (note: long operands must always be in register)
1130     switch (op->code()) {
1131       case lir_cmp:
1132       case lir_add:
1133       case lir_sub:
1134       case lir_logic_and:
1135       case lir_logic_or:
1136       case lir_logic_xor:
1137       {
1138         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1139         LIR_Op2* op2 = (LIR_Op2*)op;
1140         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1141           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1142           return shouldHaveRegister;
1143         }
1144       }
1145     }
1146   }
1147 #endif // X86 S390
1148 
1149   // all other operands require a register
1150   return mustHaveRegister;
1151 }
1152 
1153 
1154 void LinearScan::handle_method_arguments(LIR_Op* op) {
1155   // special handling for method arguments (moves from stack to virtual register):
1156   // the interval gets no register assigned, but the stack slot.
1157   // it is split before the first use by the register allocator.
1158 
1159   if (op->code() == lir_move) {
1160     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1161     LIR_Op1* move = (LIR_Op1*)op;
1162 
1163     if (move->in_opr()->is_stack()) {
1164 #ifdef ASSERT
1165       int arg_size = compilation()->method()->arg_size();
1166       LIR_Opr o = move->in_opr();
1167       if (o->is_single_stack()) {
1168         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1169       } else if (o->is_double_stack()) {
1170         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1171       } else {
1172         ShouldNotReachHere();
1173       }
1174 
1175       assert(move->id() > 0, "invalid id");
1176       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1177       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1178 
1179       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1180 #endif
1181 
1182       Interval* interval = interval_at(reg_num(move->result_opr()));
1183 
1184       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1185       interval->set_canonical_spill_slot(stack_slot);
1186       interval->assign_reg(stack_slot);
1187     }
1188   }
1189 }
1190 
1191 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1192   // special handling for doubleword move from memory to register:
1193   // in this case the registers of the input address and the result
1194   // registers must not overlap -> add a temp range for the input registers
1195   if (op->code() == lir_move) {
1196     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1197     LIR_Op1* move = (LIR_Op1*)op;
1198 
1199     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1200       LIR_Address* address = move->in_opr()->as_address_ptr();
1201       if (address != NULL) {
1202         if (address->base()->is_valid()) {
1203           add_temp(address->base(), op->id(), noUse);
1204         }
1205         if (address->index()->is_valid()) {
1206           add_temp(address->index(), op->id(), noUse);
1207         }
1208       }
1209     }
1210   }
1211 }
1212 
1213 void LinearScan::add_register_hints(LIR_Op* op) {
1214   switch (op->code()) {
1215     case lir_move:      // fall through
1216     case lir_convert: {
1217       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1218       LIR_Op1* move = (LIR_Op1*)op;
1219 
1220       LIR_Opr move_from = move->in_opr();
1221       LIR_Opr move_to = move->result_opr();
1222 
1223       if (move_to->is_register() && move_from->is_register()) {
1224         Interval* from = interval_at(reg_num(move_from));
1225         Interval* to = interval_at(reg_num(move_to));
1226         if (from != NULL && to != NULL) {
1227           to->set_register_hint(from);
1228           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1229         }
1230       }
1231       break;
1232     }
1233     case lir_cmove: {
1234       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1235       LIR_Op2* cmove = (LIR_Op2*)op;
1236 
1237       LIR_Opr move_from = cmove->in_opr1();
1238       LIR_Opr move_to = cmove->result_opr();
1239 
1240       if (move_to->is_register() && move_from->is_register()) {
1241         Interval* from = interval_at(reg_num(move_from));
1242         Interval* to = interval_at(reg_num(move_to));
1243         if (from != NULL && to != NULL) {
1244           to->set_register_hint(from);
1245           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1246         }
1247       }
1248       break;
1249     }
1250   }
1251 }
1252 
1253 
1254 void LinearScan::build_intervals() {
1255   TIME_LINEAR_SCAN(timer_build_intervals);
1256 
1257   // initialize interval list with expected number of intervals
1258   // (32 is added to have some space for split children without having to resize the list)
1259   _intervals = IntervalList(num_virtual_regs() + 32);
1260   // initialize all slots that are used by build_intervals
1261   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1262 
1263   // create a list with all caller-save registers (cpu, fpu, xmm)
1264   // when an instruction is a call, a temp range is created for all these registers
1265   int num_caller_save_registers = 0;
1266   int caller_save_registers[LinearScan::nof_regs];
1267 
1268   int i;
1269   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1270     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1271     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1272     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1273     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1274   }
1275 
1276   // temp ranges for fpu registers are only created when the method has
1277   // virtual fpu operands. Otherwise no allocation for fpu registers is
1278   // perfomed and so the temp ranges would be useless
1279   if (has_fpu_registers()) {
1280 #ifdef X86
1281     if (UseSSE < 2) {
1282 #endif
1283       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1284         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1285         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1286         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1287         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1288       }
1289 #ifdef X86
1290     }
1291     if (UseSSE > 0) {
1292       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1293       for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1294         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1295         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1296         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1297         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1298       }
1299     }
1300 #endif
1301   }
1302   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1303 
1304 
1305   LIR_OpVisitState visitor;
1306 
1307   // iterate all blocks in reverse order
1308   for (i = block_count() - 1; i >= 0; i--) {
1309     BlockBegin* block = block_at(i);
1310     LIR_OpList* instructions = block->lir()->instructions_list();
1311     int         block_from =   block->first_lir_instruction_id();
1312     int         block_to =     block->last_lir_instruction_id();
1313 
1314     assert(block_from == instructions->at(0)->id(), "must be");
1315     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1316 
1317     // Update intervals for registers live at the end of this block;
1318     ResourceBitMap live = block->live_out();
1319     int size = (int)live.size();
1320     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1321       assert(live.at(number), "should not stop here otherwise");
1322       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1323       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1324 
1325       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1326 
1327       // add special use positions for loop-end blocks when the
1328       // interval is used anywhere inside this loop.  It's possible
1329       // that the block was part of a non-natural loop, so it might
1330       // have an invalid loop index.
1331       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1332           block->loop_index() != -1 &&
1333           is_interval_in_loop(number, block->loop_index())) {
1334         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1335       }
1336     }
1337 
1338     // iterate all instructions of the block in reverse order.
1339     // skip the first instruction because it is always a label
1340     // definitions of intervals are processed before uses
1341     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1342     for (int j = instructions->length() - 1; j >= 1; j--) {
1343       LIR_Op* op = instructions->at(j);
1344       int op_id = op->id();
1345 
1346       // visit operation to collect all operands
1347       visitor.visit(op);
1348 
1349       // add a temp range for each register if operation destroys caller-save registers
1350       if (visitor.has_call()) {
1351         for (int k = 0; k < num_caller_save_registers; k++) {
1352           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1353         }
1354         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1355       }
1356 
1357       // Add any platform dependent temps
1358       pd_add_temps(op);
1359 
1360       // visit definitions (output and temp operands)
1361       int k, n;
1362       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1363       for (k = 0; k < n; k++) {
1364         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1365         assert(opr->is_register(), "visitor should only return register operands");
1366         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1367       }
1368 
1369       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1370       for (k = 0; k < n; k++) {
1371         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1372         assert(opr->is_register(), "visitor should only return register operands");
1373         add_temp(opr, op_id, mustHaveRegister);
1374       }
1375 
1376       // visit uses (input operands)
1377       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1378       for (k = 0; k < n; k++) {
1379         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1380         assert(opr->is_register(), "visitor should only return register operands");
1381         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1382       }
1383 
1384       // Add uses of live locals from interpreter's point of view for proper
1385       // debug information generation
1386       // Treat these operands as temp values (if the life range is extended
1387       // to a call site, the value would be in a register at the call otherwise)
1388       n = visitor.info_count();
1389       for (k = 0; k < n; k++) {
1390         CodeEmitInfo* info = visitor.info_at(k);
1391         ValueStack* stack = info->stack();
1392         for_each_state_value(stack, value,
1393           add_use(value, block_from, op_id + 1, noUse);
1394         );
1395       }
1396 
1397       // special steps for some instructions (especially moves)
1398       handle_method_arguments(op);
1399       handle_doubleword_moves(op);
1400       add_register_hints(op);
1401 
1402     } // end of instruction iteration
1403   } // end of block iteration
1404 
1405 
1406   // add the range [0, 1[ to all fixed intervals
1407   // -> the register allocator need not handle unhandled fixed intervals
1408   for (int n = 0; n < LinearScan::nof_regs; n++) {
1409     Interval* interval = interval_at(n);
1410     if (interval != NULL) {
1411       interval->add_range(0, 1);
1412     }
1413   }
1414 }
1415 
1416 
1417 // ********** Phase 5: actual register allocation
1418 
1419 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1420   if (*a != NULL) {
1421     if (*b != NULL) {
1422       return (*a)->from() - (*b)->from();
1423     } else {
1424       return -1;
1425     }
1426   } else {
1427     if (*b != NULL) {
1428       return 1;
1429     } else {
1430       return 0;
1431     }
1432   }
1433 }
1434 
1435 #ifndef PRODUCT
1436 int interval_cmp(Interval* const& l, Interval* const& r) {
1437   return l->from() - r->from();
1438 }
1439 
1440 bool find_interval(Interval* interval, IntervalArray* intervals) {
1441   bool found;
1442   int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1443 
1444   if (!found) {
1445     return false;
1446   }
1447 
1448   int from = interval->from();
1449 
1450   // The index we've found using binary search is pointing to an interval
1451   // that is defined in the same place as the interval we were looking for.
1452   // So now we have to look around that index and find exact interval.
1453   for (int i = idx; i >= 0; i--) {
1454     if (intervals->at(i) == interval) {
1455       return true;
1456     }
1457     if (intervals->at(i)->from() != from) {
1458       break;
1459     }
1460   }
1461 
1462   for (int i = idx + 1; i < intervals->length(); i++) {
1463     if (intervals->at(i) == interval) {
1464       return true;
1465     }
1466     if (intervals->at(i)->from() != from) {
1467       break;
1468     }
1469   }
1470 
1471   return false;
1472 }
1473 
1474 bool LinearScan::is_sorted(IntervalArray* intervals) {
1475   int from = -1;
1476   int null_count = 0;
1477 
1478   for (int i = 0; i < intervals->length(); i++) {
1479     Interval* it = intervals->at(i);
1480     if (it != NULL) {
1481       assert(from <= it->from(), "Intervals are unordered");
1482       from = it->from();
1483     } else {
1484       null_count++;
1485     }
1486   }
1487 
1488   assert(null_count == 0, "Sorted intervals should not contain nulls");
1489 
1490   null_count = 0;
1491 
1492   for (int i = 0; i < interval_count(); i++) {
1493     Interval* interval = interval_at(i);
1494     if (interval != NULL) {
1495       assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1496     } else {
1497       null_count++;
1498     }
1499   }
1500 
1501   assert(interval_count() - null_count == intervals->length(),
1502       "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1503 
1504   return true;
1505 }
1506 #endif
1507 
1508 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1509   if (*prev != NULL) {
1510     (*prev)->set_next(interval);
1511   } else {
1512     *first = interval;
1513   }
1514   *prev = interval;
1515 }
1516 
1517 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1518   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1519 
1520   *list1 = *list2 = Interval::end();
1521 
1522   Interval* list1_prev = NULL;
1523   Interval* list2_prev = NULL;
1524   Interval* v;
1525 
1526   const int n = _sorted_intervals->length();
1527   for (int i = 0; i < n; i++) {
1528     v = _sorted_intervals->at(i);
1529     if (v == NULL) continue;
1530 
1531     if (is_list1(v)) {
1532       add_to_list(list1, &list1_prev, v);
1533     } else if (is_list2 == NULL || is_list2(v)) {
1534       add_to_list(list2, &list2_prev, v);
1535     }
1536   }
1537 
1538   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1539   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1540 
1541   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1542   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1543 }
1544 
1545 
1546 void LinearScan::sort_intervals_before_allocation() {
1547   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1548 
1549   if (_needs_full_resort) {
1550     // There is no known reason why this should occur but just in case...
1551     assert(false, "should never occur");
1552     // Re-sort existing interval list because an Interval::from() has changed
1553     _sorted_intervals->sort(interval_cmp);
1554     _needs_full_resort = false;
1555   }
1556 
1557   IntervalList* unsorted_list = &_intervals;
1558   int unsorted_len = unsorted_list->length();
1559   int sorted_len = 0;
1560   int unsorted_idx;
1561   int sorted_idx = 0;
1562   int sorted_from_max = -1;
1563 
1564   // calc number of items for sorted list (sorted list must not contain NULL values)
1565   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1566     if (unsorted_list->at(unsorted_idx) != NULL) {
1567       sorted_len++;
1568     }
1569   }
1570   IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1571 
1572   // special sorting algorithm: the original interval-list is almost sorted,
1573   // only some intervals are swapped. So this is much faster than a complete QuickSort
1574   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1575     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1576 
1577     if (cur_interval != NULL) {
1578       int cur_from = cur_interval->from();
1579 
1580       if (sorted_from_max <= cur_from) {
1581         sorted_list->at_put(sorted_idx++, cur_interval);
1582         sorted_from_max = cur_interval->from();
1583       } else {
1584         // the asumption that the intervals are already sorted failed,
1585         // so this interval must be sorted in manually
1586         int j;
1587         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1588           sorted_list->at_put(j + 1, sorted_list->at(j));
1589         }
1590         sorted_list->at_put(j + 1, cur_interval);
1591         sorted_idx++;
1592       }
1593     }
1594   }
1595   _sorted_intervals = sorted_list;
1596   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1597 }
1598 
1599 void LinearScan::sort_intervals_after_allocation() {
1600   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1601 
1602   if (_needs_full_resort) {
1603     // Re-sort existing interval list because an Interval::from() has changed
1604     _sorted_intervals->sort(interval_cmp);
1605     _needs_full_resort = false;
1606   }
1607 
1608   IntervalArray* old_list = _sorted_intervals;
1609   IntervalList* new_list = _new_intervals_from_allocation;
1610   int old_len = old_list->length();
1611   int new_len = new_list->length();
1612 
1613   if (new_len == 0) {
1614     // no intervals have been added during allocation, so sorted list is already up to date
1615     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1616     return;
1617   }
1618 
1619   // conventional sort-algorithm for new intervals
1620   new_list->sort(interval_cmp);
1621 
1622   // merge old and new list (both already sorted) into one combined list
1623   int combined_list_len = old_len + new_len;
1624   IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1625   int old_idx = 0;
1626   int new_idx = 0;
1627 
1628   while (old_idx + new_idx < old_len + new_len) {
1629     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1630       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1631       old_idx++;
1632     } else {
1633       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1634       new_idx++;
1635     }
1636   }
1637 
1638   _sorted_intervals = combined_list;
1639   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1640 }
1641 
1642 
1643 void LinearScan::allocate_registers() {
1644   TIME_LINEAR_SCAN(timer_allocate_registers);
1645 
1646   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1647   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1648 
1649   // allocate cpu registers
1650   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1651                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1652 
1653   // allocate fpu registers
1654   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1655                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1656 
1657   // the fpu interval allocation cannot be moved down below with the fpu section as
1658   // the cpu_lsw.walk() changes interval positions.
1659 
1660   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1661   cpu_lsw.walk();
1662   cpu_lsw.finish_allocation();
1663 
1664   if (has_fpu_registers()) {
1665     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1666     fpu_lsw.walk();
1667     fpu_lsw.finish_allocation();
1668   }
1669 }
1670 
1671 
1672 // ********** Phase 6: resolve data flow
1673 // (insert moves at edges between blocks if intervals have been split)
1674 
1675 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1676 // instead of returning NULL
1677 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1678   Interval* result = interval->split_child_at_op_id(op_id, mode);
1679   if (result != NULL) {
1680     return result;
1681   }
1682 
1683   assert(false, "must find an interval, but do a clean bailout in product mode");
1684   result = new Interval(LIR_OprDesc::vreg_base);
1685   result->assign_reg(0);
1686   result->set_type(T_INT);
1687   BAILOUT_("LinearScan: interval is NULL", result);
1688 }
1689 
1690 
1691 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1692   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1693   assert(interval_at(reg_num) != NULL, "no interval found");
1694 
1695   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1696 }
1697 
1698 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1699   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1700   assert(interval_at(reg_num) != NULL, "no interval found");
1701 
1702   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1703 }
1704 
1705 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1706   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1707   assert(interval_at(reg_num) != NULL, "no interval found");
1708 
1709   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1710 }
1711 
1712 
1713 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1714   DEBUG_ONLY(move_resolver.check_empty());
1715 
1716   const int num_regs = num_virtual_regs();
1717   const int size = live_set_size();
1718   const ResourceBitMap live_at_edge = to_block->live_in();
1719 
1720   // visit all registers where the live_at_edge bit is set
1721   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1722     assert(r < num_regs, "live information set for not exisiting interval");
1723     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1724 
1725     Interval* from_interval = interval_at_block_end(from_block, r);
1726     Interval* to_interval = interval_at_block_begin(to_block, r);
1727 
1728     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1729       // need to insert move instruction
1730       move_resolver.add_mapping(from_interval, to_interval);
1731     }
1732   }
1733 }
1734 
1735 
1736 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1737   if (from_block->number_of_sux() <= 1) {
1738     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1739 
1740     LIR_OpList* instructions = from_block->lir()->instructions_list();
1741     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1742     if (branch != NULL) {
1743       // insert moves before branch
1744       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1745       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1746     } else {
1747       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1748     }
1749 
1750   } else {
1751     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1752 #ifdef ASSERT
1753     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1754 
1755     // because the number of predecessor edges matches the number of
1756     // successor edges, blocks which are reached by switch statements
1757     // may have be more than one predecessor but it will be guaranteed
1758     // that all predecessors will be the same.
1759     for (int i = 0; i < to_block->number_of_preds(); i++) {
1760       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1761     }
1762 #endif
1763 
1764     move_resolver.set_insert_position(to_block->lir(), 0);
1765   }
1766 }
1767 
1768 
1769 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1770 void LinearScan::resolve_data_flow() {
1771   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1772 
1773   int num_blocks = block_count();
1774   MoveResolver move_resolver(this);
1775   ResourceBitMap block_completed(num_blocks);
1776   ResourceBitMap already_resolved(num_blocks);
1777 
1778   int i;
1779   for (i = 0; i < num_blocks; i++) {
1780     BlockBegin* block = block_at(i);
1781 
1782     // check if block has only one predecessor and only one successor
1783     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1784       LIR_OpList* instructions = block->lir()->instructions_list();
1785       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1786       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1787       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1788 
1789       // check if block is empty (only label and branch)
1790       if (instructions->length() == 2) {
1791         BlockBegin* pred = block->pred_at(0);
1792         BlockBegin* sux = block->sux_at(0);
1793 
1794         // prevent optimization of two consecutive blocks
1795         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1796           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1797           block_completed.set_bit(block->linear_scan_number());
1798 
1799           // directly resolve between pred and sux (without looking at the empty block between)
1800           resolve_collect_mappings(pred, sux, move_resolver);
1801           if (move_resolver.has_mappings()) {
1802             move_resolver.set_insert_position(block->lir(), 0);
1803             move_resolver.resolve_and_append_moves();
1804           }
1805         }
1806       }
1807     }
1808   }
1809 
1810 
1811   for (i = 0; i < num_blocks; i++) {
1812     if (!block_completed.at(i)) {
1813       BlockBegin* from_block = block_at(i);
1814       already_resolved.set_from(block_completed);
1815 
1816       int num_sux = from_block->number_of_sux();
1817       for (int s = 0; s < num_sux; s++) {
1818         BlockBegin* to_block = from_block->sux_at(s);
1819 
1820         // check for duplicate edges between the same blocks (can happen with switch blocks)
1821         if (!already_resolved.at(to_block->linear_scan_number())) {
1822           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1823           already_resolved.set_bit(to_block->linear_scan_number());
1824 
1825           // collect all intervals that have been split between from_block and to_block
1826           resolve_collect_mappings(from_block, to_block, move_resolver);
1827           if (move_resolver.has_mappings()) {
1828             resolve_find_insert_pos(from_block, to_block, move_resolver);
1829             move_resolver.resolve_and_append_moves();
1830           }
1831         }
1832       }
1833     }
1834   }
1835 }
1836 
1837 
1838 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1839   if (interval_at(reg_num) == NULL) {
1840     // if a phi function is never used, no interval is created -> ignore this
1841     return;
1842   }
1843 
1844   Interval* interval = interval_at_block_begin(block, reg_num);
1845   int reg = interval->assigned_reg();
1846   int regHi = interval->assigned_regHi();
1847 
1848   if ((reg < nof_regs && interval->always_in_memory()) ||
1849       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1850     // the interval is split to get a short range that is located on the stack
1851     // in the following two cases:
1852     // * the interval started in memory (e.g. method parameter), but is currently in a register
1853     //   this is an optimization for exception handling that reduces the number of moves that
1854     //   are necessary for resolving the states when an exception uses this exception handler
1855     // * the interval would be on the fpu stack at the begin of the exception handler
1856     //   this is not allowed because of the complicated fpu stack handling on Intel
1857 
1858     // range that will be spilled to memory
1859     int from_op_id = block->first_lir_instruction_id();
1860     int to_op_id = from_op_id + 1;  // short live range of length 1
1861     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1862            "no split allowed between exception entry and first instruction");
1863 
1864     if (interval->from() != from_op_id) {
1865       // the part before from_op_id is unchanged
1866       interval = interval->split(from_op_id);
1867       interval->assign_reg(reg, regHi);
1868       append_interval(interval);
1869     } else {
1870       _needs_full_resort = true;
1871     }
1872     assert(interval->from() == from_op_id, "must be true now");
1873 
1874     Interval* spilled_part = interval;
1875     if (interval->to() != to_op_id) {
1876       // the part after to_op_id is unchanged
1877       spilled_part = interval->split_from_start(to_op_id);
1878       append_interval(spilled_part);
1879       move_resolver.add_mapping(spilled_part, interval);
1880     }
1881     assign_spill_slot(spilled_part);
1882 
1883     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1884   }
1885 }
1886 
1887 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1888   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1889   DEBUG_ONLY(move_resolver.check_empty());
1890 
1891   // visit all registers where the live_in bit is set
1892   int size = live_set_size();
1893   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1894     resolve_exception_entry(block, r, move_resolver);
1895   }
1896 
1897   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1898   for_each_phi_fun(block, phi,
1899     resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1900   );
1901 
1902   if (move_resolver.has_mappings()) {
1903     // insert moves after first instruction
1904     move_resolver.set_insert_position(block->lir(), 0);
1905     move_resolver.resolve_and_append_moves();
1906   }
1907 }
1908 
1909 
1910 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1911   if (interval_at(reg_num) == NULL) {
1912     // if a phi function is never used, no interval is created -> ignore this
1913     return;
1914   }
1915 
1916   // the computation of to_interval is equal to resolve_collect_mappings,
1917   // but from_interval is more complicated because of phi functions
1918   BlockBegin* to_block = handler->entry_block();
1919   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1920 
1921   if (phi != NULL) {
1922     // phi function of the exception entry block
1923     // no moves are created for this phi function in the LIR_Generator, so the
1924     // interval at the throwing instruction must be searched using the operands
1925     // of the phi function
1926     Value from_value = phi->operand_at(handler->phi_operand());
1927 
1928     // with phi functions it can happen that the same from_value is used in
1929     // multiple mappings, so notify move-resolver that this is allowed
1930     move_resolver.set_multiple_reads_allowed();
1931 
1932     Constant* con = from_value->as_Constant();
1933     if (con != NULL && !con->is_pinned()) {
1934       // unpinned constants may have no register, so add mapping from constant to interval
1935       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1936     } else {
1937       // search split child at the throwing op_id
1938       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1939       move_resolver.add_mapping(from_interval, to_interval);
1940     }
1941 
1942   } else {
1943     // no phi function, so use reg_num also for from_interval
1944     // search split child at the throwing op_id
1945     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1946     if (from_interval != to_interval) {
1947       // optimization to reduce number of moves: when to_interval is on stack and
1948       // the stack slot is known to be always correct, then no move is necessary
1949       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1950         move_resolver.add_mapping(from_interval, to_interval);
1951       }
1952     }
1953   }
1954 }
1955 
1956 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1957   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1958 
1959   DEBUG_ONLY(move_resolver.check_empty());
1960   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1961   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1962   assert(handler->entry_code() == NULL, "code already present");
1963 
1964   // visit all registers where the live_in bit is set
1965   BlockBegin* block = handler->entry_block();
1966   int size = live_set_size();
1967   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1968     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1969   }
1970 
1971   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1972   for_each_phi_fun(block, phi,
1973     resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1974   );
1975 
1976   if (move_resolver.has_mappings()) {
1977     LIR_List* entry_code = new LIR_List(compilation());
1978     move_resolver.set_insert_position(entry_code, 0);
1979     move_resolver.resolve_and_append_moves();
1980 
1981     entry_code->jump(handler->entry_block());
1982     handler->set_entry_code(entry_code);
1983   }
1984 }
1985 
1986 
1987 void LinearScan::resolve_exception_handlers() {
1988   MoveResolver move_resolver(this);
1989   LIR_OpVisitState visitor;
1990   int num_blocks = block_count();
1991 
1992   int i;
1993   for (i = 0; i < num_blocks; i++) {
1994     BlockBegin* block = block_at(i);
1995     if (block->is_set(BlockBegin::exception_entry_flag)) {
1996       resolve_exception_entry(block, move_resolver);
1997     }
1998   }
1999 
2000   for (i = 0; i < num_blocks; i++) {
2001     BlockBegin* block = block_at(i);
2002     LIR_List* ops = block->lir();
2003     int num_ops = ops->length();
2004 
2005     // iterate all instructions of the block. skip the first because it is always a label
2006     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2007     for (int j = 1; j < num_ops; j++) {
2008       LIR_Op* op = ops->at(j);
2009       int op_id = op->id();
2010 
2011       if (op_id != -1 && has_info(op_id)) {
2012         // visit operation to collect all operands
2013         visitor.visit(op);
2014         assert(visitor.info_count() > 0, "should not visit otherwise");
2015 
2016         XHandlers* xhandlers = visitor.all_xhandler();
2017         int n = xhandlers->length();
2018         for (int k = 0; k < n; k++) {
2019           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2020         }
2021 
2022 #ifdef ASSERT
2023       } else {
2024         visitor.visit(op);
2025         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2026 #endif
2027       }
2028     }
2029   }
2030 }
2031 
2032 
2033 // ********** Phase 7: assign register numbers back to LIR
2034 // (includes computation of debug information and oop maps)
2035 
2036 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2037   VMReg reg = interval->cached_vm_reg();
2038   if (!reg->is_valid() ) {
2039     reg = vm_reg_for_operand(operand_for_interval(interval));
2040     interval->set_cached_vm_reg(reg);
2041   }
2042   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2043   return reg;
2044 }
2045 
2046 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2047   assert(opr->is_oop(), "currently only implemented for oop operands");
2048   return frame_map()->regname(opr);
2049 }
2050 
2051 
2052 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2053   LIR_Opr opr = interval->cached_opr();
2054   if (opr->is_illegal()) {
2055     opr = calc_operand_for_interval(interval);
2056     interval->set_cached_opr(opr);
2057   }
2058 
2059   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2060   return opr;
2061 }
2062 
2063 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2064   int assigned_reg = interval->assigned_reg();
2065   BasicType type = interval->type();
2066 
2067   if (assigned_reg >= nof_regs) {
2068     // stack slot
2069     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2070     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2071 
2072   } else {
2073     // register
2074     switch (type) {
2075       case T_OBJECT: {
2076         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2077         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2078         return LIR_OprFact::single_cpu_oop(assigned_reg);
2079       }
2080 
2081       case T_ADDRESS: {
2082         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2083         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2084         return LIR_OprFact::single_cpu_address(assigned_reg);
2085       }
2086 
2087       case T_METADATA: {
2088         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2089         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2090         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2091       }
2092 
2093 #ifdef __SOFTFP__
2094       case T_FLOAT:  // fall through
2095 #endif // __SOFTFP__
2096       case T_INT: {
2097         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2098         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2099         return LIR_OprFact::single_cpu(assigned_reg);
2100       }
2101 
2102 #ifdef __SOFTFP__
2103       case T_DOUBLE:  // fall through
2104 #endif // __SOFTFP__
2105       case T_LONG: {
2106         int assigned_regHi = interval->assigned_regHi();
2107         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2108         assert(num_physical_regs(T_LONG) == 1 ||
2109                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2110 
2111         assert(assigned_reg != assigned_regHi, "invalid allocation");
2112         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2113                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2114         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2115         if (requires_adjacent_regs(T_LONG)) {
2116           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2117         }
2118 
2119 #ifdef _LP64
2120         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2121 #else
2122 #if defined(SPARC) || defined(PPC32)
2123         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2124 #else
2125         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2126 #endif // SPARC
2127 #endif // LP64
2128       }
2129 
2130 #ifndef __SOFTFP__
2131       case T_FLOAT: {
2132 #ifdef X86
2133         if (UseSSE >= 1) {
2134           int last_xmm_reg = pd_last_xmm_reg;
2135 #ifdef _LP64
2136           if (UseAVX < 3) {
2137             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2138           }
2139 #endif
2140           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2141           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2142           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2143         }
2144 #endif
2145 
2146         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2147         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2148         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2149       }
2150 
2151       case T_DOUBLE: {
2152 #ifdef X86
2153         if (UseSSE >= 2) {
2154           int last_xmm_reg = pd_last_xmm_reg;
2155 #ifdef _LP64
2156           if (UseAVX < 3) {
2157             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2158           }
2159 #endif
2160           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2161           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2162           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2163         }
2164 #endif
2165 
2166 #ifdef SPARC
2167         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2168         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2169         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2170         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2171 #elif defined(ARM32)
2172         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2173         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2174         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2175         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2176 #else
2177         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2178         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2179         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2180 #endif
2181         return result;
2182       }
2183 #endif // __SOFTFP__
2184 
2185       default: {
2186         ShouldNotReachHere();
2187         return LIR_OprFact::illegalOpr;
2188       }
2189     }
2190   }
2191 }
2192 
2193 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2194   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2195   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2196 }
2197 
2198 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2199   assert(opr->is_virtual(), "should not call this otherwise");
2200 
2201   Interval* interval = interval_at(opr->vreg_number());
2202   assert(interval != NULL, "interval must exist");
2203 
2204   if (op_id != -1) {
2205 #ifdef ASSERT
2206     BlockBegin* block = block_of_op_with_id(op_id);
2207     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2208       // check if spill moves could have been appended at the end of this block, but
2209       // before the branch instruction. So the split child information for this branch would
2210       // be incorrect.
2211       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2212       if (branch != NULL) {
2213         if (block->live_out().at(opr->vreg_number())) {
2214           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2215           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2216         }
2217       }
2218     }
2219 #endif
2220 
2221     // operands are not changed when an interval is split during allocation,
2222     // so search the right interval here
2223     interval = split_child_at_op_id(interval, op_id, mode);
2224   }
2225 
2226   LIR_Opr res = operand_for_interval(interval);
2227 
2228 #ifdef X86
2229   // new semantic for is_last_use: not only set on definite end of interval,
2230   // but also before hole
2231   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2232   // last use information is completely correct
2233   // information is only needed for fpu stack allocation
2234   if (res->is_fpu_register()) {
2235     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2236       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2237       res = res->make_last_use();
2238     }
2239   }
2240 #endif
2241 
2242   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2243 
2244   return res;
2245 }
2246 
2247 
2248 #ifdef ASSERT
2249 // some methods used to check correctness of debug information
2250 
2251 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2252   if (values == NULL) {
2253     return;
2254   }
2255 
2256   for (int i = 0; i < values->length(); i++) {
2257     ScopeValue* value = values->at(i);
2258 
2259     if (value->is_location()) {
2260       Location location = ((LocationValue*)value)->location();
2261       assert(location.where() == Location::on_stack, "value is in register");
2262     }
2263   }
2264 }
2265 
2266 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2267   if (values == NULL) {
2268     return;
2269   }
2270 
2271   for (int i = 0; i < values->length(); i++) {
2272     MonitorValue* value = values->at(i);
2273 
2274     if (value->owner()->is_location()) {
2275       Location location = ((LocationValue*)value->owner())->location();
2276       assert(location.where() == Location::on_stack, "owner is in register");
2277     }
2278     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2279   }
2280 }
2281 
2282 void assert_equal(Location l1, Location l2) {
2283   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2284 }
2285 
2286 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2287   if (v1->is_location()) {
2288     assert(v2->is_location(), "");
2289     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2290   } else if (v1->is_constant_int()) {
2291     assert(v2->is_constant_int(), "");
2292     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2293   } else if (v1->is_constant_double()) {
2294     assert(v2->is_constant_double(), "");
2295     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2296   } else if (v1->is_constant_long()) {
2297     assert(v2->is_constant_long(), "");
2298     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2299   } else if (v1->is_constant_oop()) {
2300     assert(v2->is_constant_oop(), "");
2301     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2302   } else {
2303     ShouldNotReachHere();
2304   }
2305 }
2306 
2307 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2308   assert_equal(m1->owner(), m2->owner());
2309   assert_equal(m1->basic_lock(), m2->basic_lock());
2310 }
2311 
2312 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2313   assert(d1->scope() == d2->scope(), "not equal");
2314   assert(d1->bci() == d2->bci(), "not equal");
2315 
2316   if (d1->locals() != NULL) {
2317     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2318     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2319     for (int i = 0; i < d1->locals()->length(); i++) {
2320       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2321     }
2322   } else {
2323     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2324   }
2325 
2326   if (d1->expressions() != NULL) {
2327     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2328     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2329     for (int i = 0; i < d1->expressions()->length(); i++) {
2330       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2331     }
2332   } else {
2333     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2334   }
2335 
2336   if (d1->monitors() != NULL) {
2337     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2338     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2339     for (int i = 0; i < d1->monitors()->length(); i++) {
2340       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2341     }
2342   } else {
2343     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2344   }
2345 
2346   if (d1->caller() != NULL) {
2347     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2348     assert_equal(d1->caller(), d2->caller());
2349   } else {
2350     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2351   }
2352 }
2353 
2354 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2355   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2356     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2357     switch (code) {
2358       case Bytecodes::_ifnull    : // fall through
2359       case Bytecodes::_ifnonnull : // fall through
2360       case Bytecodes::_ifeq      : // fall through
2361       case Bytecodes::_ifne      : // fall through
2362       case Bytecodes::_iflt      : // fall through
2363       case Bytecodes::_ifge      : // fall through
2364       case Bytecodes::_ifgt      : // fall through
2365       case Bytecodes::_ifle      : // fall through
2366       case Bytecodes::_if_icmpeq : // fall through
2367       case Bytecodes::_if_icmpne : // fall through
2368       case Bytecodes::_if_icmplt : // fall through
2369       case Bytecodes::_if_icmpge : // fall through
2370       case Bytecodes::_if_icmpgt : // fall through
2371       case Bytecodes::_if_icmple : // fall through
2372       case Bytecodes::_if_acmpeq : // fall through
2373       case Bytecodes::_if_acmpne :
2374         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2375         break;
2376     }
2377   }
2378 }
2379 
2380 #endif // ASSERT
2381 
2382 
2383 IntervalWalker* LinearScan::init_compute_oop_maps() {
2384   // setup lists of potential oops for walking
2385   Interval* oop_intervals;
2386   Interval* non_oop_intervals;
2387 
2388   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2389 
2390   // intervals that have no oops inside need not to be processed
2391   // to ensure a walking until the last instruction id, add a dummy interval
2392   // with a high operation id
2393   non_oop_intervals = new Interval(any_reg);
2394   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2395 
2396   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2397 }
2398 
2399 
2400 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2401   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2402 
2403   // walk before the current operation -> intervals that start at
2404   // the operation (= output operands of the operation) are not
2405   // included in the oop map
2406   iw->walk_before(op->id());
2407 
2408   int frame_size = frame_map()->framesize();
2409   int arg_count = frame_map()->oop_map_arg_count();
2410   OopMap* map = new OopMap(frame_size, arg_count);
2411 
2412   // Iterate through active intervals
2413   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2414     int assigned_reg = interval->assigned_reg();
2415 
2416     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2417     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2418     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2419 
2420     // Check if this range covers the instruction. Intervals that
2421     // start or end at the current operation are not included in the
2422     // oop map, except in the case of patching moves.  For patching
2423     // moves, any intervals which end at this instruction are included
2424     // in the oop map since we may safepoint while doing the patch
2425     // before we've consumed the inputs.
2426     if (op->is_patching() || op->id() < interval->current_to()) {
2427 
2428       // caller-save registers must not be included into oop-maps at calls
2429       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2430 
2431       VMReg name = vm_reg_for_interval(interval);
2432       set_oop(map, name);
2433 
2434       // Spill optimization: when the stack value is guaranteed to be always correct,
2435       // then it must be added to the oop map even if the interval is currently in a register
2436       if (interval->always_in_memory() &&
2437           op->id() > interval->spill_definition_pos() &&
2438           interval->assigned_reg() != interval->canonical_spill_slot()) {
2439         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2440         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2441         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2442 
2443         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2444       }
2445     }
2446   }
2447 
2448   // add oops from lock stack
2449   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2450   int locks_count = info->stack()->total_locks_size();
2451   for (int i = 0; i < locks_count; i++) {
2452     set_oop(map, frame_map()->monitor_object_regname(i));
2453   }
2454 
2455   return map;
2456 }
2457 
2458 
2459 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2460   assert(visitor.info_count() > 0, "no oop map needed");
2461 
2462   // compute oop_map only for first CodeEmitInfo
2463   // because it is (in most cases) equal for all other infos of the same operation
2464   CodeEmitInfo* first_info = visitor.info_at(0);
2465   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2466 
2467   for (int i = 0; i < visitor.info_count(); i++) {
2468     CodeEmitInfo* info = visitor.info_at(i);
2469     OopMap* oop_map = first_oop_map;
2470 
2471     // compute worst case interpreter size in case of a deoptimization
2472     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2473 
2474     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2475       // this info has a different number of locks then the precomputed oop map
2476       // (possible for lock and unlock instructions) -> compute oop map with
2477       // correct lock information
2478       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2479     }
2480 
2481     if (info->_oop_map == NULL) {
2482       info->_oop_map = oop_map;
2483     } else {
2484       // a CodeEmitInfo can not be shared between different LIR-instructions
2485       // because interval splitting can occur anywhere between two instructions
2486       // and so the oop maps must be different
2487       // -> check if the already set oop_map is exactly the one calculated for this operation
2488       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2489     }
2490   }
2491 }
2492 
2493 
2494 // frequently used constants
2495 // Allocate them with new so they are never destroyed (otherwise, a
2496 // forced exit could destroy these objects while they are still in
2497 // use).
2498 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2499 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2500 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0);
2501 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2502 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2503 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2504 
2505 void LinearScan::init_compute_debug_info() {
2506   // cache for frequently used scope values
2507   // (cpu registers and stack slots)
2508   int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2509   _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2510 }
2511 
2512 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2513   Location loc;
2514   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2515     bailout("too large frame");
2516   }
2517   ScopeValue* object_scope_value = new LocationValue(loc);
2518 
2519   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2520     bailout("too large frame");
2521   }
2522   return new MonitorValue(object_scope_value, loc);
2523 }
2524 
2525 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2526   Location loc;
2527   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2528     bailout("too large frame");
2529   }
2530   return new LocationValue(loc);
2531 }
2532 
2533 
2534 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2535   assert(opr->is_constant(), "should not be called otherwise");
2536 
2537   LIR_Const* c = opr->as_constant_ptr();
2538   BasicType t = c->type();
2539   switch (t) {
2540     case T_OBJECT: {
2541       jobject value = c->as_jobject();
2542       if (value == NULL) {
2543         scope_values->append(_oop_null_scope_value);
2544       } else {
2545         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2546       }
2547       return 1;
2548     }
2549 
2550     case T_INT: // fall through
2551     case T_FLOAT: {
2552       int value = c->as_jint_bits();
2553       switch (value) {
2554         case -1: scope_values->append(_int_m1_scope_value); break;
2555         case 0:  scope_values->append(_int_0_scope_value); break;
2556         case 1:  scope_values->append(_int_1_scope_value); break;
2557         case 2:  scope_values->append(_int_2_scope_value); break;
2558         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2559       }
2560       return 1;
2561     }
2562 
2563     case T_LONG: // fall through
2564     case T_DOUBLE: {
2565 #ifdef _LP64
2566       scope_values->append(_int_0_scope_value);
2567       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2568 #else
2569       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2570         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2571         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2572       } else {
2573         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2574         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2575       }
2576 #endif
2577       return 2;
2578     }
2579 
2580     case T_ADDRESS: {
2581 #ifdef _LP64
2582       scope_values->append(new ConstantLongValue(c->as_jint()));
2583 #else
2584       scope_values->append(new ConstantIntValue(c->as_jint()));
2585 #endif
2586       return 1;
2587     }
2588 
2589     default:
2590       ShouldNotReachHere();
2591       return -1;
2592   }
2593 }
2594 
2595 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2596   if (opr->is_single_stack()) {
2597     int stack_idx = opr->single_stack_ix();
2598     bool is_oop = opr->is_oop_register();
2599     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2600 
2601     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2602     if (sv == NULL) {
2603       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2604       sv = location_for_name(stack_idx, loc_type);
2605       _scope_value_cache.at_put(cache_idx, sv);
2606     }
2607 
2608     // check if cached value is correct
2609     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2610 
2611     scope_values->append(sv);
2612     return 1;
2613 
2614   } else if (opr->is_single_cpu()) {
2615     bool is_oop = opr->is_oop_register();
2616     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2617     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2618 
2619     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2620     if (sv == NULL) {
2621       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2622       VMReg rname = frame_map()->regname(opr);
2623       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2624       _scope_value_cache.at_put(cache_idx, sv);
2625     }
2626 
2627     // check if cached value is correct
2628     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2629 
2630     scope_values->append(sv);
2631     return 1;
2632 
2633 #ifdef X86
2634   } else if (opr->is_single_xmm()) {
2635     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2636     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2637 
2638     scope_values->append(sv);
2639     return 1;
2640 #endif
2641 
2642   } else if (opr->is_single_fpu()) {
2643 #ifdef X86
2644     // the exact location of fpu stack values is only known
2645     // during fpu stack allocation, so the stack allocator object
2646     // must be present
2647     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2648     assert(_fpu_stack_allocator != NULL, "must be present");
2649     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2650 #endif
2651 
2652     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2653     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2654 #ifndef __SOFTFP__
2655 #ifndef VM_LITTLE_ENDIAN
2656     // On S390 a (single precision) float value occupies only the high
2657     // word of the full double register. So when the double register is
2658     // stored to memory (e.g. by the RegisterSaver), then the float value
2659     // is found at offset 0. I.e. the code below is not needed on S390.
2660 #ifndef S390
2661     if (! float_saved_as_double) {
2662       // On big endian system, we may have an issue if float registers use only
2663       // the low half of the (same) double registers.
2664       // Both the float and the double could have the same regnr but would correspond
2665       // to two different addresses once saved.
2666 
2667       // get next safely (no assertion checks)
2668       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2669       if (next->is_reg() &&
2670           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2671         // the back-end does use the same numbering for the double and the float
2672         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2673       }
2674     }
2675 #endif // !S390
2676 #endif
2677 #endif
2678     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2679 
2680     scope_values->append(sv);
2681     return 1;
2682 
2683   } else {
2684     // double-size operands
2685 
2686     ScopeValue* first;
2687     ScopeValue* second;
2688 
2689     if (opr->is_double_stack()) {
2690 #ifdef _LP64
2691       Location loc1;
2692       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2693       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2694         bailout("too large frame");
2695       }
2696       // Does this reverse on x86 vs. sparc?
2697       first =  new LocationValue(loc1);
2698       second = _int_0_scope_value;
2699 #else
2700       Location loc1, loc2;
2701       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2702         bailout("too large frame");
2703       }
2704       first =  new LocationValue(loc1);
2705       second = new LocationValue(loc2);
2706 #endif // _LP64
2707 
2708     } else if (opr->is_double_cpu()) {
2709 #ifdef _LP64
2710       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2711       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2712       second = _int_0_scope_value;
2713 #else
2714       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2715       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2716 
2717       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2718         // lo/hi and swapped relative to first and second, so swap them
2719         VMReg tmp = rname_first;
2720         rname_first = rname_second;
2721         rname_second = tmp;
2722       }
2723 
2724       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2725       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2726 #endif //_LP64
2727 
2728 
2729 #ifdef X86
2730     } else if (opr->is_double_xmm()) {
2731       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2732       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2733 #  ifdef _LP64
2734       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2735       second = _int_0_scope_value;
2736 #  else
2737       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2738       // %%% This is probably a waste but we'll keep things as they were for now
2739       if (true) {
2740         VMReg rname_second = rname_first->next();
2741         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2742       }
2743 #  endif
2744 #endif
2745 
2746     } else if (opr->is_double_fpu()) {
2747       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2748       // the double as float registers in the native ordering. On X86,
2749       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2750       // the low-order word of the double and fpu_regnrLo + 1 is the
2751       // name for the other half.  *first and *second must represent the
2752       // least and most significant words, respectively.
2753 
2754 #ifdef X86
2755       // the exact location of fpu stack values is only known
2756       // during fpu stack allocation, so the stack allocator object
2757       // must be present
2758       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2759       assert(_fpu_stack_allocator != NULL, "must be present");
2760       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2761 
2762       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2763 #endif
2764 #ifdef SPARC
2765       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2766 #endif
2767 #ifdef ARM32
2768       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2769 #endif
2770 #ifdef PPC32
2771       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2772 #endif
2773 
2774 #ifdef VM_LITTLE_ENDIAN
2775       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2776 #else
2777       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2778 #endif
2779 
2780 #ifdef _LP64
2781       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2782       second = _int_0_scope_value;
2783 #else
2784       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2785       // %%% This is probably a waste but we'll keep things as they were for now
2786       if (true) {
2787         VMReg rname_second = rname_first->next();
2788         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2789       }
2790 #endif
2791 
2792     } else {
2793       ShouldNotReachHere();
2794       first = NULL;
2795       second = NULL;
2796     }
2797 
2798     assert(first != NULL && second != NULL, "must be set");
2799     // The convention the interpreter uses is that the second local
2800     // holds the first raw word of the native double representation.
2801     // This is actually reasonable, since locals and stack arrays
2802     // grow downwards in all implementations.
2803     // (If, on some machine, the interpreter's Java locals or stack
2804     // were to grow upwards, the embedded doubles would be word-swapped.)
2805     scope_values->append(second);
2806     scope_values->append(first);
2807     return 2;
2808   }
2809 }
2810 
2811 
2812 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2813   if (value != NULL) {
2814     LIR_Opr opr = value->operand();
2815     Constant* con = value->as_Constant();
2816 
2817     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2818     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2819 
2820     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2821       // Unpinned constants may have a virtual operand for a part of the lifetime
2822       // or may be illegal when it was optimized away,
2823       // so always use a constant operand
2824       opr = LIR_OprFact::value_type(con->type());
2825     }
2826     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2827 
2828     if (opr->is_virtual()) {
2829       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2830 
2831       BlockBegin* block = block_of_op_with_id(op_id);
2832       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2833         // generating debug information for the last instruction of a block.
2834         // if this instruction is a branch, spill moves are inserted before this branch
2835         // and so the wrong operand would be returned (spill moves at block boundaries are not
2836         // considered in the live ranges of intervals)
2837         // Solution: use the first op_id of the branch target block instead.
2838         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2839           if (block->live_out().at(opr->vreg_number())) {
2840             op_id = block->sux_at(0)->first_lir_instruction_id();
2841             mode = LIR_OpVisitState::outputMode;
2842           }
2843         }
2844       }
2845 
2846       // Get current location of operand
2847       // The operand must be live because debug information is considered when building the intervals
2848       // if the interval is not live, color_lir_opr will cause an assertion failure
2849       opr = color_lir_opr(opr, op_id, mode);
2850       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2851 
2852       // Append to ScopeValue array
2853       return append_scope_value_for_operand(opr, scope_values);
2854 
2855     } else {
2856       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2857       assert(opr->is_constant(), "operand must be constant");
2858 
2859       return append_scope_value_for_constant(opr, scope_values);
2860     }
2861   } else {
2862     // append a dummy value because real value not needed
2863     scope_values->append(_illegal_value);
2864     return 1;
2865   }
2866 }
2867 
2868 
2869 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2870   IRScopeDebugInfo* caller_debug_info = NULL;
2871 
2872   ValueStack* caller_state = cur_state->caller_state();
2873   if (caller_state != NULL) {
2874     // process recursively to compute outermost scope first
2875     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2876   }
2877 
2878   // initialize these to null.
2879   // If we don't need deopt info or there are no locals, expressions or monitors,
2880   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2881   GrowableArray<ScopeValue*>*   locals      = NULL;
2882   GrowableArray<ScopeValue*>*   expressions = NULL;
2883   GrowableArray<MonitorValue*>* monitors    = NULL;
2884 
2885   // describe local variable values
2886   int nof_locals = cur_state->locals_size();
2887   if (nof_locals > 0) {
2888     locals = new GrowableArray<ScopeValue*>(nof_locals);
2889 
2890     int pos = 0;
2891     while (pos < nof_locals) {
2892       assert(pos < cur_state->locals_size(), "why not?");
2893 
2894       Value local = cur_state->local_at(pos);
2895       pos += append_scope_value(op_id, local, locals);
2896 
2897       assert(locals->length() == pos, "must match");
2898     }
2899     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2900     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2901   } else if (cur_scope->method()->max_locals() > 0) {
2902     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2903     nof_locals = cur_scope->method()->max_locals();
2904     locals = new GrowableArray<ScopeValue*>(nof_locals);
2905     for(int i = 0; i < nof_locals; i++) {
2906       locals->append(_illegal_value);
2907     }
2908   }
2909 
2910   // describe expression stack
2911   int nof_stack = cur_state->stack_size();
2912   if (nof_stack > 0) {
2913     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2914 
2915     int pos = 0;
2916     while (pos < nof_stack) {
2917       Value expression = cur_state->stack_at_inc(pos);
2918       append_scope_value(op_id, expression, expressions);
2919 
2920       assert(expressions->length() == pos, "must match");
2921     }
2922     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2923   }
2924 
2925   // describe monitors
2926   int nof_locks = cur_state->locks_size();
2927   if (nof_locks > 0) {
2928     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2929     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2930     for (int i = 0; i < nof_locks; i++) {
2931       monitors->append(location_for_monitor_index(lock_offset + i));
2932     }
2933   }
2934 
2935   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2936 }
2937 
2938 
2939 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2940   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2941 
2942   IRScope* innermost_scope = info->scope();
2943   ValueStack* innermost_state = info->stack();
2944 
2945   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2946 
2947   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2948 
2949   if (info->_scope_debug_info == NULL) {
2950     // compute debug information
2951     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2952   } else {
2953     // debug information already set. Check that it is correct from the current point of view
2954     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2955   }
2956 }
2957 
2958 
2959 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2960   LIR_OpVisitState visitor;
2961   int num_inst = instructions->length();
2962   bool has_dead = false;
2963 
2964   for (int j = 0; j < num_inst; j++) {
2965     LIR_Op* op = instructions->at(j);
2966     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2967       has_dead = true;
2968       continue;
2969     }
2970     int op_id = op->id();
2971 
2972     // visit instruction to get list of operands
2973     visitor.visit(op);
2974 
2975     // iterate all modes of the visitor and process all virtual operands
2976     for_each_visitor_mode(mode) {
2977       int n = visitor.opr_count(mode);
2978       for (int k = 0; k < n; k++) {
2979         LIR_Opr opr = visitor.opr_at(mode, k);
2980         if (opr->is_virtual_register()) {
2981           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2982         }
2983       }
2984     }
2985 
2986     if (visitor.info_count() > 0) {
2987       // exception handling
2988       if (compilation()->has_exception_handlers()) {
2989         XHandlers* xhandlers = visitor.all_xhandler();
2990         int n = xhandlers->length();
2991         for (int k = 0; k < n; k++) {
2992           XHandler* handler = xhandlers->handler_at(k);
2993           if (handler->entry_code() != NULL) {
2994             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
2995           }
2996         }
2997       } else {
2998         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2999       }
3000 
3001       // compute oop map
3002       assert(iw != NULL, "needed for compute_oop_map");
3003       compute_oop_map(iw, visitor, op);
3004 
3005       // compute debug information
3006       if (!use_fpu_stack_allocation()) {
3007         // compute debug information if fpu stack allocation is not needed.
3008         // when fpu stack allocation is needed, the debug information can not
3009         // be computed here because the exact location of fpu operands is not known
3010         // -> debug information is created inside the fpu stack allocator
3011         int n = visitor.info_count();
3012         for (int k = 0; k < n; k++) {
3013           compute_debug_info(visitor.info_at(k), op_id);
3014         }
3015       }
3016     }
3017 
3018 #ifdef ASSERT
3019     // make sure we haven't made the op invalid.
3020     op->verify();
3021 #endif
3022 
3023     // remove useless moves
3024     if (op->code() == lir_move) {
3025       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3026       LIR_Op1* move = (LIR_Op1*)op;
3027       LIR_Opr src = move->in_opr();
3028       LIR_Opr dst = move->result_opr();
3029       if (dst == src ||
3030           !dst->is_pointer() && !src->is_pointer() &&
3031           src->is_same_register(dst)) {
3032         instructions->at_put(j, NULL);
3033         has_dead = true;
3034       }
3035     }
3036   }
3037 
3038   if (has_dead) {
3039     // iterate all instructions of the block and remove all null-values.
3040     int insert_point = 0;
3041     for (int j = 0; j < num_inst; j++) {
3042       LIR_Op* op = instructions->at(j);
3043       if (op != NULL) {
3044         if (insert_point != j) {
3045           instructions->at_put(insert_point, op);
3046         }
3047         insert_point++;
3048       }
3049     }
3050     instructions->trunc_to(insert_point);
3051   }
3052 }
3053 
3054 void LinearScan::assign_reg_num() {
3055   TIME_LINEAR_SCAN(timer_assign_reg_num);
3056 
3057   init_compute_debug_info();
3058   IntervalWalker* iw = init_compute_oop_maps();
3059 
3060   int num_blocks = block_count();
3061   for (int i = 0; i < num_blocks; i++) {
3062     BlockBegin* block = block_at(i);
3063     assign_reg_num(block->lir()->instructions_list(), iw);
3064   }
3065 }
3066 
3067 
3068 void LinearScan::do_linear_scan() {
3069   NOT_PRODUCT(_total_timer.begin_method());
3070 
3071   number_instructions();
3072 
3073   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3074 
3075   compute_local_live_sets();
3076   compute_global_live_sets();
3077   CHECK_BAILOUT();
3078 
3079   build_intervals();
3080   CHECK_BAILOUT();
3081   sort_intervals_before_allocation();
3082 
3083   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3084   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3085 
3086   allocate_registers();
3087   CHECK_BAILOUT();
3088 
3089   resolve_data_flow();
3090   if (compilation()->has_exception_handlers()) {
3091     resolve_exception_handlers();
3092   }
3093   // fill in number of spill slots into frame_map
3094   propagate_spill_slots();
3095   CHECK_BAILOUT();
3096 
3097   NOT_PRODUCT(print_intervals("After Register Allocation"));
3098   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3099 
3100   sort_intervals_after_allocation();
3101 
3102   DEBUG_ONLY(verify());
3103 
3104   eliminate_spill_moves();
3105   assign_reg_num();
3106   CHECK_BAILOUT();
3107 
3108   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3109   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3110 
3111   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3112 
3113     if (use_fpu_stack_allocation()) {
3114       allocate_fpu_stack(); // Only has effect on Intel
3115       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3116     }
3117   }
3118 
3119   { TIME_LINEAR_SCAN(timer_optimize_lir);
3120 
3121     EdgeMoveOptimizer::optimize(ir()->code());
3122     ControlFlowOptimizer::optimize(ir()->code());
3123     // check that cfg is still correct after optimizations
3124     ir()->verify();
3125   }
3126 
3127   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3128   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3129   NOT_PRODUCT(_total_timer.end_method(this));
3130 }
3131 
3132 
3133 // ********** Printing functions
3134 
3135 #ifndef PRODUCT
3136 
3137 void LinearScan::print_timers(double total) {
3138   _total_timer.print(total);
3139 }
3140 
3141 void LinearScan::print_statistics() {
3142   _stat_before_alloc.print("before allocation");
3143   _stat_after_asign.print("after assignment of register");
3144   _stat_final.print("after optimization");
3145 }
3146 
3147 void LinearScan::print_bitmap(BitMap& b) {
3148   for (unsigned int i = 0; i < b.size(); i++) {
3149     if (b.at(i)) tty->print("%d ", i);
3150   }
3151   tty->cr();
3152 }
3153 
3154 void LinearScan::print_intervals(const char* label) {
3155   if (TraceLinearScanLevel >= 1) {
3156     int i;
3157     tty->cr();
3158     tty->print_cr("%s", label);
3159 
3160     for (i = 0; i < interval_count(); i++) {
3161       Interval* interval = interval_at(i);
3162       if (interval != NULL) {
3163         interval->print();
3164       }
3165     }
3166 
3167     tty->cr();
3168     tty->print_cr("--- Basic Blocks ---");
3169     for (i = 0; i < block_count(); i++) {
3170       BlockBegin* block = block_at(i);
3171       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3172     }
3173     tty->cr();
3174     tty->cr();
3175   }
3176 
3177   if (PrintCFGToFile) {
3178     CFGPrinter::print_intervals(&_intervals, label);
3179   }
3180 }
3181 
3182 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3183   if (TraceLinearScanLevel >= level) {
3184     tty->cr();
3185     tty->print_cr("%s", label);
3186     print_LIR(ir()->linear_scan_order());
3187     tty->cr();
3188   }
3189 
3190   if (level == 1 && PrintCFGToFile) {
3191     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3192   }
3193 }
3194 
3195 #endif //PRODUCT
3196 
3197 
3198 // ********** verification functions for allocation
3199 // (check that all intervals have a correct register and that no registers are overwritten)
3200 #ifdef ASSERT
3201 
3202 void LinearScan::verify() {
3203   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3204   verify_intervals();
3205 
3206   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3207   verify_no_oops_in_fixed_intervals();
3208 
3209   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3210   verify_constants();
3211 
3212   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3213   verify_registers();
3214 
3215   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3216 }
3217 
3218 void LinearScan::verify_intervals() {
3219   int len = interval_count();
3220   bool has_error = false;
3221 
3222   for (int i = 0; i < len; i++) {
3223     Interval* i1 = interval_at(i);
3224     if (i1 == NULL) continue;
3225 
3226     i1->check_split_children();
3227 
3228     if (i1->reg_num() != i) {
3229       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3230       has_error = true;
3231     }
3232 
3233     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3234       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3235       has_error = true;
3236     }
3237 
3238     if (i1->assigned_reg() == any_reg) {
3239       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3240       has_error = true;
3241     }
3242 
3243     if (i1->assigned_reg() == i1->assigned_regHi()) {
3244       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3245       has_error = true;
3246     }
3247 
3248     if (!is_processed_reg_num(i1->assigned_reg())) {
3249       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3250       has_error = true;
3251     }
3252 
3253     // special intervals that are created in MoveResolver
3254     // -> ignore them because the range information has no meaning there
3255     if (i1->from() == 1 && i1->to() == 2) continue;
3256 
3257     if (i1->first() == Range::end()) {
3258       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3259       has_error = true;
3260     }
3261 
3262     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3263       if (r->from() >= r->to()) {
3264         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3265         has_error = true;
3266       }
3267     }
3268 
3269     for (int j = i + 1; j < len; j++) {
3270       Interval* i2 = interval_at(j);
3271       if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3272 
3273       int r1 = i1->assigned_reg();
3274       int r1Hi = i1->assigned_regHi();
3275       int r2 = i2->assigned_reg();
3276       int r2Hi = i2->assigned_regHi();
3277       if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3278         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3279         i1->print(); tty->cr();
3280         i2->print(); tty->cr();
3281         has_error = true;
3282       }
3283     }
3284   }
3285 
3286   assert(has_error == false, "register allocation invalid");
3287 }
3288 
3289 
3290 void LinearScan::verify_no_oops_in_fixed_intervals() {
3291   Interval* fixed_intervals;
3292   Interval* other_intervals;
3293   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3294 
3295   // to ensure a walking until the last instruction id, add a dummy interval
3296   // with a high operation id
3297   other_intervals = new Interval(any_reg);
3298   other_intervals->add_range(max_jint - 2, max_jint - 1);
3299   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3300 
3301   LIR_OpVisitState visitor;
3302   for (int i = 0; i < block_count(); i++) {
3303     BlockBegin* block = block_at(i);
3304 
3305     LIR_OpList* instructions = block->lir()->instructions_list();
3306 
3307     for (int j = 0; j < instructions->length(); j++) {
3308       LIR_Op* op = instructions->at(j);
3309       int op_id = op->id();
3310 
3311       visitor.visit(op);
3312 
3313       if (visitor.info_count() > 0) {
3314         iw->walk_before(op->id());
3315         bool check_live = true;
3316         if (op->code() == lir_move) {
3317           LIR_Op1* move = (LIR_Op1*)op;
3318           check_live = (move->patch_code() == lir_patch_none);
3319         }
3320         LIR_OpBranch* branch = op->as_OpBranch();
3321         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3322           // Don't bother checking the stub in this case since the
3323           // exception stub will never return to normal control flow.
3324           check_live = false;
3325         }
3326 
3327         // Make sure none of the fixed registers is live across an
3328         // oopmap since we can't handle that correctly.
3329         if (check_live) {
3330           for (Interval* interval = iw->active_first(fixedKind);
3331                interval != Interval::end();
3332                interval = interval->next()) {
3333             if (interval->current_to() > op->id() + 1) {
3334               // This interval is live out of this op so make sure
3335               // that this interval represents some value that's
3336               // referenced by this op either as an input or output.
3337               bool ok = false;
3338               for_each_visitor_mode(mode) {
3339                 int n = visitor.opr_count(mode);
3340                 for (int k = 0; k < n; k++) {
3341                   LIR_Opr opr = visitor.opr_at(mode, k);
3342                   if (opr->is_fixed_cpu()) {
3343                     if (interval_at(reg_num(opr)) == interval) {
3344                       ok = true;
3345                       break;
3346                     }
3347                     int hi = reg_numHi(opr);
3348                     if (hi != -1 && interval_at(hi) == interval) {
3349                       ok = true;
3350                       break;
3351                     }
3352                   }
3353                 }
3354               }
3355               assert(ok, "fixed intervals should never be live across an oopmap point");
3356             }
3357           }
3358         }
3359       }
3360 
3361       // oop-maps at calls do not contain registers, so check is not needed
3362       if (!visitor.has_call()) {
3363 
3364         for_each_visitor_mode(mode) {
3365           int n = visitor.opr_count(mode);
3366           for (int k = 0; k < n; k++) {
3367             LIR_Opr opr = visitor.opr_at(mode, k);
3368 
3369             if (opr->is_fixed_cpu() && opr->is_oop()) {
3370               // operand is a non-virtual cpu register and contains an oop
3371               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3372 
3373               Interval* interval = interval_at(reg_num(opr));
3374               assert(interval != NULL, "no interval");
3375 
3376               if (mode == LIR_OpVisitState::inputMode) {
3377                 if (interval->to() >= op_id + 1) {
3378                   assert(interval->to() < op_id + 2 ||
3379                          interval->has_hole_between(op_id, op_id + 2),
3380                          "oop input operand live after instruction");
3381                 }
3382               } else if (mode == LIR_OpVisitState::outputMode) {
3383                 if (interval->from() <= op_id - 1) {
3384                   assert(interval->has_hole_between(op_id - 1, op_id),
3385                          "oop input operand live after instruction");
3386                 }
3387               }
3388             }
3389           }
3390         }
3391       }
3392     }
3393   }
3394 }
3395 
3396 
3397 void LinearScan::verify_constants() {
3398   int num_regs = num_virtual_regs();
3399   int size = live_set_size();
3400   int num_blocks = block_count();
3401 
3402   for (int i = 0; i < num_blocks; i++) {
3403     BlockBegin* block = block_at(i);
3404     ResourceBitMap live_at_edge = block->live_in();
3405 
3406     // visit all registers where the live_at_edge bit is set
3407     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3408       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3409 
3410       Value value = gen()->instruction_for_vreg(r);
3411 
3412       assert(value != NULL, "all intervals live across block boundaries must have Value");
3413       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3414       assert(value->operand()->vreg_number() == r, "register number must match");
3415       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3416     }
3417   }
3418 }
3419 
3420 
3421 class RegisterVerifier: public StackObj {
3422  private:
3423   LinearScan*   _allocator;
3424   BlockList     _work_list;      // all blocks that must be processed
3425   IntervalsList _saved_states;   // saved information of previous check
3426 
3427   // simplified access to methods of LinearScan
3428   Compilation*  compilation() const              { return _allocator->compilation(); }
3429   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3430   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3431 
3432   // currently, only registers are processed
3433   int           state_size()                     { return LinearScan::nof_regs; }
3434 
3435   // accessors
3436   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3437   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3438   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3439 
3440   // helper functions
3441   IntervalList* copy(IntervalList* input_state);
3442   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3443   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3444 
3445   void process_block(BlockBegin* block);
3446   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3447   void process_successor(BlockBegin* block, IntervalList* input_state);
3448   void process_operations(LIR_List* ops, IntervalList* input_state);
3449 
3450  public:
3451   RegisterVerifier(LinearScan* allocator)
3452     : _allocator(allocator)
3453     , _work_list(16)
3454     , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3455   { }
3456 
3457   void verify(BlockBegin* start);
3458 };
3459 
3460 
3461 // entry function from LinearScan that starts the verification
3462 void LinearScan::verify_registers() {
3463   RegisterVerifier verifier(this);
3464   verifier.verify(block_at(0));
3465 }
3466 
3467 
3468 void RegisterVerifier::verify(BlockBegin* start) {
3469   // setup input registers (method arguments) for first block
3470   int input_state_len = state_size();
3471   IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3472   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3473   for (int n = 0; n < args->length(); n++) {
3474     LIR_Opr opr = args->at(n);
3475     if (opr->is_register()) {
3476       Interval* interval = interval_at(reg_num(opr));
3477 
3478       if (interval->assigned_reg() < state_size()) {
3479         input_state->at_put(interval->assigned_reg(), interval);
3480       }
3481       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3482         input_state->at_put(interval->assigned_regHi(), interval);
3483       }
3484     }
3485   }
3486 
3487   set_state_for_block(start, input_state);
3488   add_to_work_list(start);
3489 
3490   // main loop for verification
3491   do {
3492     BlockBegin* block = _work_list.at(0);
3493     _work_list.remove_at(0);
3494 
3495     process_block(block);
3496   } while (!_work_list.is_empty());
3497 }
3498 
3499 void RegisterVerifier::process_block(BlockBegin* block) {
3500   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3501 
3502   // must copy state because it is modified
3503   IntervalList* input_state = copy(state_for_block(block));
3504 
3505   if (TraceLinearScanLevel >= 4) {
3506     tty->print_cr("Input-State of intervals:");
3507     tty->print("    ");
3508     for (int i = 0; i < state_size(); i++) {
3509       if (input_state->at(i) != NULL) {
3510         tty->print(" %4d", input_state->at(i)->reg_num());
3511       } else {
3512         tty->print("   __");
3513       }
3514     }
3515     tty->cr();
3516     tty->cr();
3517   }
3518 
3519   // process all operations of the block
3520   process_operations(block->lir(), input_state);
3521 
3522   // iterate all successors
3523   for (int i = 0; i < block->number_of_sux(); i++) {
3524     process_successor(block->sux_at(i), input_state);
3525   }
3526 }
3527 
3528 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3529   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3530 
3531   // must copy state because it is modified
3532   input_state = copy(input_state);
3533 
3534   if (xhandler->entry_code() != NULL) {
3535     process_operations(xhandler->entry_code(), input_state);
3536   }
3537   process_successor(xhandler->entry_block(), input_state);
3538 }
3539 
3540 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3541   IntervalList* saved_state = state_for_block(block);
3542 
3543   if (saved_state != NULL) {
3544     // this block was already processed before.
3545     // check if new input_state is consistent with saved_state
3546 
3547     bool saved_state_correct = true;
3548     for (int i = 0; i < state_size(); i++) {
3549       if (input_state->at(i) != saved_state->at(i)) {
3550         // current input_state and previous saved_state assume a different
3551         // interval in this register -> assume that this register is invalid
3552         if (saved_state->at(i) != NULL) {
3553           // invalidate old calculation only if it assumed that
3554           // register was valid. when the register was already invalid,
3555           // then the old calculation was correct.
3556           saved_state_correct = false;
3557           saved_state->at_put(i, NULL);
3558 
3559           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3560         }
3561       }
3562     }
3563 
3564     if (saved_state_correct) {
3565       // already processed block with correct input_state
3566       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3567     } else {
3568       // must re-visit this block
3569       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3570       add_to_work_list(block);
3571     }
3572 
3573   } else {
3574     // block was not processed before, so set initial input_state
3575     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3576 
3577     set_state_for_block(block, copy(input_state));
3578     add_to_work_list(block);
3579   }
3580 }
3581 
3582 
3583 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3584   IntervalList* copy_state = new IntervalList(input_state->length());
3585   copy_state->appendAll(input_state);
3586   return copy_state;
3587 }
3588 
3589 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3590   if (reg != LinearScan::any_reg && reg < state_size()) {
3591     if (interval != NULL) {
3592       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3593     } else if (input_state->at(reg) != NULL) {
3594       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3595     }
3596 
3597     input_state->at_put(reg, interval);
3598   }
3599 }
3600 
3601 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3602   if (reg != LinearScan::any_reg && reg < state_size()) {
3603     if (input_state->at(reg) != interval) {
3604       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3605       return true;
3606     }
3607   }
3608   return false;
3609 }
3610 
3611 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3612   // visit all instructions of the block
3613   LIR_OpVisitState visitor;
3614   bool has_error = false;
3615 
3616   for (int i = 0; i < ops->length(); i++) {
3617     LIR_Op* op = ops->at(i);
3618     visitor.visit(op);
3619 
3620     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3621 
3622     // check if input operands are correct
3623     int j;
3624     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3625     for (j = 0; j < n; j++) {
3626       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3627       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3628         Interval* interval = interval_at(reg_num(opr));
3629         if (op->id() != -1) {
3630           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3631         }
3632 
3633         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3634         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3635 
3636         // When an operand is marked with is_last_use, then the fpu stack allocator
3637         // removes the register from the fpu stack -> the register contains no value
3638         if (opr->is_last_use()) {
3639           state_put(input_state, interval->assigned_reg(),   NULL);
3640           state_put(input_state, interval->assigned_regHi(), NULL);
3641         }
3642       }
3643     }
3644 
3645     // invalidate all caller save registers at calls
3646     if (visitor.has_call()) {
3647       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3648         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3649       }
3650       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3651         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3652       }
3653 
3654 #ifdef X86
3655       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3656       for (j = 0; j < num_caller_save_xmm_regs; j++) {
3657         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3658       }
3659 #endif
3660     }
3661 
3662     // process xhandler before output and temp operands
3663     XHandlers* xhandlers = visitor.all_xhandler();
3664     n = xhandlers->length();
3665     for (int k = 0; k < n; k++) {
3666       process_xhandler(xhandlers->handler_at(k), input_state);
3667     }
3668 
3669     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3670     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3671     for (j = 0; j < n; j++) {
3672       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3673       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3674         Interval* interval = interval_at(reg_num(opr));
3675         if (op->id() != -1) {
3676           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3677         }
3678 
3679         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3680         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3681       }
3682     }
3683 
3684     // set output operands
3685     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3686     for (j = 0; j < n; j++) {
3687       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3688       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3689         Interval* interval = interval_at(reg_num(opr));
3690         if (op->id() != -1) {
3691           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3692         }
3693 
3694         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3695         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3696       }
3697     }
3698   }
3699   assert(has_error == false, "Error in register allocation");
3700 }
3701 
3702 #endif // ASSERT
3703 
3704 
3705 
3706 // **** Implementation of MoveResolver ******************************
3707 
3708 MoveResolver::MoveResolver(LinearScan* allocator) :
3709   _allocator(allocator),
3710   _multiple_reads_allowed(false),
3711   _mapping_from(8),
3712   _mapping_from_opr(8),
3713   _mapping_to(8),
3714   _insert_list(NULL),
3715   _insert_idx(-1),
3716   _insertion_buffer()
3717 {
3718   for (int i = 0; i < LinearScan::nof_regs; i++) {
3719     _register_blocked[i] = 0;
3720   }
3721   DEBUG_ONLY(check_empty());
3722 }
3723 
3724 
3725 #ifdef ASSERT
3726 
3727 void MoveResolver::check_empty() {
3728   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3729   for (int i = 0; i < LinearScan::nof_regs; i++) {
3730     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3731   }
3732   assert(_multiple_reads_allowed == false, "must have default value");
3733 }
3734 
3735 void MoveResolver::verify_before_resolve() {
3736   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3737   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3738   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3739 
3740   int i, j;
3741   if (!_multiple_reads_allowed) {
3742     for (i = 0; i < _mapping_from.length(); i++) {
3743       for (j = i + 1; j < _mapping_from.length(); j++) {
3744         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3745       }
3746     }
3747   }
3748 
3749   for (i = 0; i < _mapping_to.length(); i++) {
3750     for (j = i + 1; j < _mapping_to.length(); j++) {
3751       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3752     }
3753   }
3754 
3755 
3756   ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3757   if (!_multiple_reads_allowed) {
3758     for (i = 0; i < _mapping_from.length(); i++) {
3759       Interval* it = _mapping_from.at(i);
3760       if (it != NULL) {
3761         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3762         used_regs.set_bit(it->assigned_reg());
3763 
3764         if (it->assigned_regHi() != LinearScan::any_reg) {
3765           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3766           used_regs.set_bit(it->assigned_regHi());
3767         }
3768       }
3769     }
3770   }
3771 
3772   used_regs.clear();
3773   for (i = 0; i < _mapping_to.length(); i++) {
3774     Interval* it = _mapping_to.at(i);
3775     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3776     used_regs.set_bit(it->assigned_reg());
3777 
3778     if (it->assigned_regHi() != LinearScan::any_reg) {
3779       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3780       used_regs.set_bit(it->assigned_regHi());
3781     }
3782   }
3783 
3784   used_regs.clear();
3785   for (i = 0; i < _mapping_from.length(); i++) {
3786     Interval* it = _mapping_from.at(i);
3787     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3788       used_regs.set_bit(it->assigned_reg());
3789     }
3790   }
3791   for (i = 0; i < _mapping_to.length(); i++) {
3792     Interval* it = _mapping_to.at(i);
3793     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3794   }
3795 }
3796 
3797 #endif // ASSERT
3798 
3799 
3800 // mark assigned_reg and assigned_regHi of the interval as blocked
3801 void MoveResolver::block_registers(Interval* it) {
3802   int reg = it->assigned_reg();
3803   if (reg < LinearScan::nof_regs) {
3804     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3805     set_register_blocked(reg, 1);
3806   }
3807   reg = it->assigned_regHi();
3808   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3809     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3810     set_register_blocked(reg, 1);
3811   }
3812 }
3813 
3814 // mark assigned_reg and assigned_regHi of the interval as unblocked
3815 void MoveResolver::unblock_registers(Interval* it) {
3816   int reg = it->assigned_reg();
3817   if (reg < LinearScan::nof_regs) {
3818     assert(register_blocked(reg) > 0, "register already marked as unused");
3819     set_register_blocked(reg, -1);
3820   }
3821   reg = it->assigned_regHi();
3822   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3823     assert(register_blocked(reg) > 0, "register already marked as unused");
3824     set_register_blocked(reg, -1);
3825   }
3826 }
3827 
3828 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3829 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3830   int from_reg = -1;
3831   int from_regHi = -1;
3832   if (from != NULL) {
3833     from_reg = from->assigned_reg();
3834     from_regHi = from->assigned_regHi();
3835   }
3836 
3837   int reg = to->assigned_reg();
3838   if (reg < LinearScan::nof_regs) {
3839     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3840       return false;
3841     }
3842   }
3843   reg = to->assigned_regHi();
3844   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3845     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3846       return false;
3847     }
3848   }
3849 
3850   return true;
3851 }
3852 
3853 
3854 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3855   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3856   _insertion_buffer.init(list);
3857 }
3858 
3859 void MoveResolver::append_insertion_buffer() {
3860   if (_insertion_buffer.initialized()) {
3861     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3862   }
3863   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3864 
3865   _insert_list = NULL;
3866   _insert_idx = -1;
3867 }
3868 
3869 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3870   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3871   assert(from_interval->type() == to_interval->type(), "move between different types");
3872   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3873   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3874 
3875   LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3876   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3877 
3878   if (!_multiple_reads_allowed) {
3879     // the last_use flag is an optimization for FPU stack allocation. When the same
3880     // input interval is used in more than one move, then it is too difficult to determine
3881     // if this move is really the last use.
3882     from_opr = from_opr->make_last_use();
3883   }
3884   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3885 
3886   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3887 }
3888 
3889 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3890   assert(from_opr->type() == to_interval->type(), "move between different types");
3891   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3892   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3893 
3894   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3895   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3896 
3897   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3898 }
3899 
3900 
3901 void MoveResolver::resolve_mappings() {
3902   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3903   DEBUG_ONLY(verify_before_resolve());
3904 
3905   // Block all registers that are used as input operands of a move.
3906   // When a register is blocked, no move to this register is emitted.
3907   // This is necessary for detecting cycles in moves.
3908   int i;
3909   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3910     Interval* from_interval = _mapping_from.at(i);
3911     if (from_interval != NULL) {
3912       block_registers(from_interval);
3913     }
3914   }
3915 
3916   int spill_candidate = -1;
3917   while (_mapping_from.length() > 0) {
3918     bool processed_interval = false;
3919 
3920     for (i = _mapping_from.length() - 1; i >= 0; i--) {
3921       Interval* from_interval = _mapping_from.at(i);
3922       Interval* to_interval = _mapping_to.at(i);
3923 
3924       if (save_to_process_move(from_interval, to_interval)) {
3925         // this inverval can be processed because target is free
3926         if (from_interval != NULL) {
3927           insert_move(from_interval, to_interval);
3928           unblock_registers(from_interval);
3929         } else {
3930           insert_move(_mapping_from_opr.at(i), to_interval);
3931         }
3932         _mapping_from.remove_at(i);
3933         _mapping_from_opr.remove_at(i);
3934         _mapping_to.remove_at(i);
3935 
3936         processed_interval = true;
3937       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3938         // this interval cannot be processed now because target is not free
3939         // it starts in a register, so it is a possible candidate for spilling
3940         spill_candidate = i;
3941       }
3942     }
3943 
3944     if (!processed_interval) {
3945       // no move could be processed because there is a cycle in the move list
3946       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3947       assert(spill_candidate != -1, "no interval in register for spilling found");
3948 
3949       // create a new spill interval and assign a stack slot to it
3950       Interval* from_interval = _mapping_from.at(spill_candidate);
3951       Interval* spill_interval = new Interval(-1);
3952       spill_interval->set_type(from_interval->type());
3953 
3954       // add a dummy range because real position is difficult to calculate
3955       // Note: this range is a special case when the integrity of the allocation is checked
3956       spill_interval->add_range(1, 2);
3957 
3958       //       do not allocate a new spill slot for temporary interval, but
3959       //       use spill slot assigned to from_interval. Otherwise moves from
3960       //       one stack slot to another can happen (not allowed by LIR_Assembler
3961       int spill_slot = from_interval->canonical_spill_slot();
3962       if (spill_slot < 0) {
3963         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3964         from_interval->set_canonical_spill_slot(spill_slot);
3965       }
3966       spill_interval->assign_reg(spill_slot);
3967       allocator()->append_interval(spill_interval);
3968 
3969       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3970 
3971       // insert a move from register to stack and update the mapping
3972       insert_move(from_interval, spill_interval);
3973       _mapping_from.at_put(spill_candidate, spill_interval);
3974       unblock_registers(from_interval);
3975     }
3976   }
3977 
3978   // reset to default value
3979   _multiple_reads_allowed = false;
3980 
3981   // check that all intervals have been processed
3982   DEBUG_ONLY(check_empty());
3983 }
3984 
3985 
3986 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
3987   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3988   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
3989 
3990   create_insertion_buffer(insert_list);
3991   _insert_list = insert_list;
3992   _insert_idx = insert_idx;
3993 }
3994 
3995 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
3996   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3997 
3998   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
3999     // insert position changed -> resolve current mappings
4000     resolve_mappings();
4001   }
4002 
4003   if (insert_list != _insert_list) {
4004     // block changed -> append insertion_buffer because it is
4005     // bound to a specific block and create a new insertion_buffer
4006     append_insertion_buffer();
4007     create_insertion_buffer(insert_list);
4008   }
4009 
4010   _insert_list = insert_list;
4011   _insert_idx = insert_idx;
4012 }
4013 
4014 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4015   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4016 
4017   _mapping_from.append(from_interval);
4018   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4019   _mapping_to.append(to_interval);
4020 }
4021 
4022 
4023 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4024   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4025   assert(from_opr->is_constant(), "only for constants");
4026 
4027   _mapping_from.append(NULL);
4028   _mapping_from_opr.append(from_opr);
4029   _mapping_to.append(to_interval);
4030 }
4031 
4032 void MoveResolver::resolve_and_append_moves() {
4033   if (has_mappings()) {
4034     resolve_mappings();
4035   }
4036   append_insertion_buffer();
4037 }
4038 
4039 
4040 
4041 // **** Implementation of Range *************************************
4042 
4043 Range::Range(int from, int to, Range* next) :
4044   _from(from),
4045   _to(to),
4046   _next(next)
4047 {
4048 }
4049 
4050 // initialize sentinel
4051 Range* Range::_end = NULL;
4052 void Range::initialize(Arena* arena) {
4053   _end = new (arena) Range(max_jint, max_jint, NULL);
4054 }
4055 
4056 int Range::intersects_at(Range* r2) const {
4057   const Range* r1 = this;
4058 
4059   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4060   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4061 
4062   do {
4063     if (r1->from() < r2->from()) {
4064       if (r1->to() <= r2->from()) {
4065         r1 = r1->next(); if (r1 == _end) return -1;
4066       } else {
4067         return r2->from();
4068       }
4069     } else if (r2->from() < r1->from()) {
4070       if (r2->to() <= r1->from()) {
4071         r2 = r2->next(); if (r2 == _end) return -1;
4072       } else {
4073         return r1->from();
4074       }
4075     } else { // r1->from() == r2->from()
4076       if (r1->from() == r1->to()) {
4077         r1 = r1->next(); if (r1 == _end) return -1;
4078       } else if (r2->from() == r2->to()) {
4079         r2 = r2->next(); if (r2 == _end) return -1;
4080       } else {
4081         return r1->from();
4082       }
4083     }
4084   } while (true);
4085 }
4086 
4087 #ifndef PRODUCT
4088 void Range::print(outputStream* out) const {
4089   out->print("[%d, %d[ ", _from, _to);
4090 }
4091 #endif
4092 
4093 
4094 
4095 // **** Implementation of Interval **********************************
4096 
4097 // initialize sentinel
4098 Interval* Interval::_end = NULL;
4099 void Interval::initialize(Arena* arena) {
4100   Range::initialize(arena);
4101   _end = new (arena) Interval(-1);
4102 }
4103 
4104 Interval::Interval(int reg_num) :
4105   _reg_num(reg_num),
4106   _type(T_ILLEGAL),
4107   _first(Range::end()),
4108   _use_pos_and_kinds(12),
4109   _current(Range::end()),
4110   _next(_end),
4111   _state(invalidState),
4112   _assigned_reg(LinearScan::any_reg),
4113   _assigned_regHi(LinearScan::any_reg),
4114   _cached_to(-1),
4115   _cached_opr(LIR_OprFact::illegalOpr),
4116   _cached_vm_reg(VMRegImpl::Bad()),
4117   _split_children(0),
4118   _canonical_spill_slot(-1),
4119   _insert_move_when_activated(false),
4120   _register_hint(NULL),
4121   _spill_state(noDefinitionFound),
4122   _spill_definition_pos(-1)
4123 {
4124   _split_parent = this;
4125   _current_split_child = this;
4126 }
4127 
4128 int Interval::calc_to() {
4129   assert(_first != Range::end(), "interval has no range");
4130 
4131   Range* r = _first;
4132   while (r->next() != Range::end()) {
4133     r = r->next();
4134   }
4135   return r->to();
4136 }
4137 
4138 
4139 #ifdef ASSERT
4140 // consistency check of split-children
4141 void Interval::check_split_children() {
4142   if (_split_children.length() > 0) {
4143     assert(is_split_parent(), "only split parents can have children");
4144 
4145     for (int i = 0; i < _split_children.length(); i++) {
4146       Interval* i1 = _split_children.at(i);
4147 
4148       assert(i1->split_parent() == this, "not a split child of this interval");
4149       assert(i1->type() == type(), "must be equal for all split children");
4150       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4151 
4152       for (int j = i + 1; j < _split_children.length(); j++) {
4153         Interval* i2 = _split_children.at(j);
4154 
4155         assert(i1->reg_num() != i2->reg_num(), "same register number");
4156 
4157         if (i1->from() < i2->from()) {
4158           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4159         } else {
4160           assert(i2->from() < i1->from(), "intervals start at same op_id");
4161           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4162         }
4163       }
4164     }
4165   }
4166 }
4167 #endif // ASSERT
4168 
4169 Interval* Interval::register_hint(bool search_split_child) const {
4170   if (!search_split_child) {
4171     return _register_hint;
4172   }
4173 
4174   if (_register_hint != NULL) {
4175     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4176 
4177     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4178       return _register_hint;
4179 
4180     } else if (_register_hint->_split_children.length() > 0) {
4181       // search the first split child that has a register assigned
4182       int len = _register_hint->_split_children.length();
4183       for (int i = 0; i < len; i++) {
4184         Interval* cur = _register_hint->_split_children.at(i);
4185 
4186         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4187           return cur;
4188         }
4189       }
4190     }
4191   }
4192 
4193   // no hint interval found that has a register assigned
4194   return NULL;
4195 }
4196 
4197 
4198 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4199   assert(is_split_parent(), "can only be called for split parents");
4200   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4201 
4202   Interval* result;
4203   if (_split_children.length() == 0) {
4204     result = this;
4205   } else {
4206     result = NULL;
4207     int len = _split_children.length();
4208 
4209     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4210     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4211 
4212     int i;
4213     for (i = 0; i < len; i++) {
4214       Interval* cur = _split_children.at(i);
4215       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4216         if (i > 0) {
4217           // exchange current split child to start of list (faster access for next call)
4218           _split_children.at_put(i, _split_children.at(0));
4219           _split_children.at_put(0, cur);
4220         }
4221 
4222         // interval found
4223         result = cur;
4224         break;
4225       }
4226     }
4227 
4228 #ifdef ASSERT
4229     for (i = 0; i < len; i++) {
4230       Interval* tmp = _split_children.at(i);
4231       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4232         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4233         result->print();
4234         tmp->print();
4235         assert(false, "two valid result intervals found");
4236       }
4237     }
4238 #endif
4239   }
4240 
4241   assert(result != NULL, "no matching interval found");
4242   assert(result->covers(op_id, mode), "op_id not covered by interval");
4243 
4244   return result;
4245 }
4246 
4247 
4248 // returns the last split child that ends before the given op_id
4249 Interval* Interval::split_child_before_op_id(int op_id) {
4250   assert(op_id >= 0, "invalid op_id");
4251 
4252   Interval* parent = split_parent();
4253   Interval* result = NULL;
4254 
4255   int len = parent->_split_children.length();
4256   assert(len > 0, "no split children available");
4257 
4258   for (int i = len - 1; i >= 0; i--) {
4259     Interval* cur = parent->_split_children.at(i);
4260     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4261       result = cur;
4262     }
4263   }
4264 
4265   assert(result != NULL, "no split child found");
4266   return result;
4267 }
4268 
4269 
4270 // checks if op_id is covered by any split child
4271 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4272   assert(is_split_parent(), "can only be called for split parents");
4273   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4274 
4275   if (_split_children.length() == 0) {
4276     // simple case if interval was not split
4277     return covers(op_id, mode);
4278 
4279   } else {
4280     // extended case: check all split children
4281     int len = _split_children.length();
4282     for (int i = 0; i < len; i++) {
4283       Interval* cur = _split_children.at(i);
4284       if (cur->covers(op_id, mode)) {
4285         return true;
4286       }
4287     }
4288     return false;
4289   }
4290 }
4291 
4292 
4293 // Note: use positions are sorted descending -> first use has highest index
4294 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4295   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4296 
4297   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4298     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4299       return _use_pos_and_kinds.at(i);
4300     }
4301   }
4302   return max_jint;
4303 }
4304 
4305 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4306   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4307 
4308   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4309     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4310       return _use_pos_and_kinds.at(i);
4311     }
4312   }
4313   return max_jint;
4314 }
4315 
4316 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4317   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4318 
4319   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4320     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4321       return _use_pos_and_kinds.at(i);
4322     }
4323   }
4324   return max_jint;
4325 }
4326 
4327 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4328   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4329 
4330   int prev = 0;
4331   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4332     if (_use_pos_and_kinds.at(i) > from) {
4333       return prev;
4334     }
4335     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4336       prev = _use_pos_and_kinds.at(i);
4337     }
4338   }
4339   return prev;
4340 }
4341 
4342 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4343   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4344 
4345   // do not add use positions for precolored intervals because
4346   // they are never used
4347   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4348 #ifdef ASSERT
4349     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4350     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4351       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4352       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4353       if (i > 0) {
4354         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4355       }
4356     }
4357 #endif
4358 
4359     // Note: add_use is called in descending order, so list gets sorted
4360     //       automatically by just appending new use positions
4361     int len = _use_pos_and_kinds.length();
4362     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4363       _use_pos_and_kinds.append(pos);
4364       _use_pos_and_kinds.append(use_kind);
4365     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4366       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4367       _use_pos_and_kinds.at_put(len - 1, use_kind);
4368     }
4369   }
4370 }
4371 
4372 void Interval::add_range(int from, int to) {
4373   assert(from < to, "invalid range");
4374   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4375   assert(from <= first()->to(), "not inserting at begin of interval");
4376 
4377   if (first()->from() <= to) {
4378     // join intersecting ranges
4379     first()->set_from(MIN2(from, first()->from()));
4380     first()->set_to  (MAX2(to,   first()->to()));
4381   } else {
4382     // insert new range
4383     _first = new Range(from, to, first());
4384   }
4385 }
4386 
4387 Interval* Interval::new_split_child() {
4388   // allocate new interval
4389   Interval* result = new Interval(-1);
4390   result->set_type(type());
4391 
4392   Interval* parent = split_parent();
4393   result->_split_parent = parent;
4394   result->set_register_hint(parent);
4395 
4396   // insert new interval in children-list of parent
4397   if (parent->_split_children.length() == 0) {
4398     assert(is_split_parent(), "list must be initialized at first split");
4399 
4400     parent->_split_children = IntervalList(4);
4401     parent->_split_children.append(this);
4402   }
4403   parent->_split_children.append(result);
4404 
4405   return result;
4406 }
4407 
4408 // split this interval at the specified position and return
4409 // the remainder as a new interval.
4410 //
4411 // when an interval is split, a bi-directional link is established between the original interval
4412 // (the split parent) and the intervals that are split off this interval (the split children)
4413 // When a split child is split again, the new created interval is also a direct child
4414 // of the original parent (there is no tree of split children stored, but a flat list)
4415 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4416 //
4417 // Note: The new interval has no valid reg_num
4418 Interval* Interval::split(int split_pos) {
4419   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4420 
4421   // allocate new interval
4422   Interval* result = new_split_child();
4423 
4424   // split the ranges
4425   Range* prev = NULL;
4426   Range* cur = _first;
4427   while (cur != Range::end() && cur->to() <= split_pos) {
4428     prev = cur;
4429     cur = cur->next();
4430   }
4431   assert(cur != Range::end(), "split interval after end of last range");
4432 
4433   if (cur->from() < split_pos) {
4434     result->_first = new Range(split_pos, cur->to(), cur->next());
4435     cur->set_to(split_pos);
4436     cur->set_next(Range::end());
4437 
4438   } else {
4439     assert(prev != NULL, "split before start of first range");
4440     result->_first = cur;
4441     prev->set_next(Range::end());
4442   }
4443   result->_current = result->_first;
4444   _cached_to = -1; // clear cached value
4445 
4446   // split list of use positions
4447   int total_len = _use_pos_and_kinds.length();
4448   int start_idx = total_len - 2;
4449   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4450     start_idx -= 2;
4451   }
4452 
4453   intStack new_use_pos_and_kinds(total_len - start_idx);
4454   int i;
4455   for (i = start_idx + 2; i < total_len; i++) {
4456     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4457   }
4458 
4459   _use_pos_and_kinds.trunc_to(start_idx + 2);
4460   result->_use_pos_and_kinds = _use_pos_and_kinds;
4461   _use_pos_and_kinds = new_use_pos_and_kinds;
4462 
4463 #ifdef ASSERT
4464   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4465   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4466   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4467 
4468   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4469     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4470     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4471   }
4472   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4473     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4474     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4475   }
4476 #endif
4477 
4478   return result;
4479 }
4480 
4481 // split this interval at the specified position and return
4482 // the head as a new interval (the original interval is the tail)
4483 //
4484 // Currently, only the first range can be split, and the new interval
4485 // must not have split positions
4486 Interval* Interval::split_from_start(int split_pos) {
4487   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4488   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4489   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4490   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4491 
4492   // allocate new interval
4493   Interval* result = new_split_child();
4494 
4495   // the new created interval has only one range (checked by assertion above),
4496   // so the splitting of the ranges is very simple
4497   result->add_range(_first->from(), split_pos);
4498 
4499   if (split_pos == _first->to()) {
4500     assert(_first->next() != Range::end(), "must not be at end");
4501     _first = _first->next();
4502   } else {
4503     _first->set_from(split_pos);
4504   }
4505 
4506   return result;
4507 }
4508 
4509 
4510 // returns true if the op_id is inside the interval
4511 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4512   Range* cur  = _first;
4513 
4514   while (cur != Range::end() && cur->to() < op_id) {
4515     cur = cur->next();
4516   }
4517   if (cur != Range::end()) {
4518     assert(cur->to() != cur->next()->from(), "ranges not separated");
4519 
4520     if (mode == LIR_OpVisitState::outputMode) {
4521       return cur->from() <= op_id && op_id < cur->to();
4522     } else {
4523       return cur->from() <= op_id && op_id <= cur->to();
4524     }
4525   }
4526   return false;
4527 }
4528 
4529 // returns true if the interval has any hole between hole_from and hole_to
4530 // (even if the hole has only the length 1)
4531 bool Interval::has_hole_between(int hole_from, int hole_to) {
4532   assert(hole_from < hole_to, "check");
4533   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4534 
4535   Range* cur  = _first;
4536   while (cur != Range::end()) {
4537     assert(cur->to() < cur->next()->from(), "no space between ranges");
4538 
4539     // hole-range starts before this range -> hole
4540     if (hole_from < cur->from()) {
4541       return true;
4542 
4543     // hole-range completely inside this range -> no hole
4544     } else if (hole_to <= cur->to()) {
4545       return false;
4546 
4547     // overlapping of hole-range with this range -> hole
4548     } else if (hole_from <= cur->to()) {
4549       return true;
4550     }
4551 
4552     cur = cur->next();
4553   }
4554 
4555   return false;
4556 }
4557 
4558 
4559 #ifndef PRODUCT
4560 void Interval::print(outputStream* out) const {
4561   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4562   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4563 
4564   const char* type_name;
4565   LIR_Opr opr = LIR_OprFact::illegal();
4566   if (reg_num() < LIR_OprDesc::vreg_base) {
4567     type_name = "fixed";
4568     // need a temporary operand for fixed intervals because type() cannot be called
4569 #ifdef X86
4570     int last_xmm_reg = pd_last_xmm_reg;
4571 #ifdef _LP64
4572     if (UseAVX < 3) {
4573       last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
4574     }
4575 #endif
4576 #endif
4577     if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4578       opr = LIR_OprFact::single_cpu(assigned_reg());
4579     } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4580       opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4581 #ifdef X86
4582     } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) {
4583       opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4584 #endif
4585     } else {
4586       ShouldNotReachHere();
4587     }
4588   } else {
4589     type_name = type2name(type());
4590     if (assigned_reg() != -1 &&
4591         (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4592       opr = LinearScan::calc_operand_for_interval(this);
4593     }
4594   }
4595 
4596   out->print("%d %s ", reg_num(), type_name);
4597   if (opr->is_valid()) {
4598     out->print("\"");
4599     opr->print(out);
4600     out->print("\" ");
4601   }
4602   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4603 
4604   // print ranges
4605   Range* cur = _first;
4606   while (cur != Range::end()) {
4607     cur->print(out);
4608     cur = cur->next();
4609     assert(cur != NULL, "range list not closed with range sentinel");
4610   }
4611 
4612   // print use positions
4613   int prev = 0;
4614   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4615   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4616     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4617     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4618 
4619     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4620     prev = _use_pos_and_kinds.at(i);
4621   }
4622 
4623   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4624   out->cr();
4625 }
4626 #endif
4627 
4628 
4629 
4630 // **** Implementation of IntervalWalker ****************************
4631 
4632 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4633  : _compilation(allocator->compilation())
4634  , _allocator(allocator)
4635 {
4636   _unhandled_first[fixedKind] = unhandled_fixed_first;
4637   _unhandled_first[anyKind]   = unhandled_any_first;
4638   _active_first[fixedKind]    = Interval::end();
4639   _inactive_first[fixedKind]  = Interval::end();
4640   _active_first[anyKind]      = Interval::end();
4641   _inactive_first[anyKind]    = Interval::end();
4642   _current_position = -1;
4643   _current = NULL;
4644   next_interval();
4645 }
4646 
4647 
4648 // append interval at top of list
4649 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4650   interval->set_next(*list); *list = interval;
4651 }
4652 
4653 
4654 // append interval in order of current range from()
4655 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4656   Interval* prev = NULL;
4657   Interval* cur  = *list;
4658   while (cur->current_from() < interval->current_from()) {
4659     prev = cur; cur = cur->next();
4660   }
4661   if (prev == NULL) {
4662     *list = interval;
4663   } else {
4664     prev->set_next(interval);
4665   }
4666   interval->set_next(cur);
4667 }
4668 
4669 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4670   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4671 
4672   Interval* prev = NULL;
4673   Interval* cur  = *list;
4674   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4675     prev = cur; cur = cur->next();
4676   }
4677   if (prev == NULL) {
4678     *list = interval;
4679   } else {
4680     prev->set_next(interval);
4681   }
4682   interval->set_next(cur);
4683 }
4684 
4685 
4686 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4687   while (*list != Interval::end() && *list != i) {
4688     list = (*list)->next_addr();
4689   }
4690   if (*list != Interval::end()) {
4691     assert(*list == i, "check");
4692     *list = (*list)->next();
4693     return true;
4694   } else {
4695     return false;
4696   }
4697 }
4698 
4699 void IntervalWalker::remove_from_list(Interval* i) {
4700   bool deleted;
4701 
4702   if (i->state() == activeState) {
4703     deleted = remove_from_list(active_first_addr(anyKind), i);
4704   } else {
4705     assert(i->state() == inactiveState, "invalid state");
4706     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4707   }
4708 
4709   assert(deleted, "interval has not been found in list");
4710 }
4711 
4712 
4713 void IntervalWalker::walk_to(IntervalState state, int from) {
4714   assert (state == activeState || state == inactiveState, "wrong state");
4715   for_each_interval_kind(kind) {
4716     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4717     Interval* next   = *prev;
4718     while (next->current_from() <= from) {
4719       Interval* cur = next;
4720       next = cur->next();
4721 
4722       bool range_has_changed = false;
4723       while (cur->current_to() <= from) {
4724         cur->next_range();
4725         range_has_changed = true;
4726       }
4727 
4728       // also handle move from inactive list to active list
4729       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4730 
4731       if (range_has_changed) {
4732         // remove cur from list
4733         *prev = next;
4734         if (cur->current_at_end()) {
4735           // move to handled state (not maintained as a list)
4736           cur->set_state(handledState);
4737           interval_moved(cur, kind, state, handledState);
4738         } else if (cur->current_from() <= from){
4739           // sort into active list
4740           append_sorted(active_first_addr(kind), cur);
4741           cur->set_state(activeState);
4742           if (*prev == cur) {
4743             assert(state == activeState, "check");
4744             prev = cur->next_addr();
4745           }
4746           interval_moved(cur, kind, state, activeState);
4747         } else {
4748           // sort into inactive list
4749           append_sorted(inactive_first_addr(kind), cur);
4750           cur->set_state(inactiveState);
4751           if (*prev == cur) {
4752             assert(state == inactiveState, "check");
4753             prev = cur->next_addr();
4754           }
4755           interval_moved(cur, kind, state, inactiveState);
4756         }
4757       } else {
4758         prev = cur->next_addr();
4759         continue;
4760       }
4761     }
4762   }
4763 }
4764 
4765 
4766 void IntervalWalker::next_interval() {
4767   IntervalKind kind;
4768   Interval* any   = _unhandled_first[anyKind];
4769   Interval* fixed = _unhandled_first[fixedKind];
4770 
4771   if (any != Interval::end()) {
4772     // intervals may start at same position -> prefer fixed interval
4773     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4774 
4775     assert (kind == fixedKind && fixed->from() <= any->from() ||
4776             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4777     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4778 
4779   } else if (fixed != Interval::end()) {
4780     kind = fixedKind;
4781   } else {
4782     _current = NULL; return;
4783   }
4784   _current_kind = kind;
4785   _current = _unhandled_first[kind];
4786   _unhandled_first[kind] = _current->next();
4787   _current->set_next(Interval::end());
4788   _current->rewind_range();
4789 }
4790 
4791 
4792 void IntervalWalker::walk_to(int lir_op_id) {
4793   assert(_current_position <= lir_op_id, "can not walk backwards");
4794   while (current() != NULL) {
4795     bool is_active = current()->from() <= lir_op_id;
4796     int id = is_active ? current()->from() : lir_op_id;
4797 
4798     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4799 
4800     // set _current_position prior to call of walk_to
4801     _current_position = id;
4802 
4803     // call walk_to even if _current_position == id
4804     walk_to(activeState, id);
4805     walk_to(inactiveState, id);
4806 
4807     if (is_active) {
4808       current()->set_state(activeState);
4809       if (activate_current()) {
4810         append_sorted(active_first_addr(current_kind()), current());
4811         interval_moved(current(), current_kind(), unhandledState, activeState);
4812       }
4813 
4814       next_interval();
4815     } else {
4816       return;
4817     }
4818   }
4819 }
4820 
4821 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4822 #ifndef PRODUCT
4823   if (TraceLinearScanLevel >= 4) {
4824     #define print_state(state) \
4825     switch(state) {\
4826       case unhandledState: tty->print("unhandled"); break;\
4827       case activeState: tty->print("active"); break;\
4828       case inactiveState: tty->print("inactive"); break;\
4829       case handledState: tty->print("handled"); break;\
4830       default: ShouldNotReachHere(); \
4831     }
4832 
4833     print_state(from); tty->print(" to "); print_state(to);
4834     tty->fill_to(23);
4835     interval->print();
4836 
4837     #undef print_state
4838   }
4839 #endif
4840 }
4841 
4842 
4843 
4844 // **** Implementation of LinearScanWalker **************************
4845 
4846 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4847   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4848   , _move_resolver(allocator)
4849 {
4850   for (int i = 0; i < LinearScan::nof_regs; i++) {
4851     _spill_intervals[i] = new IntervalList(2);
4852   }
4853 }
4854 
4855 
4856 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4857   for (int i = _first_reg; i <= _last_reg; i++) {
4858     _use_pos[i] = max_jint;
4859 
4860     if (!only_process_use_pos) {
4861       _block_pos[i] = max_jint;
4862       _spill_intervals[i]->clear();
4863     }
4864   }
4865 }
4866 
4867 inline void LinearScanWalker::exclude_from_use(int reg) {
4868   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4869   if (reg >= _first_reg && reg <= _last_reg) {
4870     _use_pos[reg] = 0;
4871   }
4872 }
4873 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4874   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4875 
4876   exclude_from_use(i->assigned_reg());
4877   exclude_from_use(i->assigned_regHi());
4878 }
4879 
4880 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4881   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4882 
4883   if (reg >= _first_reg && reg <= _last_reg) {
4884     if (_use_pos[reg] > use_pos) {
4885       _use_pos[reg] = use_pos;
4886     }
4887     if (!only_process_use_pos) {
4888       _spill_intervals[reg]->append(i);
4889     }
4890   }
4891 }
4892 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4893   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4894   if (use_pos != -1) {
4895     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4896     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4897   }
4898 }
4899 
4900 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4901   if (reg >= _first_reg && reg <= _last_reg) {
4902     if (_block_pos[reg] > block_pos) {
4903       _block_pos[reg] = block_pos;
4904     }
4905     if (_use_pos[reg] > block_pos) {
4906       _use_pos[reg] = block_pos;
4907     }
4908   }
4909 }
4910 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4911   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4912   if (block_pos != -1) {
4913     set_block_pos(i->assigned_reg(), i, block_pos);
4914     set_block_pos(i->assigned_regHi(), i, block_pos);
4915   }
4916 }
4917 
4918 
4919 void LinearScanWalker::free_exclude_active_fixed() {
4920   Interval* list = active_first(fixedKind);
4921   while (list != Interval::end()) {
4922     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4923     exclude_from_use(list);
4924     list = list->next();
4925   }
4926 }
4927 
4928 void LinearScanWalker::free_exclude_active_any() {
4929   Interval* list = active_first(anyKind);
4930   while (list != Interval::end()) {
4931     exclude_from_use(list);
4932     list = list->next();
4933   }
4934 }
4935 
4936 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4937   Interval* list = inactive_first(fixedKind);
4938   while (list != Interval::end()) {
4939     if (cur->to() <= list->current_from()) {
4940       assert(list->current_intersects_at(cur) == -1, "must not intersect");
4941       set_use_pos(list, list->current_from(), true);
4942     } else {
4943       set_use_pos(list, list->current_intersects_at(cur), true);
4944     }
4945     list = list->next();
4946   }
4947 }
4948 
4949 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4950   Interval* list = inactive_first(anyKind);
4951   while (list != Interval::end()) {
4952     set_use_pos(list, list->current_intersects_at(cur), true);
4953     list = list->next();
4954   }
4955 }
4956 
4957 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4958   Interval* list = unhandled_first(kind);
4959   while (list != Interval::end()) {
4960     set_use_pos(list, list->intersects_at(cur), true);
4961     if (kind == fixedKind && cur->to() <= list->from()) {
4962       set_use_pos(list, list->from(), true);
4963     }
4964     list = list->next();
4965   }
4966 }
4967 
4968 void LinearScanWalker::spill_exclude_active_fixed() {
4969   Interval* list = active_first(fixedKind);
4970   while (list != Interval::end()) {
4971     exclude_from_use(list);
4972     list = list->next();
4973   }
4974 }
4975 
4976 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4977   Interval* list = unhandled_first(fixedKind);
4978   while (list != Interval::end()) {
4979     set_block_pos(list, list->intersects_at(cur));
4980     list = list->next();
4981   }
4982 }
4983 
4984 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4985   Interval* list = inactive_first(fixedKind);
4986   while (list != Interval::end()) {
4987     if (cur->to() > list->current_from()) {
4988       set_block_pos(list, list->current_intersects_at(cur));
4989     } else {
4990       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4991     }
4992 
4993     list = list->next();
4994   }
4995 }
4996 
4997 void LinearScanWalker::spill_collect_active_any() {
4998   Interval* list = active_first(anyKind);
4999   while (list != Interval::end()) {
5000     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5001     list = list->next();
5002   }
5003 }
5004 
5005 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5006   Interval* list = inactive_first(anyKind);
5007   while (list != Interval::end()) {
5008     if (list->current_intersects(cur)) {
5009       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5010     }
5011     list = list->next();
5012   }
5013 }
5014 
5015 
5016 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5017   // output all moves here. When source and target are equal, the move is
5018   // optimized away later in assign_reg_nums
5019 
5020   op_id = (op_id + 1) & ~1;
5021   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5022   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5023 
5024   // calculate index of instruction inside instruction list of current block
5025   // the minimal index (for a block with no spill moves) can be calculated because the
5026   // numbering of instructions is known.
5027   // When the block already contains spill moves, the index must be increased until the
5028   // correct index is reached.
5029   LIR_OpList* list = op_block->lir()->instructions_list();
5030   int index = (op_id - list->at(0)->id()) / 2;
5031   assert(list->at(index)->id() <= op_id, "error in calculation");
5032 
5033   while (list->at(index)->id() != op_id) {
5034     index++;
5035     assert(0 <= index && index < list->length(), "index out of bounds");
5036   }
5037   assert(1 <= index && index < list->length(), "index out of bounds");
5038   assert(list->at(index)->id() == op_id, "error in calculation");
5039 
5040   // insert new instruction before instruction at position index
5041   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5042   _move_resolver.add_mapping(src_it, dst_it);
5043 }
5044 
5045 
5046 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5047   int from_block_nr = min_block->linear_scan_number();
5048   int to_block_nr = max_block->linear_scan_number();
5049 
5050   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5051   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5052   assert(from_block_nr < to_block_nr, "must cross block boundary");
5053 
5054   // Try to split at end of max_block. If this would be after
5055   // max_split_pos, then use the begin of max_block
5056   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5057   if (optimal_split_pos > max_split_pos) {
5058     optimal_split_pos = max_block->first_lir_instruction_id();
5059   }
5060 
5061   int min_loop_depth = max_block->loop_depth();
5062   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5063     BlockBegin* cur = block_at(i);
5064 
5065     if (cur->loop_depth() < min_loop_depth) {
5066       // block with lower loop-depth found -> split at the end of this block
5067       min_loop_depth = cur->loop_depth();
5068       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5069     }
5070   }
5071   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5072 
5073   return optimal_split_pos;
5074 }
5075 
5076 
5077 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5078   int optimal_split_pos = -1;
5079   if (min_split_pos == max_split_pos) {
5080     // trivial case, no optimization of split position possible
5081     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5082     optimal_split_pos = min_split_pos;
5083 
5084   } else {
5085     assert(min_split_pos < max_split_pos, "must be true then");
5086     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5087 
5088     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5089     // beginning of a block, then min_split_pos is also a possible split position.
5090     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5091     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5092 
5093     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5094     // when an interval ends at the end of the last block of the method
5095     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5096     // block at this op_id)
5097     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5098 
5099     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5100     if (min_block == max_block) {
5101       // split position cannot be moved to block boundary, so split as late as possible
5102       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5103       optimal_split_pos = max_split_pos;
5104 
5105     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5106       // Do not move split position if the interval has a hole before max_split_pos.
5107       // Intervals resulting from Phi-Functions have more than one definition (marked
5108       // as mustHaveRegister) with a hole before each definition. When the register is needed
5109       // for the second definition, an earlier reloading is unnecessary.
5110       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5111       optimal_split_pos = max_split_pos;
5112 
5113     } else {
5114       // seach optimal block boundary between min_split_pos and max_split_pos
5115       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5116 
5117       if (do_loop_optimization) {
5118         // Loop optimization: if a loop-end marker is found between min- and max-position,
5119         // then split before this loop
5120         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5121         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5122 
5123         assert(loop_end_pos > min_split_pos, "invalid order");
5124         if (loop_end_pos < max_split_pos) {
5125           // loop-end marker found between min- and max-position
5126           // if it is not the end marker for the same loop as the min-position, then move
5127           // the max-position to this loop block.
5128           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5129           // of the interval (normally, only mustHaveRegister causes a reloading)
5130           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5131 
5132           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5133           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5134 
5135           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5136           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5137             optimal_split_pos = -1;
5138             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5139           } else {
5140             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5141           }
5142         }
5143       }
5144 
5145       if (optimal_split_pos == -1) {
5146         // not calculated by loop optimization
5147         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5148       }
5149     }
5150   }
5151   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5152 
5153   return optimal_split_pos;
5154 }
5155 
5156 
5157 /*
5158   split an interval at the optimal position between min_split_pos and
5159   max_split_pos in two parts:
5160   1) the left part has already a location assigned
5161   2) the right part is sorted into to the unhandled-list
5162 */
5163 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5164   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5165   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5166 
5167   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5168   assert(current_position() < min_split_pos, "cannot split before current position");
5169   assert(min_split_pos <= max_split_pos,     "invalid order");
5170   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5171 
5172   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5173 
5174   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5175   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5176   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5177 
5178   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5179     // the split position would be just before the end of the interval
5180     // -> no split at all necessary
5181     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5182     return;
5183   }
5184 
5185   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5186   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5187 
5188   if (!allocator()->is_block_begin(optimal_split_pos)) {
5189     // move position before actual instruction (odd op_id)
5190     optimal_split_pos = (optimal_split_pos - 1) | 1;
5191   }
5192 
5193   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5194   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5195   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5196 
5197   Interval* split_part = it->split(optimal_split_pos);
5198 
5199   allocator()->append_interval(split_part);
5200   allocator()->copy_register_flags(it, split_part);
5201   split_part->set_insert_move_when_activated(move_necessary);
5202   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5203 
5204   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5205   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5206   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5207 }
5208 
5209 /*
5210   split an interval at the optimal position between min_split_pos and
5211   max_split_pos in two parts:
5212   1) the left part has already a location assigned
5213   2) the right part is always on the stack and therefore ignored in further processing
5214 */
5215 void LinearScanWalker::split_for_spilling(Interval* it) {
5216   // calculate allowed range of splitting position
5217   int max_split_pos = current_position();
5218   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5219 
5220   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5221   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5222 
5223   assert(it->state() == activeState,     "why spill interval that is not active?");
5224   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5225   assert(min_split_pos <= max_split_pos, "invalid order");
5226   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5227   assert(current_position() < it->to(),  "interval must not end before current position");
5228 
5229   if (min_split_pos == it->from()) {
5230     // the whole interval is never used, so spill it entirely to memory
5231     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5232     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5233 
5234     allocator()->assign_spill_slot(it);
5235     allocator()->change_spill_state(it, min_split_pos);
5236 
5237     // Also kick parent intervals out of register to memory when they have no use
5238     // position. This avoids short interval in register surrounded by intervals in
5239     // memory -> avoid useless moves from memory to register and back
5240     Interval* parent = it;
5241     while (parent != NULL && parent->is_split_child()) {
5242       parent = parent->split_child_before_op_id(parent->from());
5243 
5244       if (parent->assigned_reg() < LinearScan::nof_regs) {
5245         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5246           // parent is never used, so kick it out of its assigned register
5247           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5248           allocator()->assign_spill_slot(parent);
5249         } else {
5250           // do not go further back because the register is actually used by the interval
5251           parent = NULL;
5252         }
5253       }
5254     }
5255 
5256   } else {
5257     // search optimal split pos, split interval and spill only the right hand part
5258     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5259 
5260     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5261     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5262     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5263 
5264     if (!allocator()->is_block_begin(optimal_split_pos)) {
5265       // move position before actual instruction (odd op_id)
5266       optimal_split_pos = (optimal_split_pos - 1) | 1;
5267     }
5268 
5269     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5270     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5271     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5272 
5273     Interval* spilled_part = it->split(optimal_split_pos);
5274     allocator()->append_interval(spilled_part);
5275     allocator()->assign_spill_slot(spilled_part);
5276     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5277 
5278     if (!allocator()->is_block_begin(optimal_split_pos)) {
5279       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5280       insert_move(optimal_split_pos, it, spilled_part);
5281     }
5282 
5283     // the current_split_child is needed later when moves are inserted for reloading
5284     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5285     spilled_part->make_current_split_child();
5286 
5287     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5288     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5289     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5290   }
5291 }
5292 
5293 
5294 void LinearScanWalker::split_stack_interval(Interval* it) {
5295   int min_split_pos = current_position() + 1;
5296   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5297 
5298   split_before_usage(it, min_split_pos, max_split_pos);
5299 }
5300 
5301 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5302   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5303   int max_split_pos = register_available_until;
5304 
5305   split_before_usage(it, min_split_pos, max_split_pos);
5306 }
5307 
5308 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5309   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5310 
5311   int current_pos = current_position();
5312   if (it->state() == inactiveState) {
5313     // the interval is currently inactive, so no spill slot is needed for now.
5314     // when the split part is activated, the interval has a new chance to get a register,
5315     // so in the best case no stack slot is necessary
5316     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5317     split_before_usage(it, current_pos + 1, current_pos + 1);
5318 
5319   } else {
5320     // search the position where the interval must have a register and split
5321     // at the optimal position before.
5322     // The new created part is added to the unhandled list and will get a register
5323     // when it is activated
5324     int min_split_pos = current_pos + 1;
5325     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5326 
5327     split_before_usage(it, min_split_pos, max_split_pos);
5328 
5329     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5330     split_for_spilling(it);
5331   }
5332 }
5333 
5334 
5335 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5336   int min_full_reg = any_reg;
5337   int max_partial_reg = any_reg;
5338 
5339   for (int i = _first_reg; i <= _last_reg; i++) {
5340     if (i == ignore_reg) {
5341       // this register must be ignored
5342 
5343     } else if (_use_pos[i] >= interval_to) {
5344       // this register is free for the full interval
5345       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5346         min_full_reg = i;
5347       }
5348     } else if (_use_pos[i] > reg_needed_until) {
5349       // this register is at least free until reg_needed_until
5350       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5351         max_partial_reg = i;
5352       }
5353     }
5354   }
5355 
5356   if (min_full_reg != any_reg) {
5357     return min_full_reg;
5358   } else if (max_partial_reg != any_reg) {
5359     *need_split = true;
5360     return max_partial_reg;
5361   } else {
5362     return any_reg;
5363   }
5364 }
5365 
5366 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5367   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5368 
5369   int min_full_reg = any_reg;
5370   int max_partial_reg = any_reg;
5371 
5372   for (int i = _first_reg; i < _last_reg; i+=2) {
5373     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5374       // this register is free for the full interval
5375       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5376         min_full_reg = i;
5377       }
5378     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5379       // this register is at least free until reg_needed_until
5380       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5381         max_partial_reg = i;
5382       }
5383     }
5384   }
5385 
5386   if (min_full_reg != any_reg) {
5387     return min_full_reg;
5388   } else if (max_partial_reg != any_reg) {
5389     *need_split = true;
5390     return max_partial_reg;
5391   } else {
5392     return any_reg;
5393   }
5394 }
5395 
5396 
5397 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5398   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5399 
5400   init_use_lists(true);
5401   free_exclude_active_fixed();
5402   free_exclude_active_any();
5403   free_collect_inactive_fixed(cur);
5404   free_collect_inactive_any(cur);
5405 //  free_collect_unhandled(fixedKind, cur);
5406   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5407 
5408   // _use_pos contains the start of the next interval that has this register assigned
5409   // (either as a fixed register or a normal allocated register in the past)
5410   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5411   TRACE_LINEAR_SCAN(4, tty->print_cr("      state of registers:"));
5412   TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr("      reg %d: use_pos: %d", i, _use_pos[i]));
5413 
5414   int hint_reg, hint_regHi;
5415   Interval* register_hint = cur->register_hint();
5416   if (register_hint != NULL) {
5417     hint_reg = register_hint->assigned_reg();
5418     hint_regHi = register_hint->assigned_regHi();
5419 
5420     if (allocator()->is_precolored_cpu_interval(register_hint)) {
5421       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5422       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5423     }
5424     TRACE_LINEAR_SCAN(4, tty->print("      hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5425 
5426   } else {
5427     hint_reg = any_reg;
5428     hint_regHi = any_reg;
5429   }
5430   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5431   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5432 
5433   // the register must be free at least until this position
5434   int reg_needed_until = cur->from() + 1;
5435   int interval_to = cur->to();
5436 
5437   bool need_split = false;
5438   int split_pos = -1;
5439   int reg = any_reg;
5440   int regHi = any_reg;
5441 
5442   if (_adjacent_regs) {
5443     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5444     regHi = reg + 1;
5445     if (reg == any_reg) {
5446       return false;
5447     }
5448     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5449 
5450   } else {
5451     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5452     if (reg == any_reg) {
5453       return false;
5454     }
5455     split_pos = _use_pos[reg];
5456 
5457     if (_num_phys_regs == 2) {
5458       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5459 
5460       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5461         // do not split interval if only one register can be assigned until the split pos
5462         // (when one register is found for the whole interval, split&spill is only
5463         // performed for the hi register)
5464         return false;
5465 
5466       } else if (regHi != any_reg) {
5467         split_pos = MIN2(split_pos, _use_pos[regHi]);
5468 
5469         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5470         if (reg > regHi) {
5471           int temp = reg;
5472           reg = regHi;
5473           regHi = temp;
5474         }
5475       }
5476     }
5477   }
5478 
5479   cur->assign_reg(reg, regHi);
5480   TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5481 
5482   assert(split_pos > 0, "invalid split_pos");
5483   if (need_split) {
5484     // register not available for full interval, so split it
5485     split_when_partial_register_available(cur, split_pos);
5486   }
5487 
5488   // only return true if interval is completely assigned
5489   return _num_phys_regs == 1 || regHi != any_reg;
5490 }
5491 
5492 
5493 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5494   int max_reg = any_reg;
5495 
5496   for (int i = _first_reg; i <= _last_reg; i++) {
5497     if (i == ignore_reg) {
5498       // this register must be ignored
5499 
5500     } else if (_use_pos[i] > reg_needed_until) {
5501       if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5502         max_reg = i;
5503       }
5504     }
5505   }
5506 
5507   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5508     *need_split = true;
5509   }
5510 
5511   return max_reg;
5512 }
5513 
5514 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5515   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5516 
5517   int max_reg = any_reg;
5518 
5519   for (int i = _first_reg; i < _last_reg; i+=2) {
5520     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5521       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5522         max_reg = i;
5523       }
5524     }
5525   }
5526 
5527   if (max_reg != any_reg &&
5528       (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5529     *need_split = true;
5530   }
5531 
5532   return max_reg;
5533 }
5534 
5535 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5536   assert(reg != any_reg, "no register assigned");
5537 
5538   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5539     Interval* it = _spill_intervals[reg]->at(i);
5540     remove_from_list(it);
5541     split_and_spill_interval(it);
5542   }
5543 
5544   if (regHi != any_reg) {
5545     IntervalList* processed = _spill_intervals[reg];
5546     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5547       Interval* it = _spill_intervals[regHi]->at(i);
5548       if (processed->find(it) == -1) {
5549         remove_from_list(it);
5550         split_and_spill_interval(it);
5551       }
5552     }
5553   }
5554 }
5555 
5556 
5557 // Split an Interval and spill it to memory so that cur can be placed in a register
5558 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5559   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5560 
5561   // collect current usage of registers
5562   init_use_lists(false);
5563   spill_exclude_active_fixed();
5564 //  spill_block_unhandled_fixed(cur);
5565   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5566   spill_block_inactive_fixed(cur);
5567   spill_collect_active_any();
5568   spill_collect_inactive_any(cur);
5569 
5570 #ifndef PRODUCT
5571   if (TraceLinearScanLevel >= 4) {
5572     tty->print_cr("      state of registers:");
5573     for (int i = _first_reg; i <= _last_reg; i++) {
5574       tty->print("      reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5575       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5576         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5577       }
5578       tty->cr();
5579     }
5580   }
5581 #endif
5582 
5583   // the register must be free at least until this position
5584   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5585   int interval_to = cur->to();
5586   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5587 
5588   int split_pos = 0;
5589   int use_pos = 0;
5590   bool need_split = false;
5591   int reg, regHi;
5592 
5593   if (_adjacent_regs) {
5594     reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5595     regHi = reg + 1;
5596 
5597     if (reg != any_reg) {
5598       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5599       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5600     }
5601   } else {
5602     reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5603     regHi = any_reg;
5604 
5605     if (reg != any_reg) {
5606       use_pos = _use_pos[reg];
5607       split_pos = _block_pos[reg];
5608 
5609       if (_num_phys_regs == 2) {
5610         if (cur->assigned_reg() != any_reg) {
5611           regHi = reg;
5612           reg = cur->assigned_reg();
5613         } else {
5614           regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5615           if (regHi != any_reg) {
5616             use_pos = MIN2(use_pos, _use_pos[regHi]);
5617             split_pos = MIN2(split_pos, _block_pos[regHi]);
5618           }
5619         }
5620 
5621         if (regHi != any_reg && reg > regHi) {
5622           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5623           int temp = reg;
5624           reg = regHi;
5625           regHi = temp;
5626         }
5627       }
5628     }
5629   }
5630 
5631   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5632     // the first use of cur is later than the spilling position -> spill cur
5633     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5634 
5635     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5636       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5637       // assign a reasonable register and do a bailout in product mode to avoid errors
5638       allocator()->assign_spill_slot(cur);
5639       BAILOUT("LinearScan: no register found");
5640     }
5641 
5642     split_and_spill_interval(cur);
5643   } else {
5644     TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5645     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5646     assert(split_pos > 0, "invalid split_pos");
5647     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5648 
5649     cur->assign_reg(reg, regHi);
5650     if (need_split) {
5651       // register not available for full interval, so split it
5652       split_when_partial_register_available(cur, split_pos);
5653     }
5654 
5655     // perform splitting and spilling for all affected intervalls
5656     split_and_spill_intersecting_intervals(reg, regHi);
5657   }
5658 }
5659 
5660 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5661 #ifdef X86
5662   // fast calculation of intervals that can never get a register because the
5663   // the next instruction is a call that blocks all registers
5664   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5665 
5666   // check if this interval is the result of a split operation
5667   // (an interval got a register until this position)
5668   int pos = cur->from();
5669   if ((pos & 1) == 1) {
5670     // the current instruction is a call that blocks all registers
5671     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5672       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5673 
5674       // safety check that there is really no register available
5675       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5676       return true;
5677     }
5678 
5679   }
5680 #endif
5681   return false;
5682 }
5683 
5684 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5685   BasicType type = cur->type();
5686   _num_phys_regs = LinearScan::num_physical_regs(type);
5687   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5688 
5689   if (pd_init_regs_for_alloc(cur)) {
5690     // the appropriate register range was selected.
5691   } else if (type == T_FLOAT || type == T_DOUBLE) {
5692     _first_reg = pd_first_fpu_reg;
5693     _last_reg = pd_last_fpu_reg;
5694   } else {
5695     _first_reg = pd_first_cpu_reg;
5696     _last_reg = FrameMap::last_cpu_reg();
5697   }
5698 
5699   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5700   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5701 }
5702 
5703 
5704 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5705   if (op->code() != lir_move) {
5706     return false;
5707   }
5708   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5709 
5710   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5711   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5712   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5713 }
5714 
5715 // optimization (especially for phi functions of nested loops):
5716 // assign same spill slot to non-intersecting intervals
5717 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5718   if (cur->is_split_child()) {
5719     // optimization is only suitable for split parents
5720     return;
5721   }
5722 
5723   Interval* register_hint = cur->register_hint(false);
5724   if (register_hint == NULL) {
5725     // cur is not the target of a move, otherwise register_hint would be set
5726     return;
5727   }
5728   assert(register_hint->is_split_parent(), "register hint must be split parent");
5729 
5730   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5731     // combining the stack slots for intervals where spill move optimization is applied
5732     // is not benefitial and would cause problems
5733     return;
5734   }
5735 
5736   int begin_pos = cur->from();
5737   int end_pos = cur->to();
5738   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5739     // safety check that lir_op_with_id is allowed
5740     return;
5741   }
5742 
5743   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5744     // cur and register_hint are not connected with two moves
5745     return;
5746   }
5747 
5748   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5749   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5750   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5751     // register_hint must be split, otherwise the re-writing of use positions does not work
5752     return;
5753   }
5754 
5755   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5756   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5757   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5758   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5759 
5760   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5761     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5762     return;
5763   }
5764   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5765 
5766   // modify intervals such that cur gets the same stack slot as register_hint
5767   // delete use positions to prevent the intervals to get a register at beginning
5768   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5769   cur->remove_first_use_pos();
5770   end_hint->remove_first_use_pos();
5771 }
5772 
5773 
5774 // allocate a physical register or memory location to an interval
5775 bool LinearScanWalker::activate_current() {
5776   Interval* cur = current();
5777   bool result = true;
5778 
5779   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5780   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5781 
5782   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5783     // activating an interval that has a stack slot assigned -> split it at first use position
5784     // used for method parameters
5785     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5786 
5787     split_stack_interval(cur);
5788     result = false;
5789 
5790   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5791     // activating an interval that must start in a stack slot, but may get a register later
5792     // used for lir_roundfp: rounding is done by store to stack and reload later
5793     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5794     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5795 
5796     allocator()->assign_spill_slot(cur);
5797     split_stack_interval(cur);
5798     result = false;
5799 
5800   } else if (cur->assigned_reg() == any_reg) {
5801     // interval has not assigned register -> normal allocation
5802     // (this is the normal case for most intervals)
5803     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5804 
5805     // assign same spill slot to non-intersecting intervals
5806     combine_spilled_intervals(cur);
5807 
5808     init_vars_for_alloc(cur);
5809     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5810       // no empty register available.
5811       // split and spill another interval so that this interval gets a register
5812       alloc_locked_reg(cur);
5813     }
5814 
5815     // spilled intervals need not be move to active-list
5816     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5817       result = false;
5818     }
5819   }
5820 
5821   // load spilled values that become active from stack slot to register
5822   if (cur->insert_move_when_activated()) {
5823     assert(cur->is_split_child(), "must be");
5824     assert(cur->current_split_child() != NULL, "must be");
5825     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5826     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5827 
5828     insert_move(cur->from(), cur->current_split_child(), cur);
5829   }
5830   cur->make_current_split_child();
5831 
5832   return result; // true = interval is moved to active list
5833 }
5834 
5835 
5836 // Implementation of EdgeMoveOptimizer
5837 
5838 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5839   _edge_instructions(4),
5840   _edge_instructions_idx(4)
5841 {
5842 }
5843 
5844 void EdgeMoveOptimizer::optimize(BlockList* code) {
5845   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5846 
5847   // ignore the first block in the list (index 0 is not processed)
5848   for (int i = code->length() - 1; i >= 1; i--) {
5849     BlockBegin* block = code->at(i);
5850 
5851     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5852       optimizer.optimize_moves_at_block_end(block);
5853     }
5854     if (block->number_of_sux() == 2) {
5855       optimizer.optimize_moves_at_block_begin(block);
5856     }
5857   }
5858 }
5859 
5860 
5861 // clear all internal data structures
5862 void EdgeMoveOptimizer::init_instructions() {
5863   _edge_instructions.clear();
5864   _edge_instructions_idx.clear();
5865 }
5866 
5867 // append a lir-instruction-list and the index of the current operation in to the list
5868 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5869   _edge_instructions.append(instructions);
5870   _edge_instructions_idx.append(instructions_idx);
5871 }
5872 
5873 // return the current operation of the given edge (predecessor or successor)
5874 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5875   LIR_OpList* instructions = _edge_instructions.at(edge);
5876   int idx = _edge_instructions_idx.at(edge);
5877 
5878   if (idx < instructions->length()) {
5879     return instructions->at(idx);
5880   } else {
5881     return NULL;
5882   }
5883 }
5884 
5885 // removes the current operation of the given edge (predecessor or successor)
5886 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5887   LIR_OpList* instructions = _edge_instructions.at(edge);
5888   int idx = _edge_instructions_idx.at(edge);
5889   instructions->remove_at(idx);
5890 
5891   if (decrement_index) {
5892     _edge_instructions_idx.at_put(edge, idx - 1);
5893   }
5894 }
5895 
5896 
5897 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5898   if (op1 == NULL || op2 == NULL) {
5899     // at least one block is already empty -> no optimization possible
5900     return true;
5901   }
5902 
5903   if (op1->code() == lir_move && op2->code() == lir_move) {
5904     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5905     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5906     LIR_Op1* move1 = (LIR_Op1*)op1;
5907     LIR_Op1* move2 = (LIR_Op1*)op2;
5908     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5909       // these moves are exactly equal and can be optimized
5910       return false;
5911     }
5912 
5913   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5914     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5915     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5916     LIR_Op1* fxch1 = (LIR_Op1*)op1;
5917     LIR_Op1* fxch2 = (LIR_Op1*)op2;
5918     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5919       // equal FPU stack operations can be optimized
5920       return false;
5921     }
5922 
5923   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5924     // equal FPU stack operations can be optimized
5925     return false;
5926   }
5927 
5928   // no optimization possible
5929   return true;
5930 }
5931 
5932 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5933   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5934 
5935   if (block->is_predecessor(block)) {
5936     // currently we can't handle this correctly.
5937     return;
5938   }
5939 
5940   init_instructions();
5941   int num_preds = block->number_of_preds();
5942   assert(num_preds > 1, "do not call otherwise");
5943   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5944 
5945   // setup a list with the lir-instructions of all predecessors
5946   int i;
5947   for (i = 0; i < num_preds; i++) {
5948     BlockBegin* pred = block->pred_at(i);
5949     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5950 
5951     if (pred->number_of_sux() != 1) {
5952       // this can happen with switch-statements where multiple edges are between
5953       // the same blocks.
5954       return;
5955     }
5956 
5957     assert(pred->number_of_sux() == 1, "can handle only one successor");
5958     assert(pred->sux_at(0) == block, "invalid control flow");
5959     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5960     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5961     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5962 
5963     if (pred_instructions->last()->info() != NULL) {
5964       // can not optimize instructions when debug info is needed
5965       return;
5966     }
5967 
5968     // ignore the unconditional branch at the end of the block
5969     append_instructions(pred_instructions, pred_instructions->length() - 2);
5970   }
5971 
5972 
5973   // process lir-instructions while all predecessors end with the same instruction
5974   while (true) {
5975     LIR_Op* op = instruction_at(0);
5976     for (i = 1; i < num_preds; i++) {
5977       if (operations_different(op, instruction_at(i))) {
5978         // these instructions are different and cannot be optimized ->
5979         // no further optimization possible
5980         return;
5981       }
5982     }
5983 
5984     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5985 
5986     // insert the instruction at the beginning of the current block
5987     block->lir()->insert_before(1, op);
5988 
5989     // delete the instruction at the end of all predecessors
5990     for (i = 0; i < num_preds; i++) {
5991       remove_cur_instruction(i, true);
5992     }
5993   }
5994 }
5995 
5996 
5997 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5998   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5999 
6000   init_instructions();
6001   int num_sux = block->number_of_sux();
6002 
6003   LIR_OpList* cur_instructions = block->lir()->instructions_list();
6004 
6005   assert(num_sux == 2, "method should not be called otherwise");
6006   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6007   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6008   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6009 
6010   if (cur_instructions->last()->info() != NULL) {
6011     // can no optimize instructions when debug info is needed
6012     return;
6013   }
6014 
6015   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6016   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6017     // not a valid case for optimization
6018     // currently, only blocks that end with two branches (conditional branch followed
6019     // by unconditional branch) are optimized
6020     return;
6021   }
6022 
6023   // now it is guaranteed that the block ends with two branch instructions.
6024   // the instructions are inserted at the end of the block before these two branches
6025   int insert_idx = cur_instructions->length() - 2;
6026 
6027   int i;
6028 #ifdef ASSERT
6029   for (i = insert_idx - 1; i >= 0; i--) {
6030     LIR_Op* op = cur_instructions->at(i);
6031     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6032       assert(false, "block with two successors can have only two branch instructions");
6033     }
6034   }
6035 #endif
6036 
6037   // setup a list with the lir-instructions of all successors
6038   for (i = 0; i < num_sux; i++) {
6039     BlockBegin* sux = block->sux_at(i);
6040     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6041 
6042     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6043 
6044     if (sux->number_of_preds() != 1) {
6045       // this can happen with switch-statements where multiple edges are between
6046       // the same blocks.
6047       return;
6048     }
6049     assert(sux->pred_at(0) == block, "invalid control flow");
6050     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6051 
6052     // ignore the label at the beginning of the block
6053     append_instructions(sux_instructions, 1);
6054   }
6055 
6056   // process lir-instructions while all successors begin with the same instruction
6057   while (true) {
6058     LIR_Op* op = instruction_at(0);
6059     for (i = 1; i < num_sux; i++) {
6060       if (operations_different(op, instruction_at(i))) {
6061         // these instructions are different and cannot be optimized ->
6062         // no further optimization possible
6063         return;
6064       }
6065     }
6066 
6067     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6068 
6069     // insert instruction at end of current block
6070     block->lir()->insert_before(insert_idx, op);
6071     insert_idx++;
6072 
6073     // delete the instructions at the beginning of all successors
6074     for (i = 0; i < num_sux; i++) {
6075       remove_cur_instruction(i, false);
6076     }
6077   }
6078 }
6079 
6080 
6081 // Implementation of ControlFlowOptimizer
6082 
6083 ControlFlowOptimizer::ControlFlowOptimizer() :
6084   _original_preds(4)
6085 {
6086 }
6087 
6088 void ControlFlowOptimizer::optimize(BlockList* code) {
6089   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6090 
6091   // push the OSR entry block to the end so that we're not jumping over it.
6092   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6093   if (osr_entry) {
6094     int index = osr_entry->linear_scan_number();
6095     assert(code->at(index) == osr_entry, "wrong index");
6096     code->remove_at(index);
6097     code->append(osr_entry);
6098   }
6099 
6100   optimizer.reorder_short_loops(code);
6101   optimizer.delete_empty_blocks(code);
6102   optimizer.delete_unnecessary_jumps(code);
6103   optimizer.delete_jumps_to_return(code);
6104 }
6105 
6106 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6107   int i = header_idx + 1;
6108   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6109   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6110     i++;
6111   }
6112 
6113   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6114     int end_idx = i - 1;
6115     BlockBegin* end_block = code->at(end_idx);
6116 
6117     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6118       // short loop from header_idx to end_idx found -> reorder blocks such that
6119       // the header_block is the last block instead of the first block of the loop
6120       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6121                                          end_idx - header_idx + 1,
6122                                          header_block->block_id(), end_block->block_id()));
6123 
6124       for (int j = header_idx; j < end_idx; j++) {
6125         code->at_put(j, code->at(j + 1));
6126       }
6127       code->at_put(end_idx, header_block);
6128 
6129       // correct the flags so that any loop alignment occurs in the right place.
6130       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6131       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6132       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6133     }
6134   }
6135 }
6136 
6137 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6138   for (int i = code->length() - 1; i >= 0; i--) {
6139     BlockBegin* block = code->at(i);
6140 
6141     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6142       reorder_short_loop(code, block, i);
6143     }
6144   }
6145 
6146   DEBUG_ONLY(verify(code));
6147 }
6148 
6149 // only blocks with exactly one successor can be deleted. Such blocks
6150 // must always end with an unconditional branch to this successor
6151 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6152   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6153     return false;
6154   }
6155 
6156   LIR_OpList* instructions = block->lir()->instructions_list();
6157 
6158   assert(instructions->length() >= 2, "block must have label and branch");
6159   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6160   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6161   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6162   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6163 
6164   // block must have exactly one successor
6165 
6166   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6167     return true;
6168   }
6169   return false;
6170 }
6171 
6172 // substitute branch targets in all branch-instructions of this blocks
6173 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6174   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6175 
6176   LIR_OpList* instructions = block->lir()->instructions_list();
6177 
6178   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6179   for (int i = instructions->length() - 1; i >= 1; i--) {
6180     LIR_Op* op = instructions->at(i);
6181 
6182     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6183       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6184       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6185 
6186       if (branch->block() == target_from) {
6187         branch->change_block(target_to);
6188       }
6189       if (branch->ublock() == target_from) {
6190         branch->change_ublock(target_to);
6191       }
6192     }
6193   }
6194 }
6195 
6196 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6197   int old_pos = 0;
6198   int new_pos = 0;
6199   int num_blocks = code->length();
6200 
6201   while (old_pos < num_blocks) {
6202     BlockBegin* block = code->at(old_pos);
6203 
6204     if (can_delete_block(block)) {
6205       BlockBegin* new_target = block->sux_at(0);
6206 
6207       // propagate backward branch target flag for correct code alignment
6208       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6209         new_target->set(BlockBegin::backward_branch_target_flag);
6210       }
6211 
6212       // collect a list with all predecessors that contains each predecessor only once
6213       // the predecessors of cur are changed during the substitution, so a copy of the
6214       // predecessor list is necessary
6215       int j;
6216       _original_preds.clear();
6217       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6218         BlockBegin* pred = block->pred_at(j);
6219         if (_original_preds.find(pred) == -1) {
6220           _original_preds.append(pred);
6221         }
6222       }
6223 
6224       for (j = _original_preds.length() - 1; j >= 0; j--) {
6225         BlockBegin* pred = _original_preds.at(j);
6226         substitute_branch_target(pred, block, new_target);
6227         pred->substitute_sux(block, new_target);
6228       }
6229     } else {
6230       // adjust position of this block in the block list if blocks before
6231       // have been deleted
6232       if (new_pos != old_pos) {
6233         code->at_put(new_pos, code->at(old_pos));
6234       }
6235       new_pos++;
6236     }
6237     old_pos++;
6238   }
6239   code->trunc_to(new_pos);
6240 
6241   DEBUG_ONLY(verify(code));
6242 }
6243 
6244 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6245   // skip the last block because there a branch is always necessary
6246   for (int i = code->length() - 2; i >= 0; i--) {
6247     BlockBegin* block = code->at(i);
6248     LIR_OpList* instructions = block->lir()->instructions_list();
6249 
6250     LIR_Op* last_op = instructions->last();
6251     if (last_op->code() == lir_branch) {
6252       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6253       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6254 
6255       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6256       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6257 
6258       if (last_branch->info() == NULL) {
6259         if (last_branch->block() == code->at(i + 1)) {
6260 
6261           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6262 
6263           // delete last branch instruction
6264           instructions->trunc_to(instructions->length() - 1);
6265 
6266         } else {
6267           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6268           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6269             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6270             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6271 
6272             if (prev_branch->stub() == NULL) {
6273 
6274               LIR_Op2* prev_cmp = NULL;
6275               // There might be a cmove inserted for profiling which depends on the same
6276               // compare. If we change the condition of the respective compare, we have
6277               // to take care of this cmove as well.
6278               LIR_Op2* prev_cmove = NULL;
6279 
6280               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6281                 prev_op = instructions->at(j);
6282                 // check for the cmove
6283                 if (prev_op->code() == lir_cmove) {
6284                   assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
6285                   prev_cmove = (LIR_Op2*)prev_op;
6286                   assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6287                 }
6288                 if (prev_op->code() == lir_cmp) {
6289                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6290                   prev_cmp = (LIR_Op2*)prev_op;
6291                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6292                 }
6293               }
6294               assert(prev_cmp != NULL, "should have found comp instruction for branch");
6295               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6296 
6297                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6298 
6299                 // eliminate a conditional branch to the immediate successor
6300                 prev_branch->change_block(last_branch->block());
6301                 prev_branch->negate_cond();
6302                 prev_cmp->set_condition(prev_branch->cond());
6303                 instructions->trunc_to(instructions->length() - 1);
6304                 // if we do change the condition, we have to change the cmove as well
6305                 if (prev_cmove != NULL) {
6306                   prev_cmove->set_condition(prev_branch->cond());
6307                   LIR_Opr t = prev_cmove->in_opr1();
6308                   prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6309                   prev_cmove->set_in_opr2(t);
6310                 }
6311               }
6312             }
6313           }
6314         }
6315       }
6316     }
6317   }
6318 
6319   DEBUG_ONLY(verify(code));
6320 }
6321 
6322 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6323 #ifdef ASSERT
6324   ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6325 #endif
6326 
6327   for (int i = code->length() - 1; i >= 0; i--) {
6328     BlockBegin* block = code->at(i);
6329     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6330     LIR_Op*     cur_last_op = cur_instructions->last();
6331 
6332     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6333     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6334       // the block contains only a label and a return
6335       // if a predecessor ends with an unconditional jump to this block, then the jump
6336       // can be replaced with a return instruction
6337       //
6338       // Note: the original block with only a return statement cannot be deleted completely
6339       //       because the predecessors might have other (conditional) jumps to this block
6340       //       -> this may lead to unnecesary return instructions in the final code
6341 
6342       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6343       assert(block->number_of_sux() == 0 ||
6344              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6345              "blocks that end with return must not have successors");
6346 
6347       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6348       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6349 
6350       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6351         BlockBegin* pred = block->pred_at(j);
6352         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6353         LIR_Op*     pred_last_op = pred_instructions->last();
6354 
6355         if (pred_last_op->code() == lir_branch) {
6356           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6357           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6358 
6359           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6360             // replace the jump to a return with a direct return
6361             // Note: currently the edge between the blocks is not deleted
6362             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6363 #ifdef ASSERT
6364             return_converted.set_bit(pred->block_id());
6365 #endif
6366           }
6367         }
6368       }
6369     }
6370   }
6371 }
6372 
6373 
6374 #ifdef ASSERT
6375 void ControlFlowOptimizer::verify(BlockList* code) {
6376   for (int i = 0; i < code->length(); i++) {
6377     BlockBegin* block = code->at(i);
6378     LIR_OpList* instructions = block->lir()->instructions_list();
6379 
6380     int j;
6381     for (j = 0; j < instructions->length(); j++) {
6382       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6383 
6384       if (op_branch != NULL) {
6385         assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6386         assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6387       }
6388     }
6389 
6390     for (j = 0; j < block->number_of_sux() - 1; j++) {
6391       BlockBegin* sux = block->sux_at(j);
6392       assert(code->find(sux) != -1, "successor not valid");
6393     }
6394 
6395     for (j = 0; j < block->number_of_preds() - 1; j++) {
6396       BlockBegin* pred = block->pred_at(j);
6397       assert(code->find(pred) != -1, "successor not valid");
6398     }
6399   }
6400 }
6401 #endif
6402 
6403 
6404 #ifndef PRODUCT
6405 
6406 // Implementation of LinearStatistic
6407 
6408 const char* LinearScanStatistic::counter_name(int counter_idx) {
6409   switch (counter_idx) {
6410     case counter_method:          return "compiled methods";
6411     case counter_fpu_method:      return "methods using fpu";
6412     case counter_loop_method:     return "methods with loops";
6413     case counter_exception_method:return "methods with xhandler";
6414 
6415     case counter_loop:            return "loops";
6416     case counter_block:           return "blocks";
6417     case counter_loop_block:      return "blocks inside loop";
6418     case counter_exception_block: return "exception handler entries";
6419     case counter_interval:        return "intervals";
6420     case counter_fixed_interval:  return "fixed intervals";
6421     case counter_range:           return "ranges";
6422     case counter_fixed_range:     return "fixed ranges";
6423     case counter_use_pos:         return "use positions";
6424     case counter_fixed_use_pos:   return "fixed use positions";
6425     case counter_spill_slots:     return "spill slots";
6426 
6427     // counter for classes of lir instructions
6428     case counter_instruction:     return "total instructions";
6429     case counter_label:           return "labels";
6430     case counter_entry:           return "method entries";
6431     case counter_return:          return "method returns";
6432     case counter_call:            return "method calls";
6433     case counter_move:            return "moves";
6434     case counter_cmp:             return "compare";
6435     case counter_cond_branch:     return "conditional branches";
6436     case counter_uncond_branch:   return "unconditional branches";
6437     case counter_stub_branch:     return "branches to stub";
6438     case counter_alu:             return "artithmetic + logic";
6439     case counter_alloc:           return "allocations";
6440     case counter_sync:            return "synchronisation";
6441     case counter_throw:           return "throw";
6442     case counter_unwind:          return "unwind";
6443     case counter_typecheck:       return "type+null-checks";
6444     case counter_fpu_stack:       return "fpu-stack";
6445     case counter_misc_inst:       return "other instructions";
6446     case counter_other_inst:      return "misc. instructions";
6447 
6448     // counter for different types of moves
6449     case counter_move_total:      return "total moves";
6450     case counter_move_reg_reg:    return "register->register";
6451     case counter_move_reg_stack:  return "register->stack";
6452     case counter_move_stack_reg:  return "stack->register";
6453     case counter_move_stack_stack:return "stack->stack";
6454     case counter_move_reg_mem:    return "register->memory";
6455     case counter_move_mem_reg:    return "memory->register";
6456     case counter_move_const_any:  return "constant->any";
6457 
6458     case blank_line_1:            return "";
6459     case blank_line_2:            return "";
6460 
6461     default: ShouldNotReachHere(); return "";
6462   }
6463 }
6464 
6465 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6466   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6467     return counter_method;
6468   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6469     return counter_block;
6470   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6471     return counter_instruction;
6472   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6473     return counter_move_total;
6474   }
6475   return invalid_counter;
6476 }
6477 
6478 LinearScanStatistic::LinearScanStatistic() {
6479   for (int i = 0; i < number_of_counters; i++) {
6480     _counters_sum[i] = 0;
6481     _counters_max[i] = -1;
6482   }
6483 
6484 }
6485 
6486 // add the method-local numbers to the total sum
6487 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6488   for (int i = 0; i < number_of_counters; i++) {
6489     _counters_sum[i] += method_statistic._counters_sum[i];
6490     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6491   }
6492 }
6493 
6494 void LinearScanStatistic::print(const char* title) {
6495   if (CountLinearScan || TraceLinearScanLevel > 0) {
6496     tty->cr();
6497     tty->print_cr("***** LinearScan statistic - %s *****", title);
6498 
6499     for (int i = 0; i < number_of_counters; i++) {
6500       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6501         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6502 
6503         LinearScanStatistic::Counter cntr = base_counter(i);
6504         if (cntr != invalid_counter) {
6505           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6506         } else {
6507           tty->print("           ");
6508         }
6509 
6510         if (_counters_max[i] >= 0) {
6511           tty->print("%8d", _counters_max[i]);
6512         }
6513       }
6514       tty->cr();
6515     }
6516   }
6517 }
6518 
6519 void LinearScanStatistic::collect(LinearScan* allocator) {
6520   inc_counter(counter_method);
6521   if (allocator->has_fpu_registers()) {
6522     inc_counter(counter_fpu_method);
6523   }
6524   if (allocator->num_loops() > 0) {
6525     inc_counter(counter_loop_method);
6526   }
6527   inc_counter(counter_loop, allocator->num_loops());
6528   inc_counter(counter_spill_slots, allocator->max_spills());
6529 
6530   int i;
6531   for (i = 0; i < allocator->interval_count(); i++) {
6532     Interval* cur = allocator->interval_at(i);
6533 
6534     if (cur != NULL) {
6535       inc_counter(counter_interval);
6536       inc_counter(counter_use_pos, cur->num_use_positions());
6537       if (LinearScan::is_precolored_interval(cur)) {
6538         inc_counter(counter_fixed_interval);
6539         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6540       }
6541 
6542       Range* range = cur->first();
6543       while (range != Range::end()) {
6544         inc_counter(counter_range);
6545         if (LinearScan::is_precolored_interval(cur)) {
6546           inc_counter(counter_fixed_range);
6547         }
6548         range = range->next();
6549       }
6550     }
6551   }
6552 
6553   bool has_xhandlers = false;
6554   // Note: only count blocks that are in code-emit order
6555   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6556     BlockBegin* cur = allocator->ir()->code()->at(i);
6557 
6558     inc_counter(counter_block);
6559     if (cur->loop_depth() > 0) {
6560       inc_counter(counter_loop_block);
6561     }
6562     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6563       inc_counter(counter_exception_block);
6564       has_xhandlers = true;
6565     }
6566 
6567     LIR_OpList* instructions = cur->lir()->instructions_list();
6568     for (int j = 0; j < instructions->length(); j++) {
6569       LIR_Op* op = instructions->at(j);
6570 
6571       inc_counter(counter_instruction);
6572 
6573       switch (op->code()) {
6574         case lir_label:           inc_counter(counter_label); break;
6575         case lir_std_entry:
6576         case lir_osr_entry:       inc_counter(counter_entry); break;
6577         case lir_return:          inc_counter(counter_return); break;
6578 
6579         case lir_rtcall:
6580         case lir_static_call:
6581         case lir_optvirtual_call:
6582         case lir_virtual_call:    inc_counter(counter_call); break;
6583 
6584         case lir_move: {
6585           inc_counter(counter_move);
6586           inc_counter(counter_move_total);
6587 
6588           LIR_Opr in = op->as_Op1()->in_opr();
6589           LIR_Opr res = op->as_Op1()->result_opr();
6590           if (in->is_register()) {
6591             if (res->is_register()) {
6592               inc_counter(counter_move_reg_reg);
6593             } else if (res->is_stack()) {
6594               inc_counter(counter_move_reg_stack);
6595             } else if (res->is_address()) {
6596               inc_counter(counter_move_reg_mem);
6597             } else {
6598               ShouldNotReachHere();
6599             }
6600           } else if (in->is_stack()) {
6601             if (res->is_register()) {
6602               inc_counter(counter_move_stack_reg);
6603             } else {
6604               inc_counter(counter_move_stack_stack);
6605             }
6606           } else if (in->is_address()) {
6607             assert(res->is_register(), "must be");
6608             inc_counter(counter_move_mem_reg);
6609           } else if (in->is_constant()) {
6610             inc_counter(counter_move_const_any);
6611           } else {
6612             ShouldNotReachHere();
6613           }
6614           break;
6615         }
6616 
6617         case lir_cmp:             inc_counter(counter_cmp); break;
6618 
6619         case lir_branch:
6620         case lir_cond_float_branch: {
6621           LIR_OpBranch* branch = op->as_OpBranch();
6622           if (branch->block() == NULL) {
6623             inc_counter(counter_stub_branch);
6624           } else if (branch->cond() == lir_cond_always) {
6625             inc_counter(counter_uncond_branch);
6626           } else {
6627             inc_counter(counter_cond_branch);
6628           }
6629           break;
6630         }
6631 
6632         case lir_neg:
6633         case lir_add:
6634         case lir_sub:
6635         case lir_mul:
6636         case lir_mul_strictfp:
6637         case lir_div:
6638         case lir_div_strictfp:
6639         case lir_rem:
6640         case lir_sqrt:
6641         case lir_abs:
6642         case lir_log10:
6643         case lir_logic_and:
6644         case lir_logic_or:
6645         case lir_logic_xor:
6646         case lir_shl:
6647         case lir_shr:
6648         case lir_ushr:            inc_counter(counter_alu); break;
6649 
6650         case lir_alloc_object:
6651         case lir_alloc_array:     inc_counter(counter_alloc); break;
6652 
6653         case lir_monaddr:
6654         case lir_lock:
6655         case lir_unlock:          inc_counter(counter_sync); break;
6656 
6657         case lir_throw:           inc_counter(counter_throw); break;
6658 
6659         case lir_unwind:          inc_counter(counter_unwind); break;
6660 
6661         case lir_null_check:
6662         case lir_leal:
6663         case lir_instanceof:
6664         case lir_checkcast:
6665         case lir_store_check:     inc_counter(counter_typecheck); break;
6666 
6667         case lir_fpop_raw:
6668         case lir_fxch:
6669         case lir_fld:             inc_counter(counter_fpu_stack); break;
6670 
6671         case lir_nop:
6672         case lir_push:
6673         case lir_pop:
6674         case lir_convert:
6675         case lir_roundfp:
6676         case lir_cmove:           inc_counter(counter_misc_inst); break;
6677 
6678         default:                  inc_counter(counter_other_inst); break;
6679       }
6680     }
6681   }
6682 
6683   if (has_xhandlers) {
6684     inc_counter(counter_exception_method);
6685   }
6686 }
6687 
6688 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6689   if (CountLinearScan || TraceLinearScanLevel > 0) {
6690 
6691     LinearScanStatistic local_statistic = LinearScanStatistic();
6692 
6693     local_statistic.collect(allocator);
6694     global_statistic.sum_up(local_statistic);
6695 
6696     if (TraceLinearScanLevel > 2) {
6697       local_statistic.print("current local statistic");
6698     }
6699   }
6700 }
6701 
6702 
6703 // Implementation of LinearTimers
6704 
6705 LinearScanTimers::LinearScanTimers() {
6706   for (int i = 0; i < number_of_timers; i++) {
6707     timer(i)->reset();
6708   }
6709 }
6710 
6711 const char* LinearScanTimers::timer_name(int idx) {
6712   switch (idx) {
6713     case timer_do_nothing:               return "Nothing (Time Check)";
6714     case timer_number_instructions:      return "Number Instructions";
6715     case timer_compute_local_live_sets:  return "Local Live Sets";
6716     case timer_compute_global_live_sets: return "Global Live Sets";
6717     case timer_build_intervals:          return "Build Intervals";
6718     case timer_sort_intervals_before:    return "Sort Intervals Before";
6719     case timer_allocate_registers:       return "Allocate Registers";
6720     case timer_resolve_data_flow:        return "Resolve Data Flow";
6721     case timer_sort_intervals_after:     return "Sort Intervals After";
6722     case timer_eliminate_spill_moves:    return "Spill optimization";
6723     case timer_assign_reg_num:           return "Assign Reg Num";
6724     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6725     case timer_optimize_lir:             return "Optimize LIR";
6726     default: ShouldNotReachHere();       return "";
6727   }
6728 }
6729 
6730 void LinearScanTimers::begin_method() {
6731   if (TimeEachLinearScan) {
6732     // reset all timers to measure only current method
6733     for (int i = 0; i < number_of_timers; i++) {
6734       timer(i)->reset();
6735     }
6736   }
6737 }
6738 
6739 void LinearScanTimers::end_method(LinearScan* allocator) {
6740   if (TimeEachLinearScan) {
6741 
6742     double c = timer(timer_do_nothing)->seconds();
6743     double total = 0;
6744     for (int i = 1; i < number_of_timers; i++) {
6745       total += timer(i)->seconds() - c;
6746     }
6747 
6748     if (total >= 0.0005) {
6749       // print all information in one line for automatic processing
6750       tty->print("@"); allocator->compilation()->method()->print_name();
6751 
6752       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6753       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6754       tty->print("@ %d ", allocator->block_count());
6755       tty->print("@ %d ", allocator->num_virtual_regs());
6756       tty->print("@ %d ", allocator->interval_count());
6757       tty->print("@ %d ", allocator->_num_calls);
6758       tty->print("@ %d ", allocator->num_loops());
6759 
6760       tty->print("@ %6.6f ", total);
6761       for (int i = 1; i < number_of_timers; i++) {
6762         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6763       }
6764       tty->cr();
6765     }
6766   }
6767 }
6768 
6769 void LinearScanTimers::print(double total_time) {
6770   if (TimeLinearScan) {
6771     // correction value: sum of dummy-timer that only measures the time that
6772     // is necesary to start and stop itself
6773     double c = timer(timer_do_nothing)->seconds();
6774 
6775     for (int i = 0; i < number_of_timers; i++) {
6776       double t = timer(i)->seconds();
6777       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6778     }
6779   }
6780 }
6781 
6782 #endif // #ifndef PRODUCT