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src/share/vm/c1/c1_LinearScan.cpp

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rev 12113 : 8166561: [s390] Adaptions needed for s390 port in C1 and C2.


1060     if (result_in_memory) {
1061       // Move to an interval with must_start_in_memory set.
1062       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1063       return mustHaveRegister;
1064 
1065     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1066       // Move from register to register
1067       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1068         // special handling of phi-function moves inside osr-entry blocks
1069         // input operand must have a register instead of output operand (leads to better register allocation)
1070         return mustHaveRegister;
1071       }
1072 
1073       // The input operand is not forced to a register (moves from stack to register are allowed),
1074       // but it is faster if the input operand is in a register
1075       return shouldHaveRegister;
1076     }
1077   }
1078 
1079 
1080 #ifdef X86
1081   if (op->code() == lir_cmove) {
1082     // conditional moves can handle stack operands
1083     assert(op->result_opr()->is_register(), "result must always be in a register");
1084     return shouldHaveRegister;
1085   }
1086 
1087   // optimizations for second input operand of arithmehtic operations on Intel
1088   // this operand is allowed to be on the stack in some cases
1089   BasicType opr_type = opr->type_register();
1090   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091     if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1092       // SSE float instruction (T_DOUBLE only supported with SSE2)
1093       switch (op->code()) {
1094         case lir_cmp:
1095         case lir_add:
1096         case lir_sub:
1097         case lir_mul:
1098         case lir_div:
1099         {
1100           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1101           LIR_Op2* op2 = (LIR_Op2*)op;
1102           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1103             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1104             return shouldHaveRegister;
1105           }
1106         }
1107       }
1108     } else {
1109       // FPU stack float instruction
1110       switch (op->code()) {
1111         case lir_add:


1127     // T_OBJECT doesn't get spilled along with T_LONG.
1128   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1129     // integer instruction (note: long operands must always be in register)
1130     switch (op->code()) {
1131       case lir_cmp:
1132       case lir_add:
1133       case lir_sub:
1134       case lir_logic_and:
1135       case lir_logic_or:
1136       case lir_logic_xor:
1137       {
1138         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1139         LIR_Op2* op2 = (LIR_Op2*)op;
1140         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1141           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1142           return shouldHaveRegister;
1143         }
1144       }
1145     }
1146   }
1147 #endif // X86
1148 
1149   // all other operands require a register
1150   return mustHaveRegister;
1151 }
1152 
1153 
1154 void LinearScan::handle_method_arguments(LIR_Op* op) {
1155   // special handling for method arguments (moves from stack to virtual register):
1156   // the interval gets no register assigned, but the stack slot.
1157   // it is split before the first use by the register allocator.
1158 
1159   if (op->code() == lir_move) {
1160     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1161     LIR_Op1* move = (LIR_Op1*)op;
1162 
1163     if (move->in_opr()->is_stack()) {
1164 #ifdef ASSERT
1165       int arg_size = compilation()->method()->arg_size();
1166       LIR_Opr o = move->in_opr();
1167       if (o->is_single_stack()) {


2636     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2637 
2638     scope_values->append(sv);
2639     return 1;
2640 #endif
2641 
2642   } else if (opr->is_single_fpu()) {
2643 #ifdef X86
2644     // the exact location of fpu stack values is only known
2645     // during fpu stack allocation, so the stack allocator object
2646     // must be present
2647     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2648     assert(_fpu_stack_allocator != NULL, "must be present");
2649     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2650 #endif
2651 
2652     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2653     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2654 #ifndef __SOFTFP__
2655 #ifndef VM_LITTLE_ENDIAN





2656     if (! float_saved_as_double) {
2657       // On big endian system, we may have an issue if float registers use only
2658       // the low half of the (same) double registers.
2659       // Both the float and the double could have the same regnr but would correspond
2660       // to two different addresses once saved.
2661 
2662       // get next safely (no assertion checks)
2663       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2664       if (next->is_reg() &&
2665           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2666         // the back-end does use the same numbering for the double and the float
2667         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2668       }
2669     }

2670 #endif
2671 #endif
2672     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2673 
2674     scope_values->append(sv);
2675     return 1;
2676 
2677   } else {
2678     // double-size operands
2679 
2680     ScopeValue* first;
2681     ScopeValue* second;
2682 
2683     if (opr->is_double_stack()) {
2684 #ifdef _LP64
2685       Location loc1;
2686       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2687       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2688         bailout("too large frame");
2689       }




1060     if (result_in_memory) {
1061       // Move to an interval with must_start_in_memory set.
1062       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1063       return mustHaveRegister;
1064 
1065     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1066       // Move from register to register
1067       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1068         // special handling of phi-function moves inside osr-entry blocks
1069         // input operand must have a register instead of output operand (leads to better register allocation)
1070         return mustHaveRegister;
1071       }
1072 
1073       // The input operand is not forced to a register (moves from stack to register are allowed),
1074       // but it is faster if the input operand is in a register
1075       return shouldHaveRegister;
1076     }
1077   }
1078 
1079 
1080 #if defined(X86) || defined(S390)
1081   if (op->code() == lir_cmove) {
1082     // conditional moves can handle stack operands
1083     assert(op->result_opr()->is_register(), "result must always be in a register");
1084     return shouldHaveRegister;
1085   }
1086 
1087   // optimizations for second input operand of arithmehtic operations on Intel
1088   // this operand is allowed to be on the stack in some cases
1089   BasicType opr_type = opr->type_register();
1090   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091     if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 S390_ONLY(|| true)) {
1092       // SSE float instruction (T_DOUBLE only supported with SSE2)
1093       switch (op->code()) {
1094         case lir_cmp:
1095         case lir_add:
1096         case lir_sub:
1097         case lir_mul:
1098         case lir_div:
1099         {
1100           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1101           LIR_Op2* op2 = (LIR_Op2*)op;
1102           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1103             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1104             return shouldHaveRegister;
1105           }
1106         }
1107       }
1108     } else {
1109       // FPU stack float instruction
1110       switch (op->code()) {
1111         case lir_add:


1127     // T_OBJECT doesn't get spilled along with T_LONG.
1128   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1129     // integer instruction (note: long operands must always be in register)
1130     switch (op->code()) {
1131       case lir_cmp:
1132       case lir_add:
1133       case lir_sub:
1134       case lir_logic_and:
1135       case lir_logic_or:
1136       case lir_logic_xor:
1137       {
1138         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1139         LIR_Op2* op2 = (LIR_Op2*)op;
1140         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1141           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1142           return shouldHaveRegister;
1143         }
1144       }
1145     }
1146   }
1147 #endif // X86 S390
1148 
1149   // all other operands require a register
1150   return mustHaveRegister;
1151 }
1152 
1153 
1154 void LinearScan::handle_method_arguments(LIR_Op* op) {
1155   // special handling for method arguments (moves from stack to virtual register):
1156   // the interval gets no register assigned, but the stack slot.
1157   // it is split before the first use by the register allocator.
1158 
1159   if (op->code() == lir_move) {
1160     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1161     LIR_Op1* move = (LIR_Op1*)op;
1162 
1163     if (move->in_opr()->is_stack()) {
1164 #ifdef ASSERT
1165       int arg_size = compilation()->method()->arg_size();
1166       LIR_Opr o = move->in_opr();
1167       if (o->is_single_stack()) {


2636     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2637 
2638     scope_values->append(sv);
2639     return 1;
2640 #endif
2641 
2642   } else if (opr->is_single_fpu()) {
2643 #ifdef X86
2644     // the exact location of fpu stack values is only known
2645     // during fpu stack allocation, so the stack allocator object
2646     // must be present
2647     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2648     assert(_fpu_stack_allocator != NULL, "must be present");
2649     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2650 #endif
2651 
2652     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2653     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2654 #ifndef __SOFTFP__
2655 #ifndef VM_LITTLE_ENDIAN
2656     // On S390 a (single precision) float value occupies only the high
2657     // word of the full double register. So when the double register is
2658     // stored to memory (e.g. by the RegisterSaver), then the float value
2659     // is found at offset 0. I.e. the code below is not needed on S390.
2660 #ifndef S390
2661     if (! float_saved_as_double) {
2662       // On big endian system, we may have an issue if float registers use only
2663       // the low half of the (same) double registers.
2664       // Both the float and the double could have the same regnr but would correspond
2665       // to two different addresses once saved.
2666 
2667       // get next safely (no assertion checks)
2668       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2669       if (next->is_reg() &&
2670           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2671         // the back-end does use the same numbering for the double and the float
2672         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2673       }
2674     }
2675 #endif // !S390
2676 #endif
2677 #endif
2678     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2679 
2680     scope_values->append(sv);
2681     return 1;
2682 
2683   } else {
2684     // double-size operands
2685 
2686     ScopeValue* first;
2687     ScopeValue* second;
2688 
2689     if (opr->is_double_stack()) {
2690 #ifdef _LP64
2691       Location loc1;
2692       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2693       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2694         bailout("too large frame");
2695       }


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