src/cpu/s390/vm/s390.ad

rev 12273 : 8169317: [s390] Various minor bug fixes and adaptions.

*** 1487,1498 ****
    switch (opcode) {
      case Op_CountLeadingZerosI:
      case Op_CountLeadingZerosL:
      case Op_CountTrailingZerosI:
      case Op_CountTrailingZerosL:
!       // Implementation requires FLOGR instruction.
!       return UseCountLeadingZerosInstruction;
  
      case Op_ReverseBytesI:
      case Op_ReverseBytesL:
        return UseByteReverseInstruction;
  
--- 1487,1498 ----
    switch (opcode) {
      case Op_CountLeadingZerosI:
      case Op_CountLeadingZerosL:
      case Op_CountTrailingZerosI:
      case Op_CountTrailingZerosL:
!       // Implementation requires FLOGR instruction, which is available since z9.
!       return true;
  
      case Op_ReverseBytesI:
      case Op_ReverseBytesL:
        return UseByteReverseInstruction;
  
*** 9895,9905 ****
    ins_pipe(pipe_class_dummy);
  %}
  
  // String IndexOfChar
  instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
-   predicate(CompactStrings);
    match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
    effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
    ins_cost(200);
    format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
    ins_encode %{
--- 9895,9904 ----
*** 10588,10598 ****
  // returns position 64. That's exactly what we need.
  
  instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
    match(Set dst (CountLeadingZerosI src));
    effect(KILL tmp, KILL cr);
-   predicate(UseCountLeadingZerosInstruction);  // See Matcher::match_rule_supported
    ins_cost(3 * DEFAULT_COST);
    size(14);
    format %{ "SLLG    $dst,$src,32\t# no need to always count 32 zeroes first\n\t"
              "IILH    $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t"
              "FLOGR   $dst,$dst"
--- 10587,10596 ----
*** 10627,10637 ****
  %}
  
  instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
    match(Set dst (CountLeadingZerosL src));
    effect(KILL tmp, KILL cr);
-   predicate(UseCountLeadingZerosInstruction);  // See Matcher::match_rule_supported
    ins_cost(DEFAULT_COST);
    size(4);
    format %{ "FLOGR   $dst,$src \t# count leading zeros (long)\n\t" %}
    ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
    ins_pipe(pipe_class_dummy);
--- 10625,10634 ----
*** 10653,10663 ****
  // yields ones in the trailing zeroes positions and zeroes elsewhere.
  // Now we can apply FLOGR and get 64-(trailing zeroes).
  instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
    match(Set dst (CountTrailingZerosI src));
    effect(TEMP_DEF dst, TEMP tmp, KILL cr);
-   predicate(UseCountLeadingZerosInstruction);  // See Matcher::match_rule_supported
    ins_cost(8 * DEFAULT_COST);
    // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
    format %{ "LLGFR   $dst,$src  \t# clear upper 32 bits (we are dealing with int)\n\t"
              "LCGFR   $tmp,$src  \t# load 2's complement (32->64 bit)\n\t"
              "AGHI    $dst,-1    \t# tmp1 = src-1\n\t"
--- 10650,10659 ----
*** 10707,10717 ****
  %}
  
  instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
    match(Set dst (CountTrailingZerosL src));
    effect(TEMP_DEF dst, KILL tmp, KILL cr);
-   predicate(UseCountLeadingZerosInstruction);  // See Matcher::match_rule_supported
    ins_cost(8 * DEFAULT_COST);
    // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
    format %{ "LCGR    $dst,$src  \t# preserve src\n\t"
              "NGR     $dst,$src  \t#"
              "AGHI    $dst,-1    \t# tmp1 = src-1\n\t"
--- 10703,10712 ----