1 //
   2 // Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright (c) 2016 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 
  25 // z/Architecture Architecture Description File
  26 
  27 // Major contributions by AS, JL, LS.
  28 
  29 //
  30 // Following information is derived from private mail communication
  31 // (Oct. 2011).
  32 //
  33 // General branch target alignment considerations
  34 //
  35 // z/Architecture does not imply a general branch target alignment requirement.
  36 // There are side effects and side considerations, though, which may
  37 // provide some performance benefit. These are:
  38 //  - Align branch target on octoword (32-byte) boundary
  39 //    On more recent models (from z9 on), I-fetch is done on a Octoword
  40 //    (32 bytes at a time) basis. To avoid I-fetching unnecessary
  41 //    instructions, branch targets should be 32-byte aligend. If this
  42 //    exact alingment cannot be achieved, having the branch target in
  43 //    the first doubleword still provides some benefit.
  44 //  - Avoid branch targets at the end of cache lines (> 64 bytes distance).
  45 //    Sequential instruction prefetching after the branch target starts
  46 //    immediately after having fetched the octoword containing the
  47 //    branch target. When I-fetching crosses a cache line, there may be
  48 //    a small stall. The worst case: the branch target (at the end of
  49 //    a cache line) is a L1 I-cache miss and the next line as well.
  50 //    Then, the entire target line must be filled first (to contine at the
  51 //    branch target). Only then can the next sequential line be filled.
  52 //  - Avoid multiple poorly predicted branches in a row.
  53 //
  54 
  55 //----------REGISTER DEFINITION BLOCK------------------------------------------
  56 // This information is used by the matcher and the register allocator to
  57 // describe individual registers and classes of registers within the target
  58 // architecture.
  59 
  60 register %{
  61 
  62 //----------Architecture Description Register Definitions----------------------
  63 // General Registers
  64 // "reg_def" name (register save type, C convention save type,
  65 //                   ideal register type, encoding);
  66 //
  67 // Register Save Types:
  68 //
  69 //   NS  = No-Save:     The register allocator assumes that these registers
  70 //                      can be used without saving upon entry to the method, &
  71 //                      that they do not need to be saved at call sites.
  72 //
  73 //   SOC = Save-On-Call: The register allocator assumes that these registers
  74 //                      can be used without saving upon entry to the method,
  75 //                      but that they must be saved at call sites.
  76 //
  77 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  78 //                      must be saved before using them upon entry to the
  79 //                      method, but they do not need to be saved at call sites.
  80 //
  81 //   AS  = Always-Save: The register allocator assumes that these registers
  82 //                      must be saved before using them upon entry to the
  83 //                      method, & that they must be saved at call sites.
  84 //
  85 // Ideal Register Type is used to determine how to save & restore a
  86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  88 //
  89 // The encoding number is the actual bit-pattern placed into the opcodes.
  90 
  91 // z/Architecture register definitions, based on the z/Architecture Principles
  92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
  93 // 5th Edition, March 2001.
  94 //
  95 // For each 64-bit register we must define two registers: the register
  96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
  97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
  98 // for stores, loads, etc.
  99 
 100   // Integer/Long Registers
 101   // ----------------------------
 102 
 103   // z/Architecture has 16 64-bit integer registers.
 104 
 105   // types: v = volatile, nv = non-volatile, s = system
 106   reg_def Z_R0   (SOC, SOC, Op_RegI,  0, Z_R0->as_VMReg());   // v   scratch1
 107   reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
 108   reg_def Z_R1   (SOC, SOC, Op_RegI,  1, Z_R1->as_VMReg());   // v   scratch2
 109   reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
 110   reg_def Z_R2   (SOC, SOC, Op_RegI,  2, Z_R2->as_VMReg());   // v   iarg1 & iret
 111   reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
 112   reg_def Z_R3   (SOC, SOC, Op_RegI,  3, Z_R3->as_VMReg());   // v   iarg2
 113   reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
 114   reg_def Z_R4   (SOC, SOC, Op_RegI,  4, Z_R4->as_VMReg());   // v   iarg3
 115   reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
 116   reg_def Z_R5   (SOC, SOC, Op_RegI,  5, Z_R5->as_VMReg());   // v   iarg4
 117   reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
 118   reg_def Z_R6   (SOC, SOE, Op_RegI,  6, Z_R6->as_VMReg());   // v   iarg5
 119   reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
 120   reg_def Z_R7   (SOC, SOE, Op_RegI,  7, Z_R7->as_VMReg());
 121   reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
 122   reg_def Z_R8   (SOC, SOE, Op_RegI,  8, Z_R8->as_VMReg());
 123   reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
 124   reg_def Z_R9   (SOC, SOE, Op_RegI,  9, Z_R9->as_VMReg());
 125   reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
 126   reg_def Z_R10  (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
 127   reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
 128   reg_def Z_R11  (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
 129   reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
 130   reg_def Z_R12  (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
 131   reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
 132   reg_def Z_R13  (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
 133   reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
 134   reg_def Z_R14  (NS,  NS,  Op_RegI, 14, Z_R14->as_VMReg());   // s  return_pc
 135   reg_def Z_R14_H(NS,  NS,  Op_RegI, 99, Z_R14->as_VMReg()->next());
 136   reg_def Z_R15  (NS,  NS,  Op_RegI, 15, Z_R15->as_VMReg());   // s  SP
 137   reg_def Z_R15_H(NS,  NS,  Op_RegI, 99, Z_R15->as_VMReg()->next());
 138 
 139   // Float/Double Registers
 140 
 141   // The rules of ADL require that double registers be defined in pairs.
 142   // Each pair must be two 32-bit values, but not necessarily a pair of
 143   // single float registers. In each pair, ADLC-assigned register numbers
 144   // must be adjacent, with the lower number even. Finally, when the
 145   // CPU stores such a register pair to memory, the word associated with
 146   // the lower ADLC-assigned number must be stored to the lower address.
 147 
 148   // z/Architecture has 16 64-bit floating-point registers. Each can store a single
 149   // or double precision floating-point value.
 150 
 151   // types: v = volatile, nv = non-volatile, s = system
 152   reg_def Z_F0   (SOC, SOC, Op_RegF,  0, Z_F0->as_VMReg());   // v   farg1 & fret
 153   reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
 154   reg_def Z_F1   (SOC, SOC, Op_RegF,  1, Z_F1->as_VMReg());
 155   reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
 156   reg_def Z_F2   (SOC, SOC, Op_RegF,  2, Z_F2->as_VMReg());   // v   farg2
 157   reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
 158   reg_def Z_F3   (SOC, SOC, Op_RegF,  3, Z_F3->as_VMReg());
 159   reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
 160   reg_def Z_F4   (SOC, SOC, Op_RegF,  4, Z_F4->as_VMReg());   // v   farg3
 161   reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
 162   reg_def Z_F5   (SOC, SOC, Op_RegF,  5, Z_F5->as_VMReg());
 163   reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
 164   reg_def Z_F6   (SOC, SOC, Op_RegF,  6, Z_F6->as_VMReg());
 165   reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
 166   reg_def Z_F7   (SOC, SOC, Op_RegF,  7, Z_F7->as_VMReg());
 167   reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
 168   reg_def Z_F8   (SOC, SOE, Op_RegF,  8, Z_F8->as_VMReg());
 169   reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
 170   reg_def Z_F9   (SOC, SOE, Op_RegF,  9, Z_F9->as_VMReg());
 171   reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
 172   reg_def Z_F10  (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
 173   reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
 174   reg_def Z_F11  (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
 175   reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
 176   reg_def Z_F12  (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
 177   reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
 178   reg_def Z_F13  (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
 179   reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
 180   reg_def Z_F14  (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
 181   reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
 182   reg_def Z_F15  (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
 183   reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
 184 
 185 
 186   // Special Registers
 187 
 188   // Condition Codes Flag Registers
 189 
 190   // z/Architecture has the PSW (program status word) that contains
 191   // (among other information) the condition code. We treat this
 192   // part of the PSW as a condition register CR. It consists of 4
 193   // bits. Floating point instructions influence the same condition register CR.
 194 
 195   reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg());   // volatile
 196 
 197 
 198 // Specify priority of register selection within phases of register
 199 // allocation. Highest priority is first. A useful heuristic is to
 200 // give registers a low priority when they are required by machine
 201 // instructions, and choose no-save registers before save-on-call, and
 202 // save-on-call before save-on-entry. Registers which participate in
 203 // fix calling sequences should come last. Registers which are used
 204 // as pairs must fall on an even boundary.
 205 
 206 // It's worth about 1% on SPEC geomean to get this right.
 207 
 208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
 210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
 211 // the same as Z_R3->encoding()! Furthermore, we cannot make any
 212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
 213 // Additionally, the function
 214 //   static enum RC rc_class(OptoReg::Name reg)
 215 // maps a given <register>_num value to its chunk type (except for flags)
 216 // and its current implementation relies on chunk0 and chunk1 having a
 217 // size of 64 each.
 218 
 219 alloc_class chunk0(
 220   // chunk0 contains *all* 32 integer registers halves.
 221 
 222   // potential SOE regs
 223   Z_R13,Z_R13_H,
 224   Z_R12,Z_R12_H,
 225   Z_R11,Z_R11_H,
 226   Z_R10,Z_R10_H,
 227 
 228   Z_R9,Z_R9_H,
 229   Z_R8,Z_R8_H,
 230   Z_R7,Z_R7_H,
 231 
 232   Z_R1,Z_R1_H,
 233   Z_R0,Z_R0_H,
 234 
 235   // argument registers
 236   Z_R6,Z_R6_H,
 237   Z_R5,Z_R5_H,
 238   Z_R4,Z_R4_H,
 239   Z_R3,Z_R3_H,
 240   Z_R2,Z_R2_H,
 241 
 242   // special registers
 243   Z_R14,Z_R14_H,
 244   Z_R15,Z_R15_H
 245 );
 246 
 247 alloc_class chunk1(
 248   // Chunk1 contains *all* 64 floating-point registers halves.
 249 
 250   Z_F15,Z_F15_H,
 251   Z_F14,Z_F14_H,
 252   Z_F13,Z_F13_H,
 253   Z_F12,Z_F12_H,
 254   Z_F11,Z_F11_H,
 255   Z_F10,Z_F10_H,
 256   Z_F9,Z_F9_H,
 257   Z_F8,Z_F8_H,
 258   // scratch register
 259   Z_F7,Z_F7_H,
 260   Z_F5,Z_F5_H,
 261   Z_F3,Z_F3_H,
 262   Z_F1,Z_F1_H,
 263   // argument registers
 264   Z_F6,Z_F6_H,
 265   Z_F4,Z_F4_H,
 266   Z_F2,Z_F2_H,
 267   Z_F0,Z_F0_H
 268 );
 269 
 270 alloc_class chunk2(
 271   Z_CR
 272 );
 273 
 274 
 275 //-------Architecture Description Register Classes-----------------------
 276 
 277 // Several register classes are automatically defined based upon
 278 // information in this architecture description.
 279 
 280 // 1) reg_class inline_cache_reg           (as defined in frame section)
 281 // 2) reg_class compiler_method_oop_reg    (as defined in frame section)
 282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section)
 283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */)
 284 
 285 // Integer Register Classes
 286 reg_class z_int_reg(
 287 /*Z_R0*/              // R0
 288 /*Z_R1*/
 289   Z_R2,
 290   Z_R3,
 291   Z_R4,
 292   Z_R5,
 293   Z_R6,
 294   Z_R7,
 295 /*Z_R8,*/             // Z_thread
 296   Z_R9,
 297   Z_R10,
 298   Z_R11,
 299   Z_R12,
 300   Z_R13
 301 /*Z_R14*/             // return_pc
 302 /*Z_R15*/             // SP
 303 );
 304 
 305 reg_class z_no_odd_int_reg(
 306 /*Z_R0*/              // R0
 307 /*Z_R1*/
 308   Z_R2,
 309   Z_R3,
 310   Z_R4,
 311 /*Z_R5,*/             // odd part of fix register pair
 312   Z_R6,
 313   Z_R7,
 314 /*Z_R8,*/             // Z_thread
 315   Z_R9,
 316   Z_R10,
 317   Z_R11,
 318   Z_R12,
 319   Z_R13
 320 /*Z_R14*/             // return_pc
 321 /*Z_R15*/             // SP
 322 );
 323 
 324 reg_class z_no_arg_int_reg(
 325 /*Z_R0*/              // R0
 326 /*Z_R1*/              // scratch
 327 /*Z_R2*/
 328 /*Z_R3*/
 329 /*Z_R4*/
 330 /*Z_R5*/
 331 /*Z_R6*/
 332   Z_R7,
 333 /*Z_R8*/              // Z_thread
 334   Z_R9,
 335   Z_R10,
 336   Z_R11,
 337   Z_R12,
 338   Z_R13
 339 /*Z_R14*/             // return_pc
 340 /*Z_R15*/             // SP
 341 );
 342 
 343 reg_class z_rarg1_int_reg(Z_R2);
 344 reg_class z_rarg2_int_reg(Z_R3);
 345 reg_class z_rarg3_int_reg(Z_R4);
 346 reg_class z_rarg4_int_reg(Z_R5);
 347 reg_class z_rarg5_int_reg(Z_R6);
 348 
 349 // Pointer Register Classes
 350 
 351 // 64-bit build means 64-bit pointers means hi/lo pairs.
 352 
 353 reg_class z_rarg5_ptrN_reg(Z_R6);
 354 
 355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
 356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
 357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
 358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
 359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
 360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
 361 
 362 reg_class z_ptr_reg(
 363 /*Z_R0_H,Z_R0*/     // R0
 364 /*Z_R1_H,Z_R1*/
 365   Z_R2_H,Z_R2,
 366   Z_R3_H,Z_R3,
 367   Z_R4_H,Z_R4,
 368   Z_R5_H,Z_R5,
 369   Z_R6_H,Z_R6,
 370   Z_R7_H,Z_R7,
 371 /*Z_R8_H,Z_R8,*/    // Z_thread
 372   Z_R9_H,Z_R9,
 373   Z_R10_H,Z_R10,
 374   Z_R11_H,Z_R11,
 375   Z_R12_H,Z_R12,
 376   Z_R13_H,Z_R13
 377 /*Z_R14_H,Z_R14*/   // return_pc
 378 /*Z_R15_H,Z_R15*/   // SP
 379 );
 380 
 381 reg_class z_lock_ptr_reg(
 382 /*Z_R0_H,Z_R0*/     // R0
 383 /*Z_R1_H,Z_R1*/
 384   Z_R2_H,Z_R2,
 385   Z_R3_H,Z_R3,
 386   Z_R4_H,Z_R4,
 387 /*Z_R5_H,Z_R5,*/
 388 /*Z_R6_H,Z_R6,*/
 389   Z_R7_H,Z_R7,
 390 /*Z_R8_H,Z_R8,*/    // Z_thread
 391   Z_R9_H,Z_R9,
 392   Z_R10_H,Z_R10,
 393   Z_R11_H,Z_R11,
 394   Z_R12_H,Z_R12,
 395   Z_R13_H,Z_R13
 396 /*Z_R14_H,Z_R14*/   // return_pc
 397 /*Z_R15_H,Z_R15*/   // SP
 398 );
 399 
 400 reg_class z_no_arg_ptr_reg(
 401 /*Z_R0_H,Z_R0*/        // R0
 402 /*Z_R1_H,Z_R1*/        // scratch
 403 /*Z_R2_H,Z_R2*/
 404 /*Z_R3_H,Z_R3*/
 405 /*Z_R4_H,Z_R4*/
 406 /*Z_R5_H,Z_R5*/
 407 /*Z_R6_H,Z_R6*/
 408   Z_R7_H, Z_R7,
 409 /*Z_R8_H,Z_R8*/        // Z_thread
 410   Z_R9_H,Z_R9,
 411   Z_R10_H,Z_R10,
 412   Z_R11_H,Z_R11,
 413   Z_R12_H,Z_R12,
 414   Z_R13_H,Z_R13
 415 /*Z_R14_H,Z_R14*/      // return_pc
 416 /*Z_R15_H,Z_R15*/      // SP
 417 );
 418 
 419 // Special class for storeP instructions, which can store SP or RPC to
 420 // TLS. (Note: Do not generalize this to "any_reg". If you add
 421 // another register, such as FP, to this mask, the allocator may try
 422 // to put a temp in it.)
 423 // Register class for memory access base registers,
 424 // This class is a superset of z_ptr_reg including Z_thread.
 425 reg_class z_memory_ptr_reg(
 426 /*Z_R0_H,Z_R0*/     // R0
 427 /*Z_R1_H,Z_R1*/
 428   Z_R2_H,Z_R2,
 429   Z_R3_H,Z_R3,
 430   Z_R4_H,Z_R4,
 431   Z_R5_H,Z_R5,
 432   Z_R6_H,Z_R6,
 433   Z_R7_H,Z_R7,
 434   Z_R8_H,Z_R8,      // Z_thread
 435   Z_R9_H,Z_R9,
 436   Z_R10_H,Z_R10,
 437   Z_R11_H,Z_R11,
 438   Z_R12_H,Z_R12,
 439   Z_R13_H,Z_R13
 440 /*Z_R14_H,Z_R14*/   // return_pc
 441 /*Z_R15_H,Z_R15*/   // SP
 442 );
 443 
 444 // Other special pointer regs.
 445 reg_class z_r1_regP(Z_R1_H,Z_R1);
 446 reg_class z_r9_regP(Z_R9_H,Z_R9);
 447 
 448 
 449 // Long Register Classes
 450 
 451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
 452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
 453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
 454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
 455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
 456 
 457 // Longs in 1 register. Aligned adjacent hi/lo pairs.
 458 reg_class z_long_reg(
 459 /*Z_R0_H,Z_R0*/     // R0
 460 /*Z_R1_H,Z_R1*/
 461   Z_R2_H,Z_R2,
 462   Z_R3_H,Z_R3,
 463   Z_R4_H,Z_R4,
 464   Z_R5_H,Z_R5,
 465   Z_R6_H,Z_R6,
 466   Z_R7_H,Z_R7,
 467 /*Z_R8_H,Z_R8,*/    // Z_thread
 468   Z_R9_H,Z_R9,
 469   Z_R10_H,Z_R10,
 470   Z_R11_H,Z_R11,
 471   Z_R12_H,Z_R12,
 472   Z_R13_H,Z_R13
 473 /*Z_R14_H,Z_R14,*/  // return_pc
 474 /*Z_R15_H,Z_R15*/   // SP
 475 );
 476 
 477 
 478 // Special Class for Condition Code Flags Register
 479 
 480 reg_class z_condition_reg(
 481   Z_CR
 482 );
 483 
 484 // Scratch register for late profiling. Callee saved.
 485 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
 486 
 487 
 488 // Float Register Classes
 489 
 490 reg_class z_flt_reg(
 491   Z_F0,
 492 /*Z_F1,*/ // scratch
 493   Z_F2,
 494   Z_F3,
 495   Z_F4,
 496   Z_F5,
 497   Z_F6,
 498   Z_F7,
 499   Z_F8,
 500   Z_F9,
 501   Z_F10,
 502   Z_F11,
 503   Z_F12,
 504   Z_F13,
 505   Z_F14,
 506   Z_F15
 507 );
 508 reg_class z_rscratch1_flt_reg(Z_F1);
 509 
 510 // Double precision float registers have virtual `high halves' that
 511 // are needed by the allocator.
 512 reg_class z_dbl_reg(
 513   Z_F0,Z_F0_H,
 514 /*Z_F1,Z_F1_H,*/ // scratch
 515   Z_F2,Z_F2_H,
 516   Z_F3,Z_F3_H,
 517   Z_F4,Z_F4_H,
 518   Z_F5,Z_F5_H,
 519   Z_F6,Z_F6_H,
 520   Z_F7,Z_F7_H,
 521   Z_F8,Z_F8_H,
 522   Z_F9,Z_F9_H,
 523   Z_F10,Z_F10_H,
 524   Z_F11,Z_F11_H,
 525   Z_F12,Z_F12_H,
 526   Z_F13,Z_F13_H,
 527   Z_F14,Z_F14_H,
 528   Z_F15,Z_F15_H
 529 );
 530 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
 531 
 532 %}
 533 
 534 //----------DEFINITION BLOCK---------------------------------------------------
 535 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
 536 // Current support includes integer values in the range [0, 0x7FFFFFFF].
 537 // Format:
 538 //        int_def  <name>         (<int_value>, <expression>);
 539 // Generated Code in ad_<arch>.hpp
 540 //        #define  <name>   (<expression>)
 541 //        // value == <int_value>
 542 // Generated code in ad_<arch>.cpp adlc_verification()
 543 //        assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 544 //
 545 definitions %{
 546   // The default cost (of an ALU instruction).
 547   int_def DEFAULT_COST      (   100,     100);
 548   int_def DEFAULT_COST_LOW  (    80,      80);
 549   int_def DEFAULT_COST_HIGH (   120,     120);
 550   int_def HUGE_COST         (1000000, 1000000);
 551 
 552   // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
 553   int_def ALU_REG_COST      (   100, DEFAULT_COST);
 554   int_def ALU_MEMORY_COST   (   150,          150);
 555 
 556   // Memory refs are twice as expensive as run-of-the-mill.
 557   int_def MEMORY_REF_COST_HI (   220, 2 * DEFAULT_COST+20);
 558   int_def MEMORY_REF_COST    (   200, 2 * DEFAULT_COST);
 559   int_def MEMORY_REF_COST_LO (   180, 2 * DEFAULT_COST-20);
 560 
 561   // Branches are even more expensive.
 562   int_def BRANCH_COST       (   300, DEFAULT_COST * 3);
 563   int_def CALL_COST         (   300, DEFAULT_COST * 3);
 564 %}
 565 
 566 source %{
 567 
 568 #ifdef PRODUCT
 569 #define BLOCK_COMMENT(str)
 570 #define BIND(label)        __ bind(label)
 571 #else
 572 #define BLOCK_COMMENT(str) __ block_comment(str)
 573 #define BIND(label)        __ bind(label); BLOCK_COMMENT(#label ":")
 574 #endif
 575 
 576 #define __ _masm.
 577 
 578 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ?  4 : 6
 579 #define Z_DISP3_SIZE 6
 580 
 581 // Tertiary op of a LoadP or StoreP encoding.
 582 #define REGP_OP true
 583 
 584 // Given a register encoding, produce an Integer Register object.
 585 static Register reg_to_register_object(int register_encoding);
 586 
 587 // ****************************************************************************
 588 
 589 // REQUIRED FUNCTIONALITY
 590 
 591 // !!!!! Special hack to get all type of calls to specify the byte offset
 592 //       from the start of the call to the point where the return address
 593 //       will point.
 594 
 595 int MachCallStaticJavaNode::ret_addr_offset() {
 596   if (_method) {
 597     return 8;
 598   } else {
 599     return MacroAssembler::call_far_patchable_ret_addr_offset();
 600   }
 601 }
 602 
 603 int MachCallDynamicJavaNode::ret_addr_offset() {
 604   // Consider size of receiver type profiling (C2 tiers).
 605   int profile_receiver_type_size = 0;
 606 
 607   int vtable_index = this->_vtable_index;
 608   if (vtable_index == -4) {
 609     return 14 + profile_receiver_type_size;
 610   } else {
 611     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 612     return 36 + profile_receiver_type_size;
 613   }
 614 }
 615 
 616 int MachCallRuntimeNode::ret_addr_offset() {
 617   return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
 618 }
 619 
 620 // Compute padding required for nodes which need alignment
 621 //
 622 // The addresses of the call instructions needs to be 4-byte aligned to
 623 // ensure that they don't span a cache line so that they are atomically patchable.
 624 // The actual calls get emitted at different offsets within the node emitters.
 625 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
 626 
 627 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
 628   return (0 - current_offset) & 2;
 629 }
 630 
 631 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
 632   return (6 - current_offset) & 2;
 633 }
 634 
 635 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
 636   return (12 - current_offset) & 2;
 637 }
 638 
 639 int CallLeafDirectNode::compute_padding(int current_offset) const {
 640   return (12 - current_offset) & 2;
 641 }
 642 
 643 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
 644   return (12 - current_offset) & 2;
 645 }
 646 
 647 // Indicate if the safepoint node needs the polling page as an input.
 648 // Since z/Architecture does not have absolute addressing, it does.
 649 bool SafePointNode::needs_polling_address_input() {
 650   return true;
 651 }
 652 
 653 void emit_nop(CodeBuffer &cbuf) {
 654   MacroAssembler _masm(&cbuf);
 655   __ z_nop();
 656 }
 657 
 658 // Emit an interrupt that is caught by the debugger (for debugging compiler).
 659 void emit_break(CodeBuffer &cbuf) {
 660   MacroAssembler _masm(&cbuf);
 661   __ z_illtrap();
 662 }
 663 
 664 #if !defined(PRODUCT)
 665 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
 666   os->print("TA");
 667 }
 668 #endif
 669 
 670 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 671   emit_break(cbuf);
 672 }
 673 
 674 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 675   return MachNode::size(ra_);
 676 }
 677 
 678 static inline void z_emit16(CodeBuffer &cbuf, long value) {
 679   // 32bit instructions may become sign extended.
 680   assert(value >= 0, "unintended sign extension (int->long)");
 681   assert(value < (1L << 16), "instruction too large");
 682   *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
 683   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
 684 }
 685 
 686 static inline void z_emit32(CodeBuffer &cbuf, long value) {
 687   // 32bit instructions may become sign extended.
 688   assert(value < (1L << 32), "instruction too large");
 689   *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
 690   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
 691 }
 692 
 693 static inline void z_emit48(CodeBuffer &cbuf, long value) {
 694   // 32bit instructions may become sign extended.
 695   assert(value >= 0, "unintended sign extension (int->long)");
 696   assert(value < (1L << 48), "instruction too large");
 697   value = value<<16;
 698   memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
 699   cbuf.set_insts_end(cbuf.insts_end() + 6);
 700 }
 701 
 702 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
 703   if (value < 0) {
 704     // There obviously has been an unintended sign extension (int->long). Revert it.
 705     value = (long)((unsigned long)((unsigned int)value));
 706   }
 707 
 708   if (value < (1L << 16)) { // 2-byte instruction
 709     z_emit16(cbuf, value);
 710     return 2;
 711   }
 712 
 713   if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
 714     z_emit32(cbuf, value);
 715     return 4;
 716   }
 717 
 718   // 6-byte instruction, probably unaligned store.
 719   z_emit48(cbuf, value);
 720   return 6;
 721 }
 722 
 723 // Check effective address (at runtime) for required alignment.
 724 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
 725   MacroAssembler _masm(&cbuf);
 726 
 727   __ z_lay(Z_R0, disp, index, base);
 728   __ z_nill(Z_R0, alignment-1);
 729   __ z_brc(Assembler::bcondEqual, +3);
 730   __ z_illtrap();
 731 }
 732 
 733 int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
 734                     PhaseRegAlloc* ra_, bool is_native_call = false) {
 735   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
 736   address old_mark = __ inst_mark();
 737   unsigned int start_off = __ offset();
 738 
 739   if (is_native_call) {
 740     ShouldNotReachHere();
 741   }
 742 
 743   if (rtype == relocInfo::runtime_call_w_cp_type) {
 744     assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
 745     address call_addr = __ call_c_opt((address)entry_point);
 746     if (call_addr == NULL) {
 747       Compile::current()->env()->record_out_of_memory_failure();
 748       return -1;
 749     }
 750   } else {
 751     assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
 752            rtype == relocInfo::static_call_type, "unexpected rtype");
 753     __ relocate(rtype);
 754     // BRASL must be prepended with a nop to identify it in the instruction stream.
 755     __ z_nop();
 756     __ z_brasl(Z_R14, (address)entry_point);
 757   }
 758 
 759   unsigned int ret_off = __ offset();
 760 
 761   return (ret_off - start_off);
 762 }
 763 
 764 static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
 765   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
 766   address old_mark = __ inst_mark();
 767   unsigned int start_off = __ offset();
 768 
 769   relocInfo::relocType rtype = rspec.type();
 770   assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
 771          "unexpected rtype");
 772 
 773   __ relocate(rspec);
 774   __ z_nop();
 775   __ z_brasl(Z_R14, (address)entry_point);
 776 
 777   unsigned int ret_off = __ offset();
 778 
 779   return (ret_off - start_off);
 780 }
 781 
 782 //=============================================================================
 783 
 784 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
 785 int Compile::ConstantTable::calculate_table_base_offset() const {
 786   return 0;  // absolute addressing, no offset
 787 }
 788 
 789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 791   ShouldNotReachHere();
 792 }
 793 
 794 // Even with PC-relative TOC addressing, we still need this node.
 795 // Float loads/stores do not support PC-relative addresses.
 796 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 797   MacroAssembler _masm(&cbuf);
 798   Register Rtoc = as_Register(ra_->get_encode(this));
 799   __ load_toc(Rtoc);
 800 }
 801 
 802 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 803   // PCrelative TOC access.
 804   return 6;   // sizeof(LARL)
 805 }
 806 
 807 #if !defined(PRODUCT)
 808 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 809   Register r = as_Register(ra_->get_encode(this));
 810   st->print("LARL    %s,&constant_pool # MachConstantBaseNode", r->name());
 811 }
 812 #endif
 813 
 814 //=============================================================================
 815 
 816 #if !defined(PRODUCT)
 817 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 818   Compile* C = ra_->C;
 819   st->print_cr("--- MachPrologNode ---");
 820   st->print("\t");
 821   for (int i = 0; i < OptoPrologueNops; i++) {
 822     st->print_cr("NOP"); st->print("\t");
 823   }
 824 
 825   if (VerifyThread) {
 826     st->print_cr("Verify_Thread");
 827     st->print("\t");
 828   }
 829 
 830   long framesize = C->frame_size_in_bytes();
 831   int bangsize   = C->bang_size_in_bytes();
 832 
 833   // Calls to C2R adapters often do not accept exceptional returns.
 834   // We require that their callers must bang for them. But be
 835   // careful, because some VM calls (such as call site linkage) can
 836   // use several kilobytes of stack. But the stack safety zone should
 837   // account for that. See bugs 4446381, 4468289, 4497237.
 838   if (C->need_stack_bang(bangsize) && UseStackBanging) {
 839     st->print_cr("# stack bang"); st->print("\t");
 840   }
 841   st->print_cr("push_frame %d", (int)-framesize);
 842   st->print("\t");
 843 }
 844 #endif
 845 
 846 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 847   Compile* C = ra_->C;
 848   MacroAssembler _masm(&cbuf);
 849 
 850   __ verify_thread();
 851 
 852   size_t framesize = C->frame_size_in_bytes();
 853   size_t bangsize  = C->bang_size_in_bytes();
 854 
 855   assert(framesize % wordSize == 0, "must preserve wordSize alignment");
 856 
 857   // Calls to C2R adapters often do not accept exceptional returns.
 858   // We require that their callers must bang for them. But be
 859   // careful, because some VM calls (such as call site linkage) can
 860   // use several kilobytes of stack. But the stack safety zone should
 861   // account for that. See bugs 4446381, 4468289, 4497237.
 862   if (C->need_stack_bang(bangsize) && UseStackBanging) {
 863     __ generate_stack_overflow_check(bangsize);
 864   }
 865 
 866   assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
 867   __ save_return_pc();
 868 
 869   // The z/Architecture abi is already accounted for in `framesize' via the
 870   // 'out_preserve_stack_slots' declaration.
 871   __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
 872 
 873   if (C->has_mach_constant_base_node()) {
 874     // NOTE: We set the table base offset here because users might be
 875     // emitted before MachConstantBaseNode.
 876     Compile::ConstantTable& constant_table = C->constant_table();
 877     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 878   }
 879 }
 880 
 881 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
 882   // Variable size. Determine dynamically.
 883   return MachNode::size(ra_);
 884 }
 885 
 886 int MachPrologNode::reloc() const {
 887   // Return number of relocatable values contained in this instruction.
 888   return 1; // One reloc entry for load_const(toc).
 889 }
 890 
 891 //=============================================================================
 892 
 893 #if !defined(PRODUCT)
 894 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 895   os->print_cr("epilog");
 896   os->print("\t");
 897   if (do_polling() && ra_->C->is_method_compilation()) {
 898     os->print_cr("load_from_polling_page Z_R1_scratch");
 899     os->print("\t");
 900   }
 901 }
 902 #endif
 903 
 904 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 905   MacroAssembler _masm(&cbuf);
 906   Compile* C = ra_->C;
 907   __ verify_thread();
 908 
 909   // If this does safepoint polling, then do it here.
 910   bool need_polling = do_polling() && C->is_method_compilation();
 911 
 912   // Touch the polling page.
 913   // Part 1: get the page's address.
 914   if (need_polling) {
 915     AddressLiteral pp(os::get_polling_page());
 916     __ load_const_optimized(Z_R1_scratch, pp);
 917   }
 918 
 919   // Pop frame, restore return_pc, and all stuff needed by interpreter.
 920   // Pop frame by add insted of load (a penny saved is a penny got :-).
 921   int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
 922   int retPC_offset        = frame_size_in_bytes + _z_abi16(return_pc);
 923   if (Displacement::is_validDisp(retPC_offset)) {
 924     __ z_lg(Z_R14, retPC_offset, Z_SP);
 925     __ add2reg(Z_SP, frame_size_in_bytes);
 926   } else {
 927     __ add2reg(Z_SP, frame_size_in_bytes);
 928     __ restore_return_pc();
 929   }
 930 
 931   // Touch the polling page,
 932   // part 2: touch the page now.
 933   if (need_polling) {
 934     // We need to mark the code position where the load from the safepoint
 935     // polling page was emitted as relocInfo::poll_return_type here.
 936     __ relocate(relocInfo::poll_return_type);
 937     __ load_from_polling_page(Z_R1_scratch);
 938   }
 939 }
 940 
 941 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 942   // variable size. determine dynamically.
 943   return MachNode::size(ra_);
 944 }
 945 
 946 int MachEpilogNode::reloc() const {
 947   // Return number of relocatable values contained in this instruction.
 948   return 1; // One for load_from_polling_page.
 949 }
 950 
 951 const Pipeline * MachEpilogNode::pipeline() const {
 952   return MachNode::pipeline_class();
 953 }
 954 
 955 int MachEpilogNode::safepoint_offset() const {
 956   assert(do_polling(), "no return for this epilog node");
 957   return 0;
 958 }
 959 
 960 //=============================================================================
 961 
 962 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
 963 enum RC { rc_bad, rc_int, rc_float, rc_stack };
 964 
 965 static enum RC rc_class(OptoReg::Name reg) {
 966   // Return the register class for the given register. The given register
 967   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
 968   // enumeration in adGlobals_s390.hpp.
 969 
 970   if (reg == OptoReg::Bad) {
 971     return rc_bad;
 972   }
 973 
 974   // We have 32 integer register halves, starting at index 0.
 975   if (reg < 32) {
 976     return rc_int;
 977   }
 978 
 979   // We have 32 floating-point register halves, starting at index 32.
 980   if (reg < 32+32) {
 981     return rc_float;
 982   }
 983 
 984   // Between float regs & stack are the flags regs.
 985   assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
 986   return rc_stack;
 987 }
 988 
 989 // Returns size as obtained from z_emit_instr.
 990 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode,
 991                                    int reg, int offset, bool do_print, outputStream *os) {
 992 
 993   if (cbuf) {
 994     if (opcode > (1L<<32)) {
 995       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
 996                          Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
 997     } else {
 998       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
 999                          Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1000     }
1001   }
1002 
1003 #if !defined(PRODUCT)
1004   if (do_print) {
1005     os->print("%s    %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1006   }
1007 #endif
1008   return (opcode > (1L << 32)) ? 6 : 4;
1009 }
1010 
1011 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1012   if (cbuf) {
1013     MacroAssembler _masm(cbuf);
1014     __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1015   }
1016 
1017 #if !defined(PRODUCT)
1018   else if (do_print) {
1019     os->print("MVC     %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1020   }
1021 #endif
1022 
1023   return 6;
1024 }
1025 
1026 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1027   // Get registers to move.
1028   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1029   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1030   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1031   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1032 
1033   enum RC src_hi_rc = rc_class(src_hi);
1034   enum RC src_lo_rc = rc_class(src_lo);
1035   enum RC dst_hi_rc = rc_class(dst_hi);
1036   enum RC dst_lo_rc = rc_class(dst_lo);
1037 
1038   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1039   bool is64 = (src_hi_rc != rc_bad);
1040   assert(!is64 ||
1041          ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1042          "expected aligned-adjacent pairs");
1043 
1044   // Generate spill code!
1045 
1046   if (src_lo == dst_lo && src_hi == dst_hi) {
1047     return 0;            // Self copy, no move.
1048   }
1049 
1050   int  src_offset = ra_->reg2offset(src_lo);
1051   int  dst_offset = ra_->reg2offset(dst_lo);
1052   bool print = !do_size;
1053   bool src12 = Immediate::is_uimm12(src_offset);
1054   bool dst12 = Immediate::is_uimm12(dst_offset);
1055 
1056   const char   *mnemo = NULL;
1057   unsigned long opc = 0;
1058 
1059   // Memory->Memory Spill. Use Z_R0 to hold the value.
1060   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1061 
1062     assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1063            "expected same type of move for high parts");
1064 
1065     if (src12 && dst12) {
1066       return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1067     }
1068 
1069     int r0 = Z_R0_num;
1070     if (is64) {
1071       return z_ld_st_helper(cbuf, "LG  ", LG_ZOPC, r0, src_offset, print, os) +
1072              z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1073     }
1074 
1075     return z_ld_st_helper(cbuf, "LY   ", LY_ZOPC, r0, src_offset, print, os) +
1076            z_ld_st_helper(cbuf, "STY  ", STY_ZOPC, r0, dst_offset, print, os);
1077   }
1078 
1079   // Check for float->int copy. Requires a trip through memory.
1080   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1081     Unimplemented();  // Unsafe, do not remove!
1082   }
1083 
1084   // Check for integer reg-reg copy.
1085   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1086     if (cbuf) {
1087       MacroAssembler _masm(cbuf);
1088       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1089       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1090       __ z_lgr(Rdst, Rsrc);
1091       return 4;
1092     }
1093 #if !defined(PRODUCT)
1094     // else
1095     if (print) {
1096       os->print("LGR     %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1097     }
1098 #endif
1099     return 4;
1100   }
1101 
1102   // Check for integer store.
1103   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1104     assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1105            "expected same type of move for high parts");
1106 
1107     if (is64) {
1108       return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1109     }
1110 
1111     // else
1112     mnemo = dst12 ? "ST  " : "STY ";
1113     opc = dst12 ? ST_ZOPC : STY_ZOPC;
1114 
1115     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1116   }
1117 
1118   // Check for integer load
1119   // Always load cOops zero-extended. That doesn't hurt int loads.
1120   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1121 
1122     assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1123            "expected same type of move for high parts");
1124 
1125     mnemo = is64 ? "LG  " : "LLGF";
1126     opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1127 
1128     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1129   }
1130 
1131   // Check for float reg-reg copy.
1132   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1133     if (cbuf) {
1134       MacroAssembler _masm(cbuf);
1135       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1136       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1137       __ z_ldr(Rdst, Rsrc);
1138       return 2;
1139     }
1140 #if !defined(PRODUCT)
1141     // else
1142     if (print) {
1143       os->print("LDR      %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1144     }
1145 #endif
1146     return 2;
1147   }
1148 
1149   // Check for float store.
1150   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1151     assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1152            "expected same type of move for high parts");
1153 
1154     if (is64) {
1155       mnemo = dst12 ? "STD  " : "STDY ";
1156       opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1157       return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1158     }
1159     // else
1160 
1161     mnemo = dst12 ? "STE  " : "STEY ";
1162     opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1163     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1164   }
1165 
1166   // Check for float load.
1167   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1168     assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1169            "expected same type of move for high parts");
1170 
1171     if (is64) {
1172       mnemo = src12 ? "LD   " : "LDY  ";
1173       opc = src12 ? LD_ZOPC : LDY_ZOPC;
1174       return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1175     }
1176     // else
1177 
1178     mnemo = src12 ? "LE   " : "LEY  ";
1179     opc = src12 ? LE_ZOPC : LEY_ZOPC;
1180     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1181   }
1182 
1183   // --------------------------------------------------------------------
1184   // Check for hi bits still needing moving. Only happens for misaligned
1185   // arguments to native calls.
1186   if (src_hi == dst_hi) {
1187     return 0;               // Self copy, no move.
1188   }
1189 
1190   assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1191   Unimplemented();  // Unsafe, do not remove!
1192 
1193   return 0; // never reached, but make the compiler shut up!
1194 }
1195 
1196 #if !defined(PRODUCT)
1197 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1198   if (ra_ && ra_->node_regs_max_index() > 0) {
1199     implementation(NULL, ra_, false, os);
1200   } else {
1201     if (req() == 2 && in(1)) {
1202       os->print("N%d = N%d\n", _idx, in(1)->_idx);
1203     } else {
1204       const char *c = "(";
1205       os->print("N%d = ", _idx);
1206       for (uint i = 1; i < req(); ++i) {
1207         os->print("%sN%d", c, in(i)->_idx);
1208         c = ", ";
1209       }
1210       os->print(")");
1211     }
1212   }
1213 }
1214 #endif
1215 
1216 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217   implementation(&cbuf, ra_, false, NULL);
1218 }
1219 
1220 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1221   return implementation(NULL, ra_, true, NULL);
1222 }
1223 
1224 //=============================================================================
1225 
1226 #if !defined(PRODUCT)
1227 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1228   os->print("NOP     # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1229 }
1230 #endif
1231 
1232 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
1233   MacroAssembler _masm(&cbuf);
1234 
1235   int rem_space = 0;
1236   if (!(ra_->C->in_scratch_emit_size())) {
1237     rem_space = cbuf.insts()->remaining();
1238     if (rem_space <= _count*2 + 8) {
1239       tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1240     }
1241   }
1242 
1243   for (int i = 0; i < _count; i++) {
1244     __ z_nop();
1245   }
1246 
1247   if (!(ra_->C->in_scratch_emit_size())) {
1248     if (rem_space <= _count*2 + 8) {
1249       int rem_space2 = cbuf.insts()->remaining();
1250       tty->print_cr(", after = %d", rem_space2);
1251     }
1252   }
1253 }
1254 
1255 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1256    return 2 * _count;
1257 }
1258 
1259 #if !defined(PRODUCT)
1260 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1261   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1262   if (ra_ && ra_->node_regs_max_index() > 0) {
1263     int reg = ra_->get_reg_first(this);
1264     os->print("ADDHI  %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1265   } else {
1266     os->print("ADDHI  N%d = SP + %d\t// box node", _idx, offset);
1267   }
1268 }
1269 #endif
1270 
1271 // Take care of the size function, if you make changes here!
1272 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273   MacroAssembler _masm(&cbuf);
1274 
1275   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1276   int reg = ra_->get_encode(this);
1277   __ z_lay(as_Register(reg), offset, Z_SP);
1278 }
1279 
1280 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1281   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1282   return 6;
1283 }
1284 
1285  %} // end source section
1286 
1287 //----------SOURCE BLOCK-------------------------------------------------------
1288 // This is a block of C++ code which provides values, functions, and
1289 // definitions necessary in the rest of the architecture description
1290 
1291 source_hpp %{
1292 
1293 // Header information of the source block.
1294 // Method declarations/definitions which are used outside
1295 // the ad-scope can conveniently be defined here.
1296 //
1297 // To keep related declarations/definitions/uses close together,
1298 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1299 
1300 //--------------------------------------------------------------
1301 // Used for optimization in Compile::Shorten_branches
1302 //--------------------------------------------------------------
1303 
1304 class CallStubImpl {
1305  public:
1306 
1307   // call trampolines
1308   // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1309   static uint size_call_trampoline() {
1310     return 0; // no call trampolines on this platform
1311   }
1312 
1313   // call trampolines
1314   // Number of relocations needed by a call trampoline stub.
1315   static uint reloc_call_trampoline() {
1316     return 0; // No call trampolines on this platform.
1317   }
1318 };
1319 
1320 %} // end source_hpp section
1321 
1322 source %{
1323 
1324 #if !defined(PRODUCT)
1325 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1326   os->print_cr("---- MachUEPNode ----");
1327   os->print_cr("\tTA");
1328   os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1329   os->print_cr("\tBR(Z_R1)");
1330   os->print_cr("\tTA  # pad with illtraps");
1331   os->print_cr("\t...");
1332   os->print_cr("\tTA");
1333   os->print_cr("\tLTGR    Z_R2, Z_R2");
1334   os->print_cr("\tBRU     ic_miss");
1335 }
1336 #endif
1337 
1338 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1339   MacroAssembler _masm(&cbuf);
1340   const int ic_miss_offset = 2;
1341 
1342   // Inline_cache contains a klass.
1343   Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1344   // ARG1 is the receiver oop.
1345   Register R2_receiver = Z_ARG1;
1346   int      klass_offset = oopDesc::klass_offset_in_bytes();
1347   AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
1348   Register R1_ic_miss_stub_addr = Z_R1_scratch;
1349 
1350   // Null check of receiver.
1351   // This is the null check of the receiver that actually should be
1352   // done in the caller. It's here because in case of implicit null
1353   // checks we get it for free.
1354   assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()),
1355          "second word in oop should not require explicit null check.");
1356   if (!ImplicitNullChecks) {
1357     Label valid;
1358     if (VM_Version::has_CompareBranch()) {
1359       __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid);
1360     } else {
1361       __ z_ltgr(R2_receiver, R2_receiver);
1362       __ z_bre(valid);
1363     }
1364     // The ic_miss_stub will handle the null pointer exception.
1365     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1366     __ z_br(R1_ic_miss_stub_addr);
1367     __ bind(valid);
1368   }
1369 
1370   // Check whether this method is the proper implementation for the class of
1371   // the receiver (ic miss check).
1372   {
1373     Label valid;
1374     // Compare cached class against klass from receiver.
1375     // This also does an implicit null check!
1376     __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false);
1377     __ z_bre(valid);
1378     // The inline cache points to the wrong method. Call the
1379     // ic_miss_stub to find the proper method.
1380     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1381     __ z_br(R1_ic_miss_stub_addr);
1382     __ bind(valid);
1383   }
1384 
1385 }
1386 
1387 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1388   // Determine size dynamically.
1389   return MachNode::size(ra_);
1390 }
1391 
1392 //=============================================================================
1393 
1394 %} // interrupt source section
1395 
1396 source_hpp %{ // Header information of the source block.
1397 
1398 class HandlerImpl {
1399  public:
1400 
1401   static int emit_exception_handler(CodeBuffer &cbuf);
1402   static int emit_deopt_handler(CodeBuffer& cbuf);
1403 
1404   static uint size_exception_handler() {
1405     return NativeJump::max_instruction_size();
1406   }
1407 
1408   static uint size_deopt_handler() {
1409     return NativeCall::max_instruction_size();
1410   }
1411 };
1412 
1413 %} // end source_hpp section
1414 
1415 source %{
1416 
1417 // This exception handler code snippet is placed after the method's
1418 // code. It is the return point if an exception occurred. it jumps to
1419 // the exception blob.
1420 //
1421 // If the method gets deoptimized, the method and this code snippet
1422 // get patched.
1423 //
1424 // 1) Trampoline code gets patched into the end of this exception
1425 //   handler. the trampoline code jumps to the deoptimization blob.
1426 //
1427 // 2) The return address in the method's code will get patched such
1428 //   that it jumps to the trampoline.
1429 //
1430 // 3) The handler will get patched such that it does not jump to the
1431 //   exception blob, but to an entry in the deoptimization blob being
1432 //   aware of the exception.
1433 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1434   Register temp_reg = Z_R1;
1435   MacroAssembler _masm(&cbuf);
1436 
1437   address base = __ start_a_stub(size_exception_handler());
1438   if (base == NULL) {
1439     return 0;          // CodeBuffer::expand failed
1440   }
1441 
1442   int offset = __ offset();
1443   // Use unconditional pc-relative jump with 32-bit range here.
1444   __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin());
1445   __ z_br(temp_reg);
1446 
1447   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1448 
1449   __ end_a_stub();
1450 
1451   return offset;
1452 }
1453 
1454 // Emit deopt handler code.
1455 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1456   MacroAssembler _masm(&cbuf);
1457   address        base = __ start_a_stub(size_deopt_handler());
1458 
1459   if (base == NULL) {
1460     return 0;  // CodeBuffer::expand failed
1461   }
1462 
1463   int offset = __ offset();
1464 
1465   // Size_deopt_handler() must be exact on zarch, so for simplicity
1466   // we do not use load_const_opt here.
1467   __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1468   __ call(Z_R1);
1469   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1470 
1471   __ end_a_stub();
1472   return offset;
1473 }
1474 
1475 //=============================================================================
1476 
1477 
1478 // Given a register encoding, produce an Integer Register object.
1479 static Register reg_to_register_object(int register_encoding) {
1480   assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1481   return as_Register(register_encoding);
1482 }
1483 
1484 const bool Matcher::match_rule_supported(int opcode) {
1485   if (!has_match_rule(opcode)) return false;
1486 
1487   switch (opcode) {
1488     case Op_CountLeadingZerosI:
1489     case Op_CountLeadingZerosL:
1490     case Op_CountTrailingZerosI:
1491     case Op_CountTrailingZerosL:
1492       // Implementation requires FLOGR instruction, which is available since z9.
1493       return true;
1494 
1495     case Op_ReverseBytesI:
1496     case Op_ReverseBytesL:
1497       return UseByteReverseInstruction;
1498 
1499     // PopCount supported by H/W from z/Architecture G5 (z196) on.
1500     case Op_PopCountI:
1501     case Op_PopCountL:
1502       return UsePopCountInstruction && VM_Version::has_PopCount();
1503 
1504     case Op_StrComp:
1505       return SpecialStringCompareTo;
1506     case Op_StrEquals:
1507       return SpecialStringEquals;
1508     case Op_StrIndexOf:
1509     case Op_StrIndexOfChar:
1510       return SpecialStringIndexOf;
1511 
1512     case Op_GetAndAddI:
1513     case Op_GetAndAddL:
1514       return true;
1515       // return VM_Version::has_AtomicMemWithImmALUOps();
1516     case Op_GetAndSetI:
1517     case Op_GetAndSetL:
1518     case Op_GetAndSetP:
1519     case Op_GetAndSetN:
1520       return true;  // General CAS implementation, always available.
1521 
1522     default:
1523       return true;  // Per default match rules are supported.
1524                     // BUT: make sure match rule is not disabled by a false predicate!
1525   }
1526 
1527   return true;  // Per default match rules are supported.
1528                 // BUT: make sure match rule is not disabled by a false predicate!
1529 }
1530 
1531 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1532   // TODO
1533   // Identify extra cases that we might want to provide match rules for
1534   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen.
1535   bool ret_value = match_rule_supported(opcode);
1536   // Add rules here.
1537 
1538   return ret_value;  // Per default match rules are supported.
1539 }
1540 
1541 int Matcher::regnum_to_fpu_offset(int regnum) {
1542   ShouldNotReachHere();
1543   return regnum - 32; // The FP registers are in the second chunk.
1544 }
1545 
1546 const bool Matcher::has_predicated_vectors(void) {
1547   return false;
1548 }
1549 
1550 const int Matcher::float_pressure(int default_pressure_threshold) {
1551   return default_pressure_threshold;
1552 }
1553 
1554 const bool Matcher::convL2FSupported(void) {
1555   return true; // False means that conversion is done by runtime call.
1556 }
1557 
1558 //----------SUPERWORD HELPERS----------------------------------------
1559 
1560 // Vector width in bytes.
1561 const int Matcher::vector_width_in_bytes(BasicType bt) {
1562   assert(MaxVectorSize == 8, "");
1563   return 8;
1564 }
1565 
1566 // Vector ideal reg.
1567 const int Matcher::vector_ideal_reg(int size) {
1568   assert(MaxVectorSize == 8 && size == 8, "");
1569   return Op_RegL;
1570 }
1571 
1572 // Limits on vector size (number of elements) loaded into vector.
1573 const int Matcher::max_vector_size(const BasicType bt) {
1574   assert(is_java_primitive(bt), "only primitive type vectors");
1575   return vector_width_in_bytes(bt)/type2aelembytes(bt);
1576 }
1577 
1578 const int Matcher::min_vector_size(const BasicType bt) {
1579   return max_vector_size(bt); // Same as max.
1580 }
1581 
1582 const int Matcher::vector_shift_count_ideal_reg(int size) {
1583   fatal("vector shift is not supported");
1584   return Node::NotAMachineReg;
1585 }
1586 
1587 // z/Architecture does support misaligned store/load at minimal extra cost.
1588 const bool Matcher::misaligned_vectors_ok() {
1589   return true;
1590 }
1591 
1592 // Not yet ported to z/Architecture.
1593 const bool Matcher::pass_original_key_for_aes() {
1594   return false;
1595 }
1596 
1597 // RETURNS: whether this branch offset is short enough that a short
1598 // branch can be used.
1599 //
1600 // If the platform does not provide any short branch variants, then
1601 // this method should return `false' for offset 0.
1602 //
1603 // `Compile::Fill_buffer' will decide on basis of this information
1604 // whether to do the pass `Compile::Shorten_branches' at all.
1605 //
1606 // And `Compile::Shorten_branches' will decide on basis of this
1607 // information whether to replace particular branch sites by short
1608 // ones.
1609 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1610   // On zarch short branches use a 16 bit signed immediate that
1611   // is the pc-relative offset in halfword (= 2 bytes) units.
1612   return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1613 }
1614 
1615 const bool Matcher::isSimpleConstant64(jlong value) {
1616   // Probably always true, even if a temp register is required.
1617   return true;
1618 }
1619 
1620 // Should correspond to setting above
1621 const bool Matcher::init_array_count_is_in_bytes = false;
1622 
1623 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1624 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; }
1625 
1626 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1627 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1628 
1629 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)?
1630 const bool Matcher::require_postalloc_expand = false;
1631 
1632 // Do we need to mask the count passed to shift instructions or does
1633 // the cpu only look at the lower 5/6 bits anyway?
1634 // 32bit shifts mask in emitter, 64bit shifts need no mask.
1635 // Constant shift counts are handled in Ideal phase.
1636 const bool Matcher::need_masked_shift_count = false;
1637 
1638 // Set this as clone_shift_expressions.
1639 bool Matcher::narrow_oop_use_complex_address() {
1640   if (Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0) return true;
1641   return false;
1642 }
1643 
1644 bool Matcher::narrow_klass_use_complex_address() {
1645   NOT_LP64(ShouldNotCallThis());
1646   assert(UseCompressedClassPointers, "only for compressed klass code");
1647   // TODO HS25: z port if (MatchDecodeNodes) return true;
1648   return false;
1649 }
1650 
1651 bool Matcher::const_oop_prefer_decode() {
1652   // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1653   return Universe::narrow_oop_base() == NULL;
1654 }
1655 
1656 bool Matcher::const_klass_prefer_decode() {
1657   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1658   return Universe::narrow_klass_base() == NULL;
1659 }
1660 
1661 // Is it better to copy float constants, or load them directly from memory?
1662 // Most RISCs will have to materialize an address into a
1663 // register first, so they would do better to copy the constant from stack.
1664 const bool Matcher::rematerialize_float_constants = false;
1665 
1666 // If CPU can load and store mis-aligned doubles directly then no fixup is
1667 // needed. Else we split the double into 2 integer pieces and move it
1668 // piece-by-piece. Only happens when passing doubles into C code as the
1669 // Java calling convention forces doubles to be aligned.
1670 const bool Matcher::misaligned_doubles_ok = true;
1671 
1672 // Advertise here if the CPU requires explicit rounding operations
1673 // to implement the UseStrictFP mode.
1674 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1675 
1676 // Do floats take an entire double register or just half?
1677 //
1678 // A float in resides in a zarch double register. When storing it by
1679 // z_std, it cannot be restored in C-code by reloading it as a double
1680 // and casting it into a float afterwards.
1681 bool Matcher::float_in_double() { return false; }
1682 
1683 // Do ints take an entire long register or just half?
1684 // The relevant question is how the int is callee-saved:
1685 // the whole long is written but de-opt'ing will have to extract
1686 // the relevant 32 bits.
1687 const bool Matcher::int_in_long = true;
1688 
1689 // Constants for c2c and c calling conventions.
1690 
1691 const MachRegisterNumbers z_iarg_reg[5] = {
1692   Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1693 };
1694 
1695 const MachRegisterNumbers z_farg_reg[4] = {
1696   Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1697 };
1698 
1699 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1700 
1701 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1702 
1703 // Return whether or not this register is ever used as an argument. This
1704 // function is used on startup to build the trampoline stubs in generateOptoStub.
1705 // Registers not mentioned will be killed by the VM call in the trampoline, and
1706 // arguments in those registers not be available to the callee.
1707 bool Matcher::can_be_java_arg(int reg) {
1708   // We return true for all registers contained in z_iarg_reg[] and
1709   // z_farg_reg[] and their virtual halves.
1710   // We must include the virtual halves in order to get STDs and LDs
1711   // instead of STWs and LWs in the trampoline stubs.
1712 
1713   if (reg == Z_R2_num || reg == Z_R2_H_num ||
1714       reg == Z_R3_num || reg == Z_R3_H_num ||
1715       reg == Z_R4_num || reg == Z_R4_H_num ||
1716       reg == Z_R5_num || reg == Z_R5_H_num ||
1717       reg == Z_R6_num || reg == Z_R6_H_num) {
1718     return true;
1719   }
1720 
1721   if (reg == Z_F0_num || reg == Z_F0_H_num ||
1722       reg == Z_F2_num || reg == Z_F2_H_num ||
1723       reg == Z_F4_num || reg == Z_F4_H_num ||
1724       reg == Z_F6_num || reg == Z_F6_H_num) {
1725     return true;
1726   }
1727 
1728   return false;
1729 }
1730 
1731 bool Matcher::is_spillable_arg(int reg) {
1732   return can_be_java_arg(reg);
1733 }
1734 
1735 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
1736   return false;
1737 }
1738 
1739 // Register for DIVI projection of divmodI
1740 RegMask Matcher::divI_proj_mask() {
1741   return _Z_RARG4_INT_REG_mask;
1742 }
1743 
1744 // Register for MODI projection of divmodI
1745 RegMask Matcher::modI_proj_mask() {
1746   return _Z_RARG3_INT_REG_mask;
1747 }
1748 
1749 // Register for DIVL projection of divmodL
1750 RegMask Matcher::divL_proj_mask() {
1751   return _Z_RARG4_LONG_REG_mask;
1752 }
1753 
1754 // Register for MODL projection of divmodL
1755 RegMask Matcher::modL_proj_mask() {
1756   return _Z_RARG3_LONG_REG_mask;
1757 }
1758 
1759 // Copied from sparc.
1760 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1761   return RegMask();
1762 }
1763 
1764 const bool Matcher::convi2l_type_required = true;
1765 
1766 // Should the Matcher clone shifts on addressing modes, expecting them
1767 // to be subsumed into complex addressing expressions or compute them
1768 // into registers?
1769 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1770   return clone_base_plus_offset_address(m, mstack, address_visited);
1771 }
1772 
1773 void Compile::reshape_address(AddPNode* addp) {
1774 }
1775 
1776 %} // source
1777 
1778 //----------ENCODING BLOCK-----------------------------------------------------
1779 // This block specifies the encoding classes used by the compiler to output
1780 // byte streams. Encoding classes are parameterized macros used by
1781 // Machine Instruction Nodes in order to generate the bit encoding of the
1782 // instruction. Operands specify their base encoding interface with the
1783 // interface keyword. There are currently supported four interfaces,
1784 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1785 // operand to generate a function which returns its register number when
1786 // queried. CONST_INTER causes an operand to generate a function which
1787 // returns the value of the constant when queried. MEMORY_INTER causes an
1788 // operand to generate four functions which return the Base Register, the
1789 // Index Register, the Scale Value, and the Offset Value of the operand when
1790 // queried. COND_INTER causes an operand to generate six functions which
1791 // return the encoding code (ie - encoding bits for the instruction)
1792 // associated with each basic boolean condition for a conditional instruction.
1793 //
1794 // Instructions specify two basic values for encoding. Again, a function
1795 // is available to check if the constant displacement is an oop. They use the
1796 // ins_encode keyword to specify their encoding classes (which must be
1797 // a sequence of enc_class names, and their parameters, specified in
1798 // the encoding block), and they use the
1799 // opcode keyword to specify, in order, their primary, secondary, and
1800 // tertiary opcode. Only the opcode sections which a particular instruction
1801 // needs for encoding need to be specified.
1802 encode %{
1803   enc_class enc_unimplemented %{
1804     MacroAssembler _masm(&cbuf);
1805     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
1806   %}
1807 
1808   enc_class enc_untested %{
1809 #ifdef ASSERT
1810     MacroAssembler _masm(&cbuf);
1811     __ untested("Untested mach node encoding in AD file.");
1812 #endif
1813   %}
1814 
1815   enc_class z_rrform(iRegI dst, iRegI src) %{
1816     assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
1817     assert( ($primary >> 16)         == 0, "Instruction format error");
1818     z_emit16(cbuf, $primary |
1819              Assembler::reg($dst$$reg,8,16) |
1820              Assembler::reg($src$$reg,12,16));
1821   %}
1822 
1823   enc_class z_rreform(iRegI dst1, iRegI src2) %{
1824     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1825     z_emit32(cbuf, $primary |
1826              Assembler::reg($dst1$$reg,24,32) |
1827              Assembler::reg($src2$$reg,28,32));
1828   %}
1829 
1830   enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
1831     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1832     z_emit32(cbuf, $primary |
1833              Assembler::reg($dst1$$reg,24,32) |
1834              Assembler::reg($src2$$reg,28,32) |
1835              Assembler::reg($src3$$reg,16,32));
1836   %}
1837 
1838   enc_class z_riform_signed(iRegI dst, immI16 src) %{
1839     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1840     z_emit32(cbuf, $primary |
1841              Assembler::reg($dst$$reg,8,32) |
1842              Assembler::simm16($src$$constant,16,32));
1843   %}
1844 
1845   enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
1846     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1847     z_emit32(cbuf, $primary |
1848              Assembler::reg($dst$$reg,8,32) |
1849              Assembler::uimm16($src$$constant,16,32));
1850   %}
1851 
1852   enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
1853     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1854     z_emit48(cbuf, $primary |
1855              Assembler::reg($dst1$$reg,8,48) |
1856              Assembler::reg($src3$$reg,12,48) |
1857              Assembler::simm16($src2$$constant,16,48));
1858   %}
1859 
1860   enc_class z_rilform_signed(iRegI dst, immL32 src) %{
1861     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1862     z_emit48(cbuf, $primary |
1863              Assembler::reg($dst$$reg,8,48) |
1864              Assembler::simm32($src$$constant,16,48));
1865   %}
1866 
1867   enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
1868     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1869     z_emit48(cbuf, $primary |
1870              Assembler::reg($dst$$reg,8,48) |
1871              Assembler::uimm32($src$$constant,16,48));
1872   %}
1873 
1874   enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
1875     z_emit48(cbuf, $primary |
1876              Assembler::reg($dst$$reg,8,48) |
1877              Assembler::reg($src1$$reg,12,48) |
1878              Assembler::simm20($src2$$constant));
1879   %}
1880 
1881   enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
1882     z_emit48(cbuf, $primary |
1883              Assembler::reg($dst$$reg,8,48) |
1884              Assembler::reg($src$$reg,12,48) |
1885              Assembler::reg($shft$$reg,16,48) |
1886              Assembler::simm20(0));
1887   %}
1888 
1889   enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1890     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1891     z_emit32(cbuf, $primary |
1892              Assembler::reg($dst$$reg,8,32) |
1893              Assembler::reg($src1$$reg,12,32) |
1894              Assembler::reg($src2$$reg,16,32) |
1895              Assembler::uimm12($con$$constant,20,32));
1896   %}
1897 
1898   enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
1899     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1900     z_emit32(cbuf, $primary |
1901              Assembler::reg($dst$$reg,8,32) |
1902              Assembler::reg($src$$reg,16,32) |
1903              Assembler::uimm12($con$$constant,20,32));
1904   %}
1905 
1906   enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1907     z_emit48(cbuf, $primary |
1908              Assembler::reg($dst$$reg,8,48) |
1909              Assembler::reg($src1$$reg,12,48) |
1910              Assembler::reg($src2$$reg,16,48) |
1911              Assembler::simm20($con$$constant));
1912   %}
1913 
1914   enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
1915     z_emit48(cbuf, $primary |
1916              Assembler::reg($dst$$reg,8,48) |
1917              Assembler::reg($src$$reg,16,48) |
1918              Assembler::simm20($con$$constant));
1919   %}
1920 
1921   // Direct memory arithmetic.
1922   enc_class z_siyform(memoryRSY mem, immI8 src) %{
1923     int      disp = $mem$$disp;
1924     Register base = reg_to_register_object($mem$$base);
1925     int      con  = $src$$constant;
1926 
1927     assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
1928     z_emit_inst(cbuf, $primary |
1929                 Assembler::regz(base,16,48) |
1930                 Assembler::simm20(disp) |
1931                 Assembler::simm8(con,8,48));
1932   %}
1933 
1934   enc_class z_silform(memoryRS mem, immI16 src) %{
1935     z_emit_inst(cbuf, $primary |
1936                 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
1937                 Assembler::uimm12($mem$$disp,20,48) |
1938                 Assembler::simm16($src$$constant,32,48));
1939   %}
1940 
1941   // Encoder for FP ALU reg/mem instructions (support only short displacements).
1942   enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
1943     Register Ridx = $mem$$index$$Register;
1944     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1945     if ($primary > (1L << 32)) {
1946       z_emit_inst(cbuf, $primary |
1947                   Assembler::reg($dst$$reg, 8, 48) |
1948                   Assembler::uimm12($mem$$disp, 20, 48) |
1949                   Assembler::reg(Ridx, 12, 48) |
1950                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1951     } else {
1952       z_emit_inst(cbuf, $primary |
1953                   Assembler::reg($dst$$reg, 8, 32) |
1954                   Assembler::uimm12($mem$$disp, 20, 32) |
1955                   Assembler::reg(Ridx, 12, 32) |
1956                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1957     }
1958   %}
1959 
1960   enc_class z_form_rt_mem(iRegI dst, memory mem) %{
1961     Register Ridx = $mem$$index$$Register;
1962     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1963     if ($primary > (1L<<32)) {
1964       z_emit_inst(cbuf, $primary |
1965                   Assembler::reg($dst$$reg, 8, 48) |
1966                   Assembler::simm20($mem$$disp) |
1967                   Assembler::reg(Ridx, 12, 48) |
1968                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1969     } else {
1970       z_emit_inst(cbuf, $primary |
1971                   Assembler::reg($dst$$reg, 8, 32) |
1972                   Assembler::uimm12($mem$$disp, 20, 32) |
1973                   Assembler::reg(Ridx, 12, 32) |
1974                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1975     }
1976   %}
1977 
1978   enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
1979     int isize = $secondary > 1L << 32 ? 48 : 32;
1980     Register Ridx = $mem$$index$$Register;
1981     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1982 
1983     if (Displacement::is_shortDisp((long)$mem$$disp)) {
1984       z_emit_inst(cbuf, $secondary |
1985                   Assembler::reg($dst$$reg, 8, isize) |
1986                   Assembler::uimm12($mem$$disp, 20, isize) |
1987                   Assembler::reg(Ridx, 12, isize) |
1988                   Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
1989     } else if (Displacement::is_validDisp((long)$mem$$disp)) {
1990       z_emit_inst(cbuf, $primary |
1991                   Assembler::reg($dst$$reg, 8, 48) |
1992                   Assembler::simm20($mem$$disp) |
1993                   Assembler::reg(Ridx, 12, 48) |
1994                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1995     } else {
1996         MacroAssembler _masm(&cbuf);
1997         __ load_const_optimized(Z_R1_scratch, $mem$$disp);
1998         if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
1999         z_emit_inst(cbuf, $secondary |
2000                     Assembler::reg($dst$$reg, 8, isize) |
2001                     Assembler::uimm12(0, 20, isize) |
2002                     Assembler::reg(Z_R1_scratch, 12, isize) |
2003                     Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2004     }
2005   %}
2006 
2007   enc_class z_enc_brul(Label lbl) %{
2008     MacroAssembler _masm(&cbuf);
2009     Label* p = $lbl$$label;
2010 
2011     // 'p' is `NULL' when this encoding class is used only to
2012     // determine the size of the encoded instruction.
2013     // Use a bound dummy label in that case.
2014     Label d;
2015     __ bind(d);
2016     Label& l = (NULL == p) ? d : *(p);
2017     __ z_brul(l);
2018   %}
2019 
2020   enc_class z_enc_bru(Label lbl) %{
2021     MacroAssembler _masm(&cbuf);
2022     Label* p = $lbl$$label;
2023 
2024     // 'p' is `NULL' when this encoding class is used only to
2025     // determine the size of the encoded instruction.
2026     // Use a bound dummy label in that case.
2027     Label d;
2028     __ bind(d);
2029     Label& l = (NULL == p) ? d : *(p);
2030     __ z_bru(l);
2031   %}
2032 
2033   enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2034     MacroAssembler _masm(&cbuf);
2035     Label* p = $lbl$$label;
2036 
2037     // 'p' is `NULL' when this encoding class is used only to
2038     // determine the size of the encoded instruction.
2039     // Use a bound dummy label in that case.
2040     Label d;
2041     __ bind(d);
2042     Label& l = (NULL == p) ? d : *(p);
2043     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2044   %}
2045 
2046   enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2047     MacroAssembler _masm(&cbuf);
2048     Label* p = $lbl$$label;
2049 
2050     // 'p' is `NULL' when this encoding class is used only to
2051     // determine the size of the encoded instruction.
2052     // Use a bound dummy label in that case.
2053     Label d;
2054     __ bind(d);
2055     Label& l = (NULL == p) ? d : *(p);
2056     __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2057   %}
2058 
2059   enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2060     MacroAssembler _masm(&cbuf);
2061     Label* p = $lbl$$label;
2062 
2063     // 'p' is `NULL' when this encoding class is used only to
2064     // determine the size of the encoded instruction.
2065     // Use a bound dummy label in that case.
2066     Label d;
2067     __ bind(d);
2068     Label& l = (NULL == p) ? d : *(p);
2069     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2070     unsigned long instr = $primary;
2071     if (instr == CRJ_ZOPC) {
2072       __ z_crj($src1$$Register, $src2$$Register, cc, l);
2073     } else if (instr == CLRJ_ZOPC) {
2074       __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2075     } else if (instr == CGRJ_ZOPC) {
2076       __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2077     } else {
2078       guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2079       __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2080     }
2081   %}
2082 
2083   enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2084     MacroAssembler _masm(&cbuf);
2085     Label* p = $lbl$$label;
2086 
2087     // 'p' is `NULL' when this encoding class is used only to
2088     // determine the size of the encoded instruction.
2089     // Use a bound dummy label in that case.
2090     Label d;
2091     __ bind(d);
2092     Label& l = (NULL == p) ? d : *(p);
2093 
2094     unsigned long instr = $primary;
2095     if (instr == CR_ZOPC) {
2096       __ z_cr($src1$$Register, $src2$$Register);
2097     } else if (instr == CLR_ZOPC) {
2098       __ z_clr($src1$$Register, $src2$$Register);
2099     } else if (instr == CGR_ZOPC) {
2100       __ z_cgr($src1$$Register, $src2$$Register);
2101     } else {
2102       guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2103       __ z_clgr($src1$$Register, $src2$$Register);
2104     }
2105 
2106     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2107   %}
2108 
2109   enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2110     MacroAssembler _masm(&cbuf);
2111     Label* p = $lbl$$label;
2112 
2113     // 'p' is `NULL' when this encoding class is used only to
2114     // determine the size of the encoded instruction.
2115     // Use a bound dummy label in that case.
2116     Label d;
2117     __ bind(d);
2118     Label& l = (NULL == p) ? d : *(p);
2119 
2120     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2121     unsigned long instr = $primary;
2122     if (instr == CIJ_ZOPC) {
2123       __ z_cij($src1$$Register, $src2$$constant, cc, l);
2124     } else if (instr == CLIJ_ZOPC) {
2125       __ z_clij($src1$$Register, $src2$$constant, cc, l);
2126     } else if (instr == CGIJ_ZOPC) {
2127       __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2128     } else {
2129       guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2130       __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2131     }
2132   %}
2133 
2134   enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2135     MacroAssembler _masm(&cbuf);
2136     Label* p = $lbl$$label;
2137 
2138     // 'p' is `NULL' when this encoding class is used only to
2139     // determine the size of the encoded instruction.
2140     // Use a bound dummy label in that case.
2141     Label d;
2142     __ bind(d);
2143     Label& l = (NULL == p) ? d : *(p);
2144 
2145     unsigned long instr = $primary;
2146     if (instr == CHI_ZOPC) {
2147       __ z_chi($src1$$Register, $src2$$constant);
2148     } else if (instr == CLFI_ZOPC) {
2149       __ z_clfi($src1$$Register, $src2$$constant);
2150     } else if (instr == CGHI_ZOPC) {
2151       __ z_cghi($src1$$Register, $src2$$constant);
2152     } else {
2153       guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2154       __ z_clgfi($src1$$Register, $src2$$constant);
2155     }
2156 
2157     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2158   %}
2159 
2160   // Call from Java to runtime.
2161   enc_class z_enc_java_to_runtime_call(method meth) %{
2162     MacroAssembler _masm(&cbuf);
2163 
2164     // Save return pc before call to the place where we need it, since
2165     // callee doesn't.
2166     unsigned int start_off = __ offset();
2167     // Compute size of "larl + stg + call_c_opt".
2168     const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
2169     __ get_PC(Z_R14, size_of_code);
2170     __ save_return_pc();
2171     assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2172 
2173     assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2174     address call_addr = __ call_c_opt((address)$meth$$method);
2175     if (call_addr == NULL) {
2176       Compile::current()->env()->record_out_of_memory_failure();
2177       return;
2178     }
2179 
2180 #ifdef ASSERT
2181     // Plausibility check for size_of_code assumptions.
2182     unsigned int actual_ret_off = __ offset();
2183     assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
2184 #endif
2185   %}
2186 
2187   enc_class z_enc_java_static_call(method meth) %{
2188     // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2189     // whom we intended to call.
2190     MacroAssembler _masm(&cbuf);
2191     int ret_offset = 0;
2192 
2193     if (!_method) {
2194       ret_offset = emit_call_reloc(_masm, $meth$$method,
2195                                    relocInfo::runtime_call_w_cp_type, ra_);
2196     } else {
2197       int method_index = resolved_method_index(cbuf);
2198       if (_optimized_virtual) {
2199         ret_offset = emit_call_reloc(_masm, $meth$$method,
2200                                      opt_virtual_call_Relocation::spec(method_index));
2201       } else {
2202         ret_offset = emit_call_reloc(_masm, $meth$$method,
2203                                      static_call_Relocation::spec(method_index));
2204       }
2205     }
2206     assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()");
2207 
2208     if (_method) { // Emit stub for static call.
2209       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2210       if (stub == NULL) {
2211         ciEnv::current()->record_failure("CodeCache is full");
2212         return;
2213       }
2214     }
2215   %}
2216 
2217   // Java dynamic call
2218   enc_class z_enc_java_dynamic_call(method meth) %{
2219     MacroAssembler _masm(&cbuf);
2220     unsigned int start_off = __ offset();
2221 
2222     int vtable_index = this->_vtable_index;
2223     if (vtable_index == -4) {
2224       Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2225       address virtual_call_oop_addr = NULL;
2226 
2227       AddressLiteral empty_ic((address) Universe::non_oop_word());
2228       virtual_call_oop_addr = __ pc();
2229       bool success = __ load_const_from_toc(ic_reg, empty_ic);
2230       if (!success) {
2231         Compile::current()->env()->record_out_of_memory_failure();
2232         return;
2233       }
2234 
2235       // Call to fixup routine. Fixup routine uses ScopeDesc info
2236       // to determine who we intended to call.
2237       int method_index = resolved_method_index(cbuf);
2238       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2239       unsigned int ret_off = __ offset();
2240       assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2241       ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_);
2242       assert(_method, "lazy_constant may be wrong when _method==null");
2243     } else {
2244       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2245       // Go through the vtable. Get receiver klass. Receiver already
2246       // checked for non-null. If we'll go thru a C2I adapter, the
2247       // interpreter expects method in Z_method.
2248       // Use Z_method to temporarily hold the klass oop. Z_R1_scratch is destroyed
2249       // by load_heap_oop_not_null.
2250       __ load_klass(Z_method, Z_R2);
2251 
2252       int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2253       int v_off        = entry_offset + vtableEntry::method_offset_in_bytes();
2254 
2255       if (Displacement::is_validDisp(v_off) ) {
2256         // Can use load instruction with large offset.
2257         __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2258       } else {
2259         // Worse case, must load offset into register.
2260         __ load_const(Z_R1_scratch, v_off);
2261         __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2262       }
2263       // NOTE: for vtable dispatches, the vtable entry will never be
2264       // null. However it may very well end up in handle_wrong_method
2265       // if the method is abstract for the particular class.
2266       __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2267       // Call target. Either compiled code or C2I adapter.
2268       __ z_basr(Z_R14, Z_R1_scratch);
2269       unsigned int ret_off = __ offset();
2270     }
2271   %}
2272 
2273   enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2274     MacroAssembler _masm(&cbuf);
2275     Register Rdst = reg_to_register_object($dst$$reg);
2276     Register Rsrc = reg_to_register_object($src$$reg);
2277 
2278     // Don't emit code if operands are identical (same register).
2279     if (Rsrc != Rdst) {
2280       Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2281 
2282       if (VM_Version::has_LoadStoreConditional()) {
2283         __ z_locgr(Rdst, Rsrc, cc);
2284       } else {
2285         // Branch if not (cmp cr).
2286         Label done;
2287         __ z_brc(Assembler::inverse_condition(cc), done);
2288         __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2289         __ bind(done);
2290       }
2291     }
2292   %}
2293 
2294   enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2295     MacroAssembler _masm(&cbuf);
2296     Register Rdst = reg_to_register_object($dst$$reg);
2297     int      Csrc = $src$$constant;
2298     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2299     Label done;
2300     // Branch if not (cmp cr).
2301     __ z_brc(Assembler::inverse_condition(cc), done);
2302     if (Csrc == 0) {
2303       // Don't set CC.
2304       __ clear_reg(Rdst, true, false);  // Use for int, long & ptr.
2305     } else {
2306       __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2307     }
2308     __ bind(done);
2309   %}
2310 
2311   enc_class z_enc_cctobool(iRegI res) %{
2312     MacroAssembler _masm(&cbuf);
2313     Register Rres = reg_to_register_object($res$$reg);
2314 
2315     if (VM_Version::has_LoadStoreConditional()) {
2316       __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2317       __ load_const_optimized(Rres, 1L);         // true  (succeed)
2318       __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2319     } else {
2320       Label done;
2321       __ load_const_optimized(Rres, 0L); // false (failed)
2322       __ z_brne(done);                   // Assume true to be the common case.
2323       __ load_const_optimized(Rres, 1L); // true  (succeed)
2324       __ bind(done);
2325     }
2326   %}
2327 
2328   enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2329     MacroAssembler _masm(&cbuf);
2330     Register Rcomp = reg_to_register_object($compare_value$$reg);
2331     Register Rnew  = reg_to_register_object($exchange_value$$reg);
2332     Register Raddr = reg_to_register_object($addr_ptr$$reg);
2333 
2334     __ z_cs(Rcomp, Rnew, 0, Raddr);
2335   %}
2336 
2337   enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2338     MacroAssembler _masm(&cbuf);
2339     Register Rcomp = reg_to_register_object($compare_value$$reg);
2340     Register Rnew  = reg_to_register_object($exchange_value$$reg);
2341     Register Raddr = reg_to_register_object($addr_ptr$$reg);
2342 
2343     __ z_csg(Rcomp, Rnew, 0, Raddr);
2344   %}
2345 
2346   enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2347     MacroAssembler _masm(&cbuf);
2348     Register Rdst = reg_to_register_object($dst$$reg);
2349     Register Rtmp = reg_to_register_object($tmp$$reg);
2350     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2351     Label    retry;
2352 
2353     // Iterate until swap succeeds.
2354     __ z_llgf(Rtmp, $mem$$Address);  // current contents
2355     __ bind(retry);
2356       // Calculate incremented value.
2357       __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2358       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
2359     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
2360   %}
2361 
2362   enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2363     MacroAssembler _masm(&cbuf);
2364     Register Rdst = reg_to_register_object($dst$$reg);
2365     Register Rtmp = reg_to_register_object($tmp$$reg);
2366     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2367     Label    retry;
2368 
2369     // Iterate until swap succeeds.
2370     __ z_lg(Rtmp, $mem$$Address);  // current contents
2371     __ bind(retry);
2372       // Calculate incremented value.
2373       __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2374       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
2375     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
2376   %}
2377 
2378 %} // encode
2379 
2380 source %{
2381 
2382   // Check whether outs are all Stores. If so, we can omit clearing the upper
2383   // 32 bits after encoding.
2384   static bool all_outs_are_Stores(const Node *n) {
2385     for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2386       Node *out = n->fast_out(k);
2387       if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2388         // Most other outs are SpillCopy, but there are various other.
2389         // jvm98 has arond 9% Encodes where we return false.
2390         return false;
2391       }
2392     }
2393     return true;
2394   }
2395 
2396 %} // source
2397 
2398 
2399 //----------FRAME--------------------------------------------------------------
2400 // Definition of frame structure and management information.
2401 
2402 frame %{
2403   // What direction does stack grow in (assumed to be same for native & Java).
2404   stack_direction(TOWARDS_LOW);
2405 
2406   // These two registers define part of the calling convention between
2407   // compiled code and the interpreter.
2408 
2409   // Inline Cache Register
2410   inline_cache_reg(Z_R9); // Z_inline_cache
2411 
2412   // Argument pointer for I2C adapters
2413   //
2414   // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2415   // interpreter_arg_ptr_reg(Z_R6);
2416 
2417   // Temporary in compiled entry-points
2418   // compiler_method_oop_reg(Z_R1);//Z_R1_scratch
2419 
2420   // Method Oop Register when calling interpreter
2421   interpreter_method_oop_reg(Z_R9);//Z_method
2422 
2423   // Optional: name the operand used by cisc-spilling to access
2424   // [stack_pointer + offset].
2425   cisc_spilling_operand_name(indOffset12);
2426 
2427   // Number of stack slots consumed by a Monitor enter.
2428   sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2429 
2430   // Compiled code's Frame Pointer
2431   //
2432   // z/Architecture stack pointer
2433   frame_pointer(Z_R15); // Z_SP
2434 
2435   // Interpreter stores its frame pointer in a register which is
2436   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
2437   // interpreted java to compiled java.
2438   //
2439   // Z_state holds pointer to caller's cInterpreter.
2440   interpreter_frame_pointer(Z_R7); // Z_state
2441 
2442   // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2443   stack_alignment(frame::alignment_in_bytes);
2444 
2445   in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units);
2446 
2447   // A `slot' is assumed 4 bytes here!
2448   // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2449 
2450   // Number of outgoing stack slots killed above the
2451   // out_preserve_stack_slots for calls to C. Supports the var-args
2452   // backing area for register parms.
2453   varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2454 
2455   // The after-PROLOG location of the return address. Location of
2456   // return address specifies a type (REG or STACK) and a number
2457   // representing the register number (i.e. - use a register name) or
2458   // stack slot.
2459   return_addr(REG Z_R14);
2460 
2461   // This is the body of the function
2462   //
2463   // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */,
2464   //                                  uint length      /* length of array */,
2465   //                                  bool is_outgoing)
2466   //
2467   // The `sig' array is to be updated. Sig[j] represents the location
2468   // of the j-th argument, either a register or a stack slot.
2469 
2470   // Body of function which returns an integer array locating
2471   // arguments either in registers or in stack slots. Passed an array
2472   // of ideal registers called "sig" and a "length" count. Stack-slot
2473   // offsets are based on outgoing arguments, i.e. a CALLER setting up
2474   // arguments for a CALLEE. Incoming stack arguments are
2475   // automatically biased by the preserve_stack_slots field above.
2476   calling_convention %{
2477     // No difference between ingoing/outgoing just pass false.
2478     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2479   %}
2480 
2481   // Body of function which returns an integer array locating
2482   // arguments either in registers or in stack slots. Passed an array
2483   // of ideal registers called "sig" and a "length" count. Stack-slot
2484   // offsets are based on outgoing arguments, i.e. a CALLER setting up
2485   // arguments for a CALLEE. Incoming stack arguments are
2486   // automatically biased by the preserve_stack_slots field above.
2487   c_calling_convention %{
2488     // This is obviously always outgoing.
2489     // C argument must be in register AND stack slot.
2490     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2491   %}
2492 
2493   // Location of native (C/C++) and interpreter return values. This
2494   // is specified to be the same as Java. In the 32-bit VM, long
2495   // values are actually returned from native calls in O0:O1 and
2496   // returned to the interpreter in I0:I1. The copying to and from
2497   // the register pairs is done by the appropriate call and epilog
2498   // opcodes. This simplifies the register allocator.
2499   //
2500   // Use register pair for c return value.
2501   c_return_value %{
2502     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2503     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2504     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2505     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2506   %}
2507 
2508   // Use register pair for return value.
2509   // Location of compiled Java return values. Same as C
2510   return_value %{
2511     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2512     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2513     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2514     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2515   %}
2516 %}
2517 
2518 
2519 //----------ATTRIBUTES---------------------------------------------------------
2520 
2521 //----------Operand Attributes-------------------------------------------------
2522 op_attrib op_cost(1);          // Required cost attribute
2523 
2524 //----------Instruction Attributes---------------------------------------------
2525 
2526 // Cost attribute. required.
2527 ins_attrib ins_cost(DEFAULT_COST);
2528 
2529 // Is this instruction a non-matching short branch variant of some
2530 // long branch? Not required.
2531 ins_attrib ins_short_branch(0);
2532 
2533 // Indicates this is a trap based check node and final control-flow fixup
2534 // must generate a proper fall through.
2535 ins_attrib ins_is_TrapBasedCheckNode(true);
2536 
2537 // Attribute of instruction to tell how many constants the instruction will generate.
2538 // (optional attribute). Default: 0.
2539 ins_attrib ins_num_consts(0);
2540 
2541 // Required alignment attribute (must be a power of 2)
2542 // specifies the alignment that some part of the instruction (not
2543 // necessarily the start) requires. If > 1, a compute_padding()
2544 // function must be provided for the instruction.
2545 //
2546 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2547 // instructions which depend on the proper alignment, because the
2548 // desired alignment isn't guaranteed for the call to "emit()" during
2549 // the size computation.
2550 ins_attrib ins_alignment(1);
2551 
2552 // Enforce/prohibit rematerializations.
2553 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2554 //   then rematerialization of that instruction is prohibited and the
2555 //   instruction's value will be spilled if necessary.
2556 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2557 //   then rematerialization is enforced and the instruction's value will
2558 //   never get spilled. a copy of the instruction will be inserted if
2559 //   necessary.
2560 //   Note: this may result in rematerializations in front of every use.
2561 // (optional attribute)
2562 ins_attrib ins_cannot_rematerialize(false);
2563 ins_attrib ins_should_rematerialize(false);
2564 
2565 //----------OPERANDS-----------------------------------------------------------
2566 // Operand definitions must precede instruction definitions for correct
2567 // parsing in the ADLC because operands constitute user defined types
2568 // which are used in instruction definitions.
2569 
2570 //----------Simple Operands----------------------------------------------------
2571 // Immediate Operands
2572 // Please note:
2573 // Formats are generated automatically for constants and base registers.
2574 
2575 //----------------------------------------------
2576 // SIGNED (shorter than INT) immediate operands
2577 //----------------------------------------------
2578 
2579 // Byte Immediate: constant 'int -1'
2580 operand immB_minus1() %{
2581   //         sign-ext constant      zero-ext constant
2582   predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2583   match(ConI);
2584   op_cost(1);
2585   format %{ %}
2586   interface(CONST_INTER);
2587 %}
2588 
2589 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2590 operand immB_n0m1() %{
2591   //                             sign-ext constant     zero-ext constant
2592   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2593   match(ConI);
2594   op_cost(1);
2595   format %{ %}
2596   interface(CONST_INTER);
2597 %}
2598 
2599 // Short Immediate: constant 'int -1'
2600 operand immS_minus1() %{
2601   //         sign-ext constant      zero-ext constant
2602   predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2603   match(ConI);
2604   op_cost(1);
2605   format %{ %}
2606   interface(CONST_INTER);
2607 %}
2608 
2609 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2610 operand immS_n0m1() %{
2611   //                             sign-ext constant     zero-ext constant
2612   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2613   match(ConI);
2614   op_cost(1);
2615   format %{ %}
2616   interface(CONST_INTER);
2617 %}
2618 
2619 //-----------------------------------------
2620 //  SIGNED INT immediate operands
2621 //-----------------------------------------
2622 
2623 // Integer Immediate: 32-bit
2624 operand immI() %{
2625   match(ConI);
2626   op_cost(1);
2627   format %{ %}
2628   interface(CONST_INTER);
2629 %}
2630 
2631 // Int Immediate: 20-bit
2632 operand immI20() %{
2633   predicate(Immediate::is_simm20(n->get_int()));
2634   match(ConI);
2635   op_cost(1);
2636   format %{ %}
2637   interface(CONST_INTER);
2638 %}
2639 
2640 // Integer Immediate: 16-bit
2641 operand immI16() %{
2642   predicate(Immediate::is_simm16(n->get_int()));
2643   match(ConI);
2644   op_cost(1);
2645   format %{ %}
2646   interface(CONST_INTER);
2647 %}
2648 
2649 // Integer Immediate: 8-bit
2650 operand immI8() %{
2651   predicate(Immediate::is_simm8(n->get_int()));
2652   match(ConI);
2653   op_cost(1);
2654   format %{ %}
2655   interface(CONST_INTER);
2656 %}
2657 
2658 // Integer Immediate: constant 'int 0'
2659 operand immI_0() %{
2660   predicate(n->get_int() == 0);
2661   match(ConI);
2662   op_cost(1);
2663   format %{ %}
2664   interface(CONST_INTER);
2665 %}
2666 
2667 // Integer Immediate: constant 'int -1'
2668 operand immI_minus1() %{
2669   predicate(n->get_int() == -1);
2670   match(ConI);
2671   op_cost(1);
2672   format %{ %}
2673   interface(CONST_INTER);
2674 %}
2675 
2676 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2677 operand immI_n0m1() %{
2678   predicate(n->get_int() != 0 && n->get_int() != -1);
2679   match(ConI);
2680   op_cost(1);
2681   format %{ %}
2682   interface(CONST_INTER);
2683 %}
2684 
2685 //-------------------------------------------
2686 // UNSIGNED INT immediate operands
2687 //-------------------------------------------
2688 
2689 // Unsigned Integer Immediate: 32-bit
2690 operand uimmI() %{
2691   match(ConI);
2692   op_cost(1);
2693   format %{ %}
2694   interface(CONST_INTER);
2695 %}
2696 
2697 // Unsigned Integer Immediate: 16-bit
2698 operand uimmI16() %{
2699   predicate(Immediate::is_uimm16(n->get_int()));
2700   match(ConI);
2701   op_cost(1);
2702   format %{ %}
2703   interface(CONST_INTER);
2704 %}
2705 
2706 // Unsigned Integer Immediate: 12-bit
2707 operand uimmI12() %{
2708   predicate(Immediate::is_uimm12(n->get_int()));
2709   match(ConI);
2710   op_cost(1);
2711   format %{ %}
2712   interface(CONST_INTER);
2713 %}
2714 
2715 // Unsigned Integer Immediate: 12-bit
2716 operand uimmI8() %{
2717   predicate(Immediate::is_uimm8(n->get_int()));
2718   match(ConI);
2719   op_cost(1);
2720   format %{ %}
2721   interface(CONST_INTER);
2722 %}
2723 
2724 // Integer Immediate: 6-bit
2725 operand uimmI6() %{
2726   predicate(Immediate::is_uimm(n->get_int(), 6));
2727   match(ConI);
2728   op_cost(1);
2729   format %{ %}
2730   interface(CONST_INTER);
2731 %}
2732 
2733 // Integer Immediate: 5-bit
2734 operand uimmI5() %{
2735   predicate(Immediate::is_uimm(n->get_int(), 5));
2736   match(ConI);
2737   op_cost(1);
2738   format %{ %}
2739   interface(CONST_INTER);
2740 %}
2741 
2742 // Length for SS instructions, given in DWs,
2743 //   possible range [1..512], i.e. [8..4096] Bytes
2744 //   used     range [1..256], i.e. [8..2048] Bytes
2745 //   operand type int
2746 // Unsigned Integer Immediate: 9-bit
2747 operand SSlenDW() %{
2748   predicate(Immediate::is_uimm8(n->get_long()-1));
2749   match(ConL);
2750   op_cost(1);
2751   format %{ %}
2752   interface(CONST_INTER);
2753 %}
2754 
2755 //------------------------------------------
2756 // (UN)SIGNED INT specific values
2757 //------------------------------------------
2758 
2759 // Integer Immediate: the value 1
2760 operand immI_1() %{
2761   predicate(n->get_int() == 1);
2762   match(ConI);
2763   op_cost(1);
2764   format %{ %}
2765   interface(CONST_INTER);
2766 %}
2767 
2768 // Integer Immediate: the value 16.
2769 operand immI_16() %{
2770   predicate(n->get_int() == 16);
2771   match(ConI);
2772   op_cost(1);
2773   format %{ %}
2774   interface(CONST_INTER);
2775 %}
2776 
2777 // Integer Immediate: the value 24.
2778 operand immI_24() %{
2779   predicate(n->get_int() == 24);
2780   match(ConI);
2781   op_cost(1);
2782   format %{ %}
2783   interface(CONST_INTER);
2784 %}
2785 
2786 // Integer Immediate: the value 255
2787 operand immI_255() %{
2788   predicate(n->get_int() == 255);
2789   match(ConI);
2790   op_cost(1);
2791   format %{ %}
2792   interface(CONST_INTER);
2793 %}
2794 
2795 // Integer Immediate: the values 32-63
2796 operand immI_32_63() %{
2797   predicate(n->get_int() >= 32 && n->get_int() <= 63);
2798   match(ConI);
2799   op_cost(1);
2800   format %{ %}
2801   interface(CONST_INTER);
2802 %}
2803 
2804 // Unsigned Integer Immediate: LL-part, extended by 1s.
2805 operand uimmI_LL1() %{
2806   predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
2807   match(ConI);
2808   op_cost(1);
2809   format %{ %}
2810   interface(CONST_INTER);
2811 %}
2812 
2813 // Unsigned Integer Immediate: LH-part, extended by 1s.
2814 operand uimmI_LH1() %{
2815   predicate((n->get_int() & 0xFFFF) == 0xFFFF);
2816   match(ConI);
2817   op_cost(1);
2818   format %{ %}
2819   interface(CONST_INTER);
2820 %}
2821 
2822 //------------------------------------------
2823 // SIGNED LONG immediate operands
2824 //------------------------------------------
2825 
2826 operand immL() %{
2827   match(ConL);
2828   op_cost(1);
2829   format %{ %}
2830   interface(CONST_INTER);
2831 %}
2832 
2833 // Long Immediate: 32-bit
2834 operand immL32() %{
2835   predicate(Immediate::is_simm32(n->get_long()));
2836   match(ConL);
2837   op_cost(1);
2838   format %{ %}
2839   interface(CONST_INTER);
2840 %}
2841 
2842 // Long Immediate: 20-bit
2843 operand immL20() %{
2844   predicate(Immediate::is_simm20(n->get_long()));
2845   match(ConL);
2846   op_cost(1);
2847   format %{ %}
2848   interface(CONST_INTER);
2849 %}
2850 
2851 // Long Immediate: 16-bit
2852 operand immL16() %{
2853   predicate(Immediate::is_simm16(n->get_long()));
2854   match(ConL);
2855   op_cost(1);
2856   format %{ %}
2857   interface(CONST_INTER);
2858 %}
2859 
2860 // Long Immediate: 8-bit
2861 operand immL8() %{
2862   predicate(Immediate::is_simm8(n->get_long()));
2863   match(ConL);
2864   op_cost(1);
2865   format %{ %}
2866   interface(CONST_INTER);
2867 %}
2868 
2869 //--------------------------------------------
2870 // UNSIGNED LONG immediate operands
2871 //--------------------------------------------
2872 
2873 operand uimmL32() %{
2874   predicate(Immediate::is_uimm32(n->get_long()));
2875   match(ConL);
2876   op_cost(1);
2877   format %{ %}
2878   interface(CONST_INTER);
2879 %}
2880 
2881 // Unsigned Long Immediate: 16-bit
2882 operand uimmL16() %{
2883   predicate(Immediate::is_uimm16(n->get_long()));
2884   match(ConL);
2885   op_cost(1);
2886   format %{ %}
2887   interface(CONST_INTER);
2888 %}
2889 
2890 // Unsigned Long Immediate: 12-bit
2891 operand uimmL12() %{
2892   predicate(Immediate::is_uimm12(n->get_long()));
2893   match(ConL);
2894   op_cost(1);
2895   format %{ %}
2896   interface(CONST_INTER);
2897 %}
2898 
2899 // Unsigned Long Immediate: 8-bit
2900 operand uimmL8() %{
2901   predicate(Immediate::is_uimm8(n->get_long()));
2902   match(ConL);
2903   op_cost(1);
2904   format %{ %}
2905   interface(CONST_INTER);
2906 %}
2907 
2908 //-------------------------------------------
2909 // (UN)SIGNED LONG specific values
2910 //-------------------------------------------
2911 
2912 // Long Immediate: the value FF
2913 operand immL_FF() %{
2914   predicate(n->get_long() == 0xFFL);
2915   match(ConL);
2916   op_cost(1);
2917   format %{ %}
2918   interface(CONST_INTER);
2919 %}
2920 
2921 // Long Immediate: the value FFFF
2922 operand immL_FFFF() %{
2923   predicate(n->get_long() == 0xFFFFL);
2924   match(ConL);
2925   op_cost(1);
2926   format %{ %}
2927   interface(CONST_INTER);
2928 %}
2929 
2930 // Long Immediate: the value FFFFFFFF
2931 operand immL_FFFFFFFF() %{
2932   predicate(n->get_long() == 0xFFFFFFFFL);
2933   match(ConL);
2934   op_cost(1);
2935   format %{ %}
2936   interface(CONST_INTER);
2937 %}
2938 
2939 operand immL_0() %{
2940   predicate(n->get_long() == 0L);
2941   match(ConL);
2942   op_cost(1);
2943   format %{ %}
2944   interface(CONST_INTER);
2945 %}
2946 
2947 // Unsigned Long Immediate: LL-part, extended by 1s.
2948 operand uimmL_LL1() %{
2949   predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
2950   match(ConL);
2951   op_cost(1);
2952   format %{ %}
2953   interface(CONST_INTER);
2954 %}
2955 
2956 // Unsigned Long Immediate: LH-part, extended by 1s.
2957 operand uimmL_LH1() %{
2958   predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
2959   match(ConL);
2960   op_cost(1);
2961   format %{ %}
2962   interface(CONST_INTER);
2963 %}
2964 
2965 // Unsigned Long Immediate: HL-part, extended by 1s.
2966 operand uimmL_HL1() %{
2967   predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
2968   match(ConL);
2969   op_cost(1);
2970   format %{ %}
2971   interface(CONST_INTER);
2972 %}
2973 
2974 // Unsigned Long Immediate: HH-part, extended by 1s.
2975 operand uimmL_HH1() %{
2976   predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
2977   match(ConL);
2978   op_cost(1);
2979   format %{ %}
2980   interface(CONST_INTER);
2981 %}
2982 
2983 // Long Immediate: low 32-bit mask
2984 operand immL_32bits() %{
2985   predicate(n->get_long() == 0xFFFFFFFFL);
2986   match(ConL);
2987   op_cost(1);
2988   format %{ %}
2989   interface(CONST_INTER);
2990 %}
2991 
2992 //--------------------------------------
2993 //  POINTER immediate operands
2994 //--------------------------------------
2995 
2996 // Pointer Immediate: 64-bit
2997 operand immP() %{
2998   match(ConP);
2999   op_cost(1);
3000   format %{ %}
3001   interface(CONST_INTER);
3002 %}
3003 
3004 // Pointer Immediate: 32-bit
3005 operand immP32() %{
3006   predicate(Immediate::is_uimm32(n->get_ptr()));
3007   match(ConP);
3008   op_cost(1);
3009   format %{ %}
3010   interface(CONST_INTER);
3011 %}
3012 
3013 // Pointer Immediate: 16-bit
3014 operand immP16() %{
3015   predicate(Immediate::is_uimm16(n->get_ptr()));
3016   match(ConP);
3017   op_cost(1);
3018   format %{ %}
3019   interface(CONST_INTER);
3020 %}
3021 
3022 // Pointer Immediate: 8-bit
3023 operand immP8() %{
3024   predicate(Immediate::is_uimm8(n->get_ptr()));
3025   match(ConP);
3026   op_cost(1);
3027   format %{ %}
3028   interface(CONST_INTER);
3029 %}
3030 
3031 //-----------------------------------
3032 // POINTER specific values
3033 //-----------------------------------
3034 
3035 // Pointer Immediate: NULL
3036 operand immP0() %{
3037   predicate(n->get_ptr() == 0);
3038   match(ConP);
3039   op_cost(1);
3040   format %{ %}
3041   interface(CONST_INTER);
3042 %}
3043 
3044 //---------------------------------------------
3045 // NARROW POINTER immediate operands
3046 //---------------------------------------------
3047 
3048 // Narrow Pointer Immediate
3049 operand immN() %{
3050   match(ConN);
3051   op_cost(1);
3052   format %{ %}
3053   interface(CONST_INTER);
3054 %}
3055 
3056 operand immNKlass() %{
3057   match(ConNKlass);
3058   op_cost(1);
3059   format %{ %}
3060   interface(CONST_INTER);
3061 %}
3062 
3063 // Narrow Pointer Immediate
3064 operand immN8() %{
3065   predicate(Immediate::is_uimm8(n->get_narrowcon()));
3066   match(ConN);
3067   op_cost(1);
3068   format %{ %}
3069   interface(CONST_INTER);
3070 %}
3071 
3072 // Narrow NULL Pointer Immediate
3073 operand immN0() %{
3074   predicate(n->get_narrowcon() == 0);
3075   match(ConN);
3076   op_cost(1);
3077   format %{ %}
3078   interface(CONST_INTER);
3079 %}
3080 
3081 // FLOAT and DOUBLE immediate operands
3082 
3083 // Double Immediate
3084 operand immD() %{
3085   match(ConD);
3086   op_cost(1);
3087   format %{ %}
3088   interface(CONST_INTER);
3089 %}
3090 
3091 // Double Immediate: +-0
3092 operand immDpm0() %{
3093   predicate(n->getd() == 0);
3094   match(ConD);
3095   op_cost(1);
3096   format %{ %}
3097   interface(CONST_INTER);
3098 %}
3099 
3100 // Double Immediate: +0
3101 operand immDp0() %{
3102   predicate(jlong_cast(n->getd()) == 0);
3103   match(ConD);
3104   op_cost(1);
3105   format %{ %}
3106   interface(CONST_INTER);
3107 %}
3108 
3109 // Float Immediate
3110 operand immF() %{
3111   match(ConF);
3112   op_cost(1);
3113   format %{ %}
3114   interface(CONST_INTER);
3115 %}
3116 
3117 // Float Immediate: +-0
3118 operand immFpm0() %{
3119   predicate(n->getf() == 0);
3120   match(ConF);
3121   op_cost(1);
3122   format %{ %}
3123   interface(CONST_INTER);
3124 %}
3125 
3126 // Float Immediate: +0
3127 operand immFp0() %{
3128   predicate(jint_cast(n->getf()) == 0);
3129   match(ConF);
3130   op_cost(1);
3131   format %{ %}
3132   interface(CONST_INTER);
3133 %}
3134 
3135 // End of Immediate Operands
3136 
3137 // Integer Register Operands
3138 // Integer Register
3139 operand iRegI() %{
3140   constraint(ALLOC_IN_RC(z_int_reg));
3141   match(RegI);
3142   match(noArg_iRegI);
3143   match(rarg1RegI);
3144   match(rarg2RegI);
3145   match(rarg3RegI);
3146   match(rarg4RegI);
3147   match(rarg5RegI);
3148   match(noOdd_iRegI);
3149   match(revenRegI);
3150   match(roddRegI);
3151   format %{ %}
3152   interface(REG_INTER);
3153 %}
3154 
3155 operand noArg_iRegI() %{
3156   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3157   match(RegI);
3158   format %{ %}
3159   interface(REG_INTER);
3160 %}
3161 
3162 // Revenregi and roddRegI constitute and even-odd-pair.
3163 operand revenRegI() %{
3164   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3165   match(iRegI);
3166   format %{ %}
3167   interface(REG_INTER);
3168 %}
3169 
3170 // Revenregi and roddRegI constitute and even-odd-pair.
3171 operand roddRegI() %{
3172   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3173   match(iRegI);
3174   format %{ %}
3175   interface(REG_INTER);
3176 %}
3177 
3178 operand rarg1RegI() %{
3179   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3180   match(iRegI);
3181   format %{ %}
3182   interface(REG_INTER);
3183 %}
3184 
3185 operand rarg2RegI() %{
3186   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3187   match(iRegI);
3188   format %{ %}
3189   interface(REG_INTER);
3190 %}
3191 
3192 operand rarg3RegI() %{
3193   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3194   match(iRegI);
3195   format %{ %}
3196   interface(REG_INTER);
3197 %}
3198 
3199 operand rarg4RegI() %{
3200   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3201   match(iRegI);
3202   format %{ %}
3203   interface(REG_INTER);
3204 %}
3205 
3206 operand rarg5RegI() %{
3207   constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3208   match(iRegI);
3209   format %{ %}
3210   interface(REG_INTER);
3211 %}
3212 
3213 operand noOdd_iRegI() %{
3214   constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3215   match(RegI);
3216   match(revenRegI);
3217   format %{ %}
3218   interface(REG_INTER);
3219 %}
3220 
3221 // Pointer Register
3222 operand iRegP() %{
3223   constraint(ALLOC_IN_RC(z_ptr_reg));
3224   match(RegP);
3225   match(noArg_iRegP);
3226   match(rarg1RegP);
3227   match(rarg2RegP);
3228   match(rarg3RegP);
3229   match(rarg4RegP);
3230   match(rarg5RegP);
3231   match(revenRegP);
3232   match(roddRegP);
3233   format %{ %}
3234   interface(REG_INTER);
3235 %}
3236 
3237 // thread operand
3238 operand threadRegP() %{
3239   constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3240   match(RegP);
3241   format %{ "Z_THREAD" %}
3242   interface(REG_INTER);
3243 %}
3244 
3245 operand noArg_iRegP() %{
3246   constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3247   match(iRegP);
3248   format %{ %}
3249   interface(REG_INTER);
3250 %}
3251 
3252 operand rarg1RegP() %{
3253   constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3254   match(iRegP);
3255   format %{ %}
3256   interface(REG_INTER);
3257 %}
3258 
3259 operand rarg2RegP() %{
3260   constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3261   match(iRegP);
3262   format %{ %}
3263   interface(REG_INTER);
3264 %}
3265 
3266 operand rarg3RegP() %{
3267   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3268   match(iRegP);
3269   format %{ %}
3270   interface(REG_INTER);
3271 %}
3272 
3273 operand rarg4RegP() %{
3274   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3275   match(iRegP);
3276   format %{ %}
3277   interface(REG_INTER);
3278 %}
3279 
3280 operand rarg5RegP() %{
3281   constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3282   match(iRegP);
3283   format %{ %}
3284   interface(REG_INTER);
3285 %}
3286 
3287 operand memoryRegP() %{
3288   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3289   match(RegP);
3290   match(iRegP);
3291   match(threadRegP);
3292   format %{ %}
3293   interface(REG_INTER);
3294 %}
3295 
3296 // Revenregp and roddRegP constitute and even-odd-pair.
3297 operand revenRegP() %{
3298   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3299   match(iRegP);
3300   format %{ %}
3301   interface(REG_INTER);
3302 %}
3303 
3304 // Revenregl and roddRegL constitute and even-odd-pair.
3305 operand roddRegP() %{
3306   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3307   match(iRegP);
3308   format %{ %}
3309   interface(REG_INTER);
3310 %}
3311 
3312 operand lock_ptr_RegP() %{
3313   constraint(ALLOC_IN_RC(z_lock_ptr_reg));
3314   match(RegP);
3315   format %{ %}
3316   interface(REG_INTER);
3317 %}
3318 
3319 operand rscratch2RegP() %{
3320   constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg));
3321   match(RegP);
3322   format %{ %}
3323   interface(REG_INTER);
3324 %}
3325 
3326 operand iRegN() %{
3327   constraint(ALLOC_IN_RC(z_int_reg));
3328   match(RegN);
3329   match(noArg_iRegN);
3330   match(rarg1RegN);
3331   match(rarg2RegN);
3332   match(rarg3RegN);
3333   match(rarg4RegN);
3334   match(rarg5RegN);
3335   format %{ %}
3336   interface(REG_INTER);
3337 %}
3338 
3339 operand noArg_iRegN() %{
3340   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3341   match(iRegN);
3342   format %{ %}
3343   interface(REG_INTER);
3344 %}
3345 
3346 operand rarg1RegN() %{
3347   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3348   match(iRegN);
3349   format %{ %}
3350   interface(REG_INTER);
3351 %}
3352 
3353 operand rarg2RegN() %{
3354   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3355   match(iRegN);
3356   format %{ %}
3357   interface(REG_INTER);
3358 %}
3359 
3360 operand rarg3RegN() %{
3361   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3362   match(iRegN);
3363   format %{ %}
3364   interface(REG_INTER);
3365 %}
3366 
3367 operand rarg4RegN() %{
3368   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3369   match(iRegN);
3370   format %{ %}
3371   interface(REG_INTER);
3372 %}
3373 
3374 operand rarg5RegN() %{
3375   constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3376   match(iRegN);
3377   format %{ %}
3378   interface(REG_INTER);
3379 %}
3380 
3381 // Long Register
3382 operand iRegL() %{
3383   constraint(ALLOC_IN_RC(z_long_reg));
3384   match(RegL);
3385   match(revenRegL);
3386   match(roddRegL);
3387   match(rarg1RegL);
3388   match(rarg5RegL);
3389   format %{ %}
3390   interface(REG_INTER);
3391 %}
3392 
3393 // Revenregl and roddRegL constitute and even-odd-pair.
3394 operand revenRegL() %{
3395   constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3396   match(iRegL);
3397   format %{ %}
3398   interface(REG_INTER);
3399 %}
3400 
3401 // Revenregl and roddRegL constitute and even-odd-pair.
3402 operand roddRegL() %{
3403   constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3404   match(iRegL);
3405   format %{ %}
3406   interface(REG_INTER);
3407 %}
3408 
3409 operand rarg1RegL() %{
3410   constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3411   match(iRegL);
3412   format %{ %}
3413   interface(REG_INTER);
3414 %}
3415 
3416 operand rarg5RegL() %{
3417   constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3418   match(iRegL);
3419   format %{ %}
3420   interface(REG_INTER);
3421 %}
3422 
3423 // Condition Code Flag Registers
3424 operand flagsReg() %{
3425   constraint(ALLOC_IN_RC(z_condition_reg));
3426   match(RegFlags);
3427   format %{ "CR" %}
3428   interface(REG_INTER);
3429 %}
3430 
3431 // Condition Code Flag Registers for rules with result tuples
3432 operand TD_flagsReg() %{
3433   constraint(ALLOC_IN_RC(z_condition_reg));
3434   match(RegFlags);
3435   format %{ "CR" %}
3436   interface(REG_TUPLE_DEST_INTER);
3437 %}
3438 
3439 operand regD() %{
3440   constraint(ALLOC_IN_RC(z_dbl_reg));
3441   match(RegD);
3442   format %{ %}
3443   interface(REG_INTER);
3444 %}
3445 
3446 operand rscratchRegD() %{
3447   constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg));
3448   match(RegD);
3449   format %{ %}
3450   interface(REG_INTER);
3451 %}
3452 
3453 operand regF() %{
3454   constraint(ALLOC_IN_RC(z_flt_reg));
3455   match(RegF);
3456   format %{ %}
3457   interface(REG_INTER);
3458 %}
3459 
3460 operand rscratchRegF() %{
3461   constraint(ALLOC_IN_RC(z_rscratch1_flt_reg));
3462   match(RegF);
3463   format %{ %}
3464   interface(REG_INTER);
3465 %}
3466 
3467 // Special Registers
3468 
3469 // Method Register
3470 operand inline_cache_regP(iRegP reg) %{
3471   constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3472   match(reg);
3473   format %{ %}
3474   interface(REG_INTER);
3475 %}
3476 
3477 operand compiler_method_oop_regP(iRegP reg) %{
3478   constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg
3479   match(reg);
3480   format %{ %}
3481   interface(REG_INTER);
3482 %}
3483 
3484 operand interpreter_method_oop_regP(iRegP reg) %{
3485   constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg
3486   match(reg);
3487   format %{ %}
3488   interface(REG_INTER);
3489 %}
3490 
3491 // Operands to remove register moves in unscaled mode.
3492 // Match read/write registers with an EncodeP node if neither shift nor add are required.
3493 operand iRegP2N(iRegP reg) %{
3494   predicate(Universe::narrow_oop_shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL);
3495   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3496   match(EncodeP reg);
3497   format %{ "$reg" %}
3498   interface(REG_INTER)
3499 %}
3500 
3501 operand iRegN2P(iRegN reg) %{
3502   predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0 &&
3503             _leaf->as_DecodeN()->in(0) == NULL);
3504   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3505   match(DecodeN reg);
3506   format %{ "$reg" %}
3507   interface(REG_INTER)
3508 %}
3509 
3510 
3511 //----------Complex Operands---------------------------------------------------
3512 
3513 // Indirect Memory Reference
3514 operand indirect(memoryRegP base) %{
3515   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3516   match(base);
3517   op_cost(1);
3518   format %{ "#0[,$base]" %}
3519   interface(MEMORY_INTER) %{
3520     base($base);
3521     index(0xffffFFFF); // noreg
3522     scale(0x0);
3523     disp(0x0);
3524   %}
3525 %}
3526 
3527 // Indirect with Offset (long)
3528 operand indOffset20(memoryRegP base, immL20 offset) %{
3529   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3530   match(AddP base offset);
3531   op_cost(1);
3532   format %{ "$offset[,$base]" %}
3533   interface(MEMORY_INTER) %{
3534     base($base);
3535     index(0xffffFFFF); // noreg
3536     scale(0x0);
3537     disp($offset);
3538   %}
3539 %}
3540 
3541 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3542   predicate(Matcher::narrow_oop_use_complex_address());
3543   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3544   match(AddP (DecodeN base) offset);
3545   op_cost(1);
3546   format %{ "$offset[,$base]" %}
3547   interface(MEMORY_INTER) %{
3548     base($base);
3549     index(0xffffFFFF); // noreg
3550     scale(0x0);
3551     disp($offset);
3552   %}
3553 %}
3554 
3555 // Indirect with Offset (short)
3556 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3557   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3558   match(AddP base offset);
3559   op_cost(1);
3560   format %{ "$offset[[,$base]]" %}
3561   interface(MEMORY_INTER) %{
3562     base($base);
3563     index(0xffffFFFF); // noreg
3564     scale(0x0);
3565     disp($offset);
3566   %}
3567 %}
3568 
3569 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3570   predicate(Matcher::narrow_oop_use_complex_address());
3571   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3572   match(AddP (DecodeN base) offset);
3573   op_cost(1);
3574   format %{ "$offset[[,$base]]" %}
3575   interface(MEMORY_INTER) %{
3576     base($base);
3577     index(0xffffFFFF); // noreg
3578     scale(0x0);
3579     disp($offset);
3580   %}
3581 %}
3582 
3583 // Indirect with Register Index
3584 operand indIndex(memoryRegP base, iRegL index) %{
3585   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3586   match(AddP base index);
3587   op_cost(1);
3588   format %{ "#0[($index,$base)]" %}
3589   interface(MEMORY_INTER) %{
3590     base($base);
3591     index($index);
3592     scale(0x0);
3593     disp(0x0);
3594   %}
3595 %}
3596 
3597 // Indirect with Offset (long) and index
3598 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3599   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3600   match(AddP (AddP base index) offset);
3601   op_cost(1);
3602   format %{ "$offset[($index,$base)]" %}
3603   interface(MEMORY_INTER) %{
3604     base($base);
3605     index($index);
3606     scale(0x0);
3607     disp($offset);
3608   %}
3609 %}
3610 
3611 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3612   predicate(Matcher::narrow_oop_use_complex_address());
3613   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3614   match(AddP (AddP (DecodeN base) index) offset);
3615   op_cost(1);
3616   format %{ "$offset[($index,$base)]" %}
3617   interface(MEMORY_INTER) %{
3618     base($base);
3619     index($index);
3620     scale(0x0);
3621     disp($offset);
3622   %}
3623 %}
3624 
3625 // Indirect with Offset (short) and index
3626 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3627   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3628   match(AddP (AddP base index) offset);
3629   op_cost(1);
3630   format %{ "$offset[[($index,$base)]]" %}
3631   interface(MEMORY_INTER) %{
3632     base($base);
3633     index($index);
3634     scale(0x0);
3635     disp($offset);
3636   %}
3637 %}
3638 
3639 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3640   predicate(Matcher::narrow_oop_use_complex_address());
3641   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3642   match(AddP (AddP (DecodeN base) index) offset);
3643   op_cost(1);
3644   format %{ "$offset[[($index,$base)]]" %}
3645   interface(MEMORY_INTER) %{
3646     base($base);
3647     index($index);
3648     scale(0x0);
3649     disp($offset);
3650   %}
3651 %}
3652 
3653 //----------Special Memory Operands--------------------------------------------
3654 
3655 // Stack Slot Operand
3656 // This operand is used for loading and storing temporary values on
3657 // the stack where a match requires a value to flow through memory.
3658 operand stackSlotI(sRegI reg) %{
3659   constraint(ALLOC_IN_RC(stack_slots));
3660   op_cost(1);
3661   format %{ "[$reg(stackSlotI)]" %}
3662   interface(MEMORY_INTER) %{
3663     base(0xf);   // Z_SP
3664     index(0xffffFFFF); // noreg
3665     scale(0x0);
3666     disp($reg);  // stack offset
3667   %}
3668 %}
3669 
3670 operand stackSlotP(sRegP reg) %{
3671   constraint(ALLOC_IN_RC(stack_slots));
3672   op_cost(1);
3673   format %{ "[$reg(stackSlotP)]" %}
3674   interface(MEMORY_INTER) %{
3675     base(0xf);   // Z_SP
3676     index(0xffffFFFF); // noreg
3677     scale(0x0);
3678     disp($reg);  // Stack Offset
3679   %}
3680 %}
3681 
3682 operand stackSlotF(sRegF reg) %{
3683   constraint(ALLOC_IN_RC(stack_slots));
3684   op_cost(1);
3685   format %{ "[$reg(stackSlotF)]" %}
3686   interface(MEMORY_INTER) %{
3687     base(0xf);   // Z_SP
3688     index(0xffffFFFF); // noreg
3689     scale(0x0);
3690     disp($reg);  // Stack Offset
3691   %}
3692 %}
3693 
3694 operand stackSlotD(sRegD reg) %{
3695   constraint(ALLOC_IN_RC(stack_slots));
3696   op_cost(1);
3697   //match(RegD);
3698   format %{ "[$reg(stackSlotD)]" %}
3699   interface(MEMORY_INTER) %{
3700     base(0xf);   // Z_SP
3701     index(0xffffFFFF); // noreg
3702     scale(0x0);
3703     disp($reg);  // Stack Offset
3704   %}
3705 %}
3706 
3707 operand stackSlotL(sRegL reg) %{
3708   constraint(ALLOC_IN_RC(stack_slots));
3709   op_cost(1);  //match(RegL);
3710   format %{ "[$reg(stackSlotL)]" %}
3711   interface(MEMORY_INTER) %{
3712     base(0xf);   // Z_SP
3713     index(0xffffFFFF); // noreg
3714     scale(0x0);
3715     disp($reg);  // Stack Offset
3716   %}
3717 %}
3718 
3719 // Operands for expressing Control Flow
3720 // NOTE: Label is a predefined operand which should not be redefined in
3721 // the AD file. It is generically handled within the ADLC.
3722 
3723 //----------Conditional Branch Operands----------------------------------------
3724 // Comparison Op  - This is the operation of the comparison, and is limited to
3725 //                  the following set of codes:
3726 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3727 //
3728 // Other attributes of the comparison, such as unsignedness, are specified
3729 // by the comparison instruction that sets a condition code flags register.
3730 // That result is represented by a flags operand whose subtype is appropriate
3731 // to the unsignedness (etc.) of the comparison.
3732 //
3733 // Later, the instruction which matches both the Comparison Op (a Bool) and
3734 // the flags (produced by the Cmp) specifies the coding of the comparison op
3735 // by matching a specific subtype of Bool operand below.
3736 
3737 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3738 // have mask bit #3 set.
3739 operand cmpOpT() %{
3740   match(Bool);
3741   format %{ "" %}
3742   interface(COND_INTER) %{
3743     equal(0x8);         // Assembler::bcondEqual
3744     not_equal(0x6);     // Assembler::bcondNotEqual
3745     less(0x4);          // Assembler::bcondLow
3746     greater_equal(0xa); // Assembler::bcondNotLow
3747     less_equal(0xc);    // Assembler::bcondNotHigh
3748     greater(0x2);       // Assembler::bcondHigh
3749     overflow(0x1);      // Assembler::bcondOverflow
3750     no_overflow(0xe);   // Assembler::bcondNotOverflow
3751   %}
3752 %}
3753 
3754 // When used for floating point comparisons: unordered is treated as less.
3755 operand cmpOpF() %{
3756   match(Bool);
3757   format %{ "" %}
3758   interface(COND_INTER) %{
3759     equal(0x8);
3760     not_equal(0x7);     // Includes 'unordered'.
3761     less(0x5);          // Includes 'unordered'.
3762     greater_equal(0xa);
3763     less_equal(0xd);    // Includes 'unordered'.
3764     greater(0x2);
3765     overflow(0x0);      // Not meaningful on z/Architecture.
3766     no_overflow(0x0);   // leave unchanged (zero) therefore
3767   %}
3768 %}
3769 
3770 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3771 operand cmpOp() %{
3772   match(Bool);
3773   format %{ "" %}
3774   interface(COND_INTER) %{
3775     equal(0x8);
3776     not_equal(0x7);     // Includes 'unordered'.
3777     less(0x5);          // Includes 'unordered'.
3778     greater_equal(0xa);
3779     less_equal(0xd);    // Includes 'unordered'.
3780     greater(0x2);
3781     overflow(0x1);      // Assembler::bcondOverflow
3782     no_overflow(0xe);   // Assembler::bcondNotOverflow
3783   %}
3784 %}
3785 
3786 //----------OPERAND CLASSES----------------------------------------------------
3787 // Operand Classes are groups of operands that are used to simplify
3788 // instruction definitions by not requiring the AD writer to specify
3789 // seperate instructions for every form of operand when the
3790 // instruction accepts multiple operand types with the same basic
3791 // encoding and format.  The classic case of this is memory operands.
3792 // Indirect is not included since its use is limited to Compare & Swap
3793 
3794 // Most general memory operand, allows base, index, and long displacement.
3795 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3796 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3797 
3798 // General memory operand, allows base, index, and short displacement.
3799 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3800 
3801 // Memory operand, allows only base and long displacement.
3802 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3803 
3804 // Memory operand, allows only base and short displacement.
3805 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3806 
3807 // Operand classes to match encode and decode.
3808 opclass iRegN_P2N(iRegN);
3809 opclass iRegP_N2P(iRegP);
3810 
3811 
3812 //----------PIPELINE-----------------------------------------------------------
3813 pipeline %{
3814 
3815 //----------ATTRIBUTES---------------------------------------------------------
3816 attributes %{
3817   // z/Architecture instructions are of length 2, 4, or 6 bytes.
3818   variable_size_instructions;
3819   instruction_unit_size = 2;
3820 
3821   // Meaningless on z/Architecture.
3822   max_instructions_per_bundle = 1;
3823 
3824   // The z/Architecture processor fetches 64 bytes...
3825   instruction_fetch_unit_size = 64;
3826 
3827   // ...in one line.
3828   instruction_fetch_units = 1
3829 %}
3830 
3831 //----------RESOURCES----------------------------------------------------------
3832 // Resources are the functional units available to the machine.
3833 resources(
3834    Z_BR,     // branch unit
3835    Z_CR,     // condition unit
3836    Z_FX1,    // integer arithmetic unit 1
3837    Z_FX2,    // integer arithmetic unit 2
3838    Z_LDST1,  // load/store unit 1
3839    Z_LDST2,  // load/store unit 2
3840    Z_FP1,    // float arithmetic unit 1
3841    Z_FP2,    // float arithmetic unit 2
3842    Z_LDST = Z_LDST1 | Z_LDST2,
3843    Z_FX   = Z_FX1 | Z_FX2,
3844    Z_FP   = Z_FP1 | Z_FP2
3845   );
3846 
3847 //----------PIPELINE DESCRIPTION-----------------------------------------------
3848 // Pipeline Description specifies the stages in the machine's pipeline.
3849 pipe_desc(
3850    // TODO: adapt
3851    Z_IF,  // instruction fetch
3852    Z_IC,
3853    Z_D0,  // decode
3854    Z_D1,  // decode
3855    Z_D2,  // decode
3856    Z_D3,  // decode
3857    Z_Xfer1,
3858    Z_GD,  // group definition
3859    Z_MP,  // map
3860    Z_ISS, // issue
3861    Z_RF,  // resource fetch
3862    Z_EX1, // execute (all units)
3863    Z_EX2, // execute (FP, LDST)
3864    Z_EX3, // execute (FP, LDST)
3865    Z_EX4, // execute (FP)
3866    Z_EX5, // execute (FP)
3867    Z_EX6, // execute (FP)
3868    Z_WB,  // write back
3869    Z_Xfer2,
3870    Z_CP
3871   );
3872 
3873 //----------PIPELINE CLASSES---------------------------------------------------
3874 // Pipeline Classes describe the stages in which input and output are
3875 // referenced by the hardware pipeline.
3876 
3877 // Providing the `ins_pipe' declarations in the instruction
3878 // specifications seems to be of little use. So we use
3879 // `pipe_class_dummy' for all our instructions at present.
3880 pipe_class pipe_class_dummy() %{
3881   single_instruction;
3882   fixed_latency(4);
3883 %}
3884 
3885 // SIGTRAP based implicit range checks in compiled code.
3886 // Currently, no pipe classes are used on z/Architecture.
3887 pipe_class pipe_class_trap() %{
3888   single_instruction;
3889 %}
3890 
3891 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
3892   single_instruction;
3893   dst  : Z_EX1(write);
3894   src1 : Z_RF(read);
3895   src2 : Z_RF(read);
3896   Z_FX : Z_RF;
3897 %}
3898 
3899 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
3900   single_instruction;
3901   mem : Z_RF(read);
3902   dst : Z_WB(write);
3903   Z_LDST : Z_RF;
3904 %}
3905 
3906 define %{
3907   MachNop = pipe_class_dummy;
3908 %}
3909 
3910 %}
3911 
3912 //----------INSTRUCTIONS-------------------------------------------------------
3913 
3914 //---------- Chain stack slots between similar types --------
3915 
3916 // Load integer from stack slot.
3917 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
3918   match(Set dst src);
3919   ins_cost(MEMORY_REF_COST);
3920   // TODO: s390 port size(FIXED_SIZE);
3921   format %{ "L       $dst,$src\t # stk reload int" %}
3922   opcode(L_ZOPC);
3923   ins_encode(z_form_rt_mem(dst, src));
3924   ins_pipe(pipe_class_dummy);
3925 %}
3926 
3927 // Store integer to stack slot.
3928 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
3929   match(Set dst src);
3930   ins_cost(MEMORY_REF_COST);
3931   // TODO: s390 port size(FIXED_SIZE);
3932   format %{ "ST      $src,$dst\t # stk spill int" %}
3933   opcode(ST_ZOPC);
3934   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3935   ins_pipe(pipe_class_dummy);
3936 %}
3937 
3938 // Load long from stack slot.
3939 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
3940   match(Set dst src);
3941   ins_cost(MEMORY_REF_COST);
3942   // TODO: s390 port size(FIXED_SIZE);
3943   format %{ "LG      $dst,$src\t # stk reload long" %}
3944   opcode(LG_ZOPC);
3945   ins_encode(z_form_rt_mem(dst, src));
3946   ins_pipe(pipe_class_dummy);
3947 %}
3948 
3949 // Store long to stack slot.
3950 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
3951   match(Set dst src);
3952   ins_cost(MEMORY_REF_COST);
3953   size(6);
3954   format %{ "STG     $src,$dst\t # stk spill long" %}
3955   opcode(STG_ZOPC);
3956   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3957   ins_pipe(pipe_class_dummy);
3958 %}
3959 
3960 // Load pointer from stack slot, 64-bit encoding.
3961 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
3962   match(Set dst src);
3963   ins_cost(MEMORY_REF_COST);
3964   // TODO: s390 port size(FIXED_SIZE);
3965   format %{ "LG      $dst,$src\t # stk reload ptr" %}
3966   opcode(LG_ZOPC);
3967   ins_encode(z_form_rt_mem(dst, src));
3968   ins_pipe(pipe_class_dummy);
3969 %}
3970 
3971 // Store pointer to stack slot.
3972 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
3973   match(Set dst src);
3974   ins_cost(MEMORY_REF_COST);
3975   // TODO: s390 port size(FIXED_SIZE);
3976   format %{ "STG     $src,$dst\t # stk spill ptr" %}
3977   opcode(STG_ZOPC);
3978   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3979   ins_pipe(pipe_class_dummy);
3980 %}
3981 
3982 //  Float types
3983 
3984 // Load float value from stack slot.
3985 instruct stkF_to_regF(regF dst, stackSlotF src) %{
3986   match(Set dst src);
3987   ins_cost(MEMORY_REF_COST);
3988   size(4);
3989   format %{ "LE(Y)   $dst,$src\t # stk reload float" %}
3990   opcode(LE_ZOPC);
3991   ins_encode(z_form_rt_mem(dst, src));
3992   ins_pipe(pipe_class_dummy);
3993 %}
3994 
3995 // Store float value to stack slot.
3996 instruct regF_to_stkF(stackSlotF dst, regF src) %{
3997   match(Set dst src);
3998   ins_cost(MEMORY_REF_COST);
3999   size(4);
4000   format %{ "STE(Y)  $src,$dst\t # stk spill float" %}
4001   opcode(STE_ZOPC);
4002   ins_encode(z_form_rt_mem(src, dst));
4003   ins_pipe(pipe_class_dummy);
4004 %}
4005 
4006 // Load double value from stack slot.
4007 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4008   match(Set dst src);
4009   ins_cost(MEMORY_REF_COST);
4010   // TODO: s390 port size(FIXED_SIZE);
4011   format %{ "LD(Y)   $dst,$src\t # stk reload double" %}
4012   opcode(LD_ZOPC);
4013   ins_encode(z_form_rt_mem(dst, src));
4014   ins_pipe(pipe_class_dummy);
4015 %}
4016 
4017 // Store double value to stack slot.
4018 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4019   match(Set dst src);
4020   ins_cost(MEMORY_REF_COST);
4021   size(4);
4022   format %{ "STD(Y)  $src,$dst\t # stk spill double" %}
4023   opcode(STD_ZOPC);
4024   ins_encode(z_form_rt_mem(src, dst));
4025   ins_pipe(pipe_class_dummy);
4026 %}
4027 
4028 //----------Load/Store/Move Instructions---------------------------------------
4029 
4030 //----------Load Instructions--------------------------------------------------
4031 
4032 //------------------
4033 //  MEMORY
4034 //------------------
4035 
4036 //  BYTE
4037 // Load Byte (8bit signed)
4038 instruct loadB(iRegI dst, memory mem) %{
4039   match(Set dst (LoadB mem));
4040   ins_cost(MEMORY_REF_COST);
4041   size(Z_DISP3_SIZE);
4042   format %{ "LB      $dst, $mem\t # sign-extend byte to int" %}
4043   opcode(LB_ZOPC, LB_ZOPC);
4044   ins_encode(z_form_rt_mem_opt(dst, mem));
4045   ins_pipe(pipe_class_dummy);
4046 %}
4047 
4048 // Load Byte (8bit signed)
4049 instruct loadB2L(iRegL dst, memory mem) %{
4050   match(Set dst (ConvI2L (LoadB mem)));
4051   ins_cost(MEMORY_REF_COST);
4052   size(Z_DISP3_SIZE);
4053   format %{ "LGB     $dst, $mem\t # sign-extend byte to long" %}
4054   opcode(LGB_ZOPC, LGB_ZOPC);
4055   ins_encode(z_form_rt_mem_opt(dst, mem));
4056   ins_pipe(pipe_class_dummy);
4057 %}
4058 
4059 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4060 instruct loadUB(iRegI dst, memory mem) %{
4061   match(Set dst (LoadUB mem));
4062   ins_cost(MEMORY_REF_COST);
4063   size(Z_DISP3_SIZE);
4064   format %{ "LLGC    $dst,$mem\t # zero-extend byte to int" %}
4065   opcode(LLGC_ZOPC, LLGC_ZOPC);
4066   ins_encode(z_form_rt_mem_opt(dst, mem));
4067   ins_pipe(pipe_class_dummy);
4068 %}
4069 
4070 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4071 instruct loadUB2L(iRegL dst, memory mem) %{
4072   match(Set dst (ConvI2L (LoadUB mem)));
4073   ins_cost(MEMORY_REF_COST);
4074   size(Z_DISP3_SIZE);
4075   format %{ "LLGC    $dst,$mem\t # zero-extend byte to long" %}
4076   opcode(LLGC_ZOPC, LLGC_ZOPC);
4077   ins_encode(z_form_rt_mem_opt(dst, mem));
4078   ins_pipe(pipe_class_dummy);
4079 %}
4080 
4081 // CHAR/SHORT
4082 
4083 // Load Short (16bit signed)
4084 instruct loadS(iRegI dst, memory mem) %{
4085   match(Set dst (LoadS mem));
4086   ins_cost(MEMORY_REF_COST);
4087   size(Z_DISP_SIZE);
4088   format %{ "LH(Y)   $dst,$mem\t # sign-extend short to int" %}
4089   opcode(LHY_ZOPC, LH_ZOPC);
4090   ins_encode(z_form_rt_mem_opt(dst, mem));
4091   ins_pipe(pipe_class_dummy);
4092 %}
4093 
4094 // Load Short (16bit signed)
4095 instruct loadS2L(iRegL dst, memory mem) %{
4096   match(Set dst (ConvI2L (LoadS mem)));
4097   ins_cost(MEMORY_REF_COST);
4098   size(Z_DISP3_SIZE);
4099   format %{ "LGH     $dst,$mem\t # sign-extend short to long" %}
4100   opcode(LGH_ZOPC, LGH_ZOPC);
4101   ins_encode(z_form_rt_mem_opt(dst, mem));
4102   ins_pipe(pipe_class_dummy);
4103 %}
4104 
4105 // Load Char (16bit Unsigned)
4106 instruct loadUS(iRegI dst, memory mem) %{
4107   match(Set dst (LoadUS mem));
4108   ins_cost(MEMORY_REF_COST);
4109   size(Z_DISP3_SIZE);
4110   format %{ "LLGH    $dst,$mem\t # zero-extend short to int" %}
4111   opcode(LLGH_ZOPC, LLGH_ZOPC);
4112   ins_encode(z_form_rt_mem_opt(dst, mem));
4113   ins_pipe(pipe_class_dummy);
4114 %}
4115 
4116 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4117 instruct loadUS2L(iRegL dst, memory mem) %{
4118   match(Set dst (ConvI2L (LoadUS mem)));
4119   ins_cost(MEMORY_REF_COST);
4120   size(Z_DISP3_SIZE);
4121   format %{ "LLGH    $dst,$mem\t # zero-extend short to long" %}
4122   opcode(LLGH_ZOPC, LLGH_ZOPC);
4123   ins_encode(z_form_rt_mem_opt(dst, mem));
4124   ins_pipe(pipe_class_dummy);
4125 %}
4126 
4127 // INT
4128 
4129 // Load Integer
4130 instruct loadI(iRegI dst, memory mem) %{
4131   match(Set dst (LoadI mem));
4132   ins_cost(MEMORY_REF_COST);
4133   size(Z_DISP_SIZE);
4134   format %{ "L(Y)    $dst,$mem\t #" %}
4135   opcode(LY_ZOPC, L_ZOPC);
4136   ins_encode(z_form_rt_mem_opt(dst, mem));
4137   ins_pipe(pipe_class_dummy);
4138 %}
4139 
4140 // Load and convert to long.
4141 instruct loadI2L(iRegL dst, memory mem) %{
4142   match(Set dst (ConvI2L (LoadI mem)));
4143   ins_cost(MEMORY_REF_COST);
4144   size(Z_DISP3_SIZE);
4145   format %{ "LGF     $dst,$mem\t #" %}
4146   opcode(LGF_ZOPC, LGF_ZOPC);
4147   ins_encode(z_form_rt_mem_opt(dst, mem));
4148   ins_pipe(pipe_class_dummy);
4149 %}
4150 
4151 // Load Unsigned Integer into a Long Register
4152 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4153   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4154   ins_cost(MEMORY_REF_COST);
4155   size(Z_DISP3_SIZE);
4156   format %{ "LLGF    $dst,$mem\t # zero-extend int to long" %}
4157   opcode(LLGF_ZOPC, LLGF_ZOPC);
4158   ins_encode(z_form_rt_mem_opt(dst, mem));
4159   ins_pipe(pipe_class_dummy);
4160 %}
4161 
4162 // range = array length (=jint)
4163 // Load Range
4164 instruct loadRange(iRegI dst, memory mem) %{
4165   match(Set dst (LoadRange mem));
4166   ins_cost(MEMORY_REF_COST);
4167   size(Z_DISP_SIZE);
4168   format %{ "L(Y)    $dst,$mem\t # range" %}
4169   opcode(LY_ZOPC, L_ZOPC);
4170   ins_encode(z_form_rt_mem_opt(dst, mem));
4171   ins_pipe(pipe_class_dummy);
4172 %}
4173 
4174 // LONG
4175 
4176 // Load Long - aligned
4177 instruct loadL(iRegL dst, memory mem) %{
4178   match(Set dst (LoadL mem));
4179   ins_cost(MEMORY_REF_COST);
4180   size(Z_DISP3_SIZE);
4181   format %{ "LG      $dst,$mem\t # long" %}
4182   opcode(LG_ZOPC, LG_ZOPC);
4183   ins_encode(z_form_rt_mem_opt(dst, mem));
4184   ins_pipe(pipe_class_dummy);
4185 %}
4186 
4187 // Load Long - UNaligned
4188 instruct loadL_unaligned(iRegL dst, memory mem) %{
4189   match(Set dst (LoadL_unaligned mem));
4190   ins_cost(MEMORY_REF_COST);
4191   size(Z_DISP3_SIZE);
4192   format %{ "LG      $dst,$mem\t # unaligned long" %}
4193   opcode(LG_ZOPC, LG_ZOPC);
4194   ins_encode(z_form_rt_mem_opt(dst, mem));
4195   ins_pipe(pipe_class_dummy);
4196 %}
4197 
4198 
4199 // PTR
4200 
4201 // Load Pointer
4202 instruct loadP(iRegP dst, memory mem) %{
4203   match(Set dst (LoadP mem));
4204   ins_cost(MEMORY_REF_COST);
4205   size(Z_DISP3_SIZE);
4206   format %{ "LG      $dst,$mem\t # ptr" %}
4207   opcode(LG_ZOPC, LG_ZOPC);
4208   ins_encode(z_form_rt_mem_opt(dst, mem));
4209   ins_pipe(pipe_class_dummy);
4210 %}
4211 
4212 // LoadP + CastP2L
4213 instruct castP2X_loadP(iRegL dst, memory mem) %{
4214   match(Set dst (CastP2X (LoadP mem)));
4215   ins_cost(MEMORY_REF_COST);
4216   size(Z_DISP3_SIZE);
4217   format %{ "LG      $dst,$mem\t # ptr + p2x" %}
4218   opcode(LG_ZOPC, LG_ZOPC);
4219   ins_encode(z_form_rt_mem_opt(dst, mem));
4220   ins_pipe(pipe_class_dummy);
4221 %}
4222 
4223 // Load Klass Pointer
4224 instruct loadKlass(iRegP dst, memory mem) %{
4225   match(Set dst (LoadKlass mem));
4226   ins_cost(MEMORY_REF_COST);
4227   size(Z_DISP3_SIZE);
4228   format %{ "LG      $dst,$mem\t # klass ptr" %}
4229   opcode(LG_ZOPC, LG_ZOPC);
4230   ins_encode(z_form_rt_mem_opt(dst, mem));
4231   ins_pipe(pipe_class_dummy);
4232 %}
4233 
4234 instruct loadTOC(iRegL dst) %{
4235   effect(DEF dst);
4236   ins_cost(DEFAULT_COST);
4237   // TODO: s390 port size(FIXED_SIZE);
4238   // TODO: check why this attribute causes many unnecessary rematerializations.
4239   //
4240   // The graphs I saw just had high register pressure. Further the
4241   // register TOC is loaded to is overwritten by the constant short
4242   // after. Here something as round robin register allocation might
4243   // help. But rematerializing seems not to hurt, jack even seems to
4244   // improve slightly.
4245   //
4246   // Without this flag we get spill-split recycle sanity check
4247   // failures in
4248   // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4249   // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4250   // tlsLoadP has a huge amount of outs and forces the TOC down to the
4251   // stack. Later tlsLoadP is rematerialized, leaving the register
4252   // allocator with TOC on the stack and a badly placed reload.
4253   ins_should_rematerialize(true);
4254   format %{ "LARL    $dst, &constant_pool\t; load dynTOC" %}
4255   ins_encode %{ __ load_toc($dst$$Register); %}
4256   ins_pipe(pipe_class_dummy);
4257 %}
4258 
4259 // FLOAT
4260 
4261 // Load Float
4262 instruct loadF(regF dst, memory mem) %{
4263   match(Set dst (LoadF mem));
4264   ins_cost(MEMORY_REF_COST);
4265   size(Z_DISP_SIZE);
4266   format %{ "LE(Y)    $dst,$mem" %}
4267   opcode(LEY_ZOPC, LE_ZOPC);
4268   ins_encode(z_form_rt_mem_opt(dst, mem));
4269   ins_pipe(pipe_class_dummy);
4270 %}
4271 
4272 // DOUBLE
4273 
4274 // Load Double
4275 instruct loadD(regD dst, memory mem) %{
4276   match(Set dst (LoadD mem));
4277   ins_cost(MEMORY_REF_COST);
4278   size(Z_DISP_SIZE);
4279   format %{ "LD(Y)    $dst,$mem" %}
4280   opcode(LDY_ZOPC, LD_ZOPC);
4281   ins_encode(z_form_rt_mem_opt(dst, mem));
4282   ins_pipe(pipe_class_dummy);
4283 %}
4284 
4285 // Load Double - UNaligned
4286 instruct loadD_unaligned(regD dst, memory mem) %{
4287   match(Set dst (LoadD_unaligned mem));
4288   ins_cost(MEMORY_REF_COST);
4289   size(Z_DISP_SIZE);
4290   format %{ "LD(Y)    $dst,$mem" %}
4291   opcode(LDY_ZOPC, LD_ZOPC);
4292   ins_encode(z_form_rt_mem_opt(dst, mem));
4293   ins_pipe(pipe_class_dummy);
4294 %}
4295 
4296 
4297 //----------------------
4298 //  IMMEDIATES
4299 //----------------------
4300 
4301 instruct loadConI(iRegI dst, immI src) %{
4302   match(Set dst src);
4303   ins_cost(DEFAULT_COST);
4304   size(6);
4305   format %{ "LGFI     $dst,$src\t # (int)" %}
4306   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4307   ins_pipe(pipe_class_dummy);
4308 %}
4309 
4310 instruct loadConI16(iRegI dst, immI16 src) %{
4311   match(Set dst src);
4312   ins_cost(DEFAULT_COST_LOW);
4313   size(4);
4314   format %{ "LGHI     $dst,$src\t # (int)" %}
4315   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4316   ins_pipe(pipe_class_dummy);
4317 %}
4318 
4319 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4320   match(Set dst src);
4321   effect(KILL cr);
4322   ins_cost(DEFAULT_COST_LOW);
4323   size(4);
4324   format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4325   opcode(XGR_ZOPC);
4326   ins_encode(z_rreform(dst, dst));
4327   ins_pipe(pipe_class_dummy);
4328 %}
4329 
4330 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4331   match(Set dst src);
4332   // TODO: s390 port size(FIXED_SIZE);
4333   format %{ "LLILL    $dst,$src" %}
4334   opcode(LLILL_ZOPC);
4335   ins_encode(z_riform_unsigned(dst, src) );
4336   ins_pipe(pipe_class_dummy);
4337 %}
4338 
4339 // Load long constant from TOC with pcrelative address.
4340 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4341   match(Set dst src);
4342   ins_cost(MEMORY_REF_COST_LO);
4343   size(6);
4344   format %{ "LGRL    $dst,[pcrelTOC]\t # load long $src from table" %}
4345   ins_encode %{
4346     address long_address = __ long_constant($src$$constant);
4347     if (long_address == NULL) {
4348       Compile::current()->env()->record_out_of_memory_failure();
4349       return;
4350     }
4351     __ load_long_pcrelative($dst$$Register, long_address);
4352   %}
4353   ins_pipe(pipe_class_dummy);
4354 %}
4355 
4356 instruct loadConL32(iRegL dst, immL32 src) %{
4357   match(Set dst src);
4358   ins_cost(DEFAULT_COST);
4359   size(6);
4360   format %{ "LGFI     $dst,$src\t # (long)" %}
4361   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4362   ins_pipe(pipe_class_dummy);
4363 %}
4364 
4365 instruct loadConL16(iRegL dst, immL16 src) %{
4366   match(Set dst src);
4367   ins_cost(DEFAULT_COST_LOW);
4368   size(4);
4369   format %{ "LGHI     $dst,$src\t # (long)" %}
4370   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4371   ins_pipe(pipe_class_dummy);
4372 %}
4373 
4374 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4375   match(Set dst src);
4376   effect(KILL cr);
4377   ins_cost(DEFAULT_COST_LOW);
4378   format %{ "LoadConL    $dst,$src\t # (long) XGR because ZERO is loaded" %}
4379   opcode(XGR_ZOPC);
4380   ins_encode(z_rreform(dst, dst));
4381   ins_pipe(pipe_class_dummy);
4382 %}
4383 
4384 // Load ptr constant from TOC with pc relative address.
4385 // Special handling for oop constants required.
4386 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4387   match(Set dst src);
4388   ins_cost(MEMORY_REF_COST_LO);
4389   size(6);
4390   format %{ "LGRL    $dst,[pcrelTOC]\t # load ptr $src from table" %}
4391   ins_encode %{
4392     relocInfo::relocType constant_reloc = $src->constant_reloc();
4393     if (constant_reloc == relocInfo::oop_type) {
4394       AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4395       bool success = __ load_oop_from_toc($dst$$Register, a);
4396       if (!success) {
4397         Compile::current()->env()->record_out_of_memory_failure();
4398         return;
4399       }
4400     } else if (constant_reloc == relocInfo::metadata_type) {
4401       AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4402       address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4403       if (const_toc_addr == NULL) {
4404         Compile::current()->env()->record_out_of_memory_failure();
4405         return;
4406       }
4407       __ load_long_pcrelative($dst$$Register, const_toc_addr);
4408     } else {          // Non-oop pointers, e.g. card mark base, heap top.
4409       address long_address = __ long_constant((jlong)$src$$constant);
4410       if (long_address == NULL) {
4411         Compile::current()->env()->record_out_of_memory_failure();
4412         return;
4413       }
4414       __ load_long_pcrelative($dst$$Register, long_address);
4415     }
4416   %}
4417   ins_pipe(pipe_class_dummy);
4418 %}
4419 
4420 // We don't use immP16 to avoid problems with oops.
4421 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4422   match(Set dst src);
4423   effect(KILL cr);
4424   size(4);
4425   format %{ "XGR     $dst,$dst\t # NULL ptr" %}
4426   opcode(XGR_ZOPC);
4427   ins_encode(z_rreform(dst, dst));
4428   ins_pipe(pipe_class_dummy);
4429 %}
4430 
4431 //----------Load Float Constant Instructions-------------------------------------------------
4432 
4433 // We may not specify this instruction via an `expand' rule. If we do,
4434 // code selection will forget that this instruction needs a floating
4435 // point constant inserted into the code buffer. So `Shorten_branches'
4436 // will fail.
4437 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4438   match(Set dst src);
4439   effect(KILL cr);
4440   ins_cost(MEMORY_REF_COST);
4441   size(6);
4442   // If this instruction rematerializes, it prolongs the live range
4443   // of the toc node, causing illegal graphs.
4444   ins_cannot_rematerialize(true);
4445   format %{ "LE(Y)    $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4446   ins_encode %{
4447     __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4448   %}
4449   ins_pipe(pipe_class_dummy);
4450 %}
4451 
4452 // E may not specify this instruction via an `expand' rule. If we do,
4453 // code selection will forget that this instruction needs a floating
4454 // point constant inserted into the code buffer. So `Shorten_branches'
4455 // will fail.
4456 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4457   match(Set dst src);
4458   effect(KILL cr);
4459   ins_cost(MEMORY_REF_COST);
4460   size(6);
4461   // If this instruction rematerializes, it prolongs the live range
4462   // of the toc node, causing illegal graphs.
4463   ins_cannot_rematerialize(true);
4464   format %{ "LD(Y)    $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4465   ins_encode %{
4466     __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4467   %}
4468   ins_pipe(pipe_class_dummy);
4469 %}
4470 
4471 // Special case: Load Const 0.0F
4472 
4473 // There's a special instr to clear a FP register.
4474 instruct loadConF0(regF dst, immFp0 src) %{
4475   match(Set dst src);
4476   ins_cost(DEFAULT_COST_LOW);
4477   size(4);
4478   format %{ "LZER     $dst,$src\t # clear to zero" %}
4479   opcode(LZER_ZOPC);
4480   ins_encode(z_rreform(dst, Z_F0));
4481   ins_pipe(pipe_class_dummy);
4482 %}
4483 
4484 // There's a special instr to clear a FP register.
4485 instruct loadConD0(regD dst, immDp0 src) %{
4486   match(Set dst src);
4487   ins_cost(DEFAULT_COST_LOW);
4488   size(4);
4489   format %{ "LZDR     $dst,$src\t # clear to zero" %}
4490   opcode(LZDR_ZOPC);
4491   ins_encode(z_rreform(dst, Z_F0));
4492   ins_pipe(pipe_class_dummy);
4493 %}
4494 
4495 
4496 //----------Store Instructions-------------------------------------------------
4497 
4498 // BYTE
4499 
4500 // Store Byte
4501 instruct storeB(memory mem, iRegI src) %{
4502   match(Set mem (StoreB mem src));
4503   ins_cost(MEMORY_REF_COST);
4504   size(Z_DISP_SIZE);
4505   format %{ "STC(Y)  $src,$mem\t # byte" %}
4506   opcode(STCY_ZOPC, STC_ZOPC);
4507   ins_encode(z_form_rt_mem_opt(src, mem));
4508   ins_pipe(pipe_class_dummy);
4509 %}
4510 
4511 instruct storeCM(memory mem, immI_0 src) %{
4512   match(Set mem (StoreCM mem src));
4513   ins_cost(MEMORY_REF_COST);
4514   // TODO: s390 port size(VARIABLE_SIZE);
4515   format %{ "STC(Y)  $src,$mem\t # CMS card-mark byte (must be 0!)" %}
4516   ins_encode %{
4517     guarantee($mem$$index$$Register != Z_R0, "content will not be used.");
4518     if ($mem$$index$$Register != noreg) {
4519       // Can't use clear_mem --> load const zero and store character.
4520       __ load_const_optimized(Z_R0_scratch, (long)0);
4521       if (Immediate::is_uimm12($mem$$disp)) {
4522         __ z_stc(Z_R0_scratch, $mem$$Address);
4523       } else {
4524         __ z_stcy(Z_R0_scratch, $mem$$Address);
4525       }
4526     } else {
4527       __ clear_mem(Address($mem$$Address), 1);
4528     }
4529   %}
4530   ins_pipe(pipe_class_dummy);
4531 %}
4532 
4533 // CHAR/SHORT
4534 
4535 // Store Char/Short
4536 instruct storeC(memory mem, iRegI src) %{
4537   match(Set mem (StoreC mem src));
4538   ins_cost(MEMORY_REF_COST);
4539   size(Z_DISP_SIZE);
4540   format %{ "STH(Y)  $src,$mem\t # short" %}
4541   opcode(STHY_ZOPC, STH_ZOPC);
4542   ins_encode(z_form_rt_mem_opt(src, mem));
4543   ins_pipe(pipe_class_dummy);
4544 %}
4545 
4546 // INT
4547 
4548 // Store Integer
4549 instruct storeI(memory mem, iRegI src) %{
4550   match(Set mem (StoreI mem src));
4551   ins_cost(MEMORY_REF_COST);
4552   size(Z_DISP_SIZE);
4553   format %{ "ST(Y)   $src,$mem\t # int" %}
4554   opcode(STY_ZOPC, ST_ZOPC);
4555   ins_encode(z_form_rt_mem_opt(src, mem));
4556   ins_pipe(pipe_class_dummy);
4557 %}
4558 
4559 // LONG
4560 
4561 // Store Long
4562 instruct storeL(memory mem, iRegL src) %{
4563   match(Set mem (StoreL mem src));
4564   ins_cost(MEMORY_REF_COST);
4565   size(Z_DISP3_SIZE);
4566   format %{ "STG     $src,$mem\t # long" %}
4567   opcode(STG_ZOPC, STG_ZOPC);
4568   ins_encode(z_form_rt_mem_opt(src, mem));
4569   ins_pipe(pipe_class_dummy);
4570 %}
4571 
4572 // PTR
4573 
4574 // Store Pointer
4575 instruct storeP(memory dst, memoryRegP src) %{
4576   match(Set dst (StoreP dst src));
4577   ins_cost(MEMORY_REF_COST);
4578   size(Z_DISP3_SIZE);
4579   format %{ "STG     $src,$dst\t # ptr" %}
4580   opcode(STG_ZOPC, STG_ZOPC);
4581   ins_encode(z_form_rt_mem_opt(src, dst));
4582   ins_pipe(pipe_class_dummy);
4583 %}
4584 
4585 // FLOAT
4586 
4587 // Store Float
4588 instruct storeF(memory mem, regF src) %{
4589   match(Set mem (StoreF mem src));
4590   ins_cost(MEMORY_REF_COST);
4591   size(Z_DISP_SIZE);
4592   format %{ "STE(Y)   $src,$mem\t # float" %}
4593   opcode(STEY_ZOPC, STE_ZOPC);
4594   ins_encode(z_form_rt_mem_opt(src, mem));
4595   ins_pipe(pipe_class_dummy);
4596 %}
4597 
4598 // DOUBLE
4599 
4600 // Store Double
4601 instruct storeD(memory mem, regD src) %{
4602   match(Set mem (StoreD mem src));
4603   ins_cost(MEMORY_REF_COST);
4604   size(Z_DISP_SIZE);
4605   format %{ "STD(Y)   $src,$mem\t # double" %}
4606   opcode(STDY_ZOPC, STD_ZOPC);
4607   ins_encode(z_form_rt_mem_opt(src, mem));
4608   ins_pipe(pipe_class_dummy);
4609 %}
4610 
4611 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4612 
4613 // Should support match rule for PrefetchAllocation.
4614 // Still needed after 8068977 for PrefetchAllocate.
4615 instruct prefetchAlloc(memory mem) %{
4616   match(PrefetchAllocation mem);
4617   predicate(VM_Version::has_Prefetch());
4618   ins_cost(DEFAULT_COST);
4619   format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4620   ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4621   ins_pipe(pipe_class_dummy);
4622 %}
4623 
4624 //----------Memory init instructions------------------------------------------
4625 
4626 // Move Immediate to 1-byte memory.
4627 instruct memInitB(memoryRSY mem, immI8 src) %{
4628   match(Set mem (StoreB mem src));
4629   ins_cost(MEMORY_REF_COST);
4630   // TODO: s390 port size(VARIABLE_SIZE);
4631   format %{ "MVI     $mem,$src\t # direct mem init 1" %}
4632   ins_encode %{
4633     if (Immediate::is_uimm12((long)$mem$$disp)) {
4634       __ z_mvi($mem$$Address, $src$$constant);
4635     } else {
4636       __ z_mviy($mem$$Address, $src$$constant);
4637     }
4638   %}
4639   ins_pipe(pipe_class_dummy);
4640 %}
4641 
4642 // Move Immediate to 2-byte memory.
4643 instruct memInitC(memoryRS mem, immI16 src) %{
4644   match(Set mem (StoreC mem src));
4645   ins_cost(MEMORY_REF_COST);
4646   size(6);
4647   format %{ "MVHHI   $mem,$src\t # direct mem init 2" %}
4648   opcode(MVHHI_ZOPC);
4649   ins_encode(z_silform(mem, src));
4650   ins_pipe(pipe_class_dummy);
4651 %}
4652 
4653 // Move Immediate to 4-byte memory.
4654 instruct memInitI(memoryRS mem, immI16 src) %{
4655   match(Set mem (StoreI mem src));
4656   ins_cost(MEMORY_REF_COST);
4657   size(6);
4658   format %{ "MVHI    $mem,$src\t # direct mem init 4" %}
4659   opcode(MVHI_ZOPC);
4660   ins_encode(z_silform(mem, src));
4661   ins_pipe(pipe_class_dummy);
4662 %}
4663 
4664 
4665 // Move Immediate to 8-byte memory.
4666 instruct memInitL(memoryRS mem, immL16 src) %{
4667   match(Set mem (StoreL mem src));
4668   ins_cost(MEMORY_REF_COST);
4669   size(6);
4670   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
4671   opcode(MVGHI_ZOPC);
4672   ins_encode(z_silform(mem, src));
4673   ins_pipe(pipe_class_dummy);
4674 %}
4675 
4676 // Move Immediate to 8-byte memory.
4677 instruct memInitP(memoryRS mem, immP16 src) %{
4678   match(Set mem (StoreP mem src));
4679   ins_cost(MEMORY_REF_COST);
4680   size(6);
4681   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
4682   opcode(MVGHI_ZOPC);
4683   ins_encode(z_silform(mem, src));
4684   ins_pipe(pipe_class_dummy);
4685 %}
4686 
4687 
4688 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4689 
4690 // See cOop encoding classes for elaborate comment.
4691 
4692 // Moved here because it is needed in expand rules for encode.
4693 // Long negation.
4694 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4695   match(Set dst (SubL zero src));
4696   effect(KILL cr);
4697   size(4);
4698   format %{ "NEG     $dst, $src\t # long" %}
4699   ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4700   ins_pipe(pipe_class_dummy);
4701 %}
4702 
4703 // Load Compressed Pointer
4704 
4705 // Load narrow oop
4706 instruct loadN(iRegN dst, memory mem) %{
4707   match(Set dst (LoadN mem));
4708   ins_cost(MEMORY_REF_COST);
4709   size(Z_DISP3_SIZE);
4710   format %{ "LoadN  $dst,$mem\t# (cOop)" %}
4711   opcode(LLGF_ZOPC, LLGF_ZOPC);
4712   ins_encode(z_form_rt_mem_opt(dst, mem));
4713   ins_pipe(pipe_class_dummy);
4714 %}
4715 
4716 // Load narrow Klass Pointer
4717 instruct loadNKlass(iRegN dst, memory mem) %{
4718   match(Set dst (LoadNKlass mem));
4719   ins_cost(MEMORY_REF_COST);
4720   size(Z_DISP3_SIZE);
4721   format %{ "LoadNKlass $dst,$mem\t# (klass cOop)" %}
4722   opcode(LLGF_ZOPC, LLGF_ZOPC);
4723   ins_encode(z_form_rt_mem_opt(dst, mem));
4724   ins_pipe(pipe_class_dummy);
4725 %}
4726 
4727 // Load constant Compressed Pointer
4728 
4729 instruct loadConN(iRegN dst, immN src) %{
4730   match(Set dst src);
4731   ins_cost(DEFAULT_COST);
4732   size(6);
4733   format %{ "loadConN    $dst,$src\t # (cOop)" %}
4734   ins_encode %{
4735     AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4736     __ relocate(cOop.rspec(), 1);
4737     __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4738   %}
4739   ins_pipe(pipe_class_dummy);
4740 %}
4741 
4742 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4743   match(Set dst src);
4744   effect(KILL cr);
4745   ins_cost(DEFAULT_COST_LOW);
4746   size(4);
4747   format %{ "loadConN    $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4748   opcode(XGR_ZOPC);
4749   ins_encode(z_rreform(dst, dst));
4750   ins_pipe(pipe_class_dummy);
4751 %}
4752 
4753 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4754   match(Set dst src);
4755   ins_cost(DEFAULT_COST);
4756   size(6);
4757   format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4758   ins_encode %{
4759     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4760     __ relocate(NKlass.rspec(), 1);
4761     __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4762   %}
4763   ins_pipe(pipe_class_dummy);
4764 %}
4765 
4766 // Load and Decode Compressed Pointer
4767 // optimized variants for Unscaled cOops
4768 
4769 instruct decodeLoadN(iRegP dst, memory mem) %{
4770   match(Set dst (DecodeN (LoadN mem)));
4771   predicate(false && (Universe::narrow_oop_base()==NULL)&&(Universe::narrow_oop_shift()==0));
4772   ins_cost(MEMORY_REF_COST);
4773   size(Z_DISP3_SIZE);
4774   format %{ "DecodeLoadN  $dst,$mem\t# (cOop Load+Decode)" %}
4775   opcode(LLGF_ZOPC, LLGF_ZOPC);
4776   ins_encode(z_form_rt_mem_opt(dst, mem));
4777   ins_pipe(pipe_class_dummy);
4778 %}
4779 
4780 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4781   match(Set dst (DecodeNKlass (LoadNKlass mem)));
4782   predicate(false && (Universe::narrow_klass_base()==NULL)&&(Universe::narrow_klass_shift()==0));
4783   ins_cost(MEMORY_REF_COST);
4784   size(Z_DISP3_SIZE);
4785   format %{ "DecodeLoadNKlass  $dst,$mem\t# (load/decode NKlass)" %}
4786   opcode(LLGF_ZOPC, LLGF_ZOPC);
4787   ins_encode(z_form_rt_mem_opt(dst, mem));
4788   ins_pipe(pipe_class_dummy);
4789 %}
4790 
4791 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4792   match(Set dst (DecodeNKlass src));
4793   ins_cost(3 * DEFAULT_COST);
4794   size(12);
4795   format %{ "DecodeLoadConNKlass  $dst,$src\t # decode(cKlass)" %}
4796   ins_encode %{
4797     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4798     __ relocate(NKlass.rspec(), 1);
4799     __ load_const($dst$$Register, (Klass*)NKlass.value());
4800   %}
4801   ins_pipe(pipe_class_dummy);
4802 %}
4803 
4804 // Decode Compressed Pointer
4805 
4806 // General decoder
4807 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4808   match(Set dst (DecodeN src));
4809   effect(KILL cr);
4810   predicate(Universe::narrow_oop_base() == NULL || !ExpandLoadingBaseDecode);
4811   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4812   // TODO: s390 port size(VARIABLE_SIZE);
4813   format %{ "decodeN  $dst,$src\t# (decode cOop)" %}
4814   ins_encode %{  __ oop_decoder($dst$$Register, $src$$Register, true); %}
4815   ins_pipe(pipe_class_dummy);
4816 %}
4817 
4818 // General Klass decoder
4819 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4820   match(Set dst (DecodeNKlass src));
4821   effect(KILL cr);
4822   ins_cost(3 * DEFAULT_COST);
4823   format %{ "decode_klass $dst,$src" %}
4824   ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4825   ins_pipe(pipe_class_dummy);
4826 %}
4827 
4828 // General decoder
4829 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4830   match(Set dst (DecodeN src));
4831   effect(KILL cr);
4832   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4833              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4834             (Universe::narrow_oop_base()== NULL || !ExpandLoadingBaseDecode_NN));
4835   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4836   // TODO: s390 port size(VARIABLE_SIZE);
4837   format %{ "decodeN  $dst,$src\t# (decode cOop NN)" %}
4838   ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4839   ins_pipe(pipe_class_dummy);
4840 %}
4841 
4842   instruct loadBase(iRegL dst, immL baseImm) %{
4843     effect(DEF dst, USE baseImm);
4844     predicate(false);
4845     format %{ "llihl    $dst=$baseImm \t// load heap base" %}
4846     ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4847     ins_pipe(pipe_class_dummy);
4848   %}
4849 
4850   // Decoder for heapbased mode peeling off loading the base.
4851   instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4852     match(Set dst (DecodeN src base));
4853     // Note: Effect TEMP dst was used with the intention to get
4854     // different regs for dst and base, but this has caused ADLC to
4855     // generate wrong code. Oop_decoder generates additional lgr when
4856     // dst==base.
4857     effect(KILL cr);
4858     predicate(false);
4859     // TODO: s390 port size(VARIABLE_SIZE);
4860     format %{ "decodeN  $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
4861     ins_encode %{
4862       __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4863                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
4864     %}
4865     ins_pipe(pipe_class_dummy);
4866   %}
4867 
4868   // Decoder for heapbased mode peeling off loading the base.
4869   instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4870     match(Set dst (DecodeN src base));
4871     effect(KILL cr);
4872     predicate(false);
4873     // TODO: s390 port size(VARIABLE_SIZE);
4874     format %{ "decodeN  $dst = ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
4875     ins_encode %{
4876       __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
4877                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
4878     %}
4879     ins_pipe(pipe_class_dummy);
4880   %}
4881 
4882 // Decoder for heapbased mode peeling off loading the base.
4883 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4884   match(Set dst (DecodeN src));
4885   predicate(Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode);
4886   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4887   // TODO: s390 port size(VARIABLE_SIZE);
4888   expand %{
4889     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
4890     iRegL base;
4891     loadBase(base, baseImm);
4892     decodeN_base(dst, src, base, cr);
4893   %}
4894 %}
4895 
4896 // Decoder for heapbased mode peeling off loading the base.
4897 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4898   match(Set dst (DecodeN src));
4899   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4900              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4901             Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode_NN);
4902   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4903   // TODO: s390 port size(VARIABLE_SIZE);
4904   expand %{
4905     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
4906     iRegL base;
4907     loadBase(base, baseImm);
4908     decodeN_NN_base(dst, src, base, cr);
4909   %}
4910 %}
4911 
4912 //  Encode Compressed Pointer
4913 
4914 // General encoder
4915 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
4916   match(Set dst (EncodeP src));
4917   effect(KILL cr);
4918   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4919             (Universe::narrow_oop_base() == 0 ||
4920              Universe::narrow_oop_base_disjoint() ||
4921              !ExpandLoadingBaseEncode));
4922   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4923   // TODO: s390 port size(VARIABLE_SIZE);
4924   format %{ "encodeP  $dst,$src\t# (encode cOop)" %}
4925   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4926   ins_pipe(pipe_class_dummy);
4927 %}
4928 
4929 // General class encoder
4930 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
4931   match(Set dst (EncodePKlass src));
4932   effect(KILL cr);
4933   format %{ "encode_klass $dst,$src" %}
4934   ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
4935   ins_pipe(pipe_class_dummy);
4936 %}
4937 
4938 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
4939   match(Set dst (EncodeP src));
4940   effect(KILL cr);
4941   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
4942             (Universe::narrow_oop_base() == 0 ||
4943              Universe::narrow_oop_base_disjoint() ||
4944              !ExpandLoadingBaseEncode_NN));
4945   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4946   // TODO: s390 port size(VARIABLE_SIZE);
4947   format %{ "encodeP  $dst,$src\t# (encode cOop)" %}
4948   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4949   ins_pipe(pipe_class_dummy);
4950 %}
4951 
4952   // Encoder for heapbased mode peeling off loading the base.
4953   instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
4954     match(Set dst (EncodeP src (Binary base dst)));
4955     effect(TEMP_DEF dst);
4956     predicate(false);
4957     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4958     // TODO: s390 port size(VARIABLE_SIZE);
4959     format %{ "encodeP  $dst = ($src>>3) +$base + pow2_offset\t# (encode cOop)" %}
4960     ins_encode %{
4961       jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
4962         (((uint64_t)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift());
4963       __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
4964     %}
4965     ins_pipe(pipe_class_dummy);
4966   %}
4967 
4968   // Encoder for heapbased mode peeling off loading the base.
4969   instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
4970     match(Set dst (EncodeP src base));
4971     effect(USE pow2_offset);
4972     predicate(false);
4973     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4974     // TODO: s390 port size(VARIABLE_SIZE);
4975     format %{ "encodeP  $dst = ($src>>3) +$base + $pow2_offset\t# (encode cOop)" %}
4976     ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
4977     ins_pipe(pipe_class_dummy);
4978   %}
4979 
4980 // Encoder for heapbased mode peeling off loading the base.
4981 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
4982   match(Set dst (EncodeP src));
4983   effect(KILL cr);
4984   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4985             (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode));
4986   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4987   // TODO: s390 port size(VARIABLE_SIZE);
4988   expand %{
4989     immL baseImm %{ ((jlong)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift() %}
4990     immL_0 zero %{ (0) %}
4991     flagsReg ccr;
4992     iRegL base;
4993     iRegL negBase;
4994     loadBase(base, baseImm);
4995     negL_reg_reg(negBase, zero, base, ccr);
4996     encodeP_base(dst, src, negBase);
4997   %}
4998 %}
4999 
5000 // Encoder for heapbased mode peeling off loading the base.
5001 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5002   match(Set dst (EncodeP src));
5003   effect(KILL cr);
5004   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5005             (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode_NN));
5006   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5007   // TODO: s390 port size(VARIABLE_SIZE);
5008   expand %{
5009     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
5010     immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)Universe::narrow_oop_base())) %}
5011     immL_0 zero %{ 0 %}
5012     flagsReg ccr;
5013     iRegL base;
5014     iRegL negBase;
5015     loadBase(base, baseImm);
5016     negL_reg_reg(negBase, zero, base, ccr);
5017     encodeP_NN_base(dst, src, negBase, pow2_offset);
5018   %}
5019 %}
5020 
5021 //  Store Compressed Pointer
5022 
5023 // Store Compressed Pointer
5024 instruct storeN(memory mem, iRegN_P2N src) %{
5025   match(Set mem (StoreN mem src));
5026   ins_cost(MEMORY_REF_COST);
5027   size(Z_DISP_SIZE);
5028   format %{ "ST      $src,$mem\t# (cOop)" %}
5029   opcode(STY_ZOPC, ST_ZOPC);
5030   ins_encode(z_form_rt_mem_opt(src, mem));
5031   ins_pipe(pipe_class_dummy);
5032 %}
5033 
5034 // Store Compressed Klass pointer
5035 instruct storeNKlass(memory mem, iRegN src) %{
5036   match(Set mem (StoreNKlass mem src));
5037   ins_cost(MEMORY_REF_COST);
5038   size(Z_DISP_SIZE);
5039   format %{ "ST      $src,$mem\t# (cKlass)" %}
5040   opcode(STY_ZOPC, ST_ZOPC);
5041   ins_encode(z_form_rt_mem_opt(src, mem));
5042   ins_pipe(pipe_class_dummy);
5043 %}
5044 
5045 // Compare Compressed Pointers
5046 
5047 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5048   match(Set cr (CmpN src1 src2));
5049   ins_cost(DEFAULT_COST);
5050   size(2);
5051   format %{ "CLR     $src1,$src2\t# (cOop)" %}
5052   opcode(CLR_ZOPC);
5053   ins_encode(z_rrform(src1, src2));
5054   ins_pipe(pipe_class_dummy);
5055 %}
5056 
5057 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5058   match(Set cr (CmpN src1 src2));
5059   ins_cost(DEFAULT_COST);
5060   size(6);
5061   format %{ "CLFI    $src1,$src2\t# (cOop) compare immediate narrow" %}
5062   ins_encode %{
5063     AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5064     __ relocate(cOop.rspec(), 1);
5065     __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5066   %}
5067   ins_pipe(pipe_class_dummy);
5068 %}
5069 
5070 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5071   match(Set cr (CmpN src1 src2));
5072   ins_cost(DEFAULT_COST);
5073   size(6);
5074   format %{ "CLFI    $src1,$src2\t# (NKlass) compare immediate narrow" %}
5075   ins_encode %{
5076     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5077     __ relocate(NKlass.rspec(), 1);
5078     __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5079   %}
5080   ins_pipe(pipe_class_dummy);
5081 %}
5082 
5083 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5084   match(Set cr (CmpN src1 src2));
5085   ins_cost(DEFAULT_COST);
5086   size(2);
5087   format %{ "LTR     $src1,$src2\t# (cOop) LTR because comparing against zero" %}
5088   opcode(LTR_ZOPC);
5089   ins_encode(z_rrform(src1, src1));
5090   ins_pipe(pipe_class_dummy);
5091 %}
5092 
5093 
5094 //----------MemBar Instructions-----------------------------------------------
5095 
5096 // Memory barrier flavors
5097 
5098 instruct membar_acquire() %{
5099   match(MemBarAcquire);
5100   match(LoadFence);
5101   ins_cost(4*MEMORY_REF_COST);
5102   size(0);
5103   format %{ "MEMBAR-acquire" %}
5104   ins_encode %{ __ z_acquire(); %}
5105   ins_pipe(pipe_class_dummy);
5106 %}
5107 
5108 instruct membar_acquire_lock() %{
5109   match(MemBarAcquireLock);
5110   ins_cost(0);
5111   size(0);
5112   format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5113   ins_encode(/*empty*/);
5114   ins_pipe(pipe_class_dummy);
5115 %}
5116 
5117 instruct membar_release() %{
5118   match(MemBarRelease);
5119   match(StoreFence);
5120   ins_cost(4 * MEMORY_REF_COST);
5121   size(0);
5122   format %{ "MEMBAR-release" %}
5123   ins_encode %{ __ z_release(); %}
5124   ins_pipe(pipe_class_dummy);
5125 %}
5126 
5127 instruct membar_release_lock() %{
5128   match(MemBarReleaseLock);
5129   ins_cost(0);
5130   size(0);
5131   format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5132   ins_encode(/*empty*/);
5133   ins_pipe(pipe_class_dummy);
5134 %}
5135 
5136 instruct membar_volatile() %{
5137   match(MemBarVolatile);
5138   ins_cost(4 * MEMORY_REF_COST);
5139   size(2);
5140   format %{ "MEMBAR-volatile" %}
5141   ins_encode %{ __ z_fence(); %}
5142   ins_pipe(pipe_class_dummy);
5143 %}
5144 
5145 instruct unnecessary_membar_volatile() %{
5146   match(MemBarVolatile);
5147   predicate(Matcher::post_store_load_barrier(n));
5148   ins_cost(0);
5149   size(0);
5150   format %{ "# MEMBAR-volatile (empty)" %}
5151   ins_encode(/*empty*/);
5152   ins_pipe(pipe_class_dummy);
5153 %}
5154 
5155 instruct membar_CPUOrder() %{
5156   match(MemBarCPUOrder);
5157   ins_cost(0);
5158   // TODO: s390 port size(FIXED_SIZE);
5159   format %{ "MEMBAR-CPUOrder (empty)" %}
5160   ins_encode(/*empty*/);
5161   ins_pipe(pipe_class_dummy);
5162 %}
5163 
5164 instruct membar_storestore() %{
5165   match(MemBarStoreStore);
5166   ins_cost(0);
5167   size(0);
5168   format %{ "MEMBAR-storestore (empty)" %}
5169   ins_encode();
5170   ins_pipe(pipe_class_dummy);
5171 %}
5172 
5173 
5174 //----------Register Move Instructions-----------------------------------------
5175 instruct roundDouble_nop(regD dst) %{
5176   match(Set dst (RoundDouble dst));
5177   ins_cost(0);
5178   // TODO: s390 port size(FIXED_SIZE);
5179   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5180   ins_encode();
5181   ins_pipe(pipe_class_dummy);
5182 %}
5183 
5184 instruct roundFloat_nop(regF dst) %{
5185   match(Set dst (RoundFloat dst));
5186   ins_cost(0);
5187   // TODO: s390 port size(FIXED_SIZE);
5188   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5189   ins_encode();
5190   ins_pipe(pipe_class_dummy);
5191 %}
5192 
5193 // Cast Long to Pointer for unsafe natives.
5194 instruct castX2P(iRegP dst, iRegL src) %{
5195   match(Set dst (CastX2P src));
5196   // TODO: s390 port size(VARIABLE_SIZE);
5197   format %{ "LGR     $dst,$src\t # CastX2P" %}
5198   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5199   ins_pipe(pipe_class_dummy);
5200 %}
5201 
5202 // Cast Pointer to Long for unsafe natives.
5203 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5204   match(Set dst (CastP2X src));
5205   // TODO: s390 port size(VARIABLE_SIZE);
5206   format %{ "LGR     $dst,$src\t # CastP2X" %}
5207   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5208   ins_pipe(pipe_class_dummy);
5209 %}
5210 
5211 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5212   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5213   match(Set stkSlot src);   // chain rule
5214   ins_cost(MEMORY_REF_COST);
5215   // TODO: s390 port size(FIXED_SIZE);
5216   format %{ " STD   $src,$stkSlot\t # stk" %}
5217   opcode(STD_ZOPC);
5218   ins_encode(z_form_rt_mem(src, stkSlot));
5219   ins_pipe(pipe_class_dummy);
5220 %}
5221 
5222 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5223   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5224   match(Set stkSlot src);   // chain rule
5225   ins_cost(MEMORY_REF_COST);
5226   // TODO: s390 port size(FIXED_SIZE);
5227   format %{ "STE   $src,$stkSlot\t # stk" %}
5228   opcode(STE_ZOPC);
5229   ins_encode(z_form_rt_mem(src, stkSlot));
5230   ins_pipe(pipe_class_dummy);
5231 %}
5232 
5233 //----------Conditional Move---------------------------------------------------
5234 
5235 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5236   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5237   ins_cost(DEFAULT_COST + BRANCH_COST);
5238   // TODO: s390 port size(VARIABLE_SIZE);
5239   format %{ "CMoveN,$cmp   $dst,$src" %}
5240   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5241   ins_pipe(pipe_class_dummy);
5242 %}
5243 
5244 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5245   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5246   ins_cost(DEFAULT_COST + BRANCH_COST);
5247   // TODO: s390 port size(VARIABLE_SIZE);
5248   format %{ "CMoveN,$cmp   $dst,$src" %}
5249   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5250   ins_pipe(pipe_class_dummy);
5251 %}
5252 
5253 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5254   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5255   ins_cost(DEFAULT_COST + BRANCH_COST);
5256   // TODO: s390 port size(VARIABLE_SIZE);
5257   format %{ "CMoveI,$cmp   $dst,$src" %}
5258   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5259   ins_pipe(pipe_class_dummy);
5260 %}
5261 
5262 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5263   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5264   ins_cost(DEFAULT_COST + BRANCH_COST);
5265   // TODO: s390 port size(VARIABLE_SIZE);
5266   format %{ "CMoveI,$cmp   $dst,$src" %}
5267   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5268   ins_pipe(pipe_class_dummy);
5269 %}
5270 
5271 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5272   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5273   ins_cost(DEFAULT_COST + BRANCH_COST);
5274   // TODO: s390 port size(VARIABLE_SIZE);
5275   format %{ "CMoveP,$cmp    $dst,$src" %}
5276   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5277   ins_pipe(pipe_class_dummy);
5278 %}
5279 
5280 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5281   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5282   ins_cost(DEFAULT_COST + BRANCH_COST);
5283   // TODO: s390 port size(VARIABLE_SIZE);
5284   format %{ "CMoveP,$cmp  $dst,$src" %}
5285   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5286   ins_pipe(pipe_class_dummy);
5287 %}
5288 
5289 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5290   match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5291   ins_cost(DEFAULT_COST + BRANCH_COST);
5292   // TODO: s390 port size(VARIABLE_SIZE);
5293   format %{ "CMoveF,$cmp   $dst,$src" %}
5294   ins_encode %{
5295     // Don't emit code if operands are identical (same register).
5296     if ($dst$$FloatRegister != $src$$FloatRegister) {
5297       Label done;
5298       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5299       __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5300       __ bind(done);
5301     }
5302   %}
5303   ins_pipe(pipe_class_dummy);
5304 %}
5305 
5306 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5307   match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5308   ins_cost(DEFAULT_COST + BRANCH_COST);
5309   // TODO: s390 port size(VARIABLE_SIZE);
5310   format %{ "CMoveD,$cmp   $dst,$src" %}
5311   ins_encode %{
5312     // Don't emit code if operands are identical (same register).
5313     if ($dst$$FloatRegister != $src$$FloatRegister) {
5314       Label done;
5315       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5316       __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5317       __ bind(done);
5318     }
5319   %}
5320   ins_pipe(pipe_class_dummy);
5321 %}
5322 
5323 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5324   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5325   ins_cost(DEFAULT_COST + BRANCH_COST);
5326   // TODO: s390 port size(VARIABLE_SIZE);
5327   format %{ "CMoveL,$cmp  $dst,$src" %}
5328   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5329   ins_pipe(pipe_class_dummy);
5330 %}
5331 
5332 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5333   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5334   ins_cost(DEFAULT_COST + BRANCH_COST);
5335   // TODO: s390 port size(VARIABLE_SIZE);
5336   format %{ "CMoveL,$cmp  $dst,$src" %}
5337   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5338   ins_pipe(pipe_class_dummy);
5339 %}
5340 
5341 //----------OS and Locking Instructions----------------------------------------
5342 
5343 // This name is KNOWN by the ADLC and cannot be changed.
5344 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5345 // for this guy.
5346 instruct tlsLoadP(threadRegP dst) %{
5347   match(Set dst (ThreadLocal));
5348   ins_cost(0);
5349   size(0);
5350   ins_should_rematerialize(true);
5351   format %{ "# $dst=ThreadLocal" %}
5352   ins_encode(/* empty */);
5353   ins_pipe(pipe_class_dummy);
5354 %}
5355 
5356 instruct checkCastPP(iRegP dst) %{
5357   match(Set dst (CheckCastPP dst));
5358   size(0);
5359   format %{ "# checkcastPP of $dst" %}
5360   ins_encode(/*empty*/);
5361   ins_pipe(pipe_class_dummy);
5362 %}
5363 
5364 instruct castPP(iRegP dst) %{
5365   match(Set dst (CastPP dst));
5366   size(0);
5367   format %{ "# castPP of $dst" %}
5368   ins_encode(/*empty*/);
5369   ins_pipe(pipe_class_dummy);
5370 %}
5371 
5372 instruct castII(iRegI dst) %{
5373   match(Set dst (CastII dst));
5374   size(0);
5375   format %{ "# castII of $dst" %}
5376   ins_encode(/*empty*/);
5377   ins_pipe(pipe_class_dummy);
5378 %}
5379 
5380 
5381 //----------Conditional_store--------------------------------------------------
5382 // Conditional-store of the updated heap-top.
5383 // Used during allocation of the shared heap.
5384 // Sets flags (EQ) on success.
5385 
5386 // Implement LoadPLocked. Must be ordered against changes of the memory location
5387 // by storePConditional.
5388 // Don't know whether this is ever used.
5389 instruct loadPLocked(iRegP dst, memory mem) %{
5390   match(Set dst (LoadPLocked mem));
5391   ins_cost(MEMORY_REF_COST);
5392   size(Z_DISP3_SIZE);
5393   format %{ "LG      $dst,$mem\t # LoadPLocked" %}
5394   opcode(LG_ZOPC, LG_ZOPC);
5395   ins_encode(z_form_rt_mem_opt(dst, mem));
5396   ins_pipe(pipe_class_dummy);
5397 %}
5398 
5399 // As compareAndSwapP, but return flag register instead of boolean value in
5400 // int register.
5401 // This instruction is matched if UseTLAB is off. Needed to pass
5402 // option tests.  Mem_ptr must be a memory operand, else this node
5403 // does not get Flag_needs_anti_dependence_check set by adlc. If this
5404 // is not set this node can be rematerialized which leads to errors.
5405 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
5406   match(Set cr (StorePConditional mem_ptr (Binary oldval newval)));
5407   effect(KILL oldval);
5408   // TODO: s390 port size(FIXED_SIZE);
5409   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5410   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5411   ins_pipe(pipe_class_dummy);
5412 %}
5413 
5414 // As compareAndSwapL, but return flag register instead of boolean value in
5415 // int register.
5416 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory
5417 // operand, else this node does not get
5418 // Flag_needs_anti_dependence_check set by adlc. If this is not set
5419 // this node can be rematerialized which leads to errors.
5420 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
5421   match(Set cr (StoreLConditional mem_ptr (Binary oldval newval)));
5422   effect(KILL oldval);
5423   // TODO: s390 port size(FIXED_SIZE);
5424   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5425   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5426   ins_pipe(pipe_class_dummy);
5427 %}
5428 
5429 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5430 
5431 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5432   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5433   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5434   size(16);
5435   format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5436   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5437              z_enc_cctobool(res));
5438   ins_pipe(pipe_class_dummy);
5439 %}
5440 
5441 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5442   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5443   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5444   size(18);
5445   format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5446   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5447              z_enc_cctobool(res));
5448   ins_pipe(pipe_class_dummy);
5449 %}
5450 
5451 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5452   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5453   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5454   size(18);
5455   format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5456   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5457              z_enc_cctobool(res));
5458   ins_pipe(pipe_class_dummy);
5459 %}
5460 
5461 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5462   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5463   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5464   size(16);
5465   format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5466   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5467              z_enc_cctobool(res));
5468   ins_pipe(pipe_class_dummy);
5469 %}
5470 
5471 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5472 
5473 // Exploit: direct memory arithmetic
5474 // Prereqs: - instructions available
5475 //          - instructions guarantee atomicity
5476 //          - immediate operand to be added
5477 //          - immediate operand is small enough (8-bit signed).
5478 //          - result of instruction is not used
5479 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5480   match(Set dummy (GetAndAddI mem src));
5481   effect(KILL cr);
5482   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5483   ins_cost(MEMORY_REF_COST);
5484   size(6);
5485   format %{ "ASI     [$mem],$src\t # GetAndAddI (atomic)" %}
5486   opcode(ASI_ZOPC);
5487   ins_encode(z_siyform(mem, src));
5488   ins_pipe(pipe_class_dummy);
5489 %}
5490 
5491 // Fallback: direct memory arithmetic not available
5492 // Disadvantages: - CS-Loop required, very expensive.
5493 //                - more code generated (26 to xx bytes vs. 6 bytes)
5494 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5495   match(Set dst (GetAndAddI mem src));
5496   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5497   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5498   format %{ "BEGIN ATOMIC {\n\t"
5499             "  LGF     $dst,[$mem]\n\t"
5500             "  AHIK    $tmp,$dst,$src\n\t"
5501             "  CSY     $dst,$tmp,$mem\n\t"
5502             "  retry if failed\n\t"
5503             "} END ATOMIC"
5504          %}
5505   ins_encode %{
5506     Register Rdst = $dst$$Register;
5507     Register Rtmp = $tmp$$Register;
5508     int      Isrc = $src$$constant;
5509     Label    retry;
5510 
5511     // Iterate until update with incremented value succeeds.
5512     __ z_lgf(Rdst, $mem$$Address);    // current contents
5513     __ bind(retry);
5514       // Calculate incremented value.
5515       if (VM_Version::has_DistinctOpnds()) {
5516         __ z_ahik(Rtmp, Rdst, Isrc);
5517       } else {
5518         __ z_lr(Rtmp, Rdst);
5519         __ z_ahi(Rtmp, Isrc);
5520       }
5521       // Swap into memory location.
5522       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5523     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5524   %}
5525   ins_pipe(pipe_class_dummy);
5526 %}
5527 
5528 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5529   match(Set dst (GetAndAddI mem src));
5530   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5531   ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5532   format %{ "BEGIN ATOMIC {\n\t"
5533             "  LGF     $dst,[$mem]\n\t"
5534             "  LGR     $tmp,$dst\n\t"
5535             "  AFI     $tmp,$src\n\t"
5536             "  CSY     $dst,$tmp,$mem\n\t"
5537             "  retry if failed\n\t"
5538             "} END ATOMIC"
5539          %}
5540   ins_encode %{
5541     Register Rdst = $dst$$Register;
5542     Register Rtmp = $tmp$$Register;
5543     int      Isrc = $src$$constant;
5544     Label    retry;
5545 
5546     // Iterate until update with incremented value succeeds.
5547     __ z_lgf(Rdst, $mem$$Address);    // current contents
5548     __ bind(retry);
5549       // Calculate incremented value.
5550       __ z_lr(Rtmp, Rdst);
5551       __ z_afi(Rtmp, Isrc);
5552       // Swap into memory location.
5553       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5554     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5555   %}
5556   ins_pipe(pipe_class_dummy);
5557 %}
5558 
5559 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5560   match(Set dst (GetAndAddI mem src));
5561   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5562   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5563   format %{ "BEGIN ATOMIC {\n\t"
5564             "  LGF     $dst,[$mem]\n\t"
5565             "  ARK     $tmp,$dst,$src\n\t"
5566             "  CSY     $dst,$tmp,$mem\n\t"
5567             "  retry if failed\n\t"
5568             "} END ATOMIC"
5569          %}
5570   ins_encode %{
5571     Register Rsrc = $src$$Register;
5572     Register Rdst = $dst$$Register;
5573     Register Rtmp = $tmp$$Register;
5574     Label    retry;
5575 
5576     // Iterate until update with incremented value succeeds.
5577     __ z_lgf(Rdst, $mem$$Address);  // current contents
5578     __ bind(retry);
5579       // Calculate incremented value.
5580       if (VM_Version::has_DistinctOpnds()) {
5581         __ z_ark(Rtmp, Rdst, Rsrc);
5582       } else {
5583         __ z_lr(Rtmp, Rdst);
5584         __ z_ar(Rtmp, Rsrc);
5585       }
5586       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5587     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5588   %}
5589   ins_pipe(pipe_class_dummy);
5590 %}
5591 
5592 
5593 // Exploit: direct memory arithmetic
5594 // Prereqs: - instructions available
5595 //          - instructions guarantee atomicity
5596 //          - immediate operand to be added
5597 //          - immediate operand is small enough (8-bit signed).
5598 //          - result of instruction is not used
5599 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5600   match(Set dummy (GetAndAddL mem src));
5601   effect(KILL cr);
5602   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5603   ins_cost(MEMORY_REF_COST);
5604   size(6);
5605   format %{ "AGSI    [$mem],$src\t # GetAndAddL (atomic)" %}
5606   opcode(AGSI_ZOPC);
5607   ins_encode(z_siyform(mem, src));
5608   ins_pipe(pipe_class_dummy);
5609 %}
5610 
5611 // Fallback: direct memory arithmetic not available
5612 // Disadvantages: - CS-Loop required, very expensive.
5613 //                - more code generated (26 to xx bytes vs. 6 bytes)
5614 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5615   match(Set dst (GetAndAddL mem src));
5616   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5617   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5618   format %{ "BEGIN ATOMIC {\n\t"
5619             "  LG      $dst,[$mem]\n\t"
5620             "  AGHIK   $tmp,$dst,$src\n\t"
5621             "  CSG     $dst,$tmp,$mem\n\t"
5622             "  retry if failed\n\t"
5623             "} END ATOMIC"
5624          %}
5625   ins_encode %{
5626     Register Rdst = $dst$$Register;
5627     Register Rtmp = $tmp$$Register;
5628     int      Isrc = $src$$constant;
5629     Label    retry;
5630 
5631     // Iterate until update with incremented value succeeds.
5632     __ z_lg(Rdst, $mem$$Address);  // current contents
5633     __ bind(retry);
5634       // Calculate incremented value.
5635       if (VM_Version::has_DistinctOpnds()) {
5636         __ z_aghik(Rtmp, Rdst, Isrc);
5637       } else {
5638         __ z_lgr(Rtmp, Rdst);
5639         __ z_aghi(Rtmp, Isrc);
5640       }
5641       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5642     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5643   %}
5644   ins_pipe(pipe_class_dummy);
5645 %}
5646 
5647 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5648   match(Set dst (GetAndAddL mem src));
5649   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5650   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5651   format %{ "BEGIN ATOMIC {\n\t"
5652             "  LG      $dst,[$mem]\n\t"
5653             "  LGR     $tmp,$dst\n\t"
5654             "  AGFI    $tmp,$src\n\t"
5655             "  CSG     $dst,$tmp,$mem\n\t"
5656             "  retry if failed\n\t"
5657             "} END ATOMIC"
5658          %}
5659   ins_encode %{
5660     Register Rdst = $dst$$Register;
5661     Register Rtmp = $tmp$$Register;
5662     int      Isrc = $src$$constant;
5663     Label    retry;
5664 
5665     // Iterate until update with incremented value succeeds.
5666     __ z_lg(Rdst, $mem$$Address);  // current contents
5667     __ bind(retry);
5668       // Calculate incremented value.
5669       __ z_lgr(Rtmp, Rdst);
5670       __ z_agfi(Rtmp, Isrc);
5671       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5672     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5673   %}
5674   ins_pipe(pipe_class_dummy);
5675 %}
5676 
5677 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5678   match(Set dst (GetAndAddL mem src));
5679   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5680   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5681   format %{ "BEGIN ATOMIC {\n\t"
5682             "  LG      $dst,[$mem]\n\t"
5683             "  AGRK    $tmp,$dst,$src\n\t"
5684             "  CSG     $dst,$tmp,$mem\n\t"
5685             "  retry if failed\n\t"
5686             "} END ATOMIC"
5687          %}
5688   ins_encode %{
5689     Register Rsrc = $src$$Register;
5690     Register Rdst = $dst$$Register;
5691     Register Rtmp = $tmp$$Register;
5692     Label    retry;
5693 
5694     // Iterate until update with incremented value succeeds.
5695     __ z_lg(Rdst, $mem$$Address);  // current contents
5696     __ bind(retry);
5697       // Calculate incremented value.
5698       if (VM_Version::has_DistinctOpnds()) {
5699         __ z_agrk(Rtmp, Rdst, Rsrc);
5700       } else {
5701         __ z_lgr(Rtmp, Rdst);
5702         __ z_agr(Rtmp, Rsrc);
5703       }
5704       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5705     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5706   %}
5707   ins_pipe(pipe_class_dummy);
5708 %}
5709 
5710 // Increment value in memory, save old value in dst.
5711 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5712   match(Set dst (GetAndAddI mem src));
5713   predicate(VM_Version::has_LoadAndALUAtomicV1());
5714   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5715   size(6);
5716   format %{ "LAA     $dst,$src,[$mem]" %}
5717   ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5718   ins_pipe(pipe_class_dummy);
5719 %}
5720 
5721 // Increment value in memory, save old value in dst.
5722 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5723   match(Set dst (GetAndAddL mem src));
5724   predicate(VM_Version::has_LoadAndALUAtomicV1());
5725   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5726   size(6);
5727   format %{ "LAAG    $dst,$src,[$mem]" %}
5728   ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5729   ins_pipe(pipe_class_dummy);
5730 %}
5731 
5732 
5733 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5734   match(Set dst (GetAndSetI mem dst));
5735   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5736   format %{ "XCHGI   $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5737   ins_encode(z_enc_SwapI(mem, dst, tmp));
5738   ins_pipe(pipe_class_dummy);
5739 %}
5740 
5741 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5742   match(Set dst (GetAndSetL mem dst));
5743   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5744   format %{ "XCHGL   $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5745   ins_encode(z_enc_SwapL(mem, dst, tmp));
5746   ins_pipe(pipe_class_dummy);
5747 %}
5748 
5749 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5750   match(Set dst (GetAndSetN mem dst));
5751   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5752   format %{ "XCHGN   $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5753   ins_encode(z_enc_SwapI(mem, dst, tmp));
5754   ins_pipe(pipe_class_dummy);
5755 %}
5756 
5757 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5758   match(Set dst (GetAndSetP mem dst));
5759   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5760   format %{ "XCHGP   $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5761   ins_encode(z_enc_SwapL(mem, dst, tmp));
5762   ins_pipe(pipe_class_dummy);
5763 %}
5764 
5765 
5766 //----------Arithmetic Instructions--------------------------------------------
5767 
5768 // The rules are sorted by right operand type and operand length. Please keep
5769 // it that way.
5770 // Left operand type is always reg. Left operand len is I, L, P
5771 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5772 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5773 
5774 // ADD
5775 
5776 // REG = REG + REG
5777 
5778 // Register Addition
5779 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5780   match(Set dst (AddI dst src));
5781   effect(KILL cr);
5782   // TODO: s390 port size(FIXED_SIZE);
5783   format %{ "AR      $dst,$src\t # int  CISC ALU" %}
5784   opcode(AR_ZOPC);
5785   ins_encode(z_rrform(dst, src));
5786   ins_pipe(pipe_class_dummy);
5787 %}
5788 
5789 // Avoid use of LA(Y) for general ALU operation.
5790 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5791   match(Set dst (AddI src1 src2));
5792   effect(KILL cr);
5793   predicate(VM_Version::has_DistinctOpnds());
5794   ins_cost(DEFAULT_COST);
5795   size(4);
5796   format %{ "ARK     $dst,$src1,$src2\t # int  RISC ALU" %}
5797   opcode(ARK_ZOPC);
5798   ins_encode(z_rrfform(dst, src1, src2));
5799   ins_pipe(pipe_class_dummy);
5800 %}
5801 
5802 // REG = REG + IMM
5803 
5804 // Avoid use of LA(Y) for general ALU operation.
5805 // Immediate Addition
5806 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5807   match(Set dst (AddI dst con));
5808   effect(KILL cr);
5809   ins_cost(DEFAULT_COST);
5810   // TODO: s390 port size(FIXED_SIZE);
5811   format %{ "AHI     $dst,$con\t # int  CISC ALU" %}
5812   opcode(AHI_ZOPC);
5813   ins_encode(z_riform_signed(dst, con));
5814   ins_pipe(pipe_class_dummy);
5815 %}
5816 
5817 // Avoid use of LA(Y) for general ALU operation.
5818 // Immediate Addition
5819 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5820   match(Set dst (AddI src con));
5821   effect(KILL cr);
5822   predicate( VM_Version::has_DistinctOpnds());
5823   ins_cost(DEFAULT_COST);
5824   // TODO: s390 port size(FIXED_SIZE);
5825   format %{ "AHIK    $dst,$src,$con\t # int  RISC ALU" %}
5826   opcode(AHIK_ZOPC);
5827   ins_encode(z_rieform_d(dst, src, con));
5828   ins_pipe(pipe_class_dummy);
5829 %}
5830 
5831 // Immediate Addition
5832 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5833   match(Set dst (AddI dst src));
5834   effect(KILL cr);
5835   ins_cost(DEFAULT_COST_HIGH);
5836   size(6);
5837   format %{ "AFI     $dst,$src" %}
5838   opcode(AFI_ZOPC);
5839   ins_encode(z_rilform_signed(dst, src));
5840   ins_pipe(pipe_class_dummy);
5841 %}
5842 
5843 // Immediate Addition
5844 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5845   match(Set dst (AddI src con));
5846   predicate(PreferLAoverADD);
5847   ins_cost(DEFAULT_COST_LOW);
5848   size(4);
5849   format %{ "LA      $dst,$con(,$src)\t # int d12(,b)" %}
5850   opcode(LA_ZOPC);
5851   ins_encode(z_rxform_imm_reg(dst, con, src));
5852   ins_pipe(pipe_class_dummy);
5853 %}
5854 
5855 // Immediate Addition
5856 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
5857   match(Set dst (AddI src con));
5858   predicate(PreferLAoverADD);
5859   ins_cost(DEFAULT_COST);
5860   size(6);
5861   format %{ "LAY     $dst,$con(,$src)\t # int d20(,b)" %}
5862   opcode(LAY_ZOPC);
5863   ins_encode(z_rxyform_imm_reg(dst, con, src));
5864   ins_pipe(pipe_class_dummy);
5865 %}
5866 
5867 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
5868   match(Set dst (AddI (AddI src1 src2) con));
5869   predicate( PreferLAoverADD);
5870   ins_cost(DEFAULT_COST_LOW);
5871   size(4);
5872   format %{ "LA      $dst,$con($src1,$src2)\t # int d12(x,b)" %}
5873   opcode(LA_ZOPC);
5874   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
5875   ins_pipe(pipe_class_dummy);
5876 %}
5877 
5878 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
5879   match(Set dst (AddI (AddI src1 src2) con));
5880   predicate(PreferLAoverADD);
5881   ins_cost(DEFAULT_COST);
5882   size(6);
5883   format %{ "LAY     $dst,$con($src1,$src2)\t # int d20(x,b)" %}
5884   opcode(LAY_ZOPC);
5885   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
5886   ins_pipe(pipe_class_dummy);
5887 %}
5888 
5889 // REG = REG + MEM
5890 
5891 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
5892   match(Set dst (AddI dst (LoadI src)));
5893   effect(KILL cr);
5894   ins_cost(MEMORY_REF_COST);
5895   // TODO: s390 port size(VARIABLE_SIZE);
5896   format %{ "A(Y)    $dst, $src\t # int" %}
5897   opcode(AY_ZOPC, A_ZOPC);
5898   ins_encode(z_form_rt_mem_opt(dst, src));
5899   ins_pipe(pipe_class_dummy);
5900 %}
5901 
5902 // MEM = MEM + IMM
5903 
5904 // Add Immediate to 4-byte memory operand and result
5905 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
5906   match(Set mem (StoreI mem (AddI (LoadI mem) src)));
5907   effect(KILL cr);
5908   predicate(VM_Version::has_MemWithImmALUOps());
5909   ins_cost(MEMORY_REF_COST);
5910   size(6);
5911   format %{ "ASI     $mem,$src\t # direct mem add 4" %}
5912   opcode(ASI_ZOPC);
5913   ins_encode(z_siyform(mem, src));
5914   ins_pipe(pipe_class_dummy);
5915 %}
5916 
5917 
5918 //
5919 
5920 // REG = REG + REG
5921 
5922 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
5923   match(Set dst (AddL dst (ConvI2L src)));
5924   effect(KILL cr);
5925   size(4);
5926   format %{ "AGFR    $dst,$src\t # long<-int CISC ALU" %}
5927   opcode(AGFR_ZOPC);
5928   ins_encode(z_rreform(dst, src));
5929   ins_pipe(pipe_class_dummy);
5930 %}
5931 
5932 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
5933   match(Set dst (AddL dst src));
5934   effect(KILL cr);
5935   // TODO: s390 port size(FIXED_SIZE);
5936   format %{ "AGR     $dst, $src\t # long CISC ALU" %}
5937   opcode(AGR_ZOPC);
5938   ins_encode(z_rreform(dst, src));
5939   ins_pipe(pipe_class_dummy);
5940 %}
5941 
5942 // Avoid use of LA(Y) for general ALU operation.
5943 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
5944   match(Set dst (AddL src1 src2));
5945   effect(KILL cr);
5946   predicate(VM_Version::has_DistinctOpnds());
5947   ins_cost(DEFAULT_COST);
5948   size(4);
5949   format %{ "AGRK    $dst,$src1,$src2\t # long RISC ALU" %}
5950   opcode(AGRK_ZOPC);
5951   ins_encode(z_rrfform(dst, src1, src2));
5952   ins_pipe(pipe_class_dummy);
5953 %}
5954 
5955 // REG = REG + IMM
5956 
5957 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
5958   match(Set dst (AddL src con));
5959   predicate( PreferLAoverADD);
5960   ins_cost(DEFAULT_COST_LOW);
5961   size(4);
5962   format %{ "LA      $dst,$con(,$src)\t # long d12(,b)" %}
5963   opcode(LA_ZOPC);
5964   ins_encode(z_rxform_imm_reg(dst, con, src));
5965   ins_pipe(pipe_class_dummy);
5966 %}
5967 
5968 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
5969   match(Set dst (AddL src con));
5970   predicate(PreferLAoverADD);
5971   ins_cost(DEFAULT_COST);
5972   size(6);
5973   format %{ "LAY     $dst,$con(,$src)\t # long d20(,b)" %}
5974   opcode(LAY_ZOPC);
5975   ins_encode(z_rxyform_imm_reg(dst, con, src));
5976   ins_pipe(pipe_class_dummy);
5977 %}
5978 
5979 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
5980   match(Set dst (AddL dst con));
5981   effect(KILL cr);
5982   ins_cost(DEFAULT_COST_HIGH);
5983   size(6);
5984   format %{ "AGFI    $dst,$con\t # long CISC ALU" %}
5985   opcode(AGFI_ZOPC);
5986   ins_encode(z_rilform_signed(dst, con));
5987   ins_pipe(pipe_class_dummy);
5988 %}
5989 
5990 // Avoid use of LA(Y) for general ALU operation.
5991 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
5992   match(Set dst (AddL dst con));
5993   effect(KILL cr);
5994   ins_cost(DEFAULT_COST);
5995   // TODO: s390 port size(FIXED_SIZE);
5996   format %{ "AGHI    $dst,$con\t # long CISC ALU" %}
5997   opcode(AGHI_ZOPC);
5998   ins_encode(z_riform_signed(dst, con));
5999   ins_pipe(pipe_class_dummy);
6000 %}
6001 
6002 // Avoid use of LA(Y) for general ALU operation.
6003 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6004   match(Set dst (AddL src con));
6005   effect(KILL cr);
6006   predicate( VM_Version::has_DistinctOpnds());
6007   ins_cost(DEFAULT_COST);
6008   size(6);
6009   format %{ "AGHIK   $dst,$src,$con\t # long RISC ALU" %}
6010   opcode(AGHIK_ZOPC);
6011   ins_encode(z_rieform_d(dst, src, con));
6012   ins_pipe(pipe_class_dummy);
6013 %}
6014 
6015 // REG = REG + MEM
6016 
6017 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6018   match(Set dst (AddL dst (ConvI2L (LoadI src))));
6019   effect(KILL cr);
6020   ins_cost(MEMORY_REF_COST);
6021   size(Z_DISP3_SIZE);
6022   format %{ "AGF     $dst, $src\t # long/int" %}
6023   opcode(AGF_ZOPC, AGF_ZOPC);
6024   ins_encode(z_form_rt_mem_opt(dst, src));
6025   ins_pipe(pipe_class_dummy);
6026 %}
6027 
6028 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6029   match(Set dst (AddL dst (LoadL src)));
6030   effect(KILL cr);
6031   ins_cost(MEMORY_REF_COST);
6032   size(Z_DISP3_SIZE);
6033   format %{ "AG      $dst, $src\t # long" %}
6034   opcode(AG_ZOPC, AG_ZOPC);
6035   ins_encode(z_form_rt_mem_opt(dst, src));
6036   ins_pipe(pipe_class_dummy);
6037 %}
6038 
6039 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6040   match(Set dst (AddL (AddL src1 src2) con));
6041   predicate( PreferLAoverADD);
6042   ins_cost(DEFAULT_COST_LOW);
6043   size(4);
6044   format %{ "LA     $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6045   opcode(LA_ZOPC);
6046   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6047   ins_pipe(pipe_class_dummy);
6048 %}
6049 
6050 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6051   match(Set dst (AddL (AddL src1 src2) con));
6052   predicate(PreferLAoverADD);
6053   ins_cost(DEFAULT_COST);
6054   size(6);
6055   format %{ "LAY    $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6056   opcode(LAY_ZOPC);
6057   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6058   ins_pipe(pipe_class_dummy);
6059 %}
6060 
6061 // MEM = MEM + IMM
6062 
6063 // Add Immediate to 8-byte memory operand and result.
6064 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6065   match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6066   effect(KILL cr);
6067   predicate(VM_Version::has_MemWithImmALUOps());
6068   ins_cost(MEMORY_REF_COST);
6069   size(6);
6070   format %{ "AGSI    $mem,$src\t # direct mem add 8" %}
6071   opcode(AGSI_ZOPC);
6072   ins_encode(z_siyform(mem, src));
6073   ins_pipe(pipe_class_dummy);
6074 %}
6075 
6076 
6077 // REG = REG + REG
6078 
6079 // Ptr Addition
6080 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6081   match(Set dst (AddP src1 src2));
6082   predicate( PreferLAoverADD);
6083   ins_cost(DEFAULT_COST);
6084   size(4);
6085   format %{ "LA      $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6086   opcode(LA_ZOPC);
6087   ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6088   ins_pipe(pipe_class_dummy);
6089 %}
6090 
6091 // Ptr Addition
6092 // Avoid use of LA(Y) for general ALU operation.
6093 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6094   match(Set dst (AddP dst src));
6095   effect(KILL cr);
6096   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6097   ins_cost(DEFAULT_COST);
6098   // TODO: s390 port size(FIXED_SIZE);
6099   format %{ "ALGR    $dst,$src\t # ptr CICS ALU" %}
6100   opcode(ALGR_ZOPC);
6101   ins_encode(z_rreform(dst, src));
6102   ins_pipe(pipe_class_dummy);
6103 %}
6104 
6105 // Ptr Addition
6106 // Avoid use of LA(Y) for general ALU operation.
6107 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6108   match(Set dst (AddP src1 src2));
6109   effect(KILL cr);
6110   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6111   ins_cost(DEFAULT_COST);
6112   // TODO: s390 port size(FIXED_SIZE);
6113   format %{ "ALGRK   $dst,$src1,$src2\t # ptr RISC ALU" %}
6114   opcode(ALGRK_ZOPC);
6115   ins_encode(z_rrfform(dst, src1, src2));
6116   ins_pipe(pipe_class_dummy);
6117 %}
6118 
6119 // REG = REG + IMM
6120 
6121 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6122   match(Set dst (AddP src con));
6123   predicate( PreferLAoverADD);
6124   ins_cost(DEFAULT_COST_LOW);
6125   size(4);
6126   format %{ "LA      $dst,$con(,$src)\t # ptr d12(,b)" %}
6127   opcode(LA_ZOPC);
6128   ins_encode(z_rxform_imm_reg(dst, con, src));
6129   ins_pipe(pipe_class_dummy);
6130 %}
6131 
6132 // Avoid use of LA(Y) for general ALU operation.
6133 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6134   match(Set dst (AddP dst src));
6135   effect(KILL cr);
6136   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6137   ins_cost(DEFAULT_COST);
6138   // TODO: s390 port size(FIXED_SIZE);
6139   format %{ "AGHI    $dst,$src\t # ptr CISC ALU" %}
6140   opcode(AGHI_ZOPC);
6141   ins_encode(z_riform_signed(dst, src));
6142   ins_pipe(pipe_class_dummy);
6143 %}
6144 
6145 // Avoid use of LA(Y) for general ALU operation.
6146 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6147   match(Set dst (AddP src con));
6148   effect(KILL cr);
6149   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6150   ins_cost(DEFAULT_COST);
6151   // TODO: s390 port size(FIXED_SIZE);
6152   format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6153   opcode(ALGHSIK_ZOPC);
6154   ins_encode(z_rieform_d(dst, src, con));
6155   ins_pipe(pipe_class_dummy);
6156 %}
6157 
6158 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6159   match(Set dst (AddP src con));
6160   predicate(PreferLAoverADD);
6161   ins_cost(DEFAULT_COST);
6162   size(6);
6163   format %{ "LAY     $dst,$con(,$src)\t # ptr d20(,b)" %}
6164   opcode(LAY_ZOPC);
6165   ins_encode(z_rxyform_imm_reg(dst, con, src));
6166   ins_pipe(pipe_class_dummy);
6167 %}
6168 
6169 // Pointer Immediate Addition
6170 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6171   match(Set dst (AddP dst src));
6172   effect(KILL cr);
6173   ins_cost(DEFAULT_COST_HIGH);
6174   // TODO: s390 port size(FIXED_SIZE);
6175   format %{ "AGFI    $dst,$src\t # ptr" %}
6176   opcode(AGFI_ZOPC);
6177   ins_encode(z_rilform_signed(dst, src));
6178   ins_pipe(pipe_class_dummy);
6179 %}
6180 
6181 // REG = REG1 + REG2 + IMM
6182 
6183 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6184   match(Set dst (AddP (AddP src1 src2) con));
6185   predicate( PreferLAoverADD);
6186   ins_cost(DEFAULT_COST_LOW);
6187   size(4);
6188   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6189   opcode(LA_ZOPC);
6190   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6191   ins_pipe(pipe_class_dummy);
6192 %}
6193 
6194 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6195   match(Set dst (AddP (AddP src1 src2) con));
6196   predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6197   ins_cost(DEFAULT_COST_LOW);
6198   size(4);
6199   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6200   opcode(LA_ZOPC);
6201   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6202   ins_pipe(pipe_class_dummy);
6203 %}
6204 
6205 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6206   match(Set dst (AddP (AddP src1 src2) con));
6207   predicate(PreferLAoverADD);
6208   ins_cost(DEFAULT_COST);
6209   // TODO: s390 port size(FIXED_SIZE);
6210   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6211   opcode(LAY_ZOPC);
6212   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6213   ins_pipe(pipe_class_dummy);
6214 %}
6215 
6216 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6217   match(Set dst (AddP (AddP src1 src2) con));
6218   predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6219   ins_cost(DEFAULT_COST);
6220   // TODO: s390 port size(FIXED_SIZE);
6221   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6222   opcode(LAY_ZOPC);
6223   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6224   ins_pipe(pipe_class_dummy);
6225 %}
6226 
6227 // MEM = MEM + IMM
6228 
6229 // Add Immediate to 8-byte memory operand and result
6230 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6231   match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6232   effect(KILL cr);
6233   predicate(VM_Version::has_MemWithImmALUOps());
6234   ins_cost(MEMORY_REF_COST);
6235   size(6);
6236   format %{ "AGSI    $mem,$src\t # direct mem add 8 (ptr)" %}
6237   opcode(AGSI_ZOPC);
6238   ins_encode(z_siyform(mem, src));
6239   ins_pipe(pipe_class_dummy);
6240 %}
6241 
6242 // SUB
6243 
6244 // Register Subtraction
6245 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6246   match(Set dst (SubI dst src));
6247   effect(KILL cr);
6248   // TODO: s390 port size(FIXED_SIZE);
6249   format %{ "SR      $dst,$src\t # int  CISC ALU" %}
6250   opcode(SR_ZOPC);
6251   ins_encode(z_rrform(dst, src));
6252   ins_pipe(pipe_class_dummy);
6253 %}
6254 
6255 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6256   match(Set dst (SubI src1 src2));
6257   effect(KILL cr);
6258   predicate(VM_Version::has_DistinctOpnds());
6259   ins_cost(DEFAULT_COST);
6260   size(4);
6261   format %{ "SRK     $dst,$src1,$src2\t # int  RISC ALU" %}
6262   opcode(SRK_ZOPC);
6263   ins_encode(z_rrfform(dst, src1, src2));
6264   ins_pipe(pipe_class_dummy);
6265 %}
6266 
6267 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6268   match(Set dst (SubI dst (LoadI src)));
6269   effect(KILL cr);
6270   ins_cost(MEMORY_REF_COST);
6271   // TODO: s390 port size(VARIABLE_SIZE);
6272   format %{ "S(Y)    $dst, $src\t # int" %}
6273   opcode(SY_ZOPC, S_ZOPC);
6274   ins_encode(z_form_rt_mem_opt(dst, src));
6275   ins_pipe(pipe_class_dummy);
6276 %}
6277 
6278 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6279   match(Set dst (SubI zero src));
6280   effect(KILL cr);
6281   size(2);
6282   format %{ "NEG     $dst, $src" %}
6283   ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6284   ins_pipe(pipe_class_dummy);
6285 %}
6286 
6287 //
6288 
6289 // Long subtraction
6290 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6291   match(Set dst (SubL dst src));
6292   effect(KILL cr);
6293   // TODO: s390 port size(FIXED_SIZE);
6294   format %{ "SGR     $dst,$src\t # int  CISC ALU" %}
6295   opcode(SGR_ZOPC);
6296   ins_encode(z_rreform(dst, src));
6297   ins_pipe(pipe_class_dummy);
6298 %}
6299 
6300 // Avoid use of LA(Y) for general ALU operation.
6301 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6302   match(Set dst (SubL src1 src2));
6303   effect(KILL cr);
6304   predicate(VM_Version::has_DistinctOpnds());
6305   ins_cost(DEFAULT_COST);
6306   size(4);
6307   format %{ "SGRK    $dst,$src1,$src2\t # int  RISC ALU" %}
6308   opcode(SGRK_ZOPC);
6309   ins_encode(z_rrfform(dst, src1, src2));
6310   ins_pipe(pipe_class_dummy);
6311 %}
6312 
6313 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6314   match(Set dst (SubL dst (ConvI2L src)));
6315   effect(KILL cr);
6316   size(4);
6317   format %{ "SGFR    $dst, $src\t # int  CISC ALU" %}
6318   opcode(SGFR_ZOPC);
6319   ins_encode(z_rreform(dst, src));
6320   ins_pipe(pipe_class_dummy);
6321 %}
6322 
6323 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6324   match(Set dst (SubL dst (ConvI2L (LoadI src))));
6325   effect(KILL cr);
6326   ins_cost(MEMORY_REF_COST);
6327   size(Z_DISP3_SIZE);
6328   format %{ "SGF     $dst, $src\t # long/int" %}
6329   opcode(SGF_ZOPC, SGF_ZOPC);
6330   ins_encode(z_form_rt_mem_opt(dst, src));
6331   ins_pipe(pipe_class_dummy);
6332 %}
6333 
6334 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6335   match(Set dst (SubL dst (LoadL src)));
6336   effect(KILL cr);
6337   ins_cost(MEMORY_REF_COST);
6338   size(Z_DISP3_SIZE);
6339   format %{ "SG      $dst, $src\t # long" %}
6340   opcode(SG_ZOPC, SG_ZOPC);
6341   ins_encode(z_form_rt_mem_opt(dst, src));
6342   ins_pipe(pipe_class_dummy);
6343 %}
6344 
6345 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6346 
6347 //  MUL
6348 
6349 // Register Multiplication
6350 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6351   match(Set dst (MulI dst src));
6352   ins_cost(DEFAULT_COST);
6353   size(4);
6354   format %{ "MSR     $dst, $src" %}
6355   opcode(MSR_ZOPC);
6356   ins_encode(z_rreform(dst, src));
6357   ins_pipe(pipe_class_dummy);
6358 %}
6359 
6360 // Immediate Multiplication
6361 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6362   match(Set dst (MulI dst con));
6363   ins_cost(DEFAULT_COST);
6364   // TODO: s390 port size(FIXED_SIZE);
6365   format %{ "MHI     $dst,$con" %}
6366   opcode(MHI_ZOPC);
6367   ins_encode(z_riform_signed(dst,con));
6368   ins_pipe(pipe_class_dummy);
6369 %}
6370 
6371 // Immediate (32bit) Multiplication
6372 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6373   match(Set dst (MulI dst con));
6374   ins_cost(DEFAULT_COST);
6375   size(6);
6376   format %{ "MSFI    $dst,$con" %}
6377   opcode(MSFI_ZOPC);
6378   ins_encode(z_rilform_signed(dst,con));
6379   ins_pipe(pipe_class_dummy);
6380 %}
6381 
6382 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6383   match(Set dst (MulI dst (LoadI src)));
6384   ins_cost(MEMORY_REF_COST);
6385   // TODO: s390 port size(VARIABLE_SIZE);
6386   format %{ "MS(Y)   $dst, $src\t # int" %}
6387   opcode(MSY_ZOPC, MS_ZOPC);
6388   ins_encode(z_form_rt_mem_opt(dst, src));
6389   ins_pipe(pipe_class_dummy);
6390 %}
6391 
6392 //
6393 
6394 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6395   match(Set dst (MulL dst (ConvI2L src)));
6396   ins_cost(DEFAULT_COST);
6397   // TODO: s390 port size(FIXED_SIZE);
6398   format %{ "MSGFR   $dst $src\t # long/int" %}
6399   opcode(MSGFR_ZOPC);
6400   ins_encode(z_rreform(dst, src));
6401   ins_pipe(pipe_class_dummy);
6402 %}
6403 
6404 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6405   match(Set dst (MulL dst src));
6406   ins_cost(DEFAULT_COST);
6407   size(4);
6408   format %{ "MSGR    $dst $src\t # long" %}
6409   opcode(MSGR_ZOPC);
6410   ins_encode(z_rreform(dst, src));
6411   ins_pipe(pipe_class_dummy);
6412 %}
6413 
6414 // Immediate Multiplication
6415 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6416   match(Set dst (MulL dst src));
6417   ins_cost(DEFAULT_COST);
6418   // TODO: s390 port size(FIXED_SIZE);
6419   format %{ "MGHI    $dst,$src\t # long" %}
6420   opcode(MGHI_ZOPC);
6421   ins_encode(z_riform_signed(dst, src));
6422   ins_pipe(pipe_class_dummy);
6423 %}
6424 
6425 // Immediate (32bit) Multiplication
6426 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6427   match(Set dst (MulL dst con));
6428   ins_cost(DEFAULT_COST);
6429   size(6);
6430   format %{ "MSGFI   $dst,$con" %}
6431   opcode(MSGFI_ZOPC);
6432   ins_encode(z_rilform_signed(dst,con));
6433   ins_pipe(pipe_class_dummy);
6434 %}
6435 
6436 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6437   match(Set dst (MulL dst (ConvI2L (LoadI src))));
6438   ins_cost(MEMORY_REF_COST);
6439   size(Z_DISP3_SIZE);
6440   format %{ "MSGF    $dst, $src\t # long" %}
6441   opcode(MSGF_ZOPC, MSGF_ZOPC);
6442   ins_encode(z_form_rt_mem_opt(dst, src));
6443   ins_pipe(pipe_class_dummy);
6444 %}
6445 
6446 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6447   match(Set dst (MulL dst (LoadL src)));
6448   ins_cost(MEMORY_REF_COST);
6449   size(Z_DISP3_SIZE);
6450   format %{ "MSG     $dst, $src\t # long" %}
6451   opcode(MSG_ZOPC, MSG_ZOPC);
6452   ins_encode(z_form_rt_mem_opt(dst, src));
6453   ins_pipe(pipe_class_dummy);
6454 %}
6455 
6456 //  DIV
6457 
6458 // Integer DIVMOD with Register, both quotient and mod results
6459 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6460   match(DivModI dst1src1 src2);
6461   effect(KILL cr);
6462   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6463   size(VM_Version::has_CompareBranch() ? 24 : 26);
6464   format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6465   ins_encode %{
6466     Register d1s1 = $dst1src1$$Register;
6467     Register d2   = $dst2$$Register;
6468     Register s2   = $src2$$Register;
6469 
6470     assert_different_registers(d1s1, s2);
6471 
6472     Label do_div, done_div;
6473     if (VM_Version::has_CompareBranch()) {
6474       __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6475     } else {
6476       __ z_chi(s2, -1);
6477       __ z_brne(do_div);
6478     }
6479     __ z_lcr(d1s1, d1s1);
6480     __ clear_reg(d2, false, false);
6481     __ z_bru(done_div);
6482     __ bind(do_div);
6483     __ z_lgfr(d1s1, d1s1);
6484     __ z_dsgfr(d2, s2);
6485     __ bind(done_div);
6486   %}
6487   ins_pipe(pipe_class_dummy);
6488 %}
6489 
6490 
6491 // Register Division
6492 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6493   match(Set dst (DivI src1 src2));
6494   effect(KILL tmp, KILL cr);
6495   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6496   size(VM_Version::has_CompareBranch() ? 20 : 22);
6497   format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6498   ins_encode %{
6499     Register a = $src1$$Register;
6500     Register b = $src2$$Register;
6501     Register t = $dst$$Register;
6502 
6503     assert_different_registers(t, b);
6504 
6505     Label do_div, done_div;
6506     if (VM_Version::has_CompareBranch()) {
6507       __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6508     } else {
6509       __ z_chi(b, -1);
6510       __ z_brne(do_div);
6511     }
6512     __ z_lcr(t, a);
6513     __ z_bru(done_div);
6514     __ bind(do_div);
6515     __ z_lgfr(t, a);
6516     __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6517     __ bind(done_div);
6518   %}
6519   ins_pipe(pipe_class_dummy);
6520 %}
6521 
6522 // Immediate Division
6523 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6524   match(Set dst (DivI src1 src2));
6525   effect(KILL tmp, KILL cr);  // R0 is killed, too.
6526   ins_cost(2 * DEFAULT_COST);
6527   // TODO: s390 port size(VARIABLE_SIZE);
6528   format %{ "DIV_const  $dst,$src1,$src2" %}
6529   ins_encode %{
6530     // No sign extension of Rdividend needed here.
6531     if ($src2$$constant != -1) {
6532       __ z_lghi(Z_R0_scratch, $src2$$constant);
6533       __ z_lgfr($dst$$Register, $src1$$Register);
6534       __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6535     } else {
6536       __ z_lcr($dst$$Register, $src1$$Register);
6537     }
6538   %}
6539   ins_pipe(pipe_class_dummy);
6540 %}
6541 
6542 // Long DIVMOD with Register, both quotient and mod results
6543 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6544   match(DivModL dst1src1 src2);
6545   effect(KILL cr);
6546   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6547   size(VM_Version::has_CompareBranch() ? 22 : 24);
6548   format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6549   ins_encode %{
6550     Register d1s1 = $dst1src1$$Register;
6551     Register d2   = $dst2$$Register;
6552     Register s2   = $src2$$Register;
6553 
6554     Label do_div, done_div;
6555     if (VM_Version::has_CompareBranch()) {
6556       __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6557     } else {
6558       __ z_cghi(s2, -1);
6559       __ z_brne(do_div);
6560     }
6561     __ z_lcgr(d1s1, d1s1);
6562     // indicate unused result
6563     (void) __ clear_reg(d2, true, false);
6564     __ z_bru(done_div);
6565     __ bind(do_div);
6566     __ z_dsgr(d2, s2);
6567     __ bind(done_div);
6568   %}
6569   ins_pipe(pipe_class_dummy);
6570 %}
6571 
6572 // Register Long Division
6573 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6574   match(Set dst (DivL dst src));
6575   effect(KILL tmp, KILL cr);
6576   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6577   size(VM_Version::has_CompareBranch() ? 18 : 20);
6578   format %{ "DIVG_checked  $dst, $src\t # long, treats special case 0x80../-1" %}
6579   ins_encode %{
6580     Register b = $src$$Register;
6581     Register t = $dst$$Register;
6582 
6583     Label done_div;
6584     __ z_lcgr(t, t);    // Does no harm. divisor is in other register.
6585     if (VM_Version::has_CompareBranch()) {
6586       __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6587     } else {
6588       __ z_cghi(b, -1);
6589       __ z_bre(done_div);
6590     }
6591     __ z_lcgr(t, t);    // Restore sign.
6592     __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6593     __ bind(done_div);
6594   %}
6595   ins_pipe(pipe_class_dummy);
6596 %}
6597 
6598 // Immediate Long Division
6599 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6600   match(Set dst (DivL src1 src2));
6601   effect(KILL tmp, KILL cr);  // R0 is killed, too.
6602   ins_cost(2 * DEFAULT_COST);
6603   // TODO: s390 port size(VARIABLE_SIZE);
6604   format %{ "DIVG_const  $dst,$src1,$src2\t # long" %}
6605   ins_encode %{
6606     if ($src2$$constant != -1) {
6607       __ z_lghi(Z_R0_scratch, $src2$$constant);
6608       __ lgr_if_needed($dst$$Register, $src1$$Register);
6609       __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6610     } else {
6611       __ z_lcgr($dst$$Register, $src1$$Register);
6612     }
6613   %}
6614   ins_pipe(pipe_class_dummy);
6615 %}
6616 
6617 // REM
6618 
6619 // Integer Remainder
6620 // Register Remainder
6621 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6622   match(Set dst (ModI src1 src2));
6623   effect(KILL tmp, KILL cr);
6624   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6625   // TODO: s390 port size(VARIABLE_SIZE);
6626   format %{ "MOD_checked   $dst,$src1,$src2" %}
6627   ins_encode %{
6628     Register a = $src1$$Register;
6629     Register b = $src2$$Register;
6630     Register t = $dst$$Register;
6631     assert_different_registers(t->successor(), b);
6632 
6633     Label do_div, done_div;
6634 
6635     if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6636       (void) __ clear_reg(t, true, false);  // Does no harm. Operands are in other regs.
6637       if (VM_Version::has_CompareBranch()) {
6638         __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6639       } else {
6640         __ z_chi(b, -1);
6641         __ z_bre(done_div);
6642       }
6643       __ z_lgfr(t->successor(), a);
6644       __ z_dsgfr(t/* t is even part of a register pair. */, b);
6645     } else {
6646       if (VM_Version::has_CompareBranch()) {
6647         __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6648       } else {
6649         __ z_chi(b, -1);
6650         __ z_brne(do_div);
6651       }
6652       __ clear_reg(t, true, false);
6653       __ z_bru(done_div);
6654       __ bind(do_div);
6655       __ z_lgfr(t->successor(), a);
6656       __ z_dsgfr(t/* t is even part of a register pair. */, b);
6657     }
6658     __ bind(done_div);
6659   %}
6660   ins_pipe(pipe_class_dummy);
6661 %}
6662 
6663 // Immediate Remainder
6664 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6665   match(Set dst (ModI src1 src2));
6666   effect(KILL tmp, KILL cr); // R0 is killed, too.
6667   ins_cost(3 * DEFAULT_COST);
6668   // TODO: s390 port size(VARIABLE_SIZE);
6669   format %{ "MOD_const  $dst,src1,$src2" %}
6670   ins_encode %{
6671     assert_different_registers($dst$$Register, $src1$$Register);
6672     assert_different_registers($dst$$Register->successor(), $src1$$Register);
6673     int divisor = $src2$$constant;
6674 
6675     if (divisor != -1) {
6676       __ z_lghi(Z_R0_scratch, divisor);
6677       __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6678       __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6679     } else {
6680       __ clear_reg($dst$$Register, true, false);
6681     }
6682   %}
6683   ins_pipe(pipe_class_dummy);
6684 %}
6685 
6686 // Register Long Remainder
6687 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6688   match(Set dst (ModL src1 src2));
6689   effect(KILL src1, KILL cr); // R0 is killed, too.
6690   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6691   // TODO: s390 port size(VARIABLE_SIZE);
6692   format %{ "MODG_checked   $dst,$src1,$src2" %}
6693   ins_encode %{
6694     Register a = $src1$$Register;
6695     Register b = $src2$$Register;
6696     Register t = $dst$$Register;
6697     assert(t->successor() == a, "(t,a) is an even-odd pair" );
6698 
6699     Label do_div, done_div;
6700     if (t->encoding() != b->encoding()) {
6701       (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6702       if (VM_Version::has_CompareBranch()) {
6703         __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6704       } else {
6705         __ z_cghi(b, -1);
6706         __ z_bre(done_div);
6707       }
6708       __ z_dsgr(t, b);
6709     } else {
6710       if (VM_Version::has_CompareBranch()) {
6711         __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6712       } else {
6713         __ z_cghi(b, -1);
6714         __ z_brne(do_div);
6715       }
6716       __ clear_reg(t, true, false);
6717       __ z_bru(done_div);
6718       __ bind(do_div);
6719       __ z_dsgr(t, b);
6720     }
6721     __ bind(done_div);
6722   %}
6723   ins_pipe(pipe_class_dummy);
6724 %}
6725 
6726 // Register Long Remainder
6727 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
6728   match(Set dst (ModL src1 src2));
6729   effect(KILL tmp, KILL cr); // R0 is killed, too.
6730   ins_cost(3 * DEFAULT_COST);
6731   // TODO: s390 port size(VARIABLE_SIZE);
6732   format %{ "MODG_const  $dst,src1,$src2\t # long" %}
6733   ins_encode %{
6734     int divisor = $src2$$constant;
6735     if (divisor != -1) {
6736       __ z_lghi(Z_R0_scratch, divisor);
6737       __ z_lgr($dst$$Register->successor(), $src1$$Register);
6738       __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch);  // Instruction kills tmp.
6739     } else {
6740       __ clear_reg($dst$$Register, true, false);
6741     }
6742   %}
6743   ins_pipe(pipe_class_dummy);
6744 %}
6745 
6746 // SHIFT
6747 
6748 // Shift left logical
6749 
6750 // Register Shift Left variable
6751 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
6752   match(Set dst (LShiftI src nbits));
6753   effect(KILL cr); // R1 is killed, too.
6754   ins_cost(3 * DEFAULT_COST);
6755   size(14);
6756   format %{ "SLL     $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %}
6757   ins_encode %{
6758     __ z_lgr(Z_R1_scratch, $nbits$$Register);
6759     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6760     __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6761   %}
6762   ins_pipe(pipe_class_dummy);
6763 %}
6764 
6765 // Register Shift Left Immediate
6766 // Constant shift count is masked in ideal graph already.
6767 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6768   match(Set dst (LShiftI src nbits));
6769   size(6);
6770   format %{ "SLL     $dst,$src,$nbits\t# use RISC-like SLLG also for int" %}
6771   ins_encode %{
6772     int Nbit = $nbits$$constant;
6773     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6774     __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6775   %}
6776   ins_pipe(pipe_class_dummy);
6777 %}
6778 
6779 // Register Shift Left Immediate by 1bit
6780 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6781   match(Set dst (LShiftI src nbits));
6782   predicate(PreferLAoverADD);
6783   ins_cost(DEFAULT_COST_LOW);
6784   size(4);
6785   format %{ "LA      $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6786   ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6787   ins_pipe(pipe_class_dummy);
6788 %}
6789 
6790 // Register Shift Left Long
6791 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
6792   match(Set dst (LShiftL src1 nbits));
6793   size(6);
6794   format %{ "SLLG    $dst,$src1,[$nbits]" %}
6795   opcode(SLLG_ZOPC);
6796   ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
6797   ins_pipe(pipe_class_dummy);
6798 %}
6799 
6800 // Register Shift Left Long Immediate
6801 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
6802   match(Set dst (LShiftL src1 nbits));
6803   size(6);
6804   format %{ "SLLG    $dst,$src1,$nbits" %}
6805   opcode(SLLG_ZOPC);
6806   ins_encode(z_rsyform_const(dst, src1, nbits));
6807   ins_pipe(pipe_class_dummy);
6808 %}
6809 
6810 // Register Shift Left Long Immediate by 1bit
6811 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
6812   match(Set dst (LShiftL src1 nbits));
6813   predicate(PreferLAoverADD);
6814   ins_cost(DEFAULT_COST_LOW);
6815   size(4);
6816   format %{ "LA      $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
6817   ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
6818   ins_pipe(pipe_class_dummy);
6819 %}
6820 
6821 // Shift right arithmetic
6822 
6823 // Register Arithmetic Shift Right
6824 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6825   match(Set dst (RShiftI dst src));
6826   effect(KILL cr); // R1 is killed, too.
6827   ins_cost(3 * DEFAULT_COST);
6828   size(12);
6829   format %{ "SRA     $dst,[$src] & 31" %}
6830   ins_encode %{
6831     __ z_lgr(Z_R1_scratch, $src$$Register);
6832     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6833     __ z_sra($dst$$Register, 0, Z_R1_scratch);
6834   %}
6835   ins_pipe(pipe_class_dummy);
6836 %}
6837 
6838 // Register Arithmetic Shift Right Immediate
6839 // Constant shift count is masked in ideal graph already.
6840 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
6841   match(Set dst (RShiftI dst src));
6842   effect(KILL cr);
6843   size(4);
6844   format %{ "SRA     $dst,$src" %}
6845   ins_encode %{
6846     int Nbit = $src$$constant;
6847     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6848     __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6849   %}
6850   ins_pipe(pipe_class_dummy);
6851 %}
6852 
6853 // Register Arithmetic Shift Right Long
6854 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
6855   match(Set dst (RShiftL src1 src2));
6856   effect(KILL cr);
6857   size(6);
6858   format %{ "SRAG    $dst,$src1,[$src2]" %}
6859   opcode(SRAG_ZOPC);
6860   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6861   ins_pipe(pipe_class_dummy);
6862 %}
6863 
6864 // Register Arithmetic Shift Right Long Immediate
6865 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
6866   match(Set dst (RShiftL src1 src2));
6867   effect(KILL cr);
6868   size(6);
6869   format %{ "SRAG    $dst,$src1,$src2" %}
6870   opcode(SRAG_ZOPC);
6871   ins_encode(z_rsyform_const(dst, src1, src2));
6872   ins_pipe(pipe_class_dummy);
6873 %}
6874 
6875 //  Shift right logical
6876 
6877 // Register Shift Right
6878 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6879   match(Set dst (URShiftI dst src));
6880   effect(KILL cr); // R1 is killed, too.
6881   ins_cost(3 * DEFAULT_COST);
6882   size(12);
6883   format %{ "SRL     $dst,[$src] & 31" %}
6884   ins_encode %{
6885     __ z_lgr(Z_R1_scratch, $src$$Register);
6886     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6887     __ z_srl($dst$$Register, 0, Z_R1_scratch);
6888   %}
6889   ins_pipe(pipe_class_dummy);
6890 %}
6891 
6892 // Register Shift Right Immediate
6893 // Constant shift count is masked in ideal graph already.
6894 instruct srlI_reg_imm(iRegI dst, immI src) %{
6895   match(Set dst (URShiftI dst src));
6896   size(4);
6897   format %{ "SRL     $dst,$src" %}
6898   ins_encode %{
6899     int Nbit = $src$$constant;
6900     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6901     __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6902   %}
6903   ins_pipe(pipe_class_dummy);
6904 %}
6905 
6906 // Register Shift Right Long
6907 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
6908   match(Set dst (URShiftL src1 src2));
6909   size(6);
6910   format %{ "SRLG    $dst,$src1,[$src2]" %}
6911   opcode(SRLG_ZOPC);
6912   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6913   ins_pipe(pipe_class_dummy);
6914 %}
6915 
6916 // Register Shift Right Long Immediate
6917 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
6918   match(Set dst (URShiftL src1 src2));
6919   size(6);
6920   format %{ "SRLG    $dst,$src1,$src2" %}
6921   opcode(SRLG_ZOPC);
6922   ins_encode(z_rsyform_const(dst, src1, src2));
6923   ins_pipe(pipe_class_dummy);
6924 %}
6925 
6926 // Register Shift Right Immediate with a CastP2X
6927 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
6928   match(Set dst (URShiftL (CastP2X src1) src2));
6929   size(6);
6930   format %{ "SRLG    $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
6931   opcode(SRLG_ZOPC);
6932   ins_encode(z_rsyform_const(dst, src1, src2));
6933   ins_pipe(pipe_class_dummy);
6934 %}
6935 
6936 //----------Rotate Instructions------------------------------------------------
6937 
6938 // Rotate left 32bit.
6939 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
6940   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
6941   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
6942   size(6);
6943   format %{ "RLL     $dst,$src,$lshift\t # ROTL32" %}
6944   opcode(RLL_ZOPC);
6945   ins_encode(z_rsyform_const(dst, src, lshift));
6946   ins_pipe(pipe_class_dummy);
6947 %}
6948 
6949 // Rotate left 64bit.
6950 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
6951   match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
6952   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
6953   size(6);
6954   format %{ "RLLG    $dst,$src,$lshift\t # ROTL64" %}
6955   opcode(RLLG_ZOPC);
6956   ins_encode(z_rsyform_const(dst, src, lshift));
6957   ins_pipe(pipe_class_dummy);
6958 %}
6959 
6960 // Rotate right 32bit.
6961 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
6962   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
6963   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
6964   // TODO: s390 port size(FIXED_SIZE);
6965   format %{ "RLL     $dst,$src,$rshift\t # ROTR32" %}
6966   opcode(RLL_ZOPC);
6967   ins_encode(z_rsyform_const(dst, src, rshift));
6968   ins_pipe(pipe_class_dummy);
6969 %}
6970 
6971 // Rotate right 64bit.
6972 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
6973   match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
6974   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
6975   // TODO: s390 port size(FIXED_SIZE);
6976   format %{ "RLLG    $dst,$src,$rshift\t # ROTR64" %}
6977   opcode(RLLG_ZOPC);
6978   ins_encode(z_rsyform_const(dst, src, rshift));
6979   ins_pipe(pipe_class_dummy);
6980 %}
6981 
6982 
6983 //----------Overflow Math Instructions-----------------------------------------
6984 
6985 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
6986   match(Set cr (OverflowAddI op1 op2));
6987   effect(DEF cr, USE op1, USE op2);
6988   // TODO: s390 port size(FIXED_SIZE);
6989   format %{ "AR      $op1,$op2\t # overflow check int" %}
6990   ins_encode %{
6991     __ z_lr(Z_R0_scratch, $op1$$Register);
6992     __ z_ar(Z_R0_scratch, $op2$$Register);
6993   %}
6994   ins_pipe(pipe_class_dummy);
6995 %}
6996 
6997 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
6998   match(Set cr (OverflowAddI op1 op2));
6999   effect(DEF cr, USE op1, USE op2);
7000   // TODO: s390 port size(VARIABLE_SIZE);
7001   format %{ "AR      $op1,$op2\t # overflow check int" %}
7002   ins_encode %{
7003     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7004     __ z_ar(Z_R0_scratch, $op1$$Register);
7005   %}
7006   ins_pipe(pipe_class_dummy);
7007 %}
7008 
7009 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7010   match(Set cr (OverflowAddL op1 op2));
7011   effect(DEF cr, USE op1, USE op2);
7012   // TODO: s390 port size(FIXED_SIZE);
7013   format %{ "AGR     $op1,$op2\t # overflow check long" %}
7014   ins_encode %{
7015     __ z_lgr(Z_R0_scratch, $op1$$Register);
7016     __ z_agr(Z_R0_scratch, $op2$$Register);
7017   %}
7018   ins_pipe(pipe_class_dummy);
7019 %}
7020 
7021 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7022   match(Set cr (OverflowAddL op1 op2));
7023   effect(DEF cr, USE op1, USE op2);
7024   // TODO: s390 port size(VARIABLE_SIZE);
7025   format %{ "AGR     $op1,$op2\t # overflow check long" %}
7026   ins_encode %{
7027     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7028     __ z_agr(Z_R0_scratch, $op1$$Register);
7029   %}
7030   ins_pipe(pipe_class_dummy);
7031 %}
7032 
7033 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7034   match(Set cr (OverflowSubI op1 op2));
7035   effect(DEF cr, USE op1, USE op2);
7036   // TODO: s390 port size(FIXED_SIZE);
7037   format %{ "SR      $op1,$op2\t # overflow check int" %}
7038   ins_encode %{
7039     __ z_lr(Z_R0_scratch, $op1$$Register);
7040     __ z_sr(Z_R0_scratch, $op2$$Register);
7041   %}
7042   ins_pipe(pipe_class_dummy);
7043 %}
7044 
7045 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7046   match(Set cr (OverflowSubI op1 op2));
7047   effect(DEF cr, USE op1, USE op2);
7048   // TODO: s390 port size(VARIABLE_SIZE);
7049   format %{ "SR      $op1,$op2\t # overflow check int" %}
7050   ins_encode %{
7051     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7052     __ z_lr(Z_R0_scratch, $op1$$Register);
7053     __ z_sr(Z_R0_scratch, Z_R1_scratch);
7054   %}
7055   ins_pipe(pipe_class_dummy);
7056 %}
7057 
7058 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7059   match(Set cr (OverflowSubL op1 op2));
7060   effect(DEF cr, USE op1, USE op2);
7061   // TODO: s390 port size(FIXED_SIZE);
7062   format %{ "SGR     $op1,$op2\t # overflow check long" %}
7063   ins_encode %{
7064     __ z_lgr(Z_R0_scratch, $op1$$Register);
7065     __ z_sgr(Z_R0_scratch, $op2$$Register);
7066   %}
7067   ins_pipe(pipe_class_dummy);
7068 %}
7069 
7070 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7071   match(Set cr (OverflowSubL op1 op2));
7072   effect(DEF cr, USE op1, USE op2);
7073   // TODO: s390 port size(VARIABLE_SIZE);
7074   format %{ "SGR     $op1,$op2\t # overflow check long" %}
7075   ins_encode %{
7076     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7077     __ z_lgr(Z_R0_scratch, $op1$$Register);
7078     __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7079   %}
7080   ins_pipe(pipe_class_dummy);
7081 %}
7082 
7083 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7084   match(Set cr (OverflowSubI zero op2));
7085   effect(DEF cr, USE op2);
7086   format %{ "NEG    $op2\t# overflow check int" %}
7087   ins_encode %{
7088     __ clear_reg(Z_R0_scratch, false, false);
7089     __ z_sr(Z_R0_scratch, $op2$$Register);
7090   %}
7091   ins_pipe(pipe_class_dummy);
7092 %}
7093 
7094 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7095   match(Set cr (OverflowSubL zero op2));
7096   effect(DEF cr, USE op2);
7097   format %{ "NEGG    $op2\t# overflow check long" %}
7098   ins_encode %{
7099     __ clear_reg(Z_R0_scratch, true, false);
7100     __ z_sgr(Z_R0_scratch, $op2$$Register);
7101   %}
7102   ins_pipe(pipe_class_dummy);
7103 %}
7104 
7105 // No intrinsics for multiplication, since there is no easy way
7106 // to check for overflow.
7107 
7108 
7109 //----------Floating Point Arithmetic Instructions-----------------------------
7110 
7111 //  ADD
7112 
7113 //  Add float single precision
7114 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7115   match(Set dst (AddF dst src));
7116   effect(KILL cr);
7117   ins_cost(ALU_REG_COST);
7118   size(4);
7119   format %{ "AEBR     $dst,$src" %}
7120   opcode(AEBR_ZOPC);
7121   ins_encode(z_rreform(dst, src));
7122   ins_pipe(pipe_class_dummy);
7123 %}
7124 
7125 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7126   match(Set dst (AddF dst (LoadF src)));
7127   effect(KILL cr);
7128   ins_cost(ALU_MEMORY_COST);
7129   size(6);
7130   format %{ "AEB      $dst,$src\t # floatMemory" %}
7131   opcode(AEB_ZOPC);
7132   ins_encode(z_form_rt_memFP(dst, src));
7133   ins_pipe(pipe_class_dummy);
7134 %}
7135 
7136 // Add float double precision
7137 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7138   match(Set dst (AddD dst src));
7139   effect(KILL cr);
7140   ins_cost(ALU_REG_COST);
7141   size(4);
7142   format %{ "ADBR     $dst,$src" %}
7143   opcode(ADBR_ZOPC);
7144   ins_encode(z_rreform(dst, src));
7145   ins_pipe(pipe_class_dummy);
7146 %}
7147 
7148 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7149   match(Set dst (AddD dst (LoadD src)));
7150   effect(KILL cr);
7151   ins_cost(ALU_MEMORY_COST);
7152   size(6);
7153   format %{ "ADB      $dst,$src\t # doubleMemory" %}
7154   opcode(ADB_ZOPC);
7155   ins_encode(z_form_rt_memFP(dst, src));
7156   ins_pipe(pipe_class_dummy);
7157 %}
7158 
7159 // SUB
7160 
7161 // Sub float single precision
7162 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7163   match(Set dst (SubF dst src));
7164   effect(KILL cr);
7165   ins_cost(ALU_REG_COST);
7166   size(4);
7167   format %{ "SEBR     $dst,$src" %}
7168   opcode(SEBR_ZOPC);
7169   ins_encode(z_rreform(dst, src));
7170   ins_pipe(pipe_class_dummy);
7171 %}
7172 
7173 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7174   match(Set dst (SubF dst (LoadF src)));
7175   effect(KILL cr);
7176   ins_cost(ALU_MEMORY_COST);
7177   size(6);
7178   format %{ "SEB      $dst,$src\t # floatMemory" %}
7179   opcode(SEB_ZOPC);
7180   ins_encode(z_form_rt_memFP(dst, src));
7181   ins_pipe(pipe_class_dummy);
7182 %}
7183 
7184 //  Sub float double precision
7185 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7186   match(Set dst (SubD dst src));
7187   effect(KILL cr);
7188   ins_cost(ALU_REG_COST);
7189   size(4);
7190   format %{ "SDBR     $dst,$src" %}
7191   opcode(SDBR_ZOPC);
7192   ins_encode(z_rreform(dst, src));
7193   ins_pipe(pipe_class_dummy);
7194 %}
7195 
7196 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7197   match(Set dst (SubD dst (LoadD src)));
7198   effect(KILL cr);
7199   ins_cost(ALU_MEMORY_COST);
7200   size(6);
7201   format %{ "SDB      $dst,$src\t # doubleMemory" %}
7202   opcode(SDB_ZOPC);
7203   ins_encode(z_form_rt_memFP(dst, src));
7204   ins_pipe(pipe_class_dummy);
7205 %}
7206 
7207 // MUL
7208 
7209 // Mul float single precision
7210 instruct mulF_reg_reg(regF dst, regF src) %{
7211   match(Set dst (MulF dst src));
7212   // CC unchanged by MUL.
7213   ins_cost(ALU_REG_COST);
7214   size(4);
7215   format %{ "MEEBR    $dst,$src" %}
7216   opcode(MEEBR_ZOPC);
7217   ins_encode(z_rreform(dst, src));
7218   ins_pipe(pipe_class_dummy);
7219 %}
7220 
7221 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7222   match(Set dst (MulF dst (LoadF src)));
7223   // CC unchanged by MUL.
7224   ins_cost(ALU_MEMORY_COST);
7225   size(6);
7226   format %{ "MEEB     $dst,$src\t # floatMemory" %}
7227   opcode(MEEB_ZOPC);
7228   ins_encode(z_form_rt_memFP(dst, src));
7229   ins_pipe(pipe_class_dummy);
7230 %}
7231 
7232 //  Mul float double precision
7233 instruct mulD_reg_reg(regD dst, regD src) %{
7234   match(Set dst (MulD dst src));
7235   // CC unchanged by MUL.
7236   ins_cost(ALU_REG_COST);
7237   size(4);
7238   format %{ "MDBR     $dst,$src" %}
7239   opcode(MDBR_ZOPC);
7240   ins_encode(z_rreform(dst, src));
7241   ins_pipe(pipe_class_dummy);
7242 %}
7243 
7244 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7245   match(Set dst (MulD dst (LoadD src)));
7246   // CC unchanged by MUL.
7247   ins_cost(ALU_MEMORY_COST);
7248   size(6);
7249   format %{ "MDB      $dst,$src\t # doubleMemory" %}
7250   opcode(MDB_ZOPC);
7251   ins_encode(z_form_rt_memFP(dst, src));
7252   ins_pipe(pipe_class_dummy);
7253 %}
7254 
7255 // Multiply-Accumulate
7256 // src1 * src2 + dst
7257 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7258   match(Set dst (FmaF dst (Binary src1 src2)));
7259   // CC unchanged by MUL-ADD.
7260   ins_cost(ALU_REG_COST);
7261   size(4);
7262   format %{ "MAEBR    $dst, $src1, $src2" %}
7263   ins_encode %{
7264     __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7265   %}
7266   ins_pipe(pipe_class_dummy);
7267 %}
7268 
7269 // src1 * src2 + dst
7270 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7271   match(Set dst (FmaD dst (Binary src1 src2)));
7272   // CC unchanged by MUL-ADD.
7273   ins_cost(ALU_REG_COST);
7274   size(4);
7275   format %{ "MADBR    $dst, $src1, $src2" %}
7276   ins_encode %{
7277     __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7278   %}
7279   ins_pipe(pipe_class_dummy);
7280 %}
7281 
7282 // src1 * src2 - dst
7283 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7284   match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7285   // CC unchanged by MUL-SUB.
7286   ins_cost(ALU_REG_COST);
7287   size(4);
7288   format %{ "MSEBR    $dst, $src1, $src2" %}
7289   ins_encode %{
7290     __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7291   %}
7292   ins_pipe(pipe_class_dummy);
7293 %}
7294 
7295 // src1 * src2 - dst
7296 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7297   match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7298   // CC unchanged by MUL-SUB.
7299   ins_cost(ALU_REG_COST);
7300   size(4);
7301   format %{ "MSDBR    $dst, $src1, $src2" %}
7302   ins_encode %{
7303     __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7304   %}
7305   ins_pipe(pipe_class_dummy);
7306 %}
7307 
7308 // src1 * src2 + dst
7309 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7310   match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7311   // CC unchanged by MUL-ADD.
7312   ins_cost(ALU_MEMORY_COST);
7313   size(6);
7314   format %{ "MAEB     $dst, $src1, $src2" %}
7315   ins_encode %{
7316     __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7317               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7318   %}
7319   ins_pipe(pipe_class_dummy);
7320 %}
7321 
7322 // src1 * src2 + dst
7323 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7324   match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7325   // CC unchanged by MUL-ADD.
7326   ins_cost(ALU_MEMORY_COST);
7327   size(6);
7328   format %{ "MADB     $dst, $src1, $src2" %}
7329   ins_encode %{
7330     __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7331               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7332   %}
7333   ins_pipe(pipe_class_dummy);
7334 %}
7335 
7336 // src1 * src2 - dst
7337 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7338   match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7339   // CC unchanged by MUL-SUB.
7340   ins_cost(ALU_MEMORY_COST);
7341   size(6);
7342   format %{ "MSEB     $dst, $src1, $src2" %}
7343   ins_encode %{
7344     __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7345               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7346   %}
7347   ins_pipe(pipe_class_dummy);
7348 %}
7349 
7350 // src1 * src2 - dst
7351 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7352   match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7353   // CC unchanged by MUL-SUB.
7354   ins_cost(ALU_MEMORY_COST);
7355   size(6);
7356   format %{ "MSDB    $dst, $src1, $src2" %}
7357   ins_encode %{
7358     __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7359               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7360   %}
7361   ins_pipe(pipe_class_dummy);
7362 %}
7363 
7364 // src1 * src2 + dst
7365 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7366   match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7367   // CC unchanged by MUL-ADD.
7368   ins_cost(ALU_MEMORY_COST);
7369   size(6);
7370   format %{ "MAEB     $dst, $src1, $src2" %}
7371   ins_encode %{
7372     __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7373               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7374   %}
7375   ins_pipe(pipe_class_dummy);
7376 %}
7377 
7378 // src1 * src2 + dst
7379 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7380   match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7381   // CC unchanged by MUL-ADD.
7382   ins_cost(ALU_MEMORY_COST);
7383   size(6);
7384   format %{ "MADB     $dst, $src1, $src2" %}
7385   ins_encode %{
7386     __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7387               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7388   %}
7389   ins_pipe(pipe_class_dummy);
7390 %}
7391 
7392 // src1 * src2 - dst
7393 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7394   match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7395   // CC unchanged by MUL-SUB.
7396   ins_cost(ALU_MEMORY_COST);
7397   size(6);
7398   format %{ "MSEB     $dst, $src1, $src2" %}
7399   ins_encode %{
7400     __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7401               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7402   %}
7403   ins_pipe(pipe_class_dummy);
7404 %}
7405 
7406 // src1 * src2 - dst
7407 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7408   match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7409   // CC unchanged by MUL-SUB.
7410   ins_cost(ALU_MEMORY_COST);
7411   size(6);
7412   format %{ "MSDB    $dst, $src1, $src2" %}
7413   ins_encode %{
7414     __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7415               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7416   %}
7417   ins_pipe(pipe_class_dummy);
7418 %}
7419 
7420 //  DIV
7421 
7422 //  Div float single precision
7423 instruct divF_reg_reg(regF dst, regF src) %{
7424   match(Set dst (DivF dst src));
7425   // CC unchanged by DIV.
7426   ins_cost(ALU_REG_COST);
7427   size(4);
7428   format %{ "DEBR     $dst,$src" %}
7429   opcode(DEBR_ZOPC);
7430   ins_encode(z_rreform(dst, src));
7431   ins_pipe(pipe_class_dummy);
7432 %}
7433 
7434 instruct divF_reg_mem(regF dst, memoryRX src)%{
7435   match(Set dst (DivF dst (LoadF src)));
7436   // CC unchanged by DIV.
7437   ins_cost(ALU_MEMORY_COST);
7438   size(6);
7439   format %{ "DEB      $dst,$src\t # floatMemory" %}
7440   opcode(DEB_ZOPC);
7441   ins_encode(z_form_rt_memFP(dst, src));
7442   ins_pipe(pipe_class_dummy);
7443 %}
7444 
7445 //  Div float double precision
7446 instruct divD_reg_reg(regD dst, regD src) %{
7447   match(Set dst (DivD dst src));
7448   // CC unchanged by DIV.
7449   ins_cost(ALU_REG_COST);
7450   size(4);
7451   format %{ "DDBR     $dst,$src" %}
7452   opcode(DDBR_ZOPC);
7453   ins_encode(z_rreform(dst, src));
7454   ins_pipe(pipe_class_dummy);
7455 %}
7456 
7457 instruct divD_reg_mem(regD dst, memoryRX src)%{
7458   match(Set dst (DivD dst (LoadD src)));
7459   // CC unchanged by DIV.
7460   ins_cost(ALU_MEMORY_COST);
7461   size(6);
7462   format %{ "DDB      $dst,$src\t # doubleMemory" %}
7463   opcode(DDB_ZOPC);
7464   ins_encode(z_form_rt_memFP(dst, src));
7465   ins_pipe(pipe_class_dummy);
7466 %}
7467 
7468 // ABS
7469 
7470 // Absolute float single precision
7471 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7472   match(Set dst (AbsF src));
7473   effect(KILL cr);
7474   size(4);
7475   format %{ "LPEBR    $dst,$src\t float" %}
7476   opcode(LPEBR_ZOPC);
7477   ins_encode(z_rreform(dst, src));
7478   ins_pipe(pipe_class_dummy);
7479 %}
7480 
7481 // Absolute float double precision
7482 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7483   match(Set dst (AbsD src));
7484   effect(KILL cr);
7485   size(4);
7486   format %{ "LPDBR    $dst,$src\t double" %}
7487   opcode(LPDBR_ZOPC);
7488   ins_encode(z_rreform(dst, src));
7489   ins_pipe(pipe_class_dummy);
7490 %}
7491 
7492 //  NEG(ABS)
7493 
7494 // Negative absolute float single precision
7495 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7496   match(Set dst (NegF (AbsF src)));
7497   effect(KILL cr);
7498   size(4);
7499   format %{ "LNEBR    $dst,$src\t float" %}
7500   opcode(LNEBR_ZOPC);
7501   ins_encode(z_rreform(dst, src));
7502   ins_pipe(pipe_class_dummy);
7503 %}
7504 
7505 // Negative absolute float double precision
7506 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7507   match(Set dst (NegD (AbsD src)));
7508   effect(KILL cr);
7509   size(4);
7510   format %{ "LNDBR    $dst,$src\t double" %}
7511   opcode(LNDBR_ZOPC);
7512   ins_encode(z_rreform(dst, src));
7513   ins_pipe(pipe_class_dummy);
7514 %}
7515 
7516 // NEG
7517 
7518 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7519   match(Set dst (NegF src));
7520   effect(KILL cr);
7521   size(4);
7522   format %{ "NegF     $dst,$src\t float" %}
7523   ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7524   ins_pipe(pipe_class_dummy);
7525 %}
7526 
7527 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7528   match(Set dst (NegD src));
7529   effect(KILL cr);
7530   size(4);
7531   format %{ "NegD     $dst,$src\t double" %}
7532   ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7533   ins_pipe(pipe_class_dummy);
7534 %}
7535 
7536 // SQRT
7537 
7538 // Sqrt float precision
7539 instruct sqrtF_reg(regF dst, regF src) %{
7540   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7541   // CC remains unchanged.
7542   ins_cost(ALU_REG_COST);
7543   size(4);
7544   format %{ "SQEBR    $dst,$src" %}
7545   opcode(SQEBR_ZOPC);
7546   ins_encode(z_rreform(dst, src));
7547   ins_pipe(pipe_class_dummy);
7548 %}
7549 
7550 // Sqrt double precision
7551 instruct sqrtD_reg(regD dst, regD src) %{
7552   match(Set dst (SqrtD src));
7553   // CC remains unchanged.
7554   ins_cost(ALU_REG_COST);
7555   size(4);
7556   format %{ "SQDBR    $dst,$src" %}
7557   opcode(SQDBR_ZOPC);
7558   ins_encode(z_rreform(dst, src));
7559   ins_pipe(pipe_class_dummy);
7560 %}
7561 
7562 instruct sqrtF_mem(regF dst, memoryRX src) %{
7563   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7564   // CC remains unchanged.
7565   ins_cost(ALU_MEMORY_COST);
7566   size(6);
7567   format %{ "SQEB     $dst,$src\t # floatMemory" %}
7568   opcode(SQEB_ZOPC);
7569   ins_encode(z_form_rt_memFP(dst, src));
7570   ins_pipe(pipe_class_dummy);
7571 %}
7572 
7573 instruct sqrtD_mem(regD dst, memoryRX src) %{
7574   match(Set dst (SqrtD src));
7575   // CC remains unchanged.
7576   ins_cost(ALU_MEMORY_COST);
7577   // TODO: s390 port size(FIXED_SIZE);
7578   format %{ "SQDB     $dst,$src\t # doubleMemory" %}
7579   opcode(SQDB_ZOPC);
7580   ins_encode(z_form_rt_memFP(dst, src));
7581   ins_pipe(pipe_class_dummy);
7582 %}
7583 
7584 //----------Logical Instructions-----------------------------------------------
7585 
7586 // Register And
7587 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7588   match(Set dst (AndI dst src));
7589   effect(KILL cr);
7590   ins_cost(DEFAULT_COST_LOW);
7591   size(2);
7592   format %{ "NR      $dst,$src\t # int" %}
7593   opcode(NR_ZOPC);
7594   ins_encode(z_rrform(dst, src));
7595   ins_pipe(pipe_class_dummy);
7596 %}
7597 
7598 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7599   match(Set dst (AndI dst (LoadI src)));
7600   effect(KILL cr);
7601   ins_cost(MEMORY_REF_COST);
7602   // TODO: s390 port size(VARIABLE_SIZE);
7603   format %{ "N(Y)    $dst, $src\t # int" %}
7604   opcode(NY_ZOPC, N_ZOPC);
7605   ins_encode(z_form_rt_mem_opt(dst, src));
7606   ins_pipe(pipe_class_dummy);
7607 %}
7608 
7609 // Immediate And
7610 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7611   match(Set dst (AndI dst src));
7612   effect(KILL cr);
7613   ins_cost(DEFAULT_COST_HIGH);
7614   size(6);
7615   format %{ "NILF    $dst,$src" %}
7616   opcode(NILF_ZOPC);
7617   ins_encode(z_rilform_unsigned(dst, src));
7618   ins_pipe(pipe_class_dummy);
7619 %}
7620 
7621 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7622   match(Set dst (AndI dst src));
7623   effect(KILL cr);
7624   ins_cost(DEFAULT_COST);
7625   size(4);
7626   format %{ "NILH    $dst,$src" %}
7627   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7628   ins_pipe(pipe_class_dummy);
7629 %}
7630 
7631 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7632   match(Set dst (AndI dst src));
7633   effect(KILL cr);
7634   ins_cost(DEFAULT_COST);
7635   size(4);
7636   format %{ "NILL    $dst,$src" %}
7637   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7638   ins_pipe(pipe_class_dummy);
7639 %}
7640 
7641 // Register And Long
7642 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7643   match(Set dst (AndL dst src));
7644   effect(KILL cr);
7645   ins_cost(DEFAULT_COST);
7646   size(4);
7647   format %{ "NGR     $dst,$src\t # long" %}
7648   opcode(NGR_ZOPC);
7649   ins_encode(z_rreform(dst, src));
7650   ins_pipe(pipe_class_dummy);
7651 %}
7652 
7653 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7654   match(Set dst (AndL dst (LoadL src)));
7655   effect(KILL cr);
7656   ins_cost(MEMORY_REF_COST);
7657   size(Z_DISP3_SIZE);
7658   format %{ "NG      $dst, $src\t # long" %}
7659   opcode(NG_ZOPC, NG_ZOPC);
7660   ins_encode(z_form_rt_mem_opt(dst, src));
7661   ins_pipe(pipe_class_dummy);
7662 %}
7663 
7664 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7665   match(Set dst (AndL dst src));
7666   effect(KILL cr);
7667   ins_cost(DEFAULT_COST);
7668   size(4);
7669   format %{ "NILL    $dst,$src\t # long" %}
7670   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7671   ins_pipe(pipe_class_dummy);
7672 %}
7673 
7674 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7675   match(Set dst (AndL dst src));
7676   effect(KILL cr);
7677   ins_cost(DEFAULT_COST);
7678   size(4);
7679   format %{ "NILH    $dst,$src\t # long" %}
7680   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7681   ins_pipe(pipe_class_dummy);
7682 %}
7683 
7684 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7685   match(Set dst (AndL dst src));
7686   effect(KILL cr);
7687   ins_cost(DEFAULT_COST);
7688   size(4);
7689   format %{ "NIHL    $dst,$src\t # long" %}
7690   ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7691   ins_pipe(pipe_class_dummy);
7692 %}
7693 
7694 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7695   match(Set dst (AndL dst src));
7696   effect(KILL cr);
7697   ins_cost(DEFAULT_COST);
7698   size(4);
7699   format %{ "NIHH    $dst,$src\t # long" %}
7700   ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7701   ins_pipe(pipe_class_dummy);
7702 %}
7703 
7704 //  OR
7705 
7706 // Or Instructions
7707 // Register Or
7708 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7709   match(Set dst (OrI dst src));
7710   effect(KILL cr);
7711   size(2);
7712   format %{ "OR      $dst,$src" %}
7713   opcode(OR_ZOPC);
7714   ins_encode(z_rrform(dst, src));
7715   ins_pipe(pipe_class_dummy);
7716 %}
7717 
7718 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7719   match(Set dst (OrI dst (LoadI src)));
7720   effect(KILL cr);
7721   ins_cost(MEMORY_REF_COST);
7722   // TODO: s390 port size(VARIABLE_SIZE);
7723   format %{ "O(Y)    $dst, $src\t # int" %}
7724   opcode(OY_ZOPC, O_ZOPC);
7725   ins_encode(z_form_rt_mem_opt(dst, src));
7726   ins_pipe(pipe_class_dummy);
7727 %}
7728 
7729 // Immediate Or
7730 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
7731   match(Set dst (OrI dst con));
7732   effect(KILL cr);
7733   size(4);
7734   format %{ "OILL    $dst,$con" %}
7735   opcode(OILL_ZOPC);
7736   ins_encode(z_riform_unsigned(dst,con));
7737   ins_pipe(pipe_class_dummy);
7738 %}
7739 
7740 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
7741   match(Set dst (OrI dst con));
7742   effect(KILL cr);
7743   ins_cost(DEFAULT_COST_HIGH);
7744   size(6);
7745   format %{ "OILF    $dst,$con" %}
7746   opcode(OILF_ZOPC);
7747   ins_encode(z_rilform_unsigned(dst,con));
7748   ins_pipe(pipe_class_dummy);
7749 %}
7750 
7751 // Register Or Long
7752 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7753   match(Set dst (OrL dst src));
7754   effect(KILL cr);
7755   ins_cost(DEFAULT_COST);
7756   size(4);
7757   format %{ "OGR      $dst,$src\t # long" %}
7758   opcode(OGR_ZOPC);
7759   ins_encode(z_rreform(dst, src));
7760   ins_pipe(pipe_class_dummy);
7761 %}
7762 
7763 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7764   match(Set dst (OrL dst (LoadL src)));
7765   effect(KILL cr);
7766   ins_cost(MEMORY_REF_COST);
7767   size(Z_DISP3_SIZE);
7768   format %{ "OG      $dst, $src\t # long" %}
7769   opcode(OG_ZOPC, OG_ZOPC);
7770   ins_encode(z_form_rt_mem_opt(dst, src));
7771   ins_pipe(pipe_class_dummy);
7772 %}
7773 
7774 // Immediate Or long
7775 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
7776   match(Set dst (OrL dst con));
7777   effect(KILL cr);
7778   ins_cost(DEFAULT_COST);
7779   size(4);
7780   format %{ "OILL    $dst,$con\t # long" %}
7781   opcode(OILL_ZOPC);
7782   ins_encode(z_riform_unsigned(dst,con));
7783   ins_pipe(pipe_class_dummy);
7784 %}
7785 
7786 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
7787   match(Set dst (OrI dst con));
7788   effect(KILL cr);
7789   ins_cost(DEFAULT_COST_HIGH);
7790   // TODO: s390 port size(FIXED_SIZE);
7791   format %{ "OILF    $dst,$con\t # long" %}
7792   opcode(OILF_ZOPC);
7793   ins_encode(z_rilform_unsigned(dst,con));
7794   ins_pipe(pipe_class_dummy);
7795 %}
7796 
7797 // XOR
7798 
7799 // Register Xor
7800 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7801   match(Set dst (XorI dst src));
7802   effect(KILL cr);
7803   size(2);
7804   format %{ "XR      $dst,$src" %}
7805   opcode(XR_ZOPC);
7806   ins_encode(z_rrform(dst, src));
7807   ins_pipe(pipe_class_dummy);
7808 %}
7809 
7810 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7811   match(Set dst (XorI dst (LoadI src)));
7812   effect(KILL cr);
7813   ins_cost(MEMORY_REF_COST);
7814   // TODO: s390 port size(VARIABLE_SIZE);
7815   format %{ "X(Y)    $dst, $src\t # int" %}
7816   opcode(XY_ZOPC, X_ZOPC);
7817   ins_encode(z_form_rt_mem_opt(dst, src));
7818   ins_pipe(pipe_class_dummy);
7819 %}
7820 
7821 // Immediate Xor
7822 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7823   match(Set dst (XorI dst src));
7824   effect(KILL cr);
7825   ins_cost(DEFAULT_COST_HIGH);
7826   size(6);
7827   format %{ "XILF    $dst,$src" %}
7828   opcode(XILF_ZOPC);
7829   ins_encode(z_rilform_unsigned(dst, src));
7830   ins_pipe(pipe_class_dummy);
7831 %}
7832 
7833 // Register Xor Long
7834 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7835   match(Set dst (XorL dst src));
7836   effect(KILL cr);
7837   ins_cost(DEFAULT_COST);
7838   size(4);
7839   format %{ "XGR     $dst,$src\t # long" %}
7840   opcode(XGR_ZOPC);
7841   ins_encode(z_rreform(dst, src));
7842   ins_pipe(pipe_class_dummy);
7843 %}
7844 
7845 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7846   match(Set dst (XorL dst (LoadL src)));
7847   effect(KILL cr);
7848   ins_cost(MEMORY_REF_COST);
7849   size(Z_DISP3_SIZE);
7850   format %{ "XG      $dst, $src\t # long" %}
7851   opcode(XG_ZOPC, XG_ZOPC);
7852   ins_encode(z_form_rt_mem_opt(dst, src));
7853   ins_pipe(pipe_class_dummy);
7854 %}
7855 
7856 // Immediate Xor Long
7857 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
7858   match(Set dst (XorL dst con));
7859   effect(KILL cr);
7860   ins_cost(DEFAULT_COST_HIGH);
7861   size(6);
7862   format %{ "XILF    $dst,$con\t # long" %}
7863   opcode(XILF_ZOPC);
7864   ins_encode(z_rilform_unsigned(dst,con));
7865   ins_pipe(pipe_class_dummy);
7866 %}
7867 
7868 //----------Convert to Boolean-------------------------------------------------
7869 
7870 // Convert integer to boolean.
7871 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
7872   match(Set dst (Conv2B src));
7873   effect(KILL cr);
7874   ins_cost(3 * DEFAULT_COST);
7875   size(6);
7876   format %{ "convI2B $dst,$src" %}
7877   ins_encode %{
7878     __ z_lnr($dst$$Register, $src$$Register);  // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
7879     __ z_srl($dst$$Register, 31);              // Rdst := sign(Rdest)
7880   %}
7881   ins_pipe(pipe_class_dummy);
7882 %}
7883 
7884 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
7885   match(Set dst (Conv2B src));
7886   effect(KILL cr);
7887   ins_cost(3 * DEFAULT_COST);
7888   size(10);
7889   format %{ "convP2B $dst,$src" %}
7890   ins_encode %{
7891     __ z_lngr($dst$$Register, $src$$Register);     // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
7892     __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
7893   %}
7894   ins_pipe(pipe_class_dummy);
7895 %}
7896 
7897 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7898   match(Set dst (CmpLTMask dst src));
7899   effect(KILL cr);
7900   ins_cost(2 * DEFAULT_COST);
7901   size(18);
7902   format %{ "Set $dst CmpLTMask $dst,$src" %}
7903   ins_encode %{
7904     // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
7905     __ z_lgfr(Z_R0_scratch, $src$$Register);
7906     __ z_lgfr($dst$$Register, $dst$$Register);
7907     __ z_sgr($dst$$Register, Z_R0_scratch);
7908     __ z_srag($dst$$Register, $dst$$Register, 63);
7909   %}
7910   ins_pipe(pipe_class_dummy);
7911 %}
7912 
7913 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
7914   match(Set dst (CmpLTMask dst zero));
7915   effect(KILL cr);
7916   ins_cost(DEFAULT_COST);
7917   size(4);
7918   format %{ "Set $dst CmpLTMask $dst,$zero" %}
7919   ins_encode %{ __ z_sra($dst$$Register, 31); %}
7920   ins_pipe(pipe_class_dummy);
7921 %}
7922 
7923 
7924 //----------Arithmetic Conversion Instructions---------------------------------
7925 // The conversions operations are all Alpha sorted. Please keep it that way!
7926 
7927 instruct convD2F_reg(regF dst, regD src) %{
7928   match(Set dst (ConvD2F src));
7929   // CC remains unchanged.
7930   size(4);
7931   format %{ "LEDBR   $dst,$src" %}
7932   opcode(LEDBR_ZOPC);
7933   ins_encode(z_rreform(dst, src));
7934   ins_pipe(pipe_class_dummy);
7935 %}
7936 
7937 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
7938   match(Set dst (ConvF2I src));
7939   effect(KILL cr);
7940   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7941   size(16);
7942   format %{ "convF2I  $dst,$src" %}
7943   ins_encode %{
7944     Label done;
7945     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
7946     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
7947     __ z_brno(done);                             // Result is zero if unordered argument.
7948     __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7949     __ bind(done);
7950   %}
7951   ins_pipe(pipe_class_dummy);
7952 %}
7953 
7954 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
7955   match(Set dst (ConvD2I src));
7956   effect(KILL cr);
7957   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7958   size(16);
7959   format %{ "convD2I  $dst,$src" %}
7960   ins_encode %{
7961     Label done;
7962     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
7963     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
7964     __ z_brno(done);                             // Result is zero if unordered argument.
7965     __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7966     __ bind(done);
7967   %}
7968   ins_pipe(pipe_class_dummy);
7969 %}
7970 
7971 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
7972   match(Set dst (ConvF2L src));
7973   effect(KILL cr);
7974   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7975   size(16);
7976   format %{ "convF2L  $dst,$src" %}
7977   ins_encode %{
7978     Label done;
7979     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
7980     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
7981     __ z_brno(done);                             // Result is zero if unordered argument.
7982     __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7983     __ bind(done);
7984   %}
7985   ins_pipe(pipe_class_dummy);
7986 %}
7987 
7988 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
7989   match(Set dst (ConvD2L src));
7990   effect(KILL cr);
7991   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7992   size(16);
7993   format %{ "convD2L  $dst,$src" %}
7994   ins_encode %{
7995     Label done;
7996     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
7997     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
7998     __ z_brno(done);                             // Result is zero if unordered argument.
7999     __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8000     __ bind(done);
8001   %}
8002   ins_pipe(pipe_class_dummy);
8003 %}
8004 
8005 instruct convF2D_reg(regD dst, regF src) %{
8006   match(Set dst (ConvF2D src));
8007   // CC remains unchanged.
8008   size(4);
8009   format %{ "LDEBR   $dst,$src" %}
8010   opcode(LDEBR_ZOPC);
8011   ins_encode(z_rreform(dst, src));
8012   ins_pipe(pipe_class_dummy);
8013 %}
8014 
8015 instruct convF2D_mem(regD dst, memoryRX src) %{
8016   match(Set dst (ConvF2D src));
8017   // CC remains unchanged.
8018   size(6);
8019   format %{ "LDEB    $dst,$src" %}
8020   opcode(LDEB_ZOPC);
8021   ins_encode(z_form_rt_memFP(dst, src));
8022   ins_pipe(pipe_class_dummy);
8023 %}
8024 
8025 instruct convI2D_reg(regD dst, iRegI src) %{
8026   match(Set dst (ConvI2D src));
8027   // CC remains unchanged.
8028   ins_cost(DEFAULT_COST);
8029   size(4);
8030   format %{ "CDFBR   $dst,$src" %}
8031   opcode(CDFBR_ZOPC);
8032   ins_encode(z_rreform(dst, src));
8033   ins_pipe(pipe_class_dummy);
8034 %}
8035 
8036 // Optimization that saves up to two memory operations for each conversion.
8037 instruct convI2F_ireg(regF dst, iRegI src) %{
8038   match(Set dst (ConvI2F src));
8039   // CC remains unchanged.
8040   ins_cost(DEFAULT_COST);
8041   size(4);
8042   format %{ "CEFBR   $dst,$src\t # convert int to float" %}
8043   opcode(CEFBR_ZOPC);
8044   ins_encode(z_rreform(dst, src));
8045   ins_pipe(pipe_class_dummy);
8046 %}
8047 
8048 instruct convI2L_reg(iRegL dst, iRegI src) %{
8049   match(Set dst (ConvI2L src));
8050   size(4);
8051   format %{ "LGFR    $dst,$src\t # int->long" %}
8052   opcode(LGFR_ZOPC);
8053   ins_encode(z_rreform(dst, src));
8054   ins_pipe(pipe_class_dummy);
8055 %}
8056 
8057 // Zero-extend convert int to long.
8058 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8059   match(Set dst (AndL (ConvI2L src) mask));
8060   size(4);
8061   format %{ "LLGFR   $dst, $src \t # zero-extend int to long" %}
8062   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8063   ins_pipe(pipe_class_dummy);
8064 %}
8065 
8066 // Zero-extend convert int to long.
8067 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8068   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8069   // Uses load_const_optmized, so size can vary.
8070   // TODO: s390 port size(VARIABLE_SIZE);
8071   format %{ "LLGF    $dst, $src \t # zero-extend int to long" %}
8072   opcode(LLGF_ZOPC, LLGF_ZOPC);
8073   ins_encode(z_form_rt_mem_opt(dst, src));
8074   ins_pipe(pipe_class_dummy);
8075 %}
8076 
8077 // Zero-extend long
8078 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8079   match(Set dst (AndL src mask));
8080   size(4);
8081   format %{ "LLGFR   $dst, $src \t # zero-extend long to long" %}
8082   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8083   ins_pipe(pipe_class_dummy);
8084 %}
8085 
8086 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8087   match(Set dst (RShiftI (LShiftI src amount) amount));
8088   size(4);
8089   format %{ "LHR     $dst,$src\t short->int" %}
8090   opcode(LHR_ZOPC);
8091   ins_encode(z_rreform(dst, src));
8092   ins_pipe(pipe_class_dummy);
8093 %}
8094 
8095 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8096   match(Set dst (RShiftI (LShiftI src amount) amount));
8097   size(4);
8098   format %{ "LBR     $dst,$src\t byte->int" %}
8099   opcode(LBR_ZOPC);
8100   ins_encode(z_rreform(dst, src));
8101   ins_pipe(pipe_class_dummy);
8102 %}
8103 
8104 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8105   match(Set dst (MoveF2I src));
8106   ins_cost(MEMORY_REF_COST);
8107   size(4);
8108   format %{ "L       $dst,$src\t # MoveF2I" %}
8109   opcode(L_ZOPC);
8110   ins_encode(z_form_rt_mem(dst, src));
8111   ins_pipe(pipe_class_dummy);
8112 %}
8113 
8114 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8115 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8116   match(Set dst (MoveI2F src));
8117   ins_cost(MEMORY_REF_COST);
8118   // TODO: s390 port size(FIXED_SIZE);
8119   format %{ "LE      $dst,$src\t # MoveI2F" %}
8120   opcode(LE_ZOPC);
8121   ins_encode(z_form_rt_mem(dst, src));
8122   ins_pipe(pipe_class_dummy);
8123 %}
8124 
8125 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8126   match(Set dst (MoveD2L src));
8127   ins_cost(MEMORY_REF_COST);
8128   size(6);
8129   format %{ "LG      $src,$dst\t # MoveD2L" %}
8130   opcode(LG_ZOPC);
8131   ins_encode(z_form_rt_mem(dst, src));
8132   ins_pipe(pipe_class_dummy);
8133 %}
8134 
8135 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8136   match(Set dst (MoveL2D src));
8137   ins_cost(MEMORY_REF_COST);
8138   size(4);
8139   format %{ "LD      $dst,$src\t # MoveL2D" %}
8140   opcode(LD_ZOPC);
8141   ins_encode(z_form_rt_mem(dst, src));
8142   ins_pipe(pipe_class_dummy);
8143 %}
8144 
8145 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8146   match(Set dst (MoveI2F src));
8147   ins_cost(MEMORY_REF_COST);
8148   size(4);
8149   format %{ "ST      $src,$dst\t # MoveI2F" %}
8150   opcode(ST_ZOPC);
8151   ins_encode(z_form_rt_mem(src, dst));
8152   ins_pipe(pipe_class_dummy);
8153 %}
8154 
8155 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8156   match(Set dst (MoveD2L src));
8157   effect(DEF dst, USE src);
8158   ins_cost(MEMORY_REF_COST);
8159   size(4);
8160   format %{ "STD     $src,$dst\t # MoveD2L" %}
8161   opcode(STD_ZOPC);
8162   ins_encode(z_form_rt_mem(src,dst));
8163   ins_pipe(pipe_class_dummy);
8164 %}
8165 
8166 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8167   match(Set dst (MoveL2D src));
8168   ins_cost(MEMORY_REF_COST);
8169   size(6);
8170   format %{ "STG     $src,$dst\t # MoveL2D" %}
8171   opcode(STG_ZOPC);
8172   ins_encode(z_form_rt_mem(src,dst));
8173   ins_pipe(pipe_class_dummy);
8174 %}
8175 
8176 instruct convL2F_reg(regF dst, iRegL src) %{
8177   match(Set dst (ConvL2F src));
8178   // CC remains unchanged.
8179   ins_cost(DEFAULT_COST);
8180   size(4);
8181   format %{ "CEGBR   $dst,$src" %}
8182   opcode(CEGBR_ZOPC);
8183   ins_encode(z_rreform(dst, src));
8184   ins_pipe(pipe_class_dummy);
8185 %}
8186 
8187 instruct convL2D_reg(regD dst, iRegL src) %{
8188   match(Set dst (ConvL2D src));
8189   // CC remains unchanged.
8190   ins_cost(DEFAULT_COST);
8191   size(4);
8192   format %{ "CDGBR   $dst,$src" %}
8193   opcode(CDGBR_ZOPC);
8194   ins_encode(z_rreform(dst, src));
8195   ins_pipe(pipe_class_dummy);
8196 %}
8197 
8198 instruct convL2I_reg(iRegI dst, iRegL src) %{
8199   match(Set dst (ConvL2I src));
8200   // TODO: s390 port size(VARIABLE_SIZE);
8201   format %{ "LR      $dst,$src\t # long->int (if needed)" %}
8202   ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8203   ins_pipe(pipe_class_dummy);
8204 %}
8205 
8206 // Register Shift Right Immediate
8207 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8208   match(Set dst (ConvL2I (RShiftL src cnt)));
8209   effect(KILL cr);
8210   size(6);
8211   format %{ "SRAG    $dst,$src,$cnt" %}
8212   opcode(SRAG_ZOPC);
8213   ins_encode(z_rsyform_const(dst, src, cnt));
8214   ins_pipe(pipe_class_dummy);
8215 %}
8216 
8217 //----------TRAP based zero checks and range checks----------------------------
8218 
8219 // SIGTRAP based implicit range checks in compiled code.
8220 // A range check in the ideal world has one of the following shapes:
8221 //   - (If le (CmpU length index)), (IfTrue  throw exception)
8222 //   - (If lt (CmpU index length)), (IfFalse throw exception)
8223 //
8224 // Match range check 'If le (CmpU length index)'
8225 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8226   match(If cmp (CmpU length index));
8227   effect(USE labl);
8228   predicate(TrapBasedRangeChecks &&
8229             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8230             PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8231             Matcher::branches_to_uncommon_trap(_leaf));
8232   ins_cost(1);
8233   // TODO: s390 port size(FIXED_SIZE);
8234 
8235   ins_is_TrapBasedCheckNode(true);
8236 
8237   format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8238   ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8239   ins_pipe(pipe_class_trap);
8240 %}
8241 
8242 // Match range check 'If lt (CmpU index length)'
8243 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8244   match(If cmp (CmpU index length));
8245   effect(USE labl, KILL cr);
8246   predicate(TrapBasedRangeChecks &&
8247             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8248             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8249             Matcher::branches_to_uncommon_trap(_leaf));
8250   ins_cost(1);
8251   // TODO: s390 port size(FIXED_SIZE);
8252 
8253   ins_is_TrapBasedCheckNode(true);
8254 
8255   format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8256   ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8257   ins_pipe(pipe_class_trap);
8258 %}
8259 
8260 // Match range check 'If lt (CmpU index length)'
8261 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8262   match(If cmp (CmpU index length));
8263   effect(USE labl);
8264   predicate(TrapBasedRangeChecks &&
8265             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8266             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8267             Matcher::branches_to_uncommon_trap(_leaf));
8268   ins_cost(1);
8269   // TODO: s390 port size(FIXED_SIZE);
8270 
8271   ins_is_TrapBasedCheckNode(true);
8272 
8273   format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8274   ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8275   ins_pipe(pipe_class_trap);
8276 %}
8277 
8278 // Implicit zero checks (more implicit null checks).
8279 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8280   match(If cmp (CmpP value zero));
8281   effect(USE labl);
8282   predicate(TrapBasedNullChecks &&
8283             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8284             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8285             Matcher::branches_to_uncommon_trap(_leaf));
8286   size(6);
8287 
8288   ins_is_TrapBasedCheckNode(true);
8289 
8290   format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8291   ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8292   ins_pipe(pipe_class_trap);
8293 %}
8294 
8295 // Implicit zero checks (more implicit null checks).
8296 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8297   match(If cmp (CmpN value zero));
8298   effect(USE labl);
8299   predicate(TrapBasedNullChecks &&
8300             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8301             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8302             Matcher::branches_to_uncommon_trap(_leaf));
8303   size(6);
8304 
8305   ins_is_TrapBasedCheckNode(true);
8306 
8307   format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8308   ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8309   ins_pipe(pipe_class_trap);
8310 %}
8311 
8312 //----------Compare instructions-----------------------------------------------
8313 
8314 // INT signed
8315 
8316 // Compare Integers
8317 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8318   match(Set cr (CmpI op1 op2));
8319   size(2);
8320   format %{ "CR      $op1,$op2" %}
8321   opcode(CR_ZOPC);
8322   ins_encode(z_rrform(op1, op2));
8323   ins_pipe(pipe_class_dummy);
8324 %}
8325 
8326 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8327   match(Set cr (CmpI op1 op2));
8328   size(6);
8329   format %{ "CFI     $op1,$op2" %}
8330   opcode(CFI_ZOPC);
8331   ins_encode(z_rilform_signed(op1, op2));
8332   ins_pipe(pipe_class_dummy);
8333 %}
8334 
8335 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8336   match(Set cr (CmpI op1 op2));
8337   size(4);
8338   format %{ "CHI     $op1,$op2" %}
8339   opcode(CHI_ZOPC);
8340   ins_encode(z_riform_signed(op1, op2));
8341   ins_pipe(pipe_class_dummy);
8342 %}
8343 
8344 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8345   match(Set cr (CmpI op1 zero));
8346   ins_cost(DEFAULT_COST_LOW);
8347   size(2);
8348   format %{ "LTR     $op1,$op1" %}
8349   opcode(LTR_ZOPC);
8350   ins_encode(z_rrform(op1, op1));
8351   ins_pipe(pipe_class_dummy);
8352 %}
8353 
8354 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8355   match(Set cr (CmpI op1 (LoadI op2)));
8356   ins_cost(MEMORY_REF_COST);
8357   // TODO: s390 port size(VARIABLE_SIZE);
8358   format %{ "C(Y)    $op1, $op2\t # int" %}
8359   opcode(CY_ZOPC, C_ZOPC);
8360   ins_encode(z_form_rt_mem_opt(op1, op2));
8361   ins_pipe(pipe_class_dummy);
8362 %}
8363 
8364 // INT unsigned
8365 
8366 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8367   match(Set cr (CmpU op1 op2));
8368   size(2);
8369   format %{ "CLR     $op1,$op2\t # unsigned" %}
8370   opcode(CLR_ZOPC);
8371   ins_encode(z_rrform(op1, op2));
8372   ins_pipe(pipe_class_dummy);
8373 %}
8374 
8375 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8376   match(Set cr (CmpU op1 op2));
8377   size(6);
8378   format %{ "CLFI    $op1,$op2\t # unsigned" %}
8379   opcode(CLFI_ZOPC);
8380   ins_encode(z_rilform_unsigned(op1, op2));
8381   ins_pipe(pipe_class_dummy);
8382 %}
8383 
8384 instruct compU_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8385   match(Set cr (CmpU op1 zero));
8386   ins_cost(DEFAULT_COST_LOW);
8387   size(2);
8388   format %{ "LTR     $op1,$op1\t # unsigned" %}
8389   opcode(LTR_ZOPC);
8390   ins_encode(z_rrform(op1, op1));
8391   ins_pipe(pipe_class_dummy);
8392 %}
8393 
8394 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8395   match(Set cr (CmpU op1 (LoadI op2)));
8396   ins_cost(MEMORY_REF_COST);
8397   // TODO: s390 port size(VARIABLE_SIZE);
8398   format %{ "CL(Y)   $op1, $op2\t # unsigned" %}
8399   opcode(CLY_ZOPC, CL_ZOPC);
8400   ins_encode(z_form_rt_mem_opt(op1, op2));
8401   ins_pipe(pipe_class_dummy);
8402 %}
8403 
8404 // LONG signed
8405 
8406 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8407   match(Set cr (CmpL op1 op2));
8408   size(4);
8409   format %{ "CGR     $op1,$op2\t # long" %}
8410   opcode(CGR_ZOPC);
8411   ins_encode(z_rreform(op1, op2));
8412   ins_pipe(pipe_class_dummy);
8413 %}
8414 
8415 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8416   match(Set cr (CmpL op1 (ConvI2L op2)));
8417   size(4);
8418   format %{ "CGFR    $op1,$op2\t # long/int" %}
8419   opcode(CGFR_ZOPC);
8420   ins_encode(z_rreform(op1, op2));
8421   ins_pipe(pipe_class_dummy);
8422 %}
8423 
8424 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8425   match(Set cr (CmpL op1 con));
8426   size(6);
8427   format %{ "CGFI    $op1,$con" %}
8428   opcode(CGFI_ZOPC);
8429   ins_encode(z_rilform_signed(op1, con));
8430   ins_pipe(pipe_class_dummy);
8431 %}
8432 
8433 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8434   match(Set cr (CmpL op1 con));
8435   size(4);
8436   format %{ "CGHI    $op1,$con" %}
8437   opcode(CGHI_ZOPC);
8438   ins_encode(z_riform_signed(op1, con));
8439   ins_pipe(pipe_class_dummy);
8440 %}
8441 
8442 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8443   match(Set cr (CmpL op1 con));
8444   ins_cost(DEFAULT_COST_LOW);
8445   size(4);
8446   format %{ "LTGR    $op1,$op1" %}
8447   opcode(LTGR_ZOPC);
8448   ins_encode(z_rreform(op1, op1));
8449   ins_pipe(pipe_class_dummy);
8450 %}
8451 
8452 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8453   match(Set cr (CmpL (ConvI2L op1) con));
8454   ins_cost(DEFAULT_COST_LOW);
8455   size(4);
8456   format %{ "LTGFR    $op1,$op1" %}
8457   opcode(LTGFR_ZOPC);
8458   ins_encode(z_rreform(op1, op1));
8459   ins_pipe(pipe_class_dummy);
8460 %}
8461 
8462 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8463   match(Set cr (CmpL dst (LoadL src)));
8464   ins_cost(MEMORY_REF_COST);
8465   size(Z_DISP3_SIZE);
8466   format %{ "CG      $dst, $src\t # long" %}
8467   opcode(CG_ZOPC, CG_ZOPC);
8468   ins_encode(z_form_rt_mem_opt(dst, src));
8469   ins_pipe(pipe_class_dummy);
8470 %}
8471 
8472 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8473   match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8474   ins_cost(MEMORY_REF_COST);
8475   size(Z_DISP3_SIZE);
8476   format %{ "CGF     $dst, $src\t # long/int" %}
8477   opcode(CGF_ZOPC, CGF_ZOPC);
8478   ins_encode(z_form_rt_mem_opt(dst, src));
8479   ins_pipe(pipe_class_dummy);
8480 %}
8481 
8482 //  LONG unsigned
8483 
8484 //  PTR unsigned
8485 
8486 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8487   match(Set cr (CmpP op1 op2));
8488   size(4);
8489   format %{ "CLGR    $op1,$op2\t # ptr" %}
8490   opcode(CLGR_ZOPC);
8491   ins_encode(z_rreform(op1, op2));
8492   ins_pipe(pipe_class_dummy);
8493 %}
8494 
8495 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8496   match(Set cr (CmpP op1 op2));
8497   ins_cost(DEFAULT_COST_LOW);
8498   size(4);
8499   format %{ "LTGR    $op1, $op1\t # ptr" %}
8500   opcode(LTGR_ZOPC);
8501   ins_encode(z_rreform(op1, op1));
8502   ins_pipe(pipe_class_dummy);
8503 %}
8504 
8505 // Don't use LTGFR which performs sign extend.
8506 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8507   match(Set cr (CmpP (DecodeN op1) op2));
8508   predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
8509   ins_cost(DEFAULT_COST_LOW);
8510   size(2);
8511   format %{ "LTR    $op1, $op1\t # ptr" %}
8512   opcode(LTR_ZOPC);
8513   ins_encode(z_rrform(op1, op1));
8514   ins_pipe(pipe_class_dummy);
8515 %}
8516 
8517 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8518   match(Set cr (CmpP dst (LoadP src)));
8519   ins_cost(MEMORY_REF_COST);
8520   size(Z_DISP3_SIZE);
8521   format %{ "CLG     $dst, $src\t # ptr" %}
8522   opcode(CLG_ZOPC, CLG_ZOPC);
8523   ins_encode(z_form_rt_mem_opt(dst, src));
8524   ins_pipe(pipe_class_dummy);
8525 %}
8526 
8527 //----------Max and Min--------------------------------------------------------
8528 
8529 // Max Register with Register
8530 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8531   match(Set dst (MinI src1 src2));
8532   effect(KILL cr);
8533   predicate(VM_Version::has_LoadStoreConditional());
8534   ins_cost(3 * DEFAULT_COST);
8535   // TODO: s390 port size(VARIABLE_SIZE);
8536   format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8537   ins_encode %{
8538     Register Rdst = $dst$$Register;
8539     Register Rsrc1 = $src1$$Register;
8540     Register Rsrc2 = $src2$$Register;
8541 
8542     if (Rsrc1 == Rsrc2) {
8543       if (Rdst != Rsrc1) {
8544         __ z_lgfr(Rdst, Rsrc1);
8545       }
8546     } else if (Rdst == Rsrc1) {   // Rdst preset with src1.
8547       __ z_cr(Rsrc1, Rsrc2);      // Move src2 only if src1 is NotLow.
8548       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8549     } else if (Rdst == Rsrc2) {   // Rdst preset with src2.
8550       __ z_cr(Rsrc2, Rsrc1);      // Move src1 only if src2 is NotLow.
8551       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8552     } else {
8553       // Rdst is disjoint from operands, move in either case.
8554       __ z_cr(Rsrc1, Rsrc2);
8555       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8556       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8557     }
8558   %}
8559   ins_pipe(pipe_class_dummy);
8560 %}
8561 
8562 // Min Register with Register.
8563 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8564   match(Set dst (MinI src1 src2));
8565   effect(KILL cr);
8566   predicate(VM_Version::has_CompareBranch());
8567   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8568   // TODO: s390 port size(VARIABLE_SIZE);
8569   format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8570   ins_encode %{
8571     Register Rdst = $dst$$Register;
8572     Register Rsrc1 = $src1$$Register;
8573     Register Rsrc2 = $src2$$Register;
8574     Label done;
8575 
8576     if (Rsrc1 == Rsrc2) {
8577       if (Rdst != Rsrc1) {
8578         __ z_lgfr(Rdst, Rsrc1);
8579       }
8580     } else if (Rdst == Rsrc1) {
8581       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8582       __ z_lgfr(Rdst, Rsrc2);
8583     } else if (Rdst == Rsrc2) {
8584       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8585       __ z_lgfr(Rdst, Rsrc1);
8586     } else {
8587       __ z_lgfr(Rdst, Rsrc1);
8588       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8589       __ z_lgfr(Rdst, Rsrc2);
8590     }
8591     __ bind(done);
8592   %}
8593   ins_pipe(pipe_class_dummy);
8594 %}
8595 
8596 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8597   match(Set dst (MinI src1 src2));
8598   effect(KILL cr);
8599   predicate(!VM_Version::has_CompareBranch());
8600   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8601   // TODO: s390 port size(VARIABLE_SIZE);
8602   format %{ "MinI $dst $src1,$src2\t MinI" %}
8603   ins_encode %{
8604     Register Rdst = $dst$$Register;
8605     Register Rsrc1 = $src1$$Register;
8606     Register Rsrc2 = $src2$$Register;
8607     Label done;
8608 
8609     if (Rsrc1 == Rsrc2) {
8610       if (Rdst != Rsrc1) {
8611         __ z_lgfr(Rdst, Rsrc1);
8612       }
8613     } else if (Rdst == Rsrc1) {
8614       __ z_cr(Rsrc1, Rsrc2);
8615       __ z_brl(done);
8616       __ z_lgfr(Rdst, Rsrc2);
8617     } else if (Rdst == Rsrc2) {
8618       __ z_cr(Rsrc2, Rsrc1);
8619       __ z_brl(done);
8620       __ z_lgfr(Rdst, Rsrc1);
8621     } else {
8622       __ z_lgfr(Rdst, Rsrc1);
8623       __ z_cr(Rsrc1, Rsrc2);
8624       __ z_brl(done);
8625       __ z_lgfr(Rdst, Rsrc2);
8626     }
8627     __ bind(done);
8628   %}
8629   ins_pipe(pipe_class_dummy);
8630 %}
8631 
8632 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8633   match(Set dst (MinI src1 src2));
8634   effect(KILL cr);
8635   predicate(VM_Version::has_LoadStoreConditional());
8636   ins_cost(3 * DEFAULT_COST);
8637   // TODO: s390 port size(VARIABLE_SIZE);
8638   format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8639   ins_encode %{
8640     Register Rdst = $dst$$Register;
8641     Register Rsrc1 = $src1$$Register;
8642     int      Isrc2 = $src2$$constant;
8643 
8644     if (Rdst == Rsrc1) {
8645       __ load_const_optimized(Z_R0_scratch, Isrc2);
8646       __ z_cfi(Rsrc1, Isrc2);
8647       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8648     } else {
8649       __ load_const_optimized(Rdst, Isrc2);
8650       __ z_cfi(Rsrc1, Isrc2);
8651       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8652     }
8653   %}
8654   ins_pipe(pipe_class_dummy);
8655 %}
8656 
8657 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8658   match(Set dst (MinI src1 src2));
8659   effect(KILL cr);
8660   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8661   // TODO: s390 port size(VARIABLE_SIZE);
8662   format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8663   ins_encode %{
8664     Label done;
8665     if ($dst$$Register != $src1$$Register) {
8666       __ z_lgfr($dst$$Register, $src1$$Register);
8667     }
8668     __ z_cfi($src1$$Register, $src2$$constant);
8669     __ z_brl(done);
8670     __ z_lgfi($dst$$Register, $src2$$constant);
8671     __ bind(done);
8672   %}
8673   ins_pipe(pipe_class_dummy);
8674 %}
8675 
8676 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8677   match(Set dst (MinI src1 src2));
8678   effect(KILL cr);
8679   predicate(VM_Version::has_LoadStoreConditional());
8680   ins_cost(3 * DEFAULT_COST);
8681   // TODO: s390 port size(VARIABLE_SIZE);
8682   format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8683   ins_encode %{
8684     Register Rdst = $dst$$Register;
8685     Register Rsrc1 = $src1$$Register;
8686     int      Isrc2 = $src2$$constant;
8687 
8688     if (Rdst == Rsrc1) {
8689       __ load_const_optimized(Z_R0_scratch, Isrc2);
8690       __ z_chi(Rsrc1, Isrc2);
8691       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8692     } else {
8693       __ load_const_optimized(Rdst, Isrc2);
8694       __ z_chi(Rsrc1, Isrc2);
8695       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8696     }
8697   %}
8698   ins_pipe(pipe_class_dummy);
8699 %}
8700 
8701 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8702   match(Set dst (MinI src1 src2));
8703   effect(KILL cr);
8704   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8705   // TODO: s390 port size(VARIABLE_SIZE);
8706   format %{ "MinI $dst $src1,$src2\t MinI const16" %}
8707   ins_encode %{
8708     Label done;
8709     if ($dst$$Register != $src1$$Register) {
8710       __ z_lgfr($dst$$Register, $src1$$Register);
8711     }
8712     __ z_chi($src1$$Register, $src2$$constant);
8713     __ z_brl(done);
8714     __ z_lghi($dst$$Register, $src2$$constant);
8715     __ bind(done);
8716   %}
8717   ins_pipe(pipe_class_dummy);
8718 %}
8719 
8720 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8721   match(Set dst (MinI src1 src2));
8722   effect(KILL cr);
8723   predicate(VM_Version::has_CompareBranch());
8724   ins_cost(DEFAULT_COST + BRANCH_COST);
8725   // TODO: s390 port size(VARIABLE_SIZE);
8726   format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
8727   ins_encode %{
8728     Label done;
8729     if ($dst$$Register != $src1$$Register) {
8730       __ z_lgfr($dst$$Register, $src1$$Register);
8731     }
8732     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
8733     __ z_lghi($dst$$Register, $src2$$constant);
8734     __ bind(done);
8735   %}
8736   ins_pipe(pipe_class_dummy);
8737 %}
8738 
8739 // Max Register with Register
8740 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8741   match(Set dst (MaxI src1 src2));
8742   effect(KILL cr);
8743   predicate(VM_Version::has_LoadStoreConditional());
8744   ins_cost(3 * DEFAULT_COST);
8745   // TODO: s390 port size(VARIABLE_SIZE);
8746   format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
8747   ins_encode %{
8748     Register Rdst = $dst$$Register;
8749     Register Rsrc1 = $src1$$Register;
8750     Register Rsrc2 = $src2$$Register;
8751 
8752     if (Rsrc1 == Rsrc2) {
8753       if (Rdst != Rsrc1) {
8754         __ z_lgfr(Rdst, Rsrc1);
8755       }
8756     } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8757       __ z_cr(Rsrc1, Rsrc2);    // Move src2 only if src1 is NotHigh.
8758       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8759     } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8760       __ z_cr(Rsrc2, Rsrc1);    // Move src1 only if src2 is NotHigh.
8761       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
8762     } else {                    // Rdst is disjoint from operands, move in either case.
8763       __ z_cr(Rsrc1, Rsrc2);
8764       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8765       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8766     }
8767   %}
8768   ins_pipe(pipe_class_dummy);
8769 %}
8770 
8771 // Max Register with Register
8772 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8773   match(Set dst (MaxI src1 src2));
8774   effect(KILL cr);
8775   predicate(VM_Version::has_CompareBranch());
8776   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8777   // TODO: s390 port size(VARIABLE_SIZE);
8778   format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
8779   ins_encode %{
8780     Register Rdst = $dst$$Register;
8781     Register Rsrc1 = $src1$$Register;
8782     Register Rsrc2 = $src2$$Register;
8783     Label done;
8784 
8785     if (Rsrc1 == Rsrc2) {
8786       if (Rdst != Rsrc1) {
8787         __ z_lgfr(Rdst, Rsrc1);
8788       }
8789     } else if (Rdst == Rsrc1) {
8790       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8791       __ z_lgfr(Rdst, Rsrc2);
8792     } else if (Rdst == Rsrc2) {
8793       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
8794       __ z_lgfr(Rdst, Rsrc1);
8795     } else {
8796       __ z_lgfr(Rdst, Rsrc1);
8797       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8798       __ z_lgfr(Rdst, Rsrc2);
8799     }
8800     __ bind(done);
8801   %}
8802   ins_pipe(pipe_class_dummy);
8803 %}
8804 
8805 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8806   match(Set dst (MaxI src1 src2));
8807   effect(KILL cr);
8808   predicate(!VM_Version::has_CompareBranch());
8809   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8810   // TODO: s390 port size(VARIABLE_SIZE);
8811   format %{ "MaxI $dst $src1,$src2\t MaxI" %}
8812   ins_encode %{
8813     Register Rdst = $dst$$Register;
8814     Register Rsrc1 = $src1$$Register;
8815     Register Rsrc2 = $src2$$Register;
8816     Label done;
8817 
8818     if (Rsrc1 == Rsrc2) {
8819       if (Rdst != Rsrc1) {
8820         __ z_lgfr(Rdst, Rsrc1);
8821       }
8822     } else if (Rdst == Rsrc1) {
8823       __ z_cr(Rsrc1, Rsrc2);
8824       __ z_brh(done);
8825       __ z_lgfr(Rdst, Rsrc2);
8826     } else if (Rdst == Rsrc2) {
8827       __ z_cr(Rsrc2, Rsrc1);
8828       __ z_brh(done);
8829       __ z_lgfr(Rdst, Rsrc1);
8830     } else {
8831       __ z_lgfr(Rdst, Rsrc1);
8832       __ z_cr(Rsrc1, Rsrc2);
8833       __ z_brh(done);
8834       __ z_lgfr(Rdst, Rsrc2);
8835     }
8836 
8837     __ bind(done);
8838   %}
8839 
8840   ins_pipe(pipe_class_dummy);
8841 %}
8842 
8843 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8844   match(Set dst (MaxI src1 src2));
8845   effect(KILL cr);
8846   predicate(VM_Version::has_LoadStoreConditional());
8847   ins_cost(3 * DEFAULT_COST);
8848   // TODO: s390 port size(VARIABLE_SIZE);
8849   format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
8850   ins_encode %{
8851     Register Rdst = $dst$$Register;
8852     Register Rsrc1 = $src1$$Register;
8853     int      Isrc2 = $src2$$constant;
8854 
8855     if (Rdst == Rsrc1) {
8856       __ load_const_optimized(Z_R0_scratch, Isrc2);
8857       __ z_cfi(Rsrc1, Isrc2);
8858       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8859     } else {
8860       __ load_const_optimized(Rdst, Isrc2);
8861       __ z_cfi(Rsrc1, Isrc2);
8862       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8863     }
8864   %}
8865   ins_pipe(pipe_class_dummy);
8866 %}
8867 
8868 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8869   match(Set dst (MaxI src1 src2));
8870   effect(KILL cr);
8871   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8872   // TODO: s390 port size(VARIABLE_SIZE);
8873   format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
8874   ins_encode %{
8875     Label done;
8876     if ($dst$$Register != $src1$$Register) {
8877       __ z_lgfr($dst$$Register, $src1$$Register);
8878     }
8879     __ z_cfi($src1$$Register, $src2$$constant);
8880     __ z_brh(done);
8881     __ z_lgfi($dst$$Register, $src2$$constant);
8882     __ bind(done);
8883   %}
8884   ins_pipe(pipe_class_dummy);
8885 %}
8886 
8887 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8888   match(Set dst (MaxI src1 src2));
8889   effect(KILL cr);
8890   predicate(VM_Version::has_LoadStoreConditional());
8891   ins_cost(3 * DEFAULT_COST);
8892   // TODO: s390 port size(VARIABLE_SIZE);
8893   format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
8894   ins_encode %{
8895     Register Rdst = $dst$$Register;
8896     Register Rsrc1 = $src1$$Register;
8897     int      Isrc2 = $src2$$constant;
8898     if (Rdst == Rsrc1) {
8899       __ load_const_optimized(Z_R0_scratch, Isrc2);
8900       __ z_chi(Rsrc1, Isrc2);
8901       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8902     } else {
8903       __ load_const_optimized(Rdst, Isrc2);
8904       __ z_chi(Rsrc1, Isrc2);
8905       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8906     }
8907   %}
8908   ins_pipe(pipe_class_dummy);
8909 %}
8910 
8911 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8912   match(Set dst (MaxI src1 src2));
8913   effect(KILL cr);
8914   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8915   // TODO: s390 port size(VARIABLE_SIZE);
8916   format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
8917   ins_encode %{
8918     Label done;
8919     if ($dst$$Register != $src1$$Register) {
8920       __ z_lgfr($dst$$Register, $src1$$Register);
8921     }
8922     __ z_chi($src1$$Register, $src2$$constant);
8923     __ z_brh(done);
8924     __ z_lghi($dst$$Register, $src2$$constant);
8925     __ bind(done);
8926   %}
8927   ins_pipe(pipe_class_dummy);
8928 %}
8929 
8930 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8931   match(Set dst (MaxI src1 src2));
8932   effect(KILL cr);
8933   predicate(VM_Version::has_CompareBranch());
8934   ins_cost(DEFAULT_COST + BRANCH_COST);
8935   // TODO: s390 port size(VARIABLE_SIZE);
8936   format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
8937   ins_encode %{
8938     Label done;
8939     if ($dst$$Register != $src1$$Register) {
8940       __ z_lgfr($dst$$Register, $src1$$Register);
8941     }
8942     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
8943     __ z_lghi($dst$$Register, $src2$$constant);
8944     __ bind(done);
8945   %}
8946   ins_pipe(pipe_class_dummy);
8947 %}
8948 
8949 //----------Abs---------------------------------------------------------------
8950 
8951 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
8952   match(Set dst (AbsI src));
8953   effect(KILL cr);
8954   ins_cost(DEFAULT_COST_LOW);
8955   // TODO: s390 port size(FIXED_SIZE);
8956   format %{ "LPR     $dst, $src" %}
8957   opcode(LPR_ZOPC);
8958   ins_encode(z_rrform(dst, src));
8959   ins_pipe(pipe_class_dummy);
8960 %}
8961 
8962 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
8963   match(Set dst (SubI zero (AbsI src)));
8964   effect(KILL cr);
8965   ins_cost(DEFAULT_COST_LOW);
8966   // TODO: s390 port size(FIXED_SIZE);
8967   format %{ "LNR     $dst, $src" %}
8968   opcode(LNR_ZOPC);
8969   ins_encode(z_rrform(dst, src));
8970   ins_pipe(pipe_class_dummy);
8971 %}
8972 
8973 //----------Float Compares----------------------------------------------------
8974 
8975 // Compare floating, generate condition code.
8976 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
8977   match(Set cr (CmpF src1 src2));
8978   ins_cost(ALU_REG_COST);
8979   size(4);
8980   format %{ "FCMPcc   $src1,$src2\t # float" %}
8981   ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
8982   ins_pipe(pipe_class_dummy);
8983 %}
8984 
8985 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
8986   match(Set cr (CmpD src1 src2));
8987   ins_cost(ALU_REG_COST);
8988   size(4);
8989   format %{ "FCMPcc   $src1,$src2 \t # double" %}
8990   ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
8991   ins_pipe(pipe_class_dummy);
8992 %}
8993 
8994 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
8995   match(Set cr (CmpF src1 (LoadF src2)));
8996   ins_cost(ALU_MEMORY_COST);
8997   size(6);
8998   format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
8999   opcode(CEB_ZOPC);
9000   ins_encode(z_form_rt_memFP(src1, src2));
9001   ins_pipe(pipe_class_dummy);
9002 %}
9003 
9004 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9005   match(Set cr (CmpD src1 (LoadD src2)));
9006   ins_cost(ALU_MEMORY_COST);
9007   size(6);
9008   format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9009   opcode(CDB_ZOPC);
9010   ins_encode(z_form_rt_memFP(src1, src2));
9011   ins_pipe(pipe_class_dummy);
9012 %}
9013 
9014 // Compare floating, generate condition code
9015 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9016   match(Set cr (CmpF src1 src2));
9017   ins_cost(DEFAULT_COST);
9018   size(4);
9019   format %{ "LTEBR    $src1,$src1\t # float" %}
9020   opcode(LTEBR_ZOPC);
9021   ins_encode(z_rreform(src1, src1));
9022   ins_pipe(pipe_class_dummy);
9023 %}
9024 
9025 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9026   match(Set cr (CmpD src1 src2));
9027   ins_cost(DEFAULT_COST);
9028   size(4);
9029   format %{ "LTDBR    $src1,$src1 \t # double" %}
9030   opcode(LTDBR_ZOPC);
9031   ins_encode(z_rreform(src1, src1));
9032   ins_pipe(pipe_class_dummy);
9033 %}
9034 
9035 // Compare floating, generate -1,0,1
9036 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9037   match(Set dst (CmpF3 src1 src2));
9038   effect(KILL cr);
9039   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9040   size(24);
9041   format %{ "CmpF3    $dst,$src1,$src2" %}
9042   ins_encode %{
9043     // compare registers
9044     __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9045     // Convert condition code into -1,0,1, where
9046     // -1 means unordered or less
9047     //  0 means equal
9048     //  1 means greater.
9049     if (VM_Version::has_LoadStoreConditional()) {
9050       Register one       = Z_R0_scratch;
9051       Register minus_one = Z_R1_scratch;
9052       __ z_lghi(minus_one, -1);
9053       __ z_lghi(one, 1);
9054       __ z_lghi( $dst$$Register, 0);
9055       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
9056       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9057     } else {
9058       Label done;
9059       __ clear_reg($dst$$Register, true, false);
9060       __ z_bre(done);
9061       __ z_lhi($dst$$Register, 1);
9062       __ z_brh(done);
9063       __ z_lhi($dst$$Register, -1);
9064       __ bind(done);
9065     }
9066   %}
9067   ins_pipe(pipe_class_dummy);
9068 %}
9069 
9070 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9071   match(Set dst (CmpD3 src1 src2));
9072   effect(KILL cr);
9073   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9074   size(24);
9075   format %{ "CmpD3    $dst,$src1,$src2" %}
9076   ins_encode %{
9077     // compare registers
9078     __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9079     // Convert condition code into -1,0,1, where
9080     // -1 means unordered or less
9081     //  0 means equal
9082     //  1 means greater.
9083     if (VM_Version::has_LoadStoreConditional()) {
9084       Register one       = Z_R0_scratch;
9085       Register minus_one = Z_R1_scratch;
9086       __ z_lghi(minus_one, -1);
9087       __ z_lghi(one, 1);
9088       __ z_lghi( $dst$$Register, 0);
9089       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
9090       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9091     } else {
9092       Label done;
9093       // indicate unused result
9094       (void) __ clear_reg($dst$$Register, true, false);
9095       __ z_bre(done);
9096       __ z_lhi($dst$$Register, 1);
9097       __ z_brh(done);
9098       __ z_lhi($dst$$Register, -1);
9099       __ bind(done);
9100     }
9101   %}
9102   ins_pipe(pipe_class_dummy);
9103 %}
9104 
9105 //----------Branches---------------------------------------------------------
9106 // Jump
9107 
9108 // Direct Branch.
9109 instruct branch(label labl) %{
9110   match(Goto);
9111   effect(USE labl);
9112   ins_cost(BRANCH_COST);
9113   size(4);
9114   format %{ "BRU     $labl" %}
9115   ins_encode(z_enc_bru(labl));
9116   ins_pipe(pipe_class_dummy);
9117   // If set to 1 this indicates that the current instruction is a
9118   // short variant of a long branch. This avoids using this
9119   // instruction in first-pass matching. It will then only be used in
9120   // the `Shorten_branches' pass.
9121   ins_short_branch(1);
9122 %}
9123 
9124 // Direct Branch.
9125 instruct branchFar(label labl) %{
9126   match(Goto);
9127   effect(USE labl);
9128   ins_cost(BRANCH_COST);
9129   size(6);
9130   format %{ "BRUL   $labl" %}
9131   ins_encode(z_enc_brul(labl));
9132   ins_pipe(pipe_class_dummy);
9133   // This is not a short variant of a branch, but the long variant.
9134   ins_short_branch(0);
9135 %}
9136 
9137 // Conditional Near Branch
9138 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9139   // Same match rule as `branchConFar'.
9140   match(If cmp cr);
9141   effect(USE lbl);
9142   ins_cost(BRANCH_COST);
9143   size(4);
9144   format %{ "branch_con_short,$cmp   $cr, $lbl" %}
9145   ins_encode(z_enc_branch_con_short(cmp, lbl));
9146   ins_pipe(pipe_class_dummy);
9147   // If set to 1 this indicates that the current instruction is a
9148   // short variant of a long branch. This avoids using this
9149   // instruction in first-pass matching. It will then only be used in
9150   // the `Shorten_branches' pass.
9151   ins_short_branch(1);
9152 %}
9153 
9154 // This is for cases when the z/Architecture conditional branch instruction
9155 // does not reach far enough. So we emit a far branch here, which is
9156 // more expensive.
9157 //
9158 // Conditional Far Branch
9159 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9160   // Same match rule as `branchCon'.
9161   match(If cmp cr);
9162   effect(USE cr, USE lbl);
9163   // Make more expensive to prefer compare_and_branch over separate instructions.
9164   ins_cost(2 * BRANCH_COST);
9165   size(6);
9166   format %{ "branch_con_far,$cmp   $cr, $lbl" %}
9167   ins_encode(z_enc_branch_con_far(cmp, lbl));
9168   ins_pipe(pipe_class_dummy);
9169   // This is not a short variant of a branch, but the long variant..
9170   ins_short_branch(0);
9171 %}
9172 
9173 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9174   match(CountedLoopEnd cmp cr);
9175   effect(USE labl);
9176   ins_cost(BRANCH_COST);
9177   size(4);
9178   format %{ "branch_con_short,$cmp   $labl\t # counted loop end" %}
9179   ins_encode(z_enc_branch_con_short(cmp, labl));
9180   ins_pipe(pipe_class_dummy);
9181   // If set to 1 this indicates that the current instruction is a
9182   // short variant of a long branch. This avoids using this
9183   // instruction in first-pass matching. It will then only be used in
9184   // the `Shorten_branches' pass.
9185   ins_short_branch(1);
9186 %}
9187 
9188 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9189   match(CountedLoopEnd cmp cr);
9190   effect(USE labl);
9191   ins_cost(BRANCH_COST);
9192   size(6);
9193   format %{ "branch_con_far,$cmp   $labl\t # counted loop end" %}
9194   ins_encode(z_enc_branch_con_far(cmp, labl));
9195   ins_pipe(pipe_class_dummy);
9196   // This is not a short variant of a branch, but the long variant.
9197   ins_short_branch(0);
9198 %}
9199 
9200 //----------Compare and Branch (short distance)------------------------------
9201 
9202 // INT REG operands for loop counter processing.
9203 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9204   match(CountedLoopEnd boolnode (CmpI src1 src2));
9205   effect(USE labl, KILL cr);
9206   predicate(VM_Version::has_CompareBranch());
9207   ins_cost(BRANCH_COST);
9208   // TODO: s390 port size(FIXED_SIZE);
9209   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
9210   opcode(CRJ_ZOPC);
9211   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9212   ins_pipe(pipe_class_dummy);
9213   ins_short_branch(1);
9214 %}
9215 
9216 // INT REG operands.
9217 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9218   match(If boolnode (CmpI src1 src2));
9219   effect(USE labl, KILL cr);
9220   predicate(VM_Version::has_CompareBranch());
9221   ins_cost(BRANCH_COST);
9222   // TODO: s390 port size(FIXED_SIZE);
9223   format %{ "CRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
9224   opcode(CRJ_ZOPC);
9225   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9226   ins_pipe(pipe_class_dummy);
9227   ins_short_branch(1);
9228 %}
9229 
9230 // Unsigned INT REG operands
9231 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9232   match(If boolnode (CmpU src1 src2));
9233   effect(USE labl, KILL cr);
9234   predicate(VM_Version::has_CompareBranch());
9235   ins_cost(BRANCH_COST);
9236   // TODO: s390 port size(FIXED_SIZE);
9237   format %{ "CLRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
9238   opcode(CLRJ_ZOPC);
9239   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9240   ins_pipe(pipe_class_dummy);
9241   ins_short_branch(1);
9242 %}
9243 
9244 // LONG REG operands
9245 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9246   match(If boolnode (CmpL src1 src2));
9247   effect(USE labl, KILL cr);
9248   predicate(VM_Version::has_CompareBranch());
9249   ins_cost(BRANCH_COST);
9250   // TODO: s390 port size(FIXED_SIZE);
9251   format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9252   opcode(CGRJ_ZOPC);
9253   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9254   ins_pipe(pipe_class_dummy);
9255   ins_short_branch(1);
9256 %}
9257 
9258 //  PTR REG operands
9259 
9260 // Separate rules for regular and narrow oops.  ADLC can't recognize
9261 // rules with polymorphic operands to be sisters -> shorten_branches
9262 // will not shorten.
9263 
9264 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9265   match(If boolnode (CmpP src1 src2));
9266   effect(USE labl, KILL cr);
9267   predicate(VM_Version::has_CompareBranch());
9268   ins_cost(BRANCH_COST);
9269   // TODO: s390 port size(FIXED_SIZE);
9270   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9271   opcode(CLGRJ_ZOPC);
9272   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9273   ins_pipe(pipe_class_dummy);
9274   ins_short_branch(1);
9275 %}
9276 
9277 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9278   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9279   effect(USE labl, KILL cr);
9280   predicate(VM_Version::has_CompareBranch());
9281   ins_cost(BRANCH_COST);
9282   // TODO: s390 port size(FIXED_SIZE);
9283   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9284   opcode(CLGRJ_ZOPC);
9285   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9286   ins_pipe(pipe_class_dummy);
9287   ins_short_branch(1);
9288 %}
9289 
9290 // INT REG/IMM operands for loop counter processing
9291 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9292   match(CountedLoopEnd boolnode (CmpI src1 src2));
9293   effect(USE labl, KILL cr);
9294   predicate(VM_Version::has_CompareBranch());
9295   ins_cost(BRANCH_COST);
9296   // TODO: s390 port size(FIXED_SIZE);
9297   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
9298   opcode(CIJ_ZOPC);
9299   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9300   ins_pipe(pipe_class_dummy);
9301   ins_short_branch(1);
9302 %}
9303 
9304 // INT REG/IMM operands
9305 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9306   match(If boolnode (CmpI src1 src2));
9307   effect(USE labl, KILL cr);
9308   predicate(VM_Version::has_CompareBranch());
9309   ins_cost(BRANCH_COST);
9310   // TODO: s390 port size(FIXED_SIZE);
9311   format %{ "CIJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
9312   opcode(CIJ_ZOPC);
9313   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9314   ins_pipe(pipe_class_dummy);
9315   ins_short_branch(1);
9316 %}
9317 
9318 // INT REG/IMM operands
9319 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9320   match(If boolnode (CmpU src1 src2));
9321   effect(USE labl, KILL cr);
9322   predicate(VM_Version::has_CompareBranch());
9323   ins_cost(BRANCH_COST);
9324   // TODO: s390 port size(FIXED_SIZE);
9325   format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9326   opcode(CLIJ_ZOPC);
9327   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9328   ins_pipe(pipe_class_dummy);
9329   ins_short_branch(1);
9330 %}
9331 
9332 // LONG REG/IMM operands
9333 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9334   match(If boolnode (CmpL src1 src2));
9335   effect(USE labl, KILL cr);
9336   predicate(VM_Version::has_CompareBranch());
9337   ins_cost(BRANCH_COST);
9338   // TODO: s390 port size(FIXED_SIZE);
9339   format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9340   opcode(CGIJ_ZOPC);
9341   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9342   ins_pipe(pipe_class_dummy);
9343   ins_short_branch(1);
9344 %}
9345 
9346 // PTR REG-imm operands
9347 
9348 // Separate rules for regular and narrow oops. ADLC can't recognize
9349 // rules with polymorphic operands to be sisters -> shorten_branches
9350 // will not shorten.
9351 
9352 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9353   match(If boolnode (CmpP src1 src2));
9354   effect(USE labl, KILL cr);
9355   predicate(VM_Version::has_CompareBranch());
9356   ins_cost(BRANCH_COST);
9357   // TODO: s390 port size(FIXED_SIZE);
9358   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9359   opcode(CLGIJ_ZOPC);
9360   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9361   ins_pipe(pipe_class_dummy);
9362   ins_short_branch(1);
9363 %}
9364 
9365 // Compare against zero only, do not mix N and P oops (encode/decode required).
9366 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9367   match(If boolnode (CmpP (DecodeN src1) src2));
9368   effect(USE labl, KILL cr);
9369   predicate(VM_Version::has_CompareBranch());
9370   ins_cost(BRANCH_COST);
9371   // TODO: s390 port size(FIXED_SIZE);
9372   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9373   opcode(CLGIJ_ZOPC);
9374   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9375   ins_pipe(pipe_class_dummy);
9376   ins_short_branch(1);
9377 %}
9378 
9379 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9380   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9381   effect(USE labl, KILL cr);
9382   predicate(VM_Version::has_CompareBranch());
9383   ins_cost(BRANCH_COST);
9384   // TODO: s390 port size(FIXED_SIZE);
9385   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9386   opcode(CLGIJ_ZOPC);
9387   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9388   ins_pipe(pipe_class_dummy);
9389   ins_short_branch(1);
9390 %}
9391 
9392 
9393 //----------Compare and Branch (far distance)------------------------------
9394 
9395 // INT REG operands for loop counter processing
9396 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9397   match(CountedLoopEnd boolnode (CmpI src1 src2));
9398   effect(USE labl, KILL cr);
9399   predicate(VM_Version::has_CompareBranch());
9400   ins_cost(BRANCH_COST+DEFAULT_COST);
9401   // TODO: s390 port size(FIXED_SIZE);
9402   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
9403   opcode(CR_ZOPC, BRCL_ZOPC);
9404   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9405   ins_pipe(pipe_class_dummy);
9406   ins_short_branch(0);
9407 %}
9408 
9409 // INT REG operands
9410 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9411   match(If boolnode (CmpI src1 src2));
9412   effect(USE labl, KILL cr);
9413   predicate(VM_Version::has_CompareBranch());
9414   ins_cost(BRANCH_COST+DEFAULT_COST);
9415   // TODO: s390 port size(FIXED_SIZE);
9416   format %{ "CRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9417   opcode(CR_ZOPC, BRCL_ZOPC);
9418   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9419   ins_pipe(pipe_class_dummy);
9420   ins_short_branch(0);
9421 %}
9422 
9423 // INT REG operands
9424 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9425   match(If boolnode (CmpU src1 src2));
9426   effect(USE labl, KILL cr);
9427   predicate(VM_Version::has_CompareBranch());
9428   ins_cost(BRANCH_COST+DEFAULT_COST);
9429   // TODO: s390 port size(FIXED_SIZE);
9430   format %{ "CLRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9431   opcode(CLR_ZOPC, BRCL_ZOPC);
9432   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9433   ins_pipe(pipe_class_dummy);
9434   ins_short_branch(0);
9435 %}
9436 
9437 // LONG REG operands
9438 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9439   match(If boolnode (CmpL src1 src2));
9440   effect(USE labl, KILL cr);
9441   predicate(VM_Version::has_CompareBranch());
9442   ins_cost(BRANCH_COST+DEFAULT_COST);
9443   // TODO: s390 port size(FIXED_SIZE);
9444   format %{ "CGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9445   opcode(CGR_ZOPC, BRCL_ZOPC);
9446   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9447   ins_pipe(pipe_class_dummy);
9448   ins_short_branch(0);
9449 %}
9450 
9451 // PTR REG operands
9452 
9453 // Separate rules for regular and narrow oops. ADLC can't recognize
9454 // rules with polymorphic operands to be sisters -> shorten_branches
9455 // will not shorten.
9456 
9457 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9458   match(If boolnode (CmpP src1 src2));
9459   effect(USE labl, KILL cr);
9460   predicate(VM_Version::has_CompareBranch());
9461   ins_cost(BRANCH_COST+DEFAULT_COST);
9462   // TODO: s390 port size(FIXED_SIZE);
9463   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9464   opcode(CLGR_ZOPC, BRCL_ZOPC);
9465   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9466   ins_pipe(pipe_class_dummy);
9467   ins_short_branch(0);
9468 %}
9469 
9470 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9471   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9472   effect(USE labl, KILL cr);
9473   predicate(VM_Version::has_CompareBranch());
9474   ins_cost(BRANCH_COST+DEFAULT_COST);
9475   // TODO: s390 port size(FIXED_SIZE);
9476   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9477   opcode(CLGR_ZOPC, BRCL_ZOPC);
9478   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9479   ins_pipe(pipe_class_dummy);
9480   ins_short_branch(0);
9481 %}
9482 
9483 // INT REG/IMM operands for loop counter processing
9484 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9485   match(CountedLoopEnd boolnode (CmpI src1 src2));
9486   effect(USE labl, KILL cr);
9487   predicate(VM_Version::has_CompareBranch());
9488   ins_cost(BRANCH_COST+DEFAULT_COST);
9489   // TODO: s390 port size(FIXED_SIZE);
9490   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
9491   opcode(CHI_ZOPC, BRCL_ZOPC);
9492   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9493   ins_pipe(pipe_class_dummy);
9494   ins_short_branch(0);
9495 %}
9496 
9497 // INT REG/IMM operands
9498 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9499   match(If boolnode (CmpI src1 src2));
9500   effect(USE labl, KILL cr);
9501   predicate(VM_Version::has_CompareBranch());
9502   ins_cost(BRANCH_COST+DEFAULT_COST);
9503   // TODO: s390 port size(FIXED_SIZE);
9504   format %{ "CIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9505   opcode(CHI_ZOPC, BRCL_ZOPC);
9506   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9507   ins_pipe(pipe_class_dummy);
9508   ins_short_branch(0);
9509 %}
9510 
9511 // INT REG/IMM operands
9512 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9513   match(If boolnode (CmpU src1 src2));
9514   effect(USE labl, KILL cr);
9515   predicate(VM_Version::has_CompareBranch());
9516   ins_cost(BRANCH_COST+DEFAULT_COST);
9517   // TODO: s390 port size(FIXED_SIZE);
9518   format %{ "CLIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9519   opcode(CLFI_ZOPC, BRCL_ZOPC);
9520   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9521   ins_pipe(pipe_class_dummy);
9522   ins_short_branch(0);
9523 %}
9524 
9525 // LONG REG/IMM operands
9526 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9527   match(If boolnode (CmpL src1 src2));
9528   effect(USE labl, KILL cr);
9529   predicate(VM_Version::has_CompareBranch());
9530   ins_cost(BRANCH_COST+DEFAULT_COST);
9531   // TODO: s390 port size(FIXED_SIZE);
9532   format %{ "CGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9533   opcode(CGHI_ZOPC, BRCL_ZOPC);
9534   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9535   ins_pipe(pipe_class_dummy);
9536   ins_short_branch(0);
9537 %}
9538 
9539 // PTR REG-imm operands
9540 
9541 // Separate rules for regular and narrow oops. ADLC can't recognize
9542 // rules with polymorphic operands to be sisters -> shorten_branches
9543 // will not shorten.
9544 
9545 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9546   match(If boolnode (CmpP src1 src2));
9547   effect(USE labl, KILL cr);
9548   predicate(VM_Version::has_CompareBranch());
9549   ins_cost(BRANCH_COST+DEFAULT_COST);
9550   // TODO: s390 port size(FIXED_SIZE);
9551   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9552   opcode(CLGFI_ZOPC, BRCL_ZOPC);
9553   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9554   ins_pipe(pipe_class_dummy);
9555   ins_short_branch(0);
9556 %}
9557 
9558 // Compare against zero only, do not mix N and P oops (encode/decode required).
9559 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9560   match(If boolnode (CmpP (DecodeN src1) src2));
9561   effect(USE labl, KILL cr);
9562   predicate(VM_Version::has_CompareBranch());
9563   ins_cost(BRANCH_COST+DEFAULT_COST);
9564   // TODO: s390 port size(FIXED_SIZE);
9565   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9566   opcode(CLGFI_ZOPC, BRCL_ZOPC);
9567   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9568   ins_pipe(pipe_class_dummy);
9569   ins_short_branch(0);
9570 %}
9571 
9572 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9573   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9574   effect(USE labl, KILL cr);
9575   predicate(VM_Version::has_CompareBranch());
9576   ins_cost(BRANCH_COST+DEFAULT_COST);
9577   // TODO: s390 port size(FIXED_SIZE);
9578   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9579   opcode(CLGFI_ZOPC, BRCL_ZOPC);
9580   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9581   ins_pipe(pipe_class_dummy);
9582   ins_short_branch(0);
9583 %}
9584 
9585 // ============================================================================
9586 // Long Compare
9587 
9588 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9589 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9590 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9591 // are collapsed internally in the ADLC's dfa-gen code. The match for
9592 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9593 // foo match ends up with the wrong leaf. One fix is to not match both
9594 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9595 // both forms beat the trinary form of long-compare and both are very useful
9596 // on platforms which have few registers.
9597 
9598 // Manifest a CmpL3 result in an integer register. Very painful.
9599 // This is the test to avoid.
9600 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9601   match(Set dst (CmpL3 src1 src2));
9602   effect(KILL cr);
9603   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9604   size(24);
9605   format %{ "CmpL3 $dst,$src1,$src2" %}
9606   ins_encode %{
9607     Label done;
9608     // compare registers
9609     __ z_cgr($src1$$Register, $src2$$Register);
9610     // Convert condition code into -1,0,1, where
9611     // -1 means less
9612     //  0 means equal
9613     //  1 means greater.
9614     if (VM_Version::has_LoadStoreConditional()) {
9615       Register one       = Z_R0_scratch;
9616       Register minus_one = Z_R1_scratch;
9617       __ z_lghi(minus_one, -1);
9618       __ z_lghi(one, 1);
9619       __ z_lghi( $dst$$Register, 0);
9620       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
9621       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9622     } else {
9623       __ clear_reg($dst$$Register, true, false);
9624       __ z_bre(done);
9625       __ z_lhi($dst$$Register, 1);
9626       __ z_brh(done);
9627       __ z_lhi($dst$$Register, -1);
9628     }
9629     __ bind(done);
9630   %}
9631   ins_pipe(pipe_class_dummy);
9632 %}
9633 
9634 // ============================================================================
9635 // Safepoint Instruction
9636 
9637 instruct safePoint() %{
9638   match(SafePoint);
9639   predicate(false);
9640   // TODO: s390 port size(FIXED_SIZE);
9641   format %{ "UNIMPLEMENTED Safepoint_ " %}
9642   ins_encode(enc_unimplemented());
9643   ins_pipe(pipe_class_dummy);
9644 %}
9645 
9646 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9647   match(SafePoint poll);
9648   effect(USE poll, KILL cr); // R0 is killed, too.
9649   // TODO: s390 port size(FIXED_SIZE);
9650   format %{ "TM      #0[,$poll],#111\t # Safepoint: poll for GC" %}
9651   ins_encode %{
9652     // Mark the code position where the load from the safepoint
9653     // polling page was emitted as relocInfo::poll_type.
9654     __ relocate(relocInfo::poll_type);
9655     __ load_from_polling_page($poll$$Register);
9656   %}
9657   ins_pipe(pipe_class_dummy);
9658 %}
9659 
9660 // ============================================================================
9661 
9662 // Call Instructions
9663 
9664 // Call Java Static Instruction
9665 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9666   match(CallStaticJava);
9667   effect(USE meth);
9668   ins_cost(CALL_COST);
9669   // TODO: s390 port size(VARIABLE_SIZE);
9670   format %{ "CALL,static dynTOC $meth; ==> " %}
9671   ins_encode( z_enc_java_static_call(meth) );
9672   ins_pipe(pipe_class_dummy);
9673   ins_alignment(2);
9674 %}
9675 
9676 // Call Java Dynamic Instruction
9677 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9678   match(CallDynamicJava);
9679   effect(USE meth);
9680   ins_cost(CALL_COST);
9681   // TODO: s390 port size(VARIABLE_SIZE);
9682   format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9683   ins_encode(z_enc_java_dynamic_call(meth));
9684   ins_pipe(pipe_class_dummy);
9685   ins_alignment(2);
9686 %}
9687 
9688 // Call Runtime Instruction
9689 instruct CallRuntimeDirect(method meth) %{
9690   match(CallRuntime);
9691   effect(USE meth);
9692   ins_cost(CALL_COST);
9693   // TODO: s390 port size(VARIABLE_SIZE);
9694   ins_num_consts(1);
9695   ins_alignment(2);
9696   format %{ "CALL,runtime" %}
9697   ins_encode( z_enc_java_to_runtime_call(meth) );
9698   ins_pipe(pipe_class_dummy);
9699 %}
9700 
9701 // Call runtime without safepoint - same as CallRuntime
9702 instruct CallLeafDirect(method meth) %{
9703   match(CallLeaf);
9704   effect(USE meth);
9705   ins_cost(CALL_COST);
9706   // TODO: s390 port size(VARIABLE_SIZE);
9707   ins_num_consts(1);
9708   ins_alignment(2);
9709   format %{ "CALL,runtime leaf $meth" %}
9710   ins_encode( z_enc_java_to_runtime_call(meth) );
9711   ins_pipe(pipe_class_dummy);
9712 %}
9713 
9714 // Call runtime without safepoint - same as CallLeaf
9715 instruct CallLeafNoFPDirect(method meth) %{
9716   match(CallLeafNoFP);
9717   effect(USE meth);
9718   ins_cost(CALL_COST);
9719   // TODO: s390 port size(VARIABLE_SIZE);
9720   ins_num_consts(1);
9721   format %{ "CALL,runtime leaf nofp $meth" %}
9722   ins_encode( z_enc_java_to_runtime_call(meth) );
9723   ins_pipe(pipe_class_dummy);
9724   ins_alignment(2);
9725 %}
9726 
9727 // Tail Call; Jump from runtime stub to Java code.
9728 // Also known as an 'interprocedural jump'.
9729 // Target of jump will eventually return to caller.
9730 // TailJump below removes the return address.
9731 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{
9732   match(TailCall jump_target method_oop);
9733   ins_cost(CALL_COST);
9734   size(2);
9735   format %{ "Jmp     $jump_target\t# $method_oop holds method oop" %}
9736   ins_encode %{ __ z_br($jump_target$$Register); %}
9737   ins_pipe(pipe_class_dummy);
9738 %}
9739 
9740 // Return Instruction
9741 instruct Ret() %{
9742   match(Return);
9743   size(2);
9744   format %{ "BR(Z_R14) // branch to link register" %}
9745   ins_encode %{ __ z_br(Z_R14); %}
9746   ins_pipe(pipe_class_dummy);
9747 %}
9748 
9749 // Tail Jump; remove the return address; jump to target.
9750 // TailCall above leaves the return address around.
9751 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9752 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9753 // "restore" before this instruction (in Epilogue), we need to materialize it
9754 // in %i0.
9755 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
9756   match(TailJump jump_target ex_oop);
9757   ins_cost(CALL_COST);
9758   size(8);
9759   format %{ "TailJump $jump_target" %}
9760   ins_encode %{
9761     __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
9762     __ z_br($jump_target$$Register);
9763   %}
9764   ins_pipe(pipe_class_dummy);
9765 %}
9766 
9767 // Create exception oop: created by stack-crawling runtime code.
9768 // Created exception is now available to this handler, and is setup
9769 // just prior to jumping to this handler. No code emitted.
9770 instruct CreateException(rarg1RegP ex_oop) %{
9771   match(Set ex_oop (CreateEx));
9772   ins_cost(0);
9773   size(0);
9774   format %{ "# exception oop; no code emitted" %}
9775   ins_encode(/*empty*/);
9776   ins_pipe(pipe_class_dummy);
9777 %}
9778 
9779 // Rethrow exception: The exception oop will come in the first
9780 // argument position. Then JUMP (not call) to the rethrow stub code.
9781 instruct RethrowException() %{
9782   match(Rethrow);
9783   ins_cost(CALL_COST);
9784   // TODO: s390 port size(VARIABLE_SIZE);
9785   format %{ "Jmp    rethrow_stub" %}
9786   ins_encode %{
9787     cbuf.set_insts_mark();
9788     __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
9789     __ z_br(Z_R1_scratch);
9790   %}
9791   ins_pipe(pipe_class_dummy);
9792 %}
9793 
9794 // Die now.
9795 instruct ShouldNotReachHere() %{
9796   match(Halt);
9797   ins_cost(CALL_COST);
9798   size(2);
9799   format %{ "ILLTRAP; ShouldNotReachHere" %}
9800   ins_encode %{ __ z_illtrap(); %}
9801   ins_pipe(pipe_class_dummy);
9802 %}
9803 
9804 // ============================================================================
9805 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9806 // array for an instance of the superklass. Set a hidden internal cache on a
9807 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9808 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9809 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
9810                              rarg4RegP scratch1, rarg5RegP scratch2) %{
9811   match(Set index (PartialSubtypeCheck sub super));
9812   effect(KILL pcc, KILL scratch1, KILL scratch2);
9813   ins_cost(10 * DEFAULT_COST);
9814   size(12);
9815   format %{ "  CALL   PartialSubtypeCheck\n" %}
9816   ins_encode %{
9817     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9818     __ load_const_optimized(Z_ARG4, stub_address);
9819     __ z_basr(Z_R14, Z_ARG4);
9820   %}
9821   ins_pipe(pipe_class_dummy);
9822 %}
9823 
9824 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero,
9825                                      rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
9826   match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero));
9827   effect(KILL scratch1, KILL scratch2, KILL index);
9828   ins_cost(10 * DEFAULT_COST);
9829   // TODO: s390 port size(FIXED_SIZE);
9830   format %{ "CALL   PartialSubtypeCheck_vs_zero\n" %}
9831   ins_encode %{
9832     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9833     __ load_const_optimized(Z_ARG4, stub_address);
9834     __ z_basr(Z_R14, Z_ARG4);
9835   %}
9836   ins_pipe(pipe_class_dummy);
9837 %}
9838 
9839 // ============================================================================
9840 // inlined locking and unlocking
9841 
9842 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9843   match(Set pcc (FastLock oop box));
9844   effect(TEMP tmp1, TEMP tmp2);
9845   ins_cost(100);
9846   // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized.
9847   format %{ "FASTLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9848   ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9849                                              UseBiasedLocking && !UseOptoBiasInlining); %}
9850   ins_pipe(pipe_class_dummy);
9851 %}
9852 
9853 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9854   match(Set pcc (FastUnlock oop box));
9855   effect(TEMP tmp1, TEMP tmp2);
9856   ins_cost(100);
9857   // TODO: s390 port size(FIXED_SIZE);  // emitted code depends on UseBiasedLocking being on/off.
9858   format %{ "FASTUNLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9859   ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9860                                                UseBiasedLocking && !UseOptoBiasInlining); %}
9861   ins_pipe(pipe_class_dummy);
9862 %}
9863 
9864 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
9865   match(Set dummy (ClearArray cnt base));
9866   effect(KILL cr);
9867   ins_cost(100);
9868   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to varying #instructions.
9869   format %{ "ClearArrayConst $cnt,$base" %}
9870   ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
9871   ins_pipe(pipe_class_dummy);
9872 %}
9873 
9874 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{
9875   match(Set dummy (ClearArray cnt base));
9876   effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too.
9877   ins_cost(200);
9878   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to optimized constant loader.
9879   format %{ "ClearArrayConstBig $cnt,$base" %}
9880   ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $srcA$$Register, $srcL$$Register); %}
9881   ins_pipe(pipe_class_dummy);
9882 %}
9883 
9884 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{
9885   match(Set dummy (ClearArray cnt base));
9886   effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too.
9887   ins_cost(300);
9888   // TODO: s390 port size(FIXED_SIZE);  // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
9889   format %{ "ClearArrayVar $cnt,$base" %}
9890   ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $srcA$$Register, $srcL$$Register); %}
9891   ins_pipe(pipe_class_dummy);
9892 %}
9893 
9894 // ============================================================================
9895 // CompactStrings
9896 
9897 // String equals
9898 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9899   match(Set result (StrEquals (Binary str1 str2) cnt));
9900   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9901   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
9902   ins_cost(300);
9903   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9904   ins_encode %{
9905     __ array_equals(false, $str1$$Register, $str2$$Register,
9906                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9907                     $result$$Register, true /* byte */);
9908   %}
9909   ins_pipe(pipe_class_dummy);
9910 %}
9911 
9912 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9913   match(Set result (StrEquals (Binary str1 str2) cnt));
9914   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9915   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9916   ins_cost(300);
9917   format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
9918   ins_encode %{
9919     __ array_equals(false, $str1$$Register, $str2$$Register,
9920                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9921                     $result$$Register, false /* byte */);
9922   %}
9923   ins_pipe(pipe_class_dummy);
9924 %}
9925 
9926 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
9927   match(Set result (StrEquals (Binary str1 str2) cnt));
9928   effect(KILL cr); // R0 is killed, too.
9929   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
9930   ins_cost(100);
9931   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9932   ins_encode %{
9933     const int cnt_imm = $cnt$$constant;
9934     if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
9935     __ z_lhi($result$$Register, 1);
9936     if (cnt_imm) {
9937       if (VM_Version::has_LoadStoreConditional()) {
9938         __ z_lhi(Z_R0_scratch, 0);
9939         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
9940       } else {
9941         Label Lskip;
9942         __ z_bre(Lskip);
9943         __ clear_reg($result$$Register);
9944         __ bind(Lskip);
9945       }
9946     }
9947   %}
9948   ins_pipe(pipe_class_dummy);
9949 %}
9950 
9951 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
9952   match(Set result (StrEquals (Binary str1 str2) cnt));
9953   effect(KILL cr); // R0 is killed, too.
9954   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9955   ins_cost(100);
9956   format %{ "String Equals $str1,$str2,$cnt -> $result" %}
9957   ins_encode %{
9958     const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
9959     if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
9960     __ z_lhi($result$$Register, 1);
9961     if (cnt_imm) {
9962       if (VM_Version::has_LoadStoreConditional()) {
9963         __ z_lhi(Z_R0_scratch, 0);
9964         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
9965       } else {
9966         Label Lskip;
9967         __ z_bre(Lskip);
9968         __ clear_reg($result$$Register);
9969         __ bind(Lskip);
9970       }
9971     }
9972   %}
9973   ins_pipe(pipe_class_dummy);
9974 %}
9975 
9976 // Array equals
9977 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9978   match(Set result (AryEq ary1 ary2));
9979   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9980   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
9981   ins_cost(300);
9982   format %{ "Array Equals $ary1,$ary2 -> $result" %}
9983   ins_encode %{
9984     __ array_equals(true, $ary1$$Register, $ary2$$Register,
9985                     noreg, $oddReg$$Register, $evenReg$$Register,
9986                     $result$$Register, true /* byte */);
9987   %}
9988   ins_pipe(pipe_class_dummy);
9989 %}
9990 
9991 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9992   match(Set result (AryEq ary1 ary2));
9993   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9994   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
9995   ins_cost(300);
9996   format %{ "Array Equals $ary1,$ary2 -> $result" %}
9997   ins_encode %{
9998     __ array_equals(true, $ary1$$Register, $ary2$$Register,
9999                     noreg, $oddReg$$Register, $evenReg$$Register,
10000                     $result$$Register, false /* byte */);
10001   %}
10002   ins_pipe(pipe_class_dummy);
10003 %}
10004 
10005 // String CompareTo
10006 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10007   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10008   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10009   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10010   ins_cost(300);
10011   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10012   ins_encode %{
10013     __ string_compare($str1$$Register, $str2$$Register,
10014                       $cnt1$$Register, $cnt2$$Register,
10015                       $oddReg$$Register, $evenReg$$Register,
10016                       $result$$Register, StrIntrinsicNode::LL);
10017   %}
10018   ins_pipe(pipe_class_dummy);
10019 %}
10020 
10021 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10022   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10023   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10024   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10025   ins_cost(300);
10026   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10027   ins_encode %{
10028     __ string_compare($str1$$Register, $str2$$Register,
10029                       $cnt1$$Register, $cnt2$$Register,
10030                       $oddReg$$Register, $evenReg$$Register,
10031                       $result$$Register, StrIntrinsicNode::UU);
10032   %}
10033   ins_pipe(pipe_class_dummy);
10034 %}
10035 
10036 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10037   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10038   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10039   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10040   ins_cost(300);
10041   format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10042   ins_encode %{
10043     __ string_compare($str1$$Register, $str2$$Register,
10044                       $cnt1$$Register, $cnt2$$Register,
10045                       $oddReg$$Register, $evenReg$$Register,
10046                       $result$$Register, StrIntrinsicNode::LU);
10047   %}
10048   ins_pipe(pipe_class_dummy);
10049 %}
10050 
10051 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10052   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10053   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10054   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10055   ins_cost(300);
10056   format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10057   ins_encode %{
10058     __ string_compare($str2$$Register, $str1$$Register,
10059                       $cnt2$$Register, $cnt1$$Register,
10060                       $oddReg$$Register, $evenReg$$Register,
10061                       $result$$Register, StrIntrinsicNode::UL);
10062   %}
10063   ins_pipe(pipe_class_dummy);
10064 %}
10065 
10066 // String IndexOfChar
10067 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10068   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10069   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10070   ins_cost(200);
10071   format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10072   ins_encode %{
10073     __ string_indexof_char($result$$Register,
10074                            $haystack$$Register, $haycnt$$Register,
10075                            $ch$$Register, 0 /* unused, ch is in register */,
10076                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10077   %}
10078   ins_pipe(pipe_class_dummy);
10079 %}
10080 
10081 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10082   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10083   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10084   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10085   ins_cost(200);
10086   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10087   ins_encode %{
10088     immPOper *needleOper = (immPOper *)$needle;
10089     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10090     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10091     jchar chr;
10092 #ifdef VM_LITTLE_ENDIAN
10093     Unimplemented();
10094 #else
10095     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10096            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10097 #endif
10098     __ string_indexof_char($result$$Register,
10099                            $haystack$$Register, $haycnt$$Register,
10100                            noreg, chr,
10101                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10102   %}
10103   ins_pipe(pipe_class_dummy);
10104 %}
10105 
10106 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10107   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10108   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10109   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10110   ins_cost(200);
10111   format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10112   ins_encode %{
10113     immPOper *needleOper = (immPOper *)$needle;
10114     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10115     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10116     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10117     __ string_indexof_char($result$$Register,
10118                            $haystack$$Register, $haycnt$$Register,
10119                            noreg, chr,
10120                            $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10121   %}
10122   ins_pipe(pipe_class_dummy);
10123 %}
10124 
10125 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10126   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10127   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10128   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10129   ins_cost(200);
10130   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10131   ins_encode %{
10132     immPOper *needleOper = (immPOper *)$needle;
10133     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10134     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10135     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10136     __ string_indexof_char($result$$Register,
10137                            $haystack$$Register, $haycnt$$Register,
10138                            noreg, chr,
10139                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10140   %}
10141   ins_pipe(pipe_class_dummy);
10142 %}
10143 
10144 // String IndexOf
10145 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10146   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10147   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10148   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10149   ins_cost(250);
10150   format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10151   ins_encode %{
10152     __ string_indexof($result$$Register,
10153                       $haystack$$Register, $haycnt$$Register,
10154                       $needle$$Register, noreg, $needlecntImm$$constant,
10155                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10156   %}
10157   ins_pipe(pipe_class_dummy);
10158 %}
10159 
10160 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10161   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10162   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10163   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10164   ins_cost(250);
10165   format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10166   ins_encode %{
10167     __ string_indexof($result$$Register,
10168                       $haystack$$Register, $haycnt$$Register,
10169                       $needle$$Register, noreg, $needlecntImm$$constant,
10170                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10171   %}
10172   ins_pipe(pipe_class_dummy);
10173 %}
10174 
10175 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10176   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10177   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10178   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10179   ins_cost(250);
10180   format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10181   ins_encode %{
10182     __ string_indexof($result$$Register,
10183                       $haystack$$Register, $haycnt$$Register,
10184                       $needle$$Register, noreg, $needlecntImm$$constant,
10185                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10186   %}
10187   ins_pipe(pipe_class_dummy);
10188 %}
10189 
10190 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10191   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10192   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10193   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10194   ins_cost(300);
10195   format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10196   ins_encode %{
10197     __ string_indexof($result$$Register,
10198                       $haystack$$Register, $haycnt$$Register,
10199                       $needle$$Register, $needlecnt$$Register, 0,
10200                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10201   %}
10202   ins_pipe(pipe_class_dummy);
10203 %}
10204 
10205 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10206   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10207   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10208   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10209   ins_cost(300);
10210   format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10211   ins_encode %{
10212     __ string_indexof($result$$Register,
10213                       $haystack$$Register, $haycnt$$Register,
10214                       $needle$$Register, $needlecnt$$Register, 0,
10215                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10216   %}
10217   ins_pipe(pipe_class_dummy);
10218 %}
10219 
10220 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10221   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10222   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10223   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10224   ins_cost(300);
10225   format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10226   ins_encode %{
10227     __ string_indexof($result$$Register,
10228                       $haystack$$Register, $haycnt$$Register,
10229                       $needle$$Register, $needlecnt$$Register, 0,
10230                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10231   %}
10232   ins_pipe(pipe_class_dummy);
10233 %}
10234 
10235 // char[] to byte[] compression
10236 instruct string_compress(iRegP src, rarg5RegP dst, iRegI result, roddRegI len, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10237   match(Set result (StrCompressedCopy src (Binary dst len)));
10238   effect(TEMP_DEF result, USE_KILL dst, USE_KILL len, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10239   ins_cost(300);
10240   format %{ "String Compress $src->$dst($len) -> $result" %}
10241   ins_encode %{
10242     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10243                        $evenReg$$Register, $tmp$$Register);
10244   %}
10245   ins_pipe(pipe_class_dummy);
10246 %}
10247 
10248 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10249 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10250 //  match(Set dummy (StrInflatedCopy src (Binary dst len)));
10251 //  effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10252 //  predicate(VM_Version::has_ETF2Enhancements());
10253 //  ins_cost(300);
10254 //  format %{ "String Inflate (trot) $dst,$src($len)" %}
10255 //  ins_encode %{
10256 //    __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10257 //  %}
10258 //  ins_pipe(pipe_class_dummy);
10259 //%}
10260 
10261 // byte[] to char[] inflation
10262 instruct string_inflate(Universe dummy, rarg5RegP src, iRegP dst, roddRegI len, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10263   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10264   effect(USE_KILL src, USE_KILL len, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10265   ins_cost(300);
10266   format %{ "String Inflate $src->$dst($len)" %}
10267   ins_encode %{
10268     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $evenReg$$Register, $tmp$$Register);
10269   %}
10270   ins_pipe(pipe_class_dummy);
10271 %}
10272 
10273 // StringCoding.java intrinsics
10274 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10275   match(Set result (HasNegatives ary1 len));
10276   effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10277   ins_cost(300);
10278   format %{ "has negatives byte[] $ary1($len) -> $result" %}
10279   ins_encode %{
10280     __ has_negatives($result$$Register, $ary1$$Register, $len$$Register,
10281                      $oddReg$$Register, $evenReg$$Register, $tmp$$Register);
10282   %}
10283   ins_pipe(pipe_class_dummy);
10284 %}
10285 
10286 // encode char[] to byte[] in ISO_8859_1
10287 instruct encode_iso_array(rarg5RegP src, iRegP dst, iRegI result, roddRegI len, revenRegI evenReg, iRegI tmp, iRegI tmp2, flagsReg cr) %{
10288   match(Set result (EncodeISOArray src (Binary dst len)));
10289   effect(TEMP_DEF result, USE_KILL src, USE_KILL len, TEMP evenReg, TEMP tmp, TEMP tmp2, KILL cr); // R0, R1 are killed, too.
10290   ins_cost(300);
10291   format %{ "Encode array $src->$dst($len) -> $result" %}
10292   ins_encode %{
10293     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10294                        $evenReg$$Register, $tmp$$Register, $tmp2$$Register);
10295   %}
10296   ins_pipe(pipe_class_dummy);
10297 %}
10298 
10299 
10300 //----------PEEPHOLE RULES-----------------------------------------------------
10301 // These must follow all instruction definitions as they use the names
10302 // defined in the instructions definitions.
10303 //
10304 // peepmatch (root_instr_name [preceeding_instruction]*);
10305 //
10306 // peepconstraint %{
10307 // (instruction_number.operand_name relational_op instruction_number.operand_name
10308 //  [, ...]);
10309 // // instruction numbers are zero-based using left to right order in peepmatch
10310 //
10311 // peepreplace (instr_name([instruction_number.operand_name]*));
10312 // // provide an instruction_number.operand_name for each operand that appears
10313 // // in the replacement instruction's match rule
10314 //
10315 // ---------VM FLAGS---------------------------------------------------------
10316 //
10317 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10318 //
10319 // Each peephole rule is given an identifying number starting with zero and
10320 // increasing by one in the order seen by the parser. An individual peephole
10321 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10322 // on the command-line.
10323 //
10324 // ---------CURRENT LIMITATIONS----------------------------------------------
10325 //
10326 // Only match adjacent instructions in same basic block
10327 // Only equality constraints
10328 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10329 // Only one replacement instruction
10330 //
10331 // ---------EXAMPLE----------------------------------------------------------
10332 //
10333 // // pertinent parts of existing instructions in architecture description
10334 // instruct movI(eRegI dst, eRegI src) %{
10335 //   match(Set dst (CopyI src));
10336 // %}
10337 //
10338 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10339 //   match(Set dst (AddI dst src));
10340 //   effect(KILL cr);
10341 // %}
10342 //
10343 // // Change (inc mov) to lea
10344 // peephole %{
10345 //   // increment preceeded by register-register move
10346 //   peepmatch (incI_eReg movI);
10347 //   // require that the destination register of the increment
10348 //   // match the destination register of the move
10349 //   peepconstraint (0.dst == 1.dst);
10350 //   // construct a replacement instruction that sets
10351 //   // the destination to (move's source register + one)
10352 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10353 // %}
10354 //
10355 // Implementation no longer uses movX instructions since
10356 // machine-independent system no longer uses CopyX nodes.
10357 //
10358 // peephole %{
10359 //   peepmatch (incI_eReg movI);
10360 //   peepconstraint (0.dst == 1.dst);
10361 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10362 // %}
10363 //
10364 // peephole %{
10365 //   peepmatch (decI_eReg movI);
10366 //   peepconstraint (0.dst == 1.dst);
10367 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10368 // %}
10369 //
10370 // peephole %{
10371 //   peepmatch (addI_eReg_imm movI);
10372 //   peepconstraint (0.dst == 1.dst);
10373 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10374 // %}
10375 //
10376 // peephole %{
10377 //   peepmatch (addP_eReg_imm movP);
10378 //   peepconstraint (0.dst == 1.dst);
10379 //   peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10380 // %}
10381 
10382 
10383 //  This peephole rule does not work, probably because ADLC can't handle two effects:
10384 //  Effect 1 is defining 0.op1 and effect 2 is setting CC
10385 // condense a load from memory and subsequent test for zero
10386 // into a single, more efficient ICM instruction.
10387 // peephole %{
10388 //   peepmatch (compI_iReg_imm0 loadI);
10389 //   peepconstraint (1.dst == 0.op1);
10390 //   peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10391 // %}
10392 
10393 // // Change load of spilled value to only a spill
10394 // instruct storeI(memory mem, eRegI src) %{
10395 //   match(Set mem (StoreI mem src));
10396 // %}
10397 //
10398 // instruct loadI(eRegI dst, memory mem) %{
10399 //   match(Set dst (LoadI mem));
10400 // %}
10401 //
10402 peephole %{
10403   peepmatch (loadI storeI);
10404   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10405   peepreplace (storeI(1.mem 1.mem 1.src));
10406 %}
10407 
10408 peephole %{
10409   peepmatch (loadL storeL);
10410   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10411   peepreplace (storeL(1.mem 1.mem 1.src));
10412 %}
10413 
10414 peephole %{
10415   peepmatch (loadP storeP);
10416   peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10417   peepreplace (storeP(1.dst 1.dst 1.src));
10418 %}
10419 
10420 //----------SUPERWORD RULES---------------------------------------------------
10421 
10422 //  Expand rules for special cases
10423 
10424 instruct expand_storeF(stackSlotF mem, regF src) %{
10425   // No match rule, false predicate, for expand only.
10426   effect(DEF mem, USE src);
10427   predicate(false);
10428   ins_cost(MEMORY_REF_COST);
10429   // TODO: s390 port size(FIXED_SIZE);
10430   format %{ "STE      $src,$mem\t # replicate(float2stack)" %}
10431   opcode(STE_ZOPC, STE_ZOPC);
10432   ins_encode(z_form_rt_mem(src, mem));
10433   ins_pipe(pipe_class_dummy);
10434 %}
10435 
10436 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10437   // No match rule, false predicate, for expand only.
10438   effect(DEF dst, USE mem);
10439   predicate(false);
10440   ins_cost(MEMORY_REF_COST);
10441   // TODO: s390 port size(FIXED_SIZE);
10442   format %{ "LLGF     $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10443   opcode(LLGF_ZOPC, LLGF_ZOPC);
10444   ins_encode(z_form_rt_mem(dst, mem));
10445   ins_pipe(pipe_class_dummy);
10446 %}
10447 
10448 // Replicate scalar int to packed int values (8 Bytes)
10449 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10450   // Dummy match rule, false predicate, for expand only.
10451   match(Set dst (ConvI2L src));
10452   predicate(false);
10453   ins_cost(DEFAULT_COST);
10454   // TODO: s390 port size(FIXED_SIZE);
10455   format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10456   ins_encode %{
10457     if ($dst$$Register == $src$$Register) {
10458       __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10459       __ z_ogr($dst$$Register, Z_R0_scratch);
10460     }  else {
10461       __ z_sllg($dst$$Register, $src$$Register, 64-32);
10462       __ z_ogr( $dst$$Register, $src$$Register);
10463     }
10464   %}
10465   ins_pipe(pipe_class_dummy);
10466 %}
10467 
10468 // Replication
10469 
10470 // Exploit rotate_then_insert, if available
10471 // Replicate scalar byte to packed byte values (8 Bytes).
10472 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10473   match(Set dst (ReplicateB src));
10474   effect(KILL cr);
10475   predicate((n->as_Vector()->length() == 8));
10476   format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10477   ins_encode %{
10478     if ($dst$$Register != $src$$Register) {
10479       __ z_lgr($dst$$Register, $src$$Register);
10480     }
10481     __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55,  8, false);
10482     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10483     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10484   %}
10485   ins_pipe(pipe_class_dummy);
10486 %}
10487 
10488 // Replicate scalar byte to packed byte values (8 Bytes).
10489 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10490   match(Set dst (ReplicateB src));
10491   predicate(n->as_Vector()->length() == 8);
10492   ins_should_rematerialize(true);
10493   format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10494   ins_encode %{
10495     int64_t  Isrc8 = $src$$constant & 0x000000ff;
10496     int64_t Isrc16 =  Isrc8 <<  8 |  Isrc8;
10497     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10498     assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10499 
10500     __ z_llilf($dst$$Register, Isrc32);
10501     __ z_iihf($dst$$Register, Isrc32);
10502   %}
10503   ins_pipe(pipe_class_dummy);
10504 %}
10505 
10506 // Replicate scalar byte to packed byte values (8 Bytes).
10507 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10508   match(Set dst (ReplicateB src));
10509   predicate(n->as_Vector()->length() == 8);
10510   ins_should_rematerialize(true);
10511   format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10512   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10513   ins_pipe(pipe_class_dummy);
10514 %}
10515 
10516 // Replicate scalar byte to packed byte values (8 Bytes).
10517 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10518   match(Set dst (ReplicateB src));
10519   predicate(n->as_Vector()->length() == 8);
10520   ins_should_rematerialize(true);
10521   format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10522   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10523   ins_pipe(pipe_class_dummy);
10524 %}
10525 
10526 // Exploit rotate_then_insert, if available
10527 // Replicate scalar short to packed short values (8 Bytes).
10528 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10529   match(Set dst (ReplicateS src));
10530   effect(KILL cr);
10531   predicate((n->as_Vector()->length() == 4));
10532   format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10533   ins_encode %{
10534     if ($dst$$Register != $src$$Register) {
10535       __ z_lgr($dst$$Register, $src$$Register);
10536     }
10537     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10538     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10539   %}
10540   ins_pipe(pipe_class_dummy);
10541 %}
10542 
10543 // Replicate scalar short to packed short values (8 Bytes).
10544 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10545   match(Set dst (ReplicateS src));
10546   predicate(n->as_Vector()->length() == 4);
10547   ins_should_rematerialize(true);
10548   format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10549   ins_encode %{
10550     int64_t Isrc16 = $src$$constant & 0x0000ffff;
10551     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10552     assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10553            ") should be handled by other match rules.", $src$$constant);
10554 
10555     __ z_llilf($dst$$Register, Isrc32);
10556     __ z_iihf($dst$$Register, Isrc32);
10557   %}
10558   ins_pipe(pipe_class_dummy);
10559 %}
10560 
10561 // Replicate scalar short to packed short values (8 Bytes).
10562 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10563   match(Set dst (ReplicateS src));
10564   predicate(n->as_Vector()->length() == 4);
10565   ins_should_rematerialize(true);
10566   format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10567   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10568   ins_pipe(pipe_class_dummy);
10569 %}
10570 
10571 // Replicate scalar short to packed short values (8 Bytes).
10572 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10573   match(Set dst (ReplicateS src));
10574   predicate(n->as_Vector()->length() == 4);
10575   ins_should_rematerialize(true);
10576   format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10577   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10578   ins_pipe(pipe_class_dummy);
10579 %}
10580 
10581 // Exploit rotate_then_insert, if available.
10582 // Replicate scalar int to packed int values (8 Bytes).
10583 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10584   match(Set dst (ReplicateI src));
10585   effect(KILL cr);
10586   predicate((n->as_Vector()->length() == 2));
10587   format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10588   ins_encode %{
10589     if ($dst$$Register != $src$$Register) {
10590       __ z_lgr($dst$$Register, $src$$Register);
10591     }
10592     __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10593   %}
10594   ins_pipe(pipe_class_dummy);
10595 %}
10596 
10597 // Replicate scalar int to packed int values (8 Bytes).
10598 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10599   match(Set dst (ReplicateI src));
10600   predicate(n->as_Vector()->length() == 2);
10601   ins_should_rematerialize(true);
10602   format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10603   ins_encode %{
10604     int64_t Isrc32 = $src$$constant;
10605     assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10606 
10607     __ z_llilf($dst$$Register, Isrc32);
10608     __ z_iihf($dst$$Register, Isrc32);
10609   %}
10610   ins_pipe(pipe_class_dummy);
10611 %}
10612 
10613 // Replicate scalar int to packed int values (8 Bytes).
10614 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
10615   match(Set dst (ReplicateI src));
10616   predicate(n->as_Vector()->length() == 2);
10617   ins_should_rematerialize(true);
10618   format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
10619   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10620   ins_pipe(pipe_class_dummy);
10621 %}
10622 
10623 // Replicate scalar int to packed int values (8 Bytes).
10624 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
10625   match(Set dst (ReplicateI src));
10626   predicate(n->as_Vector()->length() == 2);
10627   ins_should_rematerialize(true);
10628   format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
10629   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10630   ins_pipe(pipe_class_dummy);
10631 %}
10632 
10633 //
10634 
10635 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
10636   match(Set dst (ReplicateF src));
10637   effect(KILL cr);
10638   predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10639   format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
10640   expand %{
10641     stackSlotF tmp;
10642     iRegL      tmp2;
10643     expand_storeF(tmp, src);
10644     expand_LoadLogical_I2L(tmp2, tmp);
10645     expand_Repl2I_reg(dst, tmp2);
10646   %}
10647 %}
10648 
10649 // Replicate scalar float to packed float values in GREG (8 Bytes).
10650 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
10651   match(Set dst (ReplicateF src));
10652   effect(KILL cr);
10653   predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10654   format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
10655   ins_encode %{
10656     assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
10657     __ z_lgdr($dst$$Register, $src$$FloatRegister);
10658 
10659     __ z_srlg(Z_R0_scratch, $dst$$Register, 32);  // Floats are left-justified in 64bit reg.
10660     __ z_iilf($dst$$Register, 0);                 // Save a "result not ready" stall.
10661     __ z_ogr($dst$$Register, Z_R0_scratch);
10662   %}
10663   ins_pipe(pipe_class_dummy);
10664 %}
10665 
10666 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
10667 instruct Repl2F_imm(iRegL dst, immF src) %{
10668   match(Set dst (ReplicateF src));
10669   predicate(n->as_Vector()->length() == 2);
10670   ins_should_rematerialize(true);
10671   format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
10672   ins_encode %{
10673     union {
10674       int   Isrc32;
10675       float Fsrc32;
10676     };
10677     Fsrc32 = $src$$constant;
10678     __ z_llilf($dst$$Register, Isrc32);
10679     __ z_iihf($dst$$Register, Isrc32);
10680   %}
10681   ins_pipe(pipe_class_dummy);
10682 %}
10683 
10684 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
10685 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
10686 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
10687   match(Set dst (ReplicateF src));
10688   predicate(n->as_Vector()->length() == 2);
10689   ins_should_rematerialize(true);
10690   format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
10691   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10692   ins_pipe(pipe_class_dummy);
10693 %}
10694 
10695 // Store
10696 
10697 // Store Aligned Packed Byte register to memory (8 Bytes).
10698 instruct storeA8B(memory mem, iRegL src) %{
10699   match(Set mem (StoreVector mem src));
10700   predicate(n->as_StoreVector()->memory_size() == 8);
10701   ins_cost(MEMORY_REF_COST);
10702   // TODO: s390 port size(VARIABLE_SIZE);
10703   format %{ "STG     $src,$mem\t # ST(packed8B)" %}
10704   opcode(STG_ZOPC, STG_ZOPC);
10705   ins_encode(z_form_rt_mem_opt(src, mem));
10706   ins_pipe(pipe_class_dummy);
10707 %}
10708 
10709 // Load
10710 
10711 instruct loadV8(iRegL dst, memory mem) %{
10712   match(Set dst (LoadVector mem));
10713   predicate(n->as_LoadVector()->memory_size() == 8);
10714   ins_cost(MEMORY_REF_COST);
10715   // TODO: s390 port size(VARIABLE_SIZE);
10716   format %{ "LG      $dst,$mem\t # L(packed8B)" %}
10717   opcode(LG_ZOPC, LG_ZOPC);
10718   ins_encode(z_form_rt_mem_opt(dst, mem));
10719   ins_pipe(pipe_class_dummy);
10720 %}
10721 
10722 //----------POPULATION COUNT RULES--------------------------------------------
10723 
10724 // Byte reverse
10725 
10726 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
10727   match(Set dst (ReverseBytesI src));
10728   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10729   ins_cost(DEFAULT_COST);
10730   size(4);
10731   format %{ "LRVR    $dst,$src\t# byte reverse int" %}
10732   opcode(LRVR_ZOPC);
10733   ins_encode(z_rreform(dst, src));
10734   ins_pipe(pipe_class_dummy);
10735 %}
10736 
10737 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
10738   match(Set dst (ReverseBytesL src));
10739   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10740   ins_cost(DEFAULT_COST);
10741   // TODO: s390 port size(FIXED_SIZE);
10742   format %{ "LRVGR   $dst,$src\t# byte reverse long" %}
10743   opcode(LRVGR_ZOPC);
10744   ins_encode(z_rreform(dst, src));
10745   ins_pipe(pipe_class_dummy);
10746 %}
10747 
10748 // Leading zeroes
10749 
10750 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
10751 // returns the bit position of the leftmost 1 in the 64bit source register.
10752 // As the bits are numbered from left to right (0..63), the returned
10753 // position index is equivalent to the number of leading zeroes.
10754 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction
10755 // returns position 64. That's exactly what we need.
10756 
10757 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10758   match(Set dst (CountLeadingZerosI src));
10759   effect(KILL tmp, KILL cr);
10760   ins_cost(3 * DEFAULT_COST);
10761   size(14);
10762   format %{ "SLLG    $dst,$src,32\t# no need to always count 32 zeroes first\n\t"
10763             "IILH    $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t"
10764             "FLOGR   $dst,$dst"
10765          %}
10766   ins_encode %{
10767     // Performance experiments indicate that "FLOGR" is using some kind of
10768     // iteration to find the leftmost "1" bit.
10769     //
10770     // The prior implementation zero-extended the 32-bit argument to 64 bit,
10771     // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
10772     // We could gain measurable speedup in micro benchmark:
10773     //
10774     //               leading   trailing
10775     //   z10:   int     2.04       1.68
10776     //         long     1.00       1.02
10777     //   z196:  int     0.99       1.23
10778     //         long     1.00       1.11
10779     //
10780     // By shifting the argument into the high-word instead of zero-extending it.
10781     // The add'l branch on condition (taken for a zero argument, very infrequent,
10782     // good prediction) is well compensated for by the savings.
10783     //
10784     // We leave the previous implementation in for some time in the future when
10785     // the "FLOGR" instruction may become less iterative.
10786 
10787     // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
10788     __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
10789     __ z_iilh($dst$$Register, 0x8000);   // Insert "stop bit" to force result 32 for zero src.
10790     __ z_flogr($dst$$Register, $dst$$Register);
10791   %}
10792   ins_pipe(pipe_class_dummy);
10793 %}
10794 
10795 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
10796   match(Set dst (CountLeadingZerosL src));
10797   effect(KILL tmp, KILL cr);
10798   ins_cost(DEFAULT_COST);
10799   size(4);
10800   format %{ "FLOGR   $dst,$src \t# count leading zeros (long)\n\t" %}
10801   ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
10802   ins_pipe(pipe_class_dummy);
10803 %}
10804 
10805 // trailing zeroes
10806 
10807 // We transform the trailing zeroes problem to a leading zeroes problem
10808 // such that can use the FLOGR instruction to our advantage.
10809 
10810 // With
10811 //   tmp1 = src - 1
10812 // we flip all trailing zeroes to ones and the rightmost one to zero.
10813 // All other bits remain unchanged.
10814 // With the complement
10815 //   tmp2 = ~src
10816 // we get all ones in the trailing zeroes positions. Thus,
10817 //   tmp3 = tmp1 & tmp2
10818 // yields ones in the trailing zeroes positions and zeroes elsewhere.
10819 // Now we can apply FLOGR and get 64-(trailing zeroes).
10820 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10821   match(Set dst (CountTrailingZerosI src));
10822   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10823   ins_cost(8 * DEFAULT_COST);
10824   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10825   format %{ "LLGFR   $dst,$src  \t# clear upper 32 bits (we are dealing with int)\n\t"
10826             "LCGFR   $tmp,$src  \t# load 2's complement (32->64 bit)\n\t"
10827             "AGHI    $dst,-1    \t# tmp1 = src-1\n\t"
10828             "AGHI    $tmp,-1    \t# tmp2 = -src-1 = ~src\n\t"
10829             "NGR     $dst,$tmp  \t# tmp3 = tmp1&tmp2\n\t"
10830             "FLOGR   $dst,$dst  \t# count trailing zeros (int)\n\t"
10831             "AHI     $dst,-64   \t# tmp4 = 64-(trailing zeroes)-64\n\t"
10832             "LCR     $dst,$dst  \t# res = -tmp4"
10833          %}
10834   ins_encode %{
10835     Register Rdst = $dst$$Register;
10836     Register Rsrc = $src$$Register;
10837     // Rtmp only needed for for zero-argument shortcut. With kill effect in
10838     // match rule Rsrc = roddReg would be possible, saving one register.
10839     Register Rtmp = $tmp$$Register;
10840 
10841     assert_different_registers(Rdst, Rsrc, Rtmp);
10842 
10843     // Algorithm:
10844     // - Isolate the least significant (rightmost) set bit using (src & (-src)).
10845     //   All other bits in the result are zero.
10846     // - Find the "leftmost one" bit position in the single-bit result from previous step.
10847     // - 63-("leftmost one" bit position) gives the # of trailing zeros.
10848 
10849     // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
10850     Label done;
10851     __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
10852     __ z_lcgfr(Rtmp, Rsrc);
10853     __ z_bre(done);                    // Taken very infrequently, good prediction, no BHT entry.
10854 
10855     __ z_nr(Rtmp, Rsrc);               // (src) & (-src) leaves nothing but least significant bit.
10856     __ z_ahi(Rtmp,  -1);               // Subtract one to fill all trailing zero positions with ones.
10857                                        // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
10858                                        // into upper half of reg. Not relevant with sllg below.
10859     __ z_sllg(Rdst, Rtmp, 32);         // Shift interesting contents to upper half of register.
10860     __ z_bre(done);                    // Shortcut for argument = 1, result will be 0.
10861                                        // Depends on CC set by ahi above.
10862                                        // Taken very infrequently, good prediction, no BHT entry.
10863                                        // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
10864                                        // after SLLG Rdst == 0(64bit)).
10865     __ z_flogr(Rdst, Rdst);            // Kills tmp which is the oddReg for dst.
10866     __ add2reg(Rdst,  -32);            // 32-pos(leftmost1) is #trailing zeros
10867     __ z_lcgfr(Rdst, Rdst);            // Provide 64bit result at no cost.
10868     __ bind(done);
10869   %}
10870   ins_pipe(pipe_class_dummy);
10871 %}
10872 
10873 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
10874   match(Set dst (CountTrailingZerosL src));
10875   effect(TEMP_DEF dst, KILL tmp, KILL cr);
10876   ins_cost(8 * DEFAULT_COST);
10877   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10878   format %{ "LCGR    $dst,$src  \t# preserve src\n\t"
10879             "NGR     $dst,$src  \t#"
10880             "AGHI    $dst,-1    \t# tmp1 = src-1\n\t"
10881             "FLOGR   $dst,$dst  \t# count trailing zeros (long), kill $tmp\n\t"
10882             "AHI     $dst,-64   \t# tmp4 = 64-(trailing zeroes)-64\n\t"
10883             "LCR     $dst,$dst  \t#"
10884          %}
10885   ins_encode %{
10886     Register Rdst = $dst$$Register;
10887     Register Rsrc = $src$$Register;
10888     assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
10889 
10890     // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
10891     __ z_lcgr(Rdst, Rsrc);
10892     __ z_ngr(Rdst, Rsrc);
10893     __ add2reg(Rdst,   -1);
10894     __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10895     __ add2reg(Rdst,  -64);
10896     __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10897   %}
10898   ins_pipe(pipe_class_dummy);
10899 %}
10900 
10901 
10902 // bit count
10903 
10904 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10905   match(Set dst (PopCountI src));
10906   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10907   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10908   ins_cost(DEFAULT_COST);
10909   size(24);
10910   format %{ "POPCNT  $dst,$src\t# pop count int" %}
10911   ins_encode %{
10912     Register Rdst = $dst$$Register;
10913     Register Rsrc = $src$$Register;
10914     Register Rtmp = $tmp$$Register;
10915 
10916     // Prefer compile-time assertion over run-time SIGILL.
10917     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10918     assert_different_registers(Rdst, Rtmp);
10919 
10920     // Version 2: shows 10%(z196) improvement over original.
10921     __ z_popcnt(Rdst, Rsrc);
10922     __ z_srlg(Rtmp, Rdst, 16); // calc  byte4+byte6 and byte5+byte7
10923     __ z_alr(Rdst, Rtmp);      //   into byte6 and byte7
10924     __ z_srlg(Rtmp, Rdst,  8); // calc (byte4+byte6) + (byte5+byte7)
10925     __ z_alr(Rdst, Rtmp);      //   into byte7
10926     __ z_llgcr(Rdst, Rdst);    // zero-extend sum
10927   %}
10928   ins_pipe(pipe_class_dummy);
10929 %}
10930 
10931 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
10932   match(Set dst (PopCountL src));
10933   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10934   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10935   ins_cost(DEFAULT_COST);
10936   // TODO: s390 port size(FIXED_SIZE);
10937   format %{ "POPCNT  $dst,$src\t# pop count long" %}
10938   ins_encode %{
10939     Register Rdst = $dst$$Register;
10940     Register Rsrc = $src$$Register;
10941     Register Rtmp = $tmp$$Register;
10942 
10943     // Prefer compile-time assertion over run-time SIGILL.
10944     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10945     assert_different_registers(Rdst, Rtmp);
10946 
10947     // Original version. Using LA instead of algr seems to be a really bad idea (-35%).
10948     __ z_popcnt(Rdst, Rsrc);
10949     __ z_ahhlr(Rdst, Rdst, Rdst);
10950     __ z_sllg(Rtmp, Rdst, 16);
10951     __ z_algr(Rdst, Rtmp);
10952     __ z_sllg(Rtmp, Rdst,  8);
10953     __ z_algr(Rdst, Rtmp);
10954     __ z_srlg(Rdst, Rdst, 56);
10955   %}
10956   ins_pipe(pipe_class_dummy);
10957 %}
10958 
10959 //----------SMARTSPILL RULES---------------------------------------------------
10960 // These must follow all instruction definitions as they use the names
10961 // defined in the instructions definitions.
10962 
10963 // ============================================================================
10964 // TYPE PROFILING RULES
10965