1 /* 2 * Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "c1/c1_Defs.hpp" 28 #include "c1/c1_MacroAssembler.hpp" 29 #include "c1/c1_Runtime1.hpp" 30 #include "ci/ciUtilities.hpp" 31 #include "gc/shared/cardTable.hpp" 32 #include "gc/shared/cardTableBarrierSet.hpp" 33 #include "interpreter/interpreter.hpp" 34 #include "nativeInst_x86.hpp" 35 #include "oops/compiledICHolder.hpp" 36 #include "oops/oop.inline.hpp" 37 #include "prims/jvmtiExport.hpp" 38 #include "register_x86.hpp" 39 #include "runtime/sharedRuntime.hpp" 40 #include "runtime/signature.hpp" 41 #include "runtime/vframeArray.hpp" 42 #include "utilities/macros.hpp" 43 #include "vmreg_x86.inline.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1BarrierSet.hpp" 46 #include "gc/g1/g1CardTable.hpp" 47 #include "gc/g1/g1ThreadLocalData.hpp" 48 #endif 49 50 51 // Implementation of StubAssembler 52 53 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) { 54 // setup registers 55 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions) 56 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different"); 57 assert(oop_result1 != thread && metadata_result != thread, "registers must be different"); 58 assert(args_size >= 0, "illegal args_size"); 59 bool align_stack = false; 60 #ifdef _LP64 61 // At a method handle call, the stack may not be properly aligned 62 // when returning with an exception. 63 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id); 64 #endif 65 66 #ifdef _LP64 67 mov(c_rarg0, thread); 68 set_num_rt_args(0); // Nothing on stack 69 #else 70 set_num_rt_args(1 + args_size); 71 72 // push java thread (becomes first argument of C function) 73 get_thread(thread); 74 push(thread); 75 #endif // _LP64 76 77 int call_offset; 78 if (!align_stack) { 79 set_last_Java_frame(thread, noreg, rbp, NULL); 80 } else { 81 address the_pc = pc(); 82 call_offset = offset(); 83 set_last_Java_frame(thread, noreg, rbp, the_pc); 84 andptr(rsp, -(StackAlignmentInBytes)); // Align stack 85 } 86 87 // do the call 88 call(RuntimeAddress(entry)); 89 if (!align_stack) { 90 call_offset = offset(); 91 } 92 // verify callee-saved register 93 #ifdef ASSERT 94 guarantee(thread != rax, "change this code"); 95 push(rax); 96 { Label L; 97 get_thread(rax); 98 cmpptr(thread, rax); 99 jcc(Assembler::equal, L); 100 int3(); 101 stop("StubAssembler::call_RT: rdi not callee saved?"); 102 bind(L); 103 } 104 pop(rax); 105 #endif 106 reset_last_Java_frame(thread, true); 107 108 // discard thread and arguments 109 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord)); 110 111 // check for pending exceptions 112 { Label L; 113 cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 114 jcc(Assembler::equal, L); 115 // exception pending => remove activation and forward to exception handler 116 movptr(rax, Address(thread, Thread::pending_exception_offset())); 117 // make sure that the vm_results are cleared 118 if (oop_result1->is_valid()) { 119 movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD); 120 } 121 if (metadata_result->is_valid()) { 122 movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD); 123 } 124 if (frame_size() == no_frame_size) { 125 leave(); 126 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 127 } else if (_stub_id == Runtime1::forward_exception_id) { 128 should_not_reach_here(); 129 } else { 130 jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id))); 131 } 132 bind(L); 133 } 134 // get oop results if there are any and reset the values in the thread 135 if (oop_result1->is_valid()) { 136 get_vm_result(oop_result1, thread); 137 } 138 if (metadata_result->is_valid()) { 139 get_vm_result_2(metadata_result, thread); 140 } 141 return call_offset; 142 } 143 144 145 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) { 146 #ifdef _LP64 147 mov(c_rarg1, arg1); 148 #else 149 push(arg1); 150 #endif // _LP64 151 return call_RT(oop_result1, metadata_result, entry, 1); 152 } 153 154 155 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) { 156 #ifdef _LP64 157 if (c_rarg1 == arg2) { 158 if (c_rarg2 == arg1) { 159 xchgq(arg1, arg2); 160 } else { 161 mov(c_rarg2, arg2); 162 mov(c_rarg1, arg1); 163 } 164 } else { 165 mov(c_rarg1, arg1); 166 mov(c_rarg2, arg2); 167 } 168 #else 169 push(arg2); 170 push(arg1); 171 #endif // _LP64 172 return call_RT(oop_result1, metadata_result, entry, 2); 173 } 174 175 176 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) { 177 #ifdef _LP64 178 // if there is any conflict use the stack 179 if (arg1 == c_rarg2 || arg1 == c_rarg3 || 180 arg2 == c_rarg1 || arg1 == c_rarg3 || 181 arg3 == c_rarg1 || arg1 == c_rarg2) { 182 push(arg3); 183 push(arg2); 184 push(arg1); 185 pop(c_rarg1); 186 pop(c_rarg2); 187 pop(c_rarg3); 188 } else { 189 mov(c_rarg1, arg1); 190 mov(c_rarg2, arg2); 191 mov(c_rarg3, arg3); 192 } 193 #else 194 push(arg3); 195 push(arg2); 196 push(arg1); 197 #endif // _LP64 198 return call_RT(oop_result1, metadata_result, entry, 3); 199 } 200 201 202 // Implementation of StubFrame 203 204 class StubFrame: public StackObj { 205 private: 206 StubAssembler* _sasm; 207 208 public: 209 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments); 210 void load_argument(int offset_in_words, Register reg); 211 212 ~StubFrame(); 213 }; 214 215 216 #define __ _sasm-> 217 218 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) { 219 _sasm = sasm; 220 __ set_info(name, must_gc_arguments); 221 __ enter(); 222 } 223 224 // load parameters that were stored with LIR_Assembler::store_parameter 225 // Note: offsets for store_parameter and load_argument must match 226 void StubFrame::load_argument(int offset_in_words, Register reg) { 227 // rbp, + 0: link 228 // + 1: return address 229 // + 2: argument with offset 0 230 // + 3: argument with offset 1 231 // + 4: ... 232 233 __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord)); 234 } 235 236 237 StubFrame::~StubFrame() { 238 __ leave(); 239 __ ret(0); 240 } 241 242 #undef __ 243 244 245 // Implementation of Runtime1 246 247 #define __ sasm-> 248 249 const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2; 250 const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2; 251 252 // Stack layout for saving/restoring all the registers needed during a runtime 253 // call (this includes deoptimization) 254 // Note: note that users of this frame may well have arguments to some runtime 255 // while these values are on the stack. These positions neglect those arguments 256 // but the code in save_live_registers will take the argument count into 257 // account. 258 // 259 #ifdef _LP64 260 #define SLOT2(x) x, 261 #define SLOT_PER_WORD 2 262 #else 263 #define SLOT2(x) 264 #define SLOT_PER_WORD 1 265 #endif // _LP64 266 267 enum reg_save_layout { 268 // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that 269 // happen and will assert if the stack size we create is misaligned 270 #ifdef _LP64 271 align_dummy_0, align_dummy_1, 272 #endif // _LP64 273 #ifdef _WIN64 274 // Windows always allocates space for it's argument registers (see 275 // frame::arg_reg_save_area_bytes). 276 arg_reg_save_1, arg_reg_save_1H, // 0, 4 277 arg_reg_save_2, arg_reg_save_2H, // 8, 12 278 arg_reg_save_3, arg_reg_save_3H, // 16, 20 279 arg_reg_save_4, arg_reg_save_4H, // 24, 28 280 #endif // _WIN64 281 xmm_regs_as_doubles_off, // 32 282 float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160 283 fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224 284 // fpu_state_end_off is exclusive 285 fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352 286 marker = fpu_state_end_off, SLOT2(markerH) // 352, 356 287 extra_space_offset, // 360 288 #ifdef _LP64 289 r15_off = extra_space_offset, r15H_off, // 360, 364 290 r14_off, r14H_off, // 368, 372 291 r13_off, r13H_off, // 376, 380 292 r12_off, r12H_off, // 384, 388 293 r11_off, r11H_off, // 392, 396 294 r10_off, r10H_off, // 400, 404 295 r9_off, r9H_off, // 408, 412 296 r8_off, r8H_off, // 416, 420 297 rdi_off, rdiH_off, // 424, 428 298 #else 299 rdi_off = extra_space_offset, 300 #endif // _LP64 301 rsi_off, SLOT2(rsiH_off) // 432, 436 302 rbp_off, SLOT2(rbpH_off) // 440, 444 303 rsp_off, SLOT2(rspH_off) // 448, 452 304 rbx_off, SLOT2(rbxH_off) // 456, 460 305 rdx_off, SLOT2(rdxH_off) // 464, 468 306 rcx_off, SLOT2(rcxH_off) // 472, 476 307 rax_off, SLOT2(raxH_off) // 480, 484 308 saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492 309 return_off, SLOT2(returnH_off) // 496, 500 310 reg_save_frame_size // As noted: neglects any parameters to runtime // 504 311 }; 312 313 314 315 // Save off registers which might be killed by calls into the runtime. 316 // Tries to smart of about FP registers. In particular we separate 317 // saving and describing the FPU registers for deoptimization since we 318 // have to save the FPU registers twice if we describe them and on P4 319 // saving FPU registers which don't contain anything appears 320 // expensive. The deopt blob is the only thing which needs to 321 // describe FPU registers. In all other cases it should be sufficient 322 // to simply save their current value. 323 324 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args, 325 bool save_fpu_registers = true) { 326 327 // In 64bit all the args are in regs so there are no additional stack slots 328 LP64_ONLY(num_rt_args = 0); 329 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");) 330 int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread 331 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word); 332 333 // record saved value locations in an OopMap 334 // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread 335 OopMap* map = new OopMap(frame_size_in_slots, 0); 336 map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg()); 337 map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg()); 338 map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg()); 339 map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg()); 340 map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg()); 341 map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg()); 342 #ifdef _LP64 343 map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg()); 344 map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg()); 345 map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg()); 346 map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg()); 347 map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg()); 348 map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg()); 349 map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg()); 350 map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg()); 351 352 // This is stupid but needed. 353 map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next()); 354 map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next()); 355 map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next()); 356 map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next()); 357 map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next()); 358 map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next()); 359 360 map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next()); 361 map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next()); 362 map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next()); 363 map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next()); 364 map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next()); 365 map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next()); 366 map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next()); 367 map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next()); 368 #endif // _LP64 369 370 int xmm_bypass_limit = FrameMap::nof_xmm_regs; 371 #ifdef _LP64 372 if (UseAVX < 3) { 373 xmm_bypass_limit = xmm_bypass_limit / 2; 374 } 375 #endif 376 377 if (save_fpu_registers) { 378 if (UseSSE < 2) { 379 int fpu_off = float_regs_as_doubles_off; 380 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 381 VMReg fpu_name_0 = FrameMap::fpu_regname(n); 382 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0); 383 // %%% This is really a waste but we'll keep things as they were for now 384 if (true) { 385 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next()); 386 } 387 fpu_off += 2; 388 } 389 assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots"); 390 } 391 392 if (UseSSE >= 2) { 393 int xmm_off = xmm_regs_as_doubles_off; 394 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) { 395 if (n < xmm_bypass_limit) { 396 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg(); 397 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0); 398 // %%% This is really a waste but we'll keep things as they were for now 399 if (true) { 400 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next()); 401 } 402 } 403 xmm_off += 2; 404 } 405 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers"); 406 407 } else if (UseSSE == 1) { 408 int xmm_off = xmm_regs_as_doubles_off; 409 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 410 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg(); 411 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0); 412 xmm_off += 2; 413 } 414 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers"); 415 } 416 } 417 418 return map; 419 } 420 421 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args, 422 bool save_fpu_registers = true) { 423 __ block_comment("save_live_registers"); 424 425 __ pusha(); // integer registers 426 427 // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset"); 428 // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset"); 429 430 __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size); 431 432 #ifdef ASSERT 433 __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef); 434 #endif 435 436 if (save_fpu_registers) { 437 if (UseSSE < 2) { 438 // save FPU stack 439 __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); 440 __ fwait(); 441 442 #ifdef ASSERT 443 Label ok; 444 __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std()); 445 __ jccb(Assembler::equal, ok); 446 __ stop("corrupted control word detected"); 447 __ bind(ok); 448 #endif 449 450 // Reset the control word to guard against exceptions being unmasked 451 // since fstp_d can cause FPU stack underflow exceptions. Write it 452 // into the on stack copy and then reload that to make sure that the 453 // current and future values are correct. 454 __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std()); 455 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); 456 457 // Save the FPU registers in de-opt-able form 458 int offset = 0; 459 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 460 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset)); 461 offset += 8; 462 } 463 } 464 465 if (UseSSE >= 2) { 466 // save XMM registers 467 // XMM registers can contain float or double values, but this is not known here, 468 // so always save them as doubles. 469 // note that float values are _not_ converted automatically, so for float values 470 // the second word contains only garbage data. 471 int xmm_bypass_limit = FrameMap::nof_xmm_regs; 472 int offset = 0; 473 #ifdef _LP64 474 if (UseAVX < 3) { 475 xmm_bypass_limit = xmm_bypass_limit / 2; 476 } 477 #endif 478 for (int n = 0; n < xmm_bypass_limit; n++) { 479 XMMRegister xmm_name = as_XMMRegister(n); 480 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name); 481 offset += 8; 482 } 483 } else if (UseSSE == 1) { 484 // save XMM registers as float because double not supported without SSE2(num MMX == num fpu) 485 int offset = 0; 486 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 487 XMMRegister xmm_name = as_XMMRegister(n); 488 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name); 489 offset += 8; 490 } 491 } 492 } 493 494 // FPU stack must be empty now 495 __ verify_FPU(0, "save_live_registers"); 496 497 return generate_oop_map(sasm, num_rt_args, save_fpu_registers); 498 } 499 500 501 static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) { 502 if (restore_fpu_registers) { 503 if (UseSSE >= 2) { 504 // restore XMM registers 505 int xmm_bypass_limit = FrameMap::nof_xmm_regs; 506 #ifdef _LP64 507 if (UseAVX < 3) { 508 xmm_bypass_limit = xmm_bypass_limit / 2; 509 } 510 #endif 511 int offset = 0; 512 for (int n = 0; n < xmm_bypass_limit; n++) { 513 XMMRegister xmm_name = as_XMMRegister(n); 514 __ movdbl(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset)); 515 offset += 8; 516 } 517 } else if (UseSSE == 1) { 518 // restore XMM registers(num MMX == num fpu) 519 int offset = 0; 520 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 521 XMMRegister xmm_name = as_XMMRegister(n); 522 __ movflt(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset)); 523 offset += 8; 524 } 525 } 526 527 if (UseSSE < 2) { 528 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); 529 } else { 530 // check that FPU stack is really empty 531 __ verify_FPU(0, "restore_live_registers"); 532 } 533 534 } else { 535 // check that FPU stack is really empty 536 __ verify_FPU(0, "restore_live_registers"); 537 } 538 539 #ifdef ASSERT 540 { 541 Label ok; 542 __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef); 543 __ jcc(Assembler::equal, ok); 544 __ stop("bad offsets in frame"); 545 __ bind(ok); 546 } 547 #endif // ASSERT 548 549 __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size); 550 } 551 552 553 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) { 554 __ block_comment("restore_live_registers"); 555 556 restore_fpu(sasm, restore_fpu_registers); 557 __ popa(); 558 } 559 560 561 static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) { 562 __ block_comment("restore_live_registers_except_rax"); 563 564 restore_fpu(sasm, restore_fpu_registers); 565 566 #ifdef _LP64 567 __ movptr(r15, Address(rsp, 0)); 568 __ movptr(r14, Address(rsp, wordSize)); 569 __ movptr(r13, Address(rsp, 2 * wordSize)); 570 __ movptr(r12, Address(rsp, 3 * wordSize)); 571 __ movptr(r11, Address(rsp, 4 * wordSize)); 572 __ movptr(r10, Address(rsp, 5 * wordSize)); 573 __ movptr(r9, Address(rsp, 6 * wordSize)); 574 __ movptr(r8, Address(rsp, 7 * wordSize)); 575 __ movptr(rdi, Address(rsp, 8 * wordSize)); 576 __ movptr(rsi, Address(rsp, 9 * wordSize)); 577 __ movptr(rbp, Address(rsp, 10 * wordSize)); 578 // skip rsp 579 __ movptr(rbx, Address(rsp, 12 * wordSize)); 580 __ movptr(rdx, Address(rsp, 13 * wordSize)); 581 __ movptr(rcx, Address(rsp, 14 * wordSize)); 582 583 __ addptr(rsp, 16 * wordSize); 584 #else 585 586 __ pop(rdi); 587 __ pop(rsi); 588 __ pop(rbp); 589 __ pop(rbx); // skip this value 590 __ pop(rbx); 591 __ pop(rdx); 592 __ pop(rcx); 593 __ addptr(rsp, BytesPerWord); 594 #endif // _LP64 595 } 596 597 598 void Runtime1::initialize_pd() { 599 // nothing to do 600 } 601 602 603 // Target: the entry point of the method that creates and posts the exception oop. 604 // has_argument: true if the exception needs arguments (passed on the stack because 605 // registers must be preserved). 606 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) { 607 // Preserve all registers. 608 int num_rt_args = has_argument ? (2 + 1) : 1; 609 OopMap* oop_map = save_live_registers(sasm, num_rt_args); 610 611 // Now all registers are saved and can be used freely. 612 // Verify that no old value is used accidentally. 613 __ invalidate_registers(true, true, true, true, true, true); 614 615 // Registers used by this stub. 616 const Register temp_reg = rbx; 617 618 // Load arguments for exception that are passed as arguments into the stub. 619 if (has_argument) { 620 #ifdef _LP64 621 __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord)); 622 __ movptr(c_rarg2, Address(rbp, 3*BytesPerWord)); 623 #else 624 __ movptr(temp_reg, Address(rbp, 3*BytesPerWord)); 625 __ push(temp_reg); 626 __ movptr(temp_reg, Address(rbp, 2*BytesPerWord)); 627 __ push(temp_reg); 628 #endif // _LP64 629 } 630 int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1); 631 632 OopMapSet* oop_maps = new OopMapSet(); 633 oop_maps->add_gc_map(call_offset, oop_map); 634 635 __ stop("should not reach here"); 636 637 return oop_maps; 638 } 639 640 641 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) { 642 __ block_comment("generate_handle_exception"); 643 644 // incoming parameters 645 const Register exception_oop = rax; 646 const Register exception_pc = rdx; 647 // other registers used in this stub 648 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); 649 650 // Save registers, if required. 651 OopMapSet* oop_maps = new OopMapSet(); 652 OopMap* oop_map = NULL; 653 switch (id) { 654 case forward_exception_id: 655 // We're handling an exception in the context of a compiled frame. 656 // The registers have been saved in the standard places. Perform 657 // an exception lookup in the caller and dispatch to the handler 658 // if found. Otherwise unwind and dispatch to the callers 659 // exception handler. 660 oop_map = generate_oop_map(sasm, 1 /*thread*/); 661 662 // load and clear pending exception oop into RAX 663 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset())); 664 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD); 665 666 // load issuing PC (the return address for this stub) into rdx 667 __ movptr(exception_pc, Address(rbp, 1*BytesPerWord)); 668 669 // make sure that the vm_results are cleared (may be unnecessary) 670 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD); 671 __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD); 672 break; 673 case handle_exception_nofpu_id: 674 case handle_exception_id: 675 // At this point all registers MAY be live. 676 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id); 677 break; 678 case handle_exception_from_callee_id: { 679 // At this point all registers except exception oop (RAX) and 680 // exception pc (RDX) are dead. 681 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord); 682 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0); 683 sasm->set_frame_size(frame_size); 684 WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes)); 685 break; 686 } 687 default: ShouldNotReachHere(); 688 } 689 690 #ifdef TIERED 691 // C2 can leave the fpu stack dirty 692 if (UseSSE < 2) { 693 __ empty_FPU_stack(); 694 } 695 #endif // TIERED 696 697 // verify that only rax, and rdx is valid at this time 698 __ invalidate_registers(false, true, true, false, true, true); 699 // verify that rax, contains a valid exception 700 __ verify_not_null_oop(exception_oop); 701 702 // load address of JavaThread object for thread-local data 703 NOT_LP64(__ get_thread(thread);) 704 705 #ifdef ASSERT 706 // check that fields in JavaThread for exception oop and issuing pc are 707 // empty before writing to them 708 Label oop_empty; 709 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD); 710 __ jcc(Assembler::equal, oop_empty); 711 __ stop("exception oop already set"); 712 __ bind(oop_empty); 713 714 Label pc_empty; 715 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0); 716 __ jcc(Assembler::equal, pc_empty); 717 __ stop("exception pc already set"); 718 __ bind(pc_empty); 719 #endif 720 721 // save exception oop and issuing pc into JavaThread 722 // (exception handler will load it from here) 723 __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop); 724 __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc); 725 726 // patch throwing pc into return address (has bci & oop map) 727 __ movptr(Address(rbp, 1*BytesPerWord), exception_pc); 728 729 // compute the exception handler. 730 // the exception oop and the throwing pc are read from the fields in JavaThread 731 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc)); 732 oop_maps->add_gc_map(call_offset, oop_map); 733 734 // rax: handler address 735 // will be the deopt blob if nmethod was deoptimized while we looked up 736 // handler regardless of whether handler existed in the nmethod. 737 738 // only rax, is valid at this time, all other registers have been destroyed by the runtime call 739 __ invalidate_registers(false, true, true, true, true, true); 740 741 // patch the return address, this stub will directly return to the exception handler 742 __ movptr(Address(rbp, 1*BytesPerWord), rax); 743 744 switch (id) { 745 case forward_exception_id: 746 case handle_exception_nofpu_id: 747 case handle_exception_id: 748 // Restore the registers that were saved at the beginning. 749 restore_live_registers(sasm, id != handle_exception_nofpu_id); 750 break; 751 case handle_exception_from_callee_id: 752 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP 753 // since we do a leave anyway. 754 755 // Pop the return address. 756 __ leave(); 757 __ pop(rcx); 758 __ jmp(rcx); // jump to exception handler 759 break; 760 default: ShouldNotReachHere(); 761 } 762 763 return oop_maps; 764 } 765 766 767 void Runtime1::generate_unwind_exception(StubAssembler *sasm) { 768 // incoming parameters 769 const Register exception_oop = rax; 770 // callee-saved copy of exception_oop during runtime call 771 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14); 772 // other registers used in this stub 773 const Register exception_pc = rdx; 774 const Register handler_addr = rbx; 775 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); 776 777 // verify that only rax, is valid at this time 778 __ invalidate_registers(false, true, true, true, true, true); 779 780 #ifdef ASSERT 781 // check that fields in JavaThread for exception oop and issuing pc are empty 782 NOT_LP64(__ get_thread(thread);) 783 Label oop_empty; 784 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0); 785 __ jcc(Assembler::equal, oop_empty); 786 __ stop("exception oop must be empty"); 787 __ bind(oop_empty); 788 789 Label pc_empty; 790 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0); 791 __ jcc(Assembler::equal, pc_empty); 792 __ stop("exception pc must be empty"); 793 __ bind(pc_empty); 794 #endif 795 796 // clear the FPU stack in case any FPU results are left behind 797 __ empty_FPU_stack(); 798 799 // save exception_oop in callee-saved register to preserve it during runtime calls 800 __ verify_not_null_oop(exception_oop); 801 __ movptr(exception_oop_callee_saved, exception_oop); 802 803 NOT_LP64(__ get_thread(thread);) 804 // Get return address (is on top of stack after leave). 805 __ movptr(exception_pc, Address(rsp, 0)); 806 807 // search the exception handler address of the caller (using the return address) 808 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc); 809 // rax: exception handler address of the caller 810 811 // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call. 812 __ invalidate_registers(false, true, true, true, false, true); 813 814 // move result of call into correct register 815 __ movptr(handler_addr, rax); 816 817 // Restore exception oop to RAX (required convention of exception handler). 818 __ movptr(exception_oop, exception_oop_callee_saved); 819 820 // verify that there is really a valid exception in rax 821 __ verify_not_null_oop(exception_oop); 822 823 // get throwing pc (= return address). 824 // rdx has been destroyed by the call, so it must be set again 825 // the pop is also necessary to simulate the effect of a ret(0) 826 __ pop(exception_pc); 827 828 // continue at exception handler (return address removed) 829 // note: do *not* remove arguments when unwinding the 830 // activation since the caller assumes having 831 // all arguments on the stack when entering the 832 // runtime to determine the exception handler 833 // (GC happens at call site with arguments!) 834 // rax: exception oop 835 // rdx: throwing pc 836 // rbx: exception handler 837 __ jmp(handler_addr); 838 } 839 840 841 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) { 842 // use the maximum number of runtime-arguments here because it is difficult to 843 // distinguish each RT-Call. 844 // Note: This number affects also the RT-Call in generate_handle_exception because 845 // the oop-map is shared for all calls. 846 const int num_rt_args = 2; // thread + dummy 847 848 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 849 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 850 851 OopMap* oop_map = save_live_registers(sasm, num_rt_args); 852 853 #ifdef _LP64 854 const Register thread = r15_thread; 855 // No need to worry about dummy 856 __ mov(c_rarg0, thread); 857 #else 858 __ push(rax); // push dummy 859 860 const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions) 861 // push java thread (becomes first argument of C function) 862 __ get_thread(thread); 863 __ push(thread); 864 #endif // _LP64 865 __ set_last_Java_frame(thread, noreg, rbp, NULL); 866 // do the call 867 __ call(RuntimeAddress(target)); 868 OopMapSet* oop_maps = new OopMapSet(); 869 oop_maps->add_gc_map(__ offset(), oop_map); 870 // verify callee-saved register 871 #ifdef ASSERT 872 guarantee(thread != rax, "change this code"); 873 __ push(rax); 874 { Label L; 875 __ get_thread(rax); 876 __ cmpptr(thread, rax); 877 __ jcc(Assembler::equal, L); 878 __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?"); 879 __ bind(L); 880 } 881 __ pop(rax); 882 #endif 883 __ reset_last_Java_frame(thread, true); 884 #ifndef _LP64 885 __ pop(rcx); // discard thread arg 886 __ pop(rcx); // discard dummy 887 #endif // _LP64 888 889 // check for pending exceptions 890 { Label L; 891 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 892 __ jcc(Assembler::equal, L); 893 // exception pending => remove activation and forward to exception handler 894 895 __ testptr(rax, rax); // have we deoptimized? 896 __ jump_cc(Assembler::equal, 897 RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id))); 898 899 // the deopt blob expects exceptions in the special fields of 900 // JavaThread, so copy and clear pending exception. 901 902 // load and clear pending exception 903 __ movptr(rax, Address(thread, Thread::pending_exception_offset())); 904 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD); 905 906 // check that there is really a valid exception 907 __ verify_not_null_oop(rax); 908 909 // load throwing pc: this is the return address of the stub 910 __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size)); 911 912 #ifdef ASSERT 913 // check that fields in JavaThread for exception oop and issuing pc are empty 914 Label oop_empty; 915 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); 916 __ jcc(Assembler::equal, oop_empty); 917 __ stop("exception oop must be empty"); 918 __ bind(oop_empty); 919 920 Label pc_empty; 921 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 922 __ jcc(Assembler::equal, pc_empty); 923 __ stop("exception pc must be empty"); 924 __ bind(pc_empty); 925 #endif 926 927 // store exception oop and throwing pc to JavaThread 928 __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax); 929 __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx); 930 931 restore_live_registers(sasm); 932 933 __ leave(); 934 __ addptr(rsp, BytesPerWord); // remove return address from stack 935 936 // Forward the exception directly to deopt blob. We can blow no 937 // registers and must leave throwing pc on the stack. A patch may 938 // have values live in registers so the entry point with the 939 // exception in tls. 940 __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls())); 941 942 __ bind(L); 943 } 944 945 946 // Runtime will return true if the nmethod has been deoptimized during 947 // the patching process. In that case we must do a deopt reexecute instead. 948 949 Label reexecuteEntry, cont; 950 951 __ testptr(rax, rax); // have we deoptimized? 952 __ jcc(Assembler::equal, cont); // no 953 954 // Will reexecute. Proper return address is already on the stack we just restore 955 // registers, pop all of our frame but the return address and jump to the deopt blob 956 restore_live_registers(sasm); 957 __ leave(); 958 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); 959 960 __ bind(cont); 961 restore_live_registers(sasm); 962 __ leave(); 963 __ ret(0); 964 965 return oop_maps; 966 } 967 968 969 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) { 970 971 // for better readability 972 const bool must_gc_arguments = true; 973 const bool dont_gc_arguments = false; 974 975 // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu 976 bool save_fpu_registers = true; 977 978 // stub code & info for the different stubs 979 OopMapSet* oop_maps = NULL; 980 switch (id) { 981 case forward_exception_id: 982 { 983 oop_maps = generate_handle_exception(id, sasm); 984 __ leave(); 985 __ ret(0); 986 } 987 break; 988 989 case new_instance_id: 990 case fast_new_instance_id: 991 case fast_new_instance_init_check_id: 992 { 993 Register klass = rdx; // Incoming 994 Register obj = rax; // Result 995 996 if (id == new_instance_id) { 997 __ set_info("new_instance", dont_gc_arguments); 998 } else if (id == fast_new_instance_id) { 999 __ set_info("fast new_instance", dont_gc_arguments); 1000 } else { 1001 assert(id == fast_new_instance_init_check_id, "bad StubID"); 1002 __ set_info("fast new_instance init check", dont_gc_arguments); 1003 } 1004 1005 if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) && UseTLAB 1006 && Universe::heap()->supports_inline_contig_alloc()) { 1007 Label slow_path; 1008 Register obj_size = rcx; 1009 Register t1 = rbx; 1010 Register t2 = rsi; 1011 assert_different_registers(klass, obj, obj_size, t1, t2); 1012 1013 __ push(rdi); 1014 __ push(rbx); 1015 1016 if (id == fast_new_instance_init_check_id) { 1017 // make sure the klass is initialized 1018 __ cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized); 1019 __ jcc(Assembler::notEqual, slow_path); 1020 } 1021 1022 #ifdef ASSERT 1023 // assert object can be fast path allocated 1024 { 1025 Label ok, not_ok; 1026 __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); 1027 __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0) 1028 __ jcc(Assembler::lessEqual, not_ok); 1029 __ testl(obj_size, Klass::_lh_instance_slow_path_bit); 1030 __ jcc(Assembler::zero, ok); 1031 __ bind(not_ok); 1032 __ stop("assert(can be fast path allocated)"); 1033 __ should_not_reach_here(); 1034 __ bind(ok); 1035 } 1036 #endif // ASSERT 1037 1038 // if we got here then the TLAB allocation failed, so try 1039 // refilling the TLAB or allocating directly from eden. 1040 Label retry_tlab, try_eden; 1041 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); 1042 NOT_LP64(__ get_thread(thread)); 1043 1044 __ bind(try_eden); 1045 // get the instance size (size is postive so movl is fine for 64bit) 1046 __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); 1047 1048 __ eden_allocate(obj, obj_size, 0, t1, slow_path); 1049 __ incr_allocated_bytes(thread, obj_size, 0); 1050 1051 __ initialize_object(obj, klass, obj_size, 0, t1, t2, /* is_tlab_allocated */ false); 1052 __ verify_oop(obj); 1053 __ pop(rbx); 1054 __ pop(rdi); 1055 __ ret(0); 1056 1057 __ bind(slow_path); 1058 __ pop(rbx); 1059 __ pop(rdi); 1060 } 1061 1062 __ enter(); 1063 OopMap* map = save_live_registers(sasm, 2); 1064 int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass); 1065 oop_maps = new OopMapSet(); 1066 oop_maps->add_gc_map(call_offset, map); 1067 restore_live_registers_except_rax(sasm); 1068 __ verify_oop(obj); 1069 __ leave(); 1070 __ ret(0); 1071 1072 // rax,: new instance 1073 } 1074 1075 break; 1076 1077 case counter_overflow_id: 1078 { 1079 Register bci = rax, method = rbx; 1080 __ enter(); 1081 OopMap* map = save_live_registers(sasm, 3); 1082 // Retrieve bci 1083 __ movl(bci, Address(rbp, 2*BytesPerWord)); 1084 // And a pointer to the Method* 1085 __ movptr(method, Address(rbp, 3*BytesPerWord)); 1086 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method); 1087 oop_maps = new OopMapSet(); 1088 oop_maps->add_gc_map(call_offset, map); 1089 restore_live_registers(sasm); 1090 __ leave(); 1091 __ ret(0); 1092 } 1093 break; 1094 1095 case new_type_array_id: 1096 case new_object_array_id: 1097 { 1098 Register length = rbx; // Incoming 1099 Register klass = rdx; // Incoming 1100 Register obj = rax; // Result 1101 1102 if (id == new_type_array_id) { 1103 __ set_info("new_type_array", dont_gc_arguments); 1104 } else { 1105 __ set_info("new_object_array", dont_gc_arguments); 1106 } 1107 1108 #ifdef ASSERT 1109 // assert object type is really an array of the proper kind 1110 { 1111 Label ok; 1112 Register t0 = obj; 1113 __ movl(t0, Address(klass, Klass::layout_helper_offset())); 1114 __ sarl(t0, Klass::_lh_array_tag_shift); 1115 int tag = ((id == new_type_array_id) 1116 ? Klass::_lh_array_tag_type_value 1117 : Klass::_lh_array_tag_obj_value); 1118 __ cmpl(t0, tag); 1119 __ jcc(Assembler::equal, ok); 1120 __ stop("assert(is an array klass)"); 1121 __ should_not_reach_here(); 1122 __ bind(ok); 1123 } 1124 #endif // ASSERT 1125 1126 // If we got here, the TLAB allocation failed, so try allocating from 1127 // eden if inline contiguous allocations are supported. 1128 if (UseTLAB && Universe::heap()->supports_inline_contig_alloc()) { 1129 Register arr_size = rsi; 1130 Register t1 = rcx; // must be rcx for use as shift count 1131 Register t2 = rdi; 1132 Label slow_path; 1133 1134 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F)) 1135 // since size is positive movl does right thing on 64bit 1136 __ movl(t1, Address(klass, Klass::layout_helper_offset())); 1137 // since size is postive movl does right thing on 64bit 1138 __ movl(arr_size, length); 1139 assert(t1 == rcx, "fixed register usage"); 1140 __ shlptr(arr_size /* by t1=rcx, mod 32 */); 1141 __ shrptr(t1, Klass::_lh_header_size_shift); 1142 __ andptr(t1, Klass::_lh_header_size_mask); 1143 __ addptr(arr_size, t1); 1144 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up 1145 __ andptr(arr_size, ~MinObjAlignmentInBytesMask); 1146 1147 __ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size 1148 1149 // Using t2 for non 64-bit. 1150 const Register thread = NOT_LP64(t2) LP64_ONLY(r15_thread); 1151 NOT_LP64(__ get_thread(thread)); 1152 __ incr_allocated_bytes(thread, arr_size, 0); 1153 1154 __ initialize_header(obj, klass, length, t1, t2); 1155 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte))); 1156 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise"); 1157 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise"); 1158 __ andptr(t1, Klass::_lh_header_size_mask); 1159 __ subptr(arr_size, t1); // body length 1160 __ addptr(t1, obj); // body start 1161 __ initialize_body(t1, arr_size, 0, t2); 1162 __ verify_oop(obj); 1163 __ ret(0); 1164 1165 __ bind(slow_path); 1166 } 1167 1168 __ enter(); 1169 OopMap* map = save_live_registers(sasm, 3); 1170 int call_offset; 1171 if (id == new_type_array_id) { 1172 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length); 1173 } else { 1174 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length); 1175 } 1176 1177 oop_maps = new OopMapSet(); 1178 oop_maps->add_gc_map(call_offset, map); 1179 restore_live_registers_except_rax(sasm); 1180 1181 __ verify_oop(obj); 1182 __ leave(); 1183 __ ret(0); 1184 1185 // rax,: new array 1186 } 1187 break; 1188 1189 case new_multi_array_id: 1190 { StubFrame f(sasm, "new_multi_array", dont_gc_arguments); 1191 // rax,: klass 1192 // rbx,: rank 1193 // rcx: address of 1st dimension 1194 OopMap* map = save_live_registers(sasm, 4); 1195 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx); 1196 1197 oop_maps = new OopMapSet(); 1198 oop_maps->add_gc_map(call_offset, map); 1199 restore_live_registers_except_rax(sasm); 1200 1201 // rax,: new multi array 1202 __ verify_oop(rax); 1203 } 1204 break; 1205 1206 case register_finalizer_id: 1207 { 1208 __ set_info("register_finalizer", dont_gc_arguments); 1209 1210 // This is called via call_runtime so the arguments 1211 // will be place in C abi locations 1212 1213 #ifdef _LP64 1214 __ verify_oop(c_rarg0); 1215 __ mov(rax, c_rarg0); 1216 #else 1217 // The object is passed on the stack and we haven't pushed a 1218 // frame yet so it's one work away from top of stack. 1219 __ movptr(rax, Address(rsp, 1 * BytesPerWord)); 1220 __ verify_oop(rax); 1221 #endif // _LP64 1222 1223 // load the klass and check the has finalizer flag 1224 Label register_finalizer; 1225 Register t = rsi; 1226 __ load_klass(t, rax); 1227 __ movl(t, Address(t, Klass::access_flags_offset())); 1228 __ testl(t, JVM_ACC_HAS_FINALIZER); 1229 __ jcc(Assembler::notZero, register_finalizer); 1230 __ ret(0); 1231 1232 __ bind(register_finalizer); 1233 __ enter(); 1234 OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */); 1235 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax); 1236 oop_maps = new OopMapSet(); 1237 oop_maps->add_gc_map(call_offset, oop_map); 1238 1239 // Now restore all the live registers 1240 restore_live_registers(sasm); 1241 1242 __ leave(); 1243 __ ret(0); 1244 } 1245 break; 1246 1247 case throw_range_check_failed_id: 1248 { StubFrame f(sasm, "range_check_failed", dont_gc_arguments); 1249 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true); 1250 } 1251 break; 1252 1253 case throw_index_exception_id: 1254 { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments); 1255 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true); 1256 } 1257 break; 1258 1259 case throw_div0_exception_id: 1260 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments); 1261 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false); 1262 } 1263 break; 1264 1265 case throw_null_pointer_exception_id: 1266 { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments); 1267 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false); 1268 } 1269 break; 1270 1271 case handle_exception_nofpu_id: 1272 case handle_exception_id: 1273 { StubFrame f(sasm, "handle_exception", dont_gc_arguments); 1274 oop_maps = generate_handle_exception(id, sasm); 1275 } 1276 break; 1277 1278 case handle_exception_from_callee_id: 1279 { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments); 1280 oop_maps = generate_handle_exception(id, sasm); 1281 } 1282 break; 1283 1284 case unwind_exception_id: 1285 { __ set_info("unwind_exception", dont_gc_arguments); 1286 // note: no stubframe since we are about to leave the current 1287 // activation and we are calling a leaf VM function only. 1288 generate_unwind_exception(sasm); 1289 } 1290 break; 1291 1292 case throw_array_store_exception_id: 1293 { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments); 1294 // tos + 0: link 1295 // + 1: return address 1296 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true); 1297 } 1298 break; 1299 1300 case throw_class_cast_exception_id: 1301 { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments); 1302 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true); 1303 } 1304 break; 1305 1306 case throw_incompatible_class_change_error_id: 1307 { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments); 1308 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false); 1309 } 1310 break; 1311 1312 case slow_subtype_check_id: 1313 { 1314 // Typical calling sequence: 1315 // __ push(klass_RInfo); // object klass or other subclass 1316 // __ push(sup_k_RInfo); // array element klass or other superclass 1317 // __ call(slow_subtype_check); 1318 // Note that the subclass is pushed first, and is therefore deepest. 1319 // Previous versions of this code reversed the names 'sub' and 'super'. 1320 // This was operationally harmless but made the code unreadable. 1321 enum layout { 1322 rax_off, SLOT2(raxH_off) 1323 rcx_off, SLOT2(rcxH_off) 1324 rsi_off, SLOT2(rsiH_off) 1325 rdi_off, SLOT2(rdiH_off) 1326 // saved_rbp_off, SLOT2(saved_rbpH_off) 1327 return_off, SLOT2(returnH_off) 1328 sup_k_off, SLOT2(sup_kH_off) 1329 klass_off, SLOT2(superH_off) 1330 framesize, 1331 result_off = klass_off // deepest argument is also the return value 1332 }; 1333 1334 __ set_info("slow_subtype_check", dont_gc_arguments); 1335 __ push(rdi); 1336 __ push(rsi); 1337 __ push(rcx); 1338 __ push(rax); 1339 1340 // This is called by pushing args and not with C abi 1341 __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass 1342 __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass 1343 1344 Label miss; 1345 __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss); 1346 1347 // fallthrough on success: 1348 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result 1349 __ pop(rax); 1350 __ pop(rcx); 1351 __ pop(rsi); 1352 __ pop(rdi); 1353 __ ret(0); 1354 1355 __ bind(miss); 1356 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result 1357 __ pop(rax); 1358 __ pop(rcx); 1359 __ pop(rsi); 1360 __ pop(rdi); 1361 __ ret(0); 1362 } 1363 break; 1364 1365 case monitorenter_nofpu_id: 1366 save_fpu_registers = false; 1367 // fall through 1368 case monitorenter_id: 1369 { 1370 StubFrame f(sasm, "monitorenter", dont_gc_arguments); 1371 OopMap* map = save_live_registers(sasm, 3, save_fpu_registers); 1372 1373 // Called with store_parameter and not C abi 1374 1375 f.load_argument(1, rax); // rax,: object 1376 f.load_argument(0, rbx); // rbx,: lock address 1377 1378 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx); 1379 1380 oop_maps = new OopMapSet(); 1381 oop_maps->add_gc_map(call_offset, map); 1382 restore_live_registers(sasm, save_fpu_registers); 1383 } 1384 break; 1385 1386 case monitorexit_nofpu_id: 1387 save_fpu_registers = false; 1388 // fall through 1389 case monitorexit_id: 1390 { 1391 StubFrame f(sasm, "monitorexit", dont_gc_arguments); 1392 OopMap* map = save_live_registers(sasm, 2, save_fpu_registers); 1393 1394 // Called with store_parameter and not C abi 1395 1396 f.load_argument(0, rax); // rax,: lock address 1397 1398 // note: really a leaf routine but must setup last java sp 1399 // => use call_RT for now (speed can be improved by 1400 // doing last java sp setup manually) 1401 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax); 1402 1403 oop_maps = new OopMapSet(); 1404 oop_maps->add_gc_map(call_offset, map); 1405 restore_live_registers(sasm, save_fpu_registers); 1406 } 1407 break; 1408 1409 case deoptimize_id: 1410 { 1411 StubFrame f(sasm, "deoptimize", dont_gc_arguments); 1412 const int num_rt_args = 2; // thread, trap_request 1413 OopMap* oop_map = save_live_registers(sasm, num_rt_args); 1414 f.load_argument(0, rax); 1415 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), rax); 1416 oop_maps = new OopMapSet(); 1417 oop_maps->add_gc_map(call_offset, oop_map); 1418 restore_live_registers(sasm); 1419 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 1420 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 1421 __ leave(); 1422 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); 1423 } 1424 break; 1425 1426 case access_field_patching_id: 1427 { StubFrame f(sasm, "access_field_patching", dont_gc_arguments); 1428 // we should set up register map 1429 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching)); 1430 } 1431 break; 1432 1433 case load_klass_patching_id: 1434 { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments); 1435 // we should set up register map 1436 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching)); 1437 } 1438 break; 1439 1440 case load_mirror_patching_id: 1441 { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments); 1442 // we should set up register map 1443 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching)); 1444 } 1445 break; 1446 1447 case load_appendix_patching_id: 1448 { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments); 1449 // we should set up register map 1450 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching)); 1451 } 1452 break; 1453 1454 case dtrace_object_alloc_id: 1455 { // rax,: object 1456 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments); 1457 // we can't gc here so skip the oopmap but make sure that all 1458 // the live registers get saved. 1459 save_live_registers(sasm, 1); 1460 1461 __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax)); 1462 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc))); 1463 NOT_LP64(__ pop(rax)); 1464 1465 restore_live_registers(sasm); 1466 } 1467 break; 1468 1469 case fpu2long_stub_id: 1470 { 1471 // rax, and rdx are destroyed, but should be free since the result is returned there 1472 // preserve rsi,ecx 1473 __ push(rsi); 1474 __ push(rcx); 1475 LP64_ONLY(__ push(rdx);) 1476 1477 // check for NaN 1478 Label return0, do_return, return_min_jlong, do_convert; 1479 1480 Address value_high_word(rsp, wordSize + 4); 1481 Address value_low_word(rsp, wordSize); 1482 Address result_high_word(rsp, 3*wordSize + 4); 1483 Address result_low_word(rsp, 3*wordSize); 1484 1485 __ subptr(rsp, 32); // more than enough on 32bit 1486 __ fst_d(value_low_word); 1487 __ movl(rax, value_high_word); 1488 __ andl(rax, 0x7ff00000); 1489 __ cmpl(rax, 0x7ff00000); 1490 __ jcc(Assembler::notEqual, do_convert); 1491 __ movl(rax, value_high_word); 1492 __ andl(rax, 0xfffff); 1493 __ orl(rax, value_low_word); 1494 __ jcc(Assembler::notZero, return0); 1495 1496 __ bind(do_convert); 1497 __ fnstcw(Address(rsp, 0)); 1498 __ movzwl(rax, Address(rsp, 0)); 1499 __ orl(rax, 0xc00); 1500 __ movw(Address(rsp, 2), rax); 1501 __ fldcw(Address(rsp, 2)); 1502 __ fwait(); 1503 __ fistp_d(result_low_word); 1504 __ fldcw(Address(rsp, 0)); 1505 __ fwait(); 1506 // This gets the entire long in rax on 64bit 1507 __ movptr(rax, result_low_word); 1508 // testing of high bits 1509 __ movl(rdx, result_high_word); 1510 __ mov(rcx, rax); 1511 // What the heck is the point of the next instruction??? 1512 __ xorl(rcx, 0x0); 1513 __ movl(rsi, 0x80000000); 1514 __ xorl(rsi, rdx); 1515 __ orl(rcx, rsi); 1516 __ jcc(Assembler::notEqual, do_return); 1517 __ fldz(); 1518 __ fcomp_d(value_low_word); 1519 __ fnstsw_ax(); 1520 #ifdef _LP64 1521 __ testl(rax, 0x4100); // ZF & CF == 0 1522 __ jcc(Assembler::equal, return_min_jlong); 1523 #else 1524 __ sahf(); 1525 __ jcc(Assembler::above, return_min_jlong); 1526 #endif // _LP64 1527 // return max_jlong 1528 #ifndef _LP64 1529 __ movl(rdx, 0x7fffffff); 1530 __ movl(rax, 0xffffffff); 1531 #else 1532 __ mov64(rax, CONST64(0x7fffffffffffffff)); 1533 #endif // _LP64 1534 __ jmp(do_return); 1535 1536 __ bind(return_min_jlong); 1537 #ifndef _LP64 1538 __ movl(rdx, 0x80000000); 1539 __ xorl(rax, rax); 1540 #else 1541 __ mov64(rax, UCONST64(0x8000000000000000)); 1542 #endif // _LP64 1543 __ jmp(do_return); 1544 1545 __ bind(return0); 1546 __ fpop(); 1547 #ifndef _LP64 1548 __ xorptr(rdx,rdx); 1549 __ xorptr(rax,rax); 1550 #else 1551 __ xorptr(rax, rax); 1552 #endif // _LP64 1553 1554 __ bind(do_return); 1555 __ addptr(rsp, 32); 1556 LP64_ONLY(__ pop(rdx);) 1557 __ pop(rcx); 1558 __ pop(rsi); 1559 __ ret(0); 1560 } 1561 break; 1562 1563 #if INCLUDE_ALL_GCS 1564 case g1_pre_barrier_slow_id: 1565 { 1566 StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments); 1567 // arg0 : previous value of memory 1568 1569 BarrierSet* bs = BarrierSet::barrier_set(); 1570 if (bs->kind() != BarrierSet::G1BarrierSet) { 1571 __ movptr(rax, (int)id); 1572 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax); 1573 __ should_not_reach_here(); 1574 break; 1575 } 1576 __ push(rax); 1577 __ push(rdx); 1578 1579 const Register pre_val = rax; 1580 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread); 1581 const Register tmp = rdx; 1582 1583 NOT_LP64(__ get_thread(thread);) 1584 1585 Address queue_active(thread, in_bytes(G1ThreadLocalData::satb_mark_queue_active_offset())); 1586 Address queue_index(thread, in_bytes(G1ThreadLocalData::satb_mark_queue_index_offset())); 1587 Address buffer(thread, in_bytes(G1ThreadLocalData::satb_mark_queue_buffer_offset())); 1588 1589 Label done; 1590 Label runtime; 1591 1592 // Is marking still active? 1593 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 1594 __ cmpl(queue_active, 0); 1595 } else { 1596 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 1597 __ cmpb(queue_active, 0); 1598 } 1599 __ jcc(Assembler::equal, done); 1600 1601 // Can we store original value in the thread's buffer? 1602 1603 __ movptr(tmp, queue_index); 1604 __ testptr(tmp, tmp); 1605 __ jcc(Assembler::zero, runtime); 1606 __ subptr(tmp, wordSize); 1607 __ movptr(queue_index, tmp); 1608 __ addptr(tmp, buffer); 1609 1610 // prev_val (rax) 1611 f.load_argument(0, pre_val); 1612 __ movptr(Address(tmp, 0), pre_val); 1613 __ jmp(done); 1614 1615 __ bind(runtime); 1616 1617 save_live_registers(sasm, 3); 1618 1619 // load the pre-value 1620 f.load_argument(0, rcx); 1621 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), rcx, thread); 1622 1623 restore_live_registers(sasm); 1624 1625 __ bind(done); 1626 1627 __ pop(rdx); 1628 __ pop(rax); 1629 } 1630 break; 1631 1632 case g1_post_barrier_slow_id: 1633 { 1634 StubFrame f(sasm, "g1_post_barrier", dont_gc_arguments); 1635 1636 BarrierSet* bs = BarrierSet::barrier_set(); 1637 if (bs->kind() != BarrierSet::G1BarrierSet) { 1638 __ movptr(rax, (int)id); 1639 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax); 1640 __ should_not_reach_here(); 1641 break; 1642 } 1643 1644 // arg0: store_address 1645 Address store_addr(rbp, 2*BytesPerWord); 1646 1647 Label done; 1648 Label enqueued; 1649 Label runtime; 1650 1651 // At this point we know new_value is non-NULL and the new_value crosses regions. 1652 // Must check to see if card is already dirty 1653 1654 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread); 1655 1656 Address queue_index(thread, in_bytes(G1ThreadLocalData::dirty_card_queue_index_offset())); 1657 Address buffer(thread, in_bytes(G1ThreadLocalData::dirty_card_queue_buffer_offset())); 1658 1659 __ push(rax); 1660 __ push(rcx); 1661 1662 const Register cardtable = rax; 1663 const Register card_addr = rcx; 1664 1665 f.load_argument(0, card_addr); 1666 __ shrptr(card_addr, CardTable::card_shift); 1667 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 1668 // a valid address and therefore is not properly handled by the relocation code. 1669 __ movptr(cardtable, ci_card_table_address_as<intptr_t>()); 1670 __ addptr(card_addr, cardtable); 1671 1672 NOT_LP64(__ get_thread(thread);) 1673 1674 __ cmpb(Address(card_addr, 0), (int)G1CardTable::g1_young_card_val()); 1675 __ jcc(Assembler::equal, done); 1676 1677 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 1678 __ cmpb(Address(card_addr, 0), (int)CardTable::dirty_card_val()); 1679 __ jcc(Assembler::equal, done); 1680 1681 // storing region crossing non-NULL, card is clean. 1682 // dirty card and log. 1683 1684 __ movb(Address(card_addr, 0), (int)CardTable::dirty_card_val()); 1685 1686 const Register tmp = rdx; 1687 __ push(rdx); 1688 1689 __ movptr(tmp, queue_index); 1690 __ testptr(tmp, tmp); 1691 __ jcc(Assembler::zero, runtime); 1692 __ subptr(tmp, wordSize); 1693 __ movptr(queue_index, tmp); 1694 __ addptr(tmp, buffer); 1695 __ movptr(Address(tmp, 0), card_addr); 1696 __ jmp(enqueued); 1697 1698 __ bind(runtime); 1699 1700 save_live_registers(sasm, 3); 1701 1702 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 1703 1704 restore_live_registers(sasm); 1705 1706 __ bind(enqueued); 1707 __ pop(rdx); 1708 1709 __ bind(done); 1710 __ pop(rcx); 1711 __ pop(rax); 1712 } 1713 break; 1714 #endif // INCLUDE_ALL_GCS 1715 1716 case predicate_failed_trap_id: 1717 { 1718 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments); 1719 1720 OopMap* map = save_live_registers(sasm, 1); 1721 1722 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap)); 1723 oop_maps = new OopMapSet(); 1724 oop_maps->add_gc_map(call_offset, map); 1725 restore_live_registers(sasm); 1726 __ leave(); 1727 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 1728 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 1729 1730 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); 1731 } 1732 break; 1733 1734 default: 1735 { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments); 1736 __ movptr(rax, (int)id); 1737 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax); 1738 __ should_not_reach_here(); 1739 } 1740 break; 1741 } 1742 return oop_maps; 1743 } 1744 1745 #undef __ 1746 1747 const char *Runtime1::pd_name_for_address(address entry) { 1748 return "<unknown function>"; 1749 }