1 /*
   2  * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "c1/c1_Defs.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_MacroAssembler.hpp"
  30 #include "c1/c1_Runtime1.hpp"
  31 #include "ci/ciUtilities.hpp"
  32 #include "gc/shared/cardTable.hpp"
  33 #include "gc/shared/cardTableBarrierSet.hpp"
  34 #include "interpreter/interpreter.hpp"
  35 #include "nativeInst_arm.hpp"
  36 #include "oops/compiledICHolder.hpp"
  37 #include "oops/oop.inline.hpp"
  38 #include "prims/jvmtiExport.hpp"
  39 #include "register_arm.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "runtime/signature.hpp"
  42 #include "runtime/vframeArray.hpp"
  43 #include "utilities/align.hpp"
  44 #include "vmreg_arm.inline.hpp"
  45 
  46 // Note: Rtemp usage is this file should not impact C2 and should be
  47 // correct as long as it is not implicitly used in lower layers (the
  48 // arm [macro]assembler) and used with care in the other C1 specific
  49 // files.
  50 
  51 // Implementation of StubAssembler
  52 
  53 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
  54   mov(R0, Rthread);
  55 
  56   int call_offset = set_last_Java_frame(SP, FP, false, Rtemp);
  57 
  58   call(entry);
  59   if (call_offset == -1) { // PC not saved
  60     call_offset = offset();
  61   }
  62   reset_last_Java_frame(Rtemp);
  63 
  64   assert(frame_size() != no_frame_size, "frame must be fixed");
  65   if (_stub_id != Runtime1::forward_exception_id) {
  66     ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
  67   }
  68 
  69   if (oop_result1->is_valid()) {
  70     assert_different_registers(oop_result1, R3, Rtemp);
  71     get_vm_result(oop_result1, Rtemp);
  72   }
  73   if (metadata_result->is_valid()) {
  74     assert_different_registers(metadata_result, R3, Rtemp);
  75     get_vm_result_2(metadata_result, Rtemp);
  76   }
  77 
  78   // Check for pending exception
  79   // unpack_with_exception_in_tls path is taken through
  80   // Runtime1::exception_handler_for_pc
  81   if (_stub_id != Runtime1::forward_exception_id) {
  82     assert(frame_size() != no_frame_size, "cannot directly call forward_exception_id");
  83 #ifdef AARCH64
  84     Label skip;
  85     cbz(R3, skip);
  86     jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp);
  87     bind(skip);
  88 #else
  89     cmp(R3, 0);
  90     jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp, ne);
  91 #endif // AARCH64
  92   } else {
  93 #ifdef ASSERT
  94     // Should not have pending exception in forward_exception stub
  95     ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
  96     cmp(R3, 0);
  97     breakpoint(ne);
  98 #endif // ASSERT
  99   }
 100   return call_offset;
 101 }
 102 
 103 
 104 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
 105   if (arg1 != R1) {
 106     mov(R1, arg1);
 107   }
 108   return call_RT(oop_result1, metadata_result, entry, 1);
 109 }
 110 
 111 
 112 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
 113   assert(arg1 == R1 && arg2 == R2, "cannot handle otherwise");
 114   return call_RT(oop_result1, metadata_result, entry, 2);
 115 }
 116 
 117 
 118 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
 119   assert(arg1 == R1 && arg2 == R2 && arg3 == R3, "cannot handle otherwise");
 120   return call_RT(oop_result1, metadata_result, entry, 3);
 121 }
 122 
 123 
 124 #define __ sasm->
 125 
 126 // TODO: ARM - does this duplicate RegisterSaver in SharedRuntime?
 127 #ifdef AARCH64
 128 
 129   //
 130   // On AArch64 registers save area has the following layout:
 131   //
 132   // |---------------------|
 133   // | return address (LR) |
 134   // | FP                  |
 135   // |---------------------|
 136   // | D31                 |
 137   // | ...                 |
 138   // | D0                  |
 139   // |---------------------|
 140   // | padding             |
 141   // |---------------------|
 142   // | R28                 |
 143   // | ...                 |
 144   // | R0                  |
 145   // |---------------------| <-- SP
 146   //
 147 
 148 enum RegisterLayout {
 149   number_of_saved_gprs = 29,
 150   number_of_saved_fprs = FloatRegisterImpl::number_of_registers,
 151 
 152   R0_offset  = 0,
 153   D0_offset  = R0_offset + number_of_saved_gprs + 1,
 154   FP_offset  = D0_offset + number_of_saved_fprs,
 155   LR_offset  = FP_offset + 1,
 156 
 157   reg_save_size = LR_offset + 1,
 158 
 159   arg1_offset = reg_save_size * wordSize,
 160   arg2_offset = (reg_save_size + 1) * wordSize
 161 };
 162 
 163 #else
 164 
 165 enum RegisterLayout {
 166   fpu_save_size = pd_nof_fpu_regs_reg_alloc,
 167 #ifndef __SOFTFP__
 168   D0_offset = 0,
 169 #endif
 170   R0_offset = fpu_save_size,
 171   R1_offset,
 172   R2_offset,
 173   R3_offset,
 174   R4_offset,
 175   R5_offset,
 176   R6_offset,
 177 #if (FP_REG_NUM != 7)
 178   R7_offset,
 179 #endif
 180   R8_offset,
 181   R9_offset,
 182   R10_offset,
 183 #if (FP_REG_NUM != 11)
 184   R11_offset,
 185 #endif
 186   R12_offset,
 187   FP_offset,
 188   LR_offset,
 189   reg_save_size,
 190   arg1_offset = reg_save_size * wordSize,
 191   arg2_offset = (reg_save_size + 1) * wordSize
 192 };
 193 
 194 #endif // AARCH64
 195 
 196 static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
 197   sasm->set_frame_size(reg_save_size /* in words */);
 198 
 199   // Record saved value locations in an OopMap.
 200   // Locations are offsets from sp after runtime call.
 201   OopMap* map = new OopMap(VMRegImpl::slots_per_word * reg_save_size, 0);
 202 
 203 #ifdef AARCH64
 204   for (int i = 0; i < number_of_saved_gprs; i++) {
 205     map->set_callee_saved(VMRegImpl::stack2reg((R0_offset + i) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg());
 206   }
 207   map->set_callee_saved(VMRegImpl::stack2reg(FP_offset * VMRegImpl::slots_per_word), FP->as_VMReg());
 208   map->set_callee_saved(VMRegImpl::stack2reg(LR_offset * VMRegImpl::slots_per_word), LR->as_VMReg());
 209 
 210   if (save_fpu_registers) {
 211     for (int i = 0; i < number_of_saved_fprs; i++) {
 212       map->set_callee_saved(VMRegImpl::stack2reg((D0_offset + i) * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg());
 213     }
 214   }
 215 #else
 216   int j=0;
 217   for (int i = R0_offset; i < R10_offset; i++) {
 218     if (j == FP_REG_NUM) {
 219       // skip the FP register, saved below
 220       j++;
 221     }
 222     map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
 223     j++;
 224   }
 225   assert(j == R10->encoding(), "must be");
 226 #if (FP_REG_NUM != 11)
 227   // add R11, if not saved as FP
 228   map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
 229 #endif
 230   map->set_callee_saved(VMRegImpl::stack2reg(FP_offset), FP->as_VMReg());
 231   map->set_callee_saved(VMRegImpl::stack2reg(LR_offset), LR->as_VMReg());
 232 
 233   if (save_fpu_registers) {
 234     for (int i = 0; i < fpu_save_size; i++) {
 235       map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
 236     }
 237   }
 238 #endif // AARCH64
 239 
 240   return map;
 241 }
 242 
 243 static OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
 244   __ block_comment("save_live_registers");
 245   sasm->set_frame_size(reg_save_size /* in words */);
 246 
 247 #ifdef AARCH64
 248   assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned");
 249 
 250   __ raw_push(FP, LR);
 251 
 252   __ sub(SP, SP, (reg_save_size - 2) * wordSize);
 253 
 254   for (int i = 0; i < align_down((int)number_of_saved_gprs, 2); i += 2) {
 255     __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
 256   }
 257 
 258   if (is_odd(number_of_saved_gprs)) {
 259     int i = number_of_saved_gprs - 1;
 260     __ str(as_Register(i), Address(SP, (R0_offset + i) * wordSize));
 261   }
 262 
 263   if (save_fpu_registers) {
 264     assert (is_even(number_of_saved_fprs), "adjust this code");
 265     for (int i = 0; i < number_of_saved_fprs; i += 2) {
 266       __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
 267     }
 268   }
 269 #else
 270   __ push(RegisterSet(FP) | RegisterSet(LR));
 271   __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
 272   if (save_fpu_registers) {
 273     __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
 274   } else {
 275     __ sub(SP, SP, fpu_save_size * wordSize);
 276   }
 277 #endif // AARCH64
 278 
 279   return generate_oop_map(sasm, save_fpu_registers);
 280 }
 281 
 282 
 283 static void restore_live_registers(StubAssembler* sasm,
 284                                    bool restore_R0,
 285                                    bool restore_FP_LR,
 286                                    bool do_return,
 287                                    bool restore_fpu_registers = HaveVFP) {
 288   __ block_comment("restore_live_registers");
 289 
 290 #ifdef AARCH64
 291   if (restore_R0) {
 292     __ ldr(R0, Address(SP, R0_offset * wordSize));
 293   }
 294 
 295   assert(is_odd(number_of_saved_gprs), "adjust this code");
 296   for (int i = 1; i < number_of_saved_gprs; i += 2) {
 297     __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
 298   }
 299 
 300   if (restore_fpu_registers) {
 301     assert (is_even(number_of_saved_fprs), "adjust this code");
 302     for (int i = 0; i < number_of_saved_fprs; i += 2) {
 303       __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
 304     }
 305   }
 306 
 307   __ add(SP, SP, (reg_save_size - 2) * wordSize);
 308 
 309   if (restore_FP_LR) {
 310     __ raw_pop(FP, LR);
 311     if (do_return) {
 312       __ ret();
 313     }
 314   } else {
 315     assert (!do_return, "return without restoring FP/LR");
 316   }
 317 #else
 318   if (restore_fpu_registers) {
 319     __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
 320     if (!restore_R0) {
 321       __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize);
 322     }
 323   } else {
 324     __ add(SP, SP, (restore_R0 ? fpu_save_size : R1_offset) * wordSize);
 325   }
 326   __ pop(RegisterSet((restore_R0 ? R0 : R1), R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
 327   if (restore_FP_LR) {
 328     __ pop(RegisterSet(FP) | RegisterSet(do_return ? PC : LR));
 329   } else {
 330     assert (!do_return, "return without restoring FP/LR");
 331   }
 332 #endif // AARCH64
 333 }
 334 
 335 
 336 static void restore_live_registers_except_R0(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 337   restore_live_registers(sasm, false, true, true, restore_fpu_registers);
 338 }
 339 
 340 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 341   restore_live_registers(sasm, true, true, true, restore_fpu_registers);
 342 }
 343 
 344 #ifndef AARCH64
 345 static void restore_live_registers_except_FP_LR(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 346   restore_live_registers(sasm, true, false, false, restore_fpu_registers);
 347 }
 348 #endif // !AARCH64
 349 
 350 static void restore_live_registers_without_return(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 351   restore_live_registers(sasm, true, true, false, restore_fpu_registers);
 352 }
 353 
 354 void StubAssembler::save_live_registers() {
 355   ::save_live_registers(this);
 356 }
 357 
 358 void StubAssembler::restore_live_registers_without_return() {
 359   ::restore_live_registers_without_return(this);
 360 }
 361 
 362 void Runtime1::initialize_pd() {
 363 }
 364 
 365 
 366 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
 367   OopMap* oop_map = save_live_registers(sasm);
 368 
 369   if (has_argument) {
 370     __ ldr(R1, Address(SP, arg1_offset));
 371     __ ldr(R2, Address(SP, arg2_offset));
 372   }
 373 
 374   int call_offset = __ call_RT(noreg, noreg, target);
 375   OopMapSet* oop_maps = new OopMapSet();
 376   oop_maps->add_gc_map(call_offset, oop_map);
 377 
 378   DEBUG_ONLY(STOP("generate_exception_throw");)  // Should not reach here
 379   return oop_maps;
 380 }
 381 
 382 
 383 static void restore_sp_for_method_handle(StubAssembler* sasm) {
 384   // Restore SP from its saved reg (FP) if the exception PC is a MethodHandle call site.
 385   __ ldr_s32(Rtemp, Address(Rthread, JavaThread::is_method_handle_return_offset()));
 386 #ifdef AARCH64
 387   Label skip;
 388   __ cbz(Rtemp, skip);
 389   __ mov(SP, Rmh_SP_save);
 390   __ bind(skip);
 391 #else
 392   __ cmp(Rtemp, 0);
 393   __ mov(SP, Rmh_SP_save, ne);
 394 #endif // AARCH64
 395 }
 396 
 397 
 398 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
 399   __ block_comment("generate_handle_exception");
 400 
 401   bool save_fpu_registers = false;
 402 
 403   // Save registers, if required.
 404   OopMapSet* oop_maps = new OopMapSet();
 405   OopMap* oop_map = NULL;
 406 
 407   switch (id) {
 408   case forward_exception_id: {
 409     save_fpu_registers = HaveVFP;
 410     oop_map = generate_oop_map(sasm);
 411     __ ldr(Rexception_obj, Address(Rthread, Thread::pending_exception_offset()));
 412     __ ldr(Rexception_pc, Address(SP, LR_offset * wordSize));
 413     Register zero = __ zero_register(Rtemp);
 414     __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
 415     break;
 416   }
 417   case handle_exception_id:
 418     save_fpu_registers = HaveVFP;
 419     // fall-through
 420   case handle_exception_nofpu_id:
 421     // At this point all registers MAY be live.
 422     oop_map = save_live_registers(sasm, save_fpu_registers);
 423     break;
 424   case handle_exception_from_callee_id:
 425     // At this point all registers except exception oop (R4/R19) and
 426     // exception pc (R5/R20) are dead.
 427     oop_map = save_live_registers(sasm);  // TODO it's not required to save all registers
 428     break;
 429   default:  ShouldNotReachHere();
 430   }
 431 
 432   __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
 433   __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
 434 
 435   __ str(Rexception_pc, Address(SP, LR_offset * wordSize)); // patch throwing pc into return address
 436 
 437   int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
 438   oop_maps->add_gc_map(call_offset, oop_map);
 439 
 440   // Exception handler found
 441   __ str(R0, Address(SP, LR_offset * wordSize)); // patch the return address
 442 
 443   // Restore the registers that were saved at the beginning, remove
 444   // frame and jump to the exception handler.
 445   switch (id) {
 446   case forward_exception_id:
 447   case handle_exception_nofpu_id:
 448   case handle_exception_id:
 449     restore_live_registers(sasm, save_fpu_registers);
 450     // Note: the restore live registers includes the jump to LR (patched to R0)
 451     break;
 452   case handle_exception_from_callee_id:
 453     restore_live_registers_without_return(sasm); // must not jump immediatly to handler
 454     restore_sp_for_method_handle(sasm);
 455     __ ret();
 456     break;
 457   default:  ShouldNotReachHere();
 458   }
 459 
 460   DEBUG_ONLY(STOP("generate_handle_exception");)  // Should not reach here
 461 
 462   return oop_maps;
 463 }
 464 
 465 
 466 void Runtime1::generate_unwind_exception(StubAssembler* sasm) {
 467   // FP no longer used to find the frame start
 468   // on entry, remove_frame() has already been called (restoring FP and LR)
 469 
 470   // search the exception handler address of the caller (using the return address)
 471   __ mov(c_rarg0, Rthread);
 472   __ mov(Rexception_pc, LR);
 473   __ mov(c_rarg1, LR);
 474   __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), c_rarg0, c_rarg1);
 475 
 476   // Exception oop should be still in Rexception_obj and pc in Rexception_pc
 477   // Jump to handler
 478   __ verify_not_null_oop(Rexception_obj);
 479 
 480   // JSR292 extension
 481   restore_sp_for_method_handle(sasm);
 482 
 483   __ jump(R0);
 484 }
 485 
 486 
 487 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
 488   OopMap* oop_map = save_live_registers(sasm);
 489 
 490   // call the runtime patching routine, returns non-zero if nmethod got deopted.
 491   int call_offset = __ call_RT(noreg, noreg, target);
 492   OopMapSet* oop_maps = new OopMapSet();
 493   oop_maps->add_gc_map(call_offset, oop_map);
 494 
 495   DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
 496   assert(deopt_blob != NULL, "deoptimization blob must have been created");
 497 
 498   __ cmp_32(R0, 0);
 499 
 500 #ifdef AARCH64
 501   Label call_deopt;
 502 
 503   restore_live_registers_without_return(sasm);
 504   __ b(call_deopt, ne);
 505   __ ret();
 506 
 507   __ bind(call_deopt);
 508 #else
 509   restore_live_registers_except_FP_LR(sasm);
 510   __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
 511 
 512   // Deoptimization needed
 513   // TODO: ARM - no need to restore FP & LR because unpack_with_reexecution() stores them back
 514   __ pop(RegisterSet(FP) | RegisterSet(LR));
 515 #endif // AARCH64
 516 
 517   __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
 518 
 519   DEBUG_ONLY(STOP("generate_patching");)  // Should not reach here
 520   return oop_maps;
 521 }
 522 
 523 
 524 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
 525   const bool must_gc_arguments = true;
 526   const bool dont_gc_arguments = false;
 527 
 528   OopMapSet* oop_maps = NULL;
 529   bool save_fpu_registers = HaveVFP;
 530 
 531   switch (id) {
 532     case forward_exception_id:
 533       {
 534         oop_maps = generate_handle_exception(id, sasm);
 535         // does not return on ARM
 536       }
 537       break;
 538 
 539     case new_instance_id:
 540     case fast_new_instance_id:
 541     case fast_new_instance_init_check_id:
 542       {
 543         const Register result = R0;
 544         const Register klass  = R1;
 545 
 546         if (UseTLAB && Universe::heap()->supports_inline_contig_alloc() && id != new_instance_id) {
 547           // We come here when TLAB allocation failed.
 548           // In this case we try to allocate directly from eden.
 549           Label slow_case, slow_case_no_pop;
 550 
 551           // Make sure the class is fully initialized
 552           if (id == fast_new_instance_init_check_id) {
 553             __ ldrb(result, Address(klass, InstanceKlass::init_state_offset()));
 554             __ cmp(result, InstanceKlass::fully_initialized);
 555             __ b(slow_case_no_pop, ne);
 556           }
 557 
 558           // Free some temporary registers
 559           const Register obj_size = R4;
 560           const Register tmp1     = R5;
 561           const Register tmp2     = LR;
 562           const Register obj_end  = Rtemp;
 563 
 564           __ raw_push(R4, R5, LR);
 565 
 566           __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
 567           __ eden_allocate(result, obj_end, tmp1, tmp2, obj_size, slow_case);        // initializes result and obj_end
 568           __ incr_allocated_bytes(obj_size, tmp2);
 569           __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
 570                                instanceOopDesc::header_size() * HeapWordSize, -1,
 571                                /* is_tlab_allocated */ false);
 572           __ raw_pop_and_ret(R4, R5);
 573 
 574           __ bind(slow_case);
 575           __ raw_pop(R4, R5, LR);
 576 
 577           __ bind(slow_case_no_pop);
 578         }
 579 
 580         OopMap* map = save_live_registers(sasm);
 581         int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
 582         oop_maps = new OopMapSet();
 583         oop_maps->add_gc_map(call_offset, map);
 584 
 585         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 586 
 587         restore_live_registers_except_R0(sasm);
 588       }
 589       break;
 590 
 591     case counter_overflow_id:
 592       {
 593         OopMap* oop_map = save_live_registers(sasm);
 594         __ ldr(R1, Address(SP, arg1_offset));
 595         __ ldr(R2, Address(SP, arg2_offset));
 596         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), R1, R2);
 597         oop_maps = new OopMapSet();
 598         oop_maps->add_gc_map(call_offset, oop_map);
 599         restore_live_registers(sasm);
 600       }
 601       break;
 602 
 603     case new_type_array_id:
 604     case new_object_array_id:
 605       {
 606         if (id == new_type_array_id) {
 607           __ set_info("new_type_array", dont_gc_arguments);
 608         } else {
 609           __ set_info("new_object_array", dont_gc_arguments);
 610         }
 611 
 612         const Register result = R0;
 613         const Register klass  = R1;
 614         const Register length = R2;
 615 
 616         if (UseTLAB && Universe::heap()->supports_inline_contig_alloc()) {
 617           // We come here when TLAB allocation failed.
 618           // In this case we try to allocate directly from eden.
 619           Label slow_case, slow_case_no_pop;
 620 
 621 #ifdef AARCH64
 622           __ mov_slow(Rtemp, C1_MacroAssembler::max_array_allocation_length);
 623           __ cmp_32(length, Rtemp);
 624 #else
 625           __ cmp_32(length, C1_MacroAssembler::max_array_allocation_length);
 626 #endif // AARCH64
 627           __ b(slow_case_no_pop, hs);
 628 
 629           // Free some temporary registers
 630           const Register arr_size = R4;
 631           const Register tmp1     = R5;
 632           const Register tmp2     = LR;
 633           const Register tmp3     = Rtemp;
 634           const Register obj_end  = tmp3;
 635 
 636           __ raw_push(R4, R5, LR);
 637 
 638           // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
 639           __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
 640           __ mov(arr_size, MinObjAlignmentInBytesMask);
 641           __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
 642 
 643 #ifdef AARCH64
 644           __ lslv_w(tmp3, length, tmp1);
 645           __ add(arr_size, arr_size, tmp3);
 646 #else
 647           __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
 648 #endif // AARCH64
 649 
 650           __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
 651           __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
 652 
 653           // eden_allocate destroys tmp2, so reload header_size after allocation
 654           // eden_allocate initializes result and obj_end
 655           __ eden_allocate(result, obj_end, tmp1, tmp2, arr_size, slow_case);
 656           __ incr_allocated_bytes(arr_size, tmp2);
 657           __ ldrb(tmp2, Address(klass, in_bytes(Klass::layout_helper_offset()) +
 658                                        Klass::_lh_header_size_shift / BitsPerByte));
 659           __ initialize_object(result, obj_end, klass, length, tmp1, tmp2, tmp2, -1, /* is_tlab_allocated */ false);
 660           __ raw_pop_and_ret(R4, R5);
 661 
 662           __ bind(slow_case);
 663           __ raw_pop(R4, R5, LR);
 664           __ bind(slow_case_no_pop);
 665         }
 666 
 667         OopMap* map = save_live_registers(sasm);
 668         int call_offset;
 669         if (id == new_type_array_id) {
 670           call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
 671         } else {
 672           call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
 673         }
 674         oop_maps = new OopMapSet();
 675         oop_maps->add_gc_map(call_offset, map);
 676 
 677         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 678 
 679         restore_live_registers_except_R0(sasm);
 680       }
 681       break;
 682 
 683     case new_multi_array_id:
 684       {
 685         __ set_info("new_multi_array", dont_gc_arguments);
 686 
 687         // R0: klass
 688         // R2: rank
 689         // SP: address of 1st dimension
 690         const Register result = R0;
 691         OopMap* map = save_live_registers(sasm);
 692 
 693         __ mov(R1, R0);
 694         __ add(R3, SP, arg1_offset);
 695         int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_multi_array), R1, R2, R3);
 696 
 697         oop_maps = new OopMapSet();
 698         oop_maps->add_gc_map(call_offset, map);
 699 
 700         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 701 
 702         restore_live_registers_except_R0(sasm);
 703       }
 704       break;
 705 
 706     case register_finalizer_id:
 707       {
 708         __ set_info("register_finalizer", dont_gc_arguments);
 709 
 710         // Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set
 711         __ load_klass(Rtemp, R0);
 712         __ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
 713 
 714 #ifdef AARCH64
 715         Label L;
 716         __ tbnz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), L);
 717         __ ret();
 718         __ bind(L);
 719 #else
 720         __ tst(Rtemp, JVM_ACC_HAS_FINALIZER);
 721         __ bx(LR, eq);
 722 #endif // AARCH64
 723 
 724         // Call VM
 725         OopMap* map = save_live_registers(sasm);
 726         oop_maps = new OopMapSet();
 727         int call_offset = __ call_RT(noreg, noreg,
 728                                      CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), R0);
 729         oop_maps->add_gc_map(call_offset, map);
 730         restore_live_registers(sasm);
 731       }
 732       break;
 733 
 734     case throw_range_check_failed_id:
 735       {
 736         __ set_info("range_check_failed", dont_gc_arguments);
 737         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
 738       }
 739       break;
 740 
 741     case throw_index_exception_id:
 742       {
 743         __ set_info("index_range_check_failed", dont_gc_arguments);
 744 #ifdef AARCH64
 745         __ NOT_TESTED();
 746 #endif
 747         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
 748       }
 749       break;
 750 
 751     case throw_div0_exception_id:
 752       {
 753         __ set_info("throw_div0_exception", dont_gc_arguments);
 754         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
 755       }
 756       break;
 757 
 758     case throw_null_pointer_exception_id:
 759       {
 760         __ set_info("throw_null_pointer_exception", dont_gc_arguments);
 761         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
 762       }
 763       break;
 764 
 765     case handle_exception_nofpu_id:
 766     case handle_exception_id:
 767       {
 768         __ set_info("handle_exception", dont_gc_arguments);
 769         oop_maps = generate_handle_exception(id, sasm);
 770       }
 771       break;
 772 
 773     case handle_exception_from_callee_id:
 774       {
 775         __ set_info("handle_exception_from_callee", dont_gc_arguments);
 776         oop_maps = generate_handle_exception(id, sasm);
 777       }
 778       break;
 779 
 780     case unwind_exception_id:
 781       {
 782         __ set_info("unwind_exception", dont_gc_arguments);
 783         generate_unwind_exception(sasm);
 784       }
 785       break;
 786 
 787     case throw_array_store_exception_id:
 788       {
 789         __ set_info("throw_array_store_exception", dont_gc_arguments);
 790         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
 791       }
 792       break;
 793 
 794     case throw_class_cast_exception_id:
 795       {
 796         __ set_info("throw_class_cast_exception", dont_gc_arguments);
 797         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
 798       }
 799       break;
 800 
 801     case throw_incompatible_class_change_error_id:
 802       {
 803         __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
 804 #ifdef AARCH64
 805         __ NOT_TESTED();
 806 #endif
 807         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
 808       }
 809       break;
 810 
 811     case slow_subtype_check_id:
 812       {
 813         // (in)  R0 - sub, destroyed,
 814         // (in)  R1 - super, not changed
 815         // (out) R0 - result: 1 if check passed, 0 otherwise
 816         __ raw_push(R2, R3, LR);
 817 
 818         // Load an array of secondary_supers
 819         __ ldr(R2, Address(R0, Klass::secondary_supers_offset()));
 820         // Length goes to R3
 821         __ ldr_s32(R3, Address(R2, Array<Klass*>::length_offset_in_bytes()));
 822         __ add(R2, R2, Array<Klass*>::base_offset_in_bytes());
 823 
 824         Label loop, miss;
 825         __ bind(loop);
 826         __ cbz(R3, miss);
 827         __ ldr(LR, Address(R2, wordSize, post_indexed));
 828         __ sub(R3, R3, 1);
 829         __ cmp(LR, R1);
 830         __ b(loop, ne);
 831 
 832         // We get here if an equal cache entry is found
 833         __ str(R1, Address(R0, Klass::secondary_super_cache_offset()));
 834         __ mov(R0, 1);
 835         __ raw_pop_and_ret(R2, R3);
 836 
 837         // A cache entry not found - return false
 838         __ bind(miss);
 839         __ mov(R0, 0);
 840         __ raw_pop_and_ret(R2, R3);
 841       }
 842       break;
 843 
 844     case monitorenter_nofpu_id:
 845       save_fpu_registers = false;
 846       // fall through
 847     case monitorenter_id:
 848       {
 849         __ set_info("monitorenter", dont_gc_arguments);
 850         const Register obj  = R1;
 851         const Register lock = R2;
 852         OopMap* map = save_live_registers(sasm, save_fpu_registers);
 853         __ ldr(obj, Address(SP, arg1_offset));
 854         __ ldr(lock, Address(SP, arg2_offset));
 855         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), obj, lock);
 856         oop_maps = new OopMapSet();
 857         oop_maps->add_gc_map(call_offset, map);
 858         restore_live_registers(sasm, save_fpu_registers);
 859       }
 860       break;
 861 
 862     case monitorexit_nofpu_id:
 863       save_fpu_registers = false;
 864       // fall through
 865     case monitorexit_id:
 866       {
 867         __ set_info("monitorexit", dont_gc_arguments);
 868         const Register lock = R1;
 869         OopMap* map = save_live_registers(sasm, save_fpu_registers);
 870         __ ldr(lock, Address(SP, arg1_offset));
 871         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), lock);
 872         oop_maps = new OopMapSet();
 873         oop_maps->add_gc_map(call_offset, map);
 874         restore_live_registers(sasm, save_fpu_registers);
 875       }
 876       break;
 877 
 878     case deoptimize_id:
 879       {
 880         __ set_info("deoptimize", dont_gc_arguments);
 881         OopMap* oop_map = save_live_registers(sasm);
 882         const Register trap_request = R1;
 883         __ ldr(trap_request, Address(SP, arg1_offset));
 884         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), trap_request);
 885         oop_maps = new OopMapSet();
 886         oop_maps->add_gc_map(call_offset, oop_map);
 887         restore_live_registers_without_return(sasm);
 888         DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
 889         assert(deopt_blob != NULL, "deoptimization blob must have been created");
 890         __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg));
 891       }
 892       break;
 893 
 894     case access_field_patching_id:
 895       {
 896         __ set_info("access_field_patching", dont_gc_arguments);
 897         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
 898       }
 899       break;
 900 
 901     case load_klass_patching_id:
 902       {
 903         __ set_info("load_klass_patching", dont_gc_arguments);
 904         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
 905       }
 906       break;
 907 
 908     case load_appendix_patching_id:
 909       {
 910         __ set_info("load_appendix_patching", dont_gc_arguments);
 911         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
 912       }
 913       break;
 914 
 915     case load_mirror_patching_id:
 916       {
 917         __ set_info("load_mirror_patching", dont_gc_arguments);
 918         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
 919       }
 920       break;
 921 
 922     case predicate_failed_trap_id:
 923       {
 924         __ set_info("predicate_failed_trap", dont_gc_arguments);
 925 
 926         OopMap* oop_map = save_live_registers(sasm);
 927         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
 928 
 929         oop_maps = new OopMapSet();
 930         oop_maps->add_gc_map(call_offset, oop_map);
 931 
 932         restore_live_registers_without_return(sasm);
 933 
 934         DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
 935         assert(deopt_blob != NULL, "deoptimization blob must have been created");
 936         __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
 937       }
 938       break;
 939 
 940     default:
 941       {
 942         __ set_info("unimplemented entry", dont_gc_arguments);
 943         STOP("unimplemented entry");
 944       }
 945       break;
 946   }
 947   return oop_maps;
 948 }
 949 
 950 #undef __
 951 
 952 #ifdef __SOFTFP__
 953 const char *Runtime1::pd_name_for_address(address entry) {
 954 
 955 #define FUNCTION_CASE(a, f) \
 956   if ((intptr_t)a == CAST_FROM_FN_PTR(intptr_t, f))  return #f
 957 
 958   FUNCTION_CASE(entry, __aeabi_fadd_glibc);
 959   FUNCTION_CASE(entry, __aeabi_fmul);
 960   FUNCTION_CASE(entry, __aeabi_fsub_glibc);
 961   FUNCTION_CASE(entry, __aeabi_fdiv);
 962 
 963   // __aeabi_XXXX_glibc: Imported code from glibc soft-fp bundle for calculation accuracy improvement. See CR 6757269.
 964   FUNCTION_CASE(entry, __aeabi_dadd_glibc);
 965   FUNCTION_CASE(entry, __aeabi_dmul);
 966   FUNCTION_CASE(entry, __aeabi_dsub_glibc);
 967   FUNCTION_CASE(entry, __aeabi_ddiv);
 968 
 969   FUNCTION_CASE(entry, __aeabi_f2d);
 970   FUNCTION_CASE(entry, __aeabi_d2f);
 971   FUNCTION_CASE(entry, __aeabi_i2f);
 972   FUNCTION_CASE(entry, __aeabi_i2d);
 973   FUNCTION_CASE(entry, __aeabi_f2iz);
 974 
 975   FUNCTION_CASE(entry, SharedRuntime::fcmpl);
 976   FUNCTION_CASE(entry, SharedRuntime::fcmpg);
 977   FUNCTION_CASE(entry, SharedRuntime::dcmpl);
 978   FUNCTION_CASE(entry, SharedRuntime::dcmpg);
 979 
 980   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmplt);
 981   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmplt);
 982   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmple);
 983   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmple);
 984   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpge);
 985   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpge);
 986   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpgt);
 987   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpgt);
 988 
 989   FUNCTION_CASE(entry, SharedRuntime::fneg);
 990   FUNCTION_CASE(entry, SharedRuntime::dneg);
 991 
 992   FUNCTION_CASE(entry, __aeabi_fcmpeq);
 993   FUNCTION_CASE(entry, __aeabi_fcmplt);
 994   FUNCTION_CASE(entry, __aeabi_fcmple);
 995   FUNCTION_CASE(entry, __aeabi_fcmpge);
 996   FUNCTION_CASE(entry, __aeabi_fcmpgt);
 997 
 998   FUNCTION_CASE(entry, __aeabi_dcmpeq);
 999   FUNCTION_CASE(entry, __aeabi_dcmplt);
1000   FUNCTION_CASE(entry, __aeabi_dcmple);
1001   FUNCTION_CASE(entry, __aeabi_dcmpge);
1002   FUNCTION_CASE(entry, __aeabi_dcmpgt);
1003 #undef FUNCTION_CASE
1004   return "";
1005 }
1006 #else  // __SOFTFP__
1007 const char *Runtime1::pd_name_for_address(address entry) {
1008   return "<unknown function>";
1009 }
1010 #endif // __SOFTFP__