489 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
490
491 // Vector instruction support for >= Power6
492 // Vector Storage Access
493 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
494 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
495 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
496 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
497 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
498 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
499 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
500 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
501 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
502 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
503 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
504 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
505
506 // Vector-Scalar (VSX) instruction support.
507 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
508 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
509
510 // Vector Permute and Formatting
511 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
512 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
513 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
514 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
515 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
516 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
517 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
518 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
519 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
520 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
521 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
522 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
523 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
524 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
525 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
526
527 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
528 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
2082 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
2083 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
2084 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
2085 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
2086 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2087 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2088 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2089 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2090 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2091 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2092 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2093 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2094 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2095 // Vector Floating-Point not implemented yet
2096 inline void mtvscr( VectorRegister b);
2097 inline void mfvscr( VectorRegister d);
2098
2099 // Vector-Scalar (VSX) instructions.
2100 inline void lxvd2x( VectorSRegister d, Register a, Register b);
2101 inline void stxvd2x( VectorSRegister d, Register a, Register b);
2102
2103 // AES (introduced with Power 8)
2104 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2105 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2106 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2107 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2108 inline void vsbox( VectorRegister d, VectorRegister a);
2109
2110 // SHA (introduced with Power 8)
2111 // Not yet implemented.
2112
2113 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2114 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2115 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2116 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2117 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2118
2119 // Vector Permute and Xor (introduced with Power 8)
2120 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2121
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489 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
490
491 // Vector instruction support for >= Power6
492 // Vector Storage Access
493 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
494 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
495 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
496 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
497 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
498 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
499 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
500 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
501 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
502 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
503 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
504 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
505
506 // Vector-Scalar (VSX) instruction support.
507 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
508 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
509 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
510 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
511
512 // Vector Permute and Formatting
513 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
514 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
515 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
516 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
517 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
518 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
519 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
520 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
521 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
522 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
523 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
524 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
525 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
526 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
527 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
528
529 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
530 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
2084 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
2085 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
2086 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
2087 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
2088 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2089 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2090 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2091 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2092 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2093 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2094 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2095 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2096 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2097 // Vector Floating-Point not implemented yet
2098 inline void mtvscr( VectorRegister b);
2099 inline void mfvscr( VectorRegister d);
2100
2101 // Vector-Scalar (VSX) instructions.
2102 inline void lxvd2x( VectorSRegister d, Register a, Register b);
2103 inline void stxvd2x( VectorSRegister d, Register a, Register b);
2104 inline void mtvrd( VectorRegister d, Register a);
2105 inline void mfvrd( Register a, VectorRegister d);
2106
2107 // AES (introduced with Power 8)
2108 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2109 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2110 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2111 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2112 inline void vsbox( VectorRegister d, VectorRegister a);
2113
2114 // SHA (introduced with Power 8)
2115 // Not yet implemented.
2116
2117 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2118 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2119 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2120 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2121 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2122
2123 // Vector Permute and Xor (introduced with Power 8)
2124 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2125
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