< prev index next >

src/cpu/ppc/vm/assembler_ppc.hpp

Print this page




 490     // Vector instruction support for >= Power6
 491     // Vector Storage Access
 492     LVEBX_OPCODE   = (31u << OPCODE_SHIFT |    7u << 1),
 493     LVEHX_OPCODE   = (31u << OPCODE_SHIFT |   39u << 1),
 494     LVEWX_OPCODE   = (31u << OPCODE_SHIFT |   71u << 1),
 495     LVX_OPCODE     = (31u << OPCODE_SHIFT |  103u << 1),
 496     LVXL_OPCODE    = (31u << OPCODE_SHIFT |  359u << 1),
 497     STVEBX_OPCODE  = (31u << OPCODE_SHIFT |  135u << 1),
 498     STVEHX_OPCODE  = (31u << OPCODE_SHIFT |  167u << 1),
 499     STVEWX_OPCODE  = (31u << OPCODE_SHIFT |  199u << 1),
 500     STVX_OPCODE    = (31u << OPCODE_SHIFT |  231u << 1),
 501     STVXL_OPCODE   = (31u << OPCODE_SHIFT |  487u << 1),
 502     LVSL_OPCODE    = (31u << OPCODE_SHIFT |    6u << 1),
 503     LVSR_OPCODE    = (31u << OPCODE_SHIFT |   38u << 1),
 504 
 505     // Vector-Scalar (VSX) instruction support.
 506     LXVD2X_OPCODE  = (31u << OPCODE_SHIFT |  844u << 1),
 507     STXVD2X_OPCODE = (31u << OPCODE_SHIFT |  972u << 1),
 508     MTVSRD_OPCODE  = (31u << OPCODE_SHIFT |  179u << 1),
 509     MFVSRD_OPCODE  = (31u << OPCODE_SHIFT |   51u << 1),

 510 
 511     // Vector Permute and Formatting
 512     VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
 513     VPKSHSS_OPCODE = (4u  << OPCODE_SHIFT |  398u     ),
 514     VPKSWSS_OPCODE = (4u  << OPCODE_SHIFT |  462u     ),
 515     VPKSHUS_OPCODE = (4u  << OPCODE_SHIFT |  270u     ),
 516     VPKSWUS_OPCODE = (4u  << OPCODE_SHIFT |  334u     ),
 517     VPKUHUM_OPCODE = (4u  << OPCODE_SHIFT |   14u     ),
 518     VPKUWUM_OPCODE = (4u  << OPCODE_SHIFT |   78u     ),
 519     VPKUHUS_OPCODE = (4u  << OPCODE_SHIFT |  142u     ),
 520     VPKUWUS_OPCODE = (4u  << OPCODE_SHIFT |  206u     ),
 521     VUPKHPX_OPCODE = (4u  << OPCODE_SHIFT |  846u     ),
 522     VUPKHSB_OPCODE = (4u  << OPCODE_SHIFT |  526u     ),
 523     VUPKHSH_OPCODE = (4u  << OPCODE_SHIFT |  590u     ),
 524     VUPKLPX_OPCODE = (4u  << OPCODE_SHIFT |  974u     ),
 525     VUPKLSB_OPCODE = (4u  << OPCODE_SHIFT |  654u     ),
 526     VUPKLSH_OPCODE = (4u  << OPCODE_SHIFT |  718u     ),
 527 
 528     VMRGHB_OPCODE  = (4u  << OPCODE_SHIFT |   12u     ),
 529     VMRGHW_OPCODE  = (4u  << OPCODE_SHIFT |  140u     ),


2110   inline void vslb(     VectorRegister d, VectorRegister a, VectorRegister b);
2111   inline void vskw(     VectorRegister d, VectorRegister a, VectorRegister b);
2112   inline void vslh(     VectorRegister d, VectorRegister a, VectorRegister b);
2113   inline void vsrb(     VectorRegister d, VectorRegister a, VectorRegister b);
2114   inline void vsrw(     VectorRegister d, VectorRegister a, VectorRegister b);
2115   inline void vsrh(     VectorRegister d, VectorRegister a, VectorRegister b);
2116   inline void vsrab(    VectorRegister d, VectorRegister a, VectorRegister b);
2117   inline void vsraw(    VectorRegister d, VectorRegister a, VectorRegister b);
2118   inline void vsrah(    VectorRegister d, VectorRegister a, VectorRegister b);
2119   // Vector Floating-Point not implemented yet
2120   inline void mtvscr(   VectorRegister b);
2121   inline void mfvscr(   VectorRegister d);
2122 
2123   // Vector-Scalar (VSX) instructions.
2124   inline void lxvd2x(   VectorSRegister d, Register a);
2125   inline void lxvd2x(   VectorSRegister d, Register a, Register b);
2126   inline void stxvd2x(  VectorSRegister d, Register a);
2127   inline void stxvd2x(  VectorSRegister d, Register a, Register b);
2128   inline void mtvrd(    VectorRegister  d, Register a);
2129   inline void mfvrd(    Register        a, VectorRegister d);





2130 
2131   // AES (introduced with Power 8)
2132   inline void vcipher(     VectorRegister d, VectorRegister a, VectorRegister b);
2133   inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2134   inline void vncipher(    VectorRegister d, VectorRegister a, VectorRegister b);
2135   inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2136   inline void vsbox(       VectorRegister d, VectorRegister a);
2137 
2138   // SHA (introduced with Power 8)
2139   // Not yet implemented.
2140 
2141   // Vector Binary Polynomial Multiplication (introduced with Power 8)
2142   inline void vpmsumb(  VectorRegister d, VectorRegister a, VectorRegister b);
2143   inline void vpmsumd(  VectorRegister d, VectorRegister a, VectorRegister b);
2144   inline void vpmsumh(  VectorRegister d, VectorRegister a, VectorRegister b);
2145   inline void vpmsumw(  VectorRegister d, VectorRegister a, VectorRegister b);
2146 
2147   // Vector Permute and Xor (introduced with Power 8)
2148   inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2149 




 490     // Vector instruction support for >= Power6
 491     // Vector Storage Access
 492     LVEBX_OPCODE   = (31u << OPCODE_SHIFT |    7u << 1),
 493     LVEHX_OPCODE   = (31u << OPCODE_SHIFT |   39u << 1),
 494     LVEWX_OPCODE   = (31u << OPCODE_SHIFT |   71u << 1),
 495     LVX_OPCODE     = (31u << OPCODE_SHIFT |  103u << 1),
 496     LVXL_OPCODE    = (31u << OPCODE_SHIFT |  359u << 1),
 497     STVEBX_OPCODE  = (31u << OPCODE_SHIFT |  135u << 1),
 498     STVEHX_OPCODE  = (31u << OPCODE_SHIFT |  167u << 1),
 499     STVEWX_OPCODE  = (31u << OPCODE_SHIFT |  199u << 1),
 500     STVX_OPCODE    = (31u << OPCODE_SHIFT |  231u << 1),
 501     STVXL_OPCODE   = (31u << OPCODE_SHIFT |  487u << 1),
 502     LVSL_OPCODE    = (31u << OPCODE_SHIFT |    6u << 1),
 503     LVSR_OPCODE    = (31u << OPCODE_SHIFT |   38u << 1),
 504 
 505     // Vector-Scalar (VSX) instruction support.
 506     LXVD2X_OPCODE  = (31u << OPCODE_SHIFT |  844u << 1),
 507     STXVD2X_OPCODE = (31u << OPCODE_SHIFT |  972u << 1),
 508     MTVSRD_OPCODE  = (31u << OPCODE_SHIFT |  179u << 1),
 509     MFVSRD_OPCODE  = (31u << OPCODE_SHIFT |   51u << 1),
 510     MTVSRWA_OPCODE = (31u << OPCODE_SHIFT |  211u << 1),
 511 
 512     // Vector Permute and Formatting
 513     VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
 514     VPKSHSS_OPCODE = (4u  << OPCODE_SHIFT |  398u     ),
 515     VPKSWSS_OPCODE = (4u  << OPCODE_SHIFT |  462u     ),
 516     VPKSHUS_OPCODE = (4u  << OPCODE_SHIFT |  270u     ),
 517     VPKSWUS_OPCODE = (4u  << OPCODE_SHIFT |  334u     ),
 518     VPKUHUM_OPCODE = (4u  << OPCODE_SHIFT |   14u     ),
 519     VPKUWUM_OPCODE = (4u  << OPCODE_SHIFT |   78u     ),
 520     VPKUHUS_OPCODE = (4u  << OPCODE_SHIFT |  142u     ),
 521     VPKUWUS_OPCODE = (4u  << OPCODE_SHIFT |  206u     ),
 522     VUPKHPX_OPCODE = (4u  << OPCODE_SHIFT |  846u     ),
 523     VUPKHSB_OPCODE = (4u  << OPCODE_SHIFT |  526u     ),
 524     VUPKHSH_OPCODE = (4u  << OPCODE_SHIFT |  590u     ),
 525     VUPKLPX_OPCODE = (4u  << OPCODE_SHIFT |  974u     ),
 526     VUPKLSB_OPCODE = (4u  << OPCODE_SHIFT |  654u     ),
 527     VUPKLSH_OPCODE = (4u  << OPCODE_SHIFT |  718u     ),
 528 
 529     VMRGHB_OPCODE  = (4u  << OPCODE_SHIFT |   12u     ),
 530     VMRGHW_OPCODE  = (4u  << OPCODE_SHIFT |  140u     ),


2111   inline void vslb(     VectorRegister d, VectorRegister a, VectorRegister b);
2112   inline void vskw(     VectorRegister d, VectorRegister a, VectorRegister b);
2113   inline void vslh(     VectorRegister d, VectorRegister a, VectorRegister b);
2114   inline void vsrb(     VectorRegister d, VectorRegister a, VectorRegister b);
2115   inline void vsrw(     VectorRegister d, VectorRegister a, VectorRegister b);
2116   inline void vsrh(     VectorRegister d, VectorRegister a, VectorRegister b);
2117   inline void vsrab(    VectorRegister d, VectorRegister a, VectorRegister b);
2118   inline void vsraw(    VectorRegister d, VectorRegister a, VectorRegister b);
2119   inline void vsrah(    VectorRegister d, VectorRegister a, VectorRegister b);
2120   // Vector Floating-Point not implemented yet
2121   inline void mtvscr(   VectorRegister b);
2122   inline void mfvscr(   VectorRegister d);
2123 
2124   // Vector-Scalar (VSX) instructions.
2125   inline void lxvd2x(   VectorSRegister d, Register a);
2126   inline void lxvd2x(   VectorSRegister d, Register a, Register b);
2127   inline void stxvd2x(  VectorSRegister d, Register a);
2128   inline void stxvd2x(  VectorSRegister d, Register a, Register b);
2129   inline void mtvrd(    VectorRegister  d, Register a);
2130   inline void mfvrd(    Register        a, VectorRegister d);
2131 
2132   // Vector-Scalar (VSX) instructions.
2133   inline void mtfprd(   FloatRegister   d, Register a);
2134   inline void mtfprwa(  FloatRegister   d, Register a);
2135   inline void mffprd(   Register        a, FloatRegister d);
2136 
2137   // AES (introduced with Power 8)
2138   inline void vcipher(     VectorRegister d, VectorRegister a, VectorRegister b);
2139   inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2140   inline void vncipher(    VectorRegister d, VectorRegister a, VectorRegister b);
2141   inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2142   inline void vsbox(       VectorRegister d, VectorRegister a);
2143 
2144   // SHA (introduced with Power 8)
2145   // Not yet implemented.
2146 
2147   // Vector Binary Polynomial Multiplication (introduced with Power 8)
2148   inline void vpmsumb(  VectorRegister d, VectorRegister a, VectorRegister b);
2149   inline void vpmsumd(  VectorRegister d, VectorRegister a, VectorRegister b);
2150   inline void vpmsumh(  VectorRegister d, VectorRegister a, VectorRegister b);
2151   inline void vpmsumw(  VectorRegister d, VectorRegister a, VectorRegister b);
2152 
2153   // Vector Permute and Xor (introduced with Power 8)
2154   inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2155 


< prev index next >