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src/cpu/ppc/vm/assembler_ppc.hpp
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@@ -505,10 +505,11 @@
// Vector-Scalar (VSX) instruction support.
LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
+ MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
// Vector Permute and Formatting
VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
@@ -2126,10 +2127,15 @@
inline void stxvd2x( VectorSRegister d, Register a);
inline void stxvd2x( VectorSRegister d, Register a, Register b);
inline void mtvrd( VectorRegister d, Register a);
inline void mfvrd( Register a, VectorRegister d);
+ // Vector-Scalar (VSX) instructions.
+ inline void mtfprd( FloatRegister d, Register a);
+ inline void mtfprwa( FloatRegister d, Register a);
+ inline void mffprd( Register a, FloatRegister d);
+
// AES (introduced with Power 8)
inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
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