1 //
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   3 // Copyright (c) 2012, 2016 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
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  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 //
  25 
  26 //
  27 // PPC64 Architecture Description File
  28 //
  29 
  30 //----------REGISTER DEFINITION BLOCK------------------------------------------
  31 // This information is used by the matcher and the register allocator to
  32 // describe individual registers and classes of registers within the target
  33 // architecture.
  34 register %{
  35 //----------Architecture Description Register Definitions----------------------
  36 // General Registers
  37 // "reg_def"  name (register save type, C convention save type,
  38 //                  ideal register type, encoding);
  39 //
  40 // Register Save Types:
  41 //
  42 //   NS  = No-Save:     The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method, &
  44 //                      that they do not need to be saved at call sites.
  45 //
  46 //   SOC = Save-On-Call: The register allocator assumes that these registers
  47 //                      can be used without saving upon entry to the method,
  48 //                      but that they must be saved at call sites.
  49 //                      These are called "volatiles" on ppc.
  50 //
  51 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, but they do not need to be saved at call
  54 //                      sites.
  55 //                      These are called "nonvolatiles" on ppc.
  56 //
  57 //   AS  = Always-Save:   The register allocator assumes that these registers
  58 //                      must be saved before using them upon entry to the
  59 //                      method, & that they must be saved at call sites.
  60 //
  61 // Ideal Register Type is used to determine how to save & restore a
  62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  64 //
  65 // The encoding number is the actual bit-pattern placed into the opcodes.
  66 //
  67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
  68 // Supplement Version 1.7 as of 2003-10-29.
  69 //
  70 // For each 64-bit register we must define two registers: the register
  71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
  72 // e.g. R3_H, which is needed by the allocator, but is not used
  73 // for stores, loads, etc.
  74 
  75 // ----------------------------
  76 // Integer/Long Registers
  77 // ----------------------------
  78 
  79   // PPC64 has 32 64-bit integer registers.
  80 
  81   // types: v = volatile, nv = non-volatile, s = system
  82   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs
  83   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
  84   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP
  85   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );
  86   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC
  87   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
  88   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret
  89   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
  90   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2
  91   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
  92   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3
  93   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
  94   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4
  95   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
  96   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5
  97   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
  98   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6
  99   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
 100   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7
 101   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
 102   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8
 103   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
 104   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch
 105   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
 106   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch
 107   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
 108   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id
 109   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());
 110   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv
 111   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
 112   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv
 113   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
 114   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv
 115   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
 116   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv
 117   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
 118   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv
 119   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
 120   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv
 121   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
 122   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv
 123   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
 124   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv
 125   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
 126   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv
 127   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
 128   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv
 129   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
 130   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv
 131   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
 132   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv
 133   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
 134   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv
 135   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
 136   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv
 137   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
 138   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv
 139   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
 140   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv
 141   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
 142   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv
 143   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
 144   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv
 145   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
 146 
 147 
 148 // ----------------------------
 149 // Float/Double Registers
 150 // ----------------------------
 151 
 152   // Double Registers
 153   // The rules of ADL require that double registers be defined in pairs.
 154   // Each pair must be two 32-bit values, but not necessarily a pair of
 155   // single float registers. In each pair, ADLC-assigned register numbers
 156   // must be adjacent, with the lower number even. Finally, when the
 157   // CPU stores such a register pair to memory, the word associated with
 158   // the lower ADLC-assigned number must be stored to the lower address.
 159 
 160   // PPC64 has 32 64-bit floating-point registers. Each can store a single
 161   // or double precision floating-point value.
 162 
 163   // types: v = volatile, nv = non-volatile, s = system
 164   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch
 165   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
 166   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret
 167   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
 168   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2
 169   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
 170   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3
 171   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
 172   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4
 173   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
 174   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5
 175   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
 176   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6
 177   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
 178   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7
 179   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
 180   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8
 181   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
 182   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9
 183   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
 184   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10
 185   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
 186   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11
 187   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
 188   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12
 189   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
 190   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13
 191   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
 192   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv
 193   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
 194   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv
 195   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
 196   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv
 197   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
 198   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv
 199   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
 200   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv
 201   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
 202   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv
 203   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
 204   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv
 205   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
 206   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv
 207   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
 208   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv
 209   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
 210   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv
 211   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
 212   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv
 213   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
 214   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv
 215   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
 216   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv
 217   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
 218   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv
 219   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
 220   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv
 221   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
 222   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv
 223   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
 224   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv
 225   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
 226   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv
 227   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
 228 
 229 // ----------------------------
 230 // Special Registers
 231 // ----------------------------
 232 
 233 // Condition Codes Flag Registers
 234 
 235   // PPC64 has 8 condition code "registers" which are all contained
 236   // in the CR register.
 237 
 238   // types: v = volatile, nv = non-volatile, s = system
 239   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v
 240   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v
 241   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv
 242   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv
 243   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv
 244   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v
 245   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v
 246   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v
 247 
 248   // Special registers of PPC64
 249 
 250   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v
 251   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v
 252   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v
 253   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v
 254   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
 255   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v
 256 
 257 
 258 // ----------------------------
 259 // Specify priority of register selection within phases of register
 260 // allocation. Highest priority is first. A useful heuristic is to
 261 // give registers a low priority when they are required by machine
 262 // instructions, like EAX and EDX on I486, and choose no-save registers
 263 // before save-on-call, & save-on-call before save-on-entry. Registers
 264 // which participate in fixed calling sequences should come last.
 265 // Registers which are used as pairs must fall on an even boundary.
 266 
 267 // It's worth about 1% on SPEC geomean to get this right.
 268 
 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
 271 // R3_num. Therefore, R3_num may not be (and in reality is not)
 272 // the same as R3->encoding()! Furthermore, we cannot make any
 273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
 274 // Additionally, the function
 275 //   static enum RC rc_class(OptoReg::Name reg )
 276 // maps a given <register>_num value to its chunk type (except for flags)
 277 // and its current implementation relies on chunk0 and chunk1 having a
 278 // size of 64 each.
 279 
 280 // If you change this allocation class, please have a look at the
 281 // default values for the parameters RoundRobinIntegerRegIntervalStart
 282 // and RoundRobinFloatRegIntervalStart
 283 
 284 alloc_class chunk0 (
 285   // Chunk0 contains *all* 64 integer registers halves.
 286 
 287   // "non-volatile" registers
 288   R14, R14_H,
 289   R15, R15_H,
 290   R17, R17_H,
 291   R18, R18_H,
 292   R19, R19_H,
 293   R20, R20_H,
 294   R21, R21_H,
 295   R22, R22_H,
 296   R23, R23_H,
 297   R24, R24_H,
 298   R25, R25_H,
 299   R26, R26_H,
 300   R27, R27_H,
 301   R28, R28_H,
 302   R29, R29_H,
 303   R30, R30_H,
 304   R31, R31_H,
 305 
 306   // scratch/special registers
 307   R11, R11_H,
 308   R12, R12_H,
 309 
 310   // argument registers
 311   R10, R10_H,
 312   R9,  R9_H,
 313   R8,  R8_H,
 314   R7,  R7_H,
 315   R6,  R6_H,
 316   R5,  R5_H,
 317   R4,  R4_H,
 318   R3,  R3_H,
 319 
 320   // special registers, not available for allocation
 321   R16, R16_H,     // R16_thread
 322   R13, R13_H,     // system thread id
 323   R2,  R2_H,      // may be used for TOC
 324   R1,  R1_H,      // SP
 325   R0,  R0_H       // R0 (scratch)
 326 );
 327 
 328 // If you change this allocation class, please have a look at the
 329 // default values for the parameters RoundRobinIntegerRegIntervalStart
 330 // and RoundRobinFloatRegIntervalStart
 331 
 332 alloc_class chunk1 (
 333   // Chunk1 contains *all* 64 floating-point registers halves.
 334 
 335   // scratch register
 336   F0,  F0_H,
 337 
 338   // argument registers
 339   F13, F13_H,
 340   F12, F12_H,
 341   F11, F11_H,
 342   F10, F10_H,
 343   F9,  F9_H,
 344   F8,  F8_H,
 345   F7,  F7_H,
 346   F6,  F6_H,
 347   F5,  F5_H,
 348   F4,  F4_H,
 349   F3,  F3_H,
 350   F2,  F2_H,
 351   F1,  F1_H,
 352 
 353   // non-volatile registers
 354   F14, F14_H,
 355   F15, F15_H,
 356   F16, F16_H,
 357   F17, F17_H,
 358   F18, F18_H,
 359   F19, F19_H,
 360   F20, F20_H,
 361   F21, F21_H,
 362   F22, F22_H,
 363   F23, F23_H,
 364   F24, F24_H,
 365   F25, F25_H,
 366   F26, F26_H,
 367   F27, F27_H,
 368   F28, F28_H,
 369   F29, F29_H,
 370   F30, F30_H,
 371   F31, F31_H
 372 );
 373 
 374 alloc_class chunk2 (
 375   // Chunk2 contains *all* 8 condition code registers.
 376 
 377   CCR0,
 378   CCR1,
 379   CCR2,
 380   CCR3,
 381   CCR4,
 382   CCR5,
 383   CCR6,
 384   CCR7
 385 );
 386 
 387 alloc_class chunk3 (
 388   // special registers
 389   // These registers are not allocated, but used for nodes generated by postalloc expand.
 390   SR_XER,
 391   SR_LR,
 392   SR_CTR,
 393   SR_VRSAVE,
 394   SR_SPEFSCR,
 395   SR_PPR
 396 );
 397 
 398 //-------Architecture Description Register Classes-----------------------
 399 
 400 // Several register classes are automatically defined based upon
 401 // information in this architecture description.
 402 
 403 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 404 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )
 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 407 //
 408 
 409 // ----------------------------
 410 // 32 Bit Register Classes
 411 // ----------------------------
 412 
 413 // We specify registers twice, once as read/write, and once read-only.
 414 // We use the read-only registers for source operands. With this, we
 415 // can include preset read only registers in this class, as a hard-coded
 416 // '0'-register. (We used to simulate this on ppc.)
 417 
 418 // 32 bit registers that can be read and written i.e. these registers
 419 // can be dest (or src) of normal instructions.
 420 reg_class bits32_reg_rw(
 421 /*R0*/              // R0
 422 /*R1*/              // SP
 423   R2,               // TOC
 424   R3,
 425   R4,
 426   R5,
 427   R6,
 428   R7,
 429   R8,
 430   R9,
 431   R10,
 432   R11,
 433   R12,
 434 /*R13*/             // system thread id
 435   R14,
 436   R15,
 437 /*R16*/             // R16_thread
 438   R17,
 439   R18,
 440   R19,
 441   R20,
 442   R21,
 443   R22,
 444   R23,
 445   R24,
 446   R25,
 447   R26,
 448   R27,
 449   R28,
 450 /*R29,*/             // global TOC
 451   R30,
 452   R31
 453 );
 454 
 455 // 32 bit registers that can only be read i.e. these registers can
 456 // only be src of all instructions.
 457 reg_class bits32_reg_ro(
 458 /*R0*/              // R0
 459 /*R1*/              // SP
 460   R2                // TOC
 461   R3,
 462   R4,
 463   R5,
 464   R6,
 465   R7,
 466   R8,
 467   R9,
 468   R10,
 469   R11,
 470   R12,
 471 /*R13*/             // system thread id
 472   R14,
 473   R15,
 474 /*R16*/             // R16_thread
 475   R17,
 476   R18,
 477   R19,
 478   R20,
 479   R21,
 480   R22,
 481   R23,
 482   R24,
 483   R25,
 484   R26,
 485   R27,
 486   R28,
 487 /*R29,*/
 488   R30,
 489   R31
 490 );
 491 
 492 reg_class rscratch1_bits32_reg(R11);
 493 reg_class rscratch2_bits32_reg(R12);
 494 reg_class rarg1_bits32_reg(R3);
 495 reg_class rarg2_bits32_reg(R4);
 496 reg_class rarg3_bits32_reg(R5);
 497 reg_class rarg4_bits32_reg(R6);
 498 
 499 // ----------------------------
 500 // 64 Bit Register Classes
 501 // ----------------------------
 502 // 64-bit build means 64-bit pointers means hi/lo pairs
 503 
 504 reg_class rscratch1_bits64_reg(R11_H, R11);
 505 reg_class rscratch2_bits64_reg(R12_H, R12);
 506 reg_class rarg1_bits64_reg(R3_H, R3);
 507 reg_class rarg2_bits64_reg(R4_H, R4);
 508 reg_class rarg3_bits64_reg(R5_H, R5);
 509 reg_class rarg4_bits64_reg(R6_H, R6);
 510 // Thread register, 'written' by tlsLoadP, see there.
 511 reg_class thread_bits64_reg(R16_H, R16);
 512 
 513 reg_class r19_bits64_reg(R19_H, R19);
 514 
 515 // 64 bit registers that can be read and written i.e. these registers
 516 // can be dest (or src) of normal instructions.
 517 reg_class bits64_reg_rw(
 518 /*R0_H,  R0*/     // R0
 519 /*R1_H,  R1*/     // SP
 520   R2_H,  R2,      // TOC
 521   R3_H,  R3,
 522   R4_H,  R4,
 523   R5_H,  R5,
 524   R6_H,  R6,
 525   R7_H,  R7,
 526   R8_H,  R8,
 527   R9_H,  R9,
 528   R10_H, R10,
 529   R11_H, R11,
 530   R12_H, R12,
 531 /*R13_H, R13*/   // system thread id
 532   R14_H, R14,
 533   R15_H, R15,
 534 /*R16_H, R16*/   // R16_thread
 535   R17_H, R17,
 536   R18_H, R18,
 537   R19_H, R19,
 538   R20_H, R20,
 539   R21_H, R21,
 540   R22_H, R22,
 541   R23_H, R23,
 542   R24_H, R24,
 543   R25_H, R25,
 544   R26_H, R26,
 545   R27_H, R27,
 546   R28_H, R28,
 547 /*R29_H, R29,*/
 548   R30_H, R30,
 549   R31_H, R31
 550 );
 551 
 552 // 64 bit registers used excluding r2, r11 and r12
 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
 554 // r2, r11 and r12 internally.
 555 reg_class bits64_reg_leaf_call(
 556 /*R0_H,  R0*/     // R0
 557 /*R1_H,  R1*/     // SP
 558 /*R2_H,  R2*/     // TOC
 559   R3_H,  R3,
 560   R4_H,  R4,
 561   R5_H,  R5,
 562   R6_H,  R6,
 563   R7_H,  R7,
 564   R8_H,  R8,
 565   R9_H,  R9,
 566   R10_H, R10,
 567 /*R11_H, R11*/
 568 /*R12_H, R12*/
 569 /*R13_H, R13*/   // system thread id
 570   R14_H, R14,
 571   R15_H, R15,
 572 /*R16_H, R16*/   // R16_thread
 573   R17_H, R17,
 574   R18_H, R18,
 575   R19_H, R19,
 576   R20_H, R20,
 577   R21_H, R21,
 578   R22_H, R22,
 579   R23_H, R23,
 580   R24_H, R24,
 581   R25_H, R25,
 582   R26_H, R26,
 583   R27_H, R27,
 584   R28_H, R28,
 585 /*R29_H, R29,*/
 586   R30_H, R30,
 587   R31_H, R31
 588 );
 589 
 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
 591 // which uses r19 as inline cache internally and expanded LeafCall which uses
 592 // r2, r11 and r12 internally.
 593 reg_class bits64_constant_table_base(
 594 /*R0_H,  R0*/     // R0
 595 /*R1_H,  R1*/     // SP
 596 /*R2_H,  R2*/     // TOC
 597   R3_H,  R3,
 598   R4_H,  R4,
 599   R5_H,  R5,
 600   R6_H,  R6,
 601   R7_H,  R7,
 602   R8_H,  R8,
 603   R9_H,  R9,
 604   R10_H, R10,
 605 /*R11_H, R11*/
 606 /*R12_H, R12*/
 607 /*R13_H, R13*/   // system thread id
 608   R14_H, R14,
 609   R15_H, R15,
 610 /*R16_H, R16*/   // R16_thread
 611   R17_H, R17,
 612   R18_H, R18,
 613 /*R19_H, R19*/
 614   R20_H, R20,
 615   R21_H, R21,
 616   R22_H, R22,
 617   R23_H, R23,
 618   R24_H, R24,
 619   R25_H, R25,
 620   R26_H, R26,
 621   R27_H, R27,
 622   R28_H, R28,
 623 /*R29_H, R29,*/
 624   R30_H, R30,
 625   R31_H, R31
 626 );
 627 
 628 // 64 bit registers that can only be read i.e. these registers can
 629 // only be src of all instructions.
 630 reg_class bits64_reg_ro(
 631 /*R0_H,  R0*/     // R0
 632   R1_H,  R1,
 633   R2_H,  R2,       // TOC
 634   R3_H,  R3,
 635   R4_H,  R4,
 636   R5_H,  R5,
 637   R6_H,  R6,
 638   R7_H,  R7,
 639   R8_H,  R8,
 640   R9_H,  R9,
 641   R10_H, R10,
 642   R11_H, R11,
 643   R12_H, R12,
 644 /*R13_H, R13*/   // system thread id
 645   R14_H, R14,
 646   R15_H, R15,
 647   R16_H, R16,    // R16_thread
 648   R17_H, R17,
 649   R18_H, R18,
 650   R19_H, R19,
 651   R20_H, R20,
 652   R21_H, R21,
 653   R22_H, R22,
 654   R23_H, R23,
 655   R24_H, R24,
 656   R25_H, R25,
 657   R26_H, R26,
 658   R27_H, R27,
 659   R28_H, R28,
 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
 661   R30_H, R30,
 662   R31_H, R31
 663 );
 664 
 665 
 666 // ----------------------------
 667 // Special Class for Condition Code Flags Register
 668 
 669 reg_class int_flags(
 670 /*CCR0*/             // scratch
 671 /*CCR1*/             // scratch
 672 /*CCR2*/             // nv!
 673 /*CCR3*/             // nv!
 674 /*CCR4*/             // nv!
 675   CCR5,
 676   CCR6,
 677   CCR7
 678 );
 679 
 680 reg_class int_flags_ro(
 681   CCR0,
 682   CCR1,
 683   CCR2,
 684   CCR3,
 685   CCR4,
 686   CCR5,
 687   CCR6,
 688   CCR7
 689 );
 690 
 691 reg_class int_flags_CR0(CCR0);
 692 reg_class int_flags_CR1(CCR1);
 693 reg_class int_flags_CR6(CCR6);
 694 reg_class ctr_reg(SR_CTR);
 695 
 696 // ----------------------------
 697 // Float Register Classes
 698 // ----------------------------
 699 
 700 reg_class flt_reg(
 701   F0,
 702   F1,
 703   F2,
 704   F3,
 705   F4,
 706   F5,
 707   F6,
 708   F7,
 709   F8,
 710   F9,
 711   F10,
 712   F11,
 713   F12,
 714   F13,
 715   F14,              // nv!
 716   F15,              // nv!
 717   F16,              // nv!
 718   F17,              // nv!
 719   F18,              // nv!
 720   F19,              // nv!
 721   F20,              // nv!
 722   F21,              // nv!
 723   F22,              // nv!
 724   F23,              // nv!
 725   F24,              // nv!
 726   F25,              // nv!
 727   F26,              // nv!
 728   F27,              // nv!
 729   F28,              // nv!
 730   F29,              // nv!
 731   F30,              // nv!
 732   F31               // nv!
 733 );
 734 
 735 // Double precision float registers have virtual `high halves' that
 736 // are needed by the allocator.
 737 reg_class dbl_reg(
 738   F0,  F0_H,
 739   F1,  F1_H,
 740   F2,  F2_H,
 741   F3,  F3_H,
 742   F4,  F4_H,
 743   F5,  F5_H,
 744   F6,  F6_H,
 745   F7,  F7_H,
 746   F8,  F8_H,
 747   F9,  F9_H,
 748   F10, F10_H,
 749   F11, F11_H,
 750   F12, F12_H,
 751   F13, F13_H,
 752   F14, F14_H,    // nv!
 753   F15, F15_H,    // nv!
 754   F16, F16_H,    // nv!
 755   F17, F17_H,    // nv!
 756   F18, F18_H,    // nv!
 757   F19, F19_H,    // nv!
 758   F20, F20_H,    // nv!
 759   F21, F21_H,    // nv!
 760   F22, F22_H,    // nv!
 761   F23, F23_H,    // nv!
 762   F24, F24_H,    // nv!
 763   F25, F25_H,    // nv!
 764   F26, F26_H,    // nv!
 765   F27, F27_H,    // nv!
 766   F28, F28_H,    // nv!
 767   F29, F29_H,    // nv!
 768   F30, F30_H,    // nv!
 769   F31, F31_H     // nv!
 770 );
 771 
 772  %}
 773 
 774 //----------DEFINITION BLOCK---------------------------------------------------
 775 // Define name --> value mappings to inform the ADLC of an integer valued name
 776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 777 // Format:
 778 //        int_def  <name>         ( <int_value>, <expression>);
 779 // Generated Code in ad_<arch>.hpp
 780 //        #define  <name>   (<expression>)
 781 //        // value == <int_value>
 782 // Generated code in ad_<arch>.cpp adlc_verification()
 783 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 784 //
 785 definitions %{
 786   // The default cost (of an ALU instruction).
 787   int_def DEFAULT_COST_LOW        (     30,      30);
 788   int_def DEFAULT_COST            (    100,     100);
 789   int_def HUGE_COST               (1000000, 1000000);
 790 
 791   // Memory refs
 792   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);
 793   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);
 794 
 795   // Branches are even more expensive.
 796   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);
 797   int_def CALL_COST               (   1300, DEFAULT_COST * 13);
 798 %}
 799 
 800 
 801 //----------SOURCE BLOCK-------------------------------------------------------
 802 // This is a block of C++ code which provides values, functions, and
 803 // definitions necessary in the rest of the architecture description.
 804 source_hpp %{
 805   // Header information of the source block.
 806   // Method declarations/definitions which are used outside
 807   // the ad-scope can conveniently be defined here.
 808   //
 809   // To keep related declarations/definitions/uses close together,
 810   // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 811 
 812   // Returns true if Node n is followed by a MemBar node that
 813   // will do an acquire. If so, this node must not do the acquire
 814   // operation.
 815   bool followed_by_acquire(const Node *n);
 816 %}
 817 
 818 source %{
 819 
 820 // Should the Matcher clone shifts on addressing modes, expecting them
 821 // to be subsumed into complex addressing expressions or compute them
 822 // into registers?
 823 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 824   return clone_base_plus_offset_address(m, mstack, address_visited);
 825 }
 826 
 827 void Compile::reshape_address(AddPNode* addp) {
 828 }
 829 
 830 // Optimize load-acquire.
 831 //
 832 // Check if acquire is unnecessary due to following operation that does
 833 // acquire anyways.
 834 // Walk the pattern:
 835 //
 836 //      n: Load.acq
 837 //           |
 838 //      MemBarAcquire
 839 //       |         |
 840 //  Proj(ctrl)  Proj(mem)
 841 //       |         |
 842 //   MemBarRelease/Volatile
 843 //
 844 bool followed_by_acquire(const Node *load) {
 845   assert(load->is_Load(), "So far implemented only for loads.");
 846 
 847   // Find MemBarAcquire.
 848   const Node *mba = NULL;
 849   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
 850     const Node *out = load->fast_out(i);
 851     if (out->Opcode() == Op_MemBarAcquire) {
 852       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
 853       mba = out;
 854       break;
 855     }
 856   }
 857   if (!mba) return false;
 858 
 859   // Find following MemBar node.
 860   //
 861   // The following node must be reachable by control AND memory
 862   // edge to assure no other operations are in between the two nodes.
 863   //
 864   // So first get the Proj node, mem_proj, to use it to iterate forward.
 865   Node *mem_proj = NULL;
 866   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
 867     mem_proj = mba->fast_out(i);      // Throw out-of-bounds if proj not found
 868     assert(mem_proj->is_Proj(), "only projections here");
 869     ProjNode *proj = mem_proj->as_Proj();
 870     if (proj->_con == TypeFunc::Memory &&
 871         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
 872       break;
 873   }
 874   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
 875 
 876   // Search MemBar behind Proj. If there are other memory operations
 877   // behind the Proj we lost.
 878   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
 879     Node *x = mem_proj->fast_out(j);
 880     // Proj might have an edge to a store or load node which precedes the membar.
 881     if (x->is_Mem()) return false;
 882 
 883     // On PPC64 release and volatile are implemented by an instruction
 884     // that also has acquire semantics. I.e. there is no need for an
 885     // acquire before these.
 886     int xop = x->Opcode();
 887     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
 888       // Make sure we're not missing Call/Phi/MergeMem by checking
 889       // control edges. The control edge must directly lead back
 890       // to the MemBarAcquire
 891       Node *ctrl_proj = x->in(0);
 892       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
 893         return true;
 894       }
 895     }
 896   }
 897 
 898   return false;
 899 }
 900 
 901 #define __ _masm.
 902 
 903 // Tertiary op of a LoadP or StoreP encoding.
 904 #define REGP_OP true
 905 
 906 // ****************************************************************************
 907 
 908 // REQUIRED FUNCTIONALITY
 909 
 910 // !!!!! Special hack to get all type of calls to specify the byte offset
 911 //       from the start of the call to the point where the return address
 912 //       will point.
 913 
 914 // PPC port: Removed use of lazy constant construct.
 915 
 916 int MachCallStaticJavaNode::ret_addr_offset() {
 917   // It's only a single branch-and-link instruction.
 918   return 4;
 919 }
 920 
 921 int MachCallDynamicJavaNode::ret_addr_offset() {
 922   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
 923   // postalloc expanded calls if we use inline caches and do not update method data.
 924   if (UseInlineCaches)
 925     return 4;
 926 
 927   int vtable_index = this->_vtable_index;
 928   if (vtable_index < 0) {
 929     // Must be invalid_vtable_index, not nonvirtual_vtable_index.
 930     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 931     return 12;
 932   } else {
 933     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 934     return 24;
 935   }
 936 }
 937 
 938 int MachCallRuntimeNode::ret_addr_offset() {
 939 #if defined(ABI_ELFv2)
 940   return 28;
 941 #else
 942   return 40;
 943 #endif
 944 }
 945 
 946 //=============================================================================
 947 
 948 // condition code conversions
 949 
 950 static int cc_to_boint(int cc) {
 951   return Assembler::bcondCRbiIs0 | (cc & 8);
 952 }
 953 
 954 static int cc_to_inverse_boint(int cc) {
 955   return Assembler::bcondCRbiIs0 | (8-(cc & 8));
 956 }
 957 
 958 static int cc_to_biint(int cc, int flags_reg) {
 959   return (flags_reg << 2) | (cc & 3);
 960 }
 961 
 962 //=============================================================================
 963 
 964 // Compute padding required for nodes which need alignment. The padding
 965 // is the number of bytes (not instructions) which will be inserted before
 966 // the instruction. The padding must match the size of a NOP instruction.
 967 
 968 // Currently not used on this platform.
 969 
 970 //=============================================================================
 971 
 972 // Indicate if the safepoint node needs the polling page as an input.
 973 bool SafePointNode::needs_polling_address_input() {
 974   // The address is loaded from thread by a seperate node.
 975   return true;
 976 }
 977 
 978 //=============================================================================
 979 
 980 // Emit an interrupt that is caught by the debugger (for debugging compiler).
 981 void emit_break(CodeBuffer &cbuf) {
 982   MacroAssembler _masm(&cbuf);
 983   __ illtrap();
 984 }
 985 
 986 #ifndef PRODUCT
 987 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 988   st->print("BREAKPOINT");
 989 }
 990 #endif
 991 
 992 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 993   emit_break(cbuf);
 994 }
 995 
 996 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 997   return MachNode::size(ra_);
 998 }
 999 
1000 //=============================================================================
1001 
1002 void emit_nop(CodeBuffer &cbuf) {
1003   MacroAssembler _masm(&cbuf);
1004   __ nop();
1005 }
1006 
1007 static inline void emit_long(CodeBuffer &cbuf, int value) {
1008   *((int*)(cbuf.insts_end())) = value;
1009   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1010 }
1011 
1012 //=============================================================================
1013 
1014 %} // interrupt source
1015 
1016 source_hpp %{ // Header information of the source block.
1017 
1018 //--------------------------------------------------------------
1019 //---<  Used for optimization in Compile::Shorten_branches  >---
1020 //--------------------------------------------------------------
1021 
1022 class CallStubImpl {
1023 
1024  public:
1025 
1026   // Emit call stub, compiled java to interpreter.
1027   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1028 
1029   // Size of call trampoline stub.
1030   // This doesn't need to be accurate to the byte, but it
1031   // must be larger than or equal to the real size of the stub.
1032   static uint size_call_trampoline() {
1033     return MacroAssembler::trampoline_stub_size;
1034   }
1035 
1036   // number of relocations needed by a call trampoline stub
1037   static uint reloc_call_trampoline() {
1038     return 5;
1039   }
1040 
1041 };
1042 
1043 %} // end source_hpp
1044 
1045 source %{
1046 
1047 // Emit a trampoline stub for a call to a target which is too far away.
1048 //
1049 // code sequences:
1050 //
1051 // call-site:
1052 //   branch-and-link to <destination> or <trampoline stub>
1053 //
1054 // Related trampoline stub for this call-site in the stub section:
1055 //   load the call target from the constant pool
1056 //   branch via CTR (LR/link still points to the call-site above)
1057 
1058 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1059   address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset);
1060   if (stub == NULL) {
1061     ciEnv::current()->record_out_of_memory_failure();
1062   }
1063 }
1064 
1065 //=============================================================================
1066 
1067 // Emit an inline branch-and-link call and a related trampoline stub.
1068 //
1069 // code sequences:
1070 //
1071 // call-site:
1072 //   branch-and-link to <destination> or <trampoline stub>
1073 //
1074 // Related trampoline stub for this call-site in the stub section:
1075 //   load the call target from the constant pool
1076 //   branch via CTR (LR/link still points to the call-site above)
1077 //
1078 
1079 typedef struct {
1080   int insts_call_instruction_offset;
1081   int ret_addr_offset;
1082 } EmitCallOffsets;
1083 
1084 // Emit a branch-and-link instruction that branches to a trampoline.
1085 // - Remember the offset of the branch-and-link instruction.
1086 // - Add a relocation at the branch-and-link instruction.
1087 // - Emit a branch-and-link.
1088 // - Remember the return pc offset.
1089 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1090   EmitCallOffsets offsets = { -1, -1 };
1091   const int start_offset = __ offset();
1092   offsets.insts_call_instruction_offset = __ offset();
1093 
1094   // No entry point given, use the current pc.
1095   if (entry_point == NULL) entry_point = __ pc();
1096 
1097   // Put the entry point as a constant into the constant pool.
1098   const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
1099   if (entry_point_toc_addr == NULL) {
1100     ciEnv::current()->record_out_of_memory_failure();
1101     return offsets;
1102   }
1103   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1104   
1105   // Emit the trampoline stub which will be related to the branch-and-link below.
1106   CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1107   if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1108   __ relocate(rtype);
1109   
1110   // Note: At this point we do not have the address of the trampoline
1111   // stub, and the entry point might be too far away for bl, so __ pc()
1112   // serves as dummy and the bl will be patched later.
1113   __ bl((address) __ pc());
1114 
1115   offsets.ret_addr_offset = __ offset() - start_offset;
1116 
1117   return offsets;
1118 }
1119 
1120 //=============================================================================
1121 
1122 // Factory for creating loadConL* nodes for large/small constant pool.
1123 
1124 static inline jlong replicate_immF(float con) {
1125   // Replicate float con 2 times and pack into vector.
1126   int val = *((int*)&con);
1127   jlong lval = val;
1128   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1129   return lval;
1130 }
1131 
1132 //=============================================================================
1133 
1134 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1135 int Compile::ConstantTable::calculate_table_base_offset() const {
1136   return 0;  // absolute addressing, no offset
1137 }
1138 
1139 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1140 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1141   iRegPdstOper *op_dst = new iRegPdstOper();
1142   MachNode *m1 = new loadToc_hiNode();
1143   MachNode *m2 = new loadToc_loNode();
1144 
1145   m1->add_req(NULL);
1146   m2->add_req(NULL, m1);
1147   m1->_opnds[0] = op_dst;
1148   m2->_opnds[0] = op_dst;
1149   m2->_opnds[1] = op_dst;
1150   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1151   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1152   nodes->push(m1);
1153   nodes->push(m2);
1154 }
1155 
1156 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1157   // Is postalloc expanded.
1158   ShouldNotReachHere();
1159 }
1160 
1161 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1162   return 0;
1163 }
1164 
1165 #ifndef PRODUCT
1166 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1167   st->print("-- \t// MachConstantBaseNode (empty encoding)");
1168 }
1169 #endif
1170 
1171 //=============================================================================
1172 
1173 #ifndef PRODUCT
1174 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1175   Compile* C = ra_->C;
1176   const long framesize = C->frame_slots() << LogBytesPerInt;
1177 
1178   st->print("PROLOG\n\t");
1179   if (C->need_stack_bang(framesize)) {
1180     st->print("stack_overflow_check\n\t");
1181   }
1182 
1183   if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1184     st->print("save return pc\n\t");
1185     st->print("push frame %ld\n\t", -framesize);
1186   }
1187 }
1188 #endif
1189 
1190 // Macro used instead of the common __ to emulate the pipes of PPC.
1191 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1192 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1193 // still no scheduling of this code is possible, the micro scheduler is aware of the
1194 // code and can update its internal data. The following mechanism is used to achieve this:
1195 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1196 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1197 #if 0 // TODO: PPC port
1198 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1199                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1200                 _masm.
1201 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1202                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1203 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \
1204                   C->hb_scheduling()->_pdScheduling->advance_offset
1205 #else
1206 #define ___(op) if (UsePower6SchedulerPPC64)                                          \
1207                   Unimplemented();                                                    \
1208                 _masm.
1209 #define ___stop if (UsePower6SchedulerPPC64)                                          \
1210                   Unimplemented()
1211 #define ___advance if (UsePower6SchedulerPPC64)                                       \
1212                   Unimplemented()
1213 #endif
1214 
1215 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1216   Compile* C = ra_->C;
1217   MacroAssembler _masm(&cbuf);
1218 
1219   const long framesize = C->frame_size_in_bytes();
1220   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1221 
1222   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1223 
1224   const Register return_pc            = R20; // Must match return_addr() in frame section.
1225   const Register callers_sp           = R21;
1226   const Register push_frame_temp      = R22;
1227   const Register toc_temp             = R23;
1228   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1229 
1230   if (method_is_frameless) {
1231     // Add nop at beginning of all frameless methods to prevent any
1232     // oop instructions from getting overwritten by make_not_entrant
1233     // (patching attempt would fail).
1234     ___(nop) nop();
1235   } else {
1236     // Get return pc.
1237     ___(mflr) mflr(return_pc);
1238   }
1239 
1240   // Calls to C2R adapters often do not accept exceptional returns.
1241   // We require that their callers must bang for them. But be
1242   // careful, because some VM calls (such as call site linkage) can
1243   // use several kilobytes of stack. But the stack safety zone should
1244   // account for that. See bugs 4446381, 4468289, 4497237.
1245 
1246   int bangsize = C->bang_size_in_bytes();
1247   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1248   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1249     // Unfortunately we cannot use the function provided in
1250     // assembler.cpp as we have to emulate the pipes. So I had to
1251     // insert the code of generate_stack_overflow_check(), see
1252     // assembler.cpp for some illuminative comments.
1253     const int page_size = os::vm_page_size();
1254     int bang_end = JavaThread::stack_shadow_zone_size();
1255 
1256     // This is how far the previous frame's stack banging extended.
1257     const int bang_end_safe = bang_end;
1258 
1259     if (bangsize > page_size) {
1260       bang_end += bangsize;
1261     }
1262 
1263     int bang_offset = bang_end_safe;
1264 
1265     while (bang_offset <= bang_end) {
1266       // Need at least one stack bang at end of shadow zone.
1267 
1268       // Again I had to copy code, this time from assembler_ppc.cpp,
1269       // bang_stack_with_offset - see there for comments.
1270 
1271       // Stack grows down, caller passes positive offset.
1272       assert(bang_offset > 0, "must bang with positive offset");
1273 
1274       long stdoffset = -bang_offset;
1275 
1276       if (Assembler::is_simm(stdoffset, 16)) {
1277         // Signed 16 bit offset, a simple std is ok.
1278         if (UseLoadInstructionsForStackBangingPPC64) {
1279           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);
1280         } else {
1281           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1282         }
1283       } else if (Assembler::is_simm(stdoffset, 31)) {
1284         // Use largeoffset calculations for addis & ld/std.
1285         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1286         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1287 
1288         Register tmp = R11;
1289         ___(addis) addis(tmp, R1_SP, hi);
1290         if (UseLoadInstructionsForStackBangingPPC64) {
1291           ___(ld) ld(R0, lo, tmp);
1292         } else {
1293           ___(std) std(R0, lo, tmp);
1294         }
1295       } else {
1296         ShouldNotReachHere();
1297       }
1298 
1299       bang_offset += page_size;
1300     }
1301     // R11 trashed
1302   } // C->need_stack_bang(framesize) && UseStackBanging
1303 
1304   unsigned int bytes = (unsigned int)framesize;
1305   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1306   ciMethod *currMethod = C->method();
1307 
1308   // Optimized version for most common case.
1309   if (UsePower6SchedulerPPC64 &&
1310       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1311       !(false /* ConstantsALot TODO: PPC port*/)) {
1312     ___(or) mr(callers_sp, R1_SP);
1313     ___(std) std(return_pc, _abi(lr), R1_SP);
1314     ___(stdu) stdu(R1_SP, -offset, R1_SP);
1315     return;
1316   }
1317 
1318   if (!method_is_frameless) {
1319     // Get callers sp.
1320     ___(or) mr(callers_sp, R1_SP);
1321 
1322     // Push method's frame, modifies SP.
1323     assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1324     // The ABI is already accounted for in 'framesize' via the
1325     // 'out_preserve' area.
1326     Register tmp = push_frame_temp;
1327     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1328     if (Assembler::is_simm(-offset, 16)) {
1329       ___(stdu) stdu(R1_SP, -offset, R1_SP);
1330     } else {
1331       long x = -offset;
1332       // Had to insert load_const(tmp, -offset).
1333       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1334       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1335       ___(rldicr) sldi(tmp, tmp, 32);
1336       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);
1337       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));
1338 
1339       ___(stdux) stdux(R1_SP, R1_SP, tmp);
1340     }
1341   }
1342 #if 0 // TODO: PPC port
1343   // For testing large constant pools, emit a lot of constants to constant pool.
1344   // "Randomize" const_size.
1345   if (ConstantsALot) {
1346     const int num_consts = const_size();
1347     for (int i = 0; i < num_consts; i++) {
1348       __ long_constant(0xB0B5B00BBABE);
1349     }
1350   }
1351 #endif
1352   if (!method_is_frameless) {
1353     // Save return pc.
1354     ___(std) std(return_pc, _abi(lr), callers_sp);
1355   }
1356   
1357   C->set_frame_complete(cbuf.insts_size());
1358 }
1359 #undef ___
1360 #undef ___stop
1361 #undef ___advance
1362 
1363 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1364   // Variable size. determine dynamically.
1365   return MachNode::size(ra_);
1366 }
1367 
1368 int MachPrologNode::reloc() const {
1369   // Return number of relocatable values contained in this instruction.
1370   return 1; // 1 reloc entry for load_const(toc).
1371 }
1372 
1373 //=============================================================================
1374 
1375 #ifndef PRODUCT
1376 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1377   Compile* C = ra_->C;
1378 
1379   st->print("EPILOG\n\t");
1380   st->print("restore return pc\n\t");
1381   st->print("pop frame\n\t");
1382 
1383   if (do_polling() && C->is_method_compilation()) {
1384     st->print("touch polling page\n\t");
1385   }
1386 }
1387 #endif
1388 
1389 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1390   Compile* C = ra_->C;
1391   MacroAssembler _masm(&cbuf);
1392 
1393   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1394   assert(framesize >= 0, "negative frame-size?");
1395 
1396   const bool method_needs_polling = do_polling() && C->is_method_compilation();
1397   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;
1398   const Register return_pc        = R31;  // Must survive C-call to enable_stack_reserved_zone().
1399   const Register polling_page     = R12;
1400 
1401   if (!method_is_frameless) {
1402     // Restore return pc relative to callers' sp.
1403     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1404   }
1405 
1406   if (method_needs_polling) {
1407     if (LoadPollAddressFromThread) {
1408       // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1409       Unimplemented();
1410     } else {
1411       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1412     }
1413   }
1414 
1415   if (!method_is_frameless) {
1416     // Move return pc to LR.
1417     __ mtlr(return_pc);
1418     // Pop frame (fixed frame-size).
1419     __ addi(R1_SP, R1_SP, (int)framesize);
1420   }
1421 
1422   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1423     __ reserved_stack_check(return_pc);
1424   }
1425 
1426   if (method_needs_polling) {
1427     // We need to mark the code position where the load from the safepoint
1428     // polling page was emitted as relocInfo::poll_return_type here.
1429     __ relocate(relocInfo::poll_return_type);
1430     __ load_from_polling_page(polling_page);
1431   }
1432 }
1433 
1434 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1435   // Variable size. Determine dynamically.
1436   return MachNode::size(ra_);
1437 }
1438 
1439 int MachEpilogNode::reloc() const {
1440   // Return number of relocatable values contained in this instruction.
1441   return 1; // 1 for load_from_polling_page.
1442 }
1443 
1444 const Pipeline * MachEpilogNode::pipeline() const {
1445   return MachNode::pipeline_class();
1446 }
1447 
1448 // This method seems to be obsolete. It is declared in machnode.hpp
1449 // and defined in all *.ad files, but it is never called. Should we
1450 // get rid of it?
1451 int MachEpilogNode::safepoint_offset() const {
1452   assert(do_polling(), "no return for this epilog node");
1453   return 0;
1454 }
1455 
1456 #if 0 // TODO: PPC port
1457 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1458   MacroAssembler _masm(&cbuf);
1459   if (LoadPollAddressFromThread) {
1460     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1461   } else {
1462     _masm.nop();
1463   }
1464 }
1465 
1466 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1467   if (LoadPollAddressFromThread) {
1468     return 4;
1469   } else {
1470     return 4;
1471   }
1472 }
1473 
1474 #ifndef PRODUCT
1475 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1476   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1477 }
1478 #endif
1479 
1480 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1481   return RSCRATCH1_BITS64_REG_mask();
1482 }
1483 #endif // PPC port
1484 
1485 // =============================================================================
1486 
1487 // Figure out which register class each belongs in: rc_int, rc_float or
1488 // rc_stack.
1489 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1490 
1491 static enum RC rc_class(OptoReg::Name reg) {
1492   // Return the register class for the given register. The given register
1493   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1494   // enumeration in adGlobals_ppc.hpp.
1495 
1496   if (reg == OptoReg::Bad) return rc_bad;
1497 
1498   // We have 64 integer register halves, starting at index 0.
1499   if (reg < 64) return rc_int;
1500 
1501   // We have 64 floating-point register halves, starting at index 64.
1502   if (reg < 64+64) return rc_float;
1503 
1504   // Between float regs & stack are the flags regs.
1505   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1506 
1507   return rc_stack;
1508 }
1509 
1510 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1511                         bool do_print, Compile* C, outputStream *st) {
1512 
1513   assert(opcode == Assembler::LD_OPCODE   ||
1514          opcode == Assembler::STD_OPCODE  ||
1515          opcode == Assembler::LWZ_OPCODE  ||
1516          opcode == Assembler::STW_OPCODE  ||
1517          opcode == Assembler::LFD_OPCODE  ||
1518          opcode == Assembler::STFD_OPCODE ||
1519          opcode == Assembler::LFS_OPCODE  ||
1520          opcode == Assembler::STFS_OPCODE,
1521          "opcode not supported");
1522 
1523   if (cbuf) {
1524     int d =
1525       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1526         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1527       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1528     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1529   }
1530 #ifndef PRODUCT
1531   else if (do_print) {
1532     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1533               op_str,
1534               Matcher::regName[reg],
1535               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1536   }
1537 #endif
1538   return 4; // size
1539 }
1540 
1541 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1542   Compile* C = ra_->C;
1543 
1544   // Get registers to move.
1545   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1546   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1547   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1548   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1549 
1550   enum RC src_hi_rc = rc_class(src_hi);
1551   enum RC src_lo_rc = rc_class(src_lo);
1552   enum RC dst_hi_rc = rc_class(dst_hi);
1553   enum RC dst_lo_rc = rc_class(dst_lo);
1554 
1555   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1556   if (src_hi != OptoReg::Bad)
1557     assert((src_lo&1)==0 && src_lo+1==src_hi &&
1558            (dst_lo&1)==0 && dst_lo+1==dst_hi,
1559            "expected aligned-adjacent pairs");
1560   // Generate spill code!
1561   int size = 0;
1562 
1563   if (src_lo == dst_lo && src_hi == dst_hi)
1564     return size;            // Self copy, no move.
1565 
1566   // --------------------------------------
1567   // Memory->Memory Spill. Use R0 to hold the value.
1568   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1569     int src_offset = ra_->reg2offset(src_lo);
1570     int dst_offset = ra_->reg2offset(dst_lo);
1571     if (src_hi != OptoReg::Bad) {
1572       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1573              "expected same type of move for high parts");
1574       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);
1575       if (!cbuf && !do_size) st->print("\n\t");
1576       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1577     } else {
1578       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1579       if (!cbuf && !do_size) st->print("\n\t");
1580       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1581     }
1582     return size;
1583   }
1584 
1585   // --------------------------------------
1586   // Check for float->int copy; requires a trip through memory.
1587   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1588     Unimplemented();
1589   }
1590 
1591   // --------------------------------------
1592   // Check for integer reg-reg copy.
1593   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1594       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1595       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1596       size = (Rsrc != Rdst) ? 4 : 0;
1597 
1598       if (cbuf) {
1599         MacroAssembler _masm(cbuf);
1600         if (size) {
1601           __ mr(Rdst, Rsrc);
1602         }
1603       }
1604 #ifndef PRODUCT
1605       else if (!do_size) {
1606         if (size) {
1607           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1608         } else {
1609           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1610         }
1611       }
1612 #endif
1613       return size;
1614   }
1615 
1616   // Check for integer store.
1617   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1618     int dst_offset = ra_->reg2offset(dst_lo);
1619     if (src_hi != OptoReg::Bad) {
1620       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1621              "expected same type of move for high parts");
1622       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1623     } else {
1624       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1625     }
1626     return size;
1627   }
1628 
1629   // Check for integer load.
1630   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1631     int src_offset = ra_->reg2offset(src_lo);
1632     if (src_hi != OptoReg::Bad) {
1633       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1634              "expected same type of move for high parts");
1635       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1636     } else {
1637       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1638     }
1639     return size;
1640   }
1641 
1642   // Check for float reg-reg copy.
1643   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1644     if (cbuf) {
1645       MacroAssembler _masm(cbuf);
1646       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1647       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1648       __ fmr(Rdst, Rsrc);
1649     }
1650 #ifndef PRODUCT
1651     else if (!do_size) {
1652       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1653     }
1654 #endif
1655     return 4;
1656   }
1657 
1658   // Check for float store.
1659   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1660     int dst_offset = ra_->reg2offset(dst_lo);
1661     if (src_hi != OptoReg::Bad) {
1662       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1663              "expected same type of move for high parts");
1664       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1665     } else {
1666       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1667     }
1668     return size;
1669   }
1670 
1671   // Check for float load.
1672   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1673     int src_offset = ra_->reg2offset(src_lo);
1674     if (src_hi != OptoReg::Bad) {
1675       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1676              "expected same type of move for high parts");
1677       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1678     } else {
1679       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1680     }
1681     return size;
1682   }
1683 
1684   // --------------------------------------------------------------------
1685   // Check for hi bits still needing moving. Only happens for misaligned
1686   // arguments to native calls.
1687   if (src_hi == dst_hi)
1688     return size;               // Self copy; no move.
1689 
1690   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1691   ShouldNotReachHere(); // Unimplemented
1692   return 0;
1693 }
1694 
1695 #ifndef PRODUCT
1696 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1697   if (!ra_)
1698     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1699   else
1700     implementation(NULL, ra_, false, st);
1701 }
1702 #endif
1703 
1704 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1705   implementation(&cbuf, ra_, false, NULL);
1706 }
1707 
1708 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1709   return implementation(NULL, ra_, true, NULL);
1710 }
1711 
1712 #if 0 // TODO: PPC port
1713 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1714 #ifndef PRODUCT
1715   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1716 #endif
1717   assert(ra_->node_regs_max_index() != 0, "");
1718 
1719   // Get registers to move.
1720   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1721   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1722   OptoReg::Name dst_hi = ra_->get_reg_second(n);
1723   OptoReg::Name dst_lo = ra_->get_reg_first(n);
1724 
1725   enum RC src_lo_rc = rc_class(src_lo);
1726   enum RC dst_lo_rc = rc_class(dst_lo);
1727 
1728   if (src_lo == dst_lo && src_hi == dst_hi)
1729     return ppc64Opcode_none;            // Self copy, no move.
1730 
1731   // --------------------------------------
1732   // Memory->Memory Spill. Use R0 to hold the value.
1733   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1734     return ppc64Opcode_compound;
1735   }
1736 
1737   // --------------------------------------
1738   // Check for float->int copy; requires a trip through memory.
1739   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1740     Unimplemented();
1741   }
1742 
1743   // --------------------------------------
1744   // Check for integer reg-reg copy.
1745   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1746     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1747     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1748     if (Rsrc == Rdst) {
1749       return ppc64Opcode_none;
1750     } else {
1751       return ppc64Opcode_or;
1752     }
1753   }
1754 
1755   // Check for integer store.
1756   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1757     if (src_hi != OptoReg::Bad) {
1758       return ppc64Opcode_std;
1759     } else {
1760       return ppc64Opcode_stw;
1761     }
1762   }
1763 
1764   // Check for integer load.
1765   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1766     if (src_hi != OptoReg::Bad) {
1767       return ppc64Opcode_ld;
1768     } else {
1769       return ppc64Opcode_lwz;
1770     }
1771   }
1772 
1773   // Check for float reg-reg copy.
1774   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1775     return ppc64Opcode_fmr;
1776   }
1777 
1778   // Check for float store.
1779   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1780     if (src_hi != OptoReg::Bad) {
1781       return ppc64Opcode_stfd;
1782     } else {
1783       return ppc64Opcode_stfs;
1784     }
1785   }
1786 
1787   // Check for float load.
1788   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1789     if (src_hi != OptoReg::Bad) {
1790       return ppc64Opcode_lfd;
1791     } else {
1792       return ppc64Opcode_lfs;
1793     }
1794   }
1795 
1796   // --------------------------------------------------------------------
1797   // Check for hi bits still needing moving. Only happens for misaligned
1798   // arguments to native calls.
1799   if (src_hi == dst_hi) {
1800     return ppc64Opcode_none;               // Self copy; no move.
1801   }
1802 
1803   ShouldNotReachHere();
1804   return ppc64Opcode_undefined;
1805 }
1806 #endif // PPC port
1807 
1808 #ifndef PRODUCT
1809 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1810   st->print("NOP \t// %d nops to pad for loops.", _count);
1811 }
1812 #endif
1813 
1814 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1815   MacroAssembler _masm(&cbuf);
1816   // _count contains the number of nops needed for padding.
1817   for (int i = 0; i < _count; i++) {
1818     __ nop();
1819   }
1820 }
1821 
1822 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1823   return _count * 4;
1824 }
1825 
1826 #ifndef PRODUCT
1827 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1828   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1829   char reg_str[128];
1830   ra_->dump_register(this, reg_str);
1831   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1832 }
1833 #endif
1834 
1835 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1836   MacroAssembler _masm(&cbuf);
1837 
1838   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1839   int reg    = ra_->get_encode(this);
1840 
1841   if (Assembler::is_simm(offset, 16)) {
1842     __ addi(as_Register(reg), R1, offset);
1843   } else {
1844     ShouldNotReachHere();
1845   }
1846 }
1847 
1848 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1849   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1850   return 4;
1851 }
1852 
1853 #ifndef PRODUCT
1854 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1855   st->print_cr("---- MachUEPNode ----");
1856   st->print_cr("...");
1857 }
1858 #endif
1859 
1860 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1861   // This is the unverified entry point.
1862   MacroAssembler _masm(&cbuf);
1863 
1864   // Inline_cache contains a klass.
1865   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());
1866   Register receiver_klass = R12_scratch2;  // tmp
1867 
1868   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1869   assert(R11_scratch1 == R11, "need prologue scratch register");
1870 
1871   // Check for NULL argument if we don't have implicit null checks.
1872   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1873     if (TrapBasedNullChecks) {
1874       __ trap_null_check(R3_ARG1);
1875     } else {
1876       Label valid;
1877       __ cmpdi(CCR0, R3_ARG1, 0);
1878       __ bne_predict_taken(CCR0, valid);
1879       // We have a null argument, branch to ic_miss_stub.
1880       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1881                            relocInfo::runtime_call_type);
1882       __ bind(valid);
1883     }
1884   }
1885   // Assume argument is not NULL, load klass from receiver.
1886   __ load_klass(receiver_klass, R3_ARG1);
1887 
1888   if (TrapBasedICMissChecks) {
1889     __ trap_ic_miss_check(receiver_klass, ic_klass);
1890   } else {
1891     Label valid;
1892     __ cmpd(CCR0, receiver_klass, ic_klass);
1893     __ beq_predict_taken(CCR0, valid);
1894     // We have an unexpected klass, branch to ic_miss_stub.
1895     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1896                          relocInfo::runtime_call_type);
1897     __ bind(valid);
1898   }
1899 
1900   // Argument is valid and klass is as expected, continue.
1901 }
1902 
1903 #if 0 // TODO: PPC port
1904 // Optimize UEP code on z (save a load_const() call in main path).
1905 int MachUEPNode::ep_offset() {
1906   return 0;
1907 }
1908 #endif
1909 
1910 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1911   // Variable size. Determine dynamically.
1912   return MachNode::size(ra_);
1913 }
1914 
1915 //=============================================================================
1916 
1917 %} // interrupt source
1918 
1919 source_hpp %{ // Header information of the source block.
1920 
1921 class HandlerImpl {
1922 
1923  public:
1924 
1925   static int emit_exception_handler(CodeBuffer &cbuf);
1926   static int emit_deopt_handler(CodeBuffer& cbuf);
1927 
1928   static uint size_exception_handler() {
1929     // The exception_handler is a b64_patchable.
1930     return MacroAssembler::b64_patchable_size;
1931   }
1932 
1933   static uint size_deopt_handler() {
1934     // The deopt_handler is a bl64_patchable.
1935     return MacroAssembler::bl64_patchable_size;
1936   }
1937 
1938 };
1939 
1940 %} // end source_hpp
1941 
1942 source %{
1943 
1944 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1945   MacroAssembler _masm(&cbuf);
1946 
1947   address base = __ start_a_stub(size_exception_handler());
1948   if (base == NULL) return 0; // CodeBuffer::expand failed
1949 
1950   int offset = __ offset();
1951   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
1952                        relocInfo::runtime_call_type);
1953   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
1954   __ end_a_stub();
1955 
1956   return offset;
1957 }
1958 
1959 // The deopt_handler is like the exception handler, but it calls to
1960 // the deoptimization blob instead of jumping to the exception blob.
1961 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1962   MacroAssembler _masm(&cbuf);
1963 
1964   address base = __ start_a_stub(size_deopt_handler());
1965   if (base == NULL) return 0; // CodeBuffer::expand failed
1966 
1967   int offset = __ offset();
1968   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
1969                         relocInfo::runtime_call_type);
1970   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1971   __ end_a_stub();
1972 
1973   return offset;
1974 }
1975 
1976 //=============================================================================
1977 
1978 // Use a frame slots bias for frameless methods if accessing the stack.
1979 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
1980   if (as_Register(reg_enc) == R1_SP) {
1981     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
1982   }
1983   return 0;
1984 }
1985 
1986 const bool Matcher::match_rule_supported(int opcode) {
1987   if (!has_match_rule(opcode))
1988     return false;
1989 
1990   switch (opcode) {
1991   case Op_SqrtD:
1992     return VM_Version::has_fsqrt();
1993   case Op_CountLeadingZerosI:
1994   case Op_CountLeadingZerosL:
1995   case Op_CountTrailingZerosI:
1996   case Op_CountTrailingZerosL:
1997     if (!UseCountLeadingZerosInstructionsPPC64)
1998       return false;
1999     break;
2000 
2001   case Op_PopCountI:
2002   case Op_PopCountL:
2003     return (UsePopCountInstruction && VM_Version::has_popcntw());
2004 
2005   case Op_StrComp:
2006     return SpecialStringCompareTo;
2007   case Op_StrEquals:
2008     return SpecialStringEquals;
2009   case Op_StrIndexOf:
2010     return SpecialStringIndexOf;
2011   case Op_StrIndexOfChar:
2012     return SpecialStringIndexOf;
2013   }
2014 
2015   return true;  // Per default match rules are supported.
2016 }
2017 
2018 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2019 
2020   // TODO
2021   // identify extra cases that we might want to provide match rules for
2022   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2023   bool ret_value = match_rule_supported(opcode);
2024   // Add rules here.
2025 
2026   return ret_value;  // Per default match rules are supported.
2027 }
2028 
2029 const bool Matcher::has_predicated_vectors(void) {
2030   return false;
2031 }
2032 
2033 const int Matcher::float_pressure(int default_pressure_threshold) {
2034   return default_pressure_threshold;
2035 }
2036 
2037 int Matcher::regnum_to_fpu_offset(int regnum) {
2038   // No user for this method?
2039   Unimplemented();
2040   return 999;
2041 }
2042 
2043 const bool Matcher::convL2FSupported(void) {
2044   // fcfids can do the conversion (>= Power7).
2045   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2046   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2047 }
2048 
2049 // Vector width in bytes.
2050 const int Matcher::vector_width_in_bytes(BasicType bt) {
2051   assert(MaxVectorSize == 8, "");
2052   return 8;
2053 }
2054 
2055 // Vector ideal reg.
2056 const int Matcher::vector_ideal_reg(int size) {
2057   assert(MaxVectorSize == 8 && size == 8, "");
2058   return Op_RegL;
2059 }
2060 
2061 const int Matcher::vector_shift_count_ideal_reg(int size) {
2062   fatal("vector shift is not supported");
2063   return Node::NotAMachineReg;
2064 }
2065 
2066 // Limits on vector size (number of elements) loaded into vector.
2067 const int Matcher::max_vector_size(const BasicType bt) {
2068   assert(is_java_primitive(bt), "only primitive type vectors");
2069   return vector_width_in_bytes(bt)/type2aelembytes(bt);
2070 }
2071 
2072 const int Matcher::min_vector_size(const BasicType bt) {
2073   return max_vector_size(bt); // Same as max.
2074 }
2075 
2076 // PPC doesn't support misaligned vectors store/load.
2077 const bool Matcher::misaligned_vectors_ok() {
2078   return false;
2079 }
2080 
2081 // PPC AES support not yet implemented
2082 const bool Matcher::pass_original_key_for_aes() {
2083   return false;
2084 }
2085 
2086 // RETURNS: whether this branch offset is short enough that a short
2087 // branch can be used.
2088 //
2089 // If the platform does not provide any short branch variants, then
2090 // this method should return `false' for offset 0.
2091 //
2092 // `Compile::Fill_buffer' will decide on basis of this information
2093 // whether to do the pass `Compile::Shorten_branches' at all.
2094 //
2095 // And `Compile::Shorten_branches' will decide on basis of this
2096 // information whether to replace particular branch sites by short
2097 // ones.
2098 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2099   // Is the offset within the range of a ppc64 pc relative branch?
2100   bool b;
2101 
2102   const int safety_zone = 3 * BytesPerInstWord;
2103   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2104                          29 - 16 + 1 + 2);
2105   return b;
2106 }
2107 
2108 const bool Matcher::isSimpleConstant64(jlong value) {
2109   // Probably always true, even if a temp register is required.
2110   return true;
2111 }
2112 /* TODO: PPC port
2113 // Make a new machine dependent decode node (with its operands).
2114 MachTypeNode *Matcher::make_decode_node() {
2115   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2116          "This method is only implemented for unscaled cOops mode so far");
2117   MachTypeNode *decode = new decodeN_unscaledNode();
2118   decode->set_opnd_array(0, new iRegPdstOper());
2119   decode->set_opnd_array(1, new iRegNsrcOper());
2120   return decode;
2121 }
2122 */
2123 
2124 // false => size gets scaled to BytesPerLong, ok.
2125 const bool Matcher::init_array_count_is_in_bytes = false;
2126 
2127 // Use conditional move (CMOVL) on Power7.
2128 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2129 
2130 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2131 // fsel doesn't accept a condition register as input, so this would be slightly different.
2132 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2133 
2134 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2135 const bool Matcher::require_postalloc_expand = true;
2136 
2137 // Do we need to mask the count passed to shift instructions or does
2138 // the cpu only look at the lower 5/6 bits anyway?
2139 // PowerPC requires masked shift counts.
2140 const bool Matcher::need_masked_shift_count = true;
2141 
2142 // This affects two different things:
2143 //  - how Decode nodes are matched
2144 //  - how ImplicitNullCheck opportunities are recognized
2145 // If true, the matcher will try to remove all Decodes and match them
2146 // (as operands) into nodes. NullChecks are not prepared to deal with
2147 // Decodes by final_graph_reshaping().
2148 // If false, final_graph_reshaping() forces the decode behind the Cmp
2149 // for a NullCheck. The matcher matches the Decode node into a register.
2150 // Implicit_null_check optimization moves the Decode along with the
2151 // memory operation back up before the NullCheck.
2152 bool Matcher::narrow_oop_use_complex_address() {
2153   // TODO: PPC port if (MatchDecodeNodes) return true;
2154   return false;
2155 }
2156 
2157 bool Matcher::narrow_klass_use_complex_address() {
2158   NOT_LP64(ShouldNotCallThis());
2159   assert(UseCompressedClassPointers, "only for compressed klass code");
2160   // TODO: PPC port if (MatchDecodeNodes) return true;
2161   return false;
2162 }
2163 
2164 bool Matcher::const_oop_prefer_decode() {
2165   // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
2166   return Universe::narrow_oop_base() == NULL;
2167 }
2168 
2169 bool Matcher::const_klass_prefer_decode() {
2170   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
2171   return Universe::narrow_klass_base() == NULL;
2172 }
2173 
2174 // Is it better to copy float constants, or load them directly from memory?
2175 // Intel can load a float constant from a direct address, requiring no
2176 // extra registers. Most RISCs will have to materialize an address into a
2177 // register first, so they would do better to copy the constant from stack.
2178 const bool Matcher::rematerialize_float_constants = false;
2179 
2180 // If CPU can load and store mis-aligned doubles directly then no fixup is
2181 // needed. Else we split the double into 2 integer pieces and move it
2182 // piece-by-piece. Only happens when passing doubles into C code as the
2183 // Java calling convention forces doubles to be aligned.
2184 const bool Matcher::misaligned_doubles_ok = true;
2185 
2186 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2187  Unimplemented();
2188 }
2189 
2190 // Advertise here if the CPU requires explicit rounding operations
2191 // to implement the UseStrictFP mode.
2192 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2193 
2194 // Do floats take an entire double register or just half?
2195 //
2196 // A float occupies a ppc64 double register. For the allocator, a
2197 // ppc64 double register appears as a pair of float registers.
2198 bool Matcher::float_in_double() { return true; }
2199 
2200 // Do ints take an entire long register or just half?
2201 // The relevant question is how the int is callee-saved:
2202 // the whole long is written but de-opt'ing will have to extract
2203 // the relevant 32 bits.
2204 const bool Matcher::int_in_long = true;
2205 
2206 // Constants for c2c and c calling conventions.
2207 
2208 const MachRegisterNumbers iarg_reg[8] = {
2209   R3_num, R4_num, R5_num, R6_num,
2210   R7_num, R8_num, R9_num, R10_num
2211 };
2212 
2213 const MachRegisterNumbers farg_reg[13] = {
2214   F1_num, F2_num, F3_num, F4_num,
2215   F5_num, F6_num, F7_num, F8_num,
2216   F9_num, F10_num, F11_num, F12_num,
2217   F13_num
2218 };
2219 
2220 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2221 
2222 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2223 
2224 // Return whether or not this register is ever used as an argument. This
2225 // function is used on startup to build the trampoline stubs in generateOptoStub.
2226 // Registers not mentioned will be killed by the VM call in the trampoline, and
2227 // arguments in those registers not be available to the callee.
2228 bool Matcher::can_be_java_arg(int reg) {
2229   // We return true for all registers contained in iarg_reg[] and
2230   // farg_reg[] and their virtual halves.
2231   // We must include the virtual halves in order to get STDs and LDs
2232   // instead of STWs and LWs in the trampoline stubs.
2233 
2234   if (   reg == R3_num  || reg == R3_H_num
2235       || reg == R4_num  || reg == R4_H_num
2236       || reg == R5_num  || reg == R5_H_num
2237       || reg == R6_num  || reg == R6_H_num
2238       || reg == R7_num  || reg == R7_H_num
2239       || reg == R8_num  || reg == R8_H_num
2240       || reg == R9_num  || reg == R9_H_num
2241       || reg == R10_num || reg == R10_H_num)
2242     return true;
2243 
2244   if (   reg == F1_num  || reg == F1_H_num
2245       || reg == F2_num  || reg == F2_H_num
2246       || reg == F3_num  || reg == F3_H_num
2247       || reg == F4_num  || reg == F4_H_num
2248       || reg == F5_num  || reg == F5_H_num
2249       || reg == F6_num  || reg == F6_H_num
2250       || reg == F7_num  || reg == F7_H_num
2251       || reg == F8_num  || reg == F8_H_num
2252       || reg == F9_num  || reg == F9_H_num
2253       || reg == F10_num || reg == F10_H_num
2254       || reg == F11_num || reg == F11_H_num
2255       || reg == F12_num || reg == F12_H_num
2256       || reg == F13_num || reg == F13_H_num)
2257     return true;
2258 
2259   return false;
2260 }
2261 
2262 bool Matcher::is_spillable_arg(int reg) {
2263   return can_be_java_arg(reg);
2264 }
2265 
2266 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2267   return false;
2268 }
2269 
2270 // Register for DIVI projection of divmodI.
2271 RegMask Matcher::divI_proj_mask() {
2272   ShouldNotReachHere();
2273   return RegMask();
2274 }
2275 
2276 // Register for MODI projection of divmodI.
2277 RegMask Matcher::modI_proj_mask() {
2278   ShouldNotReachHere();
2279   return RegMask();
2280 }
2281 
2282 // Register for DIVL projection of divmodL.
2283 RegMask Matcher::divL_proj_mask() {
2284   ShouldNotReachHere();
2285   return RegMask();
2286 }
2287 
2288 // Register for MODL projection of divmodL.
2289 RegMask Matcher::modL_proj_mask() {
2290   ShouldNotReachHere();
2291   return RegMask();
2292 }
2293 
2294 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2295   return RegMask();
2296 }
2297 
2298 const bool Matcher::convi2l_type_required = true;
2299 
2300 %}
2301 
2302 //----------ENCODING BLOCK-----------------------------------------------------
2303 // This block specifies the encoding classes used by the compiler to output
2304 // byte streams. Encoding classes are parameterized macros used by
2305 // Machine Instruction Nodes in order to generate the bit encoding of the
2306 // instruction. Operands specify their base encoding interface with the
2307 // interface keyword. There are currently supported four interfaces,
2308 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2309 // operand to generate a function which returns its register number when
2310 // queried. CONST_INTER causes an operand to generate a function which
2311 // returns the value of the constant when queried. MEMORY_INTER causes an
2312 // operand to generate four functions which return the Base Register, the
2313 // Index Register, the Scale Value, and the Offset Value of the operand when
2314 // queried. COND_INTER causes an operand to generate six functions which
2315 // return the encoding code (ie - encoding bits for the instruction)
2316 // associated with each basic boolean condition for a conditional instruction.
2317 //
2318 // Instructions specify two basic values for encoding. Again, a function
2319 // is available to check if the constant displacement is an oop. They use the
2320 // ins_encode keyword to specify their encoding classes (which must be
2321 // a sequence of enc_class names, and their parameters, specified in
2322 // the encoding block), and they use the
2323 // opcode keyword to specify, in order, their primary, secondary, and
2324 // tertiary opcode. Only the opcode sections which a particular instruction
2325 // needs for encoding need to be specified.
2326 encode %{
2327   enc_class enc_unimplemented %{
2328     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2329     MacroAssembler _masm(&cbuf);
2330     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2331   %}
2332 
2333   enc_class enc_untested %{
2334 #ifdef ASSERT
2335     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2336     MacroAssembler _masm(&cbuf);
2337     __ untested("Untested mach node encoding in AD file.");
2338 #else
2339     // TODO: PPC port $archOpcode(ppc64Opcode_none);
2340 #endif
2341   %}
2342 
2343   enc_class enc_lbz(iRegIdst dst, memory mem) %{
2344     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2345     MacroAssembler _masm(&cbuf);
2346     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2347     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2348   %}
2349 
2350   // Load acquire.
2351   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2352     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2353     MacroAssembler _masm(&cbuf);
2354     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2355     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2356     __ twi_0($dst$$Register);
2357     __ isync();
2358   %}
2359 
2360   enc_class enc_lhz(iRegIdst dst, memory mem) %{
2361     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2362 
2363     MacroAssembler _masm(&cbuf);
2364     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2365     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2366   %}
2367 
2368   // Load acquire.
2369   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2370     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2371 
2372     MacroAssembler _masm(&cbuf);
2373     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2374     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2375     __ twi_0($dst$$Register);
2376     __ isync();
2377   %}
2378 
2379   enc_class enc_lwz(iRegIdst dst, memory mem) %{
2380     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2381 
2382     MacroAssembler _masm(&cbuf);
2383     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2384     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2385   %}
2386 
2387   // Load acquire.
2388   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2389     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2390 
2391     MacroAssembler _masm(&cbuf);
2392     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2393     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2394     __ twi_0($dst$$Register);
2395     __ isync();
2396   %}
2397 
2398   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2399     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2400     MacroAssembler _masm(&cbuf);
2401     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2402     // Operand 'ds' requires 4-alignment.
2403     assert((Idisp & 0x3) == 0, "unaligned offset");
2404     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2405   %}
2406 
2407   // Load acquire.
2408   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2409     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2410     MacroAssembler _masm(&cbuf);
2411     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2412     // Operand 'ds' requires 4-alignment.
2413     assert((Idisp & 0x3) == 0, "unaligned offset");
2414     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2415     __ twi_0($dst$$Register);
2416     __ isync();
2417   %}
2418 
2419   enc_class enc_lfd(RegF dst, memory mem) %{
2420     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2421     MacroAssembler _masm(&cbuf);
2422     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2423     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2424   %}
2425 
2426   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2427     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2428 
2429     MacroAssembler _masm(&cbuf);
2430     int toc_offset = 0;
2431 
2432     address const_toc_addr;
2433     // Create a non-oop constant, no relocation needed.
2434     // If it is an IC, it has a virtual_call_Relocation.
2435     const_toc_addr = __ long_constant((jlong)$src$$constant);
2436     if (const_toc_addr == NULL) {
2437       ciEnv::current()->record_out_of_memory_failure();
2438       return;
2439     }
2440     
2441     // Get the constant's TOC offset.
2442     toc_offset = __ offset_to_method_toc(const_toc_addr);
2443     
2444     // Keep the current instruction offset in mind.
2445     ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2446   
2447     __ ld($dst$$Register, toc_offset, $toc$$Register);
2448   %}
2449 
2450   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2451     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2452 
2453     MacroAssembler _masm(&cbuf);
2454 
2455     if (!ra_->C->in_scratch_emit_size()) {
2456       address const_toc_addr;
2457       // Create a non-oop constant, no relocation needed.
2458       // If it is an IC, it has a virtual_call_Relocation.
2459       const_toc_addr = __ long_constant((jlong)$src$$constant);
2460       if (const_toc_addr == NULL) {
2461         ciEnv::current()->record_out_of_memory_failure();
2462         return;
2463       }
2464 
2465       // Get the constant's TOC offset.
2466       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2467       // Store the toc offset of the constant.
2468       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2469 
2470       // Also keep the current instruction offset in mind.
2471       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2472     }
2473 
2474     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2475   %}
2476 
2477 %} // encode
2478 
2479 source %{
2480 
2481 typedef struct {
2482   loadConL_hiNode *_large_hi;
2483   loadConL_loNode *_large_lo;
2484   loadConLNode    *_small;
2485   MachNode        *_last;
2486 } loadConLNodesTuple;
2487 
2488 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2489                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {
2490   loadConLNodesTuple nodes;
2491 
2492   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2493   if (large_constant_pool) {
2494     // Create new nodes.
2495     loadConL_hiNode *m1 = new loadConL_hiNode();
2496     loadConL_loNode *m2 = new loadConL_loNode();
2497 
2498     // inputs for new nodes
2499     m1->add_req(NULL, toc);
2500     m2->add_req(NULL, m1);
2501 
2502     // operands for new nodes
2503     m1->_opnds[0] = new iRegLdstOper(); // dst
2504     m1->_opnds[1] = immSrc;             // src
2505     m1->_opnds[2] = new iRegPdstOper(); // toc
2506     m2->_opnds[0] = new iRegLdstOper(); // dst
2507     m2->_opnds[1] = immSrc;             // src
2508     m2->_opnds[2] = new iRegLdstOper(); // base
2509 
2510     // Initialize ins_attrib TOC fields.
2511     m1->_const_toc_offset = -1;
2512     m2->_const_toc_offset_hi_node = m1;
2513 
2514     // Initialize ins_attrib instruction offset.
2515     m1->_cbuf_insts_offset = -1;
2516 
2517     // register allocation for new nodes
2518     ra_->set_pair(m1->_idx, reg_second, reg_first);
2519     ra_->set_pair(m2->_idx, reg_second, reg_first);
2520 
2521     // Create result.
2522     nodes._large_hi = m1;
2523     nodes._large_lo = m2;
2524     nodes._small = NULL;
2525     nodes._last = nodes._large_lo;
2526     assert(m2->bottom_type()->isa_long(), "must be long");
2527   } else {
2528     loadConLNode *m2 = new loadConLNode();
2529 
2530     // inputs for new nodes
2531     m2->add_req(NULL, toc);
2532 
2533     // operands for new nodes
2534     m2->_opnds[0] = new iRegLdstOper(); // dst
2535     m2->_opnds[1] = immSrc;             // src
2536     m2->_opnds[2] = new iRegPdstOper(); // toc
2537 
2538     // Initialize ins_attrib instruction offset.
2539     m2->_cbuf_insts_offset = -1;
2540 
2541     // register allocation for new nodes
2542     ra_->set_pair(m2->_idx, reg_second, reg_first);
2543 
2544     // Create result.
2545     nodes._large_hi = NULL;
2546     nodes._large_lo = NULL;
2547     nodes._small = m2;
2548     nodes._last = nodes._small;
2549     assert(m2->bottom_type()->isa_long(), "must be long");
2550   }
2551 
2552   return nodes;
2553 }
2554 
2555 %} // source
2556 
2557 encode %{
2558   // Postalloc expand emitter for loading a long constant from the method's TOC.
2559   // Enc_class needed as consttanttablebase is not supported by postalloc
2560   // expand.
2561   enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2562     // Create new nodes.
2563     loadConLNodesTuple loadConLNodes =
2564       loadConLNodesTuple_create(ra_, n_toc, op_src,
2565                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
2566 
2567     // Push new nodes.
2568     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2569     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
2570 
2571     // some asserts
2572     assert(nodes->length() >= 1, "must have created at least 1 node");
2573     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2574   %}
2575 
2576   enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2577     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2578 
2579     MacroAssembler _masm(&cbuf);
2580     int toc_offset = 0;
2581 
2582     intptr_t val = $src$$constant;
2583     relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2584     address const_toc_addr;
2585     if (constant_reloc == relocInfo::oop_type) {
2586       // Create an oop constant and a corresponding relocation.
2587       AddressLiteral a = __ allocate_oop_address((jobject)val);
2588       const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2589       __ relocate(a.rspec());
2590     } else if (constant_reloc == relocInfo::metadata_type) {
2591       AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2592       const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2593       __ relocate(a.rspec());
2594     } else {
2595       // Create a non-oop constant, no relocation needed.
2596       const_toc_addr = __ long_constant((jlong)$src$$constant);
2597     }
2598 
2599     if (const_toc_addr == NULL) {
2600       ciEnv::current()->record_out_of_memory_failure();
2601       return;
2602     }
2603     // Get the constant's TOC offset.
2604     toc_offset = __ offset_to_method_toc(const_toc_addr);
2605 
2606     __ ld($dst$$Register, toc_offset, $toc$$Register);
2607   %}
2608 
2609   enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2610     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2611 
2612     MacroAssembler _masm(&cbuf);
2613     if (!ra_->C->in_scratch_emit_size()) {
2614       intptr_t val = $src$$constant;
2615       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2616       address const_toc_addr;
2617       if (constant_reloc == relocInfo::oop_type) {
2618         // Create an oop constant and a corresponding relocation.
2619         AddressLiteral a = __ allocate_oop_address((jobject)val);
2620         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2621         __ relocate(a.rspec());
2622       } else if (constant_reloc == relocInfo::metadata_type) {
2623         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2624         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2625         __ relocate(a.rspec());
2626       } else {  // non-oop pointers, e.g. card mark base, heap top
2627         // Create a non-oop constant, no relocation needed.
2628         const_toc_addr = __ long_constant((jlong)$src$$constant);
2629       }
2630 
2631       if (const_toc_addr == NULL) {
2632         ciEnv::current()->record_out_of_memory_failure();
2633         return;
2634       }
2635       // Get the constant's TOC offset.
2636       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2637       // Store the toc offset of the constant.
2638       ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2639     }
2640 
2641     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2642   %}
2643 
2644   // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2645   // Enc_class needed as consttanttablebase is not supported by postalloc
2646   // expand.
2647   enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2648     const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2649     if (large_constant_pool) {
2650       // Create new nodes.
2651       loadConP_hiNode *m1 = new loadConP_hiNode();
2652       loadConP_loNode *m2 = new loadConP_loNode();
2653 
2654       // inputs for new nodes
2655       m1->add_req(NULL, n_toc);
2656       m2->add_req(NULL, m1);
2657 
2658       // operands for new nodes
2659       m1->_opnds[0] = new iRegPdstOper(); // dst
2660       m1->_opnds[1] = op_src;             // src
2661       m1->_opnds[2] = new iRegPdstOper(); // toc
2662       m2->_opnds[0] = new iRegPdstOper(); // dst
2663       m2->_opnds[1] = op_src;             // src
2664       m2->_opnds[2] = new iRegLdstOper(); // base
2665 
2666       // Initialize ins_attrib TOC fields.
2667       m1->_const_toc_offset = -1;
2668       m2->_const_toc_offset_hi_node = m1;
2669 
2670       // Register allocation for new nodes.
2671       ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2672       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2673 
2674       nodes->push(m1);
2675       nodes->push(m2);
2676       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2677     } else {
2678       loadConPNode *m2 = new loadConPNode();
2679 
2680       // inputs for new nodes
2681       m2->add_req(NULL, n_toc);
2682 
2683       // operands for new nodes
2684       m2->_opnds[0] = new iRegPdstOper(); // dst
2685       m2->_opnds[1] = op_src;             // src
2686       m2->_opnds[2] = new iRegPdstOper(); // toc
2687 
2688       // Register allocation for new nodes.
2689       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2690 
2691       nodes->push(m2);
2692       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2693     }
2694   %}
2695 
2696   // Enc_class needed as consttanttablebase is not supported by postalloc
2697   // expand.
2698   enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2699     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2700 
2701     MachNode *m2;
2702     if (large_constant_pool) {
2703       m2 = new loadConFCompNode();
2704     } else {
2705       m2 = new loadConFNode();
2706     }
2707     // inputs for new nodes
2708     m2->add_req(NULL, n_toc);
2709 
2710     // operands for new nodes
2711     m2->_opnds[0] = op_dst;
2712     m2->_opnds[1] = op_src;
2713     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2714 
2715     // register allocation for new nodes
2716     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2717     nodes->push(m2);
2718   %}
2719 
2720   // Enc_class needed as consttanttablebase is not supported by postalloc
2721   // expand.
2722   enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2723     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2724 
2725     MachNode *m2;
2726     if (large_constant_pool) {
2727       m2 = new loadConDCompNode();
2728     } else {
2729       m2 = new loadConDNode();
2730     }
2731     // inputs for new nodes
2732     m2->add_req(NULL, n_toc);
2733 
2734     // operands for new nodes
2735     m2->_opnds[0] = op_dst;
2736     m2->_opnds[1] = op_src;
2737     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2738 
2739     // register allocation for new nodes
2740     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2741     nodes->push(m2);
2742   %}
2743 
2744   enc_class enc_stw(iRegIsrc src, memory mem) %{
2745     // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2746     MacroAssembler _masm(&cbuf);
2747     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2748     __ stw($src$$Register, Idisp, $mem$$base$$Register);
2749   %}
2750 
2751   enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2752     // TODO: PPC port $archOpcode(ppc64Opcode_std);
2753     MacroAssembler _masm(&cbuf);
2754     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2755     // Operand 'ds' requires 4-alignment.
2756     assert((Idisp & 0x3) == 0, "unaligned offset");
2757     __ std($src$$Register, Idisp, $mem$$base$$Register);
2758   %}
2759 
2760   enc_class enc_stfs(RegF src, memory mem) %{
2761     // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2762     MacroAssembler _masm(&cbuf);
2763     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2764     __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2765   %}
2766 
2767   enc_class enc_stfd(RegF src, memory mem) %{
2768     // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2769     MacroAssembler _masm(&cbuf);
2770     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2771     __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2772   %}
2773 
2774   // Use release_store for card-marking to ensure that previous
2775   // oop-stores are visible before the card-mark change.
2776   enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2777     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2778     // FIXME: Implement this as a cmove and use a fixed condition code
2779     // register which is written on every transition to compiled code,
2780     // e.g. in call-stub and when returning from runtime stubs.
2781     //
2782     // Proposed code sequence for the cmove implementation:
2783     //
2784     // Label skip_release;
2785     // __ beq(CCRfixed, skip_release);
2786     // __ release();
2787     // __ bind(skip_release);
2788     // __ stb(card mark);
2789 
2790     MacroAssembler _masm(&cbuf);
2791     Label skip_storestore;
2792 
2793 #if 0 // TODO: PPC port
2794     // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2795     // StoreStore barrier conditionally.
2796     __ lwz(R0, 0, $releaseFieldAddr$$Register);
2797     __ cmpwi($crx$$CondRegister, R0, 0);
2798     __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2799 #endif
2800     __ li(R0, 0);
2801     __ membar(Assembler::StoreStore);
2802 #if 0 // TODO: PPC port
2803     __ bind(skip_storestore);
2804 #endif
2805 
2806     // Do the store.
2807     if ($mem$$index == 0) {
2808       __ stb(R0, $mem$$disp, $mem$$base$$Register);
2809     } else {
2810       assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2811       __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2812     }
2813   %}
2814 
2815   enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2816 
2817     if (VM_Version::has_isel()) {
2818       // use isel instruction with Power 7
2819       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2820       encodeP_subNode    *n_sub_base = new encodeP_subNode();
2821       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2822       cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2823 
2824       n_compare->add_req(n_region, n_src);
2825       n_compare->_opnds[0] = op_crx;
2826       n_compare->_opnds[1] = op_src;
2827       n_compare->_opnds[2] = new immL16Oper(0);
2828 
2829       n_sub_base->add_req(n_region, n_src);
2830       n_sub_base->_opnds[0] = op_dst;
2831       n_sub_base->_opnds[1] = op_src;
2832       n_sub_base->_bottom_type = _bottom_type;
2833 
2834       n_shift->add_req(n_region, n_sub_base);
2835       n_shift->_opnds[0] = op_dst;
2836       n_shift->_opnds[1] = op_dst;
2837       n_shift->_bottom_type = _bottom_type;
2838 
2839       n_cond_set->add_req(n_region, n_compare, n_shift);
2840       n_cond_set->_opnds[0] = op_dst;
2841       n_cond_set->_opnds[1] = op_crx;
2842       n_cond_set->_opnds[2] = op_dst;
2843       n_cond_set->_bottom_type = _bottom_type;
2844 
2845       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2846       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2847       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2848       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2849 
2850       nodes->push(n_compare);
2851       nodes->push(n_sub_base);
2852       nodes->push(n_shift);
2853       nodes->push(n_cond_set);
2854 
2855     } else {
2856       // before Power 7
2857       moveRegNode        *n_move     = new moveRegNode();
2858       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2859       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2860       cond_sub_baseNode  *n_sub_base = new cond_sub_baseNode();
2861 
2862       n_move->add_req(n_region, n_src);
2863       n_move->_opnds[0] = op_dst;
2864       n_move->_opnds[1] = op_src;
2865       ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2866 
2867       n_compare->add_req(n_region, n_src);
2868       n_compare->add_prec(n_move);
2869 
2870       n_compare->_opnds[0] = op_crx;
2871       n_compare->_opnds[1] = op_src;
2872       n_compare->_opnds[2] = new immL16Oper(0);
2873 
2874       n_sub_base->add_req(n_region, n_compare, n_src);
2875       n_sub_base->_opnds[0] = op_dst;
2876       n_sub_base->_opnds[1] = op_crx;
2877       n_sub_base->_opnds[2] = op_src;
2878       n_sub_base->_bottom_type = _bottom_type;
2879 
2880       n_shift->add_req(n_region, n_sub_base);
2881       n_shift->_opnds[0] = op_dst;
2882       n_shift->_opnds[1] = op_dst;
2883       n_shift->_bottom_type = _bottom_type;
2884 
2885       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2886       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2887       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2888       ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2889 
2890       nodes->push(n_move);
2891       nodes->push(n_compare);
2892       nodes->push(n_sub_base);
2893       nodes->push(n_shift);
2894     }
2895 
2896     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2897   %}
2898 
2899   enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2900 
2901     encodeP_subNode *n1 = new encodeP_subNode();
2902     n1->add_req(n_region, n_src);
2903     n1->_opnds[0] = op_dst;
2904     n1->_opnds[1] = op_src;
2905     n1->_bottom_type = _bottom_type;
2906 
2907     encodeP_shiftNode *n2 = new encodeP_shiftNode();
2908     n2->add_req(n_region, n1);
2909     n2->_opnds[0] = op_dst;
2910     n2->_opnds[1] = op_dst;
2911     n2->_bottom_type = _bottom_type;
2912     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2913     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2914 
2915     nodes->push(n1);
2916     nodes->push(n2);
2917     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2918   %}
2919 
2920   enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2921     decodeN_shiftNode *n_shift    = new decodeN_shiftNode();
2922     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
2923 
2924     n_compare->add_req(n_region, n_src);
2925     n_compare->_opnds[0] = op_crx;
2926     n_compare->_opnds[1] = op_src;
2927     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2928 
2929     n_shift->add_req(n_region, n_src);
2930     n_shift->_opnds[0] = op_dst;
2931     n_shift->_opnds[1] = op_src;
2932     n_shift->_bottom_type = _bottom_type;
2933 
2934     if (VM_Version::has_isel()) {
2935       // use isel instruction with Power 7
2936 
2937       decodeN_addNode *n_add_base = new decodeN_addNode();
2938       n_add_base->add_req(n_region, n_shift);
2939       n_add_base->_opnds[0] = op_dst;
2940       n_add_base->_opnds[1] = op_dst;
2941       n_add_base->_bottom_type = _bottom_type;
2942 
2943       cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2944       n_cond_set->add_req(n_region, n_compare, n_add_base);
2945       n_cond_set->_opnds[0] = op_dst;
2946       n_cond_set->_opnds[1] = op_crx;
2947       n_cond_set->_opnds[2] = op_dst;
2948       n_cond_set->_bottom_type = _bottom_type;
2949 
2950       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2951       ra_->set_oop(n_cond_set, true);
2952 
2953       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2954       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2955       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2956       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2957 
2958       nodes->push(n_compare);
2959       nodes->push(n_shift);
2960       nodes->push(n_add_base);
2961       nodes->push(n_cond_set);
2962 
2963     } else {
2964       // before Power 7
2965       cond_add_baseNode *n_add_base = new cond_add_baseNode();
2966 
2967       n_add_base->add_req(n_region, n_compare, n_shift);
2968       n_add_base->_opnds[0] = op_dst;
2969       n_add_base->_opnds[1] = op_crx;
2970       n_add_base->_opnds[2] = op_dst;
2971       n_add_base->_bottom_type = _bottom_type;
2972 
2973       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2974       ra_->set_oop(n_add_base, true);
2975 
2976       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2977       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2978       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2979 
2980       nodes->push(n_compare);
2981       nodes->push(n_shift);
2982       nodes->push(n_add_base);
2983     }
2984   %}
2985 
2986   enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
2987     decodeN_shiftNode *n1 = new decodeN_shiftNode();
2988     n1->add_req(n_region, n_src);
2989     n1->_opnds[0] = op_dst;
2990     n1->_opnds[1] = op_src;
2991     n1->_bottom_type = _bottom_type;
2992 
2993     decodeN_addNode *n2 = new decodeN_addNode();
2994     n2->add_req(n_region, n1);
2995     n2->_opnds[0] = op_dst;
2996     n2->_opnds[1] = op_dst;
2997     n2->_bottom_type = _bottom_type;
2998     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2999     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3000 
3001     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3002     ra_->set_oop(n2, true);
3003 
3004     nodes->push(n1);
3005     nodes->push(n2);
3006   %}
3007 
3008   enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3009     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3010 
3011     MacroAssembler _masm(&cbuf);
3012     int cc        = $cmp$$cmpcode;
3013     int flags_reg = $crx$$reg;
3014     Label done;
3015     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3016     // Branch if not (cmp crx).
3017     __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3018     __ mr($dst$$Register, $src$$Register);
3019     // TODO PPC port __ endgroup_if_needed(_size == 12);
3020     __ bind(done);
3021   %}
3022 
3023   enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3024     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3025 
3026     MacroAssembler _masm(&cbuf);
3027     Label done;
3028     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3029     // Branch if not (cmp crx).
3030     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3031     __ li($dst$$Register, $src$$constant);
3032     // TODO PPC port __ endgroup_if_needed(_size == 12);
3033     __ bind(done);
3034   %}
3035 
3036   // This enc_class is needed so that scheduler gets proper
3037   // input mapping for latency computation.
3038   enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3039     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3040     MacroAssembler _masm(&cbuf);
3041     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3042   %}
3043 
3044   enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3045     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3046 
3047     MacroAssembler _masm(&cbuf);
3048 
3049     Label done;
3050     __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3051     __ li($dst$$Register, $zero$$constant);
3052     __ beq($crx$$CondRegister, done);
3053     __ li($dst$$Register, $notzero$$constant);
3054     __ bind(done);
3055   %}
3056 
3057   enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3058     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3059 
3060     MacroAssembler _masm(&cbuf);
3061 
3062     Label done;
3063     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3064     __ li($dst$$Register, $zero$$constant);
3065     __ beq($crx$$CondRegister, done);
3066     __ li($dst$$Register, $notzero$$constant);
3067     __ bind(done);
3068   %}
3069 
3070   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3071     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3072 
3073     MacroAssembler _masm(&cbuf);
3074     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3075     Label done;
3076     __ bso($crx$$CondRegister, done);
3077     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3078     // TODO PPC port __ endgroup_if_needed(_size == 12);
3079     __ bind(done);
3080   %}
3081 
3082   enc_class enc_cmove_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
3083     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3084 
3085     MacroAssembler _masm(&cbuf);
3086     Label done;
3087     __ bso($crx$$CondRegister, done);
3088     __ mffprd($dst$$Register, $src$$FloatRegister);
3089     // TODO PPC port __ endgroup_if_needed(_size == 12);
3090     __ bind(done);
3091   %}
3092 
3093   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3094     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3095 
3096     MacroAssembler _masm(&cbuf);
3097     Label d;   // dummy
3098     __ bind(d);
3099     Label* p = ($lbl$$label);
3100     // `p' is `NULL' when this encoding class is used only to
3101     // determine the size of the encoded instruction.
3102     Label& l = (NULL == p)? d : *(p);
3103     int cc = $cmp$$cmpcode;
3104     int flags_reg = $crx$$reg;
3105     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3106     int bhint = Assembler::bhintNoHint;
3107 
3108     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3109       if (_prob <= PROB_NEVER) {
3110         bhint = Assembler::bhintIsNotTaken;
3111       } else if (_prob >= PROB_ALWAYS) {
3112         bhint = Assembler::bhintIsTaken;
3113       }
3114     }
3115 
3116     __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3117           cc_to_biint(cc, flags_reg),
3118           l);
3119   %}
3120 
3121   enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3122     // The scheduler doesn't know about branch shortening, so we set the opcode
3123     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3124     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3125 
3126     MacroAssembler _masm(&cbuf);
3127     Label d;    // dummy
3128     __ bind(d);
3129     Label* p = ($lbl$$label);
3130     // `p' is `NULL' when this encoding class is used only to
3131     // determine the size of the encoded instruction.
3132     Label& l = (NULL == p)? d : *(p);
3133     int cc = $cmp$$cmpcode;
3134     int flags_reg = $crx$$reg;
3135     int bhint = Assembler::bhintNoHint;
3136 
3137     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3138       if (_prob <= PROB_NEVER) {
3139         bhint = Assembler::bhintIsNotTaken;
3140       } else if (_prob >= PROB_ALWAYS) {
3141         bhint = Assembler::bhintIsTaken;
3142       }
3143     }
3144 
3145     // Tell the conditional far branch to optimize itself when being relocated.
3146     __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3147                   cc_to_biint(cc, flags_reg),
3148                   l,
3149                   MacroAssembler::bc_far_optimize_on_relocate);
3150   %}
3151 
3152   // Branch used with Power6 scheduling (can be shortened without changing the node).
3153   enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3154     // The scheduler doesn't know about branch shortening, so we set the opcode
3155     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3156     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3157 
3158     MacroAssembler _masm(&cbuf);
3159     Label d;   // dummy
3160     __ bind(d);
3161     Label* p = ($lbl$$label);
3162     // `p' is `NULL' when this encoding class is used only to
3163     // determine the size of the encoded instruction.
3164     Label& l = (NULL == p)? d : *(p);
3165     int cc = $cmp$$cmpcode;
3166     int flags_reg = $crx$$reg;
3167     int bhint = Assembler::bhintNoHint;
3168 
3169     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3170       if (_prob <= PROB_NEVER) {
3171         bhint = Assembler::bhintIsNotTaken;
3172       } else if (_prob >= PROB_ALWAYS) {
3173         bhint = Assembler::bhintIsTaken;
3174       }
3175     }
3176 
3177 #if 0 // TODO: PPC port
3178     if (_size == 8) {
3179       // Tell the conditional far branch to optimize itself when being relocated.
3180       __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3181                     cc_to_biint(cc, flags_reg),
3182                     l,
3183                     MacroAssembler::bc_far_optimize_on_relocate);
3184     } else {
3185       __ bc    (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3186                     cc_to_biint(cc, flags_reg),
3187                     l);
3188     }
3189 #endif
3190     Unimplemented();
3191   %}
3192 
3193   // Postalloc expand emitter for loading a replicatef float constant from
3194   // the method's TOC.
3195   // Enc_class needed as consttanttablebase is not supported by postalloc
3196   // expand.
3197   enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3198     // Create new nodes.
3199 
3200     // Make an operand with the bit pattern to load as float.
3201     immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3202 
3203     loadConLNodesTuple loadConLNodes =
3204       loadConLNodesTuple_create(ra_, n_toc, op_repl,
3205                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3206 
3207     // Push new nodes.
3208     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3209     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
3210 
3211     assert(nodes->length() >= 1, "must have created at least 1 node");
3212     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3213   %}
3214 
3215   // This enc_class is needed so that scheduler gets proper
3216   // input mapping for latency computation.
3217   enc_class enc_poll(immI dst, iRegLdst poll) %{
3218     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3219     // Fake operand dst needed for PPC scheduler.
3220     assert($dst$$constant == 0x0, "dst must be 0x0");
3221 
3222     MacroAssembler _masm(&cbuf);
3223     // Mark the code position where the load from the safepoint
3224     // polling page was emitted as relocInfo::poll_type.
3225     __ relocate(relocInfo::poll_type);
3226     __ load_from_polling_page($poll$$Register);
3227   %}
3228 
3229   // A Java static call or a runtime call.
3230   //
3231   // Branch-and-link relative to a trampoline.
3232   // The trampoline loads the target address and does a long branch to there.
3233   // In case we call java, the trampoline branches to a interpreter_stub
3234   // which loads the inline cache and the real call target from the constant pool.
3235   //
3236   // This basically looks like this:
3237   //
3238   // >>>> consts      -+  -+
3239   //                   |   |- offset1
3240   // [call target1]    | <-+
3241   // [IC cache]        |- offset2
3242   // [call target2] <--+
3243   //
3244   // <<<< consts
3245   // >>>> insts
3246   //
3247   // bl offset16               -+  -+             ??? // How many bits available?
3248   //                            |   |
3249   // <<<< insts                 |   |
3250   // >>>> stubs                 |   |
3251   //                            |   |- trampoline_stub_Reloc
3252   // trampoline stub:           | <-+
3253   //   r2 = toc                 |
3254   //   r2 = [r2 + offset1]      |       // Load call target1 from const section
3255   //   mtctr r2                 |
3256   //   bctr                     |- static_stub_Reloc
3257   // comp_to_interp_stub:   <---+
3258   //   r1 = toc
3259   //   ICreg = [r1 + IC_offset]         // Load IC from const section
3260   //   r1    = [r1 + offset2]           // Load call target2 from const section
3261   //   mtctr r1
3262   //   bctr
3263   //
3264   // <<<< stubs
3265   //
3266   // The call instruction in the code either
3267   // - Branches directly to a compiled method if the offset is encodable in instruction.
3268   // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3269   // - Branches to the compiled_to_interp stub if the target is interpreted.
3270   //
3271   // Further there are three relocations from the loads to the constants in
3272   // the constant section.
3273   //
3274   // Usage of r1 and r2 in the stubs allows to distinguish them.
3275   enc_class enc_java_static_call(method meth) %{
3276     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3277 
3278     MacroAssembler _masm(&cbuf);
3279     address entry_point = (address)$meth$$method;
3280 
3281     if (!_method) {
3282       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3283       emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3284     } else {
3285       // Remember the offset not the address.
3286       const int start_offset = __ offset();
3287 
3288       // The trampoline stub.
3289       // No entry point given, use the current pc.
3290       // Make sure branch fits into
3291       if (entry_point == 0) entry_point = __ pc();
3292 
3293       // Put the entry point as a constant into the constant pool.
3294       const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3295       if (entry_point_toc_addr == NULL) {
3296         ciEnv::current()->record_out_of_memory_failure();
3297         return;
3298       }
3299       const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3300 
3301       // Emit the trampoline stub which will be related to the branch-and-link below.
3302       CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3303       if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3304       int method_index = resolved_method_index(cbuf);
3305       __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3306                   : static_call_Relocation::spec(method_index));
3307 
3308       // The real call.
3309       // Note: At this point we do not have the address of the trampoline
3310       // stub, and the entry point might be too far away for bl, so __ pc()
3311       // serves as dummy and the bl will be patched later.
3312       cbuf.set_insts_mark();
3313       __ bl(__ pc());  // Emits a relocation.
3314 
3315       // The stub for call to interpreter.
3316       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3317       if (stub == NULL) {
3318         ciEnv::current()->record_failure("CodeCache is full");
3319         return;
3320       }
3321     }
3322   %}
3323 
3324   // Second node of expanded dynamic call - the call.
3325   enc_class enc_java_dynamic_call_sched(method meth) %{
3326     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3327 
3328     MacroAssembler _masm(&cbuf);
3329 
3330     if (!ra_->C->in_scratch_emit_size()) {
3331       // Create a call trampoline stub for the given method.
3332       const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3333       const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3334       if (entry_point_const == NULL) {
3335         ciEnv::current()->record_out_of_memory_failure();
3336         return;
3337       }
3338       const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3339       CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3340       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3341 
3342       // Build relocation at call site with ic position as data.
3343       assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3344              (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3345              "must have one, but can't have both");
3346       assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3347              (_load_ic_node != NULL    && _load_ic_node->_cbuf_insts_offset != -1),
3348              "must contain instruction offset");
3349       const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3350         ? _load_ic_hi_node->_cbuf_insts_offset
3351         : _load_ic_node->_cbuf_insts_offset;
3352       const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3353       assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3354              "should be load from TOC");
3355       int method_index = resolved_method_index(cbuf);
3356       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
3357     }
3358 
3359     // At this point I do not have the address of the trampoline stub,
3360     // and the entry point might be too far away for bl. Pc() serves
3361     // as dummy and bl will be patched later.
3362     __ bl((address) __ pc());
3363   %}
3364 
3365   // postalloc expand emitter for virtual calls.
3366   enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3367 
3368     // Create the nodes for loading the IC from the TOC.
3369     loadConLNodesTuple loadConLNodes_IC =
3370       loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3371                                 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3372 
3373     // Create the call node.
3374     CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3375     call->_method_handle_invoke = _method_handle_invoke;
3376     call->_vtable_index      = _vtable_index;
3377     call->_method            = _method;
3378     call->_bci               = _bci;
3379     call->_optimized_virtual = _optimized_virtual;
3380     call->_tf                = _tf;
3381     call->_entry_point       = _entry_point;
3382     call->_cnt               = _cnt;
3383     call->_argsize           = _argsize;
3384     call->_oop_map           = _oop_map;
3385     call->_jvms              = _jvms;
3386     call->_jvmadj            = _jvmadj;
3387     call->_in_rms            = _in_rms;
3388     call->_nesting           = _nesting;
3389     call->_override_symbolic_info = _override_symbolic_info;
3390 
3391     // New call needs all inputs of old call.
3392     // Req...
3393     for (uint i = 0; i < req(); ++i) {
3394       // The expanded node does not need toc any more.
3395       // Add the inline cache constant here instead. This expresses the
3396       // register of the inline cache must be live at the call.
3397       // Else we would have to adapt JVMState by -1.
3398       if (i == mach_constant_base_node_input()) {
3399         call->add_req(loadConLNodes_IC._last);
3400       } else {
3401         call->add_req(in(i));
3402       }
3403     }
3404     // ...as well as prec
3405     for (uint i = req(); i < len(); ++i) {
3406       call->add_prec(in(i));
3407     }
3408 
3409     // Remember nodes loading the inline cache into r19.
3410     call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3411     call->_load_ic_node    = loadConLNodes_IC._small;
3412 
3413     // Operands for new nodes.
3414     call->_opnds[0] = _opnds[0];
3415     call->_opnds[1] = _opnds[1];
3416 
3417     // Only the inline cache is associated with a register.
3418     assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3419 
3420     // Push new nodes.
3421     if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3422     if (loadConLNodes_IC._last)     nodes->push(loadConLNodes_IC._last);
3423     nodes->push(call);
3424   %}
3425 
3426   // Compound version of call dynamic
3427   // Toc is only passed so that it can be used in ins_encode statement.
3428   // In the code we have to use $constanttablebase.
3429   enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3430     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3431     MacroAssembler _masm(&cbuf);
3432     int start_offset = __ offset();
3433 
3434     Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3435 #if 0
3436     int vtable_index = this->_vtable_index;
3437     if (_vtable_index < 0) {
3438       // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3439       assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3440       Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3441 
3442       // Virtual call relocation will point to ic load.
3443       address virtual_call_meta_addr = __ pc();
3444       // Load a clear inline cache.
3445       AddressLiteral empty_ic((address) Universe::non_oop_word());
3446       bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true);
3447       if (!success) {
3448         ciEnv::current()->record_out_of_memory_failure();
3449         return;
3450       }
3451       // CALL to fixup routine.  Fixup routine uses ScopeDesc info
3452       // to determine who we intended to call.
3453       __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3454       emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3455       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3456              "Fix constant in ret_addr_offset()");
3457     } else {
3458       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3459       // Go thru the vtable. Get receiver klass. Receiver already
3460       // checked for non-null. If we'll go thru a C2I adapter, the
3461       // interpreter expects method in R19_method.
3462 
3463       __ load_klass(R11_scratch1, R3);
3464 
3465       int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes();
3466       int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
3467       __ li(R19_method, v_off);
3468       __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3469       // NOTE: for vtable dispatches, the vtable entry will never be
3470       // null. However it may very well end up in handle_wrong_method
3471       // if the method is abstract for the particular class.
3472       __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3473       // Call target. Either compiled code or C2I adapter.
3474       __ mtctr(R11_scratch1);
3475       __ bctrl();
3476       if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3477         tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3478       }
3479       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3480              "Fix constant in ret_addr_offset()");
3481     }
3482 #endif
3483     Unimplemented();  // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3484   %}
3485 
3486   // a runtime call
3487   enc_class enc_java_to_runtime_call (method meth) %{
3488     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3489 
3490     MacroAssembler _masm(&cbuf);
3491     const address start_pc = __ pc();
3492 
3493 #if defined(ABI_ELFv2)
3494     address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3495     __ call_c(entry, relocInfo::runtime_call_type);
3496 #else
3497     // The function we're going to call.
3498     FunctionDescriptor fdtemp;
3499     const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3500 
3501     Register Rtoc = R12_scratch2;
3502     // Calculate the method's TOC.
3503     __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3504     // Put entry, env, toc into the constant pool, this needs up to 3 constant
3505     // pool entries; call_c_using_toc will optimize the call.
3506     bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3507     if (!success) {
3508       ciEnv::current()->record_out_of_memory_failure();
3509       return;
3510     }
3511 #endif
3512 
3513     // Check the ret_addr_offset.
3514     assert(((MachCallRuntimeNode*)this)->ret_addr_offset() ==  __ last_calls_return_pc() - start_pc,
3515            "Fix constant in ret_addr_offset()");
3516   %}
3517 
3518   // Move to ctr for leaf call.
3519   // This enc_class is needed so that scheduler gets proper
3520   // input mapping for latency computation.
3521   enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3522     // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3523     MacroAssembler _masm(&cbuf);
3524     __ mtctr($src$$Register);
3525   %}
3526 
3527   // Postalloc expand emitter for runtime leaf calls.
3528   enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3529     loadConLNodesTuple loadConLNodes_Entry;
3530 #if defined(ABI_ELFv2)
3531     jlong entry_address = (jlong) this->entry_point();
3532     assert(entry_address, "need address here");
3533     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3534                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3535 #else
3536     // Get the struct that describes the function we are about to call.
3537     FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3538     assert(fd, "need fd here");
3539     jlong entry_address = (jlong) fd->entry();
3540     // new nodes
3541     loadConLNodesTuple loadConLNodes_Env;
3542     loadConLNodesTuple loadConLNodes_Toc;
3543 
3544     // Create nodes and operands for loading the entry point.
3545     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3546                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3547 
3548 
3549     // Create nodes and operands for loading the env pointer.
3550     if (fd->env() != NULL) {
3551       loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3552                                                     OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3553     } else {
3554       loadConLNodes_Env._large_hi = NULL;
3555       loadConLNodes_Env._large_lo = NULL;
3556       loadConLNodes_Env._small    = NULL;
3557       loadConLNodes_Env._last = new loadConL16Node();
3558       loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3559       loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3560       ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3561     }
3562 
3563     // Create nodes and operands for loading the Toc point.
3564     loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3565                                                   OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3566 #endif // ABI_ELFv2
3567     // mtctr node
3568     MachNode *mtctr = new CallLeafDirect_mtctrNode();
3569 
3570     assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3571     mtctr->add_req(0, loadConLNodes_Entry._last);
3572 
3573     mtctr->_opnds[0] = new iRegLdstOper();
3574     mtctr->_opnds[1] = new iRegLdstOper();
3575 
3576     // call node
3577     MachCallLeafNode *call = new CallLeafDirectNode();
3578 
3579     call->_opnds[0] = _opnds[0];
3580     call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3581 
3582     // Make the new call node look like the old one.
3583     call->_name        = _name;
3584     call->_tf          = _tf;
3585     call->_entry_point = _entry_point;
3586     call->_cnt         = _cnt;
3587     call->_argsize     = _argsize;
3588     call->_oop_map     = _oop_map;
3589     guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3590     call->_jvms        = NULL;
3591     call->_jvmadj      = _jvmadj;
3592     call->_in_rms      = _in_rms;
3593     call->_nesting     = _nesting;
3594 
3595 
3596     // New call needs all inputs of old call.
3597     // Req...
3598     for (uint i = 0; i < req(); ++i) {
3599       if (i != mach_constant_base_node_input()) {
3600         call->add_req(in(i));
3601       }
3602     }
3603 
3604     // These must be reqired edges, as the registers are live up to
3605     // the call. Else the constants are handled as kills.
3606     call->add_req(mtctr);
3607 #if !defined(ABI_ELFv2)
3608     call->add_req(loadConLNodes_Env._last);
3609     call->add_req(loadConLNodes_Toc._last);
3610 #endif
3611 
3612     // ...as well as prec
3613     for (uint i = req(); i < len(); ++i) {
3614       call->add_prec(in(i));
3615     }
3616 
3617     // registers
3618     ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3619 
3620     // Insert the new nodes.
3621     if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3622     if (loadConLNodes_Entry._last)     nodes->push(loadConLNodes_Entry._last);
3623 #if !defined(ABI_ELFv2)
3624     if (loadConLNodes_Env._large_hi)   nodes->push(loadConLNodes_Env._large_hi);
3625     if (loadConLNodes_Env._last)       nodes->push(loadConLNodes_Env._last);
3626     if (loadConLNodes_Toc._large_hi)   nodes->push(loadConLNodes_Toc._large_hi);
3627     if (loadConLNodes_Toc._last)       nodes->push(loadConLNodes_Toc._last);
3628 #endif
3629     nodes->push(mtctr);
3630     nodes->push(call);
3631   %}
3632 %}
3633 
3634 //----------FRAME--------------------------------------------------------------
3635 // Definition of frame structure and management information.
3636 
3637 frame %{
3638   // What direction does stack grow in (assumed to be same for native & Java).
3639   stack_direction(TOWARDS_LOW);
3640 
3641   // These two registers define part of the calling convention between
3642   // compiled code and the interpreter.
3643 
3644   // Inline Cache Register or method for I2C.
3645   inline_cache_reg(R19); // R19_method
3646 
3647   // Method Oop Register when calling interpreter.
3648   interpreter_method_oop_reg(R19); // R19_method
3649 
3650   // Optional: name the operand used by cisc-spilling to access
3651   // [stack_pointer + offset].
3652   cisc_spilling_operand_name(indOffset);
3653 
3654   // Number of stack slots consumed by a Monitor enter.
3655   sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3656 
3657   // Compiled code's Frame Pointer.
3658   frame_pointer(R1); // R1_SP
3659 
3660   // Interpreter stores its frame pointer in a register which is
3661   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3662   // interpreted java to compiled java.
3663   //
3664   // R14_state holds pointer to caller's cInterpreter.
3665   interpreter_frame_pointer(R14); // R14_state
3666 
3667   stack_alignment(frame::alignment_in_bytes);
3668 
3669   in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3670 
3671   // Number of outgoing stack slots killed above the
3672   // out_preserve_stack_slots for calls to C. Supports the var-args
3673   // backing area for register parms.
3674   //
3675   varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3676 
3677   // The after-PROLOG location of the return address. Location of
3678   // return address specifies a type (REG or STACK) and a number
3679   // representing the register number (i.e. - use a register name) or
3680   // stack slot.
3681   //
3682   // A: Link register is stored in stack slot ...
3683   // M:  ... but it's in the caller's frame according to PPC-64 ABI.
3684   // J: Therefore, we make sure that the link register is also in R11_scratch1
3685   //    at the end of the prolog.
3686   // B: We use R20, now.
3687   //return_addr(REG R20);
3688 
3689   // G: After reading the comments made by all the luminaries on their
3690   //    failure to tell the compiler where the return address really is,
3691   //    I hardly dare to try myself.  However, I'm convinced it's in slot
3692   //    4 what apparently works and saves us some spills.
3693   return_addr(STACK 4);
3694 
3695   // This is the body of the function
3696   //
3697   // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3698   //                                  uint length,      // length of array
3699   //                                  bool is_outgoing)
3700   //
3701   // The `sig' array is to be updated. sig[j] represents the location
3702   // of the j-th argument, either a register or a stack slot.
3703 
3704   // Comment taken from i486.ad:
3705   // Body of function which returns an integer array locating
3706   // arguments either in registers or in stack slots. Passed an array
3707   // of ideal registers called "sig" and a "length" count. Stack-slot
3708   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3709   // arguments for a CALLEE. Incoming stack arguments are
3710   // automatically biased by the preserve_stack_slots field above.
3711   calling_convention %{
3712     // No difference between ingoing/outgoing. Just pass false.
3713     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3714   %}
3715 
3716   // Comment taken from i486.ad:
3717   // Body of function which returns an integer array locating
3718   // arguments either in registers or in stack slots. Passed an array
3719   // of ideal registers called "sig" and a "length" count. Stack-slot
3720   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3721   // arguments for a CALLEE. Incoming stack arguments are
3722   // automatically biased by the preserve_stack_slots field above.
3723   c_calling_convention %{
3724     // This is obviously always outgoing.
3725     // C argument in register AND stack slot.
3726     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3727   %}
3728 
3729   // Location of native (C/C++) and interpreter return values. This
3730   // is specified to be the same as Java. In the 32-bit VM, long
3731   // values are actually returned from native calls in O0:O1 and
3732   // returned to the interpreter in I0:I1. The copying to and from
3733   // the register pairs is done by the appropriate call and epilog
3734   // opcodes. This simplifies the register allocator.
3735   c_return_value %{
3736     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3737             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3738             "only return normal values");
3739     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3740     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3741     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3742     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3743   %}
3744 
3745   // Location of compiled Java return values.  Same as C
3746   return_value %{
3747     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3748             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3749             "only return normal values");
3750     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3751     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3752     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3753     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3754   %}
3755 %}
3756 
3757 
3758 //----------ATTRIBUTES---------------------------------------------------------
3759 
3760 //----------Operand Attributes-------------------------------------------------
3761 op_attrib op_cost(1);          // Required cost attribute.
3762 
3763 //----------Instruction Attributes---------------------------------------------
3764 
3765 // Cost attribute. required.
3766 ins_attrib ins_cost(DEFAULT_COST);
3767 
3768 // Is this instruction a non-matching short branch variant of some
3769 // long branch? Not required.
3770 ins_attrib ins_short_branch(0);
3771 
3772 ins_attrib ins_is_TrapBasedCheckNode(true);
3773 
3774 // Number of constants.
3775 // This instruction uses the given number of constants
3776 // (optional attribute).
3777 // This is needed to determine in time whether the constant pool will
3778 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3779 // is determined. It's also used to compute the constant pool size
3780 // in Output().
3781 ins_attrib ins_num_consts(0);
3782 
3783 // Required alignment attribute (must be a power of 2) specifies the
3784 // alignment that some part of the instruction (not necessarily the
3785 // start) requires. If > 1, a compute_padding() function must be
3786 // provided for the instruction.
3787 ins_attrib ins_alignment(1);
3788 
3789 // Enforce/prohibit rematerializations.
3790 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3791 //   then rematerialization of that instruction is prohibited and the
3792 //   instruction's value will be spilled if necessary.
3793 //   Causes that MachNode::rematerialize() returns false.
3794 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3795 //   then rematerialization should be enforced and a copy of the instruction
3796 //   should be inserted if possible; rematerialization is not guaranteed.
3797 //   Note: this may result in rematerializations in front of every use.
3798 //   Causes that MachNode::rematerialize() can return true.
3799 // (optional attribute)
3800 ins_attrib ins_cannot_rematerialize(false);
3801 ins_attrib ins_should_rematerialize(false);
3802 
3803 // Instruction has variable size depending on alignment.
3804 ins_attrib ins_variable_size_depending_on_alignment(false);
3805 
3806 // Instruction is a nop.
3807 ins_attrib ins_is_nop(false);
3808 
3809 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3810 ins_attrib ins_use_mach_if_fast_lock_node(false);
3811 
3812 // Field for the toc offset of a constant.
3813 //
3814 // This is needed if the toc offset is not encodable as an immediate in
3815 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3816 // added to the toc, and from this a load with immediate is performed.
3817 // With postalloc expand, we get two nodes that require the same offset
3818 // but which don't know about each other. The offset is only known
3819 // when the constant is added to the constant pool during emitting.
3820 // It is generated in the 'hi'-node adding the upper bits, and saved
3821 // in this node.  The 'lo'-node has a link to the 'hi'-node and reads
3822 // the offset from there when it gets encoded.
3823 ins_attrib ins_field_const_toc_offset(0);
3824 ins_attrib ins_field_const_toc_offset_hi_node(0);
3825 
3826 // A field that can hold the instructions offset in the code buffer.
3827 // Set in the nodes emitter.
3828 ins_attrib ins_field_cbuf_insts_offset(-1);
3829 
3830 // Fields for referencing a call's load-IC-node.
3831 // If the toc offset can not be encoded as an immediate in a load, we
3832 // use two nodes.
3833 ins_attrib ins_field_load_ic_hi_node(0);
3834 ins_attrib ins_field_load_ic_node(0);
3835 
3836 //----------OPERANDS-----------------------------------------------------------
3837 // Operand definitions must precede instruction definitions for correct
3838 // parsing in the ADLC because operands constitute user defined types
3839 // which are used in instruction definitions.
3840 //
3841 // Formats are generated automatically for constants and base registers.
3842 
3843 //----------Simple Operands----------------------------------------------------
3844 // Immediate Operands
3845 
3846 // Integer Immediate: 32-bit
3847 operand immI() %{
3848   match(ConI);
3849   op_cost(40);
3850   format %{ %}
3851   interface(CONST_INTER);
3852 %}
3853 
3854 operand immI8() %{
3855   predicate(Assembler::is_simm(n->get_int(), 8));
3856   op_cost(0);
3857   match(ConI);
3858   format %{ %}
3859   interface(CONST_INTER);
3860 %}
3861 
3862 // Integer Immediate: 16-bit
3863 operand immI16() %{
3864   predicate(Assembler::is_simm(n->get_int(), 16));
3865   op_cost(0);
3866   match(ConI);
3867   format %{ %}
3868   interface(CONST_INTER);
3869 %}
3870 
3871 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
3872 operand immIhi16() %{
3873   predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
3874   match(ConI);
3875   op_cost(0);
3876   format %{ %}
3877   interface(CONST_INTER);
3878 %}
3879 
3880 operand immInegpow2() %{
3881   predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
3882   match(ConI);
3883   op_cost(0);
3884   format %{ %}
3885   interface(CONST_INTER);
3886 %}
3887 
3888 operand immIpow2minus1() %{
3889   predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
3890   match(ConI);
3891   op_cost(0);
3892   format %{ %}
3893   interface(CONST_INTER);
3894 %}
3895 
3896 operand immIpowerOf2() %{
3897   predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
3898   match(ConI);
3899   op_cost(0);
3900   format %{ %}
3901   interface(CONST_INTER);
3902 %}
3903 
3904 // Unsigned Integer Immediate: the values 0-31
3905 operand uimmI5() %{
3906   predicate(Assembler::is_uimm(n->get_int(), 5));
3907   match(ConI);
3908   op_cost(0);
3909   format %{ %}
3910   interface(CONST_INTER);
3911 %}
3912 
3913 // Unsigned Integer Immediate: 6-bit
3914 operand uimmI6() %{
3915   predicate(Assembler::is_uimm(n->get_int(), 6));
3916   match(ConI);
3917   op_cost(0);
3918   format %{ %}
3919   interface(CONST_INTER);
3920 %}
3921 
3922 // Unsigned Integer Immediate:  6-bit int, greater than 32
3923 operand uimmI6_ge32() %{
3924   predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
3925   match(ConI);
3926   op_cost(0);
3927   format %{ %}
3928   interface(CONST_INTER);
3929 %}
3930 
3931 // Unsigned Integer Immediate: 15-bit
3932 operand uimmI15() %{
3933   predicate(Assembler::is_uimm(n->get_int(), 15));
3934   match(ConI);
3935   op_cost(0);
3936   format %{ %}
3937   interface(CONST_INTER);
3938 %}
3939 
3940 // Unsigned Integer Immediate: 16-bit
3941 operand uimmI16() %{
3942   predicate(Assembler::is_uimm(n->get_int(), 16));
3943   match(ConI);
3944   op_cost(0);
3945   format %{ %}
3946   interface(CONST_INTER);
3947 %}
3948 
3949 // constant 'int 0'.
3950 operand immI_0() %{
3951   predicate(n->get_int() == 0);
3952   match(ConI);
3953   op_cost(0);
3954   format %{ %}
3955   interface(CONST_INTER);
3956 %}
3957 
3958 // constant 'int 1'.
3959 operand immI_1() %{
3960   predicate(n->get_int() == 1);
3961   match(ConI);
3962   op_cost(0);
3963   format %{ %}
3964   interface(CONST_INTER);
3965 %}
3966 
3967 // constant 'int -1'.
3968 operand immI_minus1() %{
3969   predicate(n->get_int() == -1);
3970   match(ConI);
3971   op_cost(0);
3972   format %{ %}
3973   interface(CONST_INTER);
3974 %}
3975 
3976 // int value 16.
3977 operand immI_16() %{
3978   predicate(n->get_int() == 16);
3979   match(ConI);
3980   op_cost(0);
3981   format %{ %}
3982   interface(CONST_INTER);
3983 %}
3984 
3985 // int value 24.
3986 operand immI_24() %{
3987   predicate(n->get_int() == 24);
3988   match(ConI);
3989   op_cost(0);
3990   format %{ %}
3991   interface(CONST_INTER);
3992 %}
3993 
3994 // Compressed oops constants
3995 // Pointer Immediate
3996 operand immN() %{
3997   match(ConN);
3998 
3999   op_cost(10);
4000   format %{ %}
4001   interface(CONST_INTER);
4002 %}
4003 
4004 // NULL Pointer Immediate
4005 operand immN_0() %{
4006   predicate(n->get_narrowcon() == 0);
4007   match(ConN);
4008 
4009   op_cost(0);
4010   format %{ %}
4011   interface(CONST_INTER);
4012 %}
4013 
4014 // Compressed klass constants
4015 operand immNKlass() %{
4016   match(ConNKlass);
4017 
4018   op_cost(0);
4019   format %{ %}
4020   interface(CONST_INTER);
4021 %}
4022 
4023 // This operand can be used to avoid matching of an instruct
4024 // with chain rule.
4025 operand immNKlass_NM() %{
4026   match(ConNKlass);
4027   predicate(false);
4028   op_cost(0);
4029   format %{ %}
4030   interface(CONST_INTER);
4031 %}
4032 
4033 // Pointer Immediate: 64-bit
4034 operand immP() %{
4035   match(ConP);
4036   op_cost(0);
4037   format %{ %}
4038   interface(CONST_INTER);
4039 %}
4040 
4041 // Operand to avoid match of loadConP.
4042 // This operand can be used to avoid matching of an instruct
4043 // with chain rule.
4044 operand immP_NM() %{
4045   match(ConP);
4046   predicate(false);
4047   op_cost(0);
4048   format %{ %}
4049   interface(CONST_INTER);
4050 %}
4051 
4052 // costant 'pointer 0'.
4053 operand immP_0() %{
4054   predicate(n->get_ptr() == 0);
4055   match(ConP);
4056   op_cost(0);
4057   format %{ %}
4058   interface(CONST_INTER);
4059 %}
4060 
4061 // pointer 0x0 or 0x1
4062 operand immP_0or1() %{
4063   predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4064   match(ConP);
4065   op_cost(0);
4066   format %{ %}
4067   interface(CONST_INTER);
4068 %}
4069 
4070 operand immL() %{
4071   match(ConL);
4072   op_cost(40);
4073   format %{ %}
4074   interface(CONST_INTER);
4075 %}
4076 
4077 operand immLmax30() %{
4078   predicate((n->get_long() <= 30));
4079   match(ConL);
4080   op_cost(0);
4081   format %{ %}
4082   interface(CONST_INTER);
4083 %}
4084 
4085 // Long Immediate: 16-bit
4086 operand immL16() %{
4087   predicate(Assembler::is_simm(n->get_long(), 16));
4088   match(ConL);
4089   op_cost(0);
4090   format %{ %}
4091   interface(CONST_INTER);
4092 %}
4093 
4094 // Long Immediate: 16-bit, 4-aligned
4095 operand immL16Alg4() %{
4096   predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4097   match(ConL);
4098   op_cost(0);
4099   format %{ %}
4100   interface(CONST_INTER);
4101 %}
4102 
4103 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4104 operand immL32hi16() %{
4105   predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4106   match(ConL);
4107   op_cost(0);
4108   format %{ %}
4109   interface(CONST_INTER);
4110 %}
4111 
4112 // Long Immediate: 32-bit
4113 operand immL32() %{
4114   predicate(Assembler::is_simm(n->get_long(), 32));
4115   match(ConL);
4116   op_cost(0);
4117   format %{ %}
4118   interface(CONST_INTER);
4119 %}
4120 
4121 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4122 operand immLhighest16() %{
4123   predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4124   match(ConL);
4125   op_cost(0);
4126   format %{ %}
4127   interface(CONST_INTER);
4128 %}
4129 
4130 operand immLnegpow2() %{
4131   predicate(is_power_of_2_long((jlong)-(n->get_long())));
4132   match(ConL);
4133   op_cost(0);
4134   format %{ %}
4135   interface(CONST_INTER);
4136 %}
4137 
4138 operand immLpow2minus1() %{
4139   predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4140             (n->get_long() != (jlong)0xffffffffffffffffL));
4141   match(ConL);
4142   op_cost(0);
4143   format %{ %}
4144   interface(CONST_INTER);
4145 %}
4146 
4147 // constant 'long 0'.
4148 operand immL_0() %{
4149   predicate(n->get_long() == 0L);
4150   match(ConL);
4151   op_cost(0);
4152   format %{ %}
4153   interface(CONST_INTER);
4154 %}
4155 
4156 // constat ' long -1'.
4157 operand immL_minus1() %{
4158   predicate(n->get_long() == -1L);
4159   match(ConL);
4160   op_cost(0);
4161   format %{ %}
4162   interface(CONST_INTER);
4163 %}
4164 
4165 // Long Immediate: low 32-bit mask
4166 operand immL_32bits() %{
4167   predicate(n->get_long() == 0xFFFFFFFFL);
4168   match(ConL);
4169   op_cost(0);
4170   format %{ %}
4171   interface(CONST_INTER);
4172 %}
4173 
4174 // Unsigned Long Immediate: 16-bit
4175 operand uimmL16() %{
4176   predicate(Assembler::is_uimm(n->get_long(), 16));
4177   match(ConL);
4178   op_cost(0);
4179   format %{ %}
4180   interface(CONST_INTER);
4181 %}
4182 
4183 // Float Immediate
4184 operand immF() %{
4185   match(ConF);
4186   op_cost(40);
4187   format %{ %}
4188   interface(CONST_INTER);
4189 %}
4190 
4191 // Float Immediate: +0.0f.
4192 operand immF_0() %{
4193   predicate(jint_cast(n->getf()) == 0);
4194   match(ConF);
4195 
4196   op_cost(0);
4197   format %{ %}
4198   interface(CONST_INTER);
4199 %}
4200 
4201 // Double Immediate
4202 operand immD() %{
4203   match(ConD);
4204   op_cost(40);
4205   format %{ %}
4206   interface(CONST_INTER);
4207 %}
4208 
4209 // Integer Register Operands
4210 // Integer Destination Register
4211 // See definition of reg_class bits32_reg_rw.
4212 operand iRegIdst() %{
4213   constraint(ALLOC_IN_RC(bits32_reg_rw));
4214   match(RegI);
4215   match(rscratch1RegI);
4216   match(rscratch2RegI);
4217   match(rarg1RegI);
4218   match(rarg2RegI);
4219   match(rarg3RegI);
4220   match(rarg4RegI);
4221   format %{ %}
4222   interface(REG_INTER);
4223 %}
4224 
4225 // Integer Source Register
4226 // See definition of reg_class bits32_reg_ro.
4227 operand iRegIsrc() %{
4228   constraint(ALLOC_IN_RC(bits32_reg_ro));
4229   match(RegI);
4230   match(rscratch1RegI);
4231   match(rscratch2RegI);
4232   match(rarg1RegI);
4233   match(rarg2RegI);
4234   match(rarg3RegI);
4235   match(rarg4RegI);
4236   format %{ %}
4237   interface(REG_INTER);
4238 %}
4239 
4240 operand rscratch1RegI() %{
4241   constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4242   match(iRegIdst);
4243   format %{ %}
4244   interface(REG_INTER);
4245 %}
4246 
4247 operand rscratch2RegI() %{
4248   constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4249   match(iRegIdst);
4250   format %{ %}
4251   interface(REG_INTER);
4252 %}
4253 
4254 operand rarg1RegI() %{
4255   constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4256   match(iRegIdst);
4257   format %{ %}
4258   interface(REG_INTER);
4259 %}
4260 
4261 operand rarg2RegI() %{
4262   constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4263   match(iRegIdst);
4264   format %{ %}
4265   interface(REG_INTER);
4266 %}
4267 
4268 operand rarg3RegI() %{
4269   constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4270   match(iRegIdst);
4271   format %{ %}
4272   interface(REG_INTER);
4273 %}
4274 
4275 operand rarg4RegI() %{
4276   constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4277   match(iRegIdst);
4278   format %{ %}
4279   interface(REG_INTER);
4280 %}
4281 
4282 operand rarg1RegL() %{
4283   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4284   match(iRegLdst);
4285   format %{ %}
4286   interface(REG_INTER);
4287 %}
4288 
4289 operand rarg2RegL() %{
4290   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4291   match(iRegLdst);
4292   format %{ %}
4293   interface(REG_INTER);
4294 %}
4295 
4296 operand rarg3RegL() %{
4297   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4298   match(iRegLdst);
4299   format %{ %}
4300   interface(REG_INTER);
4301 %}
4302 
4303 operand rarg4RegL() %{
4304   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4305   match(iRegLdst);
4306   format %{ %}
4307   interface(REG_INTER);
4308 %}
4309 
4310 // Pointer Destination Register
4311 // See definition of reg_class bits64_reg_rw.
4312 operand iRegPdst() %{
4313   constraint(ALLOC_IN_RC(bits64_reg_rw));
4314   match(RegP);
4315   match(rscratch1RegP);
4316   match(rscratch2RegP);
4317   match(rarg1RegP);
4318   match(rarg2RegP);
4319   match(rarg3RegP);
4320   match(rarg4RegP);
4321   format %{ %}
4322   interface(REG_INTER);
4323 %}
4324 
4325 // Pointer Destination Register
4326 // Operand not using r11 and r12 (killed in epilog).
4327 operand iRegPdstNoScratch() %{
4328   constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4329   match(RegP);
4330   match(rarg1RegP);
4331   match(rarg2RegP);
4332   match(rarg3RegP);
4333   match(rarg4RegP);
4334   format %{ %}
4335   interface(REG_INTER);
4336 %}
4337 
4338 // Pointer Source Register
4339 // See definition of reg_class bits64_reg_ro.
4340 operand iRegPsrc() %{
4341   constraint(ALLOC_IN_RC(bits64_reg_ro));
4342   match(RegP);
4343   match(iRegPdst);
4344   match(rscratch1RegP);
4345   match(rscratch2RegP);
4346   match(rarg1RegP);
4347   match(rarg2RegP);
4348   match(rarg3RegP);
4349   match(rarg4RegP);
4350   match(threadRegP);
4351   format %{ %}
4352   interface(REG_INTER);
4353 %}
4354 
4355 // Thread operand.
4356 operand threadRegP() %{
4357   constraint(ALLOC_IN_RC(thread_bits64_reg));
4358   match(iRegPdst);
4359   format %{ "R16" %}
4360   interface(REG_INTER);
4361 %}
4362 
4363 operand rscratch1RegP() %{
4364   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4365   match(iRegPdst);
4366   format %{ "R11" %}
4367   interface(REG_INTER);
4368 %}
4369 
4370 operand rscratch2RegP() %{
4371   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4372   match(iRegPdst);
4373   format %{ %}
4374   interface(REG_INTER);
4375 %}
4376 
4377 operand rarg1RegP() %{
4378   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4379   match(iRegPdst);
4380   format %{ %}
4381   interface(REG_INTER);
4382 %}
4383 
4384 operand rarg2RegP() %{
4385   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4386   match(iRegPdst);
4387   format %{ %}
4388   interface(REG_INTER);
4389 %}
4390 
4391 operand rarg3RegP() %{
4392   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4393   match(iRegPdst);
4394   format %{ %}
4395   interface(REG_INTER);
4396 %}
4397 
4398 operand rarg4RegP() %{
4399   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4400   match(iRegPdst);
4401   format %{ %}
4402   interface(REG_INTER);
4403 %}
4404 
4405 operand iRegNsrc() %{
4406   constraint(ALLOC_IN_RC(bits32_reg_ro));
4407   match(RegN);
4408   match(iRegNdst);
4409 
4410   format %{ %}
4411   interface(REG_INTER);
4412 %}
4413 
4414 operand iRegNdst() %{
4415   constraint(ALLOC_IN_RC(bits32_reg_rw));
4416   match(RegN);
4417 
4418   format %{ %}
4419   interface(REG_INTER);
4420 %}
4421 
4422 // Long Destination Register
4423 // See definition of reg_class bits64_reg_rw.
4424 operand iRegLdst() %{
4425   constraint(ALLOC_IN_RC(bits64_reg_rw));
4426   match(RegL);
4427   match(rscratch1RegL);
4428   match(rscratch2RegL);
4429   format %{ %}
4430   interface(REG_INTER);
4431 %}
4432 
4433 // Long Source Register
4434 // See definition of reg_class bits64_reg_ro.
4435 operand iRegLsrc() %{
4436   constraint(ALLOC_IN_RC(bits64_reg_ro));
4437   match(RegL);
4438   match(iRegLdst);
4439   match(rscratch1RegL);
4440   match(rscratch2RegL);
4441   format %{ %}
4442   interface(REG_INTER);
4443 %}
4444 
4445 // Special operand for ConvL2I.
4446 operand iRegL2Isrc(iRegLsrc reg) %{
4447   constraint(ALLOC_IN_RC(bits64_reg_ro));
4448   match(ConvL2I reg);
4449   format %{ "ConvL2I($reg)" %}
4450   interface(REG_INTER)
4451 %}
4452 
4453 operand rscratch1RegL() %{
4454   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4455   match(RegL);
4456   format %{ %}
4457   interface(REG_INTER);
4458 %}
4459 
4460 operand rscratch2RegL() %{
4461   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4462   match(RegL);
4463   format %{ %}
4464   interface(REG_INTER);
4465 %}
4466 
4467 // Condition Code Flag Registers
4468 operand flagsReg() %{
4469   constraint(ALLOC_IN_RC(int_flags));
4470   match(RegFlags);
4471   format %{ %}
4472   interface(REG_INTER);
4473 %}
4474 
4475 operand flagsRegSrc() %{
4476   constraint(ALLOC_IN_RC(int_flags_ro));
4477   match(RegFlags);
4478   match(flagsReg);
4479   match(flagsRegCR0);
4480   format %{ %}
4481   interface(REG_INTER);
4482 %}
4483 
4484 // Condition Code Flag Register CR0
4485 operand flagsRegCR0() %{
4486   constraint(ALLOC_IN_RC(int_flags_CR0));
4487   match(RegFlags);
4488   format %{ "CR0" %}
4489   interface(REG_INTER);
4490 %}
4491 
4492 operand flagsRegCR1() %{
4493   constraint(ALLOC_IN_RC(int_flags_CR1));
4494   match(RegFlags);
4495   format %{ "CR1" %}
4496   interface(REG_INTER);
4497 %}
4498 
4499 operand flagsRegCR6() %{
4500   constraint(ALLOC_IN_RC(int_flags_CR6));
4501   match(RegFlags);
4502   format %{ "CR6" %}
4503   interface(REG_INTER);
4504 %}
4505 
4506 operand regCTR() %{
4507   constraint(ALLOC_IN_RC(ctr_reg));
4508   // RegFlags should work. Introducing a RegSpecial type would cause a
4509   // lot of changes.
4510   match(RegFlags);
4511   format %{"SR_CTR" %}
4512   interface(REG_INTER);
4513 %}
4514 
4515 operand regD() %{
4516   constraint(ALLOC_IN_RC(dbl_reg));
4517   match(RegD);
4518   format %{ %}
4519   interface(REG_INTER);
4520 %}
4521 
4522 operand regF() %{
4523   constraint(ALLOC_IN_RC(flt_reg));
4524   match(RegF);
4525   format %{ %}
4526   interface(REG_INTER);
4527 %}
4528 
4529 // Special Registers
4530 
4531 // Method Register
4532 operand inline_cache_regP(iRegPdst reg) %{
4533   constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4534   match(reg);
4535   format %{ %}
4536   interface(REG_INTER);
4537 %}
4538 
4539 operand compiler_method_oop_regP(iRegPdst reg) %{
4540   constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4541   match(reg);
4542   format %{ %}
4543   interface(REG_INTER);
4544 %}
4545 
4546 operand interpreter_method_oop_regP(iRegPdst reg) %{
4547   constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4548   match(reg);
4549   format %{ %}
4550   interface(REG_INTER);
4551 %}
4552 
4553 // Operands to remove register moves in unscaled mode.
4554 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4555 operand iRegP2N(iRegPsrc reg) %{
4556   predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4557   constraint(ALLOC_IN_RC(bits64_reg_ro));
4558   match(EncodeP reg);
4559   format %{ "$reg" %}
4560   interface(REG_INTER)
4561 %}
4562 
4563 operand iRegN2P(iRegNsrc reg) %{
4564   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4565   constraint(ALLOC_IN_RC(bits32_reg_ro));
4566   match(DecodeN reg);
4567   format %{ "$reg" %}
4568   interface(REG_INTER)
4569 %}
4570 
4571 operand iRegN2P_klass(iRegNsrc reg) %{
4572   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4573   constraint(ALLOC_IN_RC(bits32_reg_ro));
4574   match(DecodeNKlass reg);
4575   format %{ "$reg" %}
4576   interface(REG_INTER)
4577 %}
4578 
4579 //----------Complex Operands---------------------------------------------------
4580 // Indirect Memory Reference
4581 operand indirect(iRegPsrc reg) %{
4582   constraint(ALLOC_IN_RC(bits64_reg_ro));
4583   match(reg);
4584   op_cost(100);
4585   format %{ "[$reg]" %}
4586   interface(MEMORY_INTER) %{
4587     base($reg);
4588     index(0x0);
4589     scale(0x0);
4590     disp(0x0);
4591   %}
4592 %}
4593 
4594 // Indirect with Offset
4595 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4596   constraint(ALLOC_IN_RC(bits64_reg_ro));
4597   match(AddP reg offset);
4598   op_cost(100);
4599   format %{ "[$reg + $offset]" %}
4600   interface(MEMORY_INTER) %{
4601     base($reg);
4602     index(0x0);
4603     scale(0x0);
4604     disp($offset);
4605   %}
4606 %}
4607 
4608 // Indirect with 4-aligned Offset
4609 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4610   constraint(ALLOC_IN_RC(bits64_reg_ro));
4611   match(AddP reg offset);
4612   op_cost(100);
4613   format %{ "[$reg + $offset]" %}
4614   interface(MEMORY_INTER) %{
4615     base($reg);
4616     index(0x0);
4617     scale(0x0);
4618     disp($offset);
4619   %}
4620 %}
4621 
4622 //----------Complex Operands for Compressed OOPs-------------------------------
4623 // Compressed OOPs with narrow_oop_shift == 0.
4624 
4625 // Indirect Memory Reference, compressed OOP
4626 operand indirectNarrow(iRegNsrc reg) %{
4627   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4628   constraint(ALLOC_IN_RC(bits64_reg_ro));
4629   match(DecodeN reg);
4630   op_cost(100);
4631   format %{ "[$reg]" %}
4632   interface(MEMORY_INTER) %{
4633     base($reg);
4634     index(0x0);
4635     scale(0x0);
4636     disp(0x0);
4637   %}
4638 %}
4639 
4640 operand indirectNarrow_klass(iRegNsrc reg) %{
4641   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4642   constraint(ALLOC_IN_RC(bits64_reg_ro));
4643   match(DecodeNKlass reg);
4644   op_cost(100);
4645   format %{ "[$reg]" %}
4646   interface(MEMORY_INTER) %{
4647     base($reg);
4648     index(0x0);
4649     scale(0x0);
4650     disp(0x0);
4651   %}
4652 %}
4653 
4654 // Indirect with Offset, compressed OOP
4655 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4656   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4657   constraint(ALLOC_IN_RC(bits64_reg_ro));
4658   match(AddP (DecodeN reg) offset);
4659   op_cost(100);
4660   format %{ "[$reg + $offset]" %}
4661   interface(MEMORY_INTER) %{
4662     base($reg);
4663     index(0x0);
4664     scale(0x0);
4665     disp($offset);
4666   %}
4667 %}
4668 
4669 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4670   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4671   constraint(ALLOC_IN_RC(bits64_reg_ro));
4672   match(AddP (DecodeNKlass reg) offset);
4673   op_cost(100);
4674   format %{ "[$reg + $offset]" %}
4675   interface(MEMORY_INTER) %{
4676     base($reg);
4677     index(0x0);
4678     scale(0x0);
4679     disp($offset);
4680   %}
4681 %}
4682 
4683 // Indirect with 4-aligned Offset, compressed OOP
4684 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4685   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4686   constraint(ALLOC_IN_RC(bits64_reg_ro));
4687   match(AddP (DecodeN reg) offset);
4688   op_cost(100);
4689   format %{ "[$reg + $offset]" %}
4690   interface(MEMORY_INTER) %{
4691     base($reg);
4692     index(0x0);
4693     scale(0x0);
4694     disp($offset);
4695   %}
4696 %}
4697 
4698 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4699   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4700   constraint(ALLOC_IN_RC(bits64_reg_ro));
4701   match(AddP (DecodeNKlass reg) offset);
4702   op_cost(100);
4703   format %{ "[$reg + $offset]" %}
4704   interface(MEMORY_INTER) %{
4705     base($reg);
4706     index(0x0);
4707     scale(0x0);
4708     disp($offset);
4709   %}
4710 %}
4711 
4712 //----------Special Memory Operands--------------------------------------------
4713 // Stack Slot Operand
4714 //
4715 // This operand is used for loading and storing temporary values on
4716 // the stack where a match requires a value to flow through memory.
4717 operand stackSlotI(sRegI reg) %{
4718   constraint(ALLOC_IN_RC(stack_slots));
4719   op_cost(100);
4720   //match(RegI);
4721   format %{ "[sp+$reg]" %}
4722   interface(MEMORY_INTER) %{
4723     base(0x1);   // R1_SP
4724     index(0x0);
4725     scale(0x0);
4726     disp($reg);  // Stack Offset
4727   %}
4728 %}
4729 
4730 operand stackSlotL(sRegL reg) %{
4731   constraint(ALLOC_IN_RC(stack_slots));
4732   op_cost(100);
4733   //match(RegL);
4734   format %{ "[sp+$reg]" %}
4735   interface(MEMORY_INTER) %{
4736     base(0x1);   // R1_SP
4737     index(0x0);
4738     scale(0x0);
4739     disp($reg);  // Stack Offset
4740   %}
4741 %}
4742 
4743 operand stackSlotP(sRegP reg) %{
4744   constraint(ALLOC_IN_RC(stack_slots));
4745   op_cost(100);
4746   //match(RegP);
4747   format %{ "[sp+$reg]" %}
4748   interface(MEMORY_INTER) %{
4749     base(0x1);   // R1_SP
4750     index(0x0);
4751     scale(0x0);
4752     disp($reg);  // Stack Offset
4753   %}
4754 %}
4755 
4756 operand stackSlotF(sRegF reg) %{
4757   constraint(ALLOC_IN_RC(stack_slots));
4758   op_cost(100);
4759   //match(RegF);
4760   format %{ "[sp+$reg]" %}
4761   interface(MEMORY_INTER) %{
4762     base(0x1);   // R1_SP
4763     index(0x0);
4764     scale(0x0);
4765     disp($reg);  // Stack Offset
4766   %}
4767 %}
4768 
4769 operand stackSlotD(sRegD reg) %{
4770   constraint(ALLOC_IN_RC(stack_slots));
4771   op_cost(100);
4772   //match(RegD);
4773   format %{ "[sp+$reg]" %}
4774   interface(MEMORY_INTER) %{
4775     base(0x1);   // R1_SP
4776     index(0x0);
4777     scale(0x0);
4778     disp($reg);  // Stack Offset
4779   %}
4780 %}
4781 
4782 // Operands for expressing Control Flow
4783 // NOTE: Label is a predefined operand which should not be redefined in
4784 //       the AD file. It is generically handled within the ADLC.
4785 
4786 //----------Conditional Branch Operands----------------------------------------
4787 // Comparison Op
4788 //
4789 // This is the operation of the comparison, and is limited to the
4790 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4791 // (!=).
4792 //
4793 // Other attributes of the comparison, such as unsignedness, are specified
4794 // by the comparison instruction that sets a condition code flags register.
4795 // That result is represented by a flags operand whose subtype is appropriate
4796 // to the unsignedness (etc.) of the comparison.
4797 //
4798 // Later, the instruction which matches both the Comparison Op (a Bool) and
4799 // the flags (produced by the Cmp) specifies the coding of the comparison op
4800 // by matching a specific subtype of Bool operand below.
4801 
4802 // When used for floating point comparisons: unordered same as less.
4803 operand cmpOp() %{
4804   match(Bool);
4805   format %{ "" %}
4806   interface(COND_INTER) %{
4807                            // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4808                            //           BO          &  BI
4809     equal(0xA);            // 10 10:   bcondCRbiIs1 & Condition::equal
4810     not_equal(0x2);        // 00 10:   bcondCRbiIs0 & Condition::equal
4811     less(0x8);             // 10 00:   bcondCRbiIs1 & Condition::less
4812     greater_equal(0x0);    // 00 00:   bcondCRbiIs0 & Condition::less
4813     less_equal(0x1);       // 00 01:   bcondCRbiIs0 & Condition::greater
4814     greater(0x9);          // 10 01:   bcondCRbiIs1 & Condition::greater
4815     overflow(0xB);         // 10 11:   bcondCRbiIs1 & Condition::summary_overflow
4816     no_overflow(0x3);      // 00 11:   bcondCRbiIs0 & Condition::summary_overflow
4817   %}
4818 %}
4819 
4820 //----------OPERAND CLASSES----------------------------------------------------
4821 // Operand Classes are groups of operands that are used to simplify
4822 // instruction definitions by not requiring the AD writer to specify
4823 // seperate instructions for every form of operand when the
4824 // instruction accepts multiple operand types with the same basic
4825 // encoding and format. The classic case of this is memory operands.
4826 // Indirect is not included since its use is limited to Compare & Swap.
4827 
4828 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4829 // Memory operand where offsets are 4-aligned. Required for ld, std.
4830 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4831 opclass indirectMemory(indirect, indirectNarrow);
4832 
4833 // Special opclass for I and ConvL2I.
4834 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4835 
4836 // Operand classes to match encode and decode. iRegN_P2N is only used
4837 // for storeN. I have never seen an encode node elsewhere.
4838 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4839 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4840 
4841 //----------PIPELINE-----------------------------------------------------------
4842 
4843 pipeline %{
4844 
4845 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4846 // J. Res. & Dev., No. 1, Jan. 2002.
4847 
4848 //----------ATTRIBUTES---------------------------------------------------------
4849 attributes %{
4850 
4851   // Power4 instructions are of fixed length.
4852   fixed_size_instructions;
4853 
4854   // TODO: if `bundle' means number of instructions fetched
4855   // per cycle, this is 8. If `bundle' means Power4 `group', that is
4856   // max instructions issued per cycle, this is 5.
4857   max_instructions_per_bundle = 8;
4858 
4859   // A Power4 instruction is 4 bytes long.
4860   instruction_unit_size = 4;
4861 
4862   // The Power4 processor fetches 64 bytes...
4863   instruction_fetch_unit_size = 64;
4864 
4865   // ...in one line
4866   instruction_fetch_units = 1
4867 
4868   // Unused, list one so that array generated by adlc is not empty.
4869   // Aix compiler chokes if _nop_count = 0.
4870   nops(fxNop);
4871 %}
4872 
4873 //----------RESOURCES----------------------------------------------------------
4874 // Resources are the functional units available to the machine
4875 resources(
4876    PPC_BR,         // branch unit
4877    PPC_CR,         // condition unit
4878    PPC_FX1,        // integer arithmetic unit 1
4879    PPC_FX2,        // integer arithmetic unit 2
4880    PPC_LDST1,      // load/store unit 1
4881    PPC_LDST2,      // load/store unit 2
4882    PPC_FP1,        // float arithmetic unit 1
4883    PPC_FP2,        // float arithmetic unit 2
4884    PPC_LDST = PPC_LDST1 | PPC_LDST2,
4885    PPC_FX = PPC_FX1 | PPC_FX2,
4886    PPC_FP = PPC_FP1 | PPC_FP2
4887  );
4888 
4889 //----------PIPELINE DESCRIPTION-----------------------------------------------
4890 // Pipeline Description specifies the stages in the machine's pipeline
4891 pipe_desc(
4892    // Power4 longest pipeline path
4893    PPC_IF,   // instruction fetch
4894    PPC_IC,
4895    //PPC_BP, // branch prediction
4896    PPC_D0,   // decode
4897    PPC_D1,   // decode
4898    PPC_D2,   // decode
4899    PPC_D3,   // decode
4900    PPC_Xfer1,
4901    PPC_GD,   // group definition
4902    PPC_MP,   // map
4903    PPC_ISS,  // issue
4904    PPC_RF,   // resource fetch
4905    PPC_EX1,  // execute (all units)
4906    PPC_EX2,  // execute (FP, LDST)
4907    PPC_EX3,  // execute (FP, LDST)
4908    PPC_EX4,  // execute (FP)
4909    PPC_EX5,  // execute (FP)
4910    PPC_EX6,  // execute (FP)
4911    PPC_WB,   // write back
4912    PPC_Xfer2,
4913    PPC_CP
4914  );
4915 
4916 //----------PIPELINE CLASSES---------------------------------------------------
4917 // Pipeline Classes describe the stages in which input and output are
4918 // referenced by the hardware pipeline.
4919 
4920 // Simple pipeline classes.
4921 
4922 // Default pipeline class.
4923 pipe_class pipe_class_default() %{
4924   single_instruction;
4925   fixed_latency(2);
4926 %}
4927 
4928 // Pipeline class for empty instructions.
4929 pipe_class pipe_class_empty() %{
4930   single_instruction;
4931   fixed_latency(0);
4932 %}
4933 
4934 // Pipeline class for compares.
4935 pipe_class pipe_class_compare() %{
4936   single_instruction;
4937   fixed_latency(16);
4938 %}
4939 
4940 // Pipeline class for traps.
4941 pipe_class pipe_class_trap() %{
4942   single_instruction;
4943   fixed_latency(100);
4944 %}
4945 
4946 // Pipeline class for memory operations.
4947 pipe_class pipe_class_memory() %{
4948   single_instruction;
4949   fixed_latency(16);
4950 %}
4951 
4952 // Pipeline class for call.
4953 pipe_class pipe_class_call() %{
4954   single_instruction;
4955   fixed_latency(100);
4956 %}
4957 
4958 // Define the class for the Nop node.
4959 define %{
4960    MachNop = pipe_class_default;
4961 %}
4962 
4963 %}
4964 
4965 //----------INSTRUCTIONS-------------------------------------------------------
4966 
4967 // Naming of instructions:
4968 //   opA_operB / opA_operB_operC:
4969 //     Operation 'op' with one or two source operands 'oper'. Result
4970 //     type is A, source operand types are B and C.
4971 //     Iff A == B == C, B and C are left out.
4972 //
4973 // The instructions are ordered according to the following scheme:
4974 //  - loads
4975 //  - load constants
4976 //  - prefetch
4977 //  - store
4978 //  - encode/decode
4979 //  - membar
4980 //  - conditional moves
4981 //  - compare & swap
4982 //  - arithmetic and logic operations
4983 //    * int: Add, Sub, Mul, Div, Mod
4984 //    * int: lShift, arShift, urShift, rot
4985 //    * float: Add, Sub, Mul, Div
4986 //    * and, or, xor ...
4987 //  - register moves: float <-> int, reg <-> stack, repl
4988 //  - cast (high level type cast, XtoP, castPP, castII, not_null etc.
4989 //  - conv (low level type cast requiring bit changes (sign extend etc)
4990 //  - compares, range & zero checks.
4991 //  - branches
4992 //  - complex operations, intrinsics, min, max, replicate
4993 //  - lock
4994 //  - Calls
4995 //
4996 // If there are similar instructions with different types they are sorted:
4997 // int before float
4998 // small before big
4999 // signed before unsigned
5000 // e.g., loadS before loadUS before loadI before loadF.
5001 
5002 
5003 //----------Load/Store Instructions--------------------------------------------
5004 
5005 //----------Load Instructions--------------------------------------------------
5006 
5007 // Converts byte to int.
5008 // As convB2I_reg, but without match rule.  The match rule of convB2I_reg
5009 // reuses the 'amount' operand, but adlc expects that operand specification
5010 // and operands in match rule are equivalent.
5011 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5012   effect(DEF dst, USE src);
5013   format %{ "EXTSB   $dst, $src \t// byte->int" %}
5014   size(4);
5015   ins_encode %{
5016     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5017     __ extsb($dst$$Register, $src$$Register);
5018   %}
5019   ins_pipe(pipe_class_default);
5020 %}
5021 
5022 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5023   // match-rule, false predicate
5024   match(Set dst (LoadB mem));
5025   predicate(false);
5026 
5027   format %{ "LBZ     $dst, $mem" %}
5028   size(4);
5029   ins_encode( enc_lbz(dst, mem) );
5030   ins_pipe(pipe_class_memory);
5031 %}
5032 
5033 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5034   // match-rule, false predicate
5035   match(Set dst (LoadB mem));
5036   predicate(false);
5037 
5038   format %{ "LBZ     $dst, $mem\n\t"
5039             "TWI     $dst\n\t"
5040             "ISYNC" %}
5041   size(12);
5042   ins_encode( enc_lbz_ac(dst, mem) );
5043   ins_pipe(pipe_class_memory);
5044 %}
5045 
5046 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5047 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5048   match(Set dst (LoadB mem));
5049   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5050   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5051   expand %{
5052     iRegIdst tmp;
5053     loadUB_indirect(tmp, mem);
5054     convB2I_reg_2(dst, tmp);
5055   %}
5056 %}
5057 
5058 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5059   match(Set dst (LoadB mem));
5060   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5061   expand %{
5062     iRegIdst tmp;
5063     loadUB_indirect_ac(tmp, mem);
5064     convB2I_reg_2(dst, tmp);
5065   %}
5066 %}
5067 
5068 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5069   // match-rule, false predicate
5070   match(Set dst (LoadB mem));
5071   predicate(false);
5072 
5073   format %{ "LBZ     $dst, $mem" %}
5074   size(4);
5075   ins_encode( enc_lbz(dst, mem) );
5076   ins_pipe(pipe_class_memory);
5077 %}
5078 
5079 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5080   // match-rule, false predicate
5081   match(Set dst (LoadB mem));
5082   predicate(false);
5083 
5084   format %{ "LBZ     $dst, $mem\n\t"
5085             "TWI     $dst\n\t"
5086             "ISYNC" %}
5087   size(12);
5088   ins_encode( enc_lbz_ac(dst, mem) );
5089   ins_pipe(pipe_class_memory);
5090 %}
5091 
5092 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5093 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5094   match(Set dst (LoadB mem));
5095   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5096   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5097 
5098   expand %{
5099     iRegIdst tmp;
5100     loadUB_indOffset16(tmp, mem);
5101     convB2I_reg_2(dst, tmp);
5102   %}
5103 %}
5104 
5105 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5106   match(Set dst (LoadB mem));
5107   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5108 
5109   expand %{
5110     iRegIdst tmp;
5111     loadUB_indOffset16_ac(tmp, mem);
5112     convB2I_reg_2(dst, tmp);
5113   %}
5114 %}
5115 
5116 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5117 instruct loadUB(iRegIdst dst, memory mem) %{
5118   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5119   match(Set dst (LoadUB mem));
5120   ins_cost(MEMORY_REF_COST);
5121 
5122   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int" %}
5123   size(4);
5124   ins_encode( enc_lbz(dst, mem) );
5125   ins_pipe(pipe_class_memory);
5126 %}
5127 
5128 // Load  Unsigned Byte (8bit UNsigned) acquire.
5129 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5130   match(Set dst (LoadUB mem));
5131   ins_cost(3*MEMORY_REF_COST);
5132 
5133   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5134             "TWI     $dst\n\t"
5135             "ISYNC" %}
5136   size(12);
5137   ins_encode( enc_lbz_ac(dst, mem) );
5138   ins_pipe(pipe_class_memory);
5139 %}
5140 
5141 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5142 instruct loadUB2L(iRegLdst dst, memory mem) %{
5143   match(Set dst (ConvI2L (LoadUB mem)));
5144   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5145   ins_cost(MEMORY_REF_COST);
5146 
5147   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long" %}
5148   size(4);
5149   ins_encode( enc_lbz(dst, mem) );
5150   ins_pipe(pipe_class_memory);
5151 %}
5152 
5153 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5154   match(Set dst (ConvI2L (LoadUB mem)));
5155   ins_cost(3*MEMORY_REF_COST);
5156 
5157   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5158             "TWI     $dst\n\t"
5159             "ISYNC" %}
5160   size(12);
5161   ins_encode( enc_lbz_ac(dst, mem) );
5162   ins_pipe(pipe_class_memory);
5163 %}
5164 
5165 // Load Short (16bit signed)
5166 instruct loadS(iRegIdst dst, memory mem) %{
5167   match(Set dst (LoadS mem));
5168   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5169   ins_cost(MEMORY_REF_COST);
5170 
5171   format %{ "LHA     $dst, $mem" %}
5172   size(4);
5173   ins_encode %{
5174     // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5175     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5176     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5177   %}
5178   ins_pipe(pipe_class_memory);
5179 %}
5180 
5181 // Load Short (16bit signed) acquire.
5182 instruct loadS_ac(iRegIdst dst, memory mem) %{
5183   match(Set dst (LoadS mem));
5184   ins_cost(3*MEMORY_REF_COST);
5185 
5186   format %{ "LHA     $dst, $mem\t acquire\n\t"
5187             "TWI     $dst\n\t"
5188             "ISYNC" %}
5189   size(12);
5190   ins_encode %{
5191     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5192     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5193     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5194     __ twi_0($dst$$Register);
5195     __ isync();
5196   %}
5197   ins_pipe(pipe_class_memory);
5198 %}
5199 
5200 // Load Char (16bit unsigned)
5201 instruct loadUS(iRegIdst dst, memory mem) %{
5202   match(Set dst (LoadUS mem));
5203   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5204   ins_cost(MEMORY_REF_COST);
5205 
5206   format %{ "LHZ     $dst, $mem" %}
5207   size(4);
5208   ins_encode( enc_lhz(dst, mem) );
5209   ins_pipe(pipe_class_memory);
5210 %}
5211 
5212 // Load Char (16bit unsigned) acquire.
5213 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5214   match(Set dst (LoadUS mem));
5215   ins_cost(3*MEMORY_REF_COST);
5216 
5217   format %{ "LHZ     $dst, $mem \t// acquire\n\t"
5218             "TWI     $dst\n\t"
5219             "ISYNC" %}
5220   size(12);
5221   ins_encode( enc_lhz_ac(dst, mem) );
5222   ins_pipe(pipe_class_memory);
5223 %}
5224 
5225 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5226 instruct loadUS2L(iRegLdst dst, memory mem) %{
5227   match(Set dst (ConvI2L (LoadUS mem)));
5228   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5229   ins_cost(MEMORY_REF_COST);
5230 
5231   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long" %}
5232   size(4);
5233   ins_encode( enc_lhz(dst, mem) );
5234   ins_pipe(pipe_class_memory);
5235 %}
5236 
5237 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5238 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5239   match(Set dst (ConvI2L (LoadUS mem)));
5240   ins_cost(3*MEMORY_REF_COST);
5241 
5242   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5243             "TWI     $dst\n\t"
5244             "ISYNC" %}
5245   size(12);
5246   ins_encode( enc_lhz_ac(dst, mem) );
5247   ins_pipe(pipe_class_memory);
5248 %}
5249 
5250 // Load Integer.
5251 instruct loadI(iRegIdst dst, memory mem) %{
5252   match(Set dst (LoadI mem));
5253   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5254   ins_cost(MEMORY_REF_COST);
5255 
5256   format %{ "LWZ     $dst, $mem" %}
5257   size(4);
5258   ins_encode( enc_lwz(dst, mem) );
5259   ins_pipe(pipe_class_memory);
5260 %}
5261 
5262 // Load Integer acquire.
5263 instruct loadI_ac(iRegIdst dst, memory mem) %{
5264   match(Set dst (LoadI mem));
5265   ins_cost(3*MEMORY_REF_COST);
5266 
5267   format %{ "LWZ     $dst, $mem \t// load acquire\n\t"
5268             "TWI     $dst\n\t"
5269             "ISYNC" %}
5270   size(12);
5271   ins_encode( enc_lwz_ac(dst, mem) );
5272   ins_pipe(pipe_class_memory);
5273 %}
5274 
5275 // Match loading integer and casting it to unsigned int in
5276 // long register.
5277 // LoadI + ConvI2L + AndL 0xffffffff.
5278 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5279   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5280   predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5281   ins_cost(MEMORY_REF_COST);
5282 
5283   format %{ "LWZ     $dst, $mem \t// zero-extend to long" %}
5284   size(4);
5285   ins_encode( enc_lwz(dst, mem) );
5286   ins_pipe(pipe_class_memory);
5287 %}
5288 
5289 // Match loading integer and casting it to long.
5290 instruct loadI2L(iRegLdst dst, memoryAlg4 mem) %{
5291   match(Set dst (ConvI2L (LoadI mem)));
5292   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5293   ins_cost(MEMORY_REF_COST);
5294 
5295   format %{ "LWA     $dst, $mem \t// loadI2L" %}
5296   size(4);
5297   ins_encode %{
5298     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5299     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5300     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5301   %}
5302   ins_pipe(pipe_class_memory);
5303 %}
5304 
5305 // Match loading integer and casting it to long - acquire.
5306 instruct loadI2L_ac(iRegLdst dst, memoryAlg4 mem) %{
5307   match(Set dst (ConvI2L (LoadI mem)));
5308   ins_cost(3*MEMORY_REF_COST);
5309 
5310   format %{ "LWA     $dst, $mem \t// loadI2L acquire"
5311             "TWI     $dst\n\t"
5312             "ISYNC" %}
5313   size(12);
5314   ins_encode %{
5315     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5316     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5317     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5318     __ twi_0($dst$$Register);
5319     __ isync();
5320   %}
5321   ins_pipe(pipe_class_memory);
5322 %}
5323 
5324 // Load Long - aligned
5325 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5326   match(Set dst (LoadL mem));
5327   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5328   ins_cost(MEMORY_REF_COST);
5329 
5330   format %{ "LD      $dst, $mem \t// long" %}
5331   size(4);
5332   ins_encode( enc_ld(dst, mem) );
5333   ins_pipe(pipe_class_memory);
5334 %}
5335 
5336 // Load Long - aligned acquire.
5337 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5338   match(Set dst (LoadL mem));
5339   ins_cost(3*MEMORY_REF_COST);
5340 
5341   format %{ "LD      $dst, $mem \t// long acquire\n\t"
5342             "TWI     $dst\n\t"
5343             "ISYNC" %}
5344   size(12);
5345   ins_encode( enc_ld_ac(dst, mem) );
5346   ins_pipe(pipe_class_memory);
5347 %}
5348 
5349 // Load Long - UNaligned
5350 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5351   match(Set dst (LoadL_unaligned mem));
5352   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5353   ins_cost(MEMORY_REF_COST);
5354 
5355   format %{ "LD      $dst, $mem \t// unaligned long" %}
5356   size(4);
5357   ins_encode( enc_ld(dst, mem) );
5358   ins_pipe(pipe_class_memory);
5359 %}
5360 
5361 // Load nodes for superwords
5362 
5363 // Load Aligned Packed Byte
5364 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5365   predicate(n->as_LoadVector()->memory_size() == 8);
5366   match(Set dst (LoadVector mem));
5367   ins_cost(MEMORY_REF_COST);
5368 
5369   format %{ "LD      $dst, $mem \t// load 8-byte Vector" %}
5370   size(4);
5371   ins_encode( enc_ld(dst, mem) );
5372   ins_pipe(pipe_class_memory);
5373 %}
5374 
5375 // Load Range, range = array length (=jint)
5376 instruct loadRange(iRegIdst dst, memory mem) %{
5377   match(Set dst (LoadRange mem));
5378   ins_cost(MEMORY_REF_COST);
5379 
5380   format %{ "LWZ     $dst, $mem \t// range" %}
5381   size(4);
5382   ins_encode( enc_lwz(dst, mem) );
5383   ins_pipe(pipe_class_memory);
5384 %}
5385 
5386 // Load Compressed Pointer
5387 instruct loadN(iRegNdst dst, memory mem) %{
5388   match(Set dst (LoadN mem));
5389   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5390   ins_cost(MEMORY_REF_COST);
5391 
5392   format %{ "LWZ     $dst, $mem \t// load compressed ptr" %}
5393   size(4);
5394   ins_encode( enc_lwz(dst, mem) );
5395   ins_pipe(pipe_class_memory);
5396 %}
5397 
5398 // Load Compressed Pointer acquire.
5399 instruct loadN_ac(iRegNdst dst, memory mem) %{
5400   match(Set dst (LoadN mem));
5401   ins_cost(3*MEMORY_REF_COST);
5402 
5403   format %{ "LWZ     $dst, $mem \t// load acquire compressed ptr\n\t"
5404             "TWI     $dst\n\t"
5405             "ISYNC" %}
5406   size(12);
5407   ins_encode( enc_lwz_ac(dst, mem) );
5408   ins_pipe(pipe_class_memory);
5409 %}
5410 
5411 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5412 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5413   match(Set dst (DecodeN (LoadN mem)));
5414   predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5415   ins_cost(MEMORY_REF_COST);
5416 
5417   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5418   size(4);
5419   ins_encode( enc_lwz(dst, mem) );
5420   ins_pipe(pipe_class_memory);
5421 %}
5422 
5423 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5424   match(Set dst (DecodeNKlass (LoadNKlass mem)));
5425   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5426             _kids[0]->_leaf->as_Load()->is_unordered());
5427   ins_cost(MEMORY_REF_COST);
5428 
5429   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5430   size(4);
5431   ins_encode( enc_lwz(dst, mem) );
5432   ins_pipe(pipe_class_memory);
5433 %}
5434 
5435 // Load Pointer
5436 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5437   match(Set dst (LoadP mem));
5438   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5439   ins_cost(MEMORY_REF_COST);
5440 
5441   format %{ "LD      $dst, $mem \t// ptr" %}
5442   size(4);
5443   ins_encode( enc_ld(dst, mem) );
5444   ins_pipe(pipe_class_memory);
5445 %}
5446 
5447 // Load Pointer acquire.
5448 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5449   match(Set dst (LoadP mem));
5450   ins_cost(3*MEMORY_REF_COST);
5451 
5452   format %{ "LD      $dst, $mem \t// ptr acquire\n\t"
5453             "TWI     $dst\n\t"
5454             "ISYNC" %}
5455   size(12);
5456   ins_encode( enc_ld_ac(dst, mem) );
5457   ins_pipe(pipe_class_memory);
5458 %}
5459 
5460 // LoadP + CastP2L
5461 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5462   match(Set dst (CastP2X (LoadP mem)));
5463   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5464   ins_cost(MEMORY_REF_COST);
5465 
5466   format %{ "LD      $dst, $mem \t// ptr + p2x" %}
5467   size(4);
5468   ins_encode( enc_ld(dst, mem) );
5469   ins_pipe(pipe_class_memory);
5470 %}
5471 
5472 // Load compressed klass pointer.
5473 instruct loadNKlass(iRegNdst dst, memory mem) %{
5474   match(Set dst (LoadNKlass mem));
5475   ins_cost(MEMORY_REF_COST);
5476 
5477   format %{ "LWZ     $dst, $mem \t// compressed klass ptr" %}
5478   size(4);
5479   ins_encode( enc_lwz(dst, mem) );
5480   ins_pipe(pipe_class_memory);
5481 %}
5482 
5483 // Load Klass Pointer
5484 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5485   match(Set dst (LoadKlass mem));
5486   ins_cost(MEMORY_REF_COST);
5487 
5488   format %{ "LD      $dst, $mem \t// klass ptr" %}
5489   size(4);
5490   ins_encode( enc_ld(dst, mem) );
5491   ins_pipe(pipe_class_memory);
5492 %}
5493 
5494 // Load Float
5495 instruct loadF(regF dst, memory mem) %{
5496   match(Set dst (LoadF mem));
5497   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5498   ins_cost(MEMORY_REF_COST);
5499 
5500   format %{ "LFS     $dst, $mem" %}
5501   size(4);
5502   ins_encode %{
5503     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5504     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5505     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5506   %}
5507   ins_pipe(pipe_class_memory);
5508 %}
5509 
5510 // Load Float acquire.
5511 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5512   match(Set dst (LoadF mem));
5513   effect(TEMP cr0);
5514   ins_cost(3*MEMORY_REF_COST);
5515 
5516   format %{ "LFS     $dst, $mem \t// acquire\n\t"
5517             "FCMPU   cr0, $dst, $dst\n\t"
5518             "BNE     cr0, next\n"
5519             "next:\n\t"
5520             "ISYNC" %}
5521   size(16);
5522   ins_encode %{
5523     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5524     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5525     Label next;
5526     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5527     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5528     __ bne(CCR0, next);
5529     __ bind(next);
5530     __ isync();
5531   %}
5532   ins_pipe(pipe_class_memory);
5533 %}
5534 
5535 // Load Double - aligned
5536 instruct loadD(regD dst, memory mem) %{
5537   match(Set dst (LoadD mem));
5538   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5539   ins_cost(MEMORY_REF_COST);
5540 
5541   format %{ "LFD     $dst, $mem" %}
5542   size(4);
5543   ins_encode( enc_lfd(dst, mem) );
5544   ins_pipe(pipe_class_memory);
5545 %}
5546 
5547 // Load Double - aligned acquire.
5548 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5549   match(Set dst (LoadD mem));
5550   effect(TEMP cr0);
5551   ins_cost(3*MEMORY_REF_COST);
5552 
5553   format %{ "LFD     $dst, $mem \t// acquire\n\t"
5554             "FCMPU   cr0, $dst, $dst\n\t"
5555             "BNE     cr0, next\n"
5556             "next:\n\t"
5557             "ISYNC" %}
5558   size(16);
5559   ins_encode %{
5560     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5561     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5562     Label next;
5563     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5564     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5565     __ bne(CCR0, next);
5566     __ bind(next);
5567     __ isync();
5568   %}
5569   ins_pipe(pipe_class_memory);
5570 %}
5571 
5572 // Load Double - UNaligned
5573 instruct loadD_unaligned(regD dst, memory mem) %{
5574   match(Set dst (LoadD_unaligned mem));
5575   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5576   ins_cost(MEMORY_REF_COST);
5577 
5578   format %{ "LFD     $dst, $mem" %}
5579   size(4);
5580   ins_encode( enc_lfd(dst, mem) );
5581   ins_pipe(pipe_class_memory);
5582 %}
5583 
5584 //----------Constants--------------------------------------------------------
5585 
5586 // Load MachConstantTableBase: add hi offset to global toc.
5587 // TODO: Handle hidden register r29 in bundler!
5588 instruct loadToc_hi(iRegLdst dst) %{
5589   effect(DEF dst);
5590   ins_cost(DEFAULT_COST);
5591 
5592   format %{ "ADDIS   $dst, R29, DISP.hi \t// load TOC hi" %}
5593   size(4);
5594   ins_encode %{
5595     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5596     __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5597   %}
5598   ins_pipe(pipe_class_default);
5599 %}
5600 
5601 // Load MachConstantTableBase: add lo offset to global toc.
5602 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5603   effect(DEF dst, USE src);
5604   ins_cost(DEFAULT_COST);
5605 
5606   format %{ "ADDI    $dst, $src, DISP.lo \t// load TOC lo" %}
5607   size(4);
5608   ins_encode %{
5609     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5610     __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5611   %}
5612   ins_pipe(pipe_class_default);
5613 %}
5614 
5615 // Load 16-bit integer constant 0xssss????
5616 instruct loadConI16(iRegIdst dst, immI16 src) %{
5617   match(Set dst src);
5618 
5619   format %{ "LI      $dst, $src" %}
5620   size(4);
5621   ins_encode %{
5622     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5623     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5624   %}
5625   ins_pipe(pipe_class_default);
5626 %}
5627 
5628 // Load integer constant 0x????0000
5629 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5630   match(Set dst src);
5631   ins_cost(DEFAULT_COST);
5632 
5633   format %{ "LIS     $dst, $src.hi" %}
5634   size(4);
5635   ins_encode %{
5636     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5637     // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5638     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5639   %}
5640   ins_pipe(pipe_class_default);
5641 %}
5642 
5643 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5644 // and sign extended), this adds the low 16 bits.
5645 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5646   // no match-rule, false predicate
5647   effect(DEF dst, USE src1, USE src2);
5648   predicate(false);
5649 
5650   format %{ "ORI     $dst, $src1.hi, $src2.lo" %}
5651   size(4);
5652   ins_encode %{
5653     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5654     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5655   %}
5656   ins_pipe(pipe_class_default);
5657 %}
5658 
5659 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5660   match(Set dst src);
5661   ins_cost(DEFAULT_COST*2);
5662 
5663   expand %{
5664     // Would like to use $src$$constant.
5665     immI16 srcLo %{ _opnds[1]->constant() %}
5666     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5667     immIhi16 srcHi %{ _opnds[1]->constant() %}
5668     iRegIdst tmpI;
5669     loadConIhi16(tmpI, srcHi);
5670     loadConI32_lo16(dst, tmpI, srcLo);
5671   %}
5672 %}
5673 
5674 // No constant pool entries required.
5675 instruct loadConL16(iRegLdst dst, immL16 src) %{
5676   match(Set dst src);
5677 
5678   format %{ "LI      $dst, $src \t// long" %}
5679   size(4);
5680   ins_encode %{
5681     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5682     __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5683   %}
5684   ins_pipe(pipe_class_default);
5685 %}
5686 
5687 // Load long constant 0xssssssss????0000
5688 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5689   match(Set dst src);
5690   ins_cost(DEFAULT_COST);
5691 
5692   format %{ "LIS     $dst, $src.hi \t// long" %}
5693   size(4);
5694   ins_encode %{
5695     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5696     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5697   %}
5698   ins_pipe(pipe_class_default);
5699 %}
5700 
5701 // To load a 32 bit constant: merge lower 16 bits into already loaded
5702 // high 16 bits.
5703 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5704   // no match-rule, false predicate
5705   effect(DEF dst, USE src1, USE src2);
5706   predicate(false);
5707 
5708   format %{ "ORI     $dst, $src1, $src2.lo" %}
5709   size(4);
5710   ins_encode %{
5711     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5712     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5713   %}
5714   ins_pipe(pipe_class_default);
5715 %}
5716 
5717 // Load 32-bit long constant
5718 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5719   match(Set dst src);
5720   ins_cost(DEFAULT_COST*2);
5721 
5722   expand %{
5723     // Would like to use $src$$constant.
5724     immL16     srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5725     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5726     immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5727     iRegLdst tmpL;
5728     loadConL32hi16(tmpL, srcHi);
5729     loadConL32_lo16(dst, tmpL, srcLo);
5730   %}
5731 %}
5732 
5733 // Load long constant 0x????000000000000.
5734 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5735   match(Set dst src);
5736   ins_cost(DEFAULT_COST);
5737 
5738   expand %{
5739     immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5740     immI shift32 %{ 32 %}
5741     iRegLdst tmpL;
5742     loadConL32hi16(tmpL, srcHi);
5743     lshiftL_regL_immI(dst, tmpL, shift32);
5744   %}
5745 %}
5746 
5747 // Expand node for constant pool load: small offset.
5748 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5749   effect(DEF dst, USE src, USE toc);
5750   ins_cost(MEMORY_REF_COST);
5751 
5752   ins_num_consts(1);
5753   // Needed so that CallDynamicJavaDirect can compute the address of this
5754   // instruction for relocation.
5755   ins_field_cbuf_insts_offset(int);
5756 
5757   format %{ "LD      $dst, offset, $toc \t// load long $src from TOC" %}
5758   size(4);
5759   ins_encode( enc_load_long_constL(dst, src, toc) );
5760   ins_pipe(pipe_class_memory);
5761 %}
5762 
5763 // Expand node for constant pool load: large offset.
5764 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5765   effect(DEF dst, USE src, USE toc);
5766   predicate(false);
5767 
5768   ins_num_consts(1);
5769   ins_field_const_toc_offset(int);
5770   // Needed so that CallDynamicJavaDirect can compute the address of this
5771   // instruction for relocation.
5772   ins_field_cbuf_insts_offset(int);
5773 
5774   format %{ "ADDIS   $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5775   size(4);
5776   ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5777   ins_pipe(pipe_class_default);
5778 %}
5779 
5780 // Expand node for constant pool load: large offset.
5781 // No constant pool entries required.
5782 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5783   effect(DEF dst, USE src, USE base);
5784   predicate(false);
5785 
5786   ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5787 
5788   format %{ "LD      $dst, offset, $base \t// load long $src from TOC (lo)" %}
5789   size(4);
5790   ins_encode %{
5791     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5792     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5793     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5794   %}
5795   ins_pipe(pipe_class_memory);
5796 %}
5797 
5798 // Load long constant from constant table. Expand in case of
5799 // offset > 16 bit is needed.
5800 // Adlc adds toc node MachConstantTableBase.
5801 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5802   match(Set dst src);
5803   ins_cost(MEMORY_REF_COST);
5804 
5805   format %{ "LD      $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5806   // We can not inline the enc_class for the expand as that does not support constanttablebase.
5807   postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5808 %}
5809 
5810 // Load NULL as compressed oop.
5811 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5812   match(Set dst src);
5813   ins_cost(DEFAULT_COST);
5814 
5815   format %{ "LI      $dst, $src \t// compressed ptr" %}
5816   size(4);
5817   ins_encode %{
5818     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5819     __ li($dst$$Register, 0);
5820   %}
5821   ins_pipe(pipe_class_default);
5822 %}
5823 
5824 // Load hi part of compressed oop constant.
5825 instruct loadConN_hi(iRegNdst dst, immN src) %{
5826   effect(DEF dst, USE src);
5827   ins_cost(DEFAULT_COST);
5828 
5829   format %{ "LIS     $dst, $src \t// narrow oop hi" %}
5830   size(4);
5831   ins_encode %{
5832     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5833     __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5834   %}
5835   ins_pipe(pipe_class_default);
5836 %}
5837 
5838 // Add lo part of compressed oop constant to already loaded hi part.
5839 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5840   effect(DEF dst, USE src1, USE src2);
5841   ins_cost(DEFAULT_COST);
5842 
5843   format %{ "ORI     $dst, $src1, $src2 \t// narrow oop lo" %}
5844   size(4);
5845   ins_encode %{
5846     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5847     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5848     int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5849     RelocationHolder rspec = oop_Relocation::spec(oop_index);
5850     __ relocate(rspec, 1);
5851     __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5852   %}
5853   ins_pipe(pipe_class_default);
5854 %}
5855 
5856 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5857 // leaving the upper 32 bits with sign-extension bits.
5858 // This clears these bits: dst = src & 0xFFFFFFFF.
5859 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5860 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5861   effect(DEF dst, USE src);
5862   predicate(false);
5863 
5864   format %{ "MASK    $dst, $src, 0xFFFFFFFF" %} // mask
5865   size(4);
5866   ins_encode %{
5867     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5868     __ clrldi($dst$$Register, $src$$Register, 0x20);
5869   %}
5870   ins_pipe(pipe_class_default);
5871 %}
5872 
5873 // Optimize DecodeN for disjoint base.
5874 // Load base of compressed oops into a register
5875 instruct loadBase(iRegLdst dst) %{
5876   effect(DEF dst);
5877 
5878   format %{ "LoadConst $dst, heapbase" %}
5879   ins_encode %{
5880     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5881     __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
5882   %}
5883   ins_pipe(pipe_class_default);
5884 %}
5885 
5886 // Loading ConN must be postalloc expanded so that edges between
5887 // the nodes are safe. They may not interfere with a safepoint.
5888 // GL TODO: This needs three instructions: better put this into the constant pool.
5889 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5890   match(Set dst src);
5891   ins_cost(DEFAULT_COST*2);
5892 
5893   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
5894   postalloc_expand %{
5895     MachNode *m1 = new loadConN_hiNode();
5896     MachNode *m2 = new loadConN_loNode();
5897     MachNode *m3 = new clearMs32bNode();
5898     m1->add_req(NULL);
5899     m2->add_req(NULL, m1);
5900     m3->add_req(NULL, m2);
5901     m1->_opnds[0] = op_dst;
5902     m1->_opnds[1] = op_src;
5903     m2->_opnds[0] = op_dst;
5904     m2->_opnds[1] = op_dst;
5905     m2->_opnds[2] = op_src;
5906     m3->_opnds[0] = op_dst;
5907     m3->_opnds[1] = op_dst;
5908     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5909     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5910     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5911     nodes->push(m1);
5912     nodes->push(m2);
5913     nodes->push(m3);
5914   %}
5915 %}
5916 
5917 // We have seen a safepoint between the hi and lo parts, and this node was handled
5918 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
5919 // not a narrow oop.
5920 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
5921   match(Set dst src);
5922   effect(DEF dst, USE src);
5923   ins_cost(DEFAULT_COST);
5924 
5925   format %{ "LIS     $dst, $src \t// narrow klass hi" %}
5926   size(4);
5927   ins_encode %{
5928     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5929     intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
5930     __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
5931   %}
5932   ins_pipe(pipe_class_default);
5933 %}
5934 
5935 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
5936 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
5937   match(Set dst src1);
5938   effect(TEMP src2);
5939   ins_cost(DEFAULT_COST);
5940 
5941   format %{ "MASK    $dst, $src2, 0xFFFFFFFF" %} // mask
5942   size(4);
5943   ins_encode %{
5944     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5945     __ clrldi($dst$$Register, $src2$$Register, 0x20);
5946   %}
5947   ins_pipe(pipe_class_default);
5948 %}
5949 
5950 // This needs a match rule so that build_oop_map knows this is
5951 // not a narrow oop.
5952 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
5953   match(Set dst src1);
5954   effect(TEMP src2);
5955   ins_cost(DEFAULT_COST);
5956 
5957   format %{ "ORI     $dst, $src1, $src2 \t// narrow klass lo" %}
5958   size(4);
5959   ins_encode %{
5960     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5961     intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
5962     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5963     int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
5964     RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5965 
5966     __ relocate(rspec, 1);
5967     __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
5968   %}
5969   ins_pipe(pipe_class_default);
5970 %}
5971 
5972 // Loading ConNKlass must be postalloc expanded so that edges between
5973 // the nodes are safe. They may not interfere with a safepoint.
5974 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
5975   match(Set dst src);
5976   ins_cost(DEFAULT_COST*2);
5977 
5978   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
5979   postalloc_expand %{
5980     // Load high bits into register. Sign extended.
5981     MachNode *m1 = new loadConNKlass_hiNode();
5982     m1->add_req(NULL);
5983     m1->_opnds[0] = op_dst;
5984     m1->_opnds[1] = op_src;
5985     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5986     nodes->push(m1);
5987 
5988     MachNode *m2 = m1;
5989     if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
5990       // Value might be 1-extended. Mask out these bits.
5991       m2 = new loadConNKlass_maskNode();
5992       m2->add_req(NULL, m1);
5993       m2->_opnds[0] = op_dst;
5994       m2->_opnds[1] = op_src;
5995       m2->_opnds[2] = op_dst;
5996       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5997       nodes->push(m2);
5998     }
5999 
6000     MachNode *m3 = new loadConNKlass_loNode();
6001     m3->add_req(NULL, m2);
6002     m3->_opnds[0] = op_dst;
6003     m3->_opnds[1] = op_src;
6004     m3->_opnds[2] = op_dst;
6005     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6006     nodes->push(m3);
6007   %}
6008 %}
6009 
6010 // 0x1 is used in object initialization (initial object header).
6011 // No constant pool entries required.
6012 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6013   match(Set dst src);
6014 
6015   format %{ "LI      $dst, $src \t// ptr" %}
6016   size(4);
6017   ins_encode %{
6018     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6019     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6020   %}
6021   ins_pipe(pipe_class_default);
6022 %}
6023 
6024 // Expand node for constant pool load: small offset.
6025 // The match rule is needed to generate the correct bottom_type(),
6026 // however this node should never match. The use of predicate is not
6027 // possible since ADLC forbids predicates for chain rules. The higher
6028 // costs do not prevent matching in this case. For that reason the
6029 // operand immP_NM with predicate(false) is used.
6030 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6031   match(Set dst src);
6032   effect(TEMP toc);
6033 
6034   ins_num_consts(1);
6035 
6036   format %{ "LD      $dst, offset, $toc \t// load ptr $src from TOC" %}
6037   size(4);
6038   ins_encode( enc_load_long_constP(dst, src, toc) );
6039   ins_pipe(pipe_class_memory);
6040 %}
6041 
6042 // Expand node for constant pool load: large offset.
6043 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6044   effect(DEF dst, USE src, USE toc);
6045   predicate(false);
6046 
6047   ins_num_consts(1);
6048   ins_field_const_toc_offset(int);
6049 
6050   format %{ "ADDIS   $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6051   size(4);
6052   ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6053   ins_pipe(pipe_class_default);
6054 %}
6055 
6056 // Expand node for constant pool load: large offset.
6057 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6058   match(Set dst src);
6059   effect(TEMP base);
6060 
6061   ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6062 
6063   format %{ "LD      $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6064   size(4);
6065   ins_encode %{
6066     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6067     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6068     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6069   %}
6070   ins_pipe(pipe_class_memory);
6071 %}
6072 
6073 // Load pointer constant from constant table. Expand in case an
6074 // offset > 16 bit is needed.
6075 // Adlc adds toc node MachConstantTableBase.
6076 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6077   match(Set dst src);
6078   ins_cost(MEMORY_REF_COST);
6079 
6080   // This rule does not use "expand" because then
6081   // the result type is not known to be an Oop.  An ADLC
6082   // enhancement will be needed to make that work - not worth it!
6083 
6084   // If this instruction rematerializes, it prolongs the live range
6085   // of the toc node, causing illegal graphs.
6086   // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6087   ins_cannot_rematerialize(true);
6088 
6089   format %{ "LD    $dst, offset, $constanttablebase \t//  load ptr $src from table, postalloc expanded" %}
6090   postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6091 %}
6092 
6093 // Expand node for constant pool load: small offset.
6094 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6095   effect(DEF dst, USE src, USE toc);
6096   ins_cost(MEMORY_REF_COST);
6097 
6098   ins_num_consts(1);
6099 
6100   format %{ "LFS     $dst, offset, $toc \t// load float $src from TOC" %}
6101   size(4);
6102   ins_encode %{
6103     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6104     address float_address = __ float_constant($src$$constant);
6105     if (float_address == NULL) {
6106       ciEnv::current()->record_out_of_memory_failure();
6107       return;
6108     }
6109     __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6110   %}
6111   ins_pipe(pipe_class_memory);
6112 %}
6113 
6114 // Expand node for constant pool load: large offset.
6115 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6116   effect(DEF dst, USE src, USE toc);
6117   ins_cost(MEMORY_REF_COST);
6118 
6119   ins_num_consts(1);
6120 
6121   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6122             "LFS     $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6123             "ADDIS   $toc, $toc, -offset_hi"%}
6124   size(12);
6125   ins_encode %{
6126     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6127     FloatRegister Rdst    = $dst$$FloatRegister;
6128     Register Rtoc         = $toc$$Register;
6129     address float_address = __ float_constant($src$$constant);
6130     if (float_address == NULL) {
6131       ciEnv::current()->record_out_of_memory_failure();
6132       return;
6133     }
6134     int offset            = __ offset_to_method_toc(float_address);
6135     int hi = (offset + (1<<15))>>16;
6136     int lo = offset - hi * (1<<16);
6137 
6138     __ addis(Rtoc, Rtoc, hi);
6139     __ lfs(Rdst, lo, Rtoc);
6140     __ addis(Rtoc, Rtoc, -hi);
6141   %}
6142   ins_pipe(pipe_class_memory);
6143 %}
6144 
6145 // Adlc adds toc node MachConstantTableBase.
6146 instruct loadConF_Ex(regF dst, immF src) %{
6147   match(Set dst src);
6148   ins_cost(MEMORY_REF_COST);
6149 
6150   // See loadConP.
6151   ins_cannot_rematerialize(true);
6152 
6153   format %{ "LFS     $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6154   postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6155 %}
6156 
6157 // Expand node for constant pool load: small offset.
6158 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6159   effect(DEF dst, USE src, USE toc);
6160   ins_cost(MEMORY_REF_COST);
6161 
6162   ins_num_consts(1);
6163 
6164   format %{ "LFD     $dst, offset, $toc \t// load double $src from TOC" %}
6165   size(4);
6166   ins_encode %{
6167     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6168     address float_address = __ double_constant($src$$constant);
6169     if (float_address == NULL) {
6170       ciEnv::current()->record_out_of_memory_failure();
6171       return;
6172     }
6173     int offset =  __ offset_to_method_toc(float_address);
6174     __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6175   %}
6176   ins_pipe(pipe_class_memory);
6177 %}
6178 
6179 // Expand node for constant pool load: large offset.
6180 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6181   effect(DEF dst, USE src, USE toc);
6182   ins_cost(MEMORY_REF_COST);
6183 
6184   ins_num_consts(1);
6185 
6186   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6187             "LFD     $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6188             "ADDIS   $toc, $toc, -offset_hi" %}
6189   size(12);
6190   ins_encode %{
6191     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6192     FloatRegister Rdst    = $dst$$FloatRegister;
6193     Register      Rtoc    = $toc$$Register;
6194     address float_address = __ double_constant($src$$constant);
6195     if (float_address == NULL) {
6196       ciEnv::current()->record_out_of_memory_failure();
6197       return;
6198     }
6199     int offset = __ offset_to_method_toc(float_address);
6200     int hi = (offset + (1<<15))>>16;
6201     int lo = offset - hi * (1<<16);
6202 
6203     __ addis(Rtoc, Rtoc, hi);
6204     __ lfd(Rdst, lo, Rtoc);
6205     __ addis(Rtoc, Rtoc, -hi);
6206   %}
6207   ins_pipe(pipe_class_memory);
6208 %}
6209 
6210 // Adlc adds toc node MachConstantTableBase.
6211 instruct loadConD_Ex(regD dst, immD src) %{
6212   match(Set dst src);
6213   ins_cost(MEMORY_REF_COST);
6214 
6215   // See loadConP.
6216   ins_cannot_rematerialize(true);
6217 
6218   format %{ "ConD    $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6219   postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6220 %}
6221 
6222 // Prefetch instructions.
6223 // Must be safe to execute with invalid address (cannot fault).
6224 
6225 // Special prefetch versions which use the dcbz instruction.
6226 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6227   match(PrefetchAllocation (AddP mem src));
6228   predicate(AllocatePrefetchStyle == 3);
6229   ins_cost(MEMORY_REF_COST);
6230 
6231   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6232   size(4);
6233   ins_encode %{
6234     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6235     __ dcbz($src$$Register, $mem$$base$$Register);
6236   %}
6237   ins_pipe(pipe_class_memory);
6238 %}
6239 
6240 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6241   match(PrefetchAllocation mem);
6242   predicate(AllocatePrefetchStyle == 3);
6243   ins_cost(MEMORY_REF_COST);
6244 
6245   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6246   size(4);
6247   ins_encode %{
6248     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6249     __ dcbz($mem$$base$$Register);
6250   %}
6251   ins_pipe(pipe_class_memory);
6252 %}
6253 
6254 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6255   match(PrefetchAllocation (AddP mem src));
6256   predicate(AllocatePrefetchStyle != 3);
6257   ins_cost(MEMORY_REF_COST);
6258 
6259   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6260   size(4);
6261   ins_encode %{
6262     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6263     __ dcbtst($src$$Register, $mem$$base$$Register);
6264   %}
6265   ins_pipe(pipe_class_memory);
6266 %}
6267 
6268 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6269   match(PrefetchAllocation mem);
6270   predicate(AllocatePrefetchStyle != 3);
6271   ins_cost(MEMORY_REF_COST);
6272 
6273   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6274   size(4);
6275   ins_encode %{
6276     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6277     __ dcbtst($mem$$base$$Register);
6278   %}
6279   ins_pipe(pipe_class_memory);
6280 %}
6281 
6282 //----------Store Instructions-------------------------------------------------
6283 
6284 // Store Byte
6285 instruct storeB(memory mem, iRegIsrc src) %{
6286   match(Set mem (StoreB mem src));
6287   ins_cost(MEMORY_REF_COST);
6288 
6289   format %{ "STB     $src, $mem \t// byte" %}
6290   size(4);
6291   ins_encode %{
6292     // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6293     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6294     __ stb($src$$Register, Idisp, $mem$$base$$Register);
6295   %}
6296   ins_pipe(pipe_class_memory);
6297 %}
6298 
6299 // Store Char/Short
6300 instruct storeC(memory mem, iRegIsrc src) %{
6301   match(Set mem (StoreC mem src));
6302   ins_cost(MEMORY_REF_COST);
6303 
6304   format %{ "STH     $src, $mem \t// short" %}
6305   size(4);
6306   ins_encode %{
6307     // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6308     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6309     __ sth($src$$Register, Idisp, $mem$$base$$Register);
6310   %}
6311   ins_pipe(pipe_class_memory);
6312 %}
6313 
6314 // Store Integer
6315 instruct storeI(memory mem, iRegIsrc src) %{
6316   match(Set mem (StoreI mem src));
6317   ins_cost(MEMORY_REF_COST);
6318 
6319   format %{ "STW     $src, $mem" %}
6320   size(4);
6321   ins_encode( enc_stw(src, mem) );
6322   ins_pipe(pipe_class_memory);
6323 %}
6324 
6325 // ConvL2I + StoreI.
6326 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6327   match(Set mem (StoreI mem (ConvL2I src)));
6328   ins_cost(MEMORY_REF_COST);
6329 
6330   format %{ "STW     l2i($src), $mem" %}
6331   size(4);
6332   ins_encode( enc_stw(src, mem) );
6333   ins_pipe(pipe_class_memory);
6334 %}
6335 
6336 // Store Long
6337 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6338   match(Set mem (StoreL mem src));
6339   ins_cost(MEMORY_REF_COST);
6340 
6341   format %{ "STD     $src, $mem \t// long" %}
6342   size(4);
6343   ins_encode( enc_std(src, mem) );
6344   ins_pipe(pipe_class_memory);
6345 %}
6346 
6347 // Store super word nodes.
6348 
6349 // Store Aligned Packed Byte long register to memory
6350 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6351   predicate(n->as_StoreVector()->memory_size() == 8);
6352   match(Set mem (StoreVector mem src));
6353   ins_cost(MEMORY_REF_COST);
6354 
6355   format %{ "STD     $mem, $src \t// packed8B" %}
6356   size(4);
6357   ins_encode( enc_std(src, mem) );
6358   ins_pipe(pipe_class_memory);
6359 %}
6360 
6361 // Store Compressed Oop
6362 instruct storeN(memory dst, iRegN_P2N src) %{
6363   match(Set dst (StoreN dst src));
6364   ins_cost(MEMORY_REF_COST);
6365 
6366   format %{ "STW     $src, $dst \t// compressed oop" %}
6367   size(4);
6368   ins_encode( enc_stw(src, dst) );
6369   ins_pipe(pipe_class_memory);
6370 %}
6371 
6372 // Store Compressed KLass
6373 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6374   match(Set dst (StoreNKlass dst src));
6375   ins_cost(MEMORY_REF_COST);
6376 
6377   format %{ "STW     $src, $dst \t// compressed klass" %}
6378   size(4);
6379   ins_encode( enc_stw(src, dst) );
6380   ins_pipe(pipe_class_memory);
6381 %}
6382 
6383 // Store Pointer
6384 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6385   match(Set dst (StoreP dst src));
6386   ins_cost(MEMORY_REF_COST);
6387 
6388   format %{ "STD     $src, $dst \t// ptr" %}
6389   size(4);
6390   ins_encode( enc_std(src, dst) );
6391   ins_pipe(pipe_class_memory);
6392 %}
6393 
6394 // Store Float
6395 instruct storeF(memory mem, regF src) %{
6396   match(Set mem (StoreF mem src));
6397   ins_cost(MEMORY_REF_COST);
6398 
6399   format %{ "STFS    $src, $mem" %}
6400   size(4);
6401   ins_encode( enc_stfs(src, mem) );
6402   ins_pipe(pipe_class_memory);
6403 %}
6404 
6405 // Store Double
6406 instruct storeD(memory mem, regD src) %{
6407   match(Set mem (StoreD mem src));
6408   ins_cost(MEMORY_REF_COST);
6409 
6410   format %{ "STFD    $src, $mem" %}
6411   size(4);
6412   ins_encode( enc_stfd(src, mem) );
6413   ins_pipe(pipe_class_memory);
6414 %}
6415 
6416 //----------Store Instructions With Zeros--------------------------------------
6417 
6418 // Card-mark for CMS garbage collection.
6419 // This cardmark does an optimization so that it must not always
6420 // do a releasing store. For this, it gets the address of
6421 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6422 // (Using releaseFieldAddr in the match rule is a hack.)
6423 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6424   match(Set mem (StoreCM mem releaseFieldAddr));
6425   effect(TEMP crx);
6426   predicate(false);
6427   ins_cost(MEMORY_REF_COST);
6428 
6429   // See loadConP.
6430   ins_cannot_rematerialize(true);
6431 
6432   format %{ "STB     #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6433   ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6434   ins_pipe(pipe_class_memory);
6435 %}
6436 
6437 // Card-mark for CMS garbage collection.
6438 // This cardmark does an optimization so that it must not always
6439 // do a releasing store. For this, it needs the constant address of
6440 // CMSCollectorCardTableModRefBSExt::_requires_release.
6441 // This constant address is split off here by expand so we can use
6442 // adlc / matcher functionality to load it from the constant section.
6443 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6444   match(Set mem (StoreCM mem zero));
6445   predicate(UseConcMarkSweepGC);
6446 
6447   expand %{
6448     immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6449     iRegLdst releaseFieldAddress;
6450     flagsReg crx;
6451     loadConL_Ex(releaseFieldAddress, baseImm);
6452     storeCM_CMS(mem, releaseFieldAddress, crx);
6453   %}
6454 %}
6455 
6456 instruct storeCM_G1(memory mem, immI_0 zero) %{
6457   match(Set mem (StoreCM mem zero));
6458   predicate(UseG1GC);
6459   ins_cost(MEMORY_REF_COST);
6460 
6461   ins_cannot_rematerialize(true);
6462 
6463   format %{ "STB     #0, $mem \t// CMS card-mark byte store (G1)" %}
6464   size(8);
6465   ins_encode %{
6466     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6467     __ li(R0, 0);
6468     //__ release(); // G1: oops are allowed to get visible after dirty marking
6469     guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6470     __ stb(R0, $mem$$disp, $mem$$base$$Register);
6471   %}
6472   ins_pipe(pipe_class_memory);
6473 %}
6474 
6475 // Convert oop pointer into compressed form.
6476 
6477 // Nodes for postalloc expand.
6478 
6479 // Shift node for expand.
6480 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6481   // The match rule is needed to make it a 'MachTypeNode'!
6482   match(Set dst (EncodeP src));
6483   predicate(false);
6484 
6485   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6486   size(4);
6487   ins_encode %{
6488     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6489     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6490   %}
6491   ins_pipe(pipe_class_default);
6492 %}
6493 
6494 // Add node for expand.
6495 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6496   // The match rule is needed to make it a 'MachTypeNode'!
6497   match(Set dst (EncodeP src));
6498   predicate(false);
6499 
6500   format %{ "SUB     $dst, $src, oop_base \t// encode" %}
6501   ins_encode %{
6502     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6503     __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6504   %}
6505   ins_pipe(pipe_class_default);
6506 %}
6507 
6508 // Conditional sub base.
6509 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6510   // The match rule is needed to make it a 'MachTypeNode'!
6511   match(Set dst (EncodeP (Binary crx src1)));
6512   predicate(false);
6513 
6514   format %{ "BEQ     $crx, done\n\t"
6515             "SUB     $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6516             "done:" %}
6517   ins_encode %{
6518     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6519     Label done;
6520     __ beq($crx$$CondRegister, done);
6521     __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6522     __ bind(done);
6523   %}
6524   ins_pipe(pipe_class_default);
6525 %}
6526 
6527 // Power 7 can use isel instruction
6528 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6529   // The match rule is needed to make it a 'MachTypeNode'!
6530   match(Set dst (EncodeP (Binary crx src1)));
6531   predicate(false);
6532 
6533   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6534   size(4);
6535   ins_encode %{
6536     // This is a Power7 instruction for which no machine description exists.
6537     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6538     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6539   %}
6540   ins_pipe(pipe_class_default);
6541 %}
6542 
6543 // Disjoint narrow oop base.
6544 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6545   match(Set dst (EncodeP src));
6546   predicate(Universe::narrow_oop_base_disjoint());
6547 
6548   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6549   size(4);
6550   ins_encode %{
6551     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6552     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6553   %}
6554   ins_pipe(pipe_class_default);
6555 %}
6556 
6557 // shift != 0, base != 0
6558 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6559   match(Set dst (EncodeP src));
6560   effect(TEMP crx);
6561   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6562             Universe::narrow_oop_shift() != 0 &&
6563             Universe::narrow_oop_base_overlaps());
6564 
6565   format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6566   postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6567 %}
6568 
6569 // shift != 0, base != 0
6570 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6571   match(Set dst (EncodeP src));
6572   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6573             Universe::narrow_oop_shift() != 0 &&
6574             Universe::narrow_oop_base_overlaps());
6575 
6576   format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6577   postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6578 %}
6579 
6580 // shift != 0, base == 0
6581 // TODO: This is the same as encodeP_shift. Merge!
6582 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6583   match(Set dst (EncodeP src));
6584   predicate(Universe::narrow_oop_shift() != 0 &&
6585             Universe::narrow_oop_base() ==0);
6586 
6587   format %{ "SRDI    $dst, $src, #3 \t// encodeP, $src != NULL" %}
6588   size(4);
6589   ins_encode %{
6590     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6591     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6592   %}
6593   ins_pipe(pipe_class_default);
6594 %}
6595 
6596 // Compressed OOPs with narrow_oop_shift == 0.
6597 // shift == 0, base == 0
6598 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6599   match(Set dst (EncodeP src));
6600   predicate(Universe::narrow_oop_shift() == 0);
6601 
6602   format %{ "MR      $dst, $src \t// Ptr->Narrow" %}
6603   // variable size, 0 or 4.
6604   ins_encode %{
6605     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6606     __ mr_if_needed($dst$$Register, $src$$Register);
6607   %}
6608   ins_pipe(pipe_class_default);
6609 %}
6610 
6611 // Decode nodes.
6612 
6613 // Shift node for expand.
6614 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6615   // The match rule is needed to make it a 'MachTypeNode'!
6616   match(Set dst (DecodeN src));
6617   predicate(false);
6618 
6619   format %{ "SLDI    $dst, $src, #3 \t// DecodeN" %}
6620   size(4);
6621   ins_encode %{
6622     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6623     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6624   %}
6625   ins_pipe(pipe_class_default);
6626 %}
6627 
6628 // Add node for expand.
6629 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6630   // The match rule is needed to make it a 'MachTypeNode'!
6631   match(Set dst (DecodeN src));
6632   predicate(false);
6633 
6634   format %{ "ADD     $dst, $src, heapbase \t// DecodeN, add oop base" %}
6635   ins_encode %{
6636     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6637     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6638   %}
6639   ins_pipe(pipe_class_default);
6640 %}
6641 
6642 // conditianal add base for expand
6643 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6644   // The match rule is needed to make it a 'MachTypeNode'!
6645   // NOTICE that the rule is nonsense - we just have to make sure that:
6646   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6647   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6648   match(Set dst (DecodeN (Binary crx src)));
6649   predicate(false);
6650 
6651   format %{ "BEQ     $crx, done\n\t"
6652             "ADD     $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6653             "done:" %}
6654   ins_encode %{
6655     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6656     Label done;
6657     __ beq($crx$$CondRegister, done);
6658     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6659     __ bind(done);
6660   %}
6661   ins_pipe(pipe_class_default);
6662 %}
6663 
6664 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6665   // The match rule is needed to make it a 'MachTypeNode'!
6666   // NOTICE that the rule is nonsense - we just have to make sure that:
6667   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6668   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6669   match(Set dst (DecodeN (Binary crx src1)));
6670   predicate(false);
6671 
6672   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6673   size(4);
6674   ins_encode %{
6675     // This is a Power7 instruction for which no machine description exists.
6676     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6677     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6678   %}
6679   ins_pipe(pipe_class_default);
6680 %}
6681 
6682 //  shift != 0, base != 0
6683 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6684   match(Set dst (DecodeN src));
6685   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6686              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6687             Universe::narrow_oop_shift() != 0 &&
6688             Universe::narrow_oop_base() != 0);
6689   ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6690   effect(TEMP crx);
6691 
6692   format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6693   postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6694 %}
6695 
6696 // shift != 0, base == 0
6697 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6698   match(Set dst (DecodeN src));
6699   predicate(Universe::narrow_oop_shift() != 0 &&
6700             Universe::narrow_oop_base() == 0);
6701 
6702   format %{ "SLDI    $dst, $src, #3 \t// DecodeN (zerobased)" %}
6703   size(4);
6704   ins_encode %{
6705     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6706     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6707   %}
6708   ins_pipe(pipe_class_default);
6709 %}
6710 
6711 // Optimize DecodeN for disjoint base.
6712 // Shift narrow oop and or it into register that already contains the heap base.
6713 // Base == dst must hold, and is assured by construction in postaloc_expand.
6714 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6715   match(Set dst (DecodeN src));
6716   effect(TEMP base);
6717   predicate(false);
6718 
6719   format %{ "RLDIMI  $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6720   size(4);
6721   ins_encode %{
6722     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6723     __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6724   %}
6725   ins_pipe(pipe_class_default);
6726 %}
6727 
6728 // Optimize DecodeN for disjoint base.
6729 // This node requires only one cycle on the critical path.
6730 // We must postalloc_expand as we can not express use_def effects where
6731 // the used register is L and the def'ed register P.
6732 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6733   match(Set dst (DecodeN src));
6734   effect(TEMP_DEF dst);
6735   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6736              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6737             Universe::narrow_oop_base_disjoint());
6738   ins_cost(DEFAULT_COST);
6739 
6740   format %{ "MOV     $dst, heapbase \t\n"
6741             "RLDIMI  $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6742   postalloc_expand %{
6743     loadBaseNode *n1 = new loadBaseNode();
6744     n1->add_req(NULL);
6745     n1->_opnds[0] = op_dst;
6746 
6747     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6748     n2->add_req(n_region, n_src, n1);
6749     n2->_opnds[0] = op_dst;
6750     n2->_opnds[1] = op_src;
6751     n2->_opnds[2] = op_dst;
6752     n2->_bottom_type = _bottom_type;
6753 
6754     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6755     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6756 
6757     nodes->push(n1);
6758     nodes->push(n2);
6759   %}
6760 %}
6761 
6762 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6763   match(Set dst (DecodeN src));
6764   effect(TEMP_DEF dst, TEMP crx);
6765   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6766              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6767             Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6768   ins_cost(3 * DEFAULT_COST);
6769 
6770   format %{ "DecodeN  $dst, $src \t// decode with disjoint base using isel" %}
6771   postalloc_expand %{
6772     loadBaseNode *n1 = new loadBaseNode();
6773     n1->add_req(NULL);
6774     n1->_opnds[0] = op_dst;
6775 
6776     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
6777     n_compare->add_req(n_region, n_src);
6778     n_compare->_opnds[0] = op_crx;
6779     n_compare->_opnds[1] = op_src;
6780     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6781 
6782     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6783     n2->add_req(n_region, n_src, n1);
6784     n2->_opnds[0] = op_dst;
6785     n2->_opnds[1] = op_src;
6786     n2->_opnds[2] = op_dst;
6787     n2->_bottom_type = _bottom_type;
6788 
6789     cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6790     n_cond_set->add_req(n_region, n_compare, n2);
6791     n_cond_set->_opnds[0] = op_dst;
6792     n_cond_set->_opnds[1] = op_crx;
6793     n_cond_set->_opnds[2] = op_dst;
6794     n_cond_set->_bottom_type = _bottom_type;
6795 
6796     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6797     ra_->set_oop(n_cond_set, true);
6798 
6799     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6800     ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6801     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6802     ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6803 
6804     nodes->push(n1);
6805     nodes->push(n_compare);
6806     nodes->push(n2);
6807     nodes->push(n_cond_set);
6808   %}
6809 %}
6810 
6811 // src != 0, shift != 0, base != 0
6812 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6813   match(Set dst (DecodeN src));
6814   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6815              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6816             Universe::narrow_oop_shift() != 0 &&
6817             Universe::narrow_oop_base() != 0);
6818   ins_cost(2 * DEFAULT_COST);
6819 
6820   format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6821   postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6822 %}
6823 
6824 // Compressed OOPs with narrow_oop_shift == 0.
6825 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6826   match(Set dst (DecodeN src));
6827   predicate(Universe::narrow_oop_shift() == 0);
6828   ins_cost(DEFAULT_COST);
6829 
6830   format %{ "MR      $dst, $src \t// DecodeN (unscaled)" %}
6831   // variable size, 0 or 4.
6832   ins_encode %{
6833     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6834     __ mr_if_needed($dst$$Register, $src$$Register);
6835   %}
6836   ins_pipe(pipe_class_default);
6837 %}
6838 
6839 // Convert compressed oop into int for vectors alignment masking.
6840 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6841   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6842   predicate(Universe::narrow_oop_shift() == 0);
6843   ins_cost(DEFAULT_COST);
6844 
6845   format %{ "MR      $dst, $src \t// (int)DecodeN (unscaled)" %}
6846   // variable size, 0 or 4.
6847   ins_encode %{
6848     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6849     __ mr_if_needed($dst$$Register, $src$$Register);
6850   %}
6851   ins_pipe(pipe_class_default);
6852 %}
6853 
6854 // Convert klass pointer into compressed form.
6855 
6856 // Nodes for postalloc expand.
6857 
6858 // Shift node for expand.
6859 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6860   // The match rule is needed to make it a 'MachTypeNode'!
6861   match(Set dst (EncodePKlass src));
6862   predicate(false);
6863 
6864   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6865   size(4);
6866   ins_encode %{
6867     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6868     __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6869   %}
6870   ins_pipe(pipe_class_default);
6871 %}
6872 
6873 // Add node for expand.
6874 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6875   // The match rule is needed to make it a 'MachTypeNode'!
6876   match(Set dst (EncodePKlass (Binary base src)));
6877   predicate(false);
6878 
6879   format %{ "SUB     $dst, $base, $src \t// encode" %}
6880   size(4);
6881   ins_encode %{
6882     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6883     __ subf($dst$$Register, $base$$Register, $src$$Register);
6884   %}
6885   ins_pipe(pipe_class_default);
6886 %}
6887 
6888 // Disjoint narrow oop base.
6889 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
6890   match(Set dst (EncodePKlass src));
6891   predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6892 
6893   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6894   size(4);
6895   ins_encode %{
6896     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6897     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
6898   %}
6899   ins_pipe(pipe_class_default);
6900 %}
6901 
6902 // shift != 0, base != 0
6903 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6904   match(Set dst (EncodePKlass (Binary base src)));
6905   predicate(false);
6906 
6907   format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6908   postalloc_expand %{
6909     encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
6910     n1->add_req(n_region, n_base, n_src);
6911     n1->_opnds[0] = op_dst;
6912     n1->_opnds[1] = op_base;
6913     n1->_opnds[2] = op_src;
6914     n1->_bottom_type = _bottom_type;
6915 
6916     encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
6917     n2->add_req(n_region, n1);
6918     n2->_opnds[0] = op_dst;
6919     n2->_opnds[1] = op_dst;
6920     n2->_bottom_type = _bottom_type;
6921     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6922     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6923 
6924     nodes->push(n1);
6925     nodes->push(n2);
6926   %}
6927 %}
6928 
6929 // shift != 0, base != 0
6930 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
6931   match(Set dst (EncodePKlass src));
6932   //predicate(Universe::narrow_klass_shift() != 0 &&
6933   //          true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
6934 
6935   //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6936   ins_cost(DEFAULT_COST*2);  // Don't count constant.
6937   expand %{
6938     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
6939     iRegLdst base;
6940     loadConL_Ex(base, baseImm);
6941     encodePKlass_not_null_Ex(dst, base, src);
6942   %}
6943 %}
6944 
6945 // Decode nodes.
6946 
6947 // Shift node for expand.
6948 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
6949   // The match rule is needed to make it a 'MachTypeNode'!
6950   match(Set dst (DecodeNKlass src));
6951   predicate(false);
6952 
6953   format %{ "SLDI    $dst, $src, #3 \t// DecodeNKlass" %}
6954   size(4);
6955   ins_encode %{
6956     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6957     __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6958   %}
6959   ins_pipe(pipe_class_default);
6960 %}
6961 
6962 // Add node for expand.
6963 
6964 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6965   // The match rule is needed to make it a 'MachTypeNode'!
6966   match(Set dst (DecodeNKlass (Binary base src)));
6967   predicate(false);
6968 
6969   format %{ "ADD     $dst, $base, $src \t// DecodeNKlass, add klass base" %}
6970   size(4);
6971   ins_encode %{
6972     // TODO: PPC port $archOpcode(ppc64Opcode_add);
6973     __ add($dst$$Register, $base$$Register, $src$$Register);
6974   %}
6975   ins_pipe(pipe_class_default);
6976 %}
6977 
6978 // src != 0, shift != 0, base != 0
6979 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
6980   match(Set dst (DecodeNKlass (Binary base src)));
6981   //effect(kill src); // We need a register for the immediate result after shifting.
6982   predicate(false);
6983 
6984   format %{ "DecodeNKlass $dst =  $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
6985   postalloc_expand %{
6986     decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
6987     n1->add_req(n_region, n_base, n_src);
6988     n1->_opnds[0] = op_dst;
6989     n1->_opnds[1] = op_base;
6990     n1->_opnds[2] = op_src;
6991     n1->_bottom_type = _bottom_type;
6992 
6993     decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
6994     n2->add_req(n_region, n1);
6995     n2->_opnds[0] = op_dst;
6996     n2->_opnds[1] = op_dst;
6997     n2->_bottom_type = _bottom_type;
6998 
6999     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7000     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7001 
7002     nodes->push(n1);
7003     nodes->push(n2);
7004   %}
7005 %}
7006 
7007 // src != 0, shift != 0, base != 0
7008 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7009   match(Set dst (DecodeNKlass src));
7010   // predicate(Universe::narrow_klass_shift() != 0 &&
7011   //           Universe::narrow_klass_base() != 0);
7012 
7013   //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7014 
7015   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7016   expand %{
7017     // We add first, then we shift. Like this, we can get along with one register less.
7018     // But we have to load the base pre-shifted.
7019     immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7020     iRegLdst base;
7021     loadConL_Ex(base, baseImm);
7022     decodeNKlass_notNull_addBase_Ex(dst, base, src);
7023   %}
7024 %}
7025 
7026 //----------MemBar Instructions-----------------------------------------------
7027 // Memory barrier flavors
7028 
7029 instruct membar_acquire() %{
7030   match(LoadFence);
7031   ins_cost(4*MEMORY_REF_COST);
7032 
7033   format %{ "MEMBAR-acquire" %}
7034   size(4);
7035   ins_encode %{
7036     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7037     __ acquire();
7038   %}
7039   ins_pipe(pipe_class_default);
7040 %}
7041 
7042 instruct unnecessary_membar_acquire() %{
7043   match(MemBarAcquire);
7044   ins_cost(0);
7045 
7046   format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7047   size(0);
7048   ins_encode( /*empty*/ );
7049   ins_pipe(pipe_class_default);
7050 %}
7051 
7052 instruct membar_acquire_lock() %{
7053   match(MemBarAcquireLock);
7054   ins_cost(0);
7055 
7056   format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7057   size(0);
7058   ins_encode( /*empty*/ );
7059   ins_pipe(pipe_class_default);
7060 %}
7061 
7062 instruct membar_release() %{
7063   match(MemBarRelease);
7064   match(StoreFence);
7065   ins_cost(4*MEMORY_REF_COST);
7066 
7067   format %{ "MEMBAR-release" %}
7068   size(4);
7069   ins_encode %{
7070     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7071     __ release();
7072   %}
7073   ins_pipe(pipe_class_default);
7074 %}
7075 
7076 instruct membar_storestore() %{
7077   match(MemBarStoreStore);
7078   ins_cost(4*MEMORY_REF_COST);
7079 
7080   format %{ "MEMBAR-store-store" %}
7081   size(4);
7082   ins_encode %{
7083     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7084     __ membar(Assembler::StoreStore);
7085   %}
7086   ins_pipe(pipe_class_default);
7087 %}
7088 
7089 instruct membar_release_lock() %{
7090   match(MemBarReleaseLock);
7091   ins_cost(0);
7092 
7093   format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7094   size(0);
7095   ins_encode( /*empty*/ );
7096   ins_pipe(pipe_class_default);
7097 %}
7098 
7099 instruct membar_volatile() %{
7100   match(MemBarVolatile);
7101   ins_cost(4*MEMORY_REF_COST);
7102 
7103   format %{ "MEMBAR-volatile" %}
7104   size(4);
7105   ins_encode %{
7106     // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7107     __ fence();
7108   %}
7109   ins_pipe(pipe_class_default);
7110 %}
7111 
7112 // This optimization is wrong on PPC. The following pattern is not supported:
7113 //  MemBarVolatile
7114 //   ^        ^
7115 //   |        |
7116 //  CtrlProj MemProj
7117 //   ^        ^
7118 //   |        |
7119 //   |       Load
7120 //   |
7121 //  MemBarVolatile
7122 //
7123 //  The first MemBarVolatile could get optimized out! According to
7124 //  Vladimir, this pattern can not occur on Oracle platforms.
7125 //  However, it does occur on PPC64 (because of membars in
7126 //  inline_unsafe_load_store).
7127 //
7128 // Add this node again if we found a good solution for inline_unsafe_load_store().
7129 // Don't forget to look at the implementation of post_store_load_barrier again,
7130 // we did other fixes in that method.
7131 //instruct unnecessary_membar_volatile() %{
7132 //  match(MemBarVolatile);
7133 //  predicate(Matcher::post_store_load_barrier(n));
7134 //  ins_cost(0);
7135 //
7136 //  format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7137 //  size(0);
7138 //  ins_encode( /*empty*/ );
7139 //  ins_pipe(pipe_class_default);
7140 //%}
7141 
7142 instruct membar_CPUOrder() %{
7143   match(MemBarCPUOrder);
7144   ins_cost(0);
7145 
7146   format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7147   size(0);
7148   ins_encode( /*empty*/ );
7149   ins_pipe(pipe_class_default);
7150 %}
7151 
7152 //----------Conditional Move---------------------------------------------------
7153 
7154 // Cmove using isel.
7155 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7156   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7157   predicate(VM_Version::has_isel());
7158   ins_cost(DEFAULT_COST);
7159 
7160   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7161   size(4);
7162   ins_encode %{
7163     // This is a Power7 instruction for which no machine description
7164     // exists. Anyways, the scheduler should be off on Power7.
7165     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7166     int cc        = $cmp$$cmpcode;
7167     __ isel($dst$$Register, $crx$$CondRegister,
7168             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7169   %}
7170   ins_pipe(pipe_class_default);
7171 %}
7172 
7173 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7174   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7175   predicate(!VM_Version::has_isel());
7176   ins_cost(DEFAULT_COST+BRANCH_COST);
7177 
7178   ins_variable_size_depending_on_alignment(true);
7179 
7180   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7181   // Worst case is branch + move + stop, no stop without scheduler
7182   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7183   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7184   ins_pipe(pipe_class_default);
7185 %}
7186 
7187 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7188   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7189   ins_cost(DEFAULT_COST+BRANCH_COST);
7190 
7191   ins_variable_size_depending_on_alignment(true);
7192 
7193   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7194   // Worst case is branch + move + stop, no stop without scheduler
7195   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7196   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7197   ins_pipe(pipe_class_default);
7198 %}
7199 
7200 // Cmove using isel.
7201 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7202   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7203   predicate(VM_Version::has_isel());
7204   ins_cost(DEFAULT_COST);
7205 
7206   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7207   size(4);
7208   ins_encode %{
7209     // This is a Power7 instruction for which no machine description
7210     // exists. Anyways, the scheduler should be off on Power7.
7211     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7212     int cc        = $cmp$$cmpcode;
7213     __ isel($dst$$Register, $crx$$CondRegister,
7214             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7215   %}
7216   ins_pipe(pipe_class_default);
7217 %}
7218 
7219 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7220   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7221   predicate(!VM_Version::has_isel());
7222   ins_cost(DEFAULT_COST+BRANCH_COST);
7223 
7224   ins_variable_size_depending_on_alignment(true);
7225 
7226   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7227   // Worst case is branch + move + stop, no stop without scheduler.
7228   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7229   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7230   ins_pipe(pipe_class_default);
7231 %}
7232 
7233 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7234   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7235   ins_cost(DEFAULT_COST+BRANCH_COST);
7236 
7237   ins_variable_size_depending_on_alignment(true);
7238 
7239   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7240   // Worst case is branch + move + stop, no stop without scheduler.
7241   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7242   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7243   ins_pipe(pipe_class_default);
7244 %}
7245 
7246 // Cmove using isel.
7247 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7248   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7249   predicate(VM_Version::has_isel());
7250   ins_cost(DEFAULT_COST);
7251 
7252   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7253   size(4);
7254   ins_encode %{
7255     // This is a Power7 instruction for which no machine description
7256     // exists. Anyways, the scheduler should be off on Power7.
7257     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7258     int cc        = $cmp$$cmpcode;
7259     __ isel($dst$$Register, $crx$$CondRegister,
7260             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7261   %}
7262   ins_pipe(pipe_class_default);
7263 %}
7264 
7265 // Conditional move for RegN. Only cmov(reg, reg).
7266 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7267   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7268   predicate(!VM_Version::has_isel());
7269   ins_cost(DEFAULT_COST+BRANCH_COST);
7270 
7271   ins_variable_size_depending_on_alignment(true);
7272 
7273   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7274   // Worst case is branch + move + stop, no stop without scheduler.
7275   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7276   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7277   ins_pipe(pipe_class_default);
7278 %}
7279 
7280 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7281   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7282   ins_cost(DEFAULT_COST+BRANCH_COST);
7283 
7284   ins_variable_size_depending_on_alignment(true);
7285 
7286   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7287   // Worst case is branch + move + stop, no stop without scheduler.
7288   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7289   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7290   ins_pipe(pipe_class_default);
7291 %}
7292 
7293 // Cmove using isel.
7294 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7295   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7296   predicate(VM_Version::has_isel());
7297   ins_cost(DEFAULT_COST);
7298 
7299   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7300   size(4);
7301   ins_encode %{
7302     // This is a Power7 instruction for which no machine description
7303     // exists. Anyways, the scheduler should be off on Power7.
7304     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7305     int cc        = $cmp$$cmpcode;
7306     __ isel($dst$$Register, $crx$$CondRegister,
7307             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7308   %}
7309   ins_pipe(pipe_class_default);
7310 %}
7311 
7312 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7313   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7314   predicate(!VM_Version::has_isel());
7315   ins_cost(DEFAULT_COST+BRANCH_COST);
7316 
7317   ins_variable_size_depending_on_alignment(true);
7318 
7319   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7320   // Worst case is branch + move + stop, no stop without scheduler.
7321   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7322   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7323   ins_pipe(pipe_class_default);
7324 %}
7325 
7326 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7327   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7328   ins_cost(DEFAULT_COST+BRANCH_COST);
7329 
7330   ins_variable_size_depending_on_alignment(true);
7331 
7332   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7333   // Worst case is branch + move + stop, no stop without scheduler.
7334   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7335   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7336   ins_pipe(pipe_class_default);
7337 %}
7338 
7339 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7340   match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7341   ins_cost(DEFAULT_COST+BRANCH_COST);
7342 
7343   ins_variable_size_depending_on_alignment(true);
7344 
7345   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7346   // Worst case is branch + move + stop, no stop without scheduler.
7347   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7348   ins_encode %{
7349     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7350     Label done;
7351     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7352     // Branch if not (cmp crx).
7353     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7354     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7355     // TODO PPC port __ endgroup_if_needed(_size == 12);
7356     __ bind(done);
7357   %}
7358   ins_pipe(pipe_class_default);
7359 %}
7360 
7361 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7362   match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7363   ins_cost(DEFAULT_COST+BRANCH_COST);
7364 
7365   ins_variable_size_depending_on_alignment(true);
7366 
7367   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7368   // Worst case is branch + move + stop, no stop without scheduler.
7369   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7370   ins_encode %{
7371     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7372     Label done;
7373     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7374     // Branch if not (cmp crx).
7375     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7376     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7377     // TODO PPC port __ endgroup_if_needed(_size == 12);
7378     __ bind(done);
7379   %}
7380   ins_pipe(pipe_class_default);
7381 %}
7382 
7383 //----------Conditional_store--------------------------------------------------
7384 // Conditional-store of the updated heap-top.
7385 // Used during allocation of the shared heap.
7386 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7387 
7388 // As compareAndSwapL, but return flag register instead of boolean value in
7389 // int register.
7390 // Used by sun/misc/AtomicLongCSImpl.java.
7391 // Mem_ptr must be a memory operand, else this node does not get
7392 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7393 // can be rematerialized which leads to errors.
7394 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7395   match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7396   effect(TEMP cr0);
7397   format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7398   ins_encode %{
7399     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7400     __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7401                 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7402                 noreg, NULL, true);
7403   %}
7404   ins_pipe(pipe_class_default);
7405 %}
7406 
7407 // As compareAndSwapP, but return flag register instead of boolean value in
7408 // int register.
7409 // This instruction is matched if UseTLAB is off.
7410 // Mem_ptr must be a memory operand, else this node does not get
7411 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7412 // can be rematerialized which leads to errors.
7413 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7414   match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7415   ins_cost(2*MEMORY_REF_COST);
7416 
7417   format %{ "STDCX_  if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7418   ins_encode %{
7419     // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7420     __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7421   %}
7422   ins_pipe(pipe_class_memory);
7423 %}
7424 
7425 // Implement LoadPLocked. Must be ordered against changes of the memory location
7426 // by storePConditional.
7427 // Don't know whether this is ever used.
7428 instruct loadPLocked(iRegPdst dst, memory mem) %{
7429   match(Set dst (LoadPLocked mem));
7430   ins_cost(2*MEMORY_REF_COST);
7431 
7432   format %{ "LDARX   $dst, $mem \t// loadPLocked\n\t" %}
7433   size(4);
7434   ins_encode %{
7435     // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7436     __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7437   %}
7438   ins_pipe(pipe_class_memory);
7439 %}
7440 
7441 //----------Compare-And-Swap---------------------------------------------------
7442 
7443 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7444 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))"  cannot be
7445 // matched.
7446 
7447 // Strong versions:
7448 
7449 instruct compareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7450   match(Set res (CompareAndSwapB mem_ptr (Binary src1 src2)));
7451   predicate(VM_Version::has_lqarx());
7452   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7453   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7454   ins_encode %{
7455     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7456     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7457     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7458                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7459                 $res$$Register, true);
7460     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7461       __ isync();
7462     } else {
7463       __ sync();
7464     }
7465   %}
7466   ins_pipe(pipe_class_default);
7467 %}
7468 
7469 instruct compareAndSwapB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7470   match(Set res (CompareAndSwapB mem_ptr (Binary src1 src2)));
7471   predicate(!VM_Version::has_lqarx());
7472   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7473   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7474   ins_encode %{
7475     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7476     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7477     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7478                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7479                 $res$$Register, true);
7480     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7481       __ isync();
7482     } else {
7483       __ sync();
7484     }
7485   %}
7486   ins_pipe(pipe_class_default);
7487 %}
7488 
7489 instruct compareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7490   match(Set res (CompareAndSwapS mem_ptr (Binary src1 src2)));
7491   predicate(VM_Version::has_lqarx());
7492   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7493   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7494   ins_encode %{
7495     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7496     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7497     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7498                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7499                 $res$$Register, true);
7500     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7501       __ isync();
7502     } else {
7503       __ sync();
7504     }
7505   %}
7506   ins_pipe(pipe_class_default);
7507 %}
7508 
7509 instruct compareAndSwapS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7510   match(Set res (CompareAndSwapS mem_ptr (Binary src1 src2)));
7511   predicate(!VM_Version::has_lqarx());
7512   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7513   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7514   ins_encode %{
7515     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7516     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7517     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7518                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7519                 $res$$Register, true);
7520     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7521       __ isync();
7522     } else {
7523       __ sync();
7524     }
7525   %}
7526   ins_pipe(pipe_class_default);
7527 %}
7528 
7529 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7530   match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7531   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7532   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7533   ins_encode %{
7534     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7535     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7536     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7537                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7538                 $res$$Register, true);
7539     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7540       __ isync();
7541     } else {
7542       __ sync();
7543     }
7544   %}
7545   ins_pipe(pipe_class_default);
7546 %}
7547 
7548 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7549   match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7550   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7551   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7552   ins_encode %{
7553     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7554     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7555     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7556                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7557                 $res$$Register, true);
7558     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7559       __ isync();
7560     } else {
7561       __ sync();
7562     }
7563   %}
7564   ins_pipe(pipe_class_default);
7565 %}
7566 
7567 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7568   match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7569   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7570   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7571   ins_encode %{
7572     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7573     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7574     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7575                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7576                 $res$$Register, NULL, true);
7577     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7578       __ isync();
7579     } else {
7580       __ sync();
7581     }
7582   %}
7583   ins_pipe(pipe_class_default);
7584 %}
7585 
7586 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7587   match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7588   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7589   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7590   ins_encode %{
7591     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7592     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7593     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7594                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7595                 $res$$Register, NULL, true);
7596     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7597       __ isync();
7598     } else {
7599       __ sync();
7600     }
7601   %}
7602   ins_pipe(pipe_class_default);
7603 %}
7604 
7605 // Weak versions:
7606 
7607 instruct weakCompareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7608   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7609   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7610   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7611   format %{ "weak CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7612   ins_encode %{
7613     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7614     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7615     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7616                 MacroAssembler::MemBarNone,
7617                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7618   %}
7619   ins_pipe(pipe_class_default);
7620 %}
7621 
7622 instruct weakCompareAndSwapB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7623   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7624   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7625   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7626   format %{ "weak CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7627   ins_encode %{
7628     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7629     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7630     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7631                 MacroAssembler::MemBarNone,
7632                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7633   %}
7634   ins_pipe(pipe_class_default);
7635 %}
7636 
7637 instruct weakCompareAndSwapB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7638   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7639   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7640   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7641   format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
7642   ins_encode %{
7643     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7644     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7645     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7646                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7647                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7648   %}
7649   ins_pipe(pipe_class_default);
7650 %}
7651 
7652 instruct weakCompareAndSwapB4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7653   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7654   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7655   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7656   format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
7657   ins_encode %{
7658     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7659     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7660     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7661                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7662                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7663   %}
7664   ins_pipe(pipe_class_default);
7665 %}
7666 
7667 instruct weakCompareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7668   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7669   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7670   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7671   format %{ "weak CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7672   ins_encode %{
7673     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7674     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7675     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7676                 MacroAssembler::MemBarNone,
7677                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7678   %}
7679   ins_pipe(pipe_class_default);
7680 %}
7681 
7682 instruct weakCompareAndSwapS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7683   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7684   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7685   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7686   format %{ "weak CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7687   ins_encode %{
7688     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7689     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7690     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7691                 MacroAssembler::MemBarNone,
7692                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7693   %}
7694   ins_pipe(pipe_class_default);
7695 %}
7696 
7697 instruct weakCompareAndSwapS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7698   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7699   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7700   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7701   format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
7702   ins_encode %{
7703     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7704     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7705     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7706                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7707                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7708   %}
7709   ins_pipe(pipe_class_default);
7710 %}
7711 
7712 instruct weakCompareAndSwapS4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7713   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7714   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7715   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7716   format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
7717   ins_encode %{
7718     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7719     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7720     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7721                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7722                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7723   %}
7724   ins_pipe(pipe_class_default);
7725 %}
7726 
7727 instruct weakCompareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7728   match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
7729   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7730   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7731   format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7732   ins_encode %{
7733     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7734     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7735     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7736                 MacroAssembler::MemBarNone,
7737                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7738   %}
7739   ins_pipe(pipe_class_default);
7740 %}
7741 
7742 instruct weakCompareAndSwapI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7743   match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
7744   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7745   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7746   format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
7747   ins_encode %{
7748     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7749     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7750     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7751     // value is never passed to caller.
7752     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7753                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7754                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7755   %}
7756   ins_pipe(pipe_class_default);
7757 %}
7758 
7759 instruct weakCompareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7760   match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
7761   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7762   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7763   format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7764   ins_encode %{
7765     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7766     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7767     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7768                 MacroAssembler::MemBarNone,
7769                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7770   %}
7771   ins_pipe(pipe_class_default);
7772 %}
7773 
7774 instruct weakCompareAndSwapN_acq_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7775   match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
7776   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7777   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7778   format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
7779   ins_encode %{
7780     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7781     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7782     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7783     // value is never passed to caller.
7784     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7785                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7786                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7787   %}
7788   ins_pipe(pipe_class_default);
7789 %}
7790 
7791 instruct weakCompareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7792   match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
7793   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7794   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7795   format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7796   ins_encode %{
7797     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7798     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7799     // value is never passed to caller.
7800     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7801                 MacroAssembler::MemBarNone,
7802                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7803   %}
7804   ins_pipe(pipe_class_default);
7805 %}
7806 
7807 instruct weakCompareAndSwapL_acq_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7808   match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
7809   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7810   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7811   format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool" %}
7812   ins_encode %{
7813     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7814     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7815     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7816     // value is never passed to caller.
7817     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7818                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7819                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7820   %}
7821   ins_pipe(pipe_class_default);
7822 %}
7823 
7824 instruct weakCompareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7825   match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
7826   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7827   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7828   format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7829   ins_encode %{
7830     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7831     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7832     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7833                 MacroAssembler::MemBarNone,
7834                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7835   %}
7836   ins_pipe(pipe_class_default);
7837 %}
7838 
7839 instruct weakCompareAndSwapP_acq_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7840   match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
7841   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7842   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7843   format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7844   ins_encode %{
7845     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7846     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7847     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7848     // value is never passed to caller.
7849     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7850                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7851                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7852   %}
7853   ins_pipe(pipe_class_default);
7854 %}
7855 
7856 // CompareAndExchange
7857 
7858 instruct compareAndExchangeB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7859   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7860   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7861   effect(TEMP_DEF res, TEMP cr0);
7862   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as int" %}
7863   ins_encode %{
7864     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7865     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7866     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7867                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7868                 noreg, true);
7869   %}
7870   ins_pipe(pipe_class_default);
7871 %}
7872 
7873 instruct compareAndExchangeB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7874   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7875   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7876   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7877   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as int" %}
7878   ins_encode %{
7879     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7880     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7881     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
7882                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7883                 noreg, true);
7884   %}
7885   ins_pipe(pipe_class_default);
7886 %}
7887 
7888 instruct compareAndExchangeB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7889   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7890   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7891   effect(TEMP_DEF res, TEMP cr0);
7892   format %{ "CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as int" %}
7893   ins_encode %{
7894     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7895     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7896     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7897                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7898                 noreg, true);
7899     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7900       __ isync();
7901     } else {
7902       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7903       __ sync();
7904     }
7905   %}
7906   ins_pipe(pipe_class_default);
7907 %}
7908 
7909 instruct compareAndExchangeB4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7910   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7911   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7912   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7913   format %{ "CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as int" %}
7914   ins_encode %{
7915     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7916     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7917     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
7918                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7919                 noreg, true);
7920     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7921       __ isync();
7922     } else {
7923       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7924       __ sync();
7925     }
7926   %}
7927   ins_pipe(pipe_class_default);
7928 %}
7929 
7930 instruct compareAndExchangeS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7931   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7932   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7933   effect(TEMP_DEF res, TEMP cr0);
7934   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as int" %}
7935   ins_encode %{
7936     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7937     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7938     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7939                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7940                 noreg, true);
7941   %}
7942   ins_pipe(pipe_class_default);
7943 %}
7944 
7945 instruct compareAndExchangeS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7946   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7947   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7948   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7949   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as int" %}
7950   ins_encode %{
7951     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7952     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7953     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
7954                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7955                 noreg, true);
7956   %}
7957   ins_pipe(pipe_class_default);
7958 %}
7959 
7960 instruct compareAndExchangeS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7961   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7962   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7963   effect(TEMP_DEF res, TEMP cr0);
7964   format %{ "CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as int" %}
7965   ins_encode %{
7966     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7967     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7968     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7969                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7970                 noreg, true);
7971     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7972       __ isync();
7973     } else {
7974       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7975       __ sync();
7976     }
7977   %}
7978   ins_pipe(pipe_class_default);
7979 %}
7980 
7981 instruct compareAndExchangeS4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7982   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7983   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7984   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7985   format %{ "CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as int" %}
7986   ins_encode %{
7987     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7988     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7989     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
7990                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7991                 noreg, true);
7992     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7993       __ isync();
7994     } else {
7995       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7996       __ sync();
7997     }
7998   %}
7999   ins_pipe(pipe_class_default);
8000 %}
8001 
8002 instruct compareAndExchangeI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8003   match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
8004   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8005   effect(TEMP_DEF res, TEMP cr0);
8006   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as int" %}
8007   ins_encode %{
8008     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8009     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8010     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8011                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8012                 noreg, true);
8013   %}
8014   ins_pipe(pipe_class_default);
8015 %}
8016 
8017 instruct compareAndExchangeI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8018   match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
8019   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8020   effect(TEMP_DEF res, TEMP cr0);
8021   format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as int" %}
8022   ins_encode %{
8023     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8024     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8025     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8026                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8027                 noreg, true);
8028     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8029       __ isync();
8030     } else {
8031       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8032       __ sync();
8033     }
8034   %}
8035   ins_pipe(pipe_class_default);
8036 %}
8037 
8038 instruct compareAndExchangeN_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8039   match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
8040   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8041   effect(TEMP_DEF res, TEMP cr0);
8042   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as narrow oop" %}
8043   ins_encode %{
8044     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8045     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8046     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8047                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8048                 noreg, true);
8049   %}
8050   ins_pipe(pipe_class_default);
8051 %}
8052 
8053 instruct compareAndExchangeN_acq_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8054   match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
8055   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8056   effect(TEMP_DEF res, TEMP cr0);
8057   format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as narrow oop" %}
8058   ins_encode %{
8059     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8060     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8061     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8062                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8063                 noreg, true);
8064     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8065       __ isync();
8066     } else {
8067       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8068       __ sync();
8069     }
8070   %}
8071   ins_pipe(pipe_class_default);
8072 %}
8073 
8074 instruct compareAndExchangeL_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8075   match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
8076   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8077   effect(TEMP_DEF res, TEMP cr0);
8078   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as long" %}
8079   ins_encode %{
8080     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8081     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8082     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8083                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8084                 noreg, NULL, true);
8085   %}
8086   ins_pipe(pipe_class_default);
8087 %}
8088 
8089 instruct compareAndExchangeL_acq_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8090   match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
8091   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8092   effect(TEMP_DEF res, TEMP cr0);
8093   format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as long" %}
8094   ins_encode %{
8095     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8096     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8097     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8098                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8099                 noreg, NULL, true);
8100     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8101       __ isync();
8102     } else {
8103       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8104       __ sync();
8105     }
8106   %}
8107   ins_pipe(pipe_class_default);
8108 %}
8109 
8110 instruct compareAndExchangeP_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8111   match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
8112   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8113   effect(TEMP_DEF res, TEMP cr0);
8114   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
8115   ins_encode %{
8116     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8117     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8118     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8119                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8120                 noreg, NULL, true);
8121   %}
8122   ins_pipe(pipe_class_default);
8123 %}
8124 
8125 instruct compareAndExchangeP_acq_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8126   match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
8127   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8128   effect(TEMP_DEF res, TEMP cr0);
8129   format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
8130   ins_encode %{
8131     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8132     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8133     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8134                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8135                 noreg, NULL, true);
8136     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8137       __ isync();
8138     } else {
8139       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8140       __ sync();
8141     }
8142   %}
8143   ins_pipe(pipe_class_default);
8144 %}
8145 
8146 // Special RMW
8147 
8148 instruct getAndAddB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8149   match(Set res (GetAndAddB mem_ptr src));
8150   predicate(VM_Version::has_lqarx());
8151   effect(TEMP_DEF res, TEMP cr0);
8152   format %{ "GetAndAddB $res, $mem_ptr, $src" %}
8153   ins_encode %{
8154     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
8155                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8156     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8157       __ isync();
8158     } else {
8159       __ sync();
8160     }
8161   %}
8162   ins_pipe(pipe_class_default);
8163 %}
8164 
8165 instruct getAndAddB4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8166   match(Set res (GetAndAddB mem_ptr src));
8167   predicate(!VM_Version::has_lqarx());
8168   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8169   format %{ "GetAndAddB $res, $mem_ptr, $src" %}
8170   ins_encode %{
8171     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
8172                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8173     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8174       __ isync();
8175     } else {
8176       __ sync();
8177     }
8178   %}
8179   ins_pipe(pipe_class_default);
8180 %}
8181 
8182 instruct getAndAddS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8183   match(Set res (GetAndAddS mem_ptr src));
8184   predicate(VM_Version::has_lqarx());
8185   effect(TEMP_DEF res, TEMP cr0);
8186   format %{ "GetAndAddS $res, $mem_ptr, $src" %}
8187   ins_encode %{
8188     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
8189                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8190     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8191       __ isync();
8192     } else {
8193       __ sync();
8194     }
8195   %}
8196   ins_pipe(pipe_class_default);
8197 %}
8198 
8199 instruct getAndAddS4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8200   match(Set res (GetAndAddS mem_ptr src));
8201   predicate(!VM_Version::has_lqarx());
8202   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8203   format %{ "GetAndAddS $res, $mem_ptr, $src" %}
8204   ins_encode %{
8205     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
8206                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8207     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8208       __ isync();
8209     } else {
8210       __ sync();
8211     }
8212   %}
8213   ins_pipe(pipe_class_default);
8214 %}
8215 
8216 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8217   match(Set res (GetAndAddI mem_ptr src));
8218   effect(TEMP_DEF res, TEMP cr0);
8219   format %{ "GetAndAddI $res, $mem_ptr, $src" %}
8220   ins_encode %{
8221     __ getandaddw($res$$Register, $src$$Register, $mem_ptr$$Register,
8222                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
8223     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8224       __ isync();
8225     } else {
8226       __ sync();
8227     }
8228   %}
8229   ins_pipe(pipe_class_default);
8230 %}
8231 
8232 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
8233   match(Set res (GetAndAddL mem_ptr src));
8234   effect(TEMP_DEF res, TEMP cr0);
8235   format %{ "GetAndAddL $res, $mem_ptr, $src" %}
8236   ins_encode %{
8237     __ getandaddd($res$$Register, $src$$Register, $mem_ptr$$Register,
8238                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
8239     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8240       __ isync();
8241     } else {
8242       __ sync();
8243     }
8244   %}
8245   ins_pipe(pipe_class_default);
8246 %}
8247 
8248 instruct getAndSetB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8249   match(Set res (GetAndSetB mem_ptr src));
8250   predicate(VM_Version::has_lqarx());
8251   effect(TEMP_DEF res, TEMP cr0);
8252   format %{ "GetAndSetB $res, $mem_ptr, $src" %}
8253   ins_encode %{
8254     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
8255                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8256     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8257       __ isync();
8258     } else {
8259       __ sync();
8260     }
8261   %}
8262   ins_pipe(pipe_class_default);
8263 %}
8264 
8265 instruct getAndSetB4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8266   match(Set res (GetAndSetB mem_ptr src));
8267   predicate(!VM_Version::has_lqarx());
8268   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8269   format %{ "GetAndSetB $res, $mem_ptr, $src" %}
8270   ins_encode %{
8271     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
8272                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8273     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8274       __ isync();
8275     } else {
8276       __ sync();
8277     }
8278   %}
8279   ins_pipe(pipe_class_default);
8280 %}
8281 
8282 instruct getAndSetS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8283   match(Set res (GetAndSetS mem_ptr src));
8284   predicate(VM_Version::has_lqarx());
8285   effect(TEMP_DEF res, TEMP cr0);
8286   format %{ "GetAndSetS $res, $mem_ptr, $src" %}
8287   ins_encode %{
8288     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
8289                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8290     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8291       __ isync();
8292     } else {
8293       __ sync();
8294     }
8295   %}
8296   ins_pipe(pipe_class_default);
8297 %}
8298 
8299 instruct getAndSetS4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8300   match(Set res (GetAndSetS mem_ptr src));
8301   predicate(!VM_Version::has_lqarx());
8302   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8303   format %{ "GetAndSetS $res, $mem_ptr, $src" %}
8304   ins_encode %{
8305     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
8306                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8307     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8308       __ isync();
8309     } else {
8310       __ sync();
8311     }
8312   %}
8313   ins_pipe(pipe_class_default);
8314 %}
8315 
8316 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8317   match(Set res (GetAndSetI mem_ptr src));
8318   effect(TEMP_DEF res, TEMP cr0);
8319   format %{ "GetAndSetI $res, $mem_ptr, $src" %}
8320   ins_encode %{
8321     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
8322                   MacroAssembler::cmpxchgx_hint_atomic_update());
8323     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8324       __ isync();
8325     } else {
8326       __ sync();
8327     }
8328   %}
8329   ins_pipe(pipe_class_default);
8330 %}
8331 
8332 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
8333   match(Set res (GetAndSetL mem_ptr src));
8334   effect(TEMP_DEF res, TEMP cr0);
8335   format %{ "GetAndSetL $res, $mem_ptr, $src" %}
8336   ins_encode %{
8337     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
8338                   MacroAssembler::cmpxchgx_hint_atomic_update());
8339     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8340       __ isync();
8341     } else {
8342       __ sync();
8343     }
8344   %}
8345   ins_pipe(pipe_class_default);
8346 %}
8347 
8348 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
8349   match(Set res (GetAndSetP mem_ptr src));
8350   effect(TEMP_DEF res, TEMP cr0);
8351   format %{ "GetAndSetP $res, $mem_ptr, $src" %}
8352   ins_encode %{
8353     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
8354                   MacroAssembler::cmpxchgx_hint_atomic_update());
8355     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8356       __ isync();
8357     } else {
8358       __ sync();
8359     }
8360   %}
8361   ins_pipe(pipe_class_default);
8362 %}
8363 
8364 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
8365   match(Set res (GetAndSetN mem_ptr src));
8366   effect(TEMP_DEF res, TEMP cr0);
8367   format %{ "GetAndSetN $res, $mem_ptr, $src" %}
8368   ins_encode %{
8369     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
8370                   MacroAssembler::cmpxchgx_hint_atomic_update());
8371     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8372       __ isync();
8373     } else {
8374       __ sync();
8375     }
8376   %}
8377   ins_pipe(pipe_class_default);
8378 %}
8379 
8380 //----------Arithmetic Instructions--------------------------------------------
8381 // Addition Instructions
8382 
8383 // Register Addition
8384 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
8385   match(Set dst (AddI src1 src2));
8386   format %{ "ADD     $dst, $src1, $src2" %}
8387   size(4);
8388   ins_encode %{
8389     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8390     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8391   %}
8392   ins_pipe(pipe_class_default);
8393 %}
8394 
8395 // Expand does not work with above instruct. (??)
8396 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8397   // no match-rule
8398   effect(DEF dst, USE src1, USE src2);
8399   format %{ "ADD     $dst, $src1, $src2" %}
8400   size(4);
8401   ins_encode %{
8402     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8403     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8404   %}
8405   ins_pipe(pipe_class_default);
8406 %}
8407 
8408 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8409   match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
8410   ins_cost(DEFAULT_COST*3);
8411 
8412   expand %{
8413     // FIXME: we should do this in the ideal world.
8414     iRegIdst tmp1;
8415     iRegIdst tmp2;
8416     addI_reg_reg(tmp1, src1, src2);
8417     addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
8418     addI_reg_reg(dst, tmp1, tmp2);
8419   %}
8420 %}
8421 
8422 // Immediate Addition
8423 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8424   match(Set dst (AddI src1 src2));
8425   format %{ "ADDI    $dst, $src1, $src2" %}
8426   size(4);
8427   ins_encode %{
8428     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8429     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8430   %}
8431   ins_pipe(pipe_class_default);
8432 %}
8433 
8434 // Immediate Addition with 16-bit shifted operand
8435 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
8436   match(Set dst (AddI src1 src2));
8437   format %{ "ADDIS   $dst, $src1, $src2" %}
8438   size(4);
8439   ins_encode %{
8440     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8441     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8442   %}
8443   ins_pipe(pipe_class_default);
8444 %}
8445 
8446 // Long Addition
8447 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8448   match(Set dst (AddL src1 src2));
8449   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
8450   size(4);
8451   ins_encode %{
8452     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8453     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8454   %}
8455   ins_pipe(pipe_class_default);
8456 %}
8457 
8458 // Expand does not work with above instruct. (??)
8459 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8460   // no match-rule
8461   effect(DEF dst, USE src1, USE src2);
8462   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
8463   size(4);
8464   ins_encode %{
8465     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8466     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8467   %}
8468   ins_pipe(pipe_class_default);
8469 %}
8470 
8471 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
8472   match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
8473   ins_cost(DEFAULT_COST*3);
8474 
8475   expand %{
8476     // FIXME: we should do this in the ideal world.
8477     iRegLdst tmp1;
8478     iRegLdst tmp2;
8479     addL_reg_reg(tmp1, src1, src2);
8480     addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8481     addL_reg_reg(dst, tmp1, tmp2);
8482   %}
8483 %}
8484 
8485 // AddL + ConvL2I.
8486 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8487   match(Set dst (ConvL2I (AddL src1 src2)));
8488 
8489   format %{ "ADD     $dst, $src1, $src2 \t// long + l2i" %}
8490   size(4);
8491   ins_encode %{
8492     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8493     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8494   %}
8495   ins_pipe(pipe_class_default);
8496 %}
8497 
8498 // No constant pool entries required.
8499 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8500   match(Set dst (AddL src1 src2));
8501 
8502   format %{ "ADDI    $dst, $src1, $src2" %}
8503   size(4);
8504   ins_encode %{
8505     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8506     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8507   %}
8508   ins_pipe(pipe_class_default);
8509 %}
8510 
8511 // Long Immediate Addition with 16-bit shifted operand.
8512 // No constant pool entries required.
8513 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
8514   match(Set dst (AddL src1 src2));
8515 
8516   format %{ "ADDIS   $dst, $src1, $src2" %}
8517   size(4);
8518   ins_encode %{
8519     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8520     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8521   %}
8522   ins_pipe(pipe_class_default);
8523 %}
8524 
8525 // Pointer Register Addition
8526 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
8527   match(Set dst (AddP src1 src2));
8528   format %{ "ADD     $dst, $src1, $src2" %}
8529   size(4);
8530   ins_encode %{
8531     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8532     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8533   %}
8534   ins_pipe(pipe_class_default);
8535 %}
8536 
8537 // Pointer Immediate Addition
8538 // No constant pool entries required.
8539 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
8540   match(Set dst (AddP src1 src2));
8541 
8542   format %{ "ADDI    $dst, $src1, $src2" %}
8543   size(4);
8544   ins_encode %{
8545     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8546     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8547   %}
8548   ins_pipe(pipe_class_default);
8549 %}
8550 
8551 // Pointer Immediate Addition with 16-bit shifted operand.
8552 // No constant pool entries required.
8553 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
8554   match(Set dst (AddP src1 src2));
8555 
8556   format %{ "ADDIS   $dst, $src1, $src2" %}
8557   size(4);
8558   ins_encode %{
8559     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8560     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8561   %}
8562   ins_pipe(pipe_class_default);
8563 %}
8564 
8565 //---------------------
8566 // Subtraction Instructions
8567 
8568 // Register Subtraction
8569 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8570   match(Set dst (SubI src1 src2));
8571   format %{ "SUBF    $dst, $src2, $src1" %}
8572   size(4);
8573   ins_encode %{
8574     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
8575     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
8576   %}
8577   ins_pipe(pipe_class_default);
8578 %}
8579 
8580 // Immediate Subtraction
8581 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
8582 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
8583 
8584 // SubI from constant (using subfic).
8585 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
8586   match(Set dst (SubI src1 src2));
8587   format %{ "SUBI    $dst, $src1, $src2" %}
8588 
8589   size(4);
8590   ins_encode %{
8591     // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
8592     __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
8593   %}
8594   ins_pipe(pipe_class_default);
8595 %}
8596 
8597 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
8598 // positive integers and 0xF...F for negative ones.
8599 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
8600   // no match-rule, false predicate
8601   effect(DEF dst, USE src);
8602   predicate(false);
8603 
8604   format %{ "SRAWI   $dst, $src, #31" %}
8605   size(4);
8606   ins_encode %{
8607     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8608     __ srawi($dst$$Register, $src$$Register, 0x1f);
8609   %}
8610   ins_pipe(pipe_class_default);
8611 %}
8612 
8613 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
8614   match(Set dst (AbsI src));
8615   ins_cost(DEFAULT_COST*3);
8616 
8617   expand %{
8618     iRegIdst tmp1;
8619     iRegIdst tmp2;
8620     signmask32I_regI(tmp1, src);
8621     xorI_reg_reg(tmp2, tmp1, src);
8622     subI_reg_reg(dst, tmp2, tmp1);
8623   %}
8624 %}
8625 
8626 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
8627   match(Set dst (SubI zero src2));
8628   format %{ "NEG     $dst, $src2" %}
8629   size(4);
8630   ins_encode %{
8631     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8632     __ neg($dst$$Register, $src2$$Register);
8633   %}
8634   ins_pipe(pipe_class_default);
8635 %}
8636 
8637 // Long subtraction
8638 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8639   match(Set dst (SubL src1 src2));
8640   format %{ "SUBF    $dst, $src2, $src1 \t// long" %}
8641   size(4);
8642   ins_encode %{
8643     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
8644     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
8645   %}
8646   ins_pipe(pipe_class_default);
8647 %}
8648 
8649 // SubL + convL2I.
8650 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8651   match(Set dst (ConvL2I (SubL src1 src2)));
8652 
8653   format %{ "SUBF    $dst, $src2, $src1 \t// long + l2i" %}
8654   size(4);
8655   ins_encode %{
8656     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
8657     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
8658   %}
8659   ins_pipe(pipe_class_default);
8660 %}
8661 
8662 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8663 // positive longs and 0xF...F for negative ones.
8664 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
8665   // no match-rule, false predicate
8666   effect(DEF dst, USE src);
8667   predicate(false);
8668 
8669   format %{ "SRADI   $dst, $src, #63" %}
8670   size(4);
8671   ins_encode %{
8672     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8673     __ sradi($dst$$Register, $src$$Register, 0x3f);
8674   %}
8675   ins_pipe(pipe_class_default);
8676 %}
8677 
8678 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8679 // positive longs and 0xF...F for negative ones.
8680 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8681   // no match-rule, false predicate
8682   effect(DEF dst, USE src);
8683   predicate(false);
8684 
8685   format %{ "SRADI   $dst, $src, #63" %}
8686   size(4);
8687   ins_encode %{
8688     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8689     __ sradi($dst$$Register, $src$$Register, 0x3f);
8690   %}
8691   ins_pipe(pipe_class_default);
8692 %}
8693 
8694 // Long negation
8695 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8696   match(Set dst (SubL zero src2));
8697   format %{ "NEG     $dst, $src2 \t// long" %}
8698   size(4);
8699   ins_encode %{
8700     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8701     __ neg($dst$$Register, $src2$$Register);
8702   %}
8703   ins_pipe(pipe_class_default);
8704 %}
8705 
8706 // NegL + ConvL2I.
8707 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8708   match(Set dst (ConvL2I (SubL zero src2)));
8709 
8710   format %{ "NEG     $dst, $src2 \t// long + l2i" %}
8711   size(4);
8712   ins_encode %{
8713     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8714     __ neg($dst$$Register, $src2$$Register);
8715   %}
8716   ins_pipe(pipe_class_default);
8717 %}
8718 
8719 // Multiplication Instructions
8720 // Integer Multiplication
8721 
8722 // Register Multiplication
8723 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8724   match(Set dst (MulI src1 src2));
8725   ins_cost(DEFAULT_COST);
8726 
8727   format %{ "MULLW   $dst, $src1, $src2" %}
8728   size(4);
8729   ins_encode %{
8730     // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8731     __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8732   %}
8733   ins_pipe(pipe_class_default);
8734 %}
8735 
8736 // Immediate Multiplication
8737 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8738   match(Set dst (MulI src1 src2));
8739   ins_cost(DEFAULT_COST);
8740 
8741   format %{ "MULLI   $dst, $src1, $src2" %}
8742   size(4);
8743   ins_encode %{
8744     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8745     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8746   %}
8747   ins_pipe(pipe_class_default);
8748 %}
8749 
8750 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8751   match(Set dst (MulL src1 src2));
8752   ins_cost(DEFAULT_COST);
8753 
8754   format %{ "MULLD   $dst $src1, $src2 \t// long" %}
8755   size(4);
8756   ins_encode %{
8757     // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8758     __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8759   %}
8760   ins_pipe(pipe_class_default);
8761 %}
8762 
8763 // Multiply high for optimized long division by constant.
8764 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8765   match(Set dst (MulHiL src1 src2));
8766   ins_cost(DEFAULT_COST);
8767 
8768   format %{ "MULHD   $dst $src1, $src2 \t// long" %}
8769   size(4);
8770   ins_encode %{
8771     // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8772     __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8773   %}
8774   ins_pipe(pipe_class_default);
8775 %}
8776 
8777 // Immediate Multiplication
8778 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8779   match(Set dst (MulL src1 src2));
8780   ins_cost(DEFAULT_COST);
8781 
8782   format %{ "MULLI   $dst, $src1, $src2" %}
8783   size(4);
8784   ins_encode %{
8785     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8786     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8787   %}
8788   ins_pipe(pipe_class_default);
8789 %}
8790 
8791 // Integer Division with Immediate -1: Negate.
8792 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8793   match(Set dst (DivI src1 src2));
8794   ins_cost(DEFAULT_COST);
8795 
8796   format %{ "NEG     $dst, $src1 \t// /-1" %}
8797   size(4);
8798   ins_encode %{
8799     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8800     __ neg($dst$$Register, $src1$$Register);
8801   %}
8802   ins_pipe(pipe_class_default);
8803 %}
8804 
8805 // Integer Division with constant, but not -1.
8806 // We should be able to improve this by checking the type of src2.
8807 // It might well be that src2 is known to be positive.
8808 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8809   match(Set dst (DivI src1 src2));
8810   predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8811   ins_cost(2*DEFAULT_COST);
8812 
8813   format %{ "DIVW    $dst, $src1, $src2 \t// /not-1" %}
8814   size(4);
8815   ins_encode %{
8816     // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8817     __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8818   %}
8819   ins_pipe(pipe_class_default);
8820 %}
8821 
8822 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8823   effect(USE_DEF dst, USE src1, USE crx);
8824   predicate(false);
8825 
8826   ins_variable_size_depending_on_alignment(true);
8827 
8828   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8829   // Worst case is branch + move + stop, no stop without scheduler.
8830   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8831   ins_encode %{
8832     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8833     Label done;
8834     __ bne($crx$$CondRegister, done);
8835     __ neg($dst$$Register, $src1$$Register);
8836     // TODO PPC port __ endgroup_if_needed(_size == 12);
8837     __ bind(done);
8838   %}
8839   ins_pipe(pipe_class_default);
8840 %}
8841 
8842 // Integer Division with Registers not containing constants.
8843 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8844   match(Set dst (DivI src1 src2));
8845   ins_cost(10*DEFAULT_COST);
8846 
8847   expand %{
8848     immI16 imm %{ (int)-1 %}
8849     flagsReg tmp1;
8850     cmpI_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8851     divI_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8852     cmovI_bne_negI_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8853   %}
8854 %}
8855 
8856 // Long Division with Immediate -1: Negate.
8857 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8858   match(Set dst (DivL src1 src2));
8859   ins_cost(DEFAULT_COST);
8860 
8861   format %{ "NEG     $dst, $src1 \t// /-1, long" %}
8862   size(4);
8863   ins_encode %{
8864     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8865     __ neg($dst$$Register, $src1$$Register);
8866   %}
8867   ins_pipe(pipe_class_default);
8868 %}
8869 
8870 // Long Division with constant, but not -1.
8871 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8872   match(Set dst (DivL src1 src2));
8873   predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8874   ins_cost(2*DEFAULT_COST);
8875 
8876   format %{ "DIVD    $dst, $src1, $src2 \t// /not-1, long" %}
8877   size(4);
8878   ins_encode %{
8879     // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8880     __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8881   %}
8882   ins_pipe(pipe_class_default);
8883 %}
8884 
8885 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8886   effect(USE_DEF dst, USE src1, USE crx);
8887   predicate(false);
8888 
8889   ins_variable_size_depending_on_alignment(true);
8890 
8891   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8892   // Worst case is branch + move + stop, no stop without scheduler.
8893   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8894   ins_encode %{
8895     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8896     Label done;
8897     __ bne($crx$$CondRegister, done);
8898     __ neg($dst$$Register, $src1$$Register);
8899     // TODO PPC port __ endgroup_if_needed(_size == 12);
8900     __ bind(done);
8901   %}
8902   ins_pipe(pipe_class_default);
8903 %}
8904 
8905 // Long Division with Registers not containing constants.
8906 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8907   match(Set dst (DivL src1 src2));
8908   ins_cost(10*DEFAULT_COST);
8909 
8910   expand %{
8911     immL16 imm %{ (int)-1 %}
8912     flagsReg tmp1;
8913     cmpL_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8914     divL_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8915     cmovL_bne_negL_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8916   %}
8917 %}
8918 
8919 // Integer Remainder with registers.
8920 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8921   match(Set dst (ModI src1 src2));
8922   ins_cost(10*DEFAULT_COST);
8923 
8924   expand %{
8925     immI16 imm %{ (int)-1 %}
8926     flagsReg tmp1;
8927     iRegIdst tmp2;
8928     iRegIdst tmp3;
8929     cmpI_reg_imm16(tmp1, src2, imm);           // check src2 == -1
8930     divI_reg_regnotMinus1(tmp2, src1, src2);   // tmp2 = src1 / src2
8931     cmovI_bne_negI_reg(tmp2, tmp1, src1);      // cmove tmp2 = neg(src1) if src2 == -1
8932     mulI_reg_reg(tmp3, src2, tmp2);            // tmp3 = src2 * tmp2
8933     subI_reg_reg(dst, src1, tmp3);             // dst = src1 - tmp3
8934   %}
8935 %}
8936 
8937 // Long Remainder with registers
8938 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8939   match(Set dst (ModL src1 src2));
8940   ins_cost(10*DEFAULT_COST);
8941 
8942   expand %{
8943     immL16 imm %{ (int)-1 %}
8944     flagsReg tmp1;
8945     iRegLdst tmp2;
8946     iRegLdst tmp3;
8947     cmpL_reg_imm16(tmp1, src2, imm);             // check src2 == -1
8948     divL_reg_regnotMinus1(tmp2, src1, src2);     // tmp2 = src1 / src2
8949     cmovL_bne_negL_reg(tmp2, tmp1, src1);        // cmove tmp2 = neg(src1) if src2 == -1
8950     mulL_reg_reg(tmp3, src2, tmp2);              // tmp3 = src2 * tmp2
8951     subL_reg_reg(dst, src1, tmp3);               // dst = src1 - tmp3
8952   %}
8953 %}
8954 
8955 // Integer Shift Instructions
8956 
8957 // Register Shift Left
8958 
8959 // Clear all but the lowest #mask bits.
8960 // Used to normalize shift amounts in registers.
8961 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8962   // no match-rule, false predicate
8963   effect(DEF dst, USE src, USE mask);
8964   predicate(false);
8965 
8966   format %{ "MASK    $dst, $src, $mask \t// clear $mask upper bits" %}
8967   size(4);
8968   ins_encode %{
8969     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8970     __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8971   %}
8972   ins_pipe(pipe_class_default);
8973 %}
8974 
8975 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8976   // no match-rule, false predicate
8977   effect(DEF dst, USE src1, USE src2);
8978   predicate(false);
8979 
8980   format %{ "SLW     $dst, $src1, $src2" %}
8981   size(4);
8982   ins_encode %{
8983     // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8984     __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8985   %}
8986   ins_pipe(pipe_class_default);
8987 %}
8988 
8989 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8990   match(Set dst (LShiftI src1 src2));
8991   ins_cost(DEFAULT_COST*2);
8992   expand %{
8993     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8994     iRegIdst tmpI;
8995     maskI_reg_imm(tmpI, src2, mask);
8996     lShiftI_reg_reg(dst, src1, tmpI);
8997   %}
8998 %}
8999 
9000 // Register Shift Left Immediate
9001 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9002   match(Set dst (LShiftI src1 src2));
9003 
9004   format %{ "SLWI    $dst, $src1, ($src2 & 0x1f)" %}
9005   size(4);
9006   ins_encode %{
9007     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9008     __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9009   %}
9010   ins_pipe(pipe_class_default);
9011 %}
9012 
9013 // AndI with negpow2-constant + LShiftI
9014 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
9015   match(Set dst (LShiftI (AndI src1 src2) src3));
9016   predicate(UseRotateAndMaskInstructionsPPC64);
9017 
9018   format %{ "RLWINM  $dst, lShiftI(AndI($src1, $src2), $src3)" %}
9019   size(4);
9020   ins_encode %{
9021     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
9022     long src2      = $src2$$constant;
9023     long src3      = $src3$$constant;
9024     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
9025     if (maskbits >= 32) {
9026       __ li($dst$$Register, 0); // addi
9027     } else {
9028       __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
9029     }
9030   %}
9031   ins_pipe(pipe_class_default);
9032 %}
9033 
9034 // RShiftI + AndI with negpow2-constant + LShiftI
9035 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
9036   match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
9037   predicate(UseRotateAndMaskInstructionsPPC64);
9038 
9039   format %{ "RLWINM  $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
9040   size(4);
9041   ins_encode %{
9042     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
9043     long src2      = $src2$$constant;
9044     long src3      = $src3$$constant;
9045     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
9046     if (maskbits >= 32) {
9047       __ li($dst$$Register, 0); // addi
9048     } else {
9049       __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
9050     }
9051   %}
9052   ins_pipe(pipe_class_default);
9053 %}
9054 
9055 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9056   // no match-rule, false predicate
9057   effect(DEF dst, USE src1, USE src2);
9058   predicate(false);
9059 
9060   format %{ "SLD     $dst, $src1, $src2" %}
9061   size(4);
9062   ins_encode %{
9063     // TODO: PPC port $archOpcode(ppc64Opcode_sld);
9064     __ sld($dst$$Register, $src1$$Register, $src2$$Register);
9065   %}
9066   ins_pipe(pipe_class_default);
9067 %}
9068 
9069 // Register Shift Left
9070 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9071   match(Set dst (LShiftL src1 src2));
9072   ins_cost(DEFAULT_COST*2);
9073   expand %{
9074     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9075     iRegIdst tmpI;
9076     maskI_reg_imm(tmpI, src2, mask);
9077     lShiftL_regL_regI(dst, src1, tmpI);
9078   %}
9079 %}
9080 
9081 // Register Shift Left Immediate
9082 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9083   match(Set dst (LShiftL src1 src2));
9084   format %{ "SLDI    $dst, $src1, ($src2 & 0x3f)" %}
9085   size(4);
9086   ins_encode %{
9087     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9088     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9089   %}
9090   ins_pipe(pipe_class_default);
9091 %}
9092 
9093 // If we shift more than 32 bits, we need not convert I2L.
9094 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
9095   match(Set dst (LShiftL (ConvI2L src1) src2));
9096   ins_cost(DEFAULT_COST);
9097 
9098   size(4);
9099   format %{ "SLDI    $dst, i2l($src1), $src2" %}
9100   ins_encode %{
9101     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9102     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9103   %}
9104   ins_pipe(pipe_class_default);
9105 %}
9106 
9107 // Shift a postivie int to the left.
9108 // Clrlsldi clears the upper 32 bits and shifts.
9109 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
9110   match(Set dst (LShiftL (ConvI2L src1) src2));
9111   predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
9112 
9113   format %{ "SLDI    $dst, i2l(positive_int($src1)), $src2" %}
9114   size(4);
9115   ins_encode %{
9116     // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
9117     __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
9118   %}
9119   ins_pipe(pipe_class_default);
9120 %}
9121 
9122 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9123   // no match-rule, false predicate
9124   effect(DEF dst, USE src1, USE src2);
9125   predicate(false);
9126 
9127   format %{ "SRAW    $dst, $src1, $src2" %}
9128   size(4);
9129   ins_encode %{
9130     // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
9131     __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
9132   %}
9133   ins_pipe(pipe_class_default);
9134 %}
9135 
9136 // Register Arithmetic Shift Right
9137 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9138   match(Set dst (RShiftI src1 src2));
9139   ins_cost(DEFAULT_COST*2);
9140   expand %{
9141     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9142     iRegIdst tmpI;
9143     maskI_reg_imm(tmpI, src2, mask);
9144     arShiftI_reg_reg(dst, src1, tmpI);
9145   %}
9146 %}
9147 
9148 // Register Arithmetic Shift Right Immediate
9149 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9150   match(Set dst (RShiftI src1 src2));
9151 
9152   format %{ "SRAWI   $dst, $src1, ($src2 & 0x1f)" %}
9153   size(4);
9154   ins_encode %{
9155     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9156     __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9157   %}
9158   ins_pipe(pipe_class_default);
9159 %}
9160 
9161 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9162   // no match-rule, false predicate
9163   effect(DEF dst, USE src1, USE src2);
9164   predicate(false);
9165 
9166   format %{ "SRAD    $dst, $src1, $src2" %}
9167   size(4);
9168   ins_encode %{
9169     // TODO: PPC port $archOpcode(ppc64Opcode_srad);
9170     __ srad($dst$$Register, $src1$$Register, $src2$$Register);
9171   %}
9172   ins_pipe(pipe_class_default);
9173 %}
9174 
9175 // Register Shift Right Arithmetic Long
9176 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9177   match(Set dst (RShiftL src1 src2));
9178   ins_cost(DEFAULT_COST*2);
9179 
9180   expand %{
9181     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9182     iRegIdst tmpI;
9183     maskI_reg_imm(tmpI, src2, mask);
9184     arShiftL_regL_regI(dst, src1, tmpI);
9185   %}
9186 %}
9187 
9188 // Register Shift Right Immediate
9189 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9190   match(Set dst (RShiftL src1 src2));
9191 
9192   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f)" %}
9193   size(4);
9194   ins_encode %{
9195     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9196     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9197   %}
9198   ins_pipe(pipe_class_default);
9199 %}
9200 
9201 // RShiftL + ConvL2I
9202 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
9203   match(Set dst (ConvL2I (RShiftL src1 src2)));
9204 
9205   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
9206   size(4);
9207   ins_encode %{
9208     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9209     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9210   %}
9211   ins_pipe(pipe_class_default);
9212 %}
9213 
9214 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9215   // no match-rule, false predicate
9216   effect(DEF dst, USE src1, USE src2);
9217   predicate(false);
9218 
9219   format %{ "SRW     $dst, $src1, $src2" %}
9220   size(4);
9221   ins_encode %{
9222     // TODO: PPC port $archOpcode(ppc64Opcode_srw);
9223     __ srw($dst$$Register, $src1$$Register, $src2$$Register);
9224   %}
9225   ins_pipe(pipe_class_default);
9226 %}
9227 
9228 // Register Shift Right
9229 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9230   match(Set dst (URShiftI src1 src2));
9231   ins_cost(DEFAULT_COST*2);
9232 
9233   expand %{
9234     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9235     iRegIdst tmpI;
9236     maskI_reg_imm(tmpI, src2, mask);
9237     urShiftI_reg_reg(dst, src1, tmpI);
9238   %}
9239 %}
9240 
9241 // Register Shift Right Immediate
9242 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9243   match(Set dst (URShiftI src1 src2));
9244 
9245   format %{ "SRWI    $dst, $src1, ($src2 & 0x1f)" %}
9246   size(4);
9247   ins_encode %{
9248     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9249     __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9250   %}
9251   ins_pipe(pipe_class_default);
9252 %}
9253 
9254 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9255   // no match-rule, false predicate
9256   effect(DEF dst, USE src1, USE src2);
9257   predicate(false);
9258 
9259   format %{ "SRD     $dst, $src1, $src2" %}
9260   size(4);
9261   ins_encode %{
9262     // TODO: PPC port $archOpcode(ppc64Opcode_srd);
9263     __ srd($dst$$Register, $src1$$Register, $src2$$Register);
9264   %}
9265   ins_pipe(pipe_class_default);
9266 %}
9267 
9268 // Register Shift Right
9269 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9270   match(Set dst (URShiftL src1 src2));
9271   ins_cost(DEFAULT_COST*2);
9272 
9273   expand %{
9274     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9275     iRegIdst tmpI;
9276     maskI_reg_imm(tmpI, src2, mask);
9277     urShiftL_regL_regI(dst, src1, tmpI);
9278   %}
9279 %}
9280 
9281 // Register Shift Right Immediate
9282 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9283   match(Set dst (URShiftL src1 src2));
9284 
9285   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f)" %}
9286   size(4);
9287   ins_encode %{
9288     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9289     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9290   %}
9291   ins_pipe(pipe_class_default);
9292 %}
9293 
9294 // URShiftL + ConvL2I.
9295 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
9296   match(Set dst (ConvL2I (URShiftL src1 src2)));
9297 
9298   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
9299   size(4);
9300   ins_encode %{
9301     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9302     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9303   %}
9304   ins_pipe(pipe_class_default);
9305 %}
9306 
9307 // Register Shift Right Immediate with a CastP2X
9308 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
9309   match(Set dst (URShiftL (CastP2X src1) src2));
9310 
9311   format %{ "SRDI    $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
9312   size(4);
9313   ins_encode %{
9314     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9315     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9316   %}
9317   ins_pipe(pipe_class_default);
9318 %}
9319 
9320 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
9321   match(Set dst (ConvL2I (ConvI2L src)));
9322 
9323   format %{ "EXTSW   $dst, $src \t// int->int" %}
9324   size(4);
9325   ins_encode %{
9326     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9327     __ extsw($dst$$Register, $src$$Register);
9328   %}
9329   ins_pipe(pipe_class_default);
9330 %}
9331 
9332 //----------Rotate Instructions------------------------------------------------
9333 
9334 // Rotate Left by 8-bit immediate
9335 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
9336   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
9337   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9338 
9339   format %{ "ROTLWI  $dst, $src, $lshift" %}
9340   size(4);
9341   ins_encode %{
9342     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9343     __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
9344   %}
9345   ins_pipe(pipe_class_default);
9346 %}
9347 
9348 // Rotate Right by 8-bit immediate
9349 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
9350   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
9351   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9352 
9353   format %{ "ROTRWI  $dst, $rshift" %}
9354   size(4);
9355   ins_encode %{
9356     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9357     __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
9358   %}
9359   ins_pipe(pipe_class_default);
9360 %}
9361 
9362 //----------Floating Point Arithmetic Instructions-----------------------------
9363 
9364 // Add float single precision
9365 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
9366   match(Set dst (AddF src1 src2));
9367 
9368   format %{ "FADDS   $dst, $src1, $src2" %}
9369   size(4);
9370   ins_encode %{
9371     // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
9372     __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9373   %}
9374   ins_pipe(pipe_class_default);
9375 %}
9376 
9377 // Add float double precision
9378 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
9379   match(Set dst (AddD src1 src2));
9380 
9381   format %{ "FADD    $dst, $src1, $src2" %}
9382   size(4);
9383   ins_encode %{
9384     // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
9385     __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9386   %}
9387   ins_pipe(pipe_class_default);
9388 %}
9389 
9390 // Sub float single precision
9391 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
9392   match(Set dst (SubF src1 src2));
9393 
9394   format %{ "FSUBS   $dst, $src1, $src2" %}
9395   size(4);
9396   ins_encode %{
9397     // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
9398     __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9399   %}
9400   ins_pipe(pipe_class_default);
9401 %}
9402 
9403 // Sub float double precision
9404 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
9405   match(Set dst (SubD src1 src2));
9406   format %{ "FSUB    $dst, $src1, $src2" %}
9407   size(4);
9408   ins_encode %{
9409     // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
9410     __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9411   %}
9412   ins_pipe(pipe_class_default);
9413 %}
9414 
9415 // Mul float single precision
9416 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
9417   match(Set dst (MulF src1 src2));
9418   format %{ "FMULS   $dst, $src1, $src2" %}
9419   size(4);
9420   ins_encode %{
9421     // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
9422     __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9423   %}
9424   ins_pipe(pipe_class_default);
9425 %}
9426 
9427 // Mul float double precision
9428 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
9429   match(Set dst (MulD src1 src2));
9430   format %{ "FMUL    $dst, $src1, $src2" %}
9431   size(4);
9432   ins_encode %{
9433     // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
9434     __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9435   %}
9436   ins_pipe(pipe_class_default);
9437 %}
9438 
9439 // Div float single precision
9440 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
9441   match(Set dst (DivF src1 src2));
9442   format %{ "FDIVS   $dst, $src1, $src2" %}
9443   size(4);
9444   ins_encode %{
9445     // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
9446     __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9447   %}
9448   ins_pipe(pipe_class_default);
9449 %}
9450 
9451 // Div float double precision
9452 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
9453   match(Set dst (DivD src1 src2));
9454   format %{ "FDIV    $dst, $src1, $src2" %}
9455   size(4);
9456   ins_encode %{
9457     // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
9458     __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9459   %}
9460   ins_pipe(pipe_class_default);
9461 %}
9462 
9463 // Absolute float single precision
9464 instruct absF_reg(regF dst, regF src) %{
9465   match(Set dst (AbsF src));
9466   format %{ "FABS    $dst, $src \t// float" %}
9467   size(4);
9468   ins_encode %{
9469     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
9470     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
9471   %}
9472   ins_pipe(pipe_class_default);
9473 %}
9474 
9475 // Absolute float double precision
9476 instruct absD_reg(regD dst, regD src) %{
9477   match(Set dst (AbsD src));
9478   format %{ "FABS    $dst, $src \t// double" %}
9479   size(4);
9480   ins_encode %{
9481     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
9482     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
9483   %}
9484   ins_pipe(pipe_class_default);
9485 %}
9486 
9487 instruct negF_reg(regF dst, regF src) %{
9488   match(Set dst (NegF src));
9489   format %{ "FNEG    $dst, $src \t// float" %}
9490   size(4);
9491   ins_encode %{
9492     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
9493     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
9494   %}
9495   ins_pipe(pipe_class_default);
9496 %}
9497 
9498 instruct negD_reg(regD dst, regD src) %{
9499   match(Set dst (NegD src));
9500   format %{ "FNEG    $dst, $src \t// double" %}
9501   size(4);
9502   ins_encode %{
9503     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
9504     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
9505   %}
9506   ins_pipe(pipe_class_default);
9507 %}
9508 
9509 // AbsF + NegF.
9510 instruct negF_absF_reg(regF dst, regF src) %{
9511   match(Set dst (NegF (AbsF src)));
9512   format %{ "FNABS   $dst, $src \t// float" %}
9513   size(4);
9514   ins_encode %{
9515     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
9516     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
9517   %}
9518   ins_pipe(pipe_class_default);
9519 %}
9520 
9521 // AbsD + NegD.
9522 instruct negD_absD_reg(regD dst, regD src) %{
9523   match(Set dst (NegD (AbsD src)));
9524   format %{ "FNABS   $dst, $src \t// double" %}
9525   size(4);
9526   ins_encode %{
9527     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
9528     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
9529   %}
9530   ins_pipe(pipe_class_default);
9531 %}
9532 
9533 // VM_Version::has_fsqrt() decides if this node will be used.
9534 // Sqrt float double precision
9535 instruct sqrtD_reg(regD dst, regD src) %{
9536   match(Set dst (SqrtD src));
9537   format %{ "FSQRT   $dst, $src" %}
9538   size(4);
9539   ins_encode %{
9540     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
9541     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
9542   %}
9543   ins_pipe(pipe_class_default);
9544 %}
9545 
9546 // Single-precision sqrt.
9547 instruct sqrtF_reg(regF dst, regF src) %{
9548   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
9549   predicate(VM_Version::has_fsqrts());
9550   ins_cost(DEFAULT_COST);
9551 
9552   format %{ "FSQRTS  $dst, $src" %}
9553   size(4);
9554   ins_encode %{
9555     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
9556     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
9557   %}
9558   ins_pipe(pipe_class_default);
9559 %}
9560 
9561 instruct roundDouble_nop(regD dst) %{
9562   match(Set dst (RoundDouble dst));
9563   ins_cost(0);
9564 
9565   format %{ " -- \t// RoundDouble not needed - empty" %}
9566   size(0);
9567   // PPC results are already "rounded" (i.e., normal-format IEEE).
9568   ins_encode( /*empty*/ );
9569   ins_pipe(pipe_class_default);
9570 %}
9571 
9572 instruct roundFloat_nop(regF dst) %{
9573   match(Set dst (RoundFloat dst));
9574   ins_cost(0);
9575 
9576   format %{ " -- \t// RoundFloat not needed - empty" %}
9577   size(0);
9578   // PPC results are already "rounded" (i.e., normal-format IEEE).
9579   ins_encode( /*empty*/ );
9580   ins_pipe(pipe_class_default);
9581 %}
9582 
9583 
9584 // Multiply-Accumulate
9585 // src1 * src2 + src3
9586 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9587   match(Set dst (FmaF src3 (Binary src1 src2)));
9588 
9589   format %{ "FMADDS  $dst, $src1, $src2, $src3" %}
9590   size(4);
9591   ins_encode %{
9592     // TODO: PPC port $archOpcode(ppc64Opcode_fmadds);
9593     __ fmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9594   %}
9595   ins_pipe(pipe_class_default);
9596 %}
9597 
9598 // src1 * src2 + src3
9599 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9600   match(Set dst (FmaD src3 (Binary src1 src2)));
9601 
9602   format %{ "FMADD   $dst, $src1, $src2, $src3" %}
9603   size(4);
9604   ins_encode %{
9605     // TODO: PPC port $archOpcode(ppc64Opcode_fmadd);
9606     __ fmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9607   %}
9608   ins_pipe(pipe_class_default);
9609 %}
9610 
9611 // -src1 * src2 + src3 = -(src1*src2-src3)
9612 instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9613   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
9614   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
9615 
9616   format %{ "FNMSUBS $dst, $src1, $src2, $src3" %}
9617   size(4);
9618   ins_encode %{
9619     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsubs);
9620     __ fnmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9621   %}
9622   ins_pipe(pipe_class_default);
9623 %}
9624 
9625 // -src1 * src2 + src3 = -(src1*src2-src3)
9626 instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9627   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
9628   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
9629 
9630   format %{ "FNMSUB  $dst, $src1, $src2, $src3" %}
9631   size(4);
9632   ins_encode %{
9633     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsub);
9634     __ fnmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9635   %}
9636   ins_pipe(pipe_class_default);
9637 %}
9638 
9639 // -src1 * src2 - src3 = -(src1*src2+src3)
9640 instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9641   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
9642   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
9643 
9644   format %{ "FNMADDS $dst, $src1, $src2, $src3" %}
9645   size(4);
9646   ins_encode %{
9647     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadds);
9648     __ fnmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9649   %}
9650   ins_pipe(pipe_class_default);
9651 %}
9652 
9653 // -src1 * src2 - src3 = -(src1*src2+src3)
9654 instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9655   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
9656   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
9657 
9658   format %{ "FNMADD  $dst, $src1, $src2, $src3" %}
9659   size(4);
9660   ins_encode %{
9661     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadd);
9662     __ fnmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9663   %}
9664   ins_pipe(pipe_class_default);
9665 %}
9666 
9667 // src1 * src2 - src3
9668 instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9669   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
9670 
9671   format %{ "FMSUBS  $dst, $src1, $src2, $src3" %}
9672   size(4);
9673   ins_encode %{
9674     // TODO: PPC port $archOpcode(ppc64Opcode_fmsubs);
9675     __ fmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9676   %}
9677   ins_pipe(pipe_class_default);
9678 %}
9679 
9680 // src1 * src2 - src3
9681 instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9682   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
9683 
9684   format %{ "FMSUB   $dst, $src1, $src2, $src3" %}
9685   size(4);
9686   ins_encode %{
9687     // TODO: PPC port $archOpcode(ppc64Opcode_fmsub);
9688     __ fmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9689   %}
9690   ins_pipe(pipe_class_default);
9691 %}
9692 
9693 
9694 //----------Logical Instructions-----------------------------------------------
9695 
9696 // And Instructions
9697 
9698 // Register And
9699 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9700   match(Set dst (AndI src1 src2));
9701   format %{ "AND     $dst, $src1, $src2" %}
9702   size(4);
9703   ins_encode %{
9704     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9705     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9706   %}
9707   ins_pipe(pipe_class_default);
9708 %}
9709 
9710 // Left shifted Immediate And
9711 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16  src2, flagsRegCR0 cr0) %{
9712   match(Set dst (AndI src1 src2));
9713   effect(KILL cr0);
9714   format %{ "ANDIS   $dst, $src1, $src2.hi" %}
9715   size(4);
9716   ins_encode %{
9717     // TODO: PPC port $archOpcode(ppc64Opcode_andis_);
9718     __ andis_($dst$$Register, $src1$$Register, (int)((unsigned short)(($src2$$constant & 0xFFFF0000) >> 16)));
9719   %}
9720   ins_pipe(pipe_class_default);
9721 %}
9722 
9723 // Immediate And
9724 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
9725   match(Set dst (AndI src1 src2));
9726   effect(KILL cr0);
9727 
9728   format %{ "ANDI    $dst, $src1, $src2" %}
9729   size(4);
9730   ins_encode %{
9731     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9732     // FIXME: avoid andi_ ?
9733     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9734   %}
9735   ins_pipe(pipe_class_default);
9736 %}
9737 
9738 // Immediate And where the immediate is a negative power of 2.
9739 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
9740   match(Set dst (AndI src1 src2));
9741   format %{ "ANDWI   $dst, $src1, $src2" %}
9742   size(4);
9743   ins_encode %{
9744     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9745     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
9746   %}
9747   ins_pipe(pipe_class_default);
9748 %}
9749 
9750 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
9751   match(Set dst (AndI src1 src2));
9752   format %{ "ANDWI   $dst, $src1, $src2" %}
9753   size(4);
9754   ins_encode %{
9755     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9756     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9757   %}
9758   ins_pipe(pipe_class_default);
9759 %}
9760 
9761 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
9762   match(Set dst (AndI src1 src2));
9763   predicate(UseRotateAndMaskInstructionsPPC64);
9764   format %{ "ANDWI   $dst, $src1, $src2" %}
9765   size(4);
9766   ins_encode %{
9767     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9768     __ rlwinm($dst$$Register, $src1$$Register, 0,
9769               (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
9770   %}
9771   ins_pipe(pipe_class_default);
9772 %}
9773 
9774 // Register And Long
9775 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9776   match(Set dst (AndL src1 src2));
9777   ins_cost(DEFAULT_COST);
9778 
9779   format %{ "AND     $dst, $src1, $src2 \t// long" %}
9780   size(4);
9781   ins_encode %{
9782     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9783     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9784   %}
9785   ins_pipe(pipe_class_default);
9786 %}
9787 
9788 // Immediate And long
9789 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
9790   match(Set dst (AndL src1 src2));
9791   effect(KILL cr0);
9792 
9793   format %{ "ANDI    $dst, $src1, $src2 \t// long" %}
9794   size(4);
9795   ins_encode %{
9796     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9797     // FIXME: avoid andi_ ?
9798     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9799   %}
9800   ins_pipe(pipe_class_default);
9801 %}
9802 
9803 // Immediate And Long where the immediate is a negative power of 2.
9804 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
9805   match(Set dst (AndL src1 src2));
9806   format %{ "ANDDI   $dst, $src1, $src2" %}
9807   size(4);
9808   ins_encode %{
9809     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9810     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9811   %}
9812   ins_pipe(pipe_class_default);
9813 %}
9814 
9815 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9816   match(Set dst (AndL src1 src2));
9817   format %{ "ANDDI   $dst, $src1, $src2" %}
9818   size(4);
9819   ins_encode %{
9820     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9821     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9822   %}
9823   ins_pipe(pipe_class_default);
9824 %}
9825 
9826 // AndL + ConvL2I.
9827 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9828   match(Set dst (ConvL2I (AndL src1 src2)));
9829   ins_cost(DEFAULT_COST);
9830 
9831   format %{ "ANDDI   $dst, $src1, $src2 \t// long + l2i" %}
9832   size(4);
9833   ins_encode %{
9834     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9835     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9836   %}
9837   ins_pipe(pipe_class_default);
9838 %}
9839 
9840 // Or Instructions
9841 
9842 // Register Or
9843 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9844   match(Set dst (OrI src1 src2));
9845   format %{ "OR      $dst, $src1, $src2" %}
9846   size(4);
9847   ins_encode %{
9848     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9849     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9850   %}
9851   ins_pipe(pipe_class_default);
9852 %}
9853 
9854 // Expand does not work with above instruct. (??)
9855 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9856   // no match-rule
9857   effect(DEF dst, USE src1, USE src2);
9858   format %{ "OR      $dst, $src1, $src2" %}
9859   size(4);
9860   ins_encode %{
9861     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9862     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9863   %}
9864   ins_pipe(pipe_class_default);
9865 %}
9866 
9867 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9868   match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9869   ins_cost(DEFAULT_COST*3);
9870 
9871   expand %{
9872     // FIXME: we should do this in the ideal world.
9873     iRegIdst tmp1;
9874     iRegIdst tmp2;
9875     orI_reg_reg(tmp1, src1, src2);
9876     orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9877     orI_reg_reg(dst, tmp1, tmp2);
9878   %}
9879 %}
9880 
9881 // Immediate Or
9882 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9883   match(Set dst (OrI src1 src2));
9884   format %{ "ORI     $dst, $src1, $src2" %}
9885   size(4);
9886   ins_encode %{
9887     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9888     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9889   %}
9890   ins_pipe(pipe_class_default);
9891 %}
9892 
9893 // Register Or Long
9894 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9895   match(Set dst (OrL src1 src2));
9896   ins_cost(DEFAULT_COST);
9897 
9898   size(4);
9899   format %{ "OR      $dst, $src1, $src2 \t// long" %}
9900   ins_encode %{
9901     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9902     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9903   %}
9904   ins_pipe(pipe_class_default);
9905 %}
9906 
9907 // OrL + ConvL2I.
9908 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9909   match(Set dst (ConvL2I (OrL src1 src2)));
9910   ins_cost(DEFAULT_COST);
9911 
9912   format %{ "OR      $dst, $src1, $src2 \t// long + l2i" %}
9913   size(4);
9914   ins_encode %{
9915     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9916     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9917   %}
9918   ins_pipe(pipe_class_default);
9919 %}
9920 
9921 // Immediate Or long
9922 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9923   match(Set dst (OrL src1 con));
9924   ins_cost(DEFAULT_COST);
9925 
9926   format %{ "ORI     $dst, $src1, $con \t// long" %}
9927   size(4);
9928   ins_encode %{
9929     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9930     __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9931   %}
9932   ins_pipe(pipe_class_default);
9933 %}
9934 
9935 // Xor Instructions
9936 
9937 // Register Xor
9938 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9939   match(Set dst (XorI src1 src2));
9940   format %{ "XOR     $dst, $src1, $src2" %}
9941   size(4);
9942   ins_encode %{
9943     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9944     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9945   %}
9946   ins_pipe(pipe_class_default);
9947 %}
9948 
9949 // Expand does not work with above instruct. (??)
9950 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9951   // no match-rule
9952   effect(DEF dst, USE src1, USE src2);
9953   format %{ "XOR     $dst, $src1, $src2" %}
9954   size(4);
9955   ins_encode %{
9956     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9957     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9958   %}
9959   ins_pipe(pipe_class_default);
9960 %}
9961 
9962 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9963   match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9964   ins_cost(DEFAULT_COST*3);
9965 
9966   expand %{
9967     // FIXME: we should do this in the ideal world.
9968     iRegIdst tmp1;
9969     iRegIdst tmp2;
9970     xorI_reg_reg(tmp1, src1, src2);
9971     xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9972     xorI_reg_reg(dst, tmp1, tmp2);
9973   %}
9974 %}
9975 
9976 // Immediate Xor
9977 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9978   match(Set dst (XorI src1 src2));
9979   format %{ "XORI    $dst, $src1, $src2" %}
9980   size(4);
9981   ins_encode %{
9982     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9983     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9984   %}
9985   ins_pipe(pipe_class_default);
9986 %}
9987 
9988 // Register Xor Long
9989 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9990   match(Set dst (XorL src1 src2));
9991   ins_cost(DEFAULT_COST);
9992 
9993   format %{ "XOR     $dst, $src1, $src2 \t// long" %}
9994   size(4);
9995   ins_encode %{
9996     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9997     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9998   %}
9999   ins_pipe(pipe_class_default);
10000 %}
10001 
10002 // XorL + ConvL2I.
10003 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10004   match(Set dst (ConvL2I (XorL src1 src2)));
10005   ins_cost(DEFAULT_COST);
10006 
10007   format %{ "XOR     $dst, $src1, $src2 \t// long + l2i" %}
10008   size(4);
10009   ins_encode %{
10010     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10011     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10012   %}
10013   ins_pipe(pipe_class_default);
10014 %}
10015 
10016 // Immediate Xor Long
10017 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
10018   match(Set dst (XorL src1 src2));
10019   ins_cost(DEFAULT_COST);
10020 
10021   format %{ "XORI    $dst, $src1, $src2 \t// long" %}
10022   size(4);
10023   ins_encode %{
10024     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
10025     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
10026   %}
10027   ins_pipe(pipe_class_default);
10028 %}
10029 
10030 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
10031   match(Set dst (XorI src1 src2));
10032   ins_cost(DEFAULT_COST);
10033 
10034   format %{ "NOT     $dst, $src1 ($src2)" %}
10035   size(4);
10036   ins_encode %{
10037     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
10038     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
10039   %}
10040   ins_pipe(pipe_class_default);
10041 %}
10042 
10043 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
10044   match(Set dst (XorL src1 src2));
10045   ins_cost(DEFAULT_COST);
10046 
10047   format %{ "NOT     $dst, $src1 ($src2) \t// long" %}
10048   size(4);
10049   ins_encode %{
10050     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
10051     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
10052   %}
10053   ins_pipe(pipe_class_default);
10054 %}
10055 
10056 // And-complement
10057 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
10058   match(Set dst (AndI (XorI src1 src2) src3));
10059   ins_cost(DEFAULT_COST);
10060 
10061   format %{ "ANDW    $dst, xori($src1, $src2), $src3" %}
10062   size(4);
10063   ins_encode( enc_andc(dst, src3, src1) );
10064   ins_pipe(pipe_class_default);
10065 %}
10066 
10067 // And-complement
10068 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
10069   // no match-rule, false predicate
10070   effect(DEF dst, USE src1, USE src2);
10071   predicate(false);
10072 
10073   format %{ "ANDC    $dst, $src1, $src2" %}
10074   size(4);
10075   ins_encode %{
10076     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
10077     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
10078   %}
10079   ins_pipe(pipe_class_default);
10080 %}
10081 
10082 //----------Moves between int/long and float/double----------------------------
10083 //
10084 // The following rules move values from int/long registers/stack-locations
10085 // to float/double registers/stack-locations and vice versa, without doing any
10086 // conversions. These rules are used to implement the bit-conversion methods
10087 // of java.lang.Float etc., e.g.
10088 //   int   floatToIntBits(float value)
10089 //   float intBitsToFloat(int bits)
10090 //
10091 // Notes on the implementation on ppc64:
10092 // For Power7 and earlier, the rules are limited to those which move between a
10093 // register and a stack-location, because we always have to go through memory
10094 // when moving between a float register and an integer register.
10095 // This restriction is removed in Power8 with the introduction of the mtfprd
10096 // and mffprd instructions.
10097 
10098 instruct moveL2D_reg(regD dst, iRegLsrc src) %{
10099   match(Set dst (MoveL2D src));
10100   effect(DEF dst, USE src);
10101   predicate(VM_Version::has_mtfprd());
10102 
10103   format %{ "MTFPRD  $dst, $src" %}
10104   size(4);
10105   ins_encode %{
10106     __ mtfprd($dst$$FloatRegister, $src$$Register);
10107   %}
10108   ins_pipe(pipe_class_default);
10109 %}
10110 
10111 instruct moveI2D_reg(regD dst, iRegIsrc src) %{
10112   // no match-rule, false predicate
10113   effect(DEF dst, USE src);
10114   predicate(false);
10115 
10116   format %{ "MTFPRWA $dst, $src" %}
10117   size(4);
10118   ins_encode %{
10119     __ mtfprwa($dst$$FloatRegister, $src$$Register);
10120   %}
10121   ins_pipe(pipe_class_default);
10122 %}
10123 
10124 //---------- Chain stack slots between similar types --------
10125 
10126 // These are needed so that the rules below can match.
10127 
10128 // Load integer from stack slot
10129 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
10130   match(Set dst src);
10131   ins_cost(MEMORY_REF_COST);
10132 
10133   format %{ "LWZ     $dst, $src" %}
10134   size(4);
10135   ins_encode( enc_lwz(dst, src) );
10136   ins_pipe(pipe_class_memory);
10137 %}
10138 
10139 // Store integer to stack slot
10140 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
10141   match(Set dst src);
10142   ins_cost(MEMORY_REF_COST);
10143 
10144   format %{ "STW     $src, $dst \t// stk" %}
10145   size(4);
10146   ins_encode( enc_stw(src, dst) ); // rs=rt
10147   ins_pipe(pipe_class_memory);
10148 %}
10149 
10150 // Load long from stack slot
10151 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
10152   match(Set dst src);
10153   ins_cost(MEMORY_REF_COST);
10154 
10155   format %{ "LD      $dst, $src \t// long" %}
10156   size(4);
10157   ins_encode( enc_ld(dst, src) );
10158   ins_pipe(pipe_class_memory);
10159 %}
10160 
10161 // Store long to stack slot
10162 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
10163   match(Set dst src);
10164   ins_cost(MEMORY_REF_COST);
10165 
10166   format %{ "STD     $src, $dst \t// long" %}
10167   size(4);
10168   ins_encode( enc_std(src, dst) ); // rs=rt
10169   ins_pipe(pipe_class_memory);
10170 %}
10171 
10172 //----------Moves between int and float
10173 
10174 // Move float value from float stack-location to integer register.
10175 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
10176   match(Set dst (MoveF2I src));
10177   ins_cost(MEMORY_REF_COST);
10178 
10179   format %{ "LWZ     $dst, $src \t// MoveF2I" %}
10180   size(4);
10181   ins_encode( enc_lwz(dst, src) );
10182   ins_pipe(pipe_class_memory);
10183 %}
10184 
10185 // Move float value from float register to integer stack-location.
10186 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
10187   match(Set dst (MoveF2I src));
10188   ins_cost(MEMORY_REF_COST);
10189 
10190   format %{ "STFS    $src, $dst \t// MoveF2I" %}
10191   size(4);
10192   ins_encode( enc_stfs(src, dst) );
10193   ins_pipe(pipe_class_memory);
10194 %}
10195 
10196 // Move integer value from integer stack-location to float register.
10197 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
10198   match(Set dst (MoveI2F src));
10199   ins_cost(MEMORY_REF_COST);
10200 
10201   format %{ "LFS     $dst, $src \t// MoveI2F" %}
10202   size(4);
10203   ins_encode %{
10204     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
10205     int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
10206     __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
10207   %}
10208   ins_pipe(pipe_class_memory);
10209 %}
10210 
10211 // Move integer value from integer register to float stack-location.
10212 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
10213   match(Set dst (MoveI2F src));
10214   ins_cost(MEMORY_REF_COST);
10215 
10216   format %{ "STW     $src, $dst \t// MoveI2F" %}
10217   size(4);
10218   ins_encode( enc_stw(src, dst) );
10219   ins_pipe(pipe_class_memory);
10220 %}
10221 
10222 //----------Moves between long and float
10223 
10224 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
10225   // no match-rule, false predicate
10226   effect(DEF dst, USE src);
10227   predicate(false);
10228 
10229   format %{ "storeD  $src, $dst \t// STACK" %}
10230   size(4);
10231   ins_encode( enc_stfd(src, dst) );
10232   ins_pipe(pipe_class_default);
10233 %}
10234 
10235 //----------Moves between long and double
10236 
10237 // Move double value from double stack-location to long register.
10238 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
10239   match(Set dst (MoveD2L src));
10240   ins_cost(MEMORY_REF_COST);
10241   size(4);
10242   format %{ "LD      $dst, $src \t// MoveD2L" %}
10243   ins_encode( enc_ld(dst, src) );
10244   ins_pipe(pipe_class_memory);
10245 %}
10246 
10247 // Move double value from double register to long stack-location.
10248 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
10249   match(Set dst (MoveD2L src));
10250   effect(DEF dst, USE src);
10251   ins_cost(MEMORY_REF_COST);
10252 
10253   format %{ "STFD    $src, $dst \t// MoveD2L" %}
10254   size(4);
10255   ins_encode( enc_stfd(src, dst) );
10256   ins_pipe(pipe_class_memory);
10257 %}
10258 
10259 // Move long value from long stack-location to double register.
10260 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
10261   match(Set dst (MoveL2D src));
10262   ins_cost(MEMORY_REF_COST);
10263 
10264   format %{ "LFD     $dst, $src \t// MoveL2D" %}
10265   size(4);
10266   ins_encode( enc_lfd(dst, src) );
10267   ins_pipe(pipe_class_memory);
10268 %}
10269 
10270 // Move long value from long register to double stack-location.
10271 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
10272   match(Set dst (MoveL2D src));
10273   ins_cost(MEMORY_REF_COST);
10274 
10275   format %{ "STD     $src, $dst \t// MoveL2D" %}
10276   size(4);
10277   ins_encode( enc_std(src, dst) );
10278   ins_pipe(pipe_class_memory);
10279 %}
10280 
10281 //----------Register Move Instructions-----------------------------------------
10282 
10283 // Replicate for Superword
10284 
10285 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
10286   predicate(false);
10287   effect(DEF dst, USE src);
10288 
10289   format %{ "MR      $dst, $src \t// replicate " %}
10290   // variable size, 0 or 4.
10291   ins_encode %{
10292     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10293     __ mr_if_needed($dst$$Register, $src$$Register);
10294   %}
10295   ins_pipe(pipe_class_default);
10296 %}
10297 
10298 //----------Cast instructions (Java-level type cast)---------------------------
10299 
10300 // Cast Long to Pointer for unsafe natives.
10301 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
10302   match(Set dst (CastX2P src));
10303 
10304   format %{ "MR      $dst, $src \t// Long->Ptr" %}
10305   // variable size, 0 or 4.
10306   ins_encode %{
10307     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10308     __ mr_if_needed($dst$$Register, $src$$Register);
10309   %}
10310  ins_pipe(pipe_class_default);
10311 %}
10312 
10313 // Cast Pointer to Long for unsafe natives.
10314 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
10315   match(Set dst (CastP2X src));
10316 
10317   format %{ "MR      $dst, $src \t// Ptr->Long" %}
10318   // variable size, 0 or 4.
10319   ins_encode %{
10320     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10321     __ mr_if_needed($dst$$Register, $src$$Register);
10322   %}
10323   ins_pipe(pipe_class_default);
10324 %}
10325 
10326 instruct castPP(iRegPdst dst) %{
10327   match(Set dst (CastPP dst));
10328   format %{ " -- \t// castPP of $dst" %}
10329   size(0);
10330   ins_encode( /*empty*/ );
10331   ins_pipe(pipe_class_default);
10332 %}
10333 
10334 instruct castII(iRegIdst dst) %{
10335   match(Set dst (CastII dst));
10336   format %{ " -- \t// castII of $dst" %}
10337   size(0);
10338   ins_encode( /*empty*/ );
10339   ins_pipe(pipe_class_default);
10340 %}
10341 
10342 instruct checkCastPP(iRegPdst dst) %{
10343   match(Set dst (CheckCastPP dst));
10344   format %{ " -- \t// checkcastPP of $dst" %}
10345   size(0);
10346   ins_encode( /*empty*/ );
10347   ins_pipe(pipe_class_default);
10348 %}
10349 
10350 //----------Convert instructions-----------------------------------------------
10351 
10352 // Convert to boolean.
10353 
10354 // int_to_bool(src) : { 1   if src != 0
10355 //                    { 0   else
10356 //
10357 // strategy:
10358 // 1) Count leading zeros of 32 bit-value src,
10359 //    this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
10360 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
10361 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
10362 
10363 // convI2Bool
10364 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
10365   match(Set dst (Conv2B src));
10366   predicate(UseCountLeadingZerosInstructionsPPC64);
10367   ins_cost(DEFAULT_COST);
10368 
10369   expand %{
10370     immI shiftAmount %{ 0x5 %}
10371     uimmI16 mask %{ 0x1 %}
10372     iRegIdst tmp1;
10373     iRegIdst tmp2;
10374     countLeadingZerosI(tmp1, src);
10375     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
10376     xorI_reg_uimm16(dst, tmp2, mask);
10377   %}
10378 %}
10379 
10380 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
10381   match(Set dst (Conv2B src));
10382   effect(TEMP crx);
10383   predicate(!UseCountLeadingZerosInstructionsPPC64);
10384   ins_cost(DEFAULT_COST);
10385 
10386   format %{ "CMPWI   $crx, $src, #0 \t// convI2B"
10387             "LI      $dst, #0\n\t"
10388             "BEQ     $crx, done\n\t"
10389             "LI      $dst, #1\n"
10390             "done:" %}
10391   size(16);
10392   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
10393   ins_pipe(pipe_class_compare);
10394 %}
10395 
10396 // ConvI2B + XorI
10397 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
10398   match(Set dst (XorI (Conv2B src) mask));
10399   predicate(UseCountLeadingZerosInstructionsPPC64);
10400   ins_cost(DEFAULT_COST);
10401 
10402   expand %{
10403     immI shiftAmount %{ 0x5 %}
10404     iRegIdst tmp1;
10405     countLeadingZerosI(tmp1, src);
10406     urShiftI_reg_imm(dst, tmp1, shiftAmount);
10407   %}
10408 %}
10409 
10410 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
10411   match(Set dst (XorI (Conv2B src) mask));
10412   effect(TEMP crx);
10413   predicate(!UseCountLeadingZerosInstructionsPPC64);
10414   ins_cost(DEFAULT_COST);
10415 
10416   format %{ "CMPWI   $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
10417             "LI      $dst, #1\n\t"
10418             "BEQ     $crx, done\n\t"
10419             "LI      $dst, #0\n"
10420             "done:" %}
10421   size(16);
10422   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
10423   ins_pipe(pipe_class_compare);
10424 %}
10425 
10426 // AndI 0b0..010..0 + ConvI2B
10427 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
10428   match(Set dst (Conv2B (AndI src mask)));
10429   predicate(UseRotateAndMaskInstructionsPPC64);
10430   ins_cost(DEFAULT_COST);
10431 
10432   format %{ "RLWINM  $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
10433   size(4);
10434   ins_encode %{
10435     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
10436     __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
10437   %}
10438   ins_pipe(pipe_class_default);
10439 %}
10440 
10441 // Convert pointer to boolean.
10442 //
10443 // ptr_to_bool(src) : { 1   if src != 0
10444 //                    { 0   else
10445 //
10446 // strategy:
10447 // 1) Count leading zeros of 64 bit-value src,
10448 //    this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
10449 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
10450 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
10451 
10452 // ConvP2B
10453 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
10454   match(Set dst (Conv2B src));
10455   predicate(UseCountLeadingZerosInstructionsPPC64);
10456   ins_cost(DEFAULT_COST);
10457 
10458   expand %{
10459     immI shiftAmount %{ 0x6 %}
10460     uimmI16 mask %{ 0x1 %}
10461     iRegIdst tmp1;
10462     iRegIdst tmp2;
10463     countLeadingZerosP(tmp1, src);
10464     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
10465     xorI_reg_uimm16(dst, tmp2, mask);
10466   %}
10467 %}
10468 
10469 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
10470   match(Set dst (Conv2B src));
10471   effect(TEMP crx);
10472   predicate(!UseCountLeadingZerosInstructionsPPC64);
10473   ins_cost(DEFAULT_COST);
10474 
10475   format %{ "CMPDI   $crx, $src, #0 \t// convP2B"
10476             "LI      $dst, #0\n\t"
10477             "BEQ     $crx, done\n\t"
10478             "LI      $dst, #1\n"
10479             "done:" %}
10480   size(16);
10481   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
10482   ins_pipe(pipe_class_compare);
10483 %}
10484 
10485 // ConvP2B + XorI
10486 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
10487   match(Set dst (XorI (Conv2B src) mask));
10488   predicate(UseCountLeadingZerosInstructionsPPC64);
10489   ins_cost(DEFAULT_COST);
10490 
10491   expand %{
10492     immI shiftAmount %{ 0x6 %}
10493     iRegIdst tmp1;
10494     countLeadingZerosP(tmp1, src);
10495     urShiftI_reg_imm(dst, tmp1, shiftAmount);
10496   %}
10497 %}
10498 
10499 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
10500   match(Set dst (XorI (Conv2B src) mask));
10501   effect(TEMP crx);
10502   predicate(!UseCountLeadingZerosInstructionsPPC64);
10503   ins_cost(DEFAULT_COST);
10504 
10505   format %{ "CMPDI   $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
10506             "LI      $dst, #1\n\t"
10507             "BEQ     $crx, done\n\t"
10508             "LI      $dst, #0\n"
10509             "done:" %}
10510   size(16);
10511   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
10512   ins_pipe(pipe_class_compare);
10513 %}
10514 
10515 // if src1 < src2, return -1 else return 0
10516 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
10517   match(Set dst (CmpLTMask src1 src2));
10518   ins_cost(DEFAULT_COST*4);
10519 
10520   expand %{
10521     iRegLdst src1s;
10522     iRegLdst src2s;
10523     iRegLdst diff;
10524     convI2L_reg(src1s, src1); // Ensure proper sign extension.
10525     convI2L_reg(src2s, src2); // Ensure proper sign extension.
10526     subL_reg_reg(diff, src1s, src2s);
10527     // Need to consider >=33 bit result, therefore we need signmaskL.
10528     signmask64I_regL(dst, diff);
10529   %}
10530 %}
10531 
10532 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
10533   match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
10534   format %{ "SRAWI   $dst, $src1, $src2 \t// CmpLTMask" %}
10535   size(4);
10536   ins_encode %{
10537     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
10538     __ srawi($dst$$Register, $src1$$Register, 0x1f);
10539   %}
10540   ins_pipe(pipe_class_default);
10541 %}
10542 
10543 //----------Arithmetic Conversion Instructions---------------------------------
10544 
10545 // Convert to Byte  -- nop
10546 // Convert to Short -- nop
10547 
10548 // Convert to Int
10549 
10550 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
10551   match(Set dst (RShiftI (LShiftI src amount) amount));
10552   format %{ "EXTSB   $dst, $src \t// byte->int" %}
10553   size(4);
10554   ins_encode %{
10555     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
10556     __ extsb($dst$$Register, $src$$Register);
10557   %}
10558   ins_pipe(pipe_class_default);
10559 %}
10560 
10561 // LShiftI 16 + RShiftI 16 converts short to int.
10562 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
10563   match(Set dst (RShiftI (LShiftI src amount) amount));
10564   format %{ "EXTSH   $dst, $src \t// short->int" %}
10565   size(4);
10566   ins_encode %{
10567     // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
10568     __ extsh($dst$$Register, $src$$Register);
10569   %}
10570   ins_pipe(pipe_class_default);
10571 %}
10572 
10573 // ConvL2I + ConvI2L: Sign extend int in long register.
10574 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
10575   match(Set dst (ConvI2L (ConvL2I src)));
10576 
10577   format %{ "EXTSW   $dst, $src \t// long->long" %}
10578   size(4);
10579   ins_encode %{
10580     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10581     __ extsw($dst$$Register, $src$$Register);
10582   %}
10583   ins_pipe(pipe_class_default);
10584 %}
10585 
10586 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
10587   match(Set dst (ConvL2I src));
10588   format %{ "MR      $dst, $src \t// long->int" %}
10589   // variable size, 0 or 4
10590   ins_encode %{
10591     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10592     __ mr_if_needed($dst$$Register, $src$$Register);
10593   %}
10594   ins_pipe(pipe_class_default);
10595 %}
10596 
10597 instruct convD2IRaw_regD(regD dst, regD src) %{
10598   // no match-rule, false predicate
10599   effect(DEF dst, USE src);
10600   predicate(false);
10601 
10602   format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
10603   size(4);
10604   ins_encode %{
10605     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
10606     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10607   %}
10608   ins_pipe(pipe_class_default);
10609 %}
10610 
10611 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
10612   // no match-rule, false predicate
10613   effect(DEF dst, USE crx, USE src);
10614   predicate(false);
10615 
10616   ins_variable_size_depending_on_alignment(true);
10617 
10618   format %{ "cmovI   $crx, $dst, $src" %}
10619   // Worst case is branch + move + stop, no stop without scheduler.
10620   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10621   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10622   ins_pipe(pipe_class_default);
10623 %}
10624 
10625 instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
10626   // no match-rule, false predicate
10627   effect(DEF dst, USE crx, USE src);
10628   predicate(false);
10629 
10630   ins_variable_size_depending_on_alignment(true);
10631 
10632   format %{ "cmovI   $crx, $dst, $src" %}
10633   // Worst case is branch + move + stop, no stop without scheduler.
10634   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10635   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10636   ins_pipe(pipe_class_default);
10637 %}
10638 
10639 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
10640   // no match-rule, false predicate
10641   effect(DEF dst, USE crx, USE mem);
10642   predicate(false);
10643 
10644   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
10645   postalloc_expand %{
10646     //
10647     // replaces
10648     //
10649     //   region  dst  crx  mem
10650     //    \       |    |   /
10651     //     dst=cmovI_bso_stackSlotL_conLvalue0
10652     //
10653     // with
10654     //
10655     //   region  dst
10656     //    \       /
10657     //     dst=loadConI16(0)
10658     //      |
10659     //      ^  region  dst  crx  mem
10660     //      |   \       |    |    /
10661     //      dst=cmovI_bso_stackSlotL
10662     //
10663 
10664     // Create new nodes.
10665     MachNode *m1 = new loadConI16Node();
10666     MachNode *m2 = new cmovI_bso_stackSlotLNode();
10667 
10668     // inputs for new nodes
10669     m1->add_req(n_region);
10670     m2->add_req(n_region, n_crx, n_mem);
10671 
10672     // precedences for new nodes
10673     m2->add_prec(m1);
10674 
10675     // operands for new nodes
10676     m1->_opnds[0] = op_dst;
10677     m1->_opnds[1] = new immI16Oper(0);
10678 
10679     m2->_opnds[0] = op_dst;
10680     m2->_opnds[1] = op_crx;
10681     m2->_opnds[2] = op_mem;
10682 
10683     // registers for new nodes
10684     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10685     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10686 
10687     // Insert new nodes.
10688     nodes->push(m1);
10689     nodes->push(m2);
10690   %}
10691 %}
10692 
10693 instruct cmovI_bso_reg_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, regD src) %{
10694   // no match-rule, false predicate
10695   effect(DEF dst, USE crx, USE src);
10696   predicate(false);
10697 
10698   format %{ "CmovI   $dst, $crx, $src \t// postalloc expanded" %}
10699   postalloc_expand %{
10700     //
10701     // replaces
10702     //
10703     //   region  dst  crx  src
10704     //    \       |    |   /
10705     //     dst=cmovI_bso_reg_conLvalue0
10706     //
10707     // with
10708     //
10709     //   region  dst
10710     //    \       /
10711     //     dst=loadConI16(0)
10712     //      |
10713     //      ^  region  dst  crx  src
10714     //      |   \       |    |    /
10715     //      dst=cmovI_bso_reg
10716     //
10717 
10718     // Create new nodes.
10719     MachNode *m1 = new loadConI16Node();
10720     MachNode *m2 = new cmovI_bso_regNode();
10721 
10722     // inputs for new nodes
10723     m1->add_req(n_region);
10724     m2->add_req(n_region, n_crx, n_src);
10725 
10726     // precedences for new nodes
10727     m2->add_prec(m1);
10728 
10729     // operands for new nodes
10730     m1->_opnds[0] = op_dst;
10731     m1->_opnds[1] = new immI16Oper(0);
10732 
10733     m2->_opnds[0] = op_dst;
10734     m2->_opnds[1] = op_crx;
10735     m2->_opnds[2] = op_src;
10736 
10737     // registers for new nodes
10738     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10739     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10740 
10741     // Insert new nodes.
10742     nodes->push(m1);
10743     nodes->push(m2);
10744   %}
10745 %}
10746 
10747 // Double to Int conversion, NaN is mapped to 0.
10748 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
10749   match(Set dst (ConvD2I src));
10750   predicate(!VM_Version::has_mtfprd());
10751   ins_cost(DEFAULT_COST);
10752 
10753   expand %{
10754     regD tmpD;
10755     stackSlotL tmpS;
10756     flagsReg crx;
10757     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10758     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10759     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10760     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10761   %}
10762 %}
10763 
10764 // Double to Int conversion, NaN is mapped to 0. Special version for Power8.
10765 instruct convD2I_reg_mffprd_ExEx(iRegIdst dst, regD src) %{
10766   match(Set dst (ConvD2I src));
10767   predicate(VM_Version::has_mtfprd());
10768   ins_cost(DEFAULT_COST);
10769 
10770   expand %{
10771     regD tmpD;
10772     flagsReg crx;
10773     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10774     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10775     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
10776   %}
10777 %}
10778 
10779 instruct convF2IRaw_regF(regF dst, regF src) %{
10780   // no match-rule, false predicate
10781   effect(DEF dst, USE src);
10782   predicate(false);
10783 
10784   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
10785   size(4);
10786   ins_encode %{
10787     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10788     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10789   %}
10790   ins_pipe(pipe_class_default);
10791 %}
10792 
10793 // Float to Int conversion, NaN is mapped to 0.
10794 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
10795   match(Set dst (ConvF2I src));
10796   predicate(!VM_Version::has_mtfprd());
10797   ins_cost(DEFAULT_COST);
10798 
10799   expand %{
10800     regF tmpF;
10801     stackSlotL tmpS;
10802     flagsReg crx;
10803     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10804     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10805     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10806     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10807   %}
10808 %}
10809 
10810 // Float to Int conversion, NaN is mapped to 0. Special version for Power8.
10811 instruct convF2I_regF_mffprd_ExEx(iRegIdst dst, regF src) %{
10812   match(Set dst (ConvF2I src));
10813   predicate(VM_Version::has_mtfprd());
10814   ins_cost(DEFAULT_COST);
10815 
10816   expand %{
10817     regF tmpF;
10818     flagsReg crx;
10819     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10820     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10821     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
10822   %}
10823 %}
10824 
10825 // Convert to Long
10826 
10827 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
10828   match(Set dst (ConvI2L src));
10829   format %{ "EXTSW   $dst, $src \t// int->long" %}
10830   size(4);
10831   ins_encode %{
10832     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10833     __ extsw($dst$$Register, $src$$Register);
10834   %}
10835   ins_pipe(pipe_class_default);
10836 %}
10837 
10838 // Zero-extend: convert unsigned int to long (convUI2L).
10839 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
10840   match(Set dst (AndL (ConvI2L src) mask));
10841   ins_cost(DEFAULT_COST);
10842 
10843   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10844   size(4);
10845   ins_encode %{
10846     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
10847     __ clrldi($dst$$Register, $src$$Register, 32);
10848   %}
10849   ins_pipe(pipe_class_default);
10850 %}
10851 
10852 // Zero-extend: convert unsigned int to long in long register.
10853 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
10854   match(Set dst (AndL src mask));
10855   ins_cost(DEFAULT_COST);
10856 
10857   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10858   size(4);
10859   ins_encode %{
10860     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
10861     __ clrldi($dst$$Register, $src$$Register, 32);
10862   %}
10863   ins_pipe(pipe_class_default);
10864 %}
10865 
10866 instruct convF2LRaw_regF(regF dst, regF src) %{
10867   // no match-rule, false predicate
10868   effect(DEF dst, USE src);
10869   predicate(false);
10870 
10871   format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
10872   size(4);
10873   ins_encode %{
10874     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10875     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10876   %}
10877   ins_pipe(pipe_class_default);
10878 %}
10879 
10880 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
10881   // no match-rule, false predicate
10882   effect(DEF dst, USE crx, USE src);
10883   predicate(false);
10884 
10885   ins_variable_size_depending_on_alignment(true);
10886 
10887   format %{ "cmovL   $crx, $dst, $src" %}
10888   // Worst case is branch + move + stop, no stop without scheduler.
10889   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10890   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10891   ins_pipe(pipe_class_default);
10892 %}
10893 
10894 instruct cmovL_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
10895   // no match-rule, false predicate
10896   effect(DEF dst, USE crx, USE src);
10897   predicate(false);
10898 
10899   ins_variable_size_depending_on_alignment(true);
10900 
10901   format %{ "cmovL   $crx, $dst, $src" %}
10902   // Worst case is branch + move + stop, no stop without scheduler.
10903   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10904   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10905   ins_pipe(pipe_class_default);
10906 %}
10907 
10908 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
10909   // no match-rule, false predicate
10910   effect(DEF dst, USE crx, USE mem);
10911   predicate(false);
10912 
10913   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
10914   postalloc_expand %{
10915     //
10916     // replaces
10917     //
10918     //   region  dst  crx  mem
10919     //    \       |    |   /
10920     //     dst=cmovL_bso_stackSlotL_conLvalue0
10921     //
10922     // with
10923     //
10924     //   region  dst
10925     //    \       /
10926     //     dst=loadConL16(0)
10927     //      |
10928     //      ^  region  dst  crx  mem
10929     //      |   \       |    |    /
10930     //      dst=cmovL_bso_stackSlotL
10931     //
10932 
10933     // Create new nodes.
10934     MachNode *m1 = new loadConL16Node();
10935     MachNode *m2 = new cmovL_bso_stackSlotLNode();
10936 
10937     // inputs for new nodes
10938     m1->add_req(n_region);
10939     m2->add_req(n_region, n_crx, n_mem);
10940     m2->add_prec(m1);
10941 
10942     // operands for new nodes
10943     m1->_opnds[0] = op_dst;
10944     m1->_opnds[1] = new immL16Oper(0);
10945     m2->_opnds[0] = op_dst;
10946     m2->_opnds[1] = op_crx;
10947     m2->_opnds[2] = op_mem;
10948 
10949     // registers for new nodes
10950     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10951     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10952 
10953     // Insert new nodes.
10954     nodes->push(m1);
10955     nodes->push(m2);
10956   %}
10957 %}
10958 
10959 instruct cmovL_bso_reg_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, regD src) %{
10960   // no match-rule, false predicate
10961   effect(DEF dst, USE crx, USE src);
10962   predicate(false);
10963 
10964   format %{ "CmovL   $dst, $crx, $src \t// postalloc expanded" %}
10965   postalloc_expand %{
10966     //
10967     // replaces
10968     //
10969     //   region  dst  crx  src
10970     //    \       |    |   /
10971     //     dst=cmovL_bso_reg_conLvalue0
10972     //
10973     // with
10974     //
10975     //   region  dst
10976     //    \       /
10977     //     dst=loadConL16(0)
10978     //      |
10979     //      ^  region  dst  crx  src
10980     //      |   \       |    |    /
10981     //      dst=cmovL_bso_reg
10982     //
10983 
10984     // Create new nodes.
10985     MachNode *m1 = new loadConL16Node();
10986     MachNode *m2 = new cmovL_bso_regNode();
10987 
10988     // inputs for new nodes
10989     m1->add_req(n_region);
10990     m2->add_req(n_region, n_crx, n_src);
10991     m2->add_prec(m1);
10992 
10993     // operands for new nodes
10994     m1->_opnds[0] = op_dst;
10995     m1->_opnds[1] = new immL16Oper(0);
10996     m2->_opnds[0] = op_dst;
10997     m2->_opnds[1] = op_crx;
10998     m2->_opnds[2] = op_src;
10999 
11000     // registers for new nodes
11001     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11002     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11003 
11004     // Insert new nodes.
11005     nodes->push(m1);
11006     nodes->push(m2);
11007   %}
11008 %}
11009 
11010 // Float to Long conversion, NaN is mapped to 0.
11011 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
11012   match(Set dst (ConvF2L src));
11013   predicate(!VM_Version::has_mtfprd());
11014   ins_cost(DEFAULT_COST);
11015 
11016   expand %{
11017     regF tmpF;
11018     stackSlotL tmpS;
11019     flagsReg crx;
11020     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11021     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11022     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
11023     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11024   %}
11025 %}
11026 
11027 // Float to Long conversion, NaN is mapped to 0. Special version for Power8.
11028 instruct convF2L_reg_mffprd_ExEx(iRegLdst dst, regF src) %{
11029   match(Set dst (ConvF2L src));
11030   predicate(VM_Version::has_mtfprd());
11031   ins_cost(DEFAULT_COST);
11032 
11033   expand %{
11034     regF tmpF;
11035     flagsReg crx;
11036     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11037     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11038     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
11039   %}
11040 %}
11041 
11042 instruct convD2LRaw_regD(regD dst, regD src) %{
11043   // no match-rule, false predicate
11044   effect(DEF dst, USE src);
11045   predicate(false);
11046 
11047   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
11048   size(4);
11049   ins_encode %{
11050     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
11051     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
11052   %}
11053   ins_pipe(pipe_class_default);
11054 %}
11055 
11056 // Double to Long conversion, NaN is mapped to 0.
11057 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
11058   match(Set dst (ConvD2L src));
11059   predicate(!VM_Version::has_mtfprd());
11060   ins_cost(DEFAULT_COST);
11061 
11062   expand %{
11063     regD tmpD;
11064     stackSlotL tmpS;
11065     flagsReg crx;
11066     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11067     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11068     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
11069     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11070   %}
11071 %}
11072 
11073 // Double to Long conversion, NaN is mapped to 0. Special version for Power8.
11074 instruct convD2L_reg_mffprd_ExEx(iRegLdst dst, regD src) %{
11075   match(Set dst (ConvD2L src));
11076   predicate(VM_Version::has_mtfprd());
11077   ins_cost(DEFAULT_COST);
11078 
11079   expand %{
11080     regD tmpD;
11081     flagsReg crx;
11082     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11083     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11084     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
11085   %}
11086 %}
11087 
11088 // Convert to Float
11089 
11090 // Placed here as needed in expand.
11091 instruct convL2DRaw_regD(regD dst, regD src) %{
11092   // no match-rule, false predicate
11093   effect(DEF dst, USE src);
11094   predicate(false);
11095 
11096   format %{ "FCFID $dst, $src \t// convL2D" %}
11097   size(4);
11098   ins_encode %{
11099     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11100     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
11101   %}
11102   ins_pipe(pipe_class_default);
11103 %}
11104 
11105 // Placed here as needed in expand.
11106 instruct convD2F_reg(regF dst, regD src) %{
11107   match(Set dst (ConvD2F src));
11108   format %{ "FRSP    $dst, $src \t// convD2F" %}
11109   size(4);
11110   ins_encode %{
11111     // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
11112     __ frsp($dst$$FloatRegister, $src$$FloatRegister);
11113   %}
11114   ins_pipe(pipe_class_default);
11115 %}
11116 
11117 // Integer to Float conversion.
11118 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
11119   match(Set dst (ConvI2F src));
11120   predicate(!VM_Version::has_fcfids());
11121   ins_cost(DEFAULT_COST);
11122 
11123   expand %{
11124     iRegLdst tmpL;
11125     stackSlotL tmpS;
11126     regD tmpD;
11127     regD tmpD2;
11128     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11129     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11130     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11131     convL2DRaw_regD(tmpD2, tmpD);        // Convert to double.
11132     convD2F_reg(dst, tmpD2);             // Convert double to float.
11133   %}
11134 %}
11135 
11136 instruct convL2FRaw_regF(regF dst, regD src) %{
11137   // no match-rule, false predicate
11138   effect(DEF dst, USE src);
11139   predicate(false);
11140 
11141   format %{ "FCFIDS $dst, $src \t// convL2F" %}
11142   size(4);
11143   ins_encode %{
11144     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11145     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
11146   %}
11147   ins_pipe(pipe_class_default);
11148 %}
11149 
11150 // Integer to Float conversion. Special version for Power7.
11151 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
11152   match(Set dst (ConvI2F src));
11153   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11154   ins_cost(DEFAULT_COST);
11155 
11156   expand %{
11157     iRegLdst tmpL;
11158     stackSlotL tmpS;
11159     regD tmpD;
11160     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11161     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11162     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11163     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11164   %}
11165 %}
11166 
11167 // Integer to Float conversion. Special version for Power8.
11168 instruct convI2F_ireg_mtfprd_Ex(regF dst, iRegIsrc src) %{
11169   match(Set dst (ConvI2F src));
11170   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11171   ins_cost(DEFAULT_COST);
11172 
11173   expand %{
11174     regD tmpD;
11175     moveI2D_reg(tmpD, src);
11176     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11177   %}
11178 %}
11179 
11180 // L2F to avoid runtime call.
11181 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
11182   match(Set dst (ConvL2F src));
11183   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11184   ins_cost(DEFAULT_COST);
11185 
11186   expand %{
11187     stackSlotL tmpS;
11188     regD tmpD;
11189     regL_to_stkL(tmpS, src);             // Store long to stack.
11190     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11191     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11192   %}
11193 %}
11194 
11195 // L2F to avoid runtime call.  Special version for Power8.
11196 instruct convL2F_ireg_mtfprd_Ex(regF dst, iRegLsrc src) %{
11197   match(Set dst (ConvL2F src));
11198   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11199   ins_cost(DEFAULT_COST);
11200 
11201   expand %{
11202     regD tmpD;
11203     moveL2D_reg(tmpD, src);
11204     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11205   %}
11206 %}
11207 
11208 // Moved up as used in expand.
11209 //instruct convD2F_reg(regF dst, regD src) %{%}
11210 
11211 // Convert to Double
11212 
11213 // Integer to Double conversion.
11214 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
11215   match(Set dst (ConvI2D src));
11216   predicate(!VM_Version::has_mtfprd());
11217   ins_cost(DEFAULT_COST);
11218 
11219   expand %{
11220     iRegLdst tmpL;
11221     stackSlotL tmpS;
11222     regD tmpD;
11223     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11224     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11225     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11226     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11227   %}
11228 %}
11229 
11230 // Integer to Double conversion. Special version for Power8.
11231 instruct convI2D_reg_mtfprd_Ex(regD dst, iRegIsrc src) %{
11232   match(Set dst (ConvI2D src));
11233   predicate(VM_Version::has_mtfprd());
11234   ins_cost(DEFAULT_COST);
11235 
11236   expand %{
11237     regD tmpD;
11238     moveI2D_reg(tmpD, src);
11239     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11240   %}
11241 %}
11242 
11243 // Long to Double conversion
11244 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
11245   match(Set dst (ConvL2D src));
11246   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
11247 
11248   expand %{
11249     regD tmpD;
11250     moveL2D_stack_reg(tmpD, src);
11251     convL2DRaw_regD(dst, tmpD);
11252   %}
11253 %}
11254 
11255 // Long to Double conversion. Special version for Power8.
11256 instruct convL2D_reg_mtfprd_Ex(regD dst, iRegLsrc src) %{
11257   match(Set dst (ConvL2D src));
11258   predicate(VM_Version::has_mtfprd());
11259   ins_cost(DEFAULT_COST);
11260 
11261   expand %{
11262     regD tmpD;
11263     moveL2D_reg(tmpD, src);
11264     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11265   %}
11266 %}
11267 
11268 instruct convF2D_reg(regD dst, regF src) %{
11269   match(Set dst (ConvF2D src));
11270   format %{ "FMR     $dst, $src \t// float->double" %}
11271   // variable size, 0 or 4
11272   ins_encode %{
11273     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11274     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
11275   %}
11276   ins_pipe(pipe_class_default);
11277 %}
11278 
11279 //----------Control Flow Instructions------------------------------------------
11280 // Compare Instructions
11281 
11282 // Compare Integers
11283 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11284   match(Set crx (CmpI src1 src2));
11285   size(4);
11286   format %{ "CMPW    $crx, $src1, $src2" %}
11287   ins_encode %{
11288     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
11289     __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
11290   %}
11291   ins_pipe(pipe_class_compare);
11292 %}
11293 
11294 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
11295   match(Set crx (CmpI src1 src2));
11296   format %{ "CMPWI   $crx, $src1, $src2" %}
11297   size(4);
11298   ins_encode %{
11299     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11300     __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11301   %}
11302   ins_pipe(pipe_class_compare);
11303 %}
11304 
11305 // (src1 & src2) == 0?
11306 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
11307   match(Set cr0 (CmpI (AndI src1 src2) zero));
11308   // r0 is killed
11309   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
11310   size(4);
11311   ins_encode %{
11312     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
11313     __ andi_(R0, $src1$$Register, $src2$$constant);
11314   %}
11315   ins_pipe(pipe_class_compare);
11316 %}
11317 
11318 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
11319   match(Set crx (CmpL src1 src2));
11320   format %{ "CMPD    $crx, $src1, $src2" %}
11321   size(4);
11322   ins_encode %{
11323     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
11324     __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
11325   %}
11326   ins_pipe(pipe_class_compare);
11327 %}
11328 
11329 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
11330   match(Set crx (CmpL src1 src2));
11331   format %{ "CMPDI   $crx, $src1, $src2" %}
11332   size(4);
11333   ins_encode %{
11334     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11335     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11336   %}
11337   ins_pipe(pipe_class_compare);
11338 %}
11339 
11340 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
11341   match(Set cr0 (CmpL (AndL src1 src2) zero));
11342   // r0 is killed
11343   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
11344   size(4);
11345   ins_encode %{
11346     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
11347     __ and_(R0, $src1$$Register, $src2$$Register);
11348   %}
11349   ins_pipe(pipe_class_compare);
11350 %}
11351 
11352 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
11353   match(Set cr0 (CmpL (AndL src1 src2) zero));
11354   // r0 is killed
11355   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
11356   size(4);
11357   ins_encode %{
11358     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
11359     __ andi_(R0, $src1$$Register, $src2$$constant);
11360   %}
11361   ins_pipe(pipe_class_compare);
11362 %}
11363 
11364 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
11365   // no match-rule, false predicate
11366   effect(DEF dst, USE crx);
11367   predicate(false);
11368 
11369   ins_variable_size_depending_on_alignment(true);
11370 
11371   format %{ "cmovI   $crx, $dst, -1, 0, +1" %}
11372   // Worst case is branch + move + branch + move + stop, no stop without scheduler.
11373   size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
11374   ins_encode %{
11375     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
11376     Label done;
11377     // li(Rdst, 0);              // equal -> 0
11378     __ beq($crx$$CondRegister, done);
11379     __ li($dst$$Register, 1);    // greater -> +1
11380     __ bgt($crx$$CondRegister, done);
11381     __ li($dst$$Register, -1);   // unordered or less -> -1
11382     // TODO: PPC port__ endgroup_if_needed(_size == 20);
11383     __ bind(done);
11384   %}
11385   ins_pipe(pipe_class_compare);
11386 %}
11387 
11388 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
11389   // no match-rule, false predicate
11390   effect(DEF dst, USE crx);
11391   predicate(false);
11392 
11393   format %{ "CmovI    $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
11394   postalloc_expand %{
11395     //
11396     // replaces
11397     //
11398     //   region  crx
11399     //    \       |
11400     //     dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
11401     //
11402     // with
11403     //
11404     //   region
11405     //    \
11406     //     dst=loadConI16(0)
11407     //      |
11408     //      ^  region  crx
11409     //      |   \       |
11410     //      dst=cmovI_conIvalueMinus1_conIvalue1
11411     //
11412 
11413     // Create new nodes.
11414     MachNode *m1 = new loadConI16Node();
11415     MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
11416 
11417     // inputs for new nodes
11418     m1->add_req(n_region);
11419     m2->add_req(n_region, n_crx);
11420     m2->add_prec(m1);
11421 
11422     // operands for new nodes
11423     m1->_opnds[0] = op_dst;
11424     m1->_opnds[1] = new immI16Oper(0);
11425     m2->_opnds[0] = op_dst;
11426     m2->_opnds[1] = op_crx;
11427 
11428     // registers for new nodes
11429     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11430     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11431 
11432     // Insert new nodes.
11433     nodes->push(m1);
11434     nodes->push(m2);
11435   %}
11436 %}
11437 
11438 // Manifest a CmpL3 result in an integer register. Very painful.
11439 // This is the test to avoid.
11440 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
11441 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
11442   match(Set dst (CmpL3 src1 src2));
11443   ins_cost(DEFAULT_COST*5+BRANCH_COST);
11444 
11445   expand %{
11446     flagsReg tmp1;
11447     cmpL_reg_reg(tmp1, src1, src2);
11448     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
11449   %}
11450 %}
11451 
11452 // Implicit range checks.
11453 // A range check in the ideal world has one of the following shapes:
11454 //  - (If le (CmpU length index)), (IfTrue  throw exception)
11455 //  - (If lt (CmpU index length)), (IfFalse throw exception)
11456 //
11457 // Match range check 'If le (CmpU length index)'.
11458 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
11459   match(If cmp (CmpU src_length index));
11460   effect(USE labl);
11461   predicate(TrapBasedRangeChecks &&
11462             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
11463             PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
11464             (Matcher::branches_to_uncommon_trap(_leaf)));
11465 
11466   ins_is_TrapBasedCheckNode(true);
11467 
11468   format %{ "TWI     $index $cmp $src_length \t// RangeCheck => trap $labl" %}
11469   size(4);
11470   ins_encode %{
11471     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
11472     if ($cmp$$cmpcode == 0x1 /* less_equal */) {
11473       __ trap_range_check_le($src_length$$Register, $index$$constant);
11474     } else {
11475       // Both successors are uncommon traps, probability is 0.
11476       // Node got flipped during fixup flow.
11477       assert($cmp$$cmpcode == 0x9, "must be greater");
11478       __ trap_range_check_g($src_length$$Register, $index$$constant);
11479     }
11480   %}
11481   ins_pipe(pipe_class_trap);
11482 %}
11483 
11484 // Match range check 'If lt (CmpU index length)'.
11485 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
11486   match(If cmp (CmpU src_index src_length));
11487   effect(USE labl);
11488   predicate(TrapBasedRangeChecks &&
11489             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
11490             _leaf->as_If()->_prob >= PROB_ALWAYS &&
11491             (Matcher::branches_to_uncommon_trap(_leaf)));
11492 
11493   ins_is_TrapBasedCheckNode(true);
11494 
11495   format %{ "TW      $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
11496   size(4);
11497   ins_encode %{
11498     // TODO: PPC port $archOpcode(ppc64Opcode_tw);
11499     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
11500       __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
11501     } else {
11502       // Both successors are uncommon traps, probability is 0.
11503       // Node got flipped during fixup flow.
11504       assert($cmp$$cmpcode == 0x8, "must be less");
11505       __ trap_range_check_l($src_index$$Register, $src_length$$Register);
11506     }
11507   %}
11508   ins_pipe(pipe_class_trap);
11509 %}
11510 
11511 // Match range check 'If lt (CmpU index length)'.
11512 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
11513   match(If cmp (CmpU src_index length));
11514   effect(USE labl);
11515   predicate(TrapBasedRangeChecks &&
11516             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
11517             _leaf->as_If()->_prob >= PROB_ALWAYS &&
11518             (Matcher::branches_to_uncommon_trap(_leaf)));
11519 
11520   ins_is_TrapBasedCheckNode(true);
11521 
11522   format %{ "TWI     $src_index $cmp $length \t// RangeCheck => trap $labl" %}
11523   size(4);
11524   ins_encode %{
11525     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
11526     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
11527       __ trap_range_check_ge($src_index$$Register, $length$$constant);
11528     } else {
11529       // Both successors are uncommon traps, probability is 0.
11530       // Node got flipped during fixup flow.
11531       assert($cmp$$cmpcode == 0x8, "must be less");
11532       __ trap_range_check_l($src_index$$Register, $length$$constant);
11533     }
11534   %}
11535   ins_pipe(pipe_class_trap);
11536 %}
11537 
11538 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11539   match(Set crx (CmpU src1 src2));
11540   format %{ "CMPLW   $crx, $src1, $src2 \t// unsigned" %}
11541   size(4);
11542   ins_encode %{
11543     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11544     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
11545   %}
11546   ins_pipe(pipe_class_compare);
11547 %}
11548 
11549 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
11550   match(Set crx (CmpU src1 src2));
11551   size(4);
11552   format %{ "CMPLWI  $crx, $src1, $src2" %}
11553   ins_encode %{
11554     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
11555     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11556   %}
11557   ins_pipe(pipe_class_compare);
11558 %}
11559 
11560 // Implicit zero checks (more implicit null checks).
11561 // No constant pool entries required.
11562 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
11563   match(If cmp (CmpN value zero));
11564   effect(USE labl);
11565   predicate(TrapBasedNullChecks &&
11566             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
11567             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
11568             Matcher::branches_to_uncommon_trap(_leaf));
11569   ins_cost(1);
11570 
11571   ins_is_TrapBasedCheckNode(true);
11572 
11573   format %{ "TDI     $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
11574   size(4);
11575   ins_encode %{
11576     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11577     if ($cmp$$cmpcode == 0xA) {
11578       __ trap_null_check($value$$Register);
11579     } else {
11580       // Both successors are uncommon traps, probability is 0.
11581       // Node got flipped during fixup flow.
11582       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
11583       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
11584     }
11585   %}
11586   ins_pipe(pipe_class_trap);
11587 %}
11588 
11589 // Compare narrow oops.
11590 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
11591   match(Set crx (CmpN src1 src2));
11592 
11593   size(4);
11594   ins_cost(2);
11595   format %{ "CMPLW   $crx, $src1, $src2 \t// compressed ptr" %}
11596   ins_encode %{
11597     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11598     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
11599   %}
11600   ins_pipe(pipe_class_compare);
11601 %}
11602 
11603 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
11604   match(Set crx (CmpN src1 src2));
11605   // Make this more expensive than zeroCheckN_iReg_imm0.
11606   ins_cost(2);
11607 
11608   format %{ "CMPLWI  $crx, $src1, $src2 \t// compressed ptr" %}
11609   size(4);
11610   ins_encode %{
11611     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
11612     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11613   %}
11614   ins_pipe(pipe_class_compare);
11615 %}
11616 
11617 // Implicit zero checks (more implicit null checks).
11618 // No constant pool entries required.
11619 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
11620   match(If cmp (CmpP value zero));
11621   effect(USE labl);
11622   predicate(TrapBasedNullChecks &&
11623             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
11624             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
11625             Matcher::branches_to_uncommon_trap(_leaf));
11626   ins_cost(1); // Should not be cheaper than zeroCheckN.
11627 
11628   ins_is_TrapBasedCheckNode(true);
11629 
11630   format %{ "TDI     $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
11631   size(4);
11632   ins_encode %{
11633     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11634     if ($cmp$$cmpcode == 0xA) {
11635       __ trap_null_check($value$$Register);
11636     } else {
11637       // Both successors are uncommon traps, probability is 0.
11638       // Node got flipped during fixup flow.
11639       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
11640       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
11641     }
11642   %}
11643   ins_pipe(pipe_class_trap);
11644 %}
11645 
11646 // Compare Pointers
11647 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
11648   match(Set crx (CmpP src1 src2));
11649   format %{ "CMPLD   $crx, $src1, $src2 \t// ptr" %}
11650   size(4);
11651   ins_encode %{
11652     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11653     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
11654   %}
11655   ins_pipe(pipe_class_compare);
11656 %}
11657 
11658 instruct cmpP_reg_null(flagsReg crx, iRegP_N2P src1, immP_0or1 src2) %{
11659   match(Set crx (CmpP src1 src2));
11660   format %{ "CMPLDI   $crx, $src1, $src2 \t// ptr" %}
11661   size(4);
11662   ins_encode %{
11663     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11664     __ cmpldi($crx$$CondRegister, $src1$$Register, (int)((short)($src2$$constant & 0xFFFF)));
11665   %}
11666   ins_pipe(pipe_class_compare);
11667 %}
11668 
11669 // Used in postalloc expand.
11670 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
11671   // This match rule prevents reordering of node before a safepoint.
11672   // This only makes sense if this instructions is used exclusively
11673   // for the expansion of EncodeP!
11674   match(Set crx (CmpP src1 src2));
11675   predicate(false);
11676 
11677   format %{ "CMPDI   $crx, $src1, $src2" %}
11678   size(4);
11679   ins_encode %{
11680     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11681     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11682   %}
11683   ins_pipe(pipe_class_compare);
11684 %}
11685 
11686 //----------Float Compares----------------------------------------------------
11687 
11688 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
11689   // Needs matchrule, see cmpDUnordered.
11690   match(Set crx (CmpF src1 src2));
11691   // no match-rule, false predicate
11692   predicate(false);
11693 
11694   format %{ "cmpFUrd $crx, $src1, $src2" %}
11695   size(4);
11696   ins_encode %{
11697     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
11698     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
11699   %}
11700   ins_pipe(pipe_class_default);
11701 %}
11702 
11703 instruct cmov_bns_less(flagsReg crx) %{
11704   // no match-rule, false predicate
11705   effect(DEF crx);
11706   predicate(false);
11707 
11708   ins_variable_size_depending_on_alignment(true);
11709 
11710   format %{ "cmov    $crx" %}
11711   // Worst case is branch + move + stop, no stop without scheduler.
11712   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
11713   ins_encode %{
11714     // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
11715     Label done;
11716     __ bns($crx$$CondRegister, done);        // not unordered -> keep crx
11717     __ li(R0, 0);
11718     __ cmpwi($crx$$CondRegister, R0, 1);     // unordered -> set crx to 'less'
11719     // TODO PPC port __ endgroup_if_needed(_size == 16);
11720     __ bind(done);
11721   %}
11722   ins_pipe(pipe_class_default);
11723 %}
11724 
11725 // Compare floating, generate condition code.
11726 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
11727   // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
11728   //
11729   // The following code sequence occurs a lot in mpegaudio:
11730   //
11731   // block BXX:
11732   // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
11733   //    cmpFUrd CCR6, F11, F9
11734   // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
11735   //    cmov CCR6
11736   // 8: instruct branchConSched:
11737   //    B_FARle CCR6, B56  P=0.500000 C=-1.000000
11738   match(Set crx (CmpF src1 src2));
11739   ins_cost(DEFAULT_COST+BRANCH_COST);
11740 
11741   format %{ "CmpF    $crx, $src1, $src2 \t// postalloc expanded" %}
11742   postalloc_expand %{
11743     //
11744     // replaces
11745     //
11746     //   region  src1  src2
11747     //    \       |     |
11748     //     crx=cmpF_reg_reg
11749     //
11750     // with
11751     //
11752     //   region  src1  src2
11753     //    \       |     |
11754     //     crx=cmpFUnordered_reg_reg
11755     //      |
11756     //      ^  region
11757     //      |   \
11758     //      crx=cmov_bns_less
11759     //
11760 
11761     // Create new nodes.
11762     MachNode *m1 = new cmpFUnordered_reg_regNode();
11763     MachNode *m2 = new cmov_bns_lessNode();
11764 
11765     // inputs for new nodes
11766     m1->add_req(n_region, n_src1, n_src2);
11767     m2->add_req(n_region);
11768     m2->add_prec(m1);
11769 
11770     // operands for new nodes
11771     m1->_opnds[0] = op_crx;
11772     m1->_opnds[1] = op_src1;
11773     m1->_opnds[2] = op_src2;
11774     m2->_opnds[0] = op_crx;
11775 
11776     // registers for new nodes
11777     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11778     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11779 
11780     // Insert new nodes.
11781     nodes->push(m1);
11782     nodes->push(m2);
11783   %}
11784 %}
11785 
11786 // Compare float, generate -1,0,1
11787 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
11788   match(Set dst (CmpF3 src1 src2));
11789   ins_cost(DEFAULT_COST*5+BRANCH_COST);
11790 
11791   expand %{
11792     flagsReg tmp1;
11793     cmpFUnordered_reg_reg(tmp1, src1, src2);
11794     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
11795   %}
11796 %}
11797 
11798 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
11799   // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
11800   // node right before the conditional move using it.
11801   // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
11802   // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
11803   // crashed in register allocation where the flags Reg between cmpDUnoredered and a
11804   // conditional move was supposed to be spilled.
11805   match(Set crx (CmpD src1 src2));
11806   // False predicate, shall not be matched.
11807   predicate(false);
11808 
11809   format %{ "cmpFUrd $crx, $src1, $src2" %}
11810   size(4);
11811   ins_encode %{
11812     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
11813     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
11814   %}
11815   ins_pipe(pipe_class_default);
11816 %}
11817 
11818 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
11819   match(Set crx (CmpD src1 src2));
11820   ins_cost(DEFAULT_COST+BRANCH_COST);
11821 
11822   format %{ "CmpD    $crx, $src1, $src2 \t// postalloc expanded" %}
11823   postalloc_expand %{
11824     //
11825     // replaces
11826     //
11827     //   region  src1  src2
11828     //    \       |     |
11829     //     crx=cmpD_reg_reg
11830     //
11831     // with
11832     //
11833     //   region  src1  src2
11834     //    \       |     |
11835     //     crx=cmpDUnordered_reg_reg
11836     //      |
11837     //      ^  region
11838     //      |   \
11839     //      crx=cmov_bns_less
11840     //
11841 
11842     // create new nodes
11843     MachNode *m1 = new cmpDUnordered_reg_regNode();
11844     MachNode *m2 = new cmov_bns_lessNode();
11845 
11846     // inputs for new nodes
11847     m1->add_req(n_region, n_src1, n_src2);
11848     m2->add_req(n_region);
11849     m2->add_prec(m1);
11850 
11851     // operands for new nodes
11852     m1->_opnds[0] = op_crx;
11853     m1->_opnds[1] = op_src1;
11854     m1->_opnds[2] = op_src2;
11855     m2->_opnds[0] = op_crx;
11856 
11857     // registers for new nodes
11858     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11859     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11860 
11861     // Insert new nodes.
11862     nodes->push(m1);
11863     nodes->push(m2);
11864   %}
11865 %}
11866 
11867 // Compare double, generate -1,0,1
11868 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
11869   match(Set dst (CmpD3 src1 src2));
11870   ins_cost(DEFAULT_COST*5+BRANCH_COST);
11871 
11872   expand %{
11873     flagsReg tmp1;
11874     cmpDUnordered_reg_reg(tmp1, src1, src2);
11875     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
11876   %}
11877 %}
11878 
11879 //----------Branches---------------------------------------------------------
11880 // Jump
11881 
11882 // Direct Branch.
11883 instruct branch(label labl) %{
11884   match(Goto);
11885   effect(USE labl);
11886   ins_cost(BRANCH_COST);
11887 
11888   format %{ "B       $labl" %}
11889   size(4);
11890   ins_encode %{
11891     // TODO: PPC port $archOpcode(ppc64Opcode_b);
11892      Label d;    // dummy
11893      __ bind(d);
11894      Label* p = $labl$$label;
11895      // `p' is `NULL' when this encoding class is used only to
11896      // determine the size of the encoded instruction.
11897      Label& l = (NULL == p)? d : *(p);
11898      __ b(l);
11899   %}
11900   ins_pipe(pipe_class_default);
11901 %}
11902 
11903 // Conditional Near Branch
11904 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
11905   // Same match rule as `branchConFar'.
11906   match(If cmp crx);
11907   effect(USE lbl);
11908   ins_cost(BRANCH_COST);
11909 
11910   // If set to 1 this indicates that the current instruction is a
11911   // short variant of a long branch. This avoids using this
11912   // instruction in first-pass matching. It will then only be used in
11913   // the `Shorten_branches' pass.
11914   ins_short_branch(1);
11915 
11916   format %{ "B$cmp     $crx, $lbl" %}
11917   size(4);
11918   ins_encode( enc_bc(crx, cmp, lbl) );
11919   ins_pipe(pipe_class_default);
11920 %}
11921 
11922 // This is for cases when the ppc64 `bc' instruction does not
11923 // reach far enough. So we emit a far branch here, which is more
11924 // expensive.
11925 //
11926 // Conditional Far Branch
11927 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
11928   // Same match rule as `branchCon'.
11929   match(If cmp crx);
11930   effect(USE crx, USE lbl);
11931   predicate(!false /* TODO: PPC port HB_Schedule*/);
11932   // Higher cost than `branchCon'.
11933   ins_cost(5*BRANCH_COST);
11934 
11935   // This is not a short variant of a branch, but the long variant.
11936   ins_short_branch(0);
11937 
11938   format %{ "B_FAR$cmp $crx, $lbl" %}
11939   size(8);
11940   ins_encode( enc_bc_far(crx, cmp, lbl) );
11941   ins_pipe(pipe_class_default);
11942 %}
11943 
11944 // Conditional Branch used with Power6 scheduler (can be far or short).
11945 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
11946   // Same match rule as `branchCon'.
11947   match(If cmp crx);
11948   effect(USE crx, USE lbl);
11949   predicate(false /* TODO: PPC port HB_Schedule*/);
11950   // Higher cost than `branchCon'.
11951   ins_cost(5*BRANCH_COST);
11952 
11953   // Actually size doesn't depend on alignment but on shortening.
11954   ins_variable_size_depending_on_alignment(true);
11955   // long variant.
11956   ins_short_branch(0);
11957 
11958   format %{ "B_FAR$cmp $crx, $lbl" %}
11959   size(8); // worst case
11960   ins_encode( enc_bc_short_far(crx, cmp, lbl) );
11961   ins_pipe(pipe_class_default);
11962 %}
11963 
11964 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
11965   match(CountedLoopEnd cmp crx);
11966   effect(USE labl);
11967   ins_cost(BRANCH_COST);
11968 
11969   // short variant.
11970   ins_short_branch(1);
11971 
11972   format %{ "B$cmp     $crx, $labl \t// counted loop end" %}
11973   size(4);
11974   ins_encode( enc_bc(crx, cmp, labl) );
11975   ins_pipe(pipe_class_default);
11976 %}
11977 
11978 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
11979   match(CountedLoopEnd cmp crx);
11980   effect(USE labl);
11981   predicate(!false /* TODO: PPC port HB_Schedule */);
11982   ins_cost(BRANCH_COST);
11983 
11984   // Long variant.
11985   ins_short_branch(0);
11986 
11987   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
11988   size(8);
11989   ins_encode( enc_bc_far(crx, cmp, labl) );
11990   ins_pipe(pipe_class_default);
11991 %}
11992 
11993 // Conditional Branch used with Power6 scheduler (can be far or short).
11994 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
11995   match(CountedLoopEnd cmp crx);
11996   effect(USE labl);
11997   predicate(false /* TODO: PPC port HB_Schedule */);
11998   // Higher cost than `branchCon'.
11999   ins_cost(5*BRANCH_COST);
12000 
12001   // Actually size doesn't depend on alignment but on shortening.
12002   ins_variable_size_depending_on_alignment(true);
12003   // Long variant.
12004   ins_short_branch(0);
12005 
12006   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
12007   size(8); // worst case
12008   ins_encode( enc_bc_short_far(crx, cmp, labl) );
12009   ins_pipe(pipe_class_default);
12010 %}
12011 
12012 // ============================================================================
12013 // Java runtime operations, intrinsics and other complex operations.
12014 
12015 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12016 // array for an instance of the superklass. Set a hidden internal cache on a
12017 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12018 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
12019 //
12020 // GL TODO: Improve this.
12021 // - result should not be a TEMP
12022 // - Add match rule as on sparc avoiding additional Cmp.
12023 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
12024                              iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
12025   match(Set result (PartialSubtypeCheck subklass superklass));
12026   effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
12027   ins_cost(DEFAULT_COST*10);
12028 
12029   format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
12030   ins_encode %{
12031     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12032     __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
12033                                      $tmp_klass$$Register, NULL, $result$$Register);
12034   %}
12035   ins_pipe(pipe_class_default);
12036 %}
12037 
12038 // inlined locking and unlocking
12039 
12040 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{
12041   match(Set crx (FastLock oop box));
12042   effect(TEMP tmp1, TEMP tmp2);
12043   predicate(!Compile::current()->use_rtm());
12044 
12045   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2" %}
12046   ins_encode %{
12047     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12048     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12049                                  $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0,
12050                                  UseBiasedLocking && !UseOptoBiasInlining);
12051     // If locking was successfull, crx should indicate 'EQ'.
12052     // The compiler generates a branch to the runtime call to
12053     // _complete_monitor_locking_Java for the case where crx is 'NE'.
12054   %}
12055   ins_pipe(pipe_class_compare);
12056 %}
12057 
12058 // Separate version for TM. Use bound register for box to enable USE_KILL.
12059 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12060   match(Set crx (FastLock oop box));
12061   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
12062   predicate(Compile::current()->use_rtm());
12063 
12064   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
12065   ins_encode %{
12066     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12067     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12068                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12069                                  /*Biased Locking*/ false,
12070                                  _rtm_counters, _stack_rtm_counters,
12071                                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12072                                  /*TM*/ true, ra_->C->profile_rtm());
12073     // If locking was successfull, crx should indicate 'EQ'.
12074     // The compiler generates a branch to the runtime call to
12075     // _complete_monitor_locking_Java for the case where crx is 'NE'.
12076   %}
12077   ins_pipe(pipe_class_compare);
12078 %}
12079 
12080 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12081   match(Set crx (FastUnlock oop box));
12082   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
12083   predicate(!Compile::current()->use_rtm());
12084 
12085   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2" %}
12086   ins_encode %{
12087     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12088     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12089                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12090                                    UseBiasedLocking && !UseOptoBiasInlining,
12091                                    false);
12092     // If unlocking was successfull, crx should indicate 'EQ'.
12093     // The compiler generates a branch to the runtime call to
12094     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
12095   %}
12096   ins_pipe(pipe_class_compare);
12097 %}
12098 
12099 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12100   match(Set crx (FastUnlock oop box));
12101   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
12102   predicate(Compile::current()->use_rtm());
12103 
12104   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2 (TM)" %}
12105   ins_encode %{
12106     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12107     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12108                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12109                                    /*Biased Locking*/ false, /*TM*/ true);
12110     // If unlocking was successfull, crx should indicate 'EQ'.
12111     // The compiler generates a branch to the runtime call to
12112     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
12113   %}
12114   ins_pipe(pipe_class_compare);
12115 %}
12116 
12117 // Align address.
12118 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
12119   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
12120 
12121   format %{ "ANDDI   $dst, $src, $mask \t// next aligned address" %}
12122   size(4);
12123   ins_encode %{
12124     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
12125     __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
12126   %}
12127   ins_pipe(pipe_class_default);
12128 %}
12129 
12130 // Array size computation.
12131 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
12132   match(Set dst (SubL (CastP2X end) (CastP2X start)));
12133 
12134   format %{ "SUB     $dst, $end, $start \t// array size in bytes" %}
12135   size(4);
12136   ins_encode %{
12137     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
12138     __ subf($dst$$Register, $start$$Register, $end$$Register);
12139   %}
12140   ins_pipe(pipe_class_default);
12141 %}
12142 
12143 // Clear-array with constant short array length. The versions below can use dcbz with cnt > 30.
12144 instruct inlineCallClearArrayShort(immLmax30 cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
12145   match(Set dummy (ClearArray cnt base));
12146   effect(USE_KILL base, KILL ctr);
12147   ins_cost(2 * MEMORY_REF_COST);
12148 
12149   format %{ "ClearArray $cnt, $base" %}
12150   ins_encode %{
12151     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12152     __ clear_memory_constlen($base$$Register, $cnt$$constant, R0); // kills base, R0
12153   %}
12154   ins_pipe(pipe_class_default);
12155 %}
12156 
12157 // Clear-array with constant large array length.
12158 instruct inlineCallClearArrayLarge(immL cnt, rarg2RegP base, Universe dummy, iRegLdst tmp, regCTR ctr) %{
12159   match(Set dummy (ClearArray cnt base));
12160   effect(USE_KILL base, TEMP tmp, KILL ctr);
12161   ins_cost(3 * MEMORY_REF_COST);
12162 
12163   format %{ "ClearArray $cnt, $base \t// KILL $tmp" %}
12164   ins_encode %{
12165     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12166     __ clear_memory_doubleword($base$$Register, $tmp$$Register, R0, $cnt$$constant); // kills base, R0
12167   %}
12168   ins_pipe(pipe_class_default);
12169 %}
12170 
12171 // Clear-array with dynamic array length.
12172 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
12173   match(Set dummy (ClearArray cnt base));
12174   effect(USE_KILL cnt, USE_KILL base, KILL ctr);
12175   ins_cost(4 * MEMORY_REF_COST);
12176 
12177   format %{ "ClearArray $cnt, $base" %}
12178   ins_encode %{
12179     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12180     __ clear_memory_doubleword($base$$Register, $cnt$$Register, R0); // kills cnt, base, R0
12181   %}
12182   ins_pipe(pipe_class_default);
12183 %}
12184 
12185 instruct string_compareL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12186                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12187   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12188   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12189   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12190   ins_cost(300);
12191   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12192   ins_encode %{
12193     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12194     __ string_compare($str1$$Register, $str2$$Register,
12195                       $cnt1$$Register, $cnt2$$Register,
12196                       $tmp$$Register,
12197                       $result$$Register, StrIntrinsicNode::LL);
12198   %}
12199   ins_pipe(pipe_class_default);
12200 %}
12201 
12202 instruct string_compareU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12203                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12204   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12205   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12206   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12207   ins_cost(300);
12208   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12209   ins_encode %{
12210     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12211     __ string_compare($str1$$Register, $str2$$Register,
12212                       $cnt1$$Register, $cnt2$$Register,
12213                       $tmp$$Register,
12214                       $result$$Register, StrIntrinsicNode::UU);
12215   %}
12216   ins_pipe(pipe_class_default);
12217 %}
12218 
12219 instruct string_compareLU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12220                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12221   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12222   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12223   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12224   ins_cost(300);
12225   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12226   ins_encode %{
12227     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12228     __ string_compare($str1$$Register, $str2$$Register,
12229                       $cnt1$$Register, $cnt2$$Register,
12230                       $tmp$$Register,
12231                       $result$$Register, StrIntrinsicNode::LU);
12232   %}
12233   ins_pipe(pipe_class_default);
12234 %}
12235 
12236 instruct string_compareUL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12237                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12238   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12239   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12240   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12241   ins_cost(300);
12242   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12243   ins_encode %{
12244     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12245     __ string_compare($str2$$Register, $str1$$Register,
12246                       $cnt2$$Register, $cnt1$$Register,
12247                       $tmp$$Register,
12248                       $result$$Register, StrIntrinsicNode::UL);
12249   %}
12250   ins_pipe(pipe_class_default);
12251 %}
12252 
12253 instruct string_equalsL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
12254                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12255   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
12256   match(Set result (StrEquals (Binary str1 str2) cnt));
12257   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
12258   ins_cost(300);
12259   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
12260   ins_encode %{
12261     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12262     __ array_equals(false, $str1$$Register, $str2$$Register,
12263                     $cnt$$Register, $tmp$$Register,
12264                     $result$$Register, true /* byte */);
12265   %}
12266   ins_pipe(pipe_class_default);
12267 %}
12268 
12269 instruct string_equalsU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
12270                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12271   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
12272   match(Set result (StrEquals (Binary str1 str2) cnt));
12273   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
12274   ins_cost(300);
12275   format %{ "String Equals char[]  $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
12276   ins_encode %{
12277     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12278     __ array_equals(false, $str1$$Register, $str2$$Register,
12279                     $cnt$$Register, $tmp$$Register,
12280                     $result$$Register, false /* byte */);
12281   %}
12282   ins_pipe(pipe_class_default);
12283 %}
12284 
12285 instruct array_equalsB(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
12286                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
12287   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12288   match(Set result (AryEq ary1 ary2));
12289   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
12290   ins_cost(300);
12291   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
12292   ins_encode %{
12293     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12294     __ array_equals(true, $ary1$$Register, $ary2$$Register,
12295                     $tmp1$$Register, $tmp2$$Register,
12296                     $result$$Register, true /* byte */);
12297   %}
12298   ins_pipe(pipe_class_default);
12299 %}
12300 
12301 instruct array_equalsC(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
12302                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
12303   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12304   match(Set result (AryEq ary1 ary2));
12305   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
12306   ins_cost(300);
12307   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
12308   ins_encode %{
12309     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12310     __ array_equals(true, $ary1$$Register, $ary2$$Register,
12311                     $tmp1$$Register, $tmp2$$Register,
12312                     $result$$Register, false /* byte */);
12313   %}
12314   ins_pipe(pipe_class_default);
12315 %}
12316 
12317 instruct indexOf_imm1_char_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12318                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
12319                              iRegIdst tmp1, iRegIdst tmp2,
12320                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12321   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12322   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12323   // Required for EA: check if it is still a type_array.
12324   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
12325   ins_cost(150);
12326 
12327   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12328             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12329 
12330   ins_encode %{
12331     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12332     immPOper *needleOper = (immPOper *)$needleImm;
12333     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12334     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12335     jchar chr;
12336 #ifdef VM_LITTLE_ENDIAN
12337     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
12338            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
12339 #else
12340     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
12341            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
12342 #endif
12343     __ string_indexof_char($result$$Register,
12344                            $haystack$$Register, $haycnt$$Register,
12345                            R0, chr,
12346                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12347   %}
12348   ins_pipe(pipe_class_compare);
12349 %}
12350 
12351 instruct indexOf_imm1_char_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12352                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
12353                              iRegIdst tmp1, iRegIdst tmp2,
12354                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12355   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12356   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12357   // Required for EA: check if it is still a type_array.
12358   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
12359   ins_cost(150);
12360 
12361   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12362             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12363 
12364   ins_encode %{
12365     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12366     immPOper *needleOper = (immPOper *)$needleImm;
12367     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12368     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12369     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12370     __ string_indexof_char($result$$Register,
12371                            $haystack$$Register, $haycnt$$Register,
12372                            R0, chr,
12373                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
12374   %}
12375   ins_pipe(pipe_class_compare);
12376 %}
12377 
12378 instruct indexOf_imm1_char_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12379                               immP needleImm, immL offsetImm, immI_1 needlecntImm,
12380                               iRegIdst tmp1, iRegIdst tmp2,
12381                               flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12382   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12383   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12384   // Required for EA: check if it is still a type_array.
12385   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
12386   ins_cost(150);
12387 
12388   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12389             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12390 
12391   ins_encode %{
12392     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12393     immPOper *needleOper = (immPOper *)$needleImm;
12394     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12395     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12396     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12397     __ string_indexof_char($result$$Register,
12398                            $haystack$$Register, $haycnt$$Register,
12399                            R0, chr,
12400                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12401   %}
12402   ins_pipe(pipe_class_compare);
12403 %}
12404 
12405 instruct indexOf_imm1_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12406                         rscratch2RegP needle, immI_1 needlecntImm,
12407                         iRegIdst tmp1, iRegIdst tmp2,
12408                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12409   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12410   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12411   // Required for EA: check if it is still a type_array.
12412   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
12413             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12414             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12415   ins_cost(180);
12416 
12417   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12418             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12419   ins_encode %{
12420     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12421     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12422     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12423     guarantee(needle_values, "sanity");
12424     jchar chr;
12425 #ifdef VM_LITTLE_ENDIAN
12426     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
12427            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
12428 #else
12429     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
12430            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
12431 #endif
12432     __ string_indexof_char($result$$Register,
12433                            $haystack$$Register, $haycnt$$Register,
12434                            R0, chr,
12435                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12436   %}
12437   ins_pipe(pipe_class_compare);
12438 %}
12439 
12440 instruct indexOf_imm1_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12441                         rscratch2RegP needle, immI_1 needlecntImm,
12442                         iRegIdst tmp1, iRegIdst tmp2,
12443                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12444   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12445   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12446   // Required for EA: check if it is still a type_array.
12447   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
12448             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12449             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12450   ins_cost(180);
12451 
12452   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12453             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12454   ins_encode %{
12455     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12456     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12457     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12458     guarantee(needle_values, "sanity");
12459     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12460     __ string_indexof_char($result$$Register,
12461                            $haystack$$Register, $haycnt$$Register,
12462                            R0, chr,
12463                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
12464   %}
12465   ins_pipe(pipe_class_compare);
12466 %}
12467 
12468 instruct indexOf_imm1_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12469                          rscratch2RegP needle, immI_1 needlecntImm,
12470                          iRegIdst tmp1, iRegIdst tmp2,
12471                          flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12472   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12473   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12474   // Required for EA: check if it is still a type_array.
12475   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
12476             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12477             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12478   ins_cost(180);
12479 
12480   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12481             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12482   ins_encode %{
12483     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12484     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12485     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12486     guarantee(needle_values, "sanity");
12487     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12488     __ string_indexof_char($result$$Register,
12489                            $haystack$$Register, $haycnt$$Register,
12490                            R0, chr,
12491                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12492   %}
12493   ins_pipe(pipe_class_compare);
12494 %}
12495 
12496 instruct indexOfChar_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12497                        iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
12498                        flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12499   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
12500   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12501   ins_cost(180);
12502 
12503   format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
12504             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12505   ins_encode %{
12506     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12507     __ string_indexof_char($result$$Register,
12508                            $haystack$$Register, $haycnt$$Register,
12509                            $ch$$Register, 0 /* this is not used if the character is already in a register */,
12510                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12511   %}
12512   ins_pipe(pipe_class_compare);
12513 %}
12514 
12515 instruct indexOf_imm_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
12516                        iRegPsrc needle, uimmI15 needlecntImm,
12517                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
12518                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12519   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12520   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
12521          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12522   // Required for EA: check if it is still a type_array.
12523   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
12524             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12525             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12526   ins_cost(250);
12527 
12528   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12529             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
12530   ins_encode %{
12531     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12532     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12533     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12534 
12535     __ string_indexof($result$$Register,
12536                       $haystack$$Register, $haycnt$$Register,
12537                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
12538                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
12539   %}
12540   ins_pipe(pipe_class_compare);
12541 %}
12542 
12543 instruct indexOf_imm_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
12544                        iRegPsrc needle, uimmI15 needlecntImm,
12545                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
12546                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12547   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12548   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
12549          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12550   // Required for EA: check if it is still a type_array.
12551   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
12552             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12553             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12554   ins_cost(250);
12555 
12556   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12557             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
12558   ins_encode %{
12559     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12560     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12561     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12562 
12563     __ string_indexof($result$$Register,
12564                       $haystack$$Register, $haycnt$$Register,
12565                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
12566                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
12567   %}
12568   ins_pipe(pipe_class_compare);
12569 %}
12570 
12571 instruct indexOf_imm_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
12572                         iRegPsrc needle, uimmI15 needlecntImm,
12573                         iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
12574                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12575   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12576   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
12577          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12578   // Required for EA: check if it is still a type_array.
12579   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
12580             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12581             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12582   ins_cost(250);
12583 
12584   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12585             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
12586   ins_encode %{
12587     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12588     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12589     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12590 
12591     __ string_indexof($result$$Register,
12592                       $haystack$$Register, $haycnt$$Register,
12593                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
12594                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
12595   %}
12596   ins_pipe(pipe_class_compare);
12597 %}
12598 
12599 instruct indexOf_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
12600                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
12601                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12602   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
12603   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
12604          TEMP_DEF result,
12605          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12606   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
12607   ins_cost(300);
12608 
12609   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
12610              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
12611   ins_encode %{
12612     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12613     __ string_indexof($result$$Register,
12614                       $haystack$$Register, $haycnt$$Register,
12615                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
12616                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
12617   %}
12618   ins_pipe(pipe_class_compare);
12619 %}
12620 
12621 instruct indexOf_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
12622                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
12623                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12624   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
12625   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
12626          TEMP_DEF result,
12627          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12628   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
12629   ins_cost(300);
12630 
12631   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
12632              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
12633   ins_encode %{
12634     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12635     __ string_indexof($result$$Register,
12636                       $haystack$$Register, $haycnt$$Register,
12637                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
12638                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
12639   %}
12640   ins_pipe(pipe_class_compare);
12641 %}
12642 
12643 instruct indexOf_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
12644                     iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
12645                     flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12646   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
12647   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
12648          TEMP_DEF result,
12649          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12650   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
12651   ins_cost(300);
12652 
12653   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
12654              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
12655   ins_encode %{
12656     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12657     __ string_indexof($result$$Register,
12658                       $haystack$$Register, $haycnt$$Register,
12659                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
12660                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
12661   %}
12662   ins_pipe(pipe_class_compare);
12663 %}
12664 
12665 // char[] to byte[] compression
12666 instruct string_compress(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
12667                          iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
12668   match(Set result (StrCompressedCopy src (Binary dst len)));
12669   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
12670          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
12671   ins_cost(300);
12672   format %{ "String Compress $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
12673   ins_encode %{
12674     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12675     Label Lskip, Ldone;
12676     __ li($result$$Register, 0);
12677     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
12678                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Ldone);
12679     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
12680     __ beq(CCR0, Lskip);
12681     __ string_compress($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register, Ldone);
12682     __ bind(Lskip);
12683     __ mr($result$$Register, $len$$Register);
12684     __ bind(Ldone);
12685   %}
12686   ins_pipe(pipe_class_default);
12687 %}
12688 
12689 // byte[] to char[] inflation
12690 instruct string_inflate(Universe dummy, rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegLdst tmp1,
12691                         iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
12692   match(Set dummy (StrInflatedCopy src (Binary dst len)));
12693   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
12694   ins_cost(300);
12695   format %{ "String Inflate $src,$dst,$len \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
12696   ins_encode %{
12697     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12698     Label Ldone;
12699     __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
12700                          $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
12701     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
12702     __ beq(CCR0, Ldone);
12703     __ string_inflate($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register);
12704     __ bind(Ldone);
12705   %}
12706   ins_pipe(pipe_class_default);
12707 %}
12708 
12709 // StringCoding.java intrinsics
12710 instruct has_negatives(rarg1RegP ary1, iRegIsrc len, iRegIdst result, iRegLdst tmp1, iRegLdst tmp2,
12711                        regCTR ctr, flagsRegCR0 cr0)
12712 %{
12713   match(Set result (HasNegatives ary1 len));
12714   effect(TEMP_DEF result, USE_KILL ary1, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0);
12715   ins_cost(300);
12716   format %{ "has negatives byte[] $ary1,$len -> $result \t// KILL $tmp1, $tmp2" %}
12717   ins_encode %{
12718     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12719     __ has_negatives($ary1$$Register, $len$$Register, $result$$Register,
12720                      $tmp1$$Register, $tmp2$$Register);
12721   %}
12722   ins_pipe(pipe_class_default);
12723 %}
12724 
12725 // encode char[] to byte[] in ISO_8859_1
12726 instruct encode_iso_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
12727                           iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
12728   match(Set result (EncodeISOArray src (Binary dst len)));
12729   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
12730          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
12731   ins_cost(300);
12732   format %{ "Encode array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
12733   ins_encode %{
12734     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12735     Label Lslow, Lfailure1, Lfailure2, Ldone;
12736     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
12737                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Lfailure1);
12738     __ rldicl_($result$$Register, $len$$Register, 0, 64-3); // Remaining characters.
12739     __ beq(CCR0, Ldone);
12740     __ bind(Lslow);
12741     __ string_compress($src$$Register, $dst$$Register, $result$$Register, $tmp2$$Register, Lfailure2);
12742     __ li($result$$Register, 0);
12743     __ b(Ldone);
12744 
12745     __ bind(Lfailure1);
12746     __ mr($result$$Register, $len$$Register);
12747     __ mfctr($tmp1$$Register);
12748     __ rldimi_($result$$Register, $tmp1$$Register, 3, 0); // Remaining characters.
12749     __ beq(CCR0, Ldone);
12750     __ b(Lslow);
12751 
12752     __ bind(Lfailure2);
12753     __ mfctr($result$$Register); // Remaining characters.
12754 
12755     __ bind(Ldone);
12756     __ subf($result$$Register, $result$$Register, $len$$Register);
12757   %}
12758   ins_pipe(pipe_class_default);
12759 %}
12760 
12761 
12762 //---------- Min/Max Instructions ---------------------------------------------
12763 
12764 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
12765   match(Set dst (MinI src1 src2));
12766   ins_cost(DEFAULT_COST*6);
12767 
12768   expand %{
12769     iRegLdst src1s;
12770     iRegLdst src2s;
12771     iRegLdst diff;
12772     iRegLdst sm;
12773     iRegLdst doz; // difference or zero
12774     convI2L_reg(src1s, src1); // Ensure proper sign extension.
12775     convI2L_reg(src2s, src2); // Ensure proper sign extension.
12776     subL_reg_reg(diff, src2s, src1s);
12777     // Need to consider >=33 bit result, therefore we need signmaskL.
12778     signmask64L_regL(sm, diff);
12779     andL_reg_reg(doz, diff, sm); // <=0
12780     addI_regL_regL(dst, doz, src1s);
12781   %}
12782 %}
12783 
12784 instruct minI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
12785   match(Set dst (MinI src1 src2));
12786   effect(KILL cr0);
12787   predicate(VM_Version::has_isel());
12788   ins_cost(DEFAULT_COST*2);
12789 
12790   ins_encode %{
12791     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12792     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
12793     __ isel($dst$$Register, CCR0, Assembler::less, /*invert*/false, $src1$$Register, $src2$$Register);
12794   %}
12795   ins_pipe(pipe_class_default);
12796 %}
12797 
12798 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
12799   match(Set dst (MaxI src1 src2));
12800   ins_cost(DEFAULT_COST*6);
12801 
12802   expand %{
12803     iRegLdst src1s;
12804     iRegLdst src2s;
12805     iRegLdst diff;
12806     iRegLdst sm;
12807     iRegLdst doz; // difference or zero
12808     convI2L_reg(src1s, src1); // Ensure proper sign extension.
12809     convI2L_reg(src2s, src2); // Ensure proper sign extension.
12810     subL_reg_reg(diff, src2s, src1s);
12811     // Need to consider >=33 bit result, therefore we need signmaskL.
12812     signmask64L_regL(sm, diff);
12813     andcL_reg_reg(doz, diff, sm); // >=0
12814     addI_regL_regL(dst, doz, src1s);
12815   %}
12816 %}
12817 
12818 instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
12819   match(Set dst (MaxI src1 src2));
12820   effect(KILL cr0);
12821   predicate(VM_Version::has_isel());
12822   ins_cost(DEFAULT_COST*2);
12823 
12824   ins_encode %{
12825     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12826     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
12827     __ isel($dst$$Register, CCR0, Assembler::greater, /*invert*/false, $src1$$Register, $src2$$Register);
12828   %}
12829   ins_pipe(pipe_class_default);
12830 %}
12831 
12832 //---------- Population Count Instructions ------------------------------------
12833 
12834 // Popcnt for Power7.
12835 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
12836   match(Set dst (PopCountI src));
12837   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
12838   ins_cost(DEFAULT_COST);
12839 
12840   format %{ "POPCNTW $dst, $src" %}
12841   size(4);
12842   ins_encode %{
12843     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
12844     __ popcntw($dst$$Register, $src$$Register);
12845   %}
12846   ins_pipe(pipe_class_default);
12847 %}
12848 
12849 // Popcnt for Power7.
12850 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
12851   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
12852   match(Set dst (PopCountL src));
12853   ins_cost(DEFAULT_COST);
12854 
12855   format %{ "POPCNTD $dst, $src" %}
12856   size(4);
12857   ins_encode %{
12858     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
12859     __ popcntd($dst$$Register, $src$$Register);
12860   %}
12861   ins_pipe(pipe_class_default);
12862 %}
12863 
12864 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
12865   match(Set dst (CountLeadingZerosI src));
12866   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
12867   ins_cost(DEFAULT_COST);
12868 
12869   format %{ "CNTLZW  $dst, $src" %}
12870   size(4);
12871   ins_encode %{
12872     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
12873     __ cntlzw($dst$$Register, $src$$Register);
12874   %}
12875   ins_pipe(pipe_class_default);
12876 %}
12877 
12878 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
12879   match(Set dst (CountLeadingZerosL src));
12880   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
12881   ins_cost(DEFAULT_COST);
12882 
12883   format %{ "CNTLZD  $dst, $src" %}
12884   size(4);
12885   ins_encode %{
12886     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12887     __ cntlzd($dst$$Register, $src$$Register);
12888   %}
12889   ins_pipe(pipe_class_default);
12890 %}
12891 
12892 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
12893   // no match-rule, false predicate
12894   effect(DEF dst, USE src);
12895   predicate(false);
12896 
12897   format %{ "CNTLZD  $dst, $src" %}
12898   size(4);
12899   ins_encode %{
12900     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12901     __ cntlzd($dst$$Register, $src$$Register);
12902   %}
12903   ins_pipe(pipe_class_default);
12904 %}
12905 
12906 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
12907   match(Set dst (CountTrailingZerosI src));
12908   predicate(UseCountLeadingZerosInstructionsPPC64);
12909   ins_cost(DEFAULT_COST);
12910 
12911   expand %{
12912     immI16 imm1 %{ (int)-1 %}
12913     immI16 imm2 %{ (int)32 %}
12914     immI_minus1 m1 %{ -1 %}
12915     iRegIdst tmpI1;
12916     iRegIdst tmpI2;
12917     iRegIdst tmpI3;
12918     addI_reg_imm16(tmpI1, src, imm1);
12919     andcI_reg_reg(tmpI2, src, m1, tmpI1);
12920     countLeadingZerosI(tmpI3, tmpI2);
12921     subI_imm16_reg(dst, imm2, tmpI3);
12922   %}
12923 %}
12924 
12925 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
12926   match(Set dst (CountTrailingZerosL src));
12927   predicate(UseCountLeadingZerosInstructionsPPC64);
12928   ins_cost(DEFAULT_COST);
12929 
12930   expand %{
12931     immL16 imm1 %{ (long)-1 %}
12932     immI16 imm2 %{ (int)64 %}
12933     iRegLdst tmpL1;
12934     iRegLdst tmpL2;
12935     iRegIdst tmpL3;
12936     addL_reg_imm16(tmpL1, src, imm1);
12937     andcL_reg_reg(tmpL2, tmpL1, src);
12938     countLeadingZerosL(tmpL3, tmpL2);
12939     subI_imm16_reg(dst, imm2, tmpL3);
12940  %}
12941 %}
12942 
12943 // Expand nodes for byte_reverse_int.
12944 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
12945   effect(DEF dst, USE src, USE pos, USE shift);
12946   predicate(false);
12947 
12948   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
12949   size(4);
12950   ins_encode %{
12951     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
12952     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
12953   %}
12954   ins_pipe(pipe_class_default);
12955 %}
12956 
12957 // As insrwi_a, but with USE_DEF.
12958 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
12959   effect(USE_DEF dst, USE src, USE pos, USE shift);
12960   predicate(false);
12961 
12962   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
12963   size(4);
12964   ins_encode %{
12965     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
12966     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
12967   %}
12968   ins_pipe(pipe_class_default);
12969 %}
12970 
12971 // Just slightly faster than java implementation.
12972 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
12973   match(Set dst (ReverseBytesI src));
12974   predicate(UseCountLeadingZerosInstructionsPPC64);
12975   ins_cost(DEFAULT_COST);
12976 
12977   expand %{
12978     immI16 imm24 %{ (int) 24 %}
12979     immI16 imm16 %{ (int) 16 %}
12980     immI16  imm8 %{ (int)  8 %}
12981     immI16  imm4 %{ (int)  4 %}
12982     immI16  imm0 %{ (int)  0 %}
12983     iRegLdst tmpI1;
12984     iRegLdst tmpI2;
12985     iRegLdst tmpI3;
12986 
12987     urShiftI_reg_imm(tmpI1, src, imm24);
12988     insrwi_a(dst, tmpI1, imm24, imm8);
12989     urShiftI_reg_imm(tmpI2, src, imm16);
12990     insrwi(dst, tmpI2, imm8, imm16);
12991     urShiftI_reg_imm(tmpI3, src, imm8);
12992     insrwi(dst, tmpI3, imm8, imm8);
12993     insrwi(dst, src, imm0, imm8);
12994   %}
12995 %}
12996 
12997 //---------- Replicate Vector Instructions ------------------------------------
12998 
12999 // Insrdi does replicate if src == dst.
13000 instruct repl32(iRegLdst dst) %{
13001   predicate(false);
13002   effect(USE_DEF dst);
13003 
13004   format %{ "INSRDI  $dst, #0, $dst, #32 \t// replicate" %}
13005   size(4);
13006   ins_encode %{
13007     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13008     __ insrdi($dst$$Register, $dst$$Register, 32, 0);
13009   %}
13010   ins_pipe(pipe_class_default);
13011 %}
13012 
13013 // Insrdi does replicate if src == dst.
13014 instruct repl48(iRegLdst dst) %{
13015   predicate(false);
13016   effect(USE_DEF dst);
13017 
13018   format %{ "INSRDI  $dst, #0, $dst, #48 \t// replicate" %}
13019   size(4);
13020   ins_encode %{
13021     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13022     __ insrdi($dst$$Register, $dst$$Register, 48, 0);
13023   %}
13024   ins_pipe(pipe_class_default);
13025 %}
13026 
13027 // Insrdi does replicate if src == dst.
13028 instruct repl56(iRegLdst dst) %{
13029   predicate(false);
13030   effect(USE_DEF dst);
13031 
13032   format %{ "INSRDI  $dst, #0, $dst, #56 \t// replicate" %}
13033   size(4);
13034   ins_encode %{
13035     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13036     __ insrdi($dst$$Register, $dst$$Register, 56, 0);
13037   %}
13038   ins_pipe(pipe_class_default);
13039 %}
13040 
13041 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13042   match(Set dst (ReplicateB src));
13043   predicate(n->as_Vector()->length() == 8);
13044   expand %{
13045     moveReg(dst, src);
13046     repl56(dst);
13047     repl48(dst);
13048     repl32(dst);
13049   %}
13050 %}
13051 
13052 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
13053   match(Set dst (ReplicateB zero));
13054   predicate(n->as_Vector()->length() == 8);
13055   format %{ "LI      $dst, #0 \t// replicate8B" %}
13056   size(4);
13057   ins_encode %{
13058     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13059     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13060   %}
13061   ins_pipe(pipe_class_default);
13062 %}
13063 
13064 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
13065   match(Set dst (ReplicateB src));
13066   predicate(n->as_Vector()->length() == 8);
13067   format %{ "LI      $dst, #-1 \t// replicate8B" %}
13068   size(4);
13069   ins_encode %{
13070     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13071     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13072   %}
13073   ins_pipe(pipe_class_default);
13074 %}
13075 
13076 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13077   match(Set dst (ReplicateS src));
13078   predicate(n->as_Vector()->length() == 4);
13079   expand %{
13080     moveReg(dst, src);
13081     repl48(dst);
13082     repl32(dst);
13083   %}
13084 %}
13085 
13086 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
13087   match(Set dst (ReplicateS zero));
13088   predicate(n->as_Vector()->length() == 4);
13089   format %{ "LI      $dst, #0 \t// replicate4C" %}
13090   size(4);
13091   ins_encode %{
13092     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13093     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13094   %}
13095   ins_pipe(pipe_class_default);
13096 %}
13097 
13098 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
13099   match(Set dst (ReplicateS src));
13100   predicate(n->as_Vector()->length() == 4);
13101   format %{ "LI      $dst, -1 \t// replicate4C" %}
13102   size(4);
13103   ins_encode %{
13104     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13105     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13106   %}
13107   ins_pipe(pipe_class_default);
13108 %}
13109 
13110 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13111   match(Set dst (ReplicateI src));
13112   predicate(n->as_Vector()->length() == 2);
13113   ins_cost(2 * DEFAULT_COST);
13114   expand %{
13115     moveReg(dst, src);
13116     repl32(dst);
13117   %}
13118 %}
13119 
13120 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
13121   match(Set dst (ReplicateI zero));
13122   predicate(n->as_Vector()->length() == 2);
13123   format %{ "LI      $dst, #0 \t// replicate4C" %}
13124   size(4);
13125   ins_encode %{
13126     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13127     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13128   %}
13129   ins_pipe(pipe_class_default);
13130 %}
13131 
13132 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
13133   match(Set dst (ReplicateI src));
13134   predicate(n->as_Vector()->length() == 2);
13135   format %{ "LI      $dst, -1 \t// replicate4C" %}
13136   size(4);
13137   ins_encode %{
13138     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13139     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13140   %}
13141   ins_pipe(pipe_class_default);
13142 %}
13143 
13144 // Move float to int register via stack, replicate.
13145 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
13146   match(Set dst (ReplicateF src));
13147   predicate(n->as_Vector()->length() == 2);
13148   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
13149   expand %{
13150     stackSlotL tmpS;
13151     iRegIdst tmpI;
13152     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
13153     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
13154     moveReg(dst, tmpI);             // Move int to long reg.
13155     repl32(dst);                    // Replicate bitpattern.
13156   %}
13157 %}
13158 
13159 // Replicate scalar constant to packed float values in Double register
13160 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
13161   match(Set dst (ReplicateF src));
13162   predicate(n->as_Vector()->length() == 2);
13163   ins_cost(5 * DEFAULT_COST);
13164 
13165   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
13166   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
13167 %}
13168 
13169 // Replicate scalar zero constant to packed float values in Double register
13170 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
13171   match(Set dst (ReplicateF zero));
13172   predicate(n->as_Vector()->length() == 2);
13173 
13174   format %{ "LI      $dst, #0 \t// replicate2F" %}
13175   ins_encode %{
13176     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13177     __ li($dst$$Register, 0x0);
13178   %}
13179   ins_pipe(pipe_class_default);
13180 %}
13181 
13182 
13183 //----------Overflow Math Instructions-----------------------------------------
13184 
13185 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
13186 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
13187 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
13188 
13189 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13190   match(Set cr0 (OverflowAddL op1 op2));
13191 
13192   format %{ "add_    $op1, $op2\t# overflow check long" %}
13193   ins_encode %{
13194     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13195     __ li(R0, 0);
13196     __ mtxer(R0); // clear XER.SO
13197     __ addo_(R0, $op1$$Register, $op2$$Register);
13198   %}
13199   ins_pipe(pipe_class_default);
13200 %}
13201 
13202 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13203   match(Set cr0 (OverflowSubL op1 op2));
13204 
13205   format %{ "subfo_  R0, $op2, $op1\t# overflow check long" %}
13206   ins_encode %{
13207     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13208     __ li(R0, 0);
13209     __ mtxer(R0); // clear XER.SO
13210     __ subfo_(R0, $op2$$Register, $op1$$Register);
13211   %}
13212   ins_pipe(pipe_class_default);
13213 %}
13214 
13215 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
13216   match(Set cr0 (OverflowSubL zero op2));
13217 
13218   format %{ "nego_   R0, $op2\t# overflow check long" %}
13219   ins_encode %{
13220     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13221     __ li(R0, 0);
13222     __ mtxer(R0); // clear XER.SO
13223     __ nego_(R0, $op2$$Register);
13224   %}
13225   ins_pipe(pipe_class_default);
13226 %}
13227 
13228 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13229   match(Set cr0 (OverflowMulL op1 op2));
13230 
13231   format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
13232   ins_encode %{
13233     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13234     __ li(R0, 0);
13235     __ mtxer(R0); // clear XER.SO
13236     __ mulldo_(R0, $op1$$Register, $op2$$Register);
13237   %}
13238   ins_pipe(pipe_class_default);
13239 %}
13240 
13241 
13242 // ============================================================================
13243 // Safepoint Instruction
13244 
13245 instruct safePoint_poll(iRegPdst poll) %{
13246   match(SafePoint poll);
13247   predicate(LoadPollAddressFromThread);
13248 
13249   // It caused problems to add the effect that r0 is killed, but this
13250   // effect no longer needs to be mentioned, since r0 is not contained
13251   // in a reg_class.
13252 
13253   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
13254   size(4);
13255   ins_encode( enc_poll(0x0, poll) );
13256   ins_pipe(pipe_class_default);
13257 %}
13258 
13259 // Safepoint without per-thread support. Load address of page to poll
13260 // as constant.
13261 // Rscratch2RegP is R12.
13262 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
13263 // a seperate node so that the oop map is at the right location.
13264 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
13265   match(SafePoint poll);
13266   predicate(!LoadPollAddressFromThread);
13267 
13268   // It caused problems to add the effect that r0 is killed, but this
13269   // effect no longer needs to be mentioned, since r0 is not contained
13270   // in a reg_class.
13271 
13272   format %{ "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
13273   ins_encode( enc_poll(0x0, poll) );
13274   ins_pipe(pipe_class_default);
13275 %}
13276 
13277 // ============================================================================
13278 // Call Instructions
13279 
13280 // Call Java Static Instruction
13281 
13282 // Schedulable version of call static node.
13283 instruct CallStaticJavaDirect(method meth) %{
13284   match(CallStaticJava);
13285   effect(USE meth);
13286   ins_cost(CALL_COST);
13287 
13288   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
13289 
13290   format %{ "CALL,static $meth \t// ==> " %}
13291   size(4);
13292   ins_encode( enc_java_static_call(meth) );
13293   ins_pipe(pipe_class_call);
13294 %}
13295 
13296 // Call Java Dynamic Instruction
13297 
13298 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
13299 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
13300 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
13301 // The call destination must still be placed in the constant pool.
13302 instruct CallDynamicJavaDirectSched(method meth) %{
13303   match(CallDynamicJava); // To get all the data fields we need ...
13304   effect(USE meth);
13305   predicate(false);       // ... but never match.
13306 
13307   ins_field_load_ic_hi_node(loadConL_hiNode*);
13308   ins_field_load_ic_node(loadConLNode*);
13309   ins_num_consts(1 /* 1 patchable constant: call destination */);
13310 
13311   format %{ "BL        \t// dynamic $meth ==> " %}
13312   size(4);
13313   ins_encode( enc_java_dynamic_call_sched(meth) );
13314   ins_pipe(pipe_class_call);
13315 %}
13316 
13317 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
13318 // We use postalloc expanded calls if we use inline caches
13319 // and do not update method data.
13320 //
13321 // This instruction has two constants: inline cache (IC) and call destination.
13322 // Loading the inline cache will be postalloc expanded, thus leaving a call with
13323 // one constant.
13324 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
13325   match(CallDynamicJava);
13326   effect(USE meth);
13327   predicate(UseInlineCaches);
13328   ins_cost(CALL_COST);
13329 
13330   ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
13331 
13332   format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
13333   postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
13334 %}
13335 
13336 // Compound version of call dynamic java
13337 // We use postalloc expanded calls if we use inline caches
13338 // and do not update method data.
13339 instruct CallDynamicJavaDirect(method meth) %{
13340   match(CallDynamicJava);
13341   effect(USE meth);
13342   predicate(!UseInlineCaches);
13343   ins_cost(CALL_COST);
13344 
13345   // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
13346   ins_num_consts(4);
13347 
13348   format %{ "CALL,dynamic $meth \t// ==> " %}
13349   ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
13350   ins_pipe(pipe_class_call);
13351 %}
13352 
13353 // Call Runtime Instruction
13354 
13355 instruct CallRuntimeDirect(method meth) %{
13356   match(CallRuntime);
13357   effect(USE meth);
13358   ins_cost(CALL_COST);
13359 
13360   // Enc_java_to_runtime_call needs up to 3 constants: call target,
13361   // env for callee, C-toc.
13362   ins_num_consts(3);
13363 
13364   format %{ "CALL,runtime" %}
13365   ins_encode( enc_java_to_runtime_call(meth) );
13366   ins_pipe(pipe_class_call);
13367 %}
13368 
13369 // Call Leaf
13370 
13371 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
13372 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
13373   effect(DEF dst, USE src);
13374 
13375   ins_num_consts(1);
13376 
13377   format %{ "MTCTR   $src" %}
13378   size(4);
13379   ins_encode( enc_leaf_call_mtctr(src) );
13380   ins_pipe(pipe_class_default);
13381 %}
13382 
13383 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
13384 instruct CallLeafDirect(method meth) %{
13385   match(CallLeaf);   // To get the data all the data fields we need ...
13386   effect(USE meth);
13387   predicate(false);  // but never match.
13388 
13389   format %{ "BCTRL     \t// leaf call $meth ==> " %}
13390   size(4);
13391   ins_encode %{
13392     // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
13393     __ bctrl();
13394   %}
13395   ins_pipe(pipe_class_call);
13396 %}
13397 
13398 // postalloc expand of CallLeafDirect.
13399 // Load adress to call from TOC, then bl to it.
13400 instruct CallLeafDirect_Ex(method meth) %{
13401   match(CallLeaf);
13402   effect(USE meth);
13403   ins_cost(CALL_COST);
13404 
13405   // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
13406   // env for callee, C-toc.
13407   ins_num_consts(3);
13408 
13409   format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
13410   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
13411 %}
13412 
13413 // Call runtime without safepoint - same as CallLeaf.
13414 // postalloc expand of CallLeafNoFPDirect.
13415 // Load adress to call from TOC, then bl to it.
13416 instruct CallLeafNoFPDirect_Ex(method meth) %{
13417   match(CallLeafNoFP);
13418   effect(USE meth);
13419   ins_cost(CALL_COST);
13420 
13421   // Enc_java_to_runtime_call needs up to 3 constants: call target,
13422   // env for callee, C-toc.
13423   ins_num_consts(3);
13424 
13425   format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
13426   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
13427 %}
13428 
13429 // Tail Call; Jump from runtime stub to Java code.
13430 // Also known as an 'interprocedural jump'.
13431 // Target of jump will eventually return to caller.
13432 // TailJump below removes the return address.
13433 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
13434   match(TailCall jump_target method_oop);
13435   ins_cost(CALL_COST);
13436 
13437   format %{ "MTCTR   $jump_target \t// $method_oop holds method oop\n\t"
13438             "BCTR         \t// tail call" %}
13439   size(8);
13440   ins_encode %{
13441     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13442     __ mtctr($jump_target$$Register);
13443     __ bctr();
13444   %}
13445   ins_pipe(pipe_class_call);
13446 %}
13447 
13448 // Return Instruction
13449 instruct Ret() %{
13450   match(Return);
13451   format %{ "BLR      \t// branch to link register" %}
13452   size(4);
13453   ins_encode %{
13454     // TODO: PPC port $archOpcode(ppc64Opcode_blr);
13455     // LR is restored in MachEpilogNode. Just do the RET here.
13456     __ blr();
13457   %}
13458   ins_pipe(pipe_class_default);
13459 %}
13460 
13461 // Tail Jump; remove the return address; jump to target.
13462 // TailCall above leaves the return address around.
13463 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
13464 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
13465 // "restore" before this instruction (in Epilogue), we need to materialize it
13466 // in %i0.
13467 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
13468   match(TailJump jump_target ex_oop);
13469   ins_cost(CALL_COST);
13470 
13471   format %{ "LD      R4_ARG2 = LR\n\t"
13472             "MTCTR   $jump_target\n\t"
13473             "BCTR     \t// TailJump, exception oop: $ex_oop" %}
13474   size(12);
13475   ins_encode %{
13476     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13477     __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
13478     __ mtctr($jump_target$$Register);
13479     __ bctr();
13480   %}
13481   ins_pipe(pipe_class_call);
13482 %}
13483 
13484 // Create exception oop: created by stack-crawling runtime code.
13485 // Created exception is now available to this handler, and is setup
13486 // just prior to jumping to this handler. No code emitted.
13487 instruct CreateException(rarg1RegP ex_oop) %{
13488   match(Set ex_oop (CreateEx));
13489   ins_cost(0);
13490 
13491   format %{ " -- \t// exception oop; no code emitted" %}
13492   size(0);
13493   ins_encode( /*empty*/ );
13494   ins_pipe(pipe_class_default);
13495 %}
13496 
13497 // Rethrow exception: The exception oop will come in the first
13498 // argument position. Then JUMP (not call) to the rethrow stub code.
13499 instruct RethrowException() %{
13500   match(Rethrow);
13501   ins_cost(CALL_COST);
13502 
13503   format %{ "Jmp     rethrow_stub" %}
13504   ins_encode %{
13505     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13506     cbuf.set_insts_mark();
13507     __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
13508   %}
13509   ins_pipe(pipe_class_call);
13510 %}
13511 
13512 // Die now.
13513 instruct ShouldNotReachHere() %{
13514   match(Halt);
13515   ins_cost(CALL_COST);
13516 
13517   format %{ "ShouldNotReachHere" %}
13518   size(4);
13519   ins_encode %{
13520     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
13521     __ trap_should_not_reach_here();
13522   %}
13523   ins_pipe(pipe_class_default);
13524 %}
13525 
13526 // This name is KNOWN by the ADLC and cannot be changed.  The ADLC
13527 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
13528 // Get a DEF on threadRegP, no costs, no encoding, use
13529 // 'ins_should_rematerialize(true)' to avoid spilling.
13530 instruct tlsLoadP(threadRegP dst) %{
13531   match(Set dst (ThreadLocal));
13532   ins_cost(0);
13533 
13534   ins_should_rematerialize(true);
13535 
13536   format %{ " -- \t// $dst=Thread::current(), empty" %}
13537   size(0);
13538   ins_encode( /*empty*/ );
13539   ins_pipe(pipe_class_empty);
13540 %}
13541 
13542 //---Some PPC specific nodes---------------------------------------------------
13543 
13544 // Stop a group.
13545 instruct endGroup() %{
13546   ins_cost(0);
13547 
13548   ins_is_nop(true);
13549 
13550   format %{ "End Bundle (ori r1, r1, 0)" %}
13551   size(4);
13552   ins_encode %{
13553     // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
13554     __ endgroup();
13555   %}
13556   ins_pipe(pipe_class_default);
13557 %}
13558 
13559 // Nop instructions
13560 
13561 instruct fxNop() %{
13562   ins_cost(0);
13563 
13564   ins_is_nop(true);
13565 
13566   format %{ "fxNop" %}
13567   size(4);
13568   ins_encode %{
13569     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
13570     __ nop();
13571   %}
13572   ins_pipe(pipe_class_default);
13573 %}
13574 
13575 instruct fpNop0() %{
13576   ins_cost(0);
13577 
13578   ins_is_nop(true);
13579 
13580   format %{ "fpNop0" %}
13581   size(4);
13582   ins_encode %{
13583     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
13584     __ fpnop0();
13585   %}
13586   ins_pipe(pipe_class_default);
13587 %}
13588 
13589 instruct fpNop1() %{
13590   ins_cost(0);
13591 
13592   ins_is_nop(true);
13593 
13594   format %{ "fpNop1" %}
13595   size(4);
13596   ins_encode %{
13597     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
13598     __ fpnop1();
13599   %}
13600   ins_pipe(pipe_class_default);
13601 %}
13602 
13603 instruct brNop0() %{
13604   ins_cost(0);
13605   size(4);
13606   format %{ "brNop0" %}
13607   ins_encode %{
13608     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
13609     __ brnop0();
13610   %}
13611   ins_is_nop(true);
13612   ins_pipe(pipe_class_default);
13613 %}
13614 
13615 instruct brNop1() %{
13616   ins_cost(0);
13617 
13618   ins_is_nop(true);
13619 
13620   format %{ "brNop1" %}
13621   size(4);
13622   ins_encode %{
13623     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
13624     __ brnop1();
13625   %}
13626   ins_pipe(pipe_class_default);
13627 %}
13628 
13629 instruct brNop2() %{
13630   ins_cost(0);
13631 
13632   ins_is_nop(true);
13633 
13634   format %{ "brNop2" %}
13635   size(4);
13636   ins_encode %{
13637     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
13638     __ brnop2();
13639   %}
13640   ins_pipe(pipe_class_default);
13641 %}
13642 
13643 //----------PEEPHOLE RULES-----------------------------------------------------
13644 // These must follow all instruction definitions as they use the names
13645 // defined in the instructions definitions.
13646 //
13647 // peepmatch ( root_instr_name [preceeding_instruction]* );
13648 //
13649 // peepconstraint %{
13650 // (instruction_number.operand_name relational_op instruction_number.operand_name
13651 //  [, ...] );
13652 // // instruction numbers are zero-based using left to right order in peepmatch
13653 //
13654 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13655 // // provide an instruction_number.operand_name for each operand that appears
13656 // // in the replacement instruction's match rule
13657 //
13658 // ---------VM FLAGS---------------------------------------------------------
13659 //
13660 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13661 //
13662 // Each peephole rule is given an identifying number starting with zero and
13663 // increasing by one in the order seen by the parser. An individual peephole
13664 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13665 // on the command-line.
13666 //
13667 // ---------CURRENT LIMITATIONS----------------------------------------------
13668 //
13669 // Only match adjacent instructions in same basic block
13670 // Only equality constraints
13671 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13672 // Only one replacement instruction
13673 //
13674 // ---------EXAMPLE----------------------------------------------------------
13675 //
13676 // // pertinent parts of existing instructions in architecture description
13677 // instruct movI(eRegI dst, eRegI src) %{
13678 //   match(Set dst (CopyI src));
13679 // %}
13680 //
13681 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13682 //   match(Set dst (AddI dst src));
13683 //   effect(KILL cr);
13684 // %}
13685 //
13686 // // Change (inc mov) to lea
13687 // peephole %{
13688 //   // increment preceeded by register-register move
13689 //   peepmatch ( incI_eReg movI );
13690 //   // require that the destination register of the increment
13691 //   // match the destination register of the move
13692 //   peepconstraint ( 0.dst == 1.dst );
13693 //   // construct a replacement instruction that sets
13694 //   // the destination to ( move's source register + one )
13695 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13696 // %}
13697 //
13698 // Implementation no longer uses movX instructions since
13699 // machine-independent system no longer uses CopyX nodes.
13700 //
13701 // peephole %{
13702 //   peepmatch ( incI_eReg movI );
13703 //   peepconstraint ( 0.dst == 1.dst );
13704 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13705 // %}
13706 //
13707 // peephole %{
13708 //   peepmatch ( decI_eReg movI );
13709 //   peepconstraint ( 0.dst == 1.dst );
13710 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13711 // %}
13712 //
13713 // peephole %{
13714 //   peepmatch ( addI_eReg_imm movI );
13715 //   peepconstraint ( 0.dst == 1.dst );
13716 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13717 // %}
13718 //
13719 // peephole %{
13720 //   peepmatch ( addP_eReg_imm movP );
13721 //   peepconstraint ( 0.dst == 1.dst );
13722 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13723 // %}
13724 
13725 // // Change load of spilled value to only a spill
13726 // instruct storeI(memory mem, eRegI src) %{
13727 //   match(Set mem (StoreI mem src));
13728 // %}
13729 //
13730 // instruct loadI(eRegI dst, memory mem) %{
13731 //   match(Set dst (LoadI mem));
13732 // %}
13733 //
13734 peephole %{
13735   peepmatch ( loadI storeI );
13736   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13737   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13738 %}
13739 
13740 peephole %{
13741   peepmatch ( loadL storeL );
13742   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13743   peepreplace ( storeL( 1.mem 1.mem 1.src ) );
13744 %}
13745 
13746 peephole %{
13747   peepmatch ( loadP storeP );
13748   peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
13749   peepreplace ( storeP( 1.dst 1.dst 1.src ) );
13750 %}
13751 
13752 //----------SMARTSPILL RULES---------------------------------------------------
13753 // These must follow all instruction definitions as they use the names
13754 // defined in the instructions definitions.