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src/cpu/ppc/vm/ppc.ad

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3062     Label done;
3063     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3064     __ li($dst$$Register, $zero$$constant);
3065     __ beq($crx$$CondRegister, done);
3066     __ li($dst$$Register, $notzero$$constant);
3067     __ bind(done);
3068   %}
3069 
3070   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3071     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3072 
3073     MacroAssembler _masm(&cbuf);
3074     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3075     Label done;
3076     __ bso($crx$$CondRegister, done);
3077     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3078     // TODO PPC port __ endgroup_if_needed(_size == 12);
3079     __ bind(done);
3080   %}
3081 











3082   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3083     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3084 
3085     MacroAssembler _masm(&cbuf);
3086     Label d;   // dummy
3087     __ bind(d);
3088     Label* p = ($lbl$$label);
3089     // `p' is `NULL' when this encoding class is used only to
3090     // determine the size of the encoded instruction.
3091     Label& l = (NULL == p)? d : *(p);
3092     int cc = $cmp$$cmpcode;
3093     int flags_reg = $crx$$reg;
3094     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3095     int bhint = Assembler::bhintNoHint;
3096 
3097     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3098       if (_prob <= PROB_NEVER) {
3099         bhint = Assembler::bhintIsNotTaken;
3100       } else if (_prob >= PROB_ALWAYS) {
3101         bhint = Assembler::bhintIsTaken;


10061 
10062   format %{ "ANDC    $dst, $src1, $src2" %}
10063   size(4);
10064   ins_encode %{
10065     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
10066     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
10067   %}
10068   ins_pipe(pipe_class_default);
10069 %}
10070 
10071 //----------Moves between int/long and float/double----------------------------
10072 //
10073 // The following rules move values from int/long registers/stack-locations
10074 // to float/double registers/stack-locations and vice versa, without doing any
10075 // conversions. These rules are used to implement the bit-conversion methods
10076 // of java.lang.Float etc., e.g.
10077 //   int   floatToIntBits(float value)
10078 //   float intBitsToFloat(int bits)
10079 //
10080 // Notes on the implementation on ppc64:
10081 // We only provide rules which move between a register and a stack-location,
10082 // because we always have to go through memory when moving between a float
10083 // register and an integer register.




























10084 
10085 //---------- Chain stack slots between similar types --------
10086 
10087 // These are needed so that the rules below can match.
10088 
10089 // Load integer from stack slot
10090 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
10091   match(Set dst src);
10092   ins_cost(MEMORY_REF_COST);
10093 
10094   format %{ "LWZ     $dst, $src" %}
10095   size(4);
10096   ins_encode( enc_lwz(dst, src) );
10097   ins_pipe(pipe_class_memory);
10098 %}
10099 
10100 // Store integer to stack slot
10101 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
10102   match(Set dst src);
10103   ins_cost(MEMORY_REF_COST);


10566     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
10567     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10568   %}
10569   ins_pipe(pipe_class_default);
10570 %}
10571 
10572 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
10573   // no match-rule, false predicate
10574   effect(DEF dst, USE crx, USE src);
10575   predicate(false);
10576 
10577   ins_variable_size_depending_on_alignment(true);
10578 
10579   format %{ "cmovI   $crx, $dst, $src" %}
10580   // Worst case is branch + move + stop, no stop without scheduler.
10581   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10582   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10583   ins_pipe(pipe_class_default);
10584 %}
10585 














10586 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
10587   // no match-rule, false predicate
10588   effect(DEF dst, USE crx, USE mem);
10589   predicate(false);
10590 
10591   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
10592   postalloc_expand %{
10593     //
10594     // replaces
10595     //
10596     //   region  dst  crx  mem
10597     //    \       |    |   /
10598     //     dst=cmovI_bso_stackSlotL_conLvalue0
10599     //
10600     // with
10601     //
10602     //   region  dst
10603     //    \       /
10604     //     dst=loadConI16(0)
10605     //      |


10620     m2->add_prec(m1);
10621 
10622     // operands for new nodes
10623     m1->_opnds[0] = op_dst;
10624     m1->_opnds[1] = new immI16Oper(0);
10625 
10626     m2->_opnds[0] = op_dst;
10627     m2->_opnds[1] = op_crx;
10628     m2->_opnds[2] = op_mem;
10629 
10630     // registers for new nodes
10631     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10632     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10633 
10634     // Insert new nodes.
10635     nodes->push(m1);
10636     nodes->push(m2);
10637   %}
10638 %}
10639 






















































10640 // Double to Int conversion, NaN is mapped to 0.
10641 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
10642   match(Set dst (ConvD2I src));

10643   ins_cost(DEFAULT_COST);
10644 
10645   expand %{
10646     regD tmpD;
10647     stackSlotL tmpS;
10648     flagsReg crx;
10649     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10650     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10651     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10652     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10653   %}
10654 %}
10655 















10656 instruct convF2IRaw_regF(regF dst, regF src) %{
10657   // no match-rule, false predicate
10658   effect(DEF dst, USE src);
10659   predicate(false);
10660 
10661   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
10662   size(4);
10663   ins_encode %{
10664     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10665     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10666   %}
10667   ins_pipe(pipe_class_default);
10668 %}
10669 
10670 // Float to Int conversion, NaN is mapped to 0.
10671 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
10672   match(Set dst (ConvF2I src));

10673   ins_cost(DEFAULT_COST);
10674 
10675   expand %{
10676     regF tmpF;
10677     stackSlotL tmpS;
10678     flagsReg crx;
10679     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10680     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10681     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10682     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10683   %}
10684 %}
10685 















10686 // Convert to Long
10687 
10688 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
10689   match(Set dst (ConvI2L src));
10690   format %{ "EXTSW   $dst, $src \t// int->long" %}
10691   size(4);
10692   ins_encode %{
10693     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10694     __ extsw($dst$$Register, $src$$Register);
10695   %}
10696   ins_pipe(pipe_class_default);
10697 %}
10698 
10699 // Zero-extend: convert unsigned int to long (convUI2L).
10700 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
10701   match(Set dst (AndL (ConvI2L src) mask));
10702   ins_cost(DEFAULT_COST);
10703 
10704   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10705   size(4);


10735     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10736     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10737   %}
10738   ins_pipe(pipe_class_default);
10739 %}
10740 
10741 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
10742   // no match-rule, false predicate
10743   effect(DEF dst, USE crx, USE src);
10744   predicate(false);
10745 
10746   ins_variable_size_depending_on_alignment(true);
10747 
10748   format %{ "cmovL   $crx, $dst, $src" %}
10749   // Worst case is branch + move + stop, no stop without scheduler.
10750   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10751   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10752   ins_pipe(pipe_class_default);
10753 %}
10754 














10755 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
10756   // no match-rule, false predicate
10757   effect(DEF dst, USE crx, USE mem);
10758   predicate(false);
10759 
10760   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
10761   postalloc_expand %{
10762     //
10763     // replaces
10764     //
10765     //   region  dst  crx  mem
10766     //    \       |    |   /
10767     //     dst=cmovL_bso_stackSlotL_conLvalue0
10768     //
10769     // with
10770     //
10771     //   region  dst
10772     //    \       /
10773     //     dst=loadConL16(0)
10774     //      |


10786     m2->add_req(n_region, n_crx, n_mem);
10787     m2->add_prec(m1);
10788 
10789     // operands for new nodes
10790     m1->_opnds[0] = op_dst;
10791     m1->_opnds[1] = new immL16Oper(0);
10792     m2->_opnds[0] = op_dst;
10793     m2->_opnds[1] = op_crx;
10794     m2->_opnds[2] = op_mem;
10795 
10796     // registers for new nodes
10797     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10798     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10799 
10800     // Insert new nodes.
10801     nodes->push(m1);
10802     nodes->push(m2);
10803   %}
10804 %}
10805 



















































10806 // Float to Long conversion, NaN is mapped to 0.
10807 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10808   match(Set dst (ConvF2L src));

10809   ins_cost(DEFAULT_COST);
10810 
10811   expand %{
10812     regF tmpF;
10813     stackSlotL tmpS;
10814     flagsReg crx;
10815     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10816     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
10817     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10818     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10819   %}
10820 %}
10821 















10822 instruct convD2LRaw_regD(regD dst, regD src) %{
10823   // no match-rule, false predicate
10824   effect(DEF dst, USE src);
10825   predicate(false);
10826 
10827   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10828   size(4);
10829   ins_encode %{
10830     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10831     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10832   %}
10833   ins_pipe(pipe_class_default);
10834 %}
10835 
10836 // Double to Long conversion, NaN is mapped to 0.
10837 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10838   match(Set dst (ConvD2L src));

10839   ins_cost(DEFAULT_COST);
10840 
10841   expand %{
10842     regD tmpD;
10843     stackSlotL tmpS;
10844     flagsReg crx;
10845     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10846     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
10847     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10848     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10849   %}
10850 %}
10851 















10852 // Convert to Float
10853 
10854 // Placed here as needed in expand.
10855 instruct convL2DRaw_regD(regD dst, regD src) %{
10856   // no match-rule, false predicate
10857   effect(DEF dst, USE src);
10858   predicate(false);
10859 
10860   format %{ "FCFID $dst, $src \t// convL2D" %}
10861   size(4);
10862   ins_encode %{
10863     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10864     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10865   %}
10866   ins_pipe(pipe_class_default);
10867 %}
10868 
10869 // Placed here as needed in expand.
10870 instruct convD2F_reg(regF dst, regD src) %{
10871   match(Set dst (ConvD2F src));


10897   %}
10898 %}
10899 
10900 instruct convL2FRaw_regF(regF dst, regD src) %{
10901   // no match-rule, false predicate
10902   effect(DEF dst, USE src);
10903   predicate(false);
10904 
10905   format %{ "FCFIDS $dst, $src \t// convL2F" %}
10906   size(4);
10907   ins_encode %{
10908     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10909     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10910   %}
10911   ins_pipe(pipe_class_default);
10912 %}
10913 
10914 // Integer to Float conversion. Special version for Power7.
10915 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10916   match(Set dst (ConvI2F src));
10917   predicate(VM_Version::has_fcfids());
10918   ins_cost(DEFAULT_COST);
10919 
10920   expand %{
10921     iRegLdst tmpL;
10922     stackSlotL tmpS;
10923     regD tmpD;
10924     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10925     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10926     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10927     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10928   %}
10929 %}
10930 













10931 // L2F to avoid runtime call.
10932 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10933   match(Set dst (ConvL2F src));
10934   predicate(VM_Version::has_fcfids());
10935   ins_cost(DEFAULT_COST);
10936 
10937   expand %{
10938     stackSlotL tmpS;
10939     regD tmpD;
10940     regL_to_stkL(tmpS, src);             // Store long to stack.
10941     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10942     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10943   %}
10944 %}
10945 













10946 // Moved up as used in expand.
10947 //instruct convD2F_reg(regF dst, regD src) %{%}
10948 
10949 // Convert to Double
10950 
10951 // Integer to Double conversion.
10952 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10953   match(Set dst (ConvI2D src));

10954   ins_cost(DEFAULT_COST);
10955 
10956   expand %{
10957     iRegLdst tmpL;
10958     stackSlotL tmpS;
10959     regD tmpD;
10960     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10961     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10962     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10963     convL2DRaw_regD(dst, tmpD);          // Convert to double.
10964   %}
10965 %}
10966 













10967 // Long to Double conversion
10968 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10969   match(Set dst (ConvL2D src));
10970   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10971 
10972   expand %{
10973     regD tmpD;
10974     moveL2D_stack_reg(tmpD, src);
10975     convL2DRaw_regD(dst, tmpD);













10976   %}
10977 %}
10978 
10979 instruct convF2D_reg(regD dst, regF src) %{
10980   match(Set dst (ConvF2D src));
10981   format %{ "FMR     $dst, $src \t// float->double" %}
10982   // variable size, 0 or 4
10983   ins_encode %{
10984     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10985     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10986   %}
10987   ins_pipe(pipe_class_default);
10988 %}
10989 
10990 //----------Control Flow Instructions------------------------------------------
10991 // Compare Instructions
10992 
10993 // Compare Integers
10994 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10995   match(Set crx (CmpI src1 src2));




3062     Label done;
3063     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3064     __ li($dst$$Register, $zero$$constant);
3065     __ beq($crx$$CondRegister, done);
3066     __ li($dst$$Register, $notzero$$constant);
3067     __ bind(done);
3068   %}
3069 
3070   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3071     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3072 
3073     MacroAssembler _masm(&cbuf);
3074     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3075     Label done;
3076     __ bso($crx$$CondRegister, done);
3077     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3078     // TODO PPC port __ endgroup_if_needed(_size == 12);
3079     __ bind(done);
3080   %}
3081 
3082   enc_class enc_cmove_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
3083     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3084 
3085     MacroAssembler _masm(&cbuf);
3086     Label done;
3087     __ bso($crx$$CondRegister, done);
3088     __ mffprd($dst$$Register, $src$$FloatRegister);
3089     // TODO PPC port __ endgroup_if_needed(_size == 12);
3090     __ bind(done);
3091   %}
3092 
3093   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3094     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3095 
3096     MacroAssembler _masm(&cbuf);
3097     Label d;   // dummy
3098     __ bind(d);
3099     Label* p = ($lbl$$label);
3100     // `p' is `NULL' when this encoding class is used only to
3101     // determine the size of the encoded instruction.
3102     Label& l = (NULL == p)? d : *(p);
3103     int cc = $cmp$$cmpcode;
3104     int flags_reg = $crx$$reg;
3105     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3106     int bhint = Assembler::bhintNoHint;
3107 
3108     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3109       if (_prob <= PROB_NEVER) {
3110         bhint = Assembler::bhintIsNotTaken;
3111       } else if (_prob >= PROB_ALWAYS) {
3112         bhint = Assembler::bhintIsTaken;


10072 
10073   format %{ "ANDC    $dst, $src1, $src2" %}
10074   size(4);
10075   ins_encode %{
10076     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
10077     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
10078   %}
10079   ins_pipe(pipe_class_default);
10080 %}
10081 
10082 //----------Moves between int/long and float/double----------------------------
10083 //
10084 // The following rules move values from int/long registers/stack-locations
10085 // to float/double registers/stack-locations and vice versa, without doing any
10086 // conversions. These rules are used to implement the bit-conversion methods
10087 // of java.lang.Float etc., e.g.
10088 //   int   floatToIntBits(float value)
10089 //   float intBitsToFloat(int bits)
10090 //
10091 // Notes on the implementation on ppc64:
10092 // For Power7 and earlier, the rules are limited to those which move between a
10093 // register and a stack-location, because we always have to go through memory
10094 // when moving between a float register and an integer register.
10095 // This restriction is removed in Power8 with the introduction of the mtfprd
10096 // and mffprd instructions.
10097 
10098 instruct moveL2D_reg(regD dst, iRegLsrc src) %{
10099   match(Set dst (MoveL2D src));
10100   effect(DEF dst, USE src);
10101   predicate(VM_Version::has_mtfprd());
10102 
10103   format %{ "MTFPRD  $dst, $src" %}
10104   size(4);
10105   ins_encode %{
10106     __ mtfprd($dst$$FloatRegister, $src$$Register);
10107   %}
10108   ins_pipe(pipe_class_default);
10109 %}
10110 
10111 instruct moveI2D_reg(regD dst, iRegIsrc src) %{
10112   // no match-rule, false predicate
10113   effect(DEF dst, USE src);
10114   predicate(false);
10115 
10116   format %{ "MTFPRWA $dst, $src" %}
10117   size(4);
10118   ins_encode %{
10119     __ mtfprwa($dst$$FloatRegister, $src$$Register);
10120   %}
10121   ins_pipe(pipe_class_default);
10122 %}
10123 
10124 //---------- Chain stack slots between similar types --------
10125 
10126 // These are needed so that the rules below can match.
10127 
10128 // Load integer from stack slot
10129 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
10130   match(Set dst src);
10131   ins_cost(MEMORY_REF_COST);
10132 
10133   format %{ "LWZ     $dst, $src" %}
10134   size(4);
10135   ins_encode( enc_lwz(dst, src) );
10136   ins_pipe(pipe_class_memory);
10137 %}
10138 
10139 // Store integer to stack slot
10140 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
10141   match(Set dst src);
10142   ins_cost(MEMORY_REF_COST);


10605     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
10606     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10607   %}
10608   ins_pipe(pipe_class_default);
10609 %}
10610 
10611 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
10612   // no match-rule, false predicate
10613   effect(DEF dst, USE crx, USE src);
10614   predicate(false);
10615 
10616   ins_variable_size_depending_on_alignment(true);
10617 
10618   format %{ "cmovI   $crx, $dst, $src" %}
10619   // Worst case is branch + move + stop, no stop without scheduler.
10620   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10621   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10622   ins_pipe(pipe_class_default);
10623 %}
10624 
10625 instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
10626   // no match-rule, false predicate
10627   effect(DEF dst, USE crx, USE src);
10628   predicate(false);
10629 
10630   ins_variable_size_depending_on_alignment(true);
10631 
10632   format %{ "cmovI   $crx, $dst, $src" %}
10633   // Worst case is branch + move + stop, no stop without scheduler.
10634   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10635   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10636   ins_pipe(pipe_class_default);
10637 %}
10638 
10639 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
10640   // no match-rule, false predicate
10641   effect(DEF dst, USE crx, USE mem);
10642   predicate(false);
10643 
10644   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
10645   postalloc_expand %{
10646     //
10647     // replaces
10648     //
10649     //   region  dst  crx  mem
10650     //    \       |    |   /
10651     //     dst=cmovI_bso_stackSlotL_conLvalue0
10652     //
10653     // with
10654     //
10655     //   region  dst
10656     //    \       /
10657     //     dst=loadConI16(0)
10658     //      |


10673     m2->add_prec(m1);
10674 
10675     // operands for new nodes
10676     m1->_opnds[0] = op_dst;
10677     m1->_opnds[1] = new immI16Oper(0);
10678 
10679     m2->_opnds[0] = op_dst;
10680     m2->_opnds[1] = op_crx;
10681     m2->_opnds[2] = op_mem;
10682 
10683     // registers for new nodes
10684     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10685     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10686 
10687     // Insert new nodes.
10688     nodes->push(m1);
10689     nodes->push(m2);
10690   %}
10691 %}
10692 
10693 instruct cmovI_bso_reg_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, regD src) %{
10694   // no match-rule, false predicate
10695   effect(DEF dst, USE crx, USE src);
10696   predicate(false);
10697 
10698   format %{ "CmovI   $dst, $crx, $src \t// postalloc expanded" %}
10699   postalloc_expand %{
10700     //
10701     // replaces
10702     //
10703     //   region  dst  crx  src
10704     //    \       |    |   /
10705     //     dst=cmovI_bso_reg_conLvalue0
10706     //
10707     // with
10708     //
10709     //   region  dst
10710     //    \       /
10711     //     dst=loadConI16(0)
10712     //      |
10713     //      ^  region  dst  crx  src
10714     //      |   \       |    |    /
10715     //      dst=cmovI_bso_reg
10716     //
10717 
10718     // Create new nodes.
10719     MachNode *m1 = new loadConI16Node();
10720     MachNode *m2 = new cmovI_bso_regNode();
10721 
10722     // inputs for new nodes
10723     m1->add_req(n_region);
10724     m2->add_req(n_region, n_crx, n_src);
10725 
10726     // precedences for new nodes
10727     m2->add_prec(m1);
10728 
10729     // operands for new nodes
10730     m1->_opnds[0] = op_dst;
10731     m1->_opnds[1] = new immI16Oper(0);
10732 
10733     m2->_opnds[0] = op_dst;
10734     m2->_opnds[1] = op_crx;
10735     m2->_opnds[2] = op_src;
10736 
10737     // registers for new nodes
10738     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10739     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10740 
10741     // Insert new nodes.
10742     nodes->push(m1);
10743     nodes->push(m2);
10744   %}
10745 %}
10746 
10747 // Double to Int conversion, NaN is mapped to 0.
10748 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
10749   match(Set dst (ConvD2I src));
10750   predicate(!VM_Version::has_mtfprd());
10751   ins_cost(DEFAULT_COST);
10752 
10753   expand %{
10754     regD tmpD;
10755     stackSlotL tmpS;
10756     flagsReg crx;
10757     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10758     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10759     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10760     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10761   %}
10762 %}
10763 
10764 // Double to Int conversion, NaN is mapped to 0. Special version for Power8.
10765 instruct convD2I_reg_mffprd_ExEx(iRegIdst dst, regD src) %{
10766   match(Set dst (ConvD2I src));
10767   predicate(VM_Version::has_mtfprd());
10768   ins_cost(DEFAULT_COST);
10769 
10770   expand %{
10771     regD tmpD;
10772     flagsReg crx;
10773     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10774     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10775     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
10776   %}
10777 %}
10778 
10779 instruct convF2IRaw_regF(regF dst, regF src) %{
10780   // no match-rule, false predicate
10781   effect(DEF dst, USE src);
10782   predicate(false);
10783 
10784   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
10785   size(4);
10786   ins_encode %{
10787     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10788     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10789   %}
10790   ins_pipe(pipe_class_default);
10791 %}
10792 
10793 // Float to Int conversion, NaN is mapped to 0.
10794 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
10795   match(Set dst (ConvF2I src));
10796   predicate(!VM_Version::has_mtfprd());
10797   ins_cost(DEFAULT_COST);
10798 
10799   expand %{
10800     regF tmpF;
10801     stackSlotL tmpS;
10802     flagsReg crx;
10803     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10804     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10805     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10806     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10807   %}
10808 %}
10809 
10810 // Float to Int conversion, NaN is mapped to 0. Special version for Power8.
10811 instruct convF2I_regF_mffprd_ExEx(iRegIdst dst, regF src) %{
10812   match(Set dst (ConvF2I src));
10813   predicate(VM_Version::has_mtfprd());
10814   ins_cost(DEFAULT_COST);
10815 
10816   expand %{
10817     regF tmpF;
10818     flagsReg crx;
10819     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10820     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10821     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
10822   %}
10823 %}
10824 
10825 // Convert to Long
10826 
10827 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
10828   match(Set dst (ConvI2L src));
10829   format %{ "EXTSW   $dst, $src \t// int->long" %}
10830   size(4);
10831   ins_encode %{
10832     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10833     __ extsw($dst$$Register, $src$$Register);
10834   %}
10835   ins_pipe(pipe_class_default);
10836 %}
10837 
10838 // Zero-extend: convert unsigned int to long (convUI2L).
10839 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
10840   match(Set dst (AndL (ConvI2L src) mask));
10841   ins_cost(DEFAULT_COST);
10842 
10843   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10844   size(4);


10874     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10875     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10876   %}
10877   ins_pipe(pipe_class_default);
10878 %}
10879 
10880 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
10881   // no match-rule, false predicate
10882   effect(DEF dst, USE crx, USE src);
10883   predicate(false);
10884 
10885   ins_variable_size_depending_on_alignment(true);
10886 
10887   format %{ "cmovL   $crx, $dst, $src" %}
10888   // Worst case is branch + move + stop, no stop without scheduler.
10889   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10890   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10891   ins_pipe(pipe_class_default);
10892 %}
10893 
10894 instruct cmovL_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
10895   // no match-rule, false predicate
10896   effect(DEF dst, USE crx, USE src);
10897   predicate(false);
10898 
10899   ins_variable_size_depending_on_alignment(true);
10900 
10901   format %{ "cmovL   $crx, $dst, $src" %}
10902   // Worst case is branch + move + stop, no stop without scheduler.
10903   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10904   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10905   ins_pipe(pipe_class_default);
10906 %}
10907 
10908 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
10909   // no match-rule, false predicate
10910   effect(DEF dst, USE crx, USE mem);
10911   predicate(false);
10912 
10913   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
10914   postalloc_expand %{
10915     //
10916     // replaces
10917     //
10918     //   region  dst  crx  mem
10919     //    \       |    |   /
10920     //     dst=cmovL_bso_stackSlotL_conLvalue0
10921     //
10922     // with
10923     //
10924     //   region  dst
10925     //    \       /
10926     //     dst=loadConL16(0)
10927     //      |


10939     m2->add_req(n_region, n_crx, n_mem);
10940     m2->add_prec(m1);
10941 
10942     // operands for new nodes
10943     m1->_opnds[0] = op_dst;
10944     m1->_opnds[1] = new immL16Oper(0);
10945     m2->_opnds[0] = op_dst;
10946     m2->_opnds[1] = op_crx;
10947     m2->_opnds[2] = op_mem;
10948 
10949     // registers for new nodes
10950     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10951     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10952 
10953     // Insert new nodes.
10954     nodes->push(m1);
10955     nodes->push(m2);
10956   %}
10957 %}
10958 
10959 instruct cmovL_bso_reg_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, regD src) %{
10960   // no match-rule, false predicate
10961   effect(DEF dst, USE crx, USE src);
10962   predicate(false);
10963 
10964   format %{ "CmovL   $dst, $crx, $src \t// postalloc expanded" %}
10965   postalloc_expand %{
10966     //
10967     // replaces
10968     //
10969     //   region  dst  crx  src
10970     //    \       |    |   /
10971     //     dst=cmovL_bso_reg_conLvalue0
10972     //
10973     // with
10974     //
10975     //   region  dst
10976     //    \       /
10977     //     dst=loadConL16(0)
10978     //      |
10979     //      ^  region  dst  crx  src
10980     //      |   \       |    |    /
10981     //      dst=cmovL_bso_reg
10982     //
10983 
10984     // Create new nodes.
10985     MachNode *m1 = new loadConL16Node();
10986     MachNode *m2 = new cmovL_bso_regNode();
10987 
10988     // inputs for new nodes
10989     m1->add_req(n_region);
10990     m2->add_req(n_region, n_crx, n_src);
10991     m2->add_prec(m1);
10992 
10993     // operands for new nodes
10994     m1->_opnds[0] = op_dst;
10995     m1->_opnds[1] = new immL16Oper(0);
10996     m2->_opnds[0] = op_dst;
10997     m2->_opnds[1] = op_crx;
10998     m2->_opnds[2] = op_src;
10999 
11000     // registers for new nodes
11001     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11002     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11003 
11004     // Insert new nodes.
11005     nodes->push(m1);
11006     nodes->push(m2);
11007   %}
11008 %}
11009 
11010 // Float to Long conversion, NaN is mapped to 0.
11011 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
11012   match(Set dst (ConvF2L src));
11013   predicate(!VM_Version::has_mtfprd());
11014   ins_cost(DEFAULT_COST);
11015 
11016   expand %{
11017     regF tmpF;
11018     stackSlotL tmpS;
11019     flagsReg crx;
11020     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11021     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11022     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
11023     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11024   %}
11025 %}
11026 
11027 // Float to Long conversion, NaN is mapped to 0. Special version for Power8.
11028 instruct convF2L_reg_mffprd_ExEx(iRegLdst dst, regF src) %{
11029   match(Set dst (ConvF2L src));
11030   predicate(VM_Version::has_mtfprd());
11031   ins_cost(DEFAULT_COST);
11032 
11033   expand %{
11034     regF tmpF;
11035     flagsReg crx;
11036     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11037     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11038     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
11039   %}
11040 %}
11041 
11042 instruct convD2LRaw_regD(regD dst, regD src) %{
11043   // no match-rule, false predicate
11044   effect(DEF dst, USE src);
11045   predicate(false);
11046 
11047   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
11048   size(4);
11049   ins_encode %{
11050     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
11051     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
11052   %}
11053   ins_pipe(pipe_class_default);
11054 %}
11055 
11056 // Double to Long conversion, NaN is mapped to 0.
11057 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
11058   match(Set dst (ConvD2L src));
11059   predicate(!VM_Version::has_mtfprd());
11060   ins_cost(DEFAULT_COST);
11061 
11062   expand %{
11063     regD tmpD;
11064     stackSlotL tmpS;
11065     flagsReg crx;
11066     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11067     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11068     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
11069     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11070   %}
11071 %}
11072 
11073 // Double to Long conversion, NaN is mapped to 0. Special version for Power8.
11074 instruct convD2L_reg_mffprd_ExEx(iRegLdst dst, regD src) %{
11075   match(Set dst (ConvD2L src));
11076   predicate(VM_Version::has_mtfprd());
11077   ins_cost(DEFAULT_COST);
11078 
11079   expand %{
11080     regD tmpD;
11081     flagsReg crx;
11082     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11083     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11084     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
11085   %}
11086 %}
11087 
11088 // Convert to Float
11089 
11090 // Placed here as needed in expand.
11091 instruct convL2DRaw_regD(regD dst, regD src) %{
11092   // no match-rule, false predicate
11093   effect(DEF dst, USE src);
11094   predicate(false);
11095 
11096   format %{ "FCFID $dst, $src \t// convL2D" %}
11097   size(4);
11098   ins_encode %{
11099     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11100     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
11101   %}
11102   ins_pipe(pipe_class_default);
11103 %}
11104 
11105 // Placed here as needed in expand.
11106 instruct convD2F_reg(regF dst, regD src) %{
11107   match(Set dst (ConvD2F src));


11133   %}
11134 %}
11135 
11136 instruct convL2FRaw_regF(regF dst, regD src) %{
11137   // no match-rule, false predicate
11138   effect(DEF dst, USE src);
11139   predicate(false);
11140 
11141   format %{ "FCFIDS $dst, $src \t// convL2F" %}
11142   size(4);
11143   ins_encode %{
11144     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11145     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
11146   %}
11147   ins_pipe(pipe_class_default);
11148 %}
11149 
11150 // Integer to Float conversion. Special version for Power7.
11151 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
11152   match(Set dst (ConvI2F src));
11153   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11154   ins_cost(DEFAULT_COST);
11155 
11156   expand %{
11157     iRegLdst tmpL;
11158     stackSlotL tmpS;
11159     regD tmpD;
11160     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11161     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11162     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11163     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11164   %}
11165 %}
11166 
11167 // Integer to Float conversion. Special version for Power8.
11168 instruct convI2F_ireg_mtfprd_Ex(regF dst, iRegIsrc src) %{
11169   match(Set dst (ConvI2F src));
11170   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11171   ins_cost(DEFAULT_COST);
11172 
11173   expand %{
11174     regD tmpD;
11175     moveI2D_reg(tmpD, src);
11176     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11177   %}
11178 %}
11179 
11180 // L2F to avoid runtime call.
11181 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
11182   match(Set dst (ConvL2F src));
11183   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11184   ins_cost(DEFAULT_COST);
11185 
11186   expand %{
11187     stackSlotL tmpS;
11188     regD tmpD;
11189     regL_to_stkL(tmpS, src);             // Store long to stack.
11190     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11191     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11192   %}
11193 %}
11194 
11195 // L2F to avoid runtime call.  Special version for Power8.
11196 instruct convL2F_ireg_mtfprd_Ex(regF dst, iRegLsrc src) %{
11197   match(Set dst (ConvL2F src));
11198   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11199   ins_cost(DEFAULT_COST);
11200 
11201   expand %{
11202     regD tmpD;
11203     moveL2D_reg(tmpD, src);
11204     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11205   %}
11206 %}
11207 
11208 // Moved up as used in expand.
11209 //instruct convD2F_reg(regF dst, regD src) %{%}
11210 
11211 // Convert to Double
11212 
11213 // Integer to Double conversion.
11214 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
11215   match(Set dst (ConvI2D src));
11216   predicate(!VM_Version::has_mtfprd());
11217   ins_cost(DEFAULT_COST);
11218 
11219   expand %{
11220     iRegLdst tmpL;
11221     stackSlotL tmpS;
11222     regD tmpD;
11223     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11224     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11225     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11226     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11227   %}
11228 %}
11229 
11230 // Integer to Double conversion. Special version for Power8.
11231 instruct convI2D_reg_mtfprd_Ex(regD dst, iRegIsrc src) %{
11232   match(Set dst (ConvI2D src));
11233   predicate(VM_Version::has_mtfprd());
11234   ins_cost(DEFAULT_COST);
11235 
11236   expand %{
11237     regD tmpD;
11238     moveI2D_reg(tmpD, src);
11239     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11240   %}
11241 %}
11242 
11243 // Long to Double conversion
11244 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
11245   match(Set dst (ConvL2D src));
11246   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
11247 
11248   expand %{
11249     regD tmpD;
11250     moveL2D_stack_reg(tmpD, src);
11251     convL2DRaw_regD(dst, tmpD);
11252   %}
11253 %}
11254 
11255 // Long to Double conversion. Special version for Power8.
11256 instruct convL2D_reg_mtfprd_Ex(regD dst, iRegLsrc src) %{
11257   match(Set dst (ConvL2D src));
11258   predicate(VM_Version::has_mtfprd());
11259   ins_cost(DEFAULT_COST);
11260 
11261   expand %{
11262     regD tmpD;
11263     moveL2D_reg(tmpD, src);
11264     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11265   %}
11266 %}
11267 
11268 instruct convF2D_reg(regD dst, regF src) %{
11269   match(Set dst (ConvF2D src));
11270   format %{ "FMR     $dst, $src \t// float->double" %}
11271   // variable size, 0 or 4
11272   ins_encode %{
11273     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11274     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
11275   %}
11276   ins_pipe(pipe_class_default);
11277 %}
11278 
11279 //----------Control Flow Instructions------------------------------------------
11280 // Compare Instructions
11281 
11282 // Compare Integers
11283 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11284   match(Set crx (CmpI src1 src2));


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