# HG changeset patch # User mdoerr # Date 1544120814 18000 # Thu Dec 06 13:26:54 2018 -0500 # Node ID a0db4ba3b96af38e2bfa4b1dd8cc93fc9b64dfda # Parent a253fe293726a4b4e9ce51f48371ec32872bfbe4 8185975: PPC64: Fix vsldoi interface according to the ISA Reviewed-by: mdoerr Contributed-by: Gustavo Serra Scalet diff --git a/src/cpu/ppc/vm/assembler_ppc.hpp b/src/cpu/ppc/vm/assembler_ppc.hpp --- a/src/cpu/ppc/vm/assembler_ppc.hpp +++ b/src/cpu/ppc/vm/assembler_ppc.hpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. - * Copyright 2012, 2013 SAP AG. All rights reserved. + * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2018, SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -1838,7 +1838,7 @@ inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); - inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4); + inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4); inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); diff --git a/src/cpu/ppc/vm/assembler_ppc.inline.hpp b/src/cpu/ppc/vm/assembler_ppc.inline.hpp --- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp +++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. - * Copyright 2012, 2014 SAP AG. All rights reserved. + * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2018, SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -657,7 +657,7 @@ inline void Assembler::vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VPERM_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); } inline void Assembler::vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VSEL_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); } inline void Assembler::vsl( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSL_OPCODE | vrt(d) | vra(a) | vrb(b)); } -inline void Assembler::vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4) { emit_int32( VSLDOI_OPCODE| vrt(d) | vra(a) | vrb(b) | vsldoi_shb(simm(si4,4))); } +inline void Assembler::vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4) { emit_int32( VSLDOI_OPCODE| vrt(d) | vra(a) | vrb(b) | vsldoi_shb(uimm(ui4,4))); } inline void Assembler::vslo( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSLO_OPCODE | vrt(d) | vra(a) | vrb(b)); } inline void Assembler::vsr( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSR_OPCODE | vrt(d) | vra(a) | vrb(b)); } inline void Assembler::vsro( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRO_OPCODE | vrt(d) | vra(a) | vrb(b)); } diff --git a/src/cpu/ppc/vm/macroAssembler_ppc.cpp b/src/cpu/ppc/vm/macroAssembler_ppc.cpp --- a/src/cpu/ppc/vm/macroAssembler_ppc.cpp +++ b/src/cpu/ppc/vm/macroAssembler_ppc.cpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. - * Copyright 2012, 2017 SAP AG. All rights reserved. + * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2018, SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -3570,12 +3570,12 @@ vspltisw(VR0, -1); vsldoi(mask_32bit, zeroes, VR0, 4); - vsldoi(mask_64bit, zeroes, VR0, -8); + vsldoi(mask_64bit, zeroes, VR0, 8); // Get the initial value into v8 vxor(VR8, VR8, VR8); mtvrd(VR8, crc); - vsldoi(VR8, zeroes, VR8, -8); // shift into bottom 32 bits + vsldoi(VR8, zeroes, VR8, 8); // shift into bottom 32 bits li (rLoaded, 0); @@ -3924,7 +3924,7 @@ addi(barretConstants, barretConstants, 16); lvx(const2, barretConstants); - vsldoi(VR1, VR0, VR0, -8); + vsldoi(VR1, VR0, VR0, 8); vxor(VR0, VR0, VR1); // xor two 64 bit results together // shift left one bit diff --git a/src/cpu/ppc/vm/stubGenerator_ppc.cpp b/src/cpu/ppc/vm/stubGenerator_ppc.cpp --- a/src/cpu/ppc/vm/stubGenerator_ppc.cpp +++ b/src/cpu/ppc/vm/stubGenerator_ppc.cpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. - * Copyright 2012, 2014 SAP AG. All rights reserved. + * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2018, SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -2023,7 +2023,7 @@ __ vspltisb (vTmp2, -16); __ vrld (keyPerm, keyPerm, vTmp2); __ vrld (keyPerm, keyPerm, vTmp2); - __ vsldoi (keyPerm, keyPerm, keyPerm, -8); + __ vsldoi (keyPerm, keyPerm, keyPerm, 8); // load the 1st round key to vKey1 __ li (keypos, 0); @@ -2223,7 +2223,7 @@ __ vspltisb (vTmp2, -16); __ vrld (keyPerm, keyPerm, vTmp2); __ vrld (keyPerm, keyPerm, vTmp2); - __ vsldoi (keyPerm, keyPerm, keyPerm, -8); + __ vsldoi (keyPerm, keyPerm, keyPerm, 8); __ cmpwi (CCR0, keylen, 44); __ beq (CCR0, L_do44);