src/hotspot/cpu/ppc/macroAssembler_ppc.cpp

rev 50748 : 8205582: PPC64: RTM: Fix counter for aborts on nested transactions

@@ -2422,14 +2422,14 @@
   //  3   10  Set if an internal buffer overflowed.
   //  4  ?12  Set if a debug breakpoint was hit.
   //  5  ?32  Set if an abort occurred during execution of a nested transaction.
   const  int tm_failure_bit[] = {Assembler::tm_tabort, // Note: Seems like signal handler sets this, too.
                                  Assembler::tm_failure_persistent, // inverted: transient
-                                 Assembler::tm_trans_cf,
-                                 Assembler::tm_footprint_of,
                                  Assembler::tm_non_trans_cf,
-                                 Assembler::tm_suspended};
+                                 Assembler::tm_footprint_of,
+                                 Assembler::tm_non_trans_cf, // TODO: verify correctness
+                                 Assembler::tm_transaction_level};
   const bool tm_failure_inv[] = {false, true, false, false, false, false};
   assert(sizeof(tm_failure_bit)/sizeof(int) == RTMLockingCounters::ABORT_STATUS_LIMIT, "adapt mapping!");
 
   const Register addr_Reg = R0;
   // Keep track of offset to where rtm_counters_Reg had pointed to.

@@ -2451,11 +2451,19 @@
       li(temp_Reg, counters_offs_delta); // can't use addi with R0
       add(addr_Reg, addr_Reg, temp_Reg); // point to next counter
       counters_offs_delta = sizeof(uintx);
 
       Label check_abort;
+
+      if (tm_failure_bit[i] == Assembler::tm_transaction_level) {
+        // Extract 11 bits
+        rldicr_(temp_Reg, abort_status, tm_failure_bit[i], 11);
+      } else {
+        // Extract 1 bit
       rldicr_(temp_Reg, abort_status, tm_failure_bit[i], 0);
+      }
+
       if (tm_failure_inv[i]) {
         bne(CCR0, check_abort);
       } else {
         beq(CCR0, check_abort);
       }