1618 inline void mtxer(Register s1);
1619 inline void mfxer(Register d);
1620 // Vector Register Save Register
1621 inline void mtvrsave(Register s1);
1622 inline void mfvrsave(Register d);
1623 // Timebase
1624 inline void mftb(Register d);
1625 // Introduced with Power 8:
1626 // Data Stream Control Register
1627 inline void mtdscr(Register s1);
1628 inline void mfdscr(Register d );
1629 // Transactional Memory Registers
1630 inline void mftfhar(Register d);
1631 inline void mftfiar(Register d);
1632 inline void mftexasr(Register d);
1633 inline void mftexasru(Register d);
1634
1635 // TEXASR bit description
1636 enum transaction_failure_reason {
1637 // Upper half (TEXASRU):
1638 tm_failure_persistent = 7, // The failure is likely to recur on each execution.
1639 tm_disallowed = 8, // The instruction is not permitted.
1640 tm_nesting_of = 9, // The maximum transaction level was exceeded.
1641 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded.
1642 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state.
1643 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor.
1644 tm_trans_cf = 13, // A conflict occurred with another transaction.
1645 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation.
1646 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally.
1647 tm_tabort = 31, // Termination was caused by the execution of an abort instruction.
1648 // Lower half:
1649 tm_suspended = 32, // Failure was recorded in Suspended state.
1650 tm_failure_summary = 36, // Failure has been detected and recorded.
1651 tm_tfiar_exact = 37, // Value in the TFIAR is exact.
1652 tm_rot = 38, // Rollback-only transaction.
1653 };
1654
1655 // PPC 1, section 2.4.1 Branch Instructions
1656 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1657 inline void b( Label& L);
1658 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1659 inline void bl( Label& L);
1660 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1661 inline void bc( int boint, int biint, Label& L);
1662 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1663 inline void bcl(int boint, int biint, Label& L);
1664
1665 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1666 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1667 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1668 relocInfo::relocType rt = relocInfo::none);
1669 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1670 relocInfo::relocType rt = relocInfo::none);
1671
1672 // helper function for b, bcxx
1744 inline void crnand(int d, int s1, int s2);
1745 inline void cror( int d, int s1, int s2);
1746 inline void crxor( int d, int s1, int s2);
1747 inline void crnor( int d, int s1, int s2);
1748 inline void creqv( int d, int s1, int s2);
1749 inline void crandc(int d, int s1, int s2);
1750 inline void crorc( int d, int s1, int s2);
1751
1752 // More convenient version.
1753 int condition_register_bit(ConditionRegister cr, Condition c) {
1754 return 4 * (int)(intptr_t)cr + c;
1755 }
1756 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1757 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1758 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1759 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1760 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1761 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1762 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1763 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1764
1765 // icache and dcache related instructions
1766 inline void icbi( Register s1, Register s2);
1767 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1768 inline void dcbz( Register s1, Register s2);
1769 inline void dcbst( Register s1, Register s2);
1770 inline void dcbf( Register s1, Register s2);
1771
1772 enum ct_cache_specification {
1773 ct_primary_cache = 0,
1774 ct_secondary_cache = 2
1775 };
1776 // dcache read hint
1777 inline void dcbt( Register s1, Register s2);
1778 inline void dcbtct( Register s1, Register s2, int ct);
1779 inline void dcbtds( Register s1, Register s2, int ds);
1780 // dcache write hint
1781 inline void dcbtst( Register s1, Register s2);
1782 inline void dcbtstct(Register s1, Register s2, int ct);
1783
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1618 inline void mtxer(Register s1);
1619 inline void mfxer(Register d);
1620 // Vector Register Save Register
1621 inline void mtvrsave(Register s1);
1622 inline void mfvrsave(Register d);
1623 // Timebase
1624 inline void mftb(Register d);
1625 // Introduced with Power 8:
1626 // Data Stream Control Register
1627 inline void mtdscr(Register s1);
1628 inline void mfdscr(Register d );
1629 // Transactional Memory Registers
1630 inline void mftfhar(Register d);
1631 inline void mftfiar(Register d);
1632 inline void mftexasr(Register d);
1633 inline void mftexasru(Register d);
1634
1635 // TEXASR bit description
1636 enum transaction_failure_reason {
1637 // Upper half (TEXASRU):
1638 tm_failure_code = 0, // The Failure Code is copied from tabort or treclaim operand.
1639 tm_failure_persistent = 7, // The failure is likely to recur on each execution.
1640 tm_disallowed = 8, // The instruction is not permitted.
1641 tm_nesting_of = 9, // The maximum transaction level was exceeded.
1642 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded.
1643 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state.
1644 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor.
1645 tm_trans_cf = 13, // A conflict occurred with another transaction.
1646 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation.
1647 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally.
1648 tm_tabort = 31, // Termination was caused by the execution of an abort instruction.
1649 // Lower half:
1650 tm_suspended = 32, // Failure was recorded in Suspended state.
1651 tm_failure_summary = 36, // Failure has been detected and recorded.
1652 tm_tfiar_exact = 37, // Value in the TFIAR is exact.
1653 tm_rot = 38, // Rollback-only transaction.
1654 tm_transaction_level = 52, // Transaction level (nesting depth + 1).
1655 };
1656
1657 // PPC 1, section 2.4.1 Branch Instructions
1658 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1659 inline void b( Label& L);
1660 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1661 inline void bl( Label& L);
1662 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1663 inline void bc( int boint, int biint, Label& L);
1664 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1665 inline void bcl(int boint, int biint, Label& L);
1666
1667 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1668 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1669 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1670 relocInfo::relocType rt = relocInfo::none);
1671 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1672 relocInfo::relocType rt = relocInfo::none);
1673
1674 // helper function for b, bcxx
1746 inline void crnand(int d, int s1, int s2);
1747 inline void cror( int d, int s1, int s2);
1748 inline void crxor( int d, int s1, int s2);
1749 inline void crnor( int d, int s1, int s2);
1750 inline void creqv( int d, int s1, int s2);
1751 inline void crandc(int d, int s1, int s2);
1752 inline void crorc( int d, int s1, int s2);
1753
1754 // More convenient version.
1755 int condition_register_bit(ConditionRegister cr, Condition c) {
1756 return 4 * (int)(intptr_t)cr + c;
1757 }
1758 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1759 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1760 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1761 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1762 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1763 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1764 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1765 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1766 void crnot( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1767
1768 // icache and dcache related instructions
1769 inline void icbi( Register s1, Register s2);
1770 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1771 inline void dcbz( Register s1, Register s2);
1772 inline void dcbst( Register s1, Register s2);
1773 inline void dcbf( Register s1, Register s2);
1774
1775 enum ct_cache_specification {
1776 ct_primary_cache = 0,
1777 ct_secondary_cache = 2
1778 };
1779 // dcache read hint
1780 inline void dcbt( Register s1, Register s2);
1781 inline void dcbtct( Register s1, Register s2, int ct);
1782 inline void dcbtds( Register s1, Register s2, int ds);
1783 // dcache write hint
1784 inline void dcbtst( Register s1, Register s2);
1785 inline void dcbtstct(Register s1, Register s2, int ct);
1786
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