rev 52948 : 8213754: PPC64: Add Intrinsics for isDigit/isLowerCase/isUpperCase/isWhitespace
Reviewed-by: kvn, rriggs, mdoerr, gromero

   1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2018, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "jvm.h"
  28 #include "asm/assembler.inline.hpp"
  29 #include "asm/macroAssembler.inline.hpp"
  30 #include "compiler/disassembler.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "utilities/align.hpp"
  36 #include "utilities/defaultStream.hpp"
  37 #include "utilities/globalDefinitions.hpp"
  38 #include "vm_version_ppc.hpp"
  39 
  40 #include <sys/sysinfo.h>
  41 
  42 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
  43 #include <sys/auxv.h>
  44 
  45 #ifndef PPC_FEATURE2_HTM_NOSC
  46 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
  47 #endif
  48 #endif
  49 
  50 bool VM_Version::_is_determine_features_test_running = false;
  51 uint64_t VM_Version::_dscr_val = 0;
  52 
  53 #define MSG(flag)   \
  54   if (flag && !FLAG_IS_DEFAULT(flag))                                  \
  55       jio_fprintf(defaultStream::error_stream(),                       \
  56                   "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
  57                   "         -XX:+" #flag " will be disabled!\n");
  58 
  59 void VM_Version::initialize() {
  60 
  61   // Test which instructions are supported and measure cache line size.
  62   determine_features();
  63 
  64   // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
  65   if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
  66     if (VM_Version::has_darn()) {
  67       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 9);
  68     } else if (VM_Version::has_lqarx()) {
  69       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
  70     } else if (VM_Version::has_popcntw()) {
  71       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
  72     } else if (VM_Version::has_cmpb()) {
  73       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
  74     } else if (VM_Version::has_popcntb()) {
  75       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
  76     } else {
  77       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
  78     }
  79   }
  80 
  81   bool PowerArchitecturePPC64_ok = false;
  82   switch (PowerArchitecturePPC64) {
  83     case 9: if (!VM_Version::has_darn()   ) break;
  84     case 8: if (!VM_Version::has_lqarx()  ) break;
  85     case 7: if (!VM_Version::has_popcntw()) break;
  86     case 6: if (!VM_Version::has_cmpb()   ) break;
  87     case 5: if (!VM_Version::has_popcntb()) break;
  88     case 0: PowerArchitecturePPC64_ok = true; break;
  89     default: break;
  90   }
  91   guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
  92             UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
  93 
  94   // Power 8: Configure Data Stream Control Register.
  95   if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
  96     config_dscr();
  97   }
  98 
  99   if (!UseSIGTRAP) {
 100     MSG(TrapBasedICMissChecks);
 101     MSG(TrapBasedNotEntrantChecks);
 102     MSG(TrapBasedNullChecks);
 103     FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
 104     FLAG_SET_ERGO(bool, TrapBasedNullChecks,       false);
 105     FLAG_SET_ERGO(bool, TrapBasedICMissChecks,     false);
 106   }
 107 
 108 #ifdef COMPILER2
 109   if (!UseSIGTRAP) {
 110     MSG(TrapBasedRangeChecks);
 111     FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
 112   }
 113 
 114   // On Power6 test for section size.
 115   if (PowerArchitecturePPC64 == 6) {
 116     determine_section_size();
 117   // TODO: PPC port } else {
 118   // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
 119   }
 120 
 121   if (PowerArchitecturePPC64 >= 8) {
 122     if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
 123       FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
 124     }
 125   } else {
 126     if (SuperwordUseVSX) {
 127       warning("SuperwordUseVSX specified, but needs at least Power8.");
 128       FLAG_SET_DEFAULT(SuperwordUseVSX, false);
 129     }
 130   }
 131   MaxVectorSize = SuperwordUseVSX ? 16 : 8;
 132 
 133   if (PowerArchitecturePPC64 >= 9) {
 134     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
 135       FLAG_SET_ERGO(bool, UseCountTrailingZerosInstructionsPPC64, true);
 136     }
 137     if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
 138       FLAG_SET_ERGO(bool, UseCharacterCompareIntrinsics, true);
 139     }
 140   } else {
 141     if (UseCountTrailingZerosInstructionsPPC64) {
 142       warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
 143       FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
 144     }
 145   }
 146 #endif
 147 
 148   // Create and print feature-string.
 149   char buf[(num_features+1) * 16]; // Max 16 chars per feature.
 150   jio_snprintf(buf, sizeof(buf),
 151                "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 152                (has_fsqrt()   ? " fsqrt"   : ""),
 153                (has_isel()    ? " isel"    : ""),
 154                (has_lxarxeh() ? " lxarxeh" : ""),
 155                (has_cmpb()    ? " cmpb"    : ""),
 156                (has_popcntb() ? " popcntb" : ""),
 157                (has_popcntw() ? " popcntw" : ""),
 158                (has_fcfids()  ? " fcfids"  : ""),
 159                (has_vand()    ? " vand"    : ""),
 160                (has_lqarx()   ? " lqarx"   : ""),
 161                (has_vcipher() ? " aes"     : ""),
 162                (has_vpmsumb() ? " vpmsumb" : ""),
 163                (has_mfdscr()  ? " mfdscr"  : ""),
 164                (has_vsx()     ? " vsx"     : ""),
 165                (has_ldbrx()   ? " ldbrx"   : ""),
 166                (has_stdbrx()  ? " stdbrx"  : ""),
 167                (has_vshasig() ? " sha"     : ""),
 168                (has_tm()      ? " rtm"     : ""),
 169                (has_darn()    ? " darn"    : "")
 170                // Make sure number of %s matches num_features!
 171               );
 172   _features_string = os::strdup(buf);
 173   if (Verbose) {
 174     print_features();
 175   }
 176 
 177   // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
 178   // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
 179   _supports_cx8 = true;
 180 
 181   // Used by C1.
 182   _supports_atomic_getset4 = true;
 183   _supports_atomic_getadd4 = true;
 184   _supports_atomic_getset8 = true;
 185   _supports_atomic_getadd8 = true;
 186 
 187   UseSSE = 0; // Only on x86 and x64
 188 
 189   intx cache_line_size = L1_data_cache_line_size();
 190 
 191   if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
 192 
 193   if (AllocatePrefetchStyle == 4) {
 194     AllocatePrefetchStepSize = cache_line_size; // Need exact value.
 195     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
 196     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
 197   } else {
 198     if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
 199     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
 200     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
 201   }
 202 
 203   assert(AllocatePrefetchLines > 0, "invalid value");
 204   if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
 205     AllocatePrefetchLines = 1; // Conservative value.
 206   }
 207 
 208   if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
 209     AllocatePrefetchStyle = 1; // Fall back if inappropriate.
 210   }
 211 
 212   assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
 213 
 214   // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
 215   // In all other cases, the implementation uses only generally available instructions.
 216   if (!UseCRC32Intrinsics) {
 217     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 218       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 219     }
 220   }
 221 
 222   // Implementation does not use any of the vector instructions available with Power8.
 223   // Their exploitation is still pending (aka "work in progress").
 224   if (!UseCRC32CIntrinsics) {
 225     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 226       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 227     }
 228   }
 229 
 230   // TODO: Provide implementation.
 231   if (UseAdler32Intrinsics) {
 232     warning("Adler32Intrinsics not available on this CPU.");
 233     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 234   }
 235 
 236   // The AES intrinsic stubs require AES instruction support.
 237   if (has_vcipher()) {
 238     if (FLAG_IS_DEFAULT(UseAES)) {
 239       UseAES = true;
 240     }
 241   } else if (UseAES) {
 242     if (!FLAG_IS_DEFAULT(UseAES))
 243       warning("AES instructions are not available on this CPU");
 244     FLAG_SET_DEFAULT(UseAES, false);
 245   }
 246 
 247   if (UseAES && has_vcipher()) {
 248     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 249       UseAESIntrinsics = true;
 250     }
 251   } else if (UseAESIntrinsics) {
 252     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 253       warning("AES intrinsics are not available on this CPU");
 254     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 255   }
 256 
 257   if (UseAESCTRIntrinsics) {
 258     warning("AES/CTR intrinsics are not available on this CPU");
 259     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 260   }
 261 
 262   if (UseGHASHIntrinsics) {
 263     warning("GHASH intrinsics are not available on this CPU");
 264     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 265   }
 266 
 267   if (FLAG_IS_DEFAULT(UseFMA)) {
 268     FLAG_SET_DEFAULT(UseFMA, true);
 269   }
 270 
 271   if (has_vshasig()) {
 272     if (FLAG_IS_DEFAULT(UseSHA)) {
 273       UseSHA = true;
 274     }
 275   } else if (UseSHA) {
 276     if (!FLAG_IS_DEFAULT(UseSHA))
 277       warning("SHA instructions are not available on this CPU");
 278     FLAG_SET_DEFAULT(UseSHA, false);
 279   }
 280 
 281   if (UseSHA1Intrinsics) {
 282     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 283     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 284   }
 285 
 286   if (UseSHA && has_vshasig()) {
 287     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 288       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 289     }
 290   } else if (UseSHA256Intrinsics) {
 291     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 292     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 293   }
 294 
 295   if (UseSHA && has_vshasig()) {
 296     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 297       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 298     }
 299   } else if (UseSHA512Intrinsics) {
 300     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 301     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 302   }
 303 
 304   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 305     FLAG_SET_DEFAULT(UseSHA, false);
 306   }
 307 
 308   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
 309     UseSquareToLenIntrinsic = true;
 310   }
 311   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
 312     UseMulAddIntrinsic = true;
 313   }
 314   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 315     UseMultiplyToLenIntrinsic = true;
 316   }
 317   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 318     UseMontgomeryMultiplyIntrinsic = true;
 319   }
 320   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 321     UseMontgomerySquareIntrinsic = true;
 322   }
 323 
 324   if (UseVectorizedMismatchIntrinsic) {
 325     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 326     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 327   }
 328 
 329 
 330   // Adjust RTM (Restricted Transactional Memory) flags.
 331   if (UseRTMLocking) {
 332     // If CPU or OS do not support TM:
 333     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 334     // setting during arguments processing. See use_biased_locking().
 335     // VM_Version_init() is executed after UseBiasedLocking is used
 336     // in Thread::allocate().
 337     if (PowerArchitecturePPC64 < 8) {
 338       vm_exit_during_initialization("RTM instructions are not available on this CPU.");
 339     }
 340 
 341     if (!has_tm()) {
 342       vm_exit_during_initialization("RTM is not supported on this OS version.");
 343     }
 344   }
 345 
 346   if (UseRTMLocking) {
 347 #if INCLUDE_RTM_OPT
 348     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 349       // RTM locking should be used only for applications with
 350       // high lock contention. For now we do not use it by default.
 351       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 352     }
 353 #else
 354     // Only C2 does RTM locking optimization.
 355     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 356     // setting during arguments processing. See use_biased_locking().
 357     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 358 #endif
 359   } else { // !UseRTMLocking
 360     if (UseRTMForStackLocks) {
 361       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 362         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 363       }
 364       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 365     }
 366     if (UseRTMDeopt) {
 367       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 368     }
 369     if (PrintPreciseRTMLockingStatistics) {
 370       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 371     }
 372   }
 373 
 374   // This machine allows unaligned memory accesses
 375   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
 376     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
 377   }
 378 }
 379 
 380 bool VM_Version::use_biased_locking() {
 381 #if INCLUDE_RTM_OPT
 382   // RTM locking is most useful when there is high lock contention and
 383   // low data contention. With high lock contention the lock is usually
 384   // inflated and biased locking is not suitable for that case.
 385   // RTM locking code requires that biased locking is off.
 386   // Note: we can't switch off UseBiasedLocking in get_processor_features()
 387   // because it is used by Thread::allocate() which is called before
 388   // VM_Version::initialize().
 389   if (UseRTMLocking && UseBiasedLocking) {
 390     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
 391       FLAG_SET_DEFAULT(UseBiasedLocking, false);
 392     } else {
 393       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
 394       UseBiasedLocking = false;
 395     }
 396   }
 397 #endif
 398   return UseBiasedLocking;
 399 }
 400 
 401 void VM_Version::print_features() {
 402   tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
 403 }
 404 
 405 #ifdef COMPILER2
 406 // Determine section size on power6: If section size is 8 instructions,
 407 // there should be a difference between the two testloops of ~15 %. If
 408 // no difference is detected the section is assumed to be 32 instructions.
 409 void VM_Version::determine_section_size() {
 410 
 411   int unroll = 80;
 412 
 413   const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
 414 
 415   // Allocate space for the code.
 416   ResourceMark rm;
 417   CodeBuffer cb("detect_section_size", code_size, 0);
 418   MacroAssembler* a = new MacroAssembler(&cb);
 419 
 420   uint32_t *code = (uint32_t *)a->pc();
 421   // Emit code.
 422   void (*test1)() = (void(*)())(void *)a->function_entry();
 423 
 424   Label l1;
 425 
 426   a->li(R4, 1);
 427   a->sldi(R4, R4, 28);
 428   a->b(l1);
 429   a->align(CodeEntryAlignment);
 430 
 431   a->bind(l1);
 432 
 433   for (int i = 0; i < unroll; i++) {
 434     // Schleife 1
 435     // ------- sector 0 ------------
 436     // ;; 0
 437     a->nop();                   // 1
 438     a->fpnop0();                // 2
 439     a->fpnop1();                // 3
 440     a->addi(R4,R4, -1); // 4
 441 
 442     // ;;  1
 443     a->nop();                   // 5
 444     a->fmr(F6, F6);             // 6
 445     a->fmr(F7, F7);             // 7
 446     a->endgroup();              // 8
 447     // ------- sector 8 ------------
 448 
 449     // ;;  2
 450     a->nop();                   // 9
 451     a->nop();                   // 10
 452     a->fmr(F8, F8);             // 11
 453     a->fmr(F9, F9);             // 12
 454 
 455     // ;;  3
 456     a->nop();                   // 13
 457     a->fmr(F10, F10);           // 14
 458     a->fmr(F11, F11);           // 15
 459     a->endgroup();              // 16
 460     // -------- sector 16 -------------
 461 
 462     // ;;  4
 463     a->nop();                   // 17
 464     a->nop();                   // 18
 465     a->fmr(F15, F15);           // 19
 466     a->fmr(F16, F16);           // 20
 467 
 468     // ;;  5
 469     a->nop();                   // 21
 470     a->fmr(F17, F17);           // 22
 471     a->fmr(F18, F18);           // 23
 472     a->endgroup();              // 24
 473     // ------- sector 24  ------------
 474 
 475     // ;;  6
 476     a->nop();                   // 25
 477     a->nop();                   // 26
 478     a->fmr(F19, F19);           // 27
 479     a->fmr(F20, F20);           // 28
 480 
 481     // ;;  7
 482     a->nop();                   // 29
 483     a->fmr(F21, F21);           // 30
 484     a->fmr(F22, F22);           // 31
 485     a->brnop0();                // 32
 486 
 487     // ------- sector 32 ------------
 488   }
 489 
 490   // ;; 8
 491   a->cmpdi(CCR0, R4, unroll);   // 33
 492   a->bge(CCR0, l1);             // 34
 493   a->blr();
 494 
 495   // Emit code.
 496   void (*test2)() = (void(*)())(void *)a->function_entry();
 497   // uint32_t *code = (uint32_t *)a->pc();
 498 
 499   Label l2;
 500 
 501   a->li(R4, 1);
 502   a->sldi(R4, R4, 28);
 503   a->b(l2);
 504   a->align(CodeEntryAlignment);
 505 
 506   a->bind(l2);
 507 
 508   for (int i = 0; i < unroll; i++) {
 509     // Schleife 2
 510     // ------- sector 0 ------------
 511     // ;; 0
 512     a->brnop0();                  // 1
 513     a->nop();                     // 2
 514     //a->cmpdi(CCR0, R4, unroll);
 515     a->fpnop0();                  // 3
 516     a->fpnop1();                  // 4
 517     a->addi(R4,R4, -1);           // 5
 518 
 519     // ;; 1
 520 
 521     a->nop();                     // 6
 522     a->fmr(F6, F6);               // 7
 523     a->fmr(F7, F7);               // 8
 524     // ------- sector 8 ---------------
 525 
 526     // ;; 2
 527     a->endgroup();                // 9
 528 
 529     // ;; 3
 530     a->nop();                     // 10
 531     a->nop();                     // 11
 532     a->fmr(F8, F8);               // 12
 533 
 534     // ;; 4
 535     a->fmr(F9, F9);               // 13
 536     a->nop();                     // 14
 537     a->fmr(F10, F10);             // 15
 538 
 539     // ;; 5
 540     a->fmr(F11, F11);             // 16
 541     // -------- sector 16 -------------
 542 
 543     // ;; 6
 544     a->endgroup();                // 17
 545 
 546     // ;; 7
 547     a->nop();                     // 18
 548     a->nop();                     // 19
 549     a->fmr(F15, F15);             // 20
 550 
 551     // ;; 8
 552     a->fmr(F16, F16);             // 21
 553     a->nop();                     // 22
 554     a->fmr(F17, F17);             // 23
 555 
 556     // ;; 9
 557     a->fmr(F18, F18);             // 24
 558     // -------- sector 24 -------------
 559 
 560     // ;; 10
 561     a->endgroup();                // 25
 562 
 563     // ;; 11
 564     a->nop();                     // 26
 565     a->nop();                     // 27
 566     a->fmr(F19, F19);             // 28
 567 
 568     // ;; 12
 569     a->fmr(F20, F20);             // 29
 570     a->nop();                     // 30
 571     a->fmr(F21, F21);             // 31
 572 
 573     // ;; 13
 574     a->fmr(F22, F22);             // 32
 575   }
 576 
 577   // -------- sector 32 -------------
 578   // ;; 14
 579   a->cmpdi(CCR0, R4, unroll); // 33
 580   a->bge(CCR0, l2);           // 34
 581 
 582   a->blr();
 583   uint32_t *code_end = (uint32_t *)a->pc();
 584   a->flush();
 585 
 586   double loop1_seconds,loop2_seconds, rel_diff;
 587   uint64_t start1, stop1;
 588 
 589   start1 = os::current_thread_cpu_time(false);
 590   (*test1)();
 591   stop1 = os::current_thread_cpu_time(false);
 592   loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
 593 
 594 
 595   start1 = os::current_thread_cpu_time(false);
 596   (*test2)();
 597   stop1 = os::current_thread_cpu_time(false);
 598 
 599   loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
 600 
 601   rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
 602 
 603   if (PrintAssembly) {
 604     ttyLocker ttyl;
 605     tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 606     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 607     tty->print_cr("Time loop1 :%f", loop1_seconds);
 608     tty->print_cr("Time loop2 :%f", loop2_seconds);
 609     tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
 610 
 611     if (rel_diff > 12.0) {
 612       tty->print_cr("Section Size 8 Instructions");
 613     } else{
 614       tty->print_cr("Section Size 32 Instructions or Power5");
 615     }
 616   }
 617 
 618 #if 0 // TODO: PPC port
 619   // Set sector size (if not set explicitly).
 620   if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
 621     if (rel_diff > 12.0) {
 622       PdScheduling::power6SectorSize = 0x20;
 623     } else {
 624       PdScheduling::power6SectorSize = 0x80;
 625     }
 626   } else if (Power6SectorSize128PPC64) {
 627     PdScheduling::power6SectorSize = 0x80;
 628   } else {
 629     PdScheduling::power6SectorSize = 0x20;
 630   }
 631 #endif
 632   if (UsePower6SchedulerPPC64) Unimplemented();
 633 }
 634 #endif // COMPILER2
 635 
 636 void VM_Version::determine_features() {
 637 #if defined(ABI_ELFv2)
 638   // 1 InstWord per call for the blr instruction.
 639   const int code_size = (num_features+1+2*1)*BytesPerInstWord;
 640 #else
 641   // 7 InstWords for each call (function descriptor + blr instruction).
 642   const int code_size = (num_features+1+2*7)*BytesPerInstWord;
 643 #endif
 644   int features = 0;
 645 
 646   // create test area
 647   enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
 648   char test_area[BUFFER_SIZE];
 649   char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
 650 
 651   // Allocate space for the code.
 652   ResourceMark rm;
 653   CodeBuffer cb("detect_cpu_features", code_size, 0);
 654   MacroAssembler* a = new MacroAssembler(&cb);
 655 
 656   // Must be set to true so we can generate the test code.
 657   _features = VM_Version::all_features_m;
 658 
 659   // Emit code.
 660   void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
 661   uint32_t *code = (uint32_t *)a->pc();
 662   // Don't use R0 in ldarx.
 663   // Keep R3_ARG1 unmodified, it contains &field (see below).
 664   // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
 665   a->fsqrt(F3, F4);                            // code[0]  -> fsqrt_m
 666   a->fsqrts(F3, F4);                           // code[1]  -> fsqrts_m
 667   a->isel(R7, R5, R6, 0);                      // code[2]  -> isel_m
 668   a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3]  -> lxarx_m
 669   a->cmpb(R7, R5, R6);                         // code[4]  -> cmpb
 670   a->popcntb(R7, R5);                          // code[5]  -> popcntb
 671   a->popcntw(R7, R5);                          // code[6]  -> popcntw
 672   a->fcfids(F3, F4);                           // code[7]  -> fcfids
 673   a->vand(VR0, VR0, VR0);                      // code[8]  -> vand
 674   // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
 675   a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9]  -> lqarx_m
 676   a->vcipher(VR0, VR1, VR2);                   // code[10] -> vcipher
 677   a->vpmsumb(VR0, VR1, VR2);                   // code[11] -> vpmsumb
 678   a->mfdscr(R0);                               // code[12] -> mfdscr
 679   a->lxvd2x(VSR0, R3_ARG1);                    // code[13] -> vsx
 680   a->ldbrx(R7, R3_ARG1, R4_ARG2);              // code[14] -> ldbrx
 681   a->stdbrx(R7, R3_ARG1, R4_ARG2);             // code[15] -> stdbrx
 682   a->vshasigmaw(VR0, VR1, 1, 0xF);             // code[16] -> vshasig
 683   // rtm is determined by OS
 684   a->darn(R7);                                 // code[17] -> darn
 685   a->blr();
 686 
 687   // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
 688   void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
 689   a->dcbz(R3_ARG1); // R3_ARG1 = addr
 690   a->blr();
 691 
 692   uint32_t *code_end = (uint32_t *)a->pc();
 693   a->flush();
 694   _features = VM_Version::unknown_m;
 695 
 696   // Print the detection code.
 697   if (PrintAssembly) {
 698     ttyLocker ttyl;
 699     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 700     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 701   }
 702 
 703   // Measure cache line size.
 704   memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
 705   (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
 706   int count = 0; // count zeroed bytes
 707   for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
 708   guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
 709   _L1_data_cache_line_size = count;
 710 
 711   // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
 712   VM_Version::_is_determine_features_test_running = true;
 713   // We must align the first argument to 16 bytes because of the lqarx check.
 714   (*test)(align_up((address)mid_of_test_area, 16), 0);
 715   VM_Version::_is_determine_features_test_running = false;
 716 
 717   // determine which instructions are legal.
 718   int feature_cntr = 0;
 719   if (code[feature_cntr++]) features |= fsqrt_m;
 720   if (code[feature_cntr++]) features |= fsqrts_m;
 721   if (code[feature_cntr++]) features |= isel_m;
 722   if (code[feature_cntr++]) features |= lxarxeh_m;
 723   if (code[feature_cntr++]) features |= cmpb_m;
 724   if (code[feature_cntr++]) features |= popcntb_m;
 725   if (code[feature_cntr++]) features |= popcntw_m;
 726   if (code[feature_cntr++]) features |= fcfids_m;
 727   if (code[feature_cntr++]) features |= vand_m;
 728   if (code[feature_cntr++]) features |= lqarx_m;
 729   if (code[feature_cntr++]) features |= vcipher_m;
 730   if (code[feature_cntr++]) features |= vpmsumb_m;
 731   if (code[feature_cntr++]) features |= mfdscr_m;
 732   if (code[feature_cntr++]) features |= vsx_m;
 733   if (code[feature_cntr++]) features |= ldbrx_m;
 734   if (code[feature_cntr++]) features |= stdbrx_m;
 735   if (code[feature_cntr++]) features |= vshasig_m;
 736   // feature rtm_m is determined by OS
 737   if (code[feature_cntr++]) features |= darn_m;
 738 
 739   // Print the detection code.
 740   if (PrintAssembly) {
 741     ttyLocker ttyl;
 742     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
 743     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 744   }
 745 
 746   _features = features;
 747 
 748 #ifdef AIX
 749   // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
 750   // Actually, this is supported since AIX 7.1.. Unfortunately, this first
 751   // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
 752   // The Java property os.version, which is used in RTM tests to decide
 753   // whether the feature is available, only knows major and minor versions.
 754   // We don't want to change this property, as user code might depend on it.
 755   // So the tests can not check on subversion 3.30, and we only enable RTM
 756   // with AIX 7.2.
 757   if (has_lqarx()) { // POWER8 or above
 758     if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
 759       _features |= rtm_m;
 760     }
 761   }
 762 #endif
 763 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
 764   unsigned long auxv = getauxval(AT_HWCAP2);
 765 
 766   if (auxv & PPC_FEATURE2_HTM_NOSC) {
 767     if (auxv & PPC_FEATURE2_HAS_HTM) {
 768       // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
 769       // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
 770       // POWER9 DD2.1 NV has a few issues that need a couple of firmware
 771       // and kernel workarounds, so there is a new mode only supported
 772       // on non-virtualized P9 machines called HTM with no Suspend Mode).
 773       // TM on POWER9 D2.2+ NV is not supported at all by Linux.
 774       _features |= rtm_m;
 775     }
 776   }
 777 #endif
 778 }
 779 
 780 // Power 8: Configure Data Stream Control Register.
 781 void VM_Version::config_dscr() {
 782   // 7 InstWords for each call (function descriptor + blr instruction).
 783   const int code_size = (2+2*7)*BytesPerInstWord;
 784 
 785   // Allocate space for the code.
 786   ResourceMark rm;
 787   CodeBuffer cb("config_dscr", code_size, 0);
 788   MacroAssembler* a = new MacroAssembler(&cb);
 789 
 790   // Emit code.
 791   uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
 792   uint32_t *code = (uint32_t *)a->pc();
 793   a->mfdscr(R3);
 794   a->blr();
 795 
 796   void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
 797   a->mtdscr(R3);
 798   a->blr();
 799 
 800   uint32_t *code_end = (uint32_t *)a->pc();
 801   a->flush();
 802 
 803   // Print the detection code.
 804   if (PrintAssembly) {
 805     ttyLocker ttyl;
 806     tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
 807     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 808   }
 809 
 810   // Apply the configuration if needed.
 811   _dscr_val = (*get_dscr)();
 812   if (Verbose) {
 813     tty->print_cr("dscr value was 0x%lx" , _dscr_val);
 814   }
 815   bool change_requested = false;
 816   if (DSCR_PPC64 != (uintx)-1) {
 817     _dscr_val = DSCR_PPC64;
 818     change_requested = true;
 819   }
 820   if (DSCR_DPFD_PPC64 <= 7) {
 821     uint64_t mask = 0x7;
 822     if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
 823       _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
 824       change_requested = true;
 825     }
 826   }
 827   if (DSCR_URG_PPC64 <= 7) {
 828     uint64_t mask = 0x7 << 6;
 829     if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
 830       _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
 831       change_requested = true;
 832     }
 833   }
 834   if (change_requested) {
 835     (*set_dscr)(_dscr_val);
 836     if (Verbose) {
 837       tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
 838     }
 839   }
 840 }
 841 
 842 static uint64_t saved_features = 0;
 843 
 844 void VM_Version::allow_all() {
 845   saved_features = _features;
 846   _features      = all_features_m;
 847 }
 848 
 849 void VM_Version::revert() {
 850   _features = saved_features;
 851 }
--- EOF ---