1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2018, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "utilities/align.hpp"
36 #include "utilities/defaultStream.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "vm_version_ppc.hpp"
39
40 #include <sys/sysinfo.h>
41
42 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
43 #include <sys/auxv.h>
44
45 #ifndef PPC_FEATURE2_HTM_NOSC
46 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
47 #endif
48 #endif
49
50 bool VM_Version::_is_determine_features_test_running = false;
51 uint64_t VM_Version::_dscr_val = 0;
52
53 #define MSG(flag) \
54 if (flag && !FLAG_IS_DEFAULT(flag)) \
55 jio_fprintf(defaultStream::error_stream(), \
56 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
57 " -XX:+" #flag " will be disabled!\n");
58
59 void VM_Version::initialize() {
60
61 // Test which instructions are supported and measure cache line size.
62 determine_features();
63
64 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
65 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
66 if (VM_Version::has_lqarx()) {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
68 } else if (VM_Version::has_popcntw()) {
69 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
70 } else if (VM_Version::has_cmpb()) {
71 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
72 } else if (VM_Version::has_popcntb()) {
73 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
74 } else {
75 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
76 }
77 }
78
79 bool PowerArchitecturePPC64_ok = false;
80 switch (PowerArchitecturePPC64) {
81 case 8: if (!VM_Version::has_lqarx() ) break;
82 case 7: if (!VM_Version::has_popcntw()) break;
83 case 6: if (!VM_Version::has_cmpb() ) break;
84 case 5: if (!VM_Version::has_popcntb()) break;
85 case 0: PowerArchitecturePPC64_ok = true; break;
86 default: break;
87 }
88 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
89 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
90
91 // Power 8: Configure Data Stream Control Register.
92 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
93 config_dscr();
94 }
95
96 if (!UseSIGTRAP) {
97 MSG(TrapBasedICMissChecks);
98 MSG(TrapBasedNotEntrantChecks);
99 MSG(TrapBasedNullChecks);
100 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
101 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
102 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
103 }
104
105 #ifdef COMPILER2
106 if (!UseSIGTRAP) {
107 MSG(TrapBasedRangeChecks);
108 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
109 }
110
111 // On Power6 test for section size.
112 if (PowerArchitecturePPC64 == 6) {
113 determine_section_size();
114 // TODO: PPC port } else {
115 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
116 }
117
118 if (PowerArchitecturePPC64 >= 8) {
119 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
120 FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
121 }
122 } else {
123 if (SuperwordUseVSX) {
124 warning("SuperwordUseVSX specified, but needs at least Power8.");
125 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
126 }
127 }
128 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
129 #endif
130
131 // Create and print feature-string.
132 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
133 jio_snprintf(buf, sizeof(buf),
134 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
135 (has_fsqrt() ? " fsqrt" : ""),
136 (has_isel() ? " isel" : ""),
137 (has_lxarxeh() ? " lxarxeh" : ""),
138 (has_cmpb() ? " cmpb" : ""),
139 //(has_mftgpr()? " mftgpr" : ""),
140 (has_popcntb() ? " popcntb" : ""),
141 (has_popcntw() ? " popcntw" : ""),
142 (has_fcfids() ? " fcfids" : ""),
143 (has_vand() ? " vand" : ""),
144 (has_lqarx() ? " lqarx" : ""),
145 (has_vcipher() ? " aes" : ""),
146 (has_vpmsumb() ? " vpmsumb" : ""),
147 (has_mfdscr() ? " mfdscr" : ""),
148 (has_vsx() ? " vsx" : ""),
149 (has_ldbrx() ? " ldbrx" : ""),
150 (has_stdbrx() ? " stdbrx" : ""),
151 (has_vshasig() ? " sha" : ""),
152 (has_tm() ? " rtm" : "")
153 // Make sure number of %s matches num_features!
154 );
155 _features_string = os::strdup(buf);
156 if (Verbose) {
157 print_features();
158 }
159
160 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
161 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
162 _supports_cx8 = true;
163
164 // Used by C1.
165 _supports_atomic_getset4 = true;
166 _supports_atomic_getadd4 = true;
167 _supports_atomic_getset8 = true;
168 _supports_atomic_getadd8 = true;
169
170 UseSSE = 0; // Only on x86 and x64
171
172 intx cache_line_size = L1_data_cache_line_size();
173
174 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
175
176 if (AllocatePrefetchStyle == 4) {
177 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
178 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
179 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
180 } else {
181 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
182 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
183 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
184 }
185
186 assert(AllocatePrefetchLines > 0, "invalid value");
187 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
188 AllocatePrefetchLines = 1; // Conservative value.
189 }
190
191 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
192 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
193 }
194
195 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
196
197 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
198 // In all other cases, the implementation uses only generally available instructions.
199 if (!UseCRC32Intrinsics) {
200 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
201 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
202 }
203 }
204
205 // Implementation does not use any of the vector instructions available with Power8.
206 // Their exploitation is still pending (aka "work in progress").
207 if (!UseCRC32CIntrinsics) {
208 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
209 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
210 }
211 }
212
213 // TODO: Provide implementation.
214 if (UseAdler32Intrinsics) {
215 warning("Adler32Intrinsics not available on this CPU.");
216 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
217 }
218
219 // The AES intrinsic stubs require AES instruction support.
220 if (has_vcipher()) {
221 if (FLAG_IS_DEFAULT(UseAES)) {
222 UseAES = true;
223 }
224 } else if (UseAES) {
225 if (!FLAG_IS_DEFAULT(UseAES))
226 warning("AES instructions are not available on this CPU");
227 FLAG_SET_DEFAULT(UseAES, false);
228 }
229
230 if (UseAES && has_vcipher()) {
231 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
232 UseAESIntrinsics = true;
233 }
234 } else if (UseAESIntrinsics) {
235 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
236 warning("AES intrinsics are not available on this CPU");
237 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
238 }
239
240 if (UseAESCTRIntrinsics) {
241 warning("AES/CTR intrinsics are not available on this CPU");
242 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
243 }
244
245 if (UseGHASHIntrinsics) {
246 warning("GHASH intrinsics are not available on this CPU");
247 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
248 }
249
250 if (FLAG_IS_DEFAULT(UseFMA)) {
251 FLAG_SET_DEFAULT(UseFMA, true);
252 }
253
254 if (has_vshasig()) {
255 if (FLAG_IS_DEFAULT(UseSHA)) {
256 UseSHA = true;
257 }
258 } else if (UseSHA) {
259 if (!FLAG_IS_DEFAULT(UseSHA))
260 warning("SHA instructions are not available on this CPU");
261 FLAG_SET_DEFAULT(UseSHA, false);
262 }
263
264 if (UseSHA1Intrinsics) {
265 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
266 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
267 }
268
269 if (UseSHA && has_vshasig()) {
270 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
271 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
272 }
273 } else if (UseSHA256Intrinsics) {
274 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
275 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
276 }
277
278 if (UseSHA && has_vshasig()) {
279 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
280 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
281 }
282 } else if (UseSHA512Intrinsics) {
283 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
284 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
285 }
286
287 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
288 FLAG_SET_DEFAULT(UseSHA, false);
289 }
290
291 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
292 UseSquareToLenIntrinsic = true;
293 }
294 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
295 UseMulAddIntrinsic = true;
296 }
297 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
298 UseMultiplyToLenIntrinsic = true;
299 }
300 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
301 UseMontgomeryMultiplyIntrinsic = true;
302 }
303 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
304 UseMontgomerySquareIntrinsic = true;
305 }
306
307 if (UseVectorizedMismatchIntrinsic) {
308 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
309 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
310 }
311
312
313 // Adjust RTM (Restricted Transactional Memory) flags.
314 if (UseRTMLocking) {
315 // If CPU or OS do not support TM:
316 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
317 // setting during arguments processing. See use_biased_locking().
318 // VM_Version_init() is executed after UseBiasedLocking is used
319 // in Thread::allocate().
320 if (PowerArchitecturePPC64 < 8) {
321 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
322 }
323
324 if (!has_tm()) {
325 vm_exit_during_initialization("RTM is not supported on this OS version.");
326 }
327 }
328
329 if (UseRTMLocking) {
330 #if INCLUDE_RTM_OPT
331 if (!UnlockExperimentalVMOptions) {
332 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
333 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
334 } else {
335 warning("UseRTMLocking is only available as experimental option on this platform.");
336 }
337 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
338 // RTM locking should be used only for applications with
339 // high lock contention. For now we do not use it by default.
340 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
341 }
342 #else
343 // Only C2 does RTM locking optimization.
344 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
345 // setting during arguments processing. See use_biased_locking().
346 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
347 #endif
348 } else { // !UseRTMLocking
349 if (UseRTMForStackLocks) {
350 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
351 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
352 }
353 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
354 }
355 if (UseRTMDeopt) {
356 FLAG_SET_DEFAULT(UseRTMDeopt, false);
357 }
358 if (PrintPreciseRTMLockingStatistics) {
359 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
360 }
361 }
362
363 // This machine allows unaligned memory accesses
364 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
365 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
366 }
367 }
368
369 bool VM_Version::use_biased_locking() {
370 #if INCLUDE_RTM_OPT
371 // RTM locking is most useful when there is high lock contention and
372 // low data contention. With high lock contention the lock is usually
373 // inflated and biased locking is not suitable for that case.
374 // RTM locking code requires that biased locking is off.
375 // Note: we can't switch off UseBiasedLocking in get_processor_features()
376 // because it is used by Thread::allocate() which is called before
377 // VM_Version::initialize().
378 if (UseRTMLocking && UseBiasedLocking) {
379 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
380 FLAG_SET_DEFAULT(UseBiasedLocking, false);
381 } else {
382 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
383 UseBiasedLocking = false;
384 }
385 }
386 #endif
387 return UseBiasedLocking;
388 }
389
390 void VM_Version::print_features() {
391 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
392 }
393
394 #ifdef COMPILER2
395 // Determine section size on power6: If section size is 8 instructions,
396 // there should be a difference between the two testloops of ~15 %. If
397 // no difference is detected the section is assumed to be 32 instructions.
398 void VM_Version::determine_section_size() {
399
400 int unroll = 80;
401
402 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
403
404 // Allocate space for the code.
405 ResourceMark rm;
406 CodeBuffer cb("detect_section_size", code_size, 0);
407 MacroAssembler* a = new MacroAssembler(&cb);
408
409 uint32_t *code = (uint32_t *)a->pc();
410 // Emit code.
411 void (*test1)() = (void(*)())(void *)a->function_entry();
412
413 Label l1;
414
415 a->li(R4, 1);
416 a->sldi(R4, R4, 28);
417 a->b(l1);
418 a->align(CodeEntryAlignment);
419
420 a->bind(l1);
421
422 for (int i = 0; i < unroll; i++) {
423 // Schleife 1
424 // ------- sector 0 ------------
425 // ;; 0
426 a->nop(); // 1
427 a->fpnop0(); // 2
428 a->fpnop1(); // 3
429 a->addi(R4,R4, -1); // 4
430
431 // ;; 1
432 a->nop(); // 5
433 a->fmr(F6, F6); // 6
434 a->fmr(F7, F7); // 7
435 a->endgroup(); // 8
436 // ------- sector 8 ------------
437
438 // ;; 2
439 a->nop(); // 9
440 a->nop(); // 10
441 a->fmr(F8, F8); // 11
442 a->fmr(F9, F9); // 12
443
444 // ;; 3
445 a->nop(); // 13
446 a->fmr(F10, F10); // 14
447 a->fmr(F11, F11); // 15
448 a->endgroup(); // 16
449 // -------- sector 16 -------------
450
451 // ;; 4
452 a->nop(); // 17
453 a->nop(); // 18
454 a->fmr(F15, F15); // 19
455 a->fmr(F16, F16); // 20
456
457 // ;; 5
458 a->nop(); // 21
459 a->fmr(F17, F17); // 22
460 a->fmr(F18, F18); // 23
461 a->endgroup(); // 24
462 // ------- sector 24 ------------
463
464 // ;; 6
465 a->nop(); // 25
466 a->nop(); // 26
467 a->fmr(F19, F19); // 27
468 a->fmr(F20, F20); // 28
469
470 // ;; 7
471 a->nop(); // 29
472 a->fmr(F21, F21); // 30
473 a->fmr(F22, F22); // 31
474 a->brnop0(); // 32
475
476 // ------- sector 32 ------------
477 }
478
479 // ;; 8
480 a->cmpdi(CCR0, R4, unroll); // 33
481 a->bge(CCR0, l1); // 34
482 a->blr();
483
484 // Emit code.
485 void (*test2)() = (void(*)())(void *)a->function_entry();
486 // uint32_t *code = (uint32_t *)a->pc();
487
488 Label l2;
489
490 a->li(R4, 1);
491 a->sldi(R4, R4, 28);
492 a->b(l2);
493 a->align(CodeEntryAlignment);
494
495 a->bind(l2);
496
497 for (int i = 0; i < unroll; i++) {
498 // Schleife 2
499 // ------- sector 0 ------------
500 // ;; 0
501 a->brnop0(); // 1
502 a->nop(); // 2
503 //a->cmpdi(CCR0, R4, unroll);
504 a->fpnop0(); // 3
505 a->fpnop1(); // 4
506 a->addi(R4,R4, -1); // 5
507
508 // ;; 1
509
510 a->nop(); // 6
511 a->fmr(F6, F6); // 7
512 a->fmr(F7, F7); // 8
513 // ------- sector 8 ---------------
514
515 // ;; 2
516 a->endgroup(); // 9
517
518 // ;; 3
519 a->nop(); // 10
520 a->nop(); // 11
521 a->fmr(F8, F8); // 12
522
523 // ;; 4
524 a->fmr(F9, F9); // 13
525 a->nop(); // 14
526 a->fmr(F10, F10); // 15
527
528 // ;; 5
529 a->fmr(F11, F11); // 16
530 // -------- sector 16 -------------
531
532 // ;; 6
533 a->endgroup(); // 17
534
535 // ;; 7
536 a->nop(); // 18
537 a->nop(); // 19
538 a->fmr(F15, F15); // 20
539
540 // ;; 8
541 a->fmr(F16, F16); // 21
542 a->nop(); // 22
543 a->fmr(F17, F17); // 23
544
545 // ;; 9
546 a->fmr(F18, F18); // 24
547 // -------- sector 24 -------------
548
549 // ;; 10
550 a->endgroup(); // 25
551
552 // ;; 11
553 a->nop(); // 26
554 a->nop(); // 27
555 a->fmr(F19, F19); // 28
556
557 // ;; 12
558 a->fmr(F20, F20); // 29
559 a->nop(); // 30
560 a->fmr(F21, F21); // 31
561
562 // ;; 13
563 a->fmr(F22, F22); // 32
564 }
565
566 // -------- sector 32 -------------
567 // ;; 14
568 a->cmpdi(CCR0, R4, unroll); // 33
569 a->bge(CCR0, l2); // 34
570
571 a->blr();
572 uint32_t *code_end = (uint32_t *)a->pc();
573 a->flush();
574
575 double loop1_seconds,loop2_seconds, rel_diff;
576 uint64_t start1, stop1;
577
578 start1 = os::current_thread_cpu_time(false);
579 (*test1)();
580 stop1 = os::current_thread_cpu_time(false);
581 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
582
583
584 start1 = os::current_thread_cpu_time(false);
585 (*test2)();
586 stop1 = os::current_thread_cpu_time(false);
587
588 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
589
590 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
591
592 if (PrintAssembly) {
593 ttyLocker ttyl;
594 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
595 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
596 tty->print_cr("Time loop1 :%f", loop1_seconds);
597 tty->print_cr("Time loop2 :%f", loop2_seconds);
598 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
599
600 if (rel_diff > 12.0) {
601 tty->print_cr("Section Size 8 Instructions");
602 } else{
603 tty->print_cr("Section Size 32 Instructions or Power5");
604 }
605 }
606
607 #if 0 // TODO: PPC port
608 // Set sector size (if not set explicitly).
609 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
610 if (rel_diff > 12.0) {
611 PdScheduling::power6SectorSize = 0x20;
612 } else {
613 PdScheduling::power6SectorSize = 0x80;
614 }
615 } else if (Power6SectorSize128PPC64) {
616 PdScheduling::power6SectorSize = 0x80;
617 } else {
618 PdScheduling::power6SectorSize = 0x20;
619 }
620 #endif
621 if (UsePower6SchedulerPPC64) Unimplemented();
622 }
623 #endif // COMPILER2
624
625 void VM_Version::determine_features() {
626 #if defined(ABI_ELFv2)
627 // 1 InstWord per call for the blr instruction.
628 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
629 #else
630 // 7 InstWords for each call (function descriptor + blr instruction).
631 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
632 #endif
633 int features = 0;
634
635 // create test area
636 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
637 char test_area[BUFFER_SIZE];
638 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
639
640 // Allocate space for the code.
641 ResourceMark rm;
642 CodeBuffer cb("detect_cpu_features", code_size, 0);
643 MacroAssembler* a = new MacroAssembler(&cb);
644
645 // Must be set to true so we can generate the test code.
646 _features = VM_Version::all_features_m;
647
648 // Emit code.
649 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
650 uint32_t *code = (uint32_t *)a->pc();
651 // Don't use R0 in ldarx.
652 // Keep R3_ARG1 unmodified, it contains &field (see below).
653 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
654 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
655 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
656 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
657 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
658 a->cmpb(R7, R5, R6); // code[4] -> cmpb
659 a->popcntb(R7, R5); // code[5] -> popcntb
660 a->popcntw(R7, R5); // code[6] -> popcntw
661 a->fcfids(F3, F4); // code[7] -> fcfids
662 a->vand(VR0, VR0, VR0); // code[8] -> vand
663 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
664 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
665 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
666 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
667 a->mfdscr(R0); // code[12] -> mfdscr
668 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
669 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
670 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
671 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
672 a->blr();
673
674 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
675 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
676 a->dcbz(R3_ARG1); // R3_ARG1 = addr
677 a->blr();
678
679 uint32_t *code_end = (uint32_t *)a->pc();
680 a->flush();
681 _features = VM_Version::unknown_m;
682
683 // Print the detection code.
684 if (PrintAssembly) {
685 ttyLocker ttyl;
686 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
687 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
688 }
689
690 // Measure cache line size.
691 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
692 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
693 int count = 0; // count zeroed bytes
694 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
695 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
696 _L1_data_cache_line_size = count;
697
698 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
699 VM_Version::_is_determine_features_test_running = true;
700 // We must align the first argument to 16 bytes because of the lqarx check.
701 (*test)(align_up((address)mid_of_test_area, 16), 0);
702 VM_Version::_is_determine_features_test_running = false;
703
704 // determine which instructions are legal.
705 int feature_cntr = 0;
706 if (code[feature_cntr++]) features |= fsqrt_m;
707 if (code[feature_cntr++]) features |= fsqrts_m;
708 if (code[feature_cntr++]) features |= isel_m;
709 if (code[feature_cntr++]) features |= lxarxeh_m;
710 if (code[feature_cntr++]) features |= cmpb_m;
711 if (code[feature_cntr++]) features |= popcntb_m;
712 if (code[feature_cntr++]) features |= popcntw_m;
713 if (code[feature_cntr++]) features |= fcfids_m;
714 if (code[feature_cntr++]) features |= vand_m;
715 if (code[feature_cntr++]) features |= lqarx_m;
716 if (code[feature_cntr++]) features |= vcipher_m;
717 if (code[feature_cntr++]) features |= vpmsumb_m;
718 if (code[feature_cntr++]) features |= mfdscr_m;
719 if (code[feature_cntr++]) features |= vsx_m;
720 if (code[feature_cntr++]) features |= ldbrx_m;
721 if (code[feature_cntr++]) features |= stdbrx_m;
722 if (code[feature_cntr++]) features |= vshasig_m;
723
724 // Print the detection code.
725 if (PrintAssembly) {
726 ttyLocker ttyl;
727 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
728 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
729 }
730
731 #ifdef AIX
732 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
733 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
734 // The Java property os.version, which is used in RTM tests to decide
735 // whether the feature is available, only knows major and minor versions.
736 // We don't want to change this property, as user code might depend on it.
737 // So the tests can not check on subversion 3.30, and we only enable RTM
738 // with AIX 7.2.
739 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
740 features |= rtm_m;
741 }
742 #endif
743 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
744 unsigned long auxv = getauxval(AT_HWCAP2);
745
746 if (auxv & PPC_FEATURE2_HTM_NOSC) {
747 if (auxv & PPC_FEATURE2_HAS_HTM) {
748 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
749 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
750 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
751 // and kernel workarounds, so there is a new mode only supported
752 // on non-virtualized P9 machines called HTM with no Suspend Mode).
753 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
754 features |= rtm_m;
755 }
756 }
757 #endif
758
759 _features = features;
760 }
761
762 // Power 8: Configure Data Stream Control Register.
763 void VM_Version::config_dscr() {
764 // 7 InstWords for each call (function descriptor + blr instruction).
765 const int code_size = (2+2*7)*BytesPerInstWord;
766
767 // Allocate space for the code.
768 ResourceMark rm;
769 CodeBuffer cb("config_dscr", code_size, 0);
770 MacroAssembler* a = new MacroAssembler(&cb);
771
772 // Emit code.
773 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
774 uint32_t *code = (uint32_t *)a->pc();
775 a->mfdscr(R3);
776 a->blr();
777
778 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
779 a->mtdscr(R3);
780 a->blr();
781
782 uint32_t *code_end = (uint32_t *)a->pc();
783 a->flush();
784
785 // Print the detection code.
786 if (PrintAssembly) {
787 ttyLocker ttyl;
788 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
789 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
790 }
791
792 // Apply the configuration if needed.
793 _dscr_val = (*get_dscr)();
794 if (Verbose) {
795 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
796 }
797 bool change_requested = false;
798 if (DSCR_PPC64 != (uintx)-1) {
799 _dscr_val = DSCR_PPC64;
800 change_requested = true;
801 }
802 if (DSCR_DPFD_PPC64 <= 7) {
803 uint64_t mask = 0x7;
804 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
805 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
806 change_requested = true;
807 }
808 }
809 if (DSCR_URG_PPC64 <= 7) {
810 uint64_t mask = 0x7 << 6;
811 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
812 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
813 change_requested = true;
814 }
815 }
816 if (change_requested) {
817 (*set_dscr)(_dscr_val);
818 if (Verbose) {
819 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
820 }
821 }
822 }
823
824 static uint64_t saved_features = 0;
825
826 void VM_Version::allow_all() {
827 saved_features = _features;
828 _features = all_features_m;
829 }
830
831 void VM_Version::revert() {
832 _features = saved_features;
833 }