1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2018, SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "jvm.h" 28 #include "asm/assembler.inline.hpp" 29 #include "asm/macroAssembler.inline.hpp" 30 #include "compiler/disassembler.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "runtime/java.hpp" 33 #include "runtime/os.hpp" 34 #include "runtime/stubCodeGenerator.hpp" 35 #include "utilities/align.hpp" 36 #include "utilities/defaultStream.hpp" 37 #include "utilities/globalDefinitions.hpp" 38 #include "vm_version_ppc.hpp" 39 40 #include <sys/sysinfo.h> 41 42 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN) 43 #include <sys/auxv.h> 44 45 #ifndef PPC_FEATURE2_HTM_NOSC 46 #define PPC_FEATURE2_HTM_NOSC (1 << 24) 47 #endif 48 #endif 49 50 bool VM_Version::_is_determine_features_test_running = false; 51 uint64_t VM_Version::_dscr_val = 0; 52 53 #define MSG(flag) \ 54 if (flag && !FLAG_IS_DEFAULT(flag)) \ 55 jio_fprintf(defaultStream::error_stream(), \ 56 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 57 " -XX:+" #flag " will be disabled!\n"); 58 59 void VM_Version::initialize() { 60 61 // Test which instructions are supported and measure cache line size. 62 determine_features(); 63 64 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 65 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 66 if (VM_Version::has_lqarx()) { 67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 68 } else if (VM_Version::has_popcntw()) { 69 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 70 } else if (VM_Version::has_cmpb()) { 71 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 72 } else if (VM_Version::has_popcntb()) { 73 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 74 } else { 75 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 76 } 77 } 78 79 bool PowerArchitecturePPC64_ok = false; 80 switch (PowerArchitecturePPC64) { 81 case 8: if (!VM_Version::has_lqarx() ) break; 82 case 7: if (!VM_Version::has_popcntw()) break; 83 case 6: if (!VM_Version::has_cmpb() ) break; 84 case 5: if (!VM_Version::has_popcntb()) break; 85 case 0: PowerArchitecturePPC64_ok = true; break; 86 default: break; 87 } 88 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to " 89 UINTX_FORMAT " on this machine", PowerArchitecturePPC64); 90 91 // Power 8: Configure Data Stream Control Register. 92 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) { 93 config_dscr(); 94 } 95 96 if (!UseSIGTRAP) { 97 MSG(TrapBasedICMissChecks); 98 MSG(TrapBasedNotEntrantChecks); 99 MSG(TrapBasedNullChecks); 100 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 101 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 102 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 103 } 104 105 #ifdef COMPILER2 106 if (!UseSIGTRAP) { 107 MSG(TrapBasedRangeChecks); 108 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 109 } 110 111 // On Power6 test for section size. 112 if (PowerArchitecturePPC64 == 6) { 113 determine_section_size(); 114 // TODO: PPC port } else { 115 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 116 } 117 118 if (PowerArchitecturePPC64 >= 8) { 119 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) { 120 FLAG_SET_ERGO(bool, SuperwordUseVSX, true); 121 } 122 } else { 123 if (SuperwordUseVSX) { 124 warning("SuperwordUseVSX specified, but needs at least Power8."); 125 FLAG_SET_DEFAULT(SuperwordUseVSX, false); 126 } 127 } 128 MaxVectorSize = SuperwordUseVSX ? 16 : 8; 129 #endif 130 131 // Create and print feature-string. 132 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 133 jio_snprintf(buf, sizeof(buf), 134 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 135 (has_fsqrt() ? " fsqrt" : ""), 136 (has_isel() ? " isel" : ""), 137 (has_lxarxeh() ? " lxarxeh" : ""), 138 (has_cmpb() ? " cmpb" : ""), 139 //(has_mftgpr()? " mftgpr" : ""), 140 (has_popcntb() ? " popcntb" : ""), 141 (has_popcntw() ? " popcntw" : ""), 142 (has_fcfids() ? " fcfids" : ""), 143 (has_vand() ? " vand" : ""), 144 (has_lqarx() ? " lqarx" : ""), 145 (has_vcipher() ? " aes" : ""), 146 (has_vpmsumb() ? " vpmsumb" : ""), 147 (has_mfdscr() ? " mfdscr" : ""), 148 (has_vsx() ? " vsx" : ""), 149 (has_ldbrx() ? " ldbrx" : ""), 150 (has_stdbrx() ? " stdbrx" : ""), 151 (has_vshasig() ? " sha" : "") 152 // Make sure number of %s matches num_features! 153 ); 154 _features_string = os::strdup(buf); 155 if (Verbose) { 156 print_features(); 157 } 158 159 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg) 160 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 161 _supports_cx8 = true; 162 163 // Used by C1. 164 _supports_atomic_getset4 = true; 165 _supports_atomic_getadd4 = true; 166 _supports_atomic_getset8 = true; 167 _supports_atomic_getadd8 = true; 168 169 UseSSE = 0; // Only on x86 and x64 170 171 intx cache_line_size = L1_data_cache_line_size(); 172 173 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 174 175 if (AllocatePrefetchStyle == 4) { 176 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 177 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 178 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 179 } else { 180 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 181 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 182 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 183 } 184 185 assert(AllocatePrefetchLines > 0, "invalid value"); 186 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 187 AllocatePrefetchLines = 1; // Conservative value. 188 } 189 190 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 191 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 192 } 193 194 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 195 196 // If running on Power8 or newer hardware, the implementation uses the available vector instructions. 197 // In all other cases, the implementation uses only generally available instructions. 198 if (!UseCRC32Intrinsics) { 199 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 200 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 201 } 202 } 203 204 // Implementation does not use any of the vector instructions available with Power8. 205 // Their exploitation is still pending (aka "work in progress"). 206 if (!UseCRC32CIntrinsics) { 207 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 208 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 209 } 210 } 211 212 // TODO: Provide implementation. 213 if (UseAdler32Intrinsics) { 214 warning("Adler32Intrinsics not available on this CPU."); 215 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 216 } 217 218 // The AES intrinsic stubs require AES instruction support. 219 if (has_vcipher()) { 220 if (FLAG_IS_DEFAULT(UseAES)) { 221 UseAES = true; 222 } 223 } else if (UseAES) { 224 if (!FLAG_IS_DEFAULT(UseAES)) 225 warning("AES instructions are not available on this CPU"); 226 FLAG_SET_DEFAULT(UseAES, false); 227 } 228 229 if (UseAES && has_vcipher()) { 230 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 231 UseAESIntrinsics = true; 232 } 233 } else if (UseAESIntrinsics) { 234 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 235 warning("AES intrinsics are not available on this CPU"); 236 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 237 } 238 239 if (UseAESCTRIntrinsics) { 240 warning("AES/CTR intrinsics are not available on this CPU"); 241 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 242 } 243 244 if (UseGHASHIntrinsics) { 245 warning("GHASH intrinsics are not available on this CPU"); 246 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 247 } 248 249 if (FLAG_IS_DEFAULT(UseFMA)) { 250 FLAG_SET_DEFAULT(UseFMA, true); 251 } 252 253 if (has_vshasig()) { 254 if (FLAG_IS_DEFAULT(UseSHA)) { 255 UseSHA = true; 256 } 257 } else if (UseSHA) { 258 if (!FLAG_IS_DEFAULT(UseSHA)) 259 warning("SHA instructions are not available on this CPU"); 260 FLAG_SET_DEFAULT(UseSHA, false); 261 } 262 263 if (UseSHA1Intrinsics) { 264 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 265 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 266 } 267 268 if (UseSHA && has_vshasig()) { 269 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 270 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 271 } 272 } else if (UseSHA256Intrinsics) { 273 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 274 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 275 } 276 277 if (UseSHA && has_vshasig()) { 278 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 279 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 280 } 281 } else if (UseSHA512Intrinsics) { 282 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 283 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 284 } 285 286 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 287 FLAG_SET_DEFAULT(UseSHA, false); 288 } 289 290 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 291 UseSquareToLenIntrinsic = true; 292 } 293 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 294 UseMulAddIntrinsic = true; 295 } 296 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 297 UseMultiplyToLenIntrinsic = true; 298 } 299 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 300 UseMontgomeryMultiplyIntrinsic = true; 301 } 302 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 303 UseMontgomerySquareIntrinsic = true; 304 } 305 306 if (UseVectorizedMismatchIntrinsic) { 307 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 308 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 309 } 310 311 312 // Adjust RTM (Restricted Transactional Memory) flags. 313 if (UseRTMLocking) { 314 // If CPU or OS do not support TM: 315 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 316 // setting during arguments processing. See use_biased_locking(). 317 // VM_Version_init() is executed after UseBiasedLocking is used 318 // in Thread::allocate(). 319 if (PowerArchitecturePPC64 < 8) { 320 vm_exit_during_initialization("RTM instructions are not available on this CPU."); 321 } 322 bool os_support_tm = false; 323 #ifdef AIX 324 // Actually, this is supported since AIX 7.1.. Unfortunately, this first 325 // contained bugs, so that it can only be enabled after AIX 7.1.3.30. 326 // The Java property os.version, which is used in RTM tests to decide 327 // whether the feature is available, only knows major and minor versions. 328 // We don't want to change this property, as user code might depend on it. 329 // So the tests can not check on subversion 3.30, and we only enable RTM 330 // with AIX 7.2. 331 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2. 332 os_support_tm = true; 333 } 334 #endif 335 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN) 336 unsigned long auxv = getauxval(AT_HWCAP2); 337 338 if (auxv & PPC_FEATURE2_HTM_NOSC) { 339 if (auxv & PPC_FEATURE2_HAS_HTM) { 340 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM. 341 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on 342 // POWER9 DD2.1 NV has a few issues that need a couple of firmware 343 // and kernel workarounds, so there is a new mode only supported 344 // on non-virtualized P9 machines called HTM with no Suspend Mode). 345 // TM on POWER9 D2.2+ NV is not supported at all by Linux. 346 os_support_tm = true; 347 } 348 } 349 #endif 350 if (!os_support_tm) { 351 vm_exit_during_initialization("RTM is not supported on this OS version."); 352 } 353 } 354 355 if (UseRTMLocking) { 356 #if INCLUDE_RTM_OPT 357 if (!UnlockExperimentalVMOptions) { 358 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. " 359 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 360 } else { 361 warning("UseRTMLocking is only available as experimental option on this platform."); 362 } 363 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 364 // RTM locking should be used only for applications with 365 // high lock contention. For now we do not use it by default. 366 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 367 } 368 #else 369 // Only C2 does RTM locking optimization. 370 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 371 // setting during arguments processing. See use_biased_locking(). 372 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 373 #endif 374 } else { // !UseRTMLocking 375 if (UseRTMForStackLocks) { 376 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 377 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 378 } 379 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 380 } 381 if (UseRTMDeopt) { 382 FLAG_SET_DEFAULT(UseRTMDeopt, false); 383 } 384 if (PrintPreciseRTMLockingStatistics) { 385 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 386 } 387 } 388 389 // This machine allows unaligned memory accesses 390 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 391 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 392 } 393 } 394 395 bool VM_Version::use_biased_locking() { 396 #if INCLUDE_RTM_OPT 397 // RTM locking is most useful when there is high lock contention and 398 // low data contention. With high lock contention the lock is usually 399 // inflated and biased locking is not suitable for that case. 400 // RTM locking code requires that biased locking is off. 401 // Note: we can't switch off UseBiasedLocking in get_processor_features() 402 // because it is used by Thread::allocate() which is called before 403 // VM_Version::initialize(). 404 if (UseRTMLocking && UseBiasedLocking) { 405 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 406 FLAG_SET_DEFAULT(UseBiasedLocking, false); 407 } else { 408 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 409 UseBiasedLocking = false; 410 } 411 } 412 #endif 413 return UseBiasedLocking; 414 } 415 416 void VM_Version::print_features() { 417 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size()); 418 } 419 420 #ifdef COMPILER2 421 // Determine section size on power6: If section size is 8 instructions, 422 // there should be a difference between the two testloops of ~15 %. If 423 // no difference is detected the section is assumed to be 32 instructions. 424 void VM_Version::determine_section_size() { 425 426 int unroll = 80; 427 428 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 429 430 // Allocate space for the code. 431 ResourceMark rm; 432 CodeBuffer cb("detect_section_size", code_size, 0); 433 MacroAssembler* a = new MacroAssembler(&cb); 434 435 uint32_t *code = (uint32_t *)a->pc(); 436 // Emit code. 437 void (*test1)() = (void(*)())(void *)a->function_entry(); 438 439 Label l1; 440 441 a->li(R4, 1); 442 a->sldi(R4, R4, 28); 443 a->b(l1); 444 a->align(CodeEntryAlignment); 445 446 a->bind(l1); 447 448 for (int i = 0; i < unroll; i++) { 449 // Schleife 1 450 // ------- sector 0 ------------ 451 // ;; 0 452 a->nop(); // 1 453 a->fpnop0(); // 2 454 a->fpnop1(); // 3 455 a->addi(R4,R4, -1); // 4 456 457 // ;; 1 458 a->nop(); // 5 459 a->fmr(F6, F6); // 6 460 a->fmr(F7, F7); // 7 461 a->endgroup(); // 8 462 // ------- sector 8 ------------ 463 464 // ;; 2 465 a->nop(); // 9 466 a->nop(); // 10 467 a->fmr(F8, F8); // 11 468 a->fmr(F9, F9); // 12 469 470 // ;; 3 471 a->nop(); // 13 472 a->fmr(F10, F10); // 14 473 a->fmr(F11, F11); // 15 474 a->endgroup(); // 16 475 // -------- sector 16 ------------- 476 477 // ;; 4 478 a->nop(); // 17 479 a->nop(); // 18 480 a->fmr(F15, F15); // 19 481 a->fmr(F16, F16); // 20 482 483 // ;; 5 484 a->nop(); // 21 485 a->fmr(F17, F17); // 22 486 a->fmr(F18, F18); // 23 487 a->endgroup(); // 24 488 // ------- sector 24 ------------ 489 490 // ;; 6 491 a->nop(); // 25 492 a->nop(); // 26 493 a->fmr(F19, F19); // 27 494 a->fmr(F20, F20); // 28 495 496 // ;; 7 497 a->nop(); // 29 498 a->fmr(F21, F21); // 30 499 a->fmr(F22, F22); // 31 500 a->brnop0(); // 32 501 502 // ------- sector 32 ------------ 503 } 504 505 // ;; 8 506 a->cmpdi(CCR0, R4, unroll); // 33 507 a->bge(CCR0, l1); // 34 508 a->blr(); 509 510 // Emit code. 511 void (*test2)() = (void(*)())(void *)a->function_entry(); 512 // uint32_t *code = (uint32_t *)a->pc(); 513 514 Label l2; 515 516 a->li(R4, 1); 517 a->sldi(R4, R4, 28); 518 a->b(l2); 519 a->align(CodeEntryAlignment); 520 521 a->bind(l2); 522 523 for (int i = 0; i < unroll; i++) { 524 // Schleife 2 525 // ------- sector 0 ------------ 526 // ;; 0 527 a->brnop0(); // 1 528 a->nop(); // 2 529 //a->cmpdi(CCR0, R4, unroll); 530 a->fpnop0(); // 3 531 a->fpnop1(); // 4 532 a->addi(R4,R4, -1); // 5 533 534 // ;; 1 535 536 a->nop(); // 6 537 a->fmr(F6, F6); // 7 538 a->fmr(F7, F7); // 8 539 // ------- sector 8 --------------- 540 541 // ;; 2 542 a->endgroup(); // 9 543 544 // ;; 3 545 a->nop(); // 10 546 a->nop(); // 11 547 a->fmr(F8, F8); // 12 548 549 // ;; 4 550 a->fmr(F9, F9); // 13 551 a->nop(); // 14 552 a->fmr(F10, F10); // 15 553 554 // ;; 5 555 a->fmr(F11, F11); // 16 556 // -------- sector 16 ------------- 557 558 // ;; 6 559 a->endgroup(); // 17 560 561 // ;; 7 562 a->nop(); // 18 563 a->nop(); // 19 564 a->fmr(F15, F15); // 20 565 566 // ;; 8 567 a->fmr(F16, F16); // 21 568 a->nop(); // 22 569 a->fmr(F17, F17); // 23 570 571 // ;; 9 572 a->fmr(F18, F18); // 24 573 // -------- sector 24 ------------- 574 575 // ;; 10 576 a->endgroup(); // 25 577 578 // ;; 11 579 a->nop(); // 26 580 a->nop(); // 27 581 a->fmr(F19, F19); // 28 582 583 // ;; 12 584 a->fmr(F20, F20); // 29 585 a->nop(); // 30 586 a->fmr(F21, F21); // 31 587 588 // ;; 13 589 a->fmr(F22, F22); // 32 590 } 591 592 // -------- sector 32 ------------- 593 // ;; 14 594 a->cmpdi(CCR0, R4, unroll); // 33 595 a->bge(CCR0, l2); // 34 596 597 a->blr(); 598 uint32_t *code_end = (uint32_t *)a->pc(); 599 a->flush(); 600 601 double loop1_seconds,loop2_seconds, rel_diff; 602 uint64_t start1, stop1; 603 604 start1 = os::current_thread_cpu_time(false); 605 (*test1)(); 606 stop1 = os::current_thread_cpu_time(false); 607 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 608 609 610 start1 = os::current_thread_cpu_time(false); 611 (*test2)(); 612 stop1 = os::current_thread_cpu_time(false); 613 614 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 615 616 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 617 618 if (PrintAssembly) { 619 ttyLocker ttyl; 620 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 621 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 622 tty->print_cr("Time loop1 :%f", loop1_seconds); 623 tty->print_cr("Time loop2 :%f", loop2_seconds); 624 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 625 626 if (rel_diff > 12.0) { 627 tty->print_cr("Section Size 8 Instructions"); 628 } else{ 629 tty->print_cr("Section Size 32 Instructions or Power5"); 630 } 631 } 632 633 #if 0 // TODO: PPC port 634 // Set sector size (if not set explicitly). 635 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 636 if (rel_diff > 12.0) { 637 PdScheduling::power6SectorSize = 0x20; 638 } else { 639 PdScheduling::power6SectorSize = 0x80; 640 } 641 } else if (Power6SectorSize128PPC64) { 642 PdScheduling::power6SectorSize = 0x80; 643 } else { 644 PdScheduling::power6SectorSize = 0x20; 645 } 646 #endif 647 if (UsePower6SchedulerPPC64) Unimplemented(); 648 } 649 #endif // COMPILER2 650 651 void VM_Version::determine_features() { 652 #if defined(ABI_ELFv2) 653 // 1 InstWord per call for the blr instruction. 654 const int code_size = (num_features+1+2*1)*BytesPerInstWord; 655 #else 656 // 7 InstWords for each call (function descriptor + blr instruction). 657 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 658 #endif 659 int features = 0; 660 661 // create test area 662 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 663 char test_area[BUFFER_SIZE]; 664 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 665 666 // Allocate space for the code. 667 ResourceMark rm; 668 CodeBuffer cb("detect_cpu_features", code_size, 0); 669 MacroAssembler* a = new MacroAssembler(&cb); 670 671 // Must be set to true so we can generate the test code. 672 _features = VM_Version::all_features_m; 673 674 // Emit code. 675 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 676 uint32_t *code = (uint32_t *)a->pc(); 677 // Don't use R0 in ldarx. 678 // Keep R3_ARG1 unmodified, it contains &field (see below). 679 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 680 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 681 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 682 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 683 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 684 a->cmpb(R7, R5, R6); // code[4] -> cmpb 685 a->popcntb(R7, R5); // code[5] -> popcntb 686 a->popcntw(R7, R5); // code[6] -> popcntw 687 a->fcfids(F3, F4); // code[7] -> fcfids 688 a->vand(VR0, VR0, VR0); // code[8] -> vand 689 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16 690 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m 691 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher 692 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb 693 a->mfdscr(R0); // code[12] -> mfdscr 694 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx 695 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx 696 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx 697 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig 698 a->blr(); 699 700 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 701 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 702 a->dcbz(R3_ARG1); // R3_ARG1 = addr 703 a->blr(); 704 705 uint32_t *code_end = (uint32_t *)a->pc(); 706 a->flush(); 707 _features = VM_Version::unknown_m; 708 709 // Print the detection code. 710 if (PrintAssembly) { 711 ttyLocker ttyl; 712 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 713 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 714 } 715 716 // Measure cache line size. 717 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 718 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 719 int count = 0; // count zeroed bytes 720 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 721 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 722 _L1_data_cache_line_size = count; 723 724 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 725 VM_Version::_is_determine_features_test_running = true; 726 // We must align the first argument to 16 bytes because of the lqarx check. 727 (*test)(align_up((address)mid_of_test_area, 16), 0); 728 VM_Version::_is_determine_features_test_running = false; 729 730 // determine which instructions are legal. 731 int feature_cntr = 0; 732 if (code[feature_cntr++]) features |= fsqrt_m; 733 if (code[feature_cntr++]) features |= fsqrts_m; 734 if (code[feature_cntr++]) features |= isel_m; 735 if (code[feature_cntr++]) features |= lxarxeh_m; 736 if (code[feature_cntr++]) features |= cmpb_m; 737 if (code[feature_cntr++]) features |= popcntb_m; 738 if (code[feature_cntr++]) features |= popcntw_m; 739 if (code[feature_cntr++]) features |= fcfids_m; 740 if (code[feature_cntr++]) features |= vand_m; 741 if (code[feature_cntr++]) features |= lqarx_m; 742 if (code[feature_cntr++]) features |= vcipher_m; 743 if (code[feature_cntr++]) features |= vpmsumb_m; 744 if (code[feature_cntr++]) features |= mfdscr_m; 745 if (code[feature_cntr++]) features |= vsx_m; 746 if (code[feature_cntr++]) features |= ldbrx_m; 747 if (code[feature_cntr++]) features |= stdbrx_m; 748 if (code[feature_cntr++]) features |= vshasig_m; 749 750 // Print the detection code. 751 if (PrintAssembly) { 752 ttyLocker ttyl; 753 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 754 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 755 } 756 757 _features = features; 758 } 759 760 // Power 8: Configure Data Stream Control Register. 761 void VM_Version::config_dscr() { 762 // 7 InstWords for each call (function descriptor + blr instruction). 763 const int code_size = (2+2*7)*BytesPerInstWord; 764 765 // Allocate space for the code. 766 ResourceMark rm; 767 CodeBuffer cb("config_dscr", code_size, 0); 768 MacroAssembler* a = new MacroAssembler(&cb); 769 770 // Emit code. 771 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 772 uint32_t *code = (uint32_t *)a->pc(); 773 a->mfdscr(R3); 774 a->blr(); 775 776 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 777 a->mtdscr(R3); 778 a->blr(); 779 780 uint32_t *code_end = (uint32_t *)a->pc(); 781 a->flush(); 782 783 // Print the detection code. 784 if (PrintAssembly) { 785 ttyLocker ttyl; 786 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code)); 787 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 788 } 789 790 // Apply the configuration if needed. 791 _dscr_val = (*get_dscr)(); 792 if (Verbose) { 793 tty->print_cr("dscr value was 0x%lx" , _dscr_val); 794 } 795 bool change_requested = false; 796 if (DSCR_PPC64 != (uintx)-1) { 797 _dscr_val = DSCR_PPC64; 798 change_requested = true; 799 } 800 if (DSCR_DPFD_PPC64 <= 7) { 801 uint64_t mask = 0x7; 802 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) { 803 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64); 804 change_requested = true; 805 } 806 } 807 if (DSCR_URG_PPC64 <= 7) { 808 uint64_t mask = 0x7 << 6; 809 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 810 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 811 change_requested = true; 812 } 813 } 814 if (change_requested) { 815 (*set_dscr)(_dscr_val); 816 if (Verbose) { 817 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 818 } 819 } 820 } 821 822 static uint64_t saved_features = 0; 823 824 void VM_Version::allow_all() { 825 saved_features = _features; 826 _features = all_features_m; 827 } 828 829 void VM_Version::revert() { 830 _features = saved_features; 831 }