1 //
2 // Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2012, 2018 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
4614 %}
4615
4616 // Float Immediate: +0.0f.
4617 operand immF_0() %{
4618 predicate(jint_cast(n->getf()) == 0);
4619 match(ConF);
4620
4621 op_cost(0);
4622 format %{ %}
4623 interface(CONST_INTER);
4624 %}
4625
4626 // Double Immediate
4627 operand immD() %{
4628 match(ConD);
4629 op_cost(40);
4630 format %{ %}
4631 interface(CONST_INTER);
4632 %}
4633
4634 // Integer Register Operands
4635 // Integer Destination Register
4636 // See definition of reg_class bits32_reg_rw.
4637 operand iRegIdst() %{
4638 constraint(ALLOC_IN_RC(bits32_reg_rw));
4639 match(RegI);
4640 match(rscratch1RegI);
4641 match(rscratch2RegI);
4642 match(rarg1RegI);
4643 match(rarg2RegI);
4644 match(rarg3RegI);
4645 match(rarg4RegI);
4646 format %{ %}
4647 interface(REG_INTER);
4648 %}
4649
4650 // Integer Source Register
4651 // See definition of reg_class bits32_reg_ro.
4652 operand iRegIsrc() %{
4653 constraint(ALLOC_IN_RC(bits32_reg_ro));
13992 size(4);
13993 ins_encode %{
13994 __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13995 %}
13996 ins_pipe(pipe_class_default);
13997 %}
13998
13999 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14000 match(Set dst (ReplicateS src));
14001 predicate(n->as_Vector()->length() == 4);
14002 expand %{
14003 moveReg(dst, src);
14004 repl48(dst);
14005 repl32(dst);
14006 %}
14007 %}
14008
14009 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
14010 match(Set dst (ReplicateS zero));
14011 predicate(n->as_Vector()->length() == 4);
14012 format %{ "LI $dst, #0 \t// replicate4C" %}
14013 size(4);
14014 ins_encode %{
14015 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14016 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14017 %}
14018 ins_pipe(pipe_class_default);
14019 %}
14020
14021 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
14022 match(Set dst (ReplicateS src));
14023 predicate(n->as_Vector()->length() == 4);
14024 format %{ "LI $dst, -1 \t// replicate4C" %}
14025 size(4);
14026 ins_encode %{
14027 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14028 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14029 %}
14030 ins_pipe(pipe_class_default);
14031 %}
14032
14033 instruct repl8S_reg_Ex(vecX dst, iRegIsrc src) %{
14034 match(Set dst (ReplicateS src));
14035 predicate(n->as_Vector()->length() == 8);
14036
14037 expand %{
14038 iRegLdst tmpL;
14039 vecX tmpV;
14040 immI8 zero %{ (int) 0 %}
14041 moveReg(tmpL, src);
14042 repl48(tmpL);
14043 repl32(tmpL);
14044 mtvsrd(tmpV, tmpL);
14045 xxpermdi(dst, tmpV, tmpV, zero);
14046 %}
14047 %}
14048
14049 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
14050 match(Set dst (ReplicateS zero));
14051 predicate(n->as_Vector()->length() == 8);
14052
14053 format %{ "XXLXOR $dst, $zero \t// replicate8S" %}
14054 size(4);
14055 ins_encode %{
14056 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14057 %}
14058 ins_pipe(pipe_class_default);
14059 %}
14060
14061 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
14062 match(Set dst (ReplicateS src));
14063 predicate(n->as_Vector()->length() == 8);
14064
14065 format %{ "XXLEQV $dst, $src \t// replicate16B" %}
14066 size(4);
14067 ins_encode %{
14068 __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14069 %}
14070 ins_pipe(pipe_class_default);
14071 %}
14072
14073 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14074 match(Set dst (ReplicateI src));
14075 predicate(n->as_Vector()->length() == 2);
14076 ins_cost(2 * DEFAULT_COST);
14077 expand %{
14078 moveReg(dst, src);
14079 repl32(dst);
14080 %}
14081 %}
14082
14083 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
14084 match(Set dst (ReplicateI zero));
14085 predicate(n->as_Vector()->length() == 2);
14086 format %{ "LI $dst, #0 \t// replicate4C" %}
14087 size(4);
14088 ins_encode %{
14089 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14090 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14091 %}
14092 ins_pipe(pipe_class_default);
14093 %}
14094
14095 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
14096 match(Set dst (ReplicateI src));
14097 predicate(n->as_Vector()->length() == 2);
14098 format %{ "LI $dst, -1 \t// replicate4C" %}
14099 size(4);
14100 ins_encode %{
14101 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14102 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14103 %}
14104 ins_pipe(pipe_class_default);
14105 %}
14106
14107 instruct repl4I_reg_Ex(vecX dst, iRegIsrc src) %{
14108 match(Set dst (ReplicateI src));
14109 predicate(n->as_Vector()->length() == 4);
14110 ins_cost(2 * DEFAULT_COST);
14111
14112 expand %{
14113 iRegLdst tmpL;
14114 vecX tmpV;
14115 immI8 zero %{ (int) 0 %}
14116 moveReg(tmpL, src);
14117 repl32(tmpL);
14118 mtvsrd(tmpV, tmpL);
14652
14653 format %{ "XXLXOR $dst, $zero \t// replicate4F" %}
14654 ins_encode %{
14655 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14656 %}
14657 ins_pipe(pipe_class_default);
14658 %}
14659
14660 instruct repl2D_reg_Ex(vecX dst, regD src) %{
14661 match(Set dst (ReplicateD src));
14662 predicate(n->as_Vector()->length() == 2);
14663
14664 format %{ "XXPERMDI $dst, $src, $src, 0 \t// Splat doubleword" %}
14665 size(4);
14666 ins_encode %{
14667 __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0);
14668 %}
14669 ins_pipe(pipe_class_default);
14670 %}
14671
14672 instruct repl2D_immI0(vecX dst, immI_0 zero) %{
14673 match(Set dst (ReplicateD zero));
14674 predicate(n->as_Vector()->length() == 2);
14675
14676 format %{ "XXLXOR $dst, $zero \t// replicate2D" %}
14677 size(4);
14678 ins_encode %{
14679 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14680 %}
14681 ins_pipe(pipe_class_default);
14682 %}
14683
14684 instruct repl2D_immIminus1(vecX dst, immI_minus1 src) %{
14685 match(Set dst (ReplicateD src));
14686 predicate(n->as_Vector()->length() == 2);
14687
14688 format %{ "XXLEQV $dst, $src \t// replicate16B" %}
14689 size(4);
14690 ins_encode %{
14691 __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14692 %}
14693 ins_pipe(pipe_class_default);
14694 %}
14695
14696 instruct mtvsrd(vecX dst, iRegLsrc src) %{
14697 predicate(false);
14698 effect(DEF dst, USE src);
14699
14700 format %{ "MTVSRD $dst, $src \t// Move to 16-byte register" %}
14701 size(4);
14702 ins_encode %{
14703 __ mtvsrd($dst$$VectorSRegister, $src$$Register);
14704 %}
14705 ins_pipe(pipe_class_default);
14706 %}
14707
14708 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{
14709 effect(DEF dst, USE src, USE zero);
14710
14711 format %{ "XXSPLATD $dst, $src, $zero \t// Splat doubleword" %}
14712 size(4);
14713 ins_encode %{
14714 __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant);
14715 %}
14737 xxpermdi(dst, tmpV, tmpV, zero);
14738 %}
14739 %}
14740
14741 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
14742 match(Set dst (ReplicateL zero));
14743 predicate(n->as_Vector()->length() == 2);
14744
14745 format %{ "XXLXOR $dst, $zero \t// replicate2L" %}
14746 size(4);
14747 ins_encode %{
14748 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14749 %}
14750 ins_pipe(pipe_class_default);
14751 %}
14752
14753 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
14754 match(Set dst (ReplicateL src));
14755 predicate(n->as_Vector()->length() == 2);
14756
14757 format %{ "XXLEQV $dst, $src \t// replicate16B" %}
14758 size(4);
14759 ins_encode %{
14760 __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14761 %}
14762 ins_pipe(pipe_class_default);
14763 %}
14764
14765 // ============================================================================
14766 // Safepoint Instruction
14767
14768 instruct safePoint_poll(iRegPdst poll) %{
14769 match(SafePoint poll);
14770
14771 // It caused problems to add the effect that r0 is killed, but this
14772 // effect no longer needs to be mentioned, since r0 is not contained
14773 // in a reg_class.
14774
14775 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
14776 size(4);
14777 ins_encode( enc_poll(0x0, poll) );
|
1 //
2 // Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2012, 2019 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
4614 %}
4615
4616 // Float Immediate: +0.0f.
4617 operand immF_0() %{
4618 predicate(jint_cast(n->getf()) == 0);
4619 match(ConF);
4620
4621 op_cost(0);
4622 format %{ %}
4623 interface(CONST_INTER);
4624 %}
4625
4626 // Double Immediate
4627 operand immD() %{
4628 match(ConD);
4629 op_cost(40);
4630 format %{ %}
4631 interface(CONST_INTER);
4632 %}
4633
4634 // Double Immediate: +0.0d.
4635 operand immD_0() %{
4636 predicate(jint_cast(n->getd()) == 0);
4637 match(ConD);
4638
4639 op_cost(0);
4640 format %{ %}
4641 interface(CONST_INTER);
4642 %}
4643
4644 // Integer Register Operands
4645 // Integer Destination Register
4646 // See definition of reg_class bits32_reg_rw.
4647 operand iRegIdst() %{
4648 constraint(ALLOC_IN_RC(bits32_reg_rw));
4649 match(RegI);
4650 match(rscratch1RegI);
4651 match(rscratch2RegI);
4652 match(rarg1RegI);
4653 match(rarg2RegI);
4654 match(rarg3RegI);
4655 match(rarg4RegI);
4656 format %{ %}
4657 interface(REG_INTER);
4658 %}
4659
4660 // Integer Source Register
4661 // See definition of reg_class bits32_reg_ro.
4662 operand iRegIsrc() %{
4663 constraint(ALLOC_IN_RC(bits32_reg_ro));
14002 size(4);
14003 ins_encode %{
14004 __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14005 %}
14006 ins_pipe(pipe_class_default);
14007 %}
14008
14009 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14010 match(Set dst (ReplicateS src));
14011 predicate(n->as_Vector()->length() == 4);
14012 expand %{
14013 moveReg(dst, src);
14014 repl48(dst);
14015 repl32(dst);
14016 %}
14017 %}
14018
14019 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
14020 match(Set dst (ReplicateS zero));
14021 predicate(n->as_Vector()->length() == 4);
14022 format %{ "LI $dst, #0 \t// replicate4S" %}
14023 size(4);
14024 ins_encode %{
14025 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14026 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14027 %}
14028 ins_pipe(pipe_class_default);
14029 %}
14030
14031 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
14032 match(Set dst (ReplicateS src));
14033 predicate(n->as_Vector()->length() == 4);
14034 format %{ "LI $dst, -1 \t// replicate4S" %}
14035 size(4);
14036 ins_encode %{
14037 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14038 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14039 %}
14040 ins_pipe(pipe_class_default);
14041 %}
14042
14043 instruct repl8S_reg_Ex(vecX dst, iRegIsrc src) %{
14044 match(Set dst (ReplicateS src));
14045 predicate(n->as_Vector()->length() == 8);
14046
14047 expand %{
14048 iRegLdst tmpL;
14049 vecX tmpV;
14050 immI8 zero %{ (int) 0 %}
14051 moveReg(tmpL, src);
14052 repl48(tmpL);
14053 repl32(tmpL);
14054 mtvsrd(tmpV, tmpL);
14055 xxpermdi(dst, tmpV, tmpV, zero);
14056 %}
14057 %}
14058
14059 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
14060 match(Set dst (ReplicateS zero));
14061 predicate(n->as_Vector()->length() == 8);
14062
14063 format %{ "XXLXOR $dst, $zero \t// replicate8S" %}
14064 size(4);
14065 ins_encode %{
14066 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14067 %}
14068 ins_pipe(pipe_class_default);
14069 %}
14070
14071 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
14072 match(Set dst (ReplicateS src));
14073 predicate(n->as_Vector()->length() == 8);
14074
14075 format %{ "XXLEQV $dst, $src \t// replicate8S" %}
14076 size(4);
14077 ins_encode %{
14078 __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14079 %}
14080 ins_pipe(pipe_class_default);
14081 %}
14082
14083 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14084 match(Set dst (ReplicateI src));
14085 predicate(n->as_Vector()->length() == 2);
14086 ins_cost(2 * DEFAULT_COST);
14087 expand %{
14088 moveReg(dst, src);
14089 repl32(dst);
14090 %}
14091 %}
14092
14093 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
14094 match(Set dst (ReplicateI zero));
14095 predicate(n->as_Vector()->length() == 2);
14096 format %{ "LI $dst, #0 \t// replicate2I" %}
14097 size(4);
14098 ins_encode %{
14099 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14100 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14101 %}
14102 ins_pipe(pipe_class_default);
14103 %}
14104
14105 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
14106 match(Set dst (ReplicateI src));
14107 predicate(n->as_Vector()->length() == 2);
14108 format %{ "LI $dst, -1 \t// replicate2I" %}
14109 size(4);
14110 ins_encode %{
14111 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14112 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14113 %}
14114 ins_pipe(pipe_class_default);
14115 %}
14116
14117 instruct repl4I_reg_Ex(vecX dst, iRegIsrc src) %{
14118 match(Set dst (ReplicateI src));
14119 predicate(n->as_Vector()->length() == 4);
14120 ins_cost(2 * DEFAULT_COST);
14121
14122 expand %{
14123 iRegLdst tmpL;
14124 vecX tmpV;
14125 immI8 zero %{ (int) 0 %}
14126 moveReg(tmpL, src);
14127 repl32(tmpL);
14128 mtvsrd(tmpV, tmpL);
14662
14663 format %{ "XXLXOR $dst, $zero \t// replicate4F" %}
14664 ins_encode %{
14665 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14666 %}
14667 ins_pipe(pipe_class_default);
14668 %}
14669
14670 instruct repl2D_reg_Ex(vecX dst, regD src) %{
14671 match(Set dst (ReplicateD src));
14672 predicate(n->as_Vector()->length() == 2);
14673
14674 format %{ "XXPERMDI $dst, $src, $src, 0 \t// Splat doubleword" %}
14675 size(4);
14676 ins_encode %{
14677 __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0);
14678 %}
14679 ins_pipe(pipe_class_default);
14680 %}
14681
14682 instruct repl2D_immD0(vecX dst, immD_0 zero) %{
14683 match(Set dst (ReplicateD zero));
14684 predicate(n->as_Vector()->length() == 2);
14685
14686 format %{ "XXLXOR $dst, $zero \t// replicate2D" %}
14687 size(4);
14688 ins_encode %{
14689 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14690 %}
14691 ins_pipe(pipe_class_default);
14692 %}
14693
14694 instruct mtvsrd(vecX dst, iRegLsrc src) %{
14695 predicate(false);
14696 effect(DEF dst, USE src);
14697
14698 format %{ "MTVSRD $dst, $src \t// Move to 16-byte register" %}
14699 size(4);
14700 ins_encode %{
14701 __ mtvsrd($dst$$VectorSRegister, $src$$Register);
14702 %}
14703 ins_pipe(pipe_class_default);
14704 %}
14705
14706 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{
14707 effect(DEF dst, USE src, USE zero);
14708
14709 format %{ "XXSPLATD $dst, $src, $zero \t// Splat doubleword" %}
14710 size(4);
14711 ins_encode %{
14712 __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant);
14713 %}
14735 xxpermdi(dst, tmpV, tmpV, zero);
14736 %}
14737 %}
14738
14739 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
14740 match(Set dst (ReplicateL zero));
14741 predicate(n->as_Vector()->length() == 2);
14742
14743 format %{ "XXLXOR $dst, $zero \t// replicate2L" %}
14744 size(4);
14745 ins_encode %{
14746 __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14747 %}
14748 ins_pipe(pipe_class_default);
14749 %}
14750
14751 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
14752 match(Set dst (ReplicateL src));
14753 predicate(n->as_Vector()->length() == 2);
14754
14755 format %{ "XXLEQV $dst, $src \t// replicate2L" %}
14756 size(4);
14757 ins_encode %{
14758 __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14759 %}
14760 ins_pipe(pipe_class_default);
14761 %}
14762
14763 // ============================================================================
14764 // Safepoint Instruction
14765
14766 instruct safePoint_poll(iRegPdst poll) %{
14767 match(SafePoint poll);
14768
14769 // It caused problems to add the effect that r0 is killed, but this
14770 // effect no longer needs to be mentioned, since r0 is not contained
14771 // in a reg_class.
14772
14773 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
14774 size(4);
14775 ins_encode( enc_poll(0x0, poll) );
|