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src/cpu/ppc/vm/assembler_ppc.hpp
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rev 8845 : Apply 8154156 for VSX support, with cherry picking from 8077838, 8080684, and 8149655
rev 8846 : Fix order of some lines of modified code in 8154156
@@ -1,8 +1,8 @@
/*
- * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012, 2018 SAP AG. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
@@ -467,10 +467,12 @@
STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
// Vector-Scalar (VSX) instruction support.
+ LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
+ STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
// Vector Permute and Formatting
VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
@@ -668,12 +670,14 @@
TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
// Atomics.
LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
+ LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
- STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
+ STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
+ STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
};
// Trap instructions TO bits
enum trap_to_bits {
@@ -1050,10 +1054,23 @@
static int vrb( VectorRegister r) { return vrb(r->encoding());}
static int vrc( VectorRegister r) { return vrc(r->encoding());}
static int vrs( VectorRegister r) { return vrs(r->encoding());}
static int vrt( VectorRegister r) { return vrt(r->encoding());}
+ // Support Vector-Scalar (VSX) instructions.
+ static int vsra( int x) { return opp_u_field(x, 15, 11); }
+ static int vsrb( int x) { return opp_u_field(x, 20, 16); }
+ static int vsrc( int x) { return opp_u_field(x, 25, 21); }
+ static int vsrs( int x) { return opp_u_field(x, 10, 6); }
+ static int vsrt( int x) { return opp_u_field(x, 10, 6); }
+
+ static int vsra( VectorSRegister r) { return vsra(r->encoding());}
+ static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
+ static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
+ static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
+ static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
+
static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
@@ -1661,15 +1678,18 @@
inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
// atomics
inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
+ inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
inline bool lxarx_hint_exclusive_access();
inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
+ inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
inline void stwcx_( Register s, Register a, Register b);
inline void stdcx_( Register s, Register a, Register b);
+ inline void stqcx_( Register s, Register a, Register b);
// Instructions for adjusting thread priority for simultaneous
// multithreading (SMT) on Power5.
private:
inline void smt_prio_very_low();
@@ -1941,10 +1961,12 @@
// Vector Floating-Point not implemented yet
inline void mtvscr( VectorRegister b);
inline void mfvscr( VectorRegister d);
// Vector-Scalar (VSX) instructions.
+ inline void lxvd2x( VectorSRegister d, Register a, Register b);
+ inline void stxvd2x( VectorSRegister d, Register a, Register b);
inline void mtvrd( VectorRegister d, Register a);
inline void mfvrd( Register a, VectorRegister d);
// AES (introduced with Power 8)
inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
@@ -2020,14 +2042,17 @@
inline void dcbtstct(Register s2, int ct);
// Atomics: use ra0mem to disallow R0 as base.
inline void lwarx_unchecked(Register d, Register b, int eh1);
inline void ldarx_unchecked(Register d, Register b, int eh1);
+ inline void lqarx_unchecked(Register d, Register b, int eh1);
inline void lwarx( Register d, Register b, bool hint_exclusive_access);
inline void ldarx( Register d, Register b, bool hint_exclusive_access);
+ inline void lqarx( Register d, Register b, bool hint_exclusive_access);
inline void stwcx_(Register s, Register b);
inline void stdcx_(Register s, Register b);
+ inline void stqcx_(Register s, Register b);
inline void lfs( FloatRegister d, int si16);
inline void lfsx( FloatRegister d, Register b);
inline void lfd( FloatRegister d, int si16);
inline void lfdx( FloatRegister d, Register b);
inline void stfs( FloatRegister s, int si16);
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