1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2012, 2014 SAP AG. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "runtime/java.hpp" 32 #include "runtime/stubCodeGenerator.hpp" 33 #include "utilities/defaultStream.hpp" 34 #include "vm_version_ppc.hpp" 35 #ifdef TARGET_OS_FAMILY_aix 36 # include "os_aix.inline.hpp" 37 #endif 38 #ifdef TARGET_OS_FAMILY_linux 39 # include "os_linux.inline.hpp" 40 #endif 41 42 # include <sys/sysinfo.h> 43 44 int VM_Version::_features = VM_Version::unknown_m; 45 int VM_Version::_measured_cache_line_size = 128; // default value 46 const char* VM_Version::_features_str = ""; 47 bool VM_Version::_is_determine_features_test_running = false; 48 49 50 #define MSG(flag) \ 51 if (flag && !FLAG_IS_DEFAULT(flag)) \ 52 jio_fprintf(defaultStream::error_stream(), \ 53 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 54 " -XX:+" #flag " will be disabled!\n"); 55 56 void VM_Version::initialize() { 57 58 // Test which instructions are supported and measure cache line size. 59 determine_features(); 60 61 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 62 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 63 if (VM_Version::has_popcntw()) { 64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 65 } else if (VM_Version::has_cmpb()) { 66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 67 } else if (VM_Version::has_popcntb()) { 68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 69 } else { 70 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 71 } 72 } 73 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 || 74 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7, 75 "PowerArchitecturePPC64 should be 0, 5, 6 or 7"); 76 77 if (!UseSIGTRAP) { 78 MSG(TrapBasedICMissChecks); 79 MSG(TrapBasedNotEntrantChecks); 80 MSG(TrapBasedNullChecks); 81 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 82 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 83 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 84 } 85 86 #ifdef COMPILER2 87 if (!UseSIGTRAP) { 88 MSG(TrapBasedRangeChecks); 89 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 90 } 91 92 // On Power6 test for section size. 93 if (PowerArchitecturePPC64 == 6) { 94 determine_section_size(); 95 // TODO: PPC port } else { 96 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 97 } 98 99 MaxVectorSize = 8; 100 #endif 101 102 // Create and print feature-string. 103 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 104 jio_snprintf(buf, sizeof(buf), 105 "ppc64%s%s%s%s%s%s%s%s%s%s", 106 (has_fsqrt() ? " fsqrt" : ""), 107 (has_isel() ? " isel" : ""), 108 (has_lxarxeh() ? " lxarxeh" : ""), 109 (has_cmpb() ? " cmpb" : ""), 110 //(has_mftgpr()? " mftgpr" : ""), 111 (has_popcntb() ? " popcntb" : ""), 112 (has_popcntw() ? " popcntw" : ""), 113 (has_fcfids() ? " fcfids" : ""), 114 (has_vand() ? " vand" : ""), 115 (has_vcipher() ? " aes" : ""), 116 (has_vpmsumb() ? " vpmsumb" : "") 117 // Make sure number of %s matches num_features! 118 ); 119 _features_str = strdup(buf); 120 NOT_PRODUCT(if (Verbose) print_features();); 121 122 // PPC64 supports 8-byte compare-exchange operations (see 123 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 124 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 125 _supports_cx8 = true; 126 127 UseSSE = 0; // Only on x86 and x64 128 129 intx cache_line_size = _measured_cache_line_size; 130 131 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 132 133 if (AllocatePrefetchStyle == 4) { 134 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 135 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 136 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 137 } else { 138 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 139 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 140 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 468 469 // Must be set to true so we can generate the test code. 470 _features = VM_Version::all_features_m; 471 472 // Emit code. 473 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 474 uint32_t *code = (uint32_t *)a->pc(); 475 // Don't use R0 in ldarx. 476 // Keep R3_ARG1 unmodified, it contains &field (see below). 477 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 478 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 479 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 480 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 481 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 482 a->cmpb(R7, R5, R6); // code[4] -> bcmp 483 //a->mftgpr(R7, F3); // code[5] -> mftgpr 484 a->popcntb(R7, R5); // code[6] -> popcntb 485 a->popcntw(R7, R5); // code[7] -> popcntw 486 a->fcfids(F3, F4); // code[8] -> fcfids 487 a->vand(VR0, VR0, VR0); // code[9] -> vand 488 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher 489 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb 490 a->blr(); 491 492 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 493 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 494 a->dcbz(R3_ARG1); // R3_ARG1 = addr 495 a->blr(); 496 497 uint32_t *code_end = (uint32_t *)a->pc(); 498 a->flush(); 499 _features = VM_Version::unknown_m; 500 501 // Print the detection code. 502 if (PrintAssembly) { 503 ttyLocker ttyl; 504 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 505 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 506 } 507 508 // Measure cache line size. 509 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 513 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 514 _measured_cache_line_size = count; 515 516 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 517 VM_Version::_is_determine_features_test_running = true; 518 (*test)((address)mid_of_test_area, (uint64_t)0); 519 VM_Version::_is_determine_features_test_running = false; 520 521 // determine which instructions are legal. 522 int feature_cntr = 0; 523 if (code[feature_cntr++]) features |= fsqrt_m; 524 if (code[feature_cntr++]) features |= fsqrts_m; 525 if (code[feature_cntr++]) features |= isel_m; 526 if (code[feature_cntr++]) features |= lxarxeh_m; 527 if (code[feature_cntr++]) features |= cmpb_m; 528 //if(code[feature_cntr++])features |= mftgpr_m; 529 if (code[feature_cntr++]) features |= popcntb_m; 530 if (code[feature_cntr++]) features |= popcntw_m; 531 if (code[feature_cntr++]) features |= fcfids_m; 532 if (code[feature_cntr++]) features |= vand_m; 533 if (code[feature_cntr++]) features |= vcipher_m; 534 if (code[feature_cntr++]) features |= vpmsumb_m; 535 536 // Print the detection code. 537 if (PrintAssembly) { 538 ttyLocker ttyl; 539 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 540 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 541 } 542 543 _features = features; 544 } 545 546 547 static int saved_features = 0; 548 549 void VM_Version::allow_all() { 550 saved_features = _features; 551 _features = all_features_m; 552 } 553 554 void VM_Version::revert() { 555 _features = saved_features; 556 } | 1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2012, 2018 SAP AG. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "runtime/java.hpp" 32 #include "runtime/stubCodeGenerator.hpp" 33 #include "utilities/defaultStream.hpp" 34 #include "vm_version_ppc.hpp" 35 #ifdef TARGET_OS_FAMILY_aix 36 # include "os_aix.inline.hpp" 37 #endif 38 #ifdef TARGET_OS_FAMILY_linux 39 # include "os_linux.inline.hpp" 40 #endif 41 42 # include <sys/sysinfo.h> 43 44 int VM_Version::_features = VM_Version::unknown_m; 45 int VM_Version::_measured_cache_line_size = 128; // default value 46 const char* VM_Version::_features_str = ""; 47 bool VM_Version::_is_determine_features_test_running = false; 48 uint64_t VM_Version::_dscr_val = 0; 49 50 #define MSG(flag) \ 51 if (flag && !FLAG_IS_DEFAULT(flag)) \ 52 jio_fprintf(defaultStream::error_stream(), \ 53 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 54 " -XX:+" #flag " will be disabled!\n"); 55 56 void VM_Version::initialize() { 57 58 // Test which instructions are supported and measure cache line size. 59 determine_features(); 60 61 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 62 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 63 if (VM_Version::has_lqarx()) { 64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 65 } else if (VM_Version::has_popcntw()) { 66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 67 } else if (VM_Version::has_cmpb()) { 68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 69 } else if (VM_Version::has_popcntb()) { 70 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 71 } else { 72 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 73 } 74 } 75 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 || 76 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 || 77 PowerArchitecturePPC64 == 8, 78 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8"); 79 80 // Power 8: Configure Data Stream Control Register. 81 if (PowerArchitecturePPC64 >= 8) { 82 config_dscr(); 83 } 84 85 if (!UseSIGTRAP) { 86 MSG(TrapBasedICMissChecks); 87 MSG(TrapBasedNotEntrantChecks); 88 MSG(TrapBasedNullChecks); 89 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 90 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 91 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 92 } 93 94 #ifdef COMPILER2 95 if (!UseSIGTRAP) { 96 MSG(TrapBasedRangeChecks); 97 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 98 } 99 100 // On Power6 test for section size. 101 if (PowerArchitecturePPC64 == 6) { 102 determine_section_size(); 103 // TODO: PPC port } else { 104 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 105 } 106 107 MaxVectorSize = 8; 108 #endif 109 110 // Create and print feature-string. 111 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 112 jio_snprintf(buf, sizeof(buf), 113 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s", 114 (has_fsqrt() ? " fsqrt" : ""), 115 (has_isel() ? " isel" : ""), 116 (has_lxarxeh() ? " lxarxeh" : ""), 117 (has_cmpb() ? " cmpb" : ""), 118 //(has_mftgpr()? " mftgpr" : ""), 119 (has_popcntb() ? " popcntb" : ""), 120 (has_popcntw() ? " popcntw" : ""), 121 (has_fcfids() ? " fcfids" : ""), 122 (has_vand() ? " vand" : ""), 123 (has_lqarx() ? " lqarx" : ""), 124 (has_vcipher() ? " aes" : ""), 125 (has_vpmsumb() ? " vpmsumb" : ""), 126 (has_mfdscr() ? " mfdscr" : ""), 127 (has_vsx() ? " vsx" : "") 128 // Make sure number of %s matches num_features! 129 ); 130 _features_str = strdup(buf); 131 if (Verbose) { 132 print_features(); 133 } 134 135 // PPC64 supports 8-byte compare-exchange operations (see 136 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 137 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 138 _supports_cx8 = true; 139 140 UseSSE = 0; // Only on x86 and x64 141 142 intx cache_line_size = _measured_cache_line_size; 143 144 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 145 146 if (AllocatePrefetchStyle == 4) { 147 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 148 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 149 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 150 } else { 151 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 152 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 153 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 481 482 // Must be set to true so we can generate the test code. 483 _features = VM_Version::all_features_m; 484 485 // Emit code. 486 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 487 uint32_t *code = (uint32_t *)a->pc(); 488 // Don't use R0 in ldarx. 489 // Keep R3_ARG1 unmodified, it contains &field (see below). 490 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 491 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 492 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 493 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 494 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 495 a->cmpb(R7, R5, R6); // code[4] -> bcmp 496 //a->mftgpr(R7, F3); // code[5] -> mftgpr 497 a->popcntb(R7, R5); // code[6] -> popcntb 498 a->popcntw(R7, R5); // code[7] -> popcntw 499 a->fcfids(F3, F4); // code[8] -> fcfids 500 a->vand(VR0, VR0, VR0); // code[9] -> vand 501 a->lqarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[10] -> lqarx_m 502 a->vcipher(VR0, VR1, VR2); // code[11] -> vcipher 503 a->vpmsumb(VR0, VR1, VR2); // code[12] -> vpmsumb 504 a->mfdscr(R0); // code[13] -> mfdscr 505 a->lxvd2x(VSR0, 0, R3_ARG1); // code[14] -> vsx 506 a->blr(); 507 508 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 509 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 510 a->dcbz(R3_ARG1); // R3_ARG1 = addr 511 a->blr(); 512 513 uint32_t *code_end = (uint32_t *)a->pc(); 514 a->flush(); 515 _features = VM_Version::unknown_m; 516 517 // Print the detection code. 518 if (PrintAssembly) { 519 ttyLocker ttyl; 520 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 521 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 522 } 523 524 // Measure cache line size. 525 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 529 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 530 _measured_cache_line_size = count; 531 532 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 533 VM_Version::_is_determine_features_test_running = true; 534 (*test)((address)mid_of_test_area, (uint64_t)0); 535 VM_Version::_is_determine_features_test_running = false; 536 537 // determine which instructions are legal. 538 int feature_cntr = 0; 539 if (code[feature_cntr++]) features |= fsqrt_m; 540 if (code[feature_cntr++]) features |= fsqrts_m; 541 if (code[feature_cntr++]) features |= isel_m; 542 if (code[feature_cntr++]) features |= lxarxeh_m; 543 if (code[feature_cntr++]) features |= cmpb_m; 544 //if(code[feature_cntr++])features |= mftgpr_m; 545 if (code[feature_cntr++]) features |= popcntb_m; 546 if (code[feature_cntr++]) features |= popcntw_m; 547 if (code[feature_cntr++]) features |= fcfids_m; 548 if (code[feature_cntr++]) features |= vand_m; 549 if (code[feature_cntr++]) features |= lqarx_m; 550 if (code[feature_cntr++]) features |= vcipher_m; 551 if (code[feature_cntr++]) features |= vpmsumb_m; 552 if (code[feature_cntr++]) features |= mfdscr_m; 553 if (code[feature_cntr++]) features |= vsx_m; 554 555 // Print the detection code. 556 if (PrintAssembly) { 557 ttyLocker ttyl; 558 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 559 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 560 } 561 562 _features = features; 563 } 564 565 // Power 8: Configure Data Stream Control Register. 566 void VM_Version::config_dscr() { 567 assert(has_lqarx(), "Only execute on Power 8 or later!"); 568 569 // 7 InstWords for each call (function descriptor + blr instruction). 570 const int code_size = (2+2*7)*BytesPerInstWord; 571 572 // Allocate space for the code. 573 ResourceMark rm; 574 CodeBuffer cb("config_dscr", code_size, 0); 575 MacroAssembler* a = new MacroAssembler(&cb); 576 577 // Emit code. 578 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 579 uint32_t *code = (uint32_t *)a->pc(); 580 a->mfdscr(R3); 581 a->blr(); 582 583 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 584 a->mtdscr(R3); 585 a->blr(); 586 587 uint32_t *code_end = (uint32_t *)a->pc(); 588 a->flush(); 589 590 // Print the detection code. 591 if (PrintAssembly) { 592 ttyLocker ttyl; 593 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", code); 594 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 595 } 596 597 // Apply the configuration if needed. 598 _dscr_val = (*get_dscr)(); 599 if (Verbose) { 600 tty->print_cr("dscr value was 0x%lx" , _dscr_val); 601 } 602 bool change_requested = false; 603 if (DSCR_PPC64 != (uintx)-1) { 604 _dscr_val = DSCR_PPC64; 605 change_requested = true; 606 } 607 if (DSCR_DPFD_PPC64 <= 7) { 608 uint64_t mask = 0x7; 609 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) { 610 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64); 611 change_requested = true; 612 } 613 } 614 if (DSCR_URG_PPC64 <= 7) { 615 uint64_t mask = 0x7 << 6; 616 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 617 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 618 change_requested = true; 619 } 620 } 621 if (change_requested) { 622 (*set_dscr)(_dscr_val); 623 if (Verbose) { 624 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 625 } 626 } 627 } 628 629 static int saved_features = 0; 630 631 void VM_Version::allow_all() { 632 saved_features = _features; 633 _features = all_features_m; 634 } 635 636 void VM_Version::revert() { 637 _features = saved_features; 638 } |